Commit Graph

8478 Commits

Author SHA1 Message Date
Martin Whitaker 36eef5154f Implement supply->strong strength reduction for non-resistive switches.
As specified in 1364-2005 section 7.11.
2018-02-23 22:07:59 +00:00
Martin Whitaker 69d80839a5 Improved check for missing task/function port direction. 2018-02-21 20:07:13 +00:00
Martin Whitaker 6b1b402a79 Fix for br1027: incorrect inference of task/function port direction.
In traditional Verilog, each task_port_item must have an explicit port
direction.

In SystemVerilog, if the port direction is not specified, it should be
inherited from the preceding task_port_item for that task/function, and
only the first task_port_item should infer the direction to be 'input'.
2018-02-20 20:59:26 +00:00
Martin Whitaker f8a2a4816c Enable parameter/localparameter definitions in the compilation unit scope. 2018-02-18 19:21:18 +00:00
Martin Whitaker 2a21fe77ac Output an error message when a SV variable declaration reuses a name.
Assertion failures are not the right way to handle user code errors.
2018-02-18 17:51:56 +00:00
Martin Whitaker caf83b02c1 Enable variable declarations/initialisations in the compilation unit scope. 2018-02-18 14:09:03 +00:00
Martin Whitaker 0f95770418 Include compilation units in pform dump. 2018-02-18 12:53:29 +00:00
Cary R e7a9662b3d A #0 is not allowed in a final block 2018-01-01 21:35:26 -08:00
Cary R 24a4ec3bb2 Hide the always_comb/latch TO event by not attaching it to a scope. 2018-01-01 21:19:58 -08:00
Cary R ca01385797 The synth check needs to check the task scope 2017-12-28 08:50:32 -08:00
Cary R 932241ee87 Check system/user tasks for always_comb/ff/latch synth. 2017-12-27 23:08:32 -08:00
Cary R 7d11fa662e Fix space issues 2017-12-27 14:51:56 -08:00
Cary R 2bbd077dc9 Add some synthesis checks for the always_comb/ff/latch blocks 2017-12-27 14:51:17 -08:00
Stephen Williams 0caa109174
Merge pull request #181 from phire/portinfo_grammar
vvp grammar: .port_info statements should require/generate semicolons.
2017-12-18 10:04:42 -08:00
Scott Mansell d01e5accc0 vpp: Require semicolon after .port_info statements
Optional until 12.0
2017-12-17 00:06:09 +13:00
Scott Mansell 7b84b29bbc tgt-vvp: Output semicolon after .port_info statements
Backwards compatablity is perserved due to the parser interperting the
unexpected semicolon as an empty statement.
2017-12-16 23:59:48 +13:00
Cary R 9a8212a54f Update tp the latest files from GTKWave 2017-12-13 21:56:59 -08:00
Cary R f17992bcd0 Report the lines that have delay or event control in an always_comb/ff/latch process 2017-12-06 00:22:43 -08:00
Cary R cb0ffd734e Check to see that always_comb/ff/latch do not have delays/events 2017-12-05 22:10:43 -08:00
Cary R 39c14edb76 The delay for a join_any and join_none is different than join 2017-12-05 21:49:52 -08:00
Cary R c38ca2114b Note the always_comb/ff/latch have not been looked at for synthesis 2017-12-03 20:17:42 -08:00
Cary R db1ea05452 Fix #0 to trigger in the inactive region and add a trigger for always_comb/latch 2017-12-03 20:17:42 -08:00
Cary R a5b945f8f5 Initialize the t0 trigger value to false. 2017-12-03 20:17:42 -08:00
Cary R e611e8acc0 Add support to convert always_comb/latch to vlog95 2017-12-03 20:17:42 -08:00
Cary R 575aa9b0fb Fix spelling in always_comb 2017-12-03 20:17:42 -08:00
Cary R 84d0df8a8a Pass to the targets if an implicit T0 trigger event is needed. 2017-12-03 20:17:42 -08:00
Cary R 585a0232cb Add preliminary support for always_comb, always_ff and always_latch 2017-11-20 07:50:05 -08:00
Cary R c68a7fede3 Fix spacing 2017-11-20 07:30:52 -08:00
Cary R 3fc9ad2db0 Add support for the wild compare operators ==? and !=? 2017-11-17 19:32:50 -08:00
Cary R d23b046203 Update the enumeration methods to set their width test attributes correctly 2017-11-17 13:09:14 -08:00
Cary R 21418c6a41 Fix a couple memory leaks in $sdf_annotate() 2017-11-16 19:42:07 -08:00
Cary R f03033e612 Update flex destroy routines to work for version 2.6 and greater 2017-11-16 19:11:50 -08:00
Martin Whitaker d1487c10f1 Fix shadow warning when using older versions of gcc. 2017-11-08 21:23:22 +00:00
Martin Whitaker ad83a135e5 Fix assertion failure in vvp wide functor.
If the functor output is read before any values have propagated to
the functor inputs, the internal storage won't have been initialised.
2017-11-08 20:35:18 +00:00
Martin Whitaker 0f2ce7da45 Fix for GitHub issue #172: don't use %precedence in parser.
Older versions of bison don't support this. Use %nonassoc instead.
2017-11-08 20:20:04 +00:00
Martin Whitaker c0845d8bea Fix assertion failure when using -Wmacro-redefinition, -y, and -D.
Predefined macros get stored in the precompiled macro file that gets
read back in when processing library files. This means the predefined
macros get processed twice. We need to skip the check in this case.
2017-11-08 20:07:38 +00:00
Martin Whitaker 02daffc97e Add option to only warn about macro redefinitions that change the text.
A common use case (prior to the introduction of localparam) was to
use macros to define constant values, and to put global constant
values in an include file that gets included by each source file.
This will generate a lot of spurious warnings if we warn about all
redefinitions. Make this new option the default for -Wall.
2017-11-08 19:50:42 +00:00
Martin Whitaker c622d372f9 Fix for GitHub issue #169: nets can get given wrong scope in VPI.
In vvp, the __vpiSignal object holds a pointer to the scope containing
the signal. This was getting set to the current scope when the net was
finally resolved, rather than to the scope where the net was declared.
2017-11-07 18:48:48 +00:00
Martin Whitaker 1f85cd4154 Merge branch 'nekromant-master'
Adds warning about macro redefinition (GitHub pull request #168).
2017-11-06 21:07:47 +00:00
Martin Whitaker af1ea13c47 Don't check for macro redefinition if the warning is disabled.
And reword the comment to be a bit less dictatorial.
2017-11-06 21:03:03 +00:00
Martin Whitaker e408550d9d Merge branch 'master' of https://github.com/nekromant/iverilog into nekromant-master 2017-11-06 20:59:27 +00:00
Martin Whitaker f83e01847a Fix a couple of minor bugs in the timescale parsing rework. 2017-11-06 00:37:56 +00:00
Martin Whitaker 479af09cc3 Fix trailing whitespace. 2017-11-05 22:28:53 +00:00
Martin Whitaker fd807a7700 Rework handling of timescales in parser.
This implements and enforces the full set of rules for determining
timescales in SystemVerilog. The previous relaxation of the rules
that allowed timescales to be redefined within the compilation unit
scope has been removed. Time unit and precision redeclarations are
now recognised after a nested module declaration.
2017-11-05 17:50:05 +00:00
Martin Whitaker 9382d22063 Factor out common code for warning about inconsistent timescales.
Also reword the warning for SystemVerilog, where `timescale is not
the only (or indeed preferred) way of specifying timescales.
2017-11-05 09:39:21 +00:00
Martin Whitaker e54d19e2d2 Fix $printtimescale to support 10s and 100s values. 2017-11-05 09:28:19 +00:00
Martin Whitaker 913fb34799 Add support for the $unit scope identifier.
This relies on using the automatically generated name for the unit scope.
This could collide with an escaped identifier, so it would be better to
identify the scope by a reference to the PPackage object, but for now,
do it the easy way.
2017-10-31 20:39:49 +00:00
Martin Whitaker 988816c0b1 Support separate compilation units in SystemVerilog.
The compilation unit scope is now treated as a specialised form of
package (with an automatically generated name). All items declared
outside a design element are added to the current compilation unit
package. Apart from when searching for a symbol, once we get into
elaboration we can treat these just like any other package.
2017-10-31 20:38:59 +00:00
Martin Whitaker dfddbea26b First step towards supporting separate compilation units in SV.
This adds a -u option to the driver to allow the user to specify that
they want each source file to be treated as a separate compilation
unit, and modifies the compiler to accept a list of files (either on
the command line or via a file specified by a new -F option). This
list of files is then preprocessed and parsed separately, causing all
compiler directives (including macro definitions) to only apply to the
file containing them, as required by the SystemVerilog standard.
2017-10-31 20:36:27 +00:00
Cary R 7d78f5b2ea A few updates based on cppcheck results 2017-10-23 00:22:01 -07:00