b96e471fa2
Stub code for handling logic gates
2008-06-09 14:08:27 +01:00
7120ab7b13
Expression type might be null in some cases
2008-06-09 12:54:21 +01:00
2f5dcda3b6
Delay statements now translated correctly
2008-06-09 12:49:38 +01:00
120b5dc80e
Add constant integers
2008-06-09 12:46:55 +01:00
d762253f74
Wait statements
2008-06-09 12:40:59 +01:00
a2dc1e0a29
Add means for &A<> to index using a calculated index.
...
This is not a solution to all the problems, but is a better catch-all
then what is currently there. Allow the index field to be a T<> that
accesses the thread to get the address index.
Note that the lexor.lex currently returns the T<> as a T_SYMBOL, and the
users of T_SYMBOL objects need to interpret the meaning. This is
probably not the best idea, in light of all the other *<> formats that
now exist.
2008-06-08 21:38:35 -07:00
6a1235ac28
Rework parameter indexed part select up.
...
Indexed part select reworked to be more compact and more like the
part select.
2008-06-08 19:29:00 -07:00
7aebff2a86
Fix up parameter name part select
...
Part select of parameter names is fixed up to be structurally similar
to part select of signals, and also to behave similarly. (Though not
identically, for reason.)
2008-06-08 07:34:45 -07:00
1d28b935e8
Split vhdl_element.cc into multiple files
2008-06-08 13:27:48 +01:00
4b4a1c6cac
Tidy up type casting
2008-06-08 12:55:18 +01:00
110a1b2ac7
Replace type classes with enumeration
2008-06-08 12:48:56 +01:00
79558910d1
Catch case where NULL return wasn't detected
2008-06-07 16:44:01 +01:00
fbf85398da
Support converting bit strings to std_logic
2008-06-07 16:19:10 +01:00
1e4b96aa0a
Simplify code a bit as rval type is never needed
2008-06-07 14:57:20 +01:00
c064ae6bc3
Generate VHDL for non-blocking assignments
2008-06-07 14:54:00 +01:00
39228f3495
VHDL AST element for non-blocking assignment
2008-06-07 14:31:33 +01:00
12e2237131
Add Type'Image cast to $display parameters
2008-06-07 14:21:50 +01:00
066a9b7a61
Add AST element for function call expressions
2008-06-07 13:29:27 +01:00
cdb180e1d4
Associate a type with each VHDL expression node
2008-06-07 13:23:21 +01:00
a8ecce7421
Make sure all declarations have a type
2008-06-07 12:15:46 +01:00
8c3461f0ff
Generate sensitivity lists properly and add signal declarations
2008-06-07 11:48:38 +01:00
305f448d05
Generate code for signal references
2008-06-07 11:24:09 +01:00
b31124983a
Allow part selects to fall off the ends of the selected identifier
...
Part selects to signals are allowed to be off the ends of the signal
itself. The bits that are beyond the vector return X. This may mean
creating constant X bits on one or both ends of the result.
2008-06-06 22:05:17 -07:00
f256dfe16e
Add missing include to vvp_island.cc
...
Add # include <string.h>, needed for compilation with gcc-4.3
2008-06-06 20:48:23 -07:00
7c152685dc
Clean up more compiletf routines, etc.
...
This patch cleans up some of the code to use common compiletf
routines where appropriate. It also adds code to print the
number of extra arguments and cleans up the messages a bit.
2008-06-06 20:44:21 -07:00
5d86dd0bbd
Merge branch 'verilog-ams'
2008-06-06 20:39:42 -07:00
4f97321c75
Add more array word properties.
...
This patch adds more array word properties.
2008-06-06 20:36:55 -07:00
5f90a3e48c
Translate sub-statement of @{..}
2008-06-06 18:22:03 +01:00
96cf190720
Generate signals and sensitivity list for @(..) statement
2008-06-06 17:56:52 +01:00
373832ba22
Specify correct sensitivity list
2008-06-06 17:36:15 +01:00
4f472e451e
Stubs for statement types in mux2.v test
2008-06-06 16:55:45 +01:00
7e478cdeb8
Merge branch 'master' into verilog-ams
2008-06-05 21:52:12 -07:00
2576543bb5
Add support for exclude of a point
...
Parameter value ranges support the exclude of a point as well as
range, so add the syntax to support that case. Internally it is
handled as a degenerate range, but the parse and initial elaboration
need to know about it.
2008-06-05 21:49:49 -07:00
e453b347f4
Add missing functions to ivl.def
...
This patch adds ivl_island_flag_set and ivl_island_flag_test
to the ivl.def file. This is needed by both Cygwin and MinGW.
2008-06-05 14:41:49 -07:00
f132e09475
Fix default parameter type if localparams are present.
...
localparam declarations were messing up the state of parser variables
so that the default types of following parameters got messed up.
2008-06-05 14:38:56 -07:00
2ee976d1c0
Compile problems after merge with verilog-ams
...
The NetPartSelect::BI enumeration value does not exist any more.
2008-06-05 11:06:54 -07:00
30570adf31
Merge branch 'master' into verilog-ams
2008-06-05 10:52:58 -07:00
1c51ac4ac0
For undefined memory words (size == 0) return an X vector.
...
If a memory word was accessed before it was defined the
code was returning a zero width vector result. Now it
returns an appropriately sized vector of 'x'.
2008-06-05 10:34:18 -07:00
17a1358eb6
Remove documentation for memory opcodes.
...
The memory opcodes %assign/mv, %load/mv and %set/mv
were removed by a previous patch. This one removes
the documentation from opcodes.txt. It also removes
the documentation for the .mem* statements for the
same reason.
2008-06-05 10:31:38 -07:00
d36bbec5b5
Generate VHDL for no-op statements
2008-06-05 13:16:35 +01:00
04a7f7054a
Fix problem linking a-side and b-side tran branches.
...
Tran devices linked in series were not getting properly joined up
due to a problem with the add_branch method.
2008-06-04 20:34:04 -07:00
e97a1ad610
Try to eliminate excessive processing recursions.
...
After calculating the A side of a tran[if/vp], the B side is usually
fully specified, so make an effort to push the calculated value through.
2008-06-04 16:10:43 -07:00
e258058cf1
Fully qualify std.textio.Output to avoid name collisions
2008-06-04 21:58:51 +01:00
c3ac1aac8c
Remove debugging messages from output
2008-06-04 21:07:50 +01:00
234f73e7bf
Don't generate any output if there were errors
2008-06-04 21:03:36 +01:00
f49dd97d24
Add support for blocks and make hello1.v test pass
2008-06-04 20:57:15 +01:00
7bd1565cfb
$display now (mostly) working
2008-06-04 20:42:44 +01:00
e872310e4b
Optimize recursive branch resolution
...
Recursive branch resolution was scanning every branch end, even though
many branch ends share ports and need not be repeatedly scanned. Handle
marks and flags to cut off recursion where it is not needed so as to
save much run time.
2008-06-04 11:34:26 -07:00
6e448da90d
Emit Write() calls for parameters of $display
2008-06-04 15:19:44 +01:00
9f035108e1
Stub code for translating expressions
2008-06-04 14:59:04 +01:00
Nick Gasson
Stephen Williams
Larry Doolittle
Cary R