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Commit Graph

Author	SHA1	Message	Date
Stephen Williams	da0fb1666f	Detect always @edge patterns VHDL doesn't have a direct way to express "always @(posedge...)" statements, but we do want to detect common paradigms that naturally translate. This makes for a better translation.	2011-05-28 10:49:33 -07:00
Stephen Williams	3e419dc854	Parse/decorate sequential statements. Get to the point where our sample program parses completely, and the sequential statements generate SequentialStmt objects and a process object in the architecture. Also add a few missing expression types.	2011-05-08 16:40:35 -07:00

Author

SHA1

Message

Date

Stephen Williams

da0fb1666f

Detect always @edge patterns

VHDL doesn't have a direct way to express "always @(posedge...)"
statements, but we do want to detect common paradigms that naturally
translate. This makes for a better translation.

2011-05-28 10:49:33 -07:00

Stephen Williams

3e419dc854

Parse/decorate sequential statements.

Get to the point where our sample program parses completely, and
the sequential statements generate SequentialStmt objects and a
process object in the architecture.

Also add a few missing expression types.

2011-05-08 16:40:35 -07:00

2 Commits