Commit Graph

4553 Commits

Author SHA1 Message Date
Cary R 54aae2c1c2 Fix number to real mask generation
The << operator may not be defined when the RHS is greater than or
equal to the LHS width. To work around the problem the mask is
incrementally generated.
2007-10-19 17:10:34 -07:00
Cary R 3543c0605c Disable lxt support if libbzip2 is not found.
Configure was checking for libbzip2, but it was not doing anything with
the result. This patch disables lxt support if libbzip2 is not found.
2007-10-18 21:17:50 -07:00
Stephen Williams 230d0f24de Reformulate number-to-real on vvp code generator
There have been reports in the field of number-to-real conversions
doing bad things with the calculated mantissa. This patch eliminates
a opssible portability problem by reworking the negating of negative
mantissa values.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-18 21:09:12 -07:00
Cary R 676695c78f Check for extra digits in sized binary, octal and hex constants.
Print out a warning if extra digits are given for sized binary, octal
or hex constants. Decimal constants are very hard since we never
calculate the true number of bits the digits represent, so for now
decimal constants are not checked.
2007-10-18 10:12:20 -07:00
Cary R 58e4c562cb Add $dumplimit task.
The attached patch add an implementation for $dumplimit(). It does
not do a hard limit to the file size, but for VCD files it completes
the current time step and puts a comment in the file. For lxt and
lxt2 files the functionality is in place, but because of buffering
the file can be slightly larger than expected.
2007-10-16 14:11:51 -07:00
Stephen Williams 6e6392f2d7 Merge branch 'master' of steve-icarus@icarus.com:git/verilog 2007-10-15 20:24:08 -07:00
Stephen Williams 27b704b054 Regularize padding of signed constants
Factor common code for processing signed constants to be padded.
In the process, fix some minor bugs in the padding decisions.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-15 20:17:06 -07:00
Stephen Williams e1dbe7eede Merge branch 'master' of ssh://steve-icarus@icarus.com/home/u/icarus/steve/git/verilog 2007-10-11 14:50:00 -07:00
Cary R 5410f0f998 Implement $fopenr(), $fopenw() and $fopena().
Implements $fopenr(), $fopenw() and $fopena() from Chris Spear's File I/O
for Verilog.
2007-10-11 14:39:33 -07:00
Cary R 7bba276a79 Propagate sign for constant numbers inside $signed()/$unsigned().
The sign information from $signed() or $unsigned() was not being
propagated correctly for constant numbers.
2007-10-10 20:27:30 -07:00
Stephen Williams e97bdf8b21 Support for wide modulus operations.
Compile time support for wide modulus.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-09 21:40:08 -07:00
Stephen Williams a0b1272a62 Fix signed/unsigned warnings
Fixed some signed/unsigned warnings, including one that caused an
actual runtime error if not dealt with safely.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-09 21:19:38 -07:00
Stephen Williams 1086c480af Merge branch 'master' of steve-icarus@icarus.com:git/verilog 2007-10-09 21:06:19 -07:00
Stephen Williams ae16eacec9 Argument to $unsigned is self-determined.
The argument to $unsigned is self-determined no matter what the
context the $unsigned itself is in. This is important only where
the result can be negative but the result width is context-determined.
Do ocntext fitting manually to prevent the context fitting it and
affecting the expression argument.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-09 20:46:17 -07:00
Stephen Williams c08e547d1d Merge branch 'master' of ssh://steve-icarus@icarus.com/home/u/icarus/steve/git/verilog 2007-10-09 10:12:55 -07:00
Cary R 38a88014cb [PATCH] Implement System Verilog $urandom and $urandom_range functions.
This patch implements the System Verilog $urandom() and $urandom_range()
functions. There are no check to verify that $urandom_range is only given
unsigned arguments. If you give it a negative value the bit pattern will
be interpreted as a unsigned number.
2007-10-09 10:08:57 -07:00
Stephen Williams c7edace243 Unsized integers have minimum size
Fix the handling of expressions that have unsized integers and are
in self determined context. Unsized integers are generally assumed
to have at least 32bits.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-08 19:58:49 -07:00
Stephen Williams 08028177fe Correct elaboration of network constants.
Constant propagation incorrectly elided an entire constant net node
if only the LSB of the driven vector was HiZ. This caused the entire
vector to look like HiZ. Also, the code generator for writing the
constant values missed bits.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-05 20:31:51 -07:00
Stephen Williams 9ed8614131 Merge branch 'master' of steve-icarus@icarus.com:git/verilog 2007-10-03 22:30:37 -07:00
Stephen Williams acdbe274f9 Fix signed ocmpare of negative numbers.
signed compare in proceedural code was comparing the absolute
value if both operands were negative. Wrong!

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-03 22:26:42 -07:00
Stephen Williams 5d750b7779 Optomize runtime using immediate compare
Implement compare-immediate instructions and generate code to use
these new instructions to improve runtime performance.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-03 20:58:40 -07:00
Cary R d5fe5689e1 Command files can nest, -f is an alias for -c and better error messages.
This patch adds the ability to call command files from other command
files. There is currently a limit of 16 total levels deep (15 stored
plus the current file). -f is now an alias for -c for both the command
line and command files. The parser also reports errors when they occur
along with the file name and line number to aid in debugging problems.
2007-10-02 19:40:45 -07:00
Stephen Williams d587499276 test_width method for functions in expressions
In expressions, user defined functions have a clearly defined
width and the test_width expression needs to express that. Note
that the $signed/$unsigned functions are special and magical.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-01 20:38:20 -07:00
Stephen Williams bbf3116945 Merge branch 'master' of steve-icarus@icarus.com:git/verilog 2007-09-28 18:22:44 -07:00
Stephen Williams 5bb936a226 Fix addressing of variable words.
Variable word addresses are not to be adjusted by the bit select
of the vector direction. That is a holdover from when arrays were
stored as bit vectors.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-28 18:22:17 -07:00
Cary R 3258b7726b Pass local scope precision from compiler to vvp/etc.
This patch adds ivl_scope_time_precision() to the compiler which can
be used to extract the local scope precision. tgt-stub and tgt-vvp
have been modified to use this new function and output a value that
is appropriate. The vvp runtime has been altered to use this new
data which is accessed with the vpip_time_precision_from_handle()
function. vpiTimePrecision uses this function to return the correct
precision.
2007-09-28 15:08:02 -07:00
Cary R d186f2da04 Ambiguous resolution needs to preserve the MSB for StL/etc. signals.
The MSB was not being preserved for L strength signals. This caused
undefined signals (x) to become defined (0).
2007-09-24 17:20:01 -07:00
Stephen Williams 14c0cfd3b1 bufif and nmos/pmos are strength aware
The outputs to bufif and nmos/pmos devices are always strength-aware,
so should have their outputs connected to a net8 device.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-22 21:53:55 -07:00
Larry Doolittle a0cbd235d6 Fix gcc warnings
Fix gcc warnings in ivl_dlfcn.h.
2007-09-20 17:24:14 -07:00
Larry Doolittle bcc034f634 Compile time warnings
Fix compile time warnings detected by gccc 4.2.
2007-09-20 17:20:48 -07:00
Cary R 954579f250 Add min_typ_max to expressions.
This patch adds min_typ_max to expressions. Remember when using a
min_typ_max triplet in an expression they must be enclosed with
parenthesis (1364-2001 section 4.3 page 58).
2007-09-17 10:53:05 -07:00
Cary R 2e12dee658 Decimal constants can be undefined or high-z.
Add the ability for decimal constants to undefined or high-z.
2007-09-17 10:28:52 -07:00
Stephen Williams 3cbe4f076e Merge branch 'master' of ssh://steve-icarus@icarus.com/home/u/icarus/steve/git/verilog 2007-09-10 15:30:51 -07:00
yang yun ju 9d39b3a514 Access to modpaths via VPI
Add support for accessing the modpath nodes via PLI,
and add support for the vpi_set_delays and vpi_put_delays
functions to set the delays on those paths.

- GSoC 2007
2007-09-10 15:30:00 -07:00
Stephen Williams 9c99b002ba Resize vectors to mismatched ports
It is legal in Verilog to bind expressions to ports that do not
match the port width. Icarus Verilog needs to create the necessary
part selects to get the connections right.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-09 21:14:52 -07:00
Cary R 8fe3cc5318 Add missing primitives and fix time units error in tgt-stub.
Add code to handle all the primitives currently defined and
fixed a power of ten error in the time units display (it is
either 10^{units} or 1e{units}, but not 10e{units}).
2007-09-06 18:53:05 -07:00
Cary R d43cda3def Add port checks for primitives.
This patch adds functionality to verify that primitives are given
an appropriate number of ports. For multiple output gates (but,
not, pulldown, pullup) it also reports that Icarus currently does
not support multiple outputs when more than one is given.
2007-09-06 18:50:02 -07:00
Cary R 7c852aa075 Add cmos/rcmos primitives.
This patch adds the cmos and rcmos primitives.
2007-09-06 18:46:22 -07:00
Stephen Williams 203cb0f730 Merge branch 'master' of steve-icarus@icarus.com:git/verilog 2007-09-04 16:42:45 -07:00
Cary R b55e3c11dc mingw needs fseeko/ftello redefinitions in lxt_write.h
These redefinitions were in lxt2_write.h, but missing in lxt_write.h.
This patch adds them to lxt_write.h.
2007-09-04 16:32:52 -07:00
Stephen Williams 7290489e1a Merge branch 'master' of ssh://steve-icarus@icarus.com/home/u/icarus/steve/git/verilog 2007-09-04 16:24:19 -07:00
Cary R 7bf4b64c0a Check that logic gates are not given null ports.
Logic gates do not handle null ports so check for this and
issue an error message when it happens.
2007-09-04 16:13:46 -07:00
Stephen Williams 083b9b6ee6 Handle repeat concatenation in continuous assign
When a repeat concatenation expression is translated to a netlist,
get the repeat expression right. This comes up when an elab_and_eval
elaboration contains a repeat concationation, and the expression is
ultimately turned into a netlist by expr_synth.

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-01 17:36:57 -07:00
Martin Whitaker 963b26283a Generate scopes are more like begin-end scopes
Apparently making generate scopes look like module instances
confuses some 3rd party tools that see this information in the
VCD dump.
2007-09-01 15:06:53 -07:00
Martin Whitaker 59af5d08b7 More portable encoding of vectors
Slight modification to the description of a vector vareable in the
declarations section for the convenience of 3rd party VCD viewers.
2007-09-01 15:00:53 -07:00
Stephen Williams 4af28c7526 Signed divide of 32bit values
Signed divide of 32bit values can overflow if done in a 32bit long
due to the truncation of sign bits. So use the large value algorithm
if the values are >= 31 bits (63 bits on 64bit machines).

Signed-off-by: Stephen Williams <steve@icarus.com>
2007-09-01 14:38:57 -07:00
Cary R 4f6b47b345 Check that functions do not call invalid statements.
This patch adds checks to verify that functions do not invoke
statements that are invalid for them (#, @, wait, enable/call
tasks and non blocking assignment). For reference see section
10.3.4 of 1364-2001.
2007-08-30 20:41:45 -07:00
Cary R 3f6ea1d587 Make C style comments work in false/suppressed ifdef/etc. blocks.
C style comments were not recognized as comments in false or
suppressed sections of ifdef/etc. blocks. This prohibited an
unneeded endif/else/etc. from being commented out with this
style of comment.
2007-08-30 19:01:10 -07:00
Cary R 347ba8bc29 Comment out routines that pr1779647 made obsolete.
I decided not to delete these since we may at some point in time want
this functionality back. For now they are commented out with an
explanation so we know what is going on.
2007-08-30 19:00:07 -07:00
Cary R c7538386fc Start of simulation event needed to be run after initialization events.
This patch splits the end of compile and the start of simulation call
backs code into two different procedures. The end of compile events are
still executed at the same time they alway were. The start of simulation
events are now run after initialization.
2007-08-29 20:20:03 -07:00