Commit Graph

7964 Commits

Author SHA1 Message Date
Cary R b252dc0192 Don't elide unconnected module ports.
When performing a translation we do not want to elide any module
ports. Dropping ports can result in port mismatch issues.
2010-09-08 16:56:47 -07:00
Cary R 4b98a50dce Report and fail gracefully for recursive parameter definitions.
If someone accidentally makes a parameter depend on itself
we need to report this not crash. This patch fixes the crash
and prints an appropriate string of messages to figure out
the loop. Icarus currently supports forward references of
parameters so more complicated loops can be created. These
are also caught.
2010-09-08 16:51:41 -07:00
Cary R 5e1546faaf Don't elide a BUFZ that represents a continuous assignment.
To prevent a force from back propagating we need to keep a BUFZ
that represents a continuous assignment between two nets. This
only effects continuous assignments of the form assign out = in.
In general these are fairly rare so keeping them has minimal
impact on the simulation speed.
2010-09-08 15:16:37 -07:00
Nick Gasson 56525d0c20 Merge branch 'generics' into vhdl 2010-09-08 19:37:00 +01:00
Nick Gasson c87186a15c Add uwire support to VHDL backend
Implemented as std_ulogic which behaves almost identically.
2010-09-08 11:20:54 -07:00
Cary R c9f28902eb Warn the user that synthesis is no longer maintained.
Add code to print a warning if the user tries to use the -S flag.
We need this warning since synthesis is not currently being actively
maintained or supported in any branch after V0.8.
2010-09-04 16:37:38 -07:00
Cary R 6257d31582 Add another missing probe_expr_width() call.
The indexed select width argument was missing a call to
probe_expr_width() and was crashing the compiler.
2010-09-03 18:38:58 -07:00
Nick Gasson e41f2f36a3 List parameters/values in VHDL entity comment
For example:

  -- Generated from Verilog module child (vhdl_tests/generics.v:30)
  --   MY_VALUE = 3
  entity child is

To make it clear which values were used for this entity.
2010-08-28 17:13:23 +01:00
Nick Gasson 0c883a00bf Change VHDL $finish to use report not assert
Changes:

   assert false report "SIMULATION FINISHED" severity failure;

To just:

   report "SIMULATION FINISHED" severity failure;
2010-08-24 22:17:11 +01:00
Nick Gasson 48ae8c1ce5 Generate VHDL report statements for $display
This changes the implementation of $display/$write to use VHDL
report statements rather the the std.textio functions. The code
produced is simpler and more like what a real VHDL designed would
write. However it no longer exactly matches the Verilog output as
most VHDL simulators prepend the text with simulation time, entity
name, severity level, etc. There is a corresponding change in
ivtest to support this.
2010-08-24 22:13:08 +01:00
Nick Gasson 0cec4495ca Add VHDL report statement
Not output yet, but will be used to replace std.textio
implementation of $display.
2010-08-18 23:50:13 +01:00
Nick Gasson f9da800cf5 Reduce number of 0 ns waits in generated VHDL
Previous we generated a "wait for 0 ns" statement after
every blocking assignment that wasn't the last statement
in the process. While this implements the Verilog semantics,
it generates excessive waits, and cannot usually be synthesised.
This patch only generates "wait for 0 ns" statements when it
cannot be avoid (e.g. when the target of a blocking assignment
is read in the same process).

An example:

  begin
    x = 5;
    if (x == 2)
      y = 7;
  end

Becomes:

  x <= 5;
  wait for 0 ns;    -- Required to implement assignment semantics
  if x = 2 then
    y <= 7;         -- No need for wait here, not read
    -- wait for 0 ns  (previously)
  end if;
2010-08-17 22:49:27 +01:00
Nick Gasson 406d3936af Add find_vars method to VHDL syntax objects
Finds set of read and written variables. For use in
post-processing the syntax tree for cleanup.
2010-08-17 22:49:27 +01:00
Nick Gasson 0d6b42885b Reduce superflous parens in generated VHDL
Purely cosmetic, replaces output like:

  if (x + foo(x + (2 * y))) then ...

With:

  if x + foo(x + (2 * y)) then ...
2010-08-17 22:49:27 +01:00
Stephen Williams 2c11850f3c Merge branch 'master' of ssh://steve-icarus@icarus.com/home/u/icarus/steve/git/verilog 2010-08-15 16:38:11 -07:00
Cary R f29d09dcbe Add uwire support/functionality to the stub and vvp back ends
This patch adds a check in the vvp back end that a uwire has
at most one driver. Previously this was just converted (with
a warning message) to a wire just after elaboration.
2010-08-15 16:29:20 -07:00
Cary R 6023ab0893 Remove some incorrect const properties
A recent patch incorrectly change these two methods to const.
2010-08-13 20:16:57 -07:00
Cary R 03f6283203 Add support for calling system functions as a task (SystemVerilog)
This patch adds the ability to call a system function as a task for
the SystemVerilog generation (-g2009). The return value is really
calculated, but it is ignored.
2010-08-13 20:05:23 -07:00
Cary R 860f8627ba Fix some possible memory leaks and make some methods const.
This patch fixes a couple places where there were some memory
leaks on error and also makes some methods const that can be.
Found with cppcheck.
2010-08-11 17:39:20 -07:00
Nick Gasson d33082bca5 Resize VHDL vector before cast in signed comparison
E.g. $signed(x) > y with x, y different sizes should be

  resize(signed(x), N) > y

Not

  signed(resize(x, N)) > y

As this does not treat the sign bit correctly. Was causing
the signed5 test to fail.
2010-08-11 17:34:16 -07:00
Nick Gasson ae0fe9541d Rename modules which are VHDL reserved words 2010-08-11 17:30:27 -07:00
Nick Gasson 5e0f80afca Avoid emitting VHDL Bool_To_Logic calls for common cases
No functional change, just improves the output a bit. E.g.

  x <= Bool_To_Logic(y = z);

Becomes:

  x <= '1' when y = z else '0';
2010-08-08 14:34:13 -07:00
Nick Gasson 090f7730e6 Avoid VHDL type error in concurrent assignment
When translating a relational LPM to concurrent VHDL assignment, the
generated code would be incorrect if the input types differed in
signedness.
2010-08-08 14:34:06 -07:00
Nick Gasson 2d97486897 Rename VHDL instances which are reserved words
Fixes compiler errors with some real-world examples
2010-08-08 14:34:00 -07:00
Patrick Doyle 2ffc2d36f2 Keep expression width when evaluating expressions ahead of time.
Added 'expr_wid' parameter to calls to 'eval_expr()' within
PEBinary::elaborate_eval_expr_base_()'.  This makes a specific problem
go away and may even be the correct thing to do.
2010-08-06 22:13:13 -07:00
Stephen Williams f23a56e632 Revert "Add $info, $warning and $error as aliases to $display"
This reverts commit 99619bc326.
The $error functions are already well supported in devel, so this
patch does nt belong there. Oops.
2010-07-31 17:12:12 -07:00
Stephen Williams 99619bc326 Add $info, $warning and $error as aliases to $display
Submitted by voiz@sourceforge.net
2010-07-30 19:11:34 -07:00
Cary R 029a61d074 Fix the white space errors in tgt-vvp 2010-07-30 18:59:38 -07:00
Cary R 314714997f Add support for variable UDP delays.
This patch adds support for a UDP with variable delays. In the process the
intrinsic support for delays was removed from the UDP functor and replaced
with a call to the .delay functor. Both a normal gate and a UDP now use the
same code to generate the delay.
2010-07-30 18:59:29 -07:00
Cary R 86653ddff9 Remove some cppcheck warnings.
This patch modifies the code to remove some more cppcheck warnings.
2010-07-30 18:50:52 -07:00
Cary R 44b08a4630 Update fstapi.c to latest from gtkwave 3.3.10 2010-07-19 21:22:13 -07:00
Cary R 30fa8f64fa Cleanup some compiler warnings under CentOS 5.5
This patch cleans up a couple of warnings when compiling on CentOS 5.5
using gcc 4.1.2.
2010-07-19 21:20:24 -07:00
Stephen Williams a436f7f794 Draw code for a delayed enable to tranif gates. 2010-07-19 21:14:29 -07:00
Stephen Williams ae3b6a9de2 Show tranif delays in the diagnostic dumps. 2010-07-18 20:43:42 -07:00
Cary R df4722b92c The switch gates do not support a strength specification.
This patch splits the switch types out of the gates to allow
them to be defined to not take a strength specification.
2010-07-13 19:21:02 -07:00
Cary R 5fe5171e49 Fix bug when calculating the decay time from two variable delays.
We need to also update the decay time if the new rise/fall value
is less than the minimum value and we are in ignore decay mode.
2010-07-13 18:23:21 -07:00
Cary R 13fb07dc17 Add support for only two variable delays and add delay checks.
This patch adds checks that the delay count is correct for the
various gates and adds support for a missing variable decay
time. For this case the decay time is the minimum of the rise
and fall times. This is denoted by setting the decay variable
to 0 in the vvp file. vvp notes this and sets an ignore decay
time property in the base delay. This turns off the ability
to set the decay time and the minimum delay calculation will
also update the decay time.
2010-07-13 18:23:16 -07:00
Cary R 6fbf47025f We have already verified that we have a 64 bit immediate value.
These checks are not needed since we have already verified that
we have a 64 bit immediate value. This is likely old code that
should have been removed when the original functionality was
changed.
2010-07-13 16:25:19 -07:00
Cary R 2bf3f5d1d3 Push tranif delays to the code generator.
This patch pushes delays for tranif gates to the code generator.
We still need to add checks for the number of delays, etc. For
now an error message is printed when a tranif gate is given a
non-zero delay.
2010-07-13 16:04:05 -07:00
Cary R a8198b38fb Add unlimited tail recursion for the real ternary operator.
This patch modifies the real ternary operator code to support
unlimited tail recursion without overflowing the thread
registers. Head recursion is still limited by the available
registers.

It fixes the thread word checks to use a new define that has
the correct number of thread words (16). It adds a message
instead of just an assert if the thread words are exhausted.

And it also changes some of the error messages to use vvp.tgt
in the message to be consistent with the other messages.
2010-07-11 17:24:37 -07:00
Stephen Williams fb1853144b Continuous assignments have their own driver
Elaborate conditional assignments with BUFZ devices that do *NOT*
preserve strengths. Add a BUFT (transparent) device that can be
used in those cases where I really need a transparent buffer.
2010-07-11 17:16:15 -07:00
Cary R 4dcebe4024 Only set the multiply width if it is greater than zero and vectorable
We only need to set the width of a multiple if the width is greater
than zero and if the expression is vectorable. This matches what is
done for addition.
2010-07-06 20:15:51 -07:00
Cary R ed29161614 Update fstapi files to match the GTKWave 3.3.8 release.
This patch updates fstapi.{c,h} to match the ones in the GTKWave
3.3.8 release.
2010-07-01 16:37:10 -07:00
Cary R 21d15ceece Fix the compiler and modpath scaling of real delays.
A real delay must be scaled and rounded using the local precision
before it is finally scaled to the simulation time units. This
patch fixes the compiler to do this correctly or generate the
correct code for run time calculated delays. Delays in a CA
already worked correctly. The run time was also fixed to scale
modpath (SDF back annotation) delays correctly.
2010-06-18 16:11:54 -07:00
Cary R 3868334f5c Fix some on error memory leaks in vvp.
This patch modifies the vvp main code to cleanup if there was an
error compiling the input file. There are still a few issues, but
this takes care of most of them.
2010-06-18 15:52:21 -07:00
Cary R 07ee2e7dff On error there is no need to pop the scope.
The error routines for task and function definitions were incorrectly
popping the scope. This should not be done since no scope was pushed.
Also assert that the current_task/function is 0 to catch that kind of
error like the other definition rules.
2010-06-18 15:48:00 -07:00
Cary R 263dff6fbe Update fstapi.c to match latest from GTKWave. 2010-06-11 15:41:00 -07:00
Cary R 3f6aff47c9 Add run time support for calling system functions as task.
This patch adds two new opcodes and the infrastructure needed to call
system functions as tasks. The normal %vpi_call will generate an error
if a system function is called as a task. %vpi_call/w will generate a
warning and will ignore any value returned by the function. %vpi_call/i
will ignore the system function return value and will not print a
message. Adding this is a feature request and is supported in
SystemVerilog. Next I need to add flags to control this depending on
the compiler generation and possibly other flags.

I may leave the cast to void (%vpi_call/i) functionality unimplemented
for now.
2010-06-11 15:39:16 -07:00
Cary R 3d63f664c8 Cache vpi_call error messages so we can include file and line info.
This patch caches the vpi_call error messages (task/function does
not exist, task being called as a function and function being
called as a task). This allows us to display the file name and line
number information for the invalid usage.
2010-06-08 11:11:52 -07:00
Cary R b2d479eaf6 Don't crash when using `define value for an `include argument.
When pushing the current file path we need to get past any `define
expansions that have been pushed onto the stack to find the real
file path.

This patch is partially based on a patch submitted by Steve Tell.
2010-06-08 11:10:32 -07:00