Commit Graph

7964 Commits

Author SHA1 Message Date
Cary R b0269fa926 Add -Wextra for C++ compiling in the vpi and vvp directory.
This patch adds -Wextra to the compilation flags for C++ files in
the vvp and vpi subdirectories. It also fixes all the problems
found while adding -Wextra. This mostly entailed removing some of
the unused arguments, removing the name for others and using the
correct number of initializers.
2010-10-14 19:18:18 -07:00
Cary R be44214598 Add cppcheck target to the Makefile
This patch adds support for running cppcheck from the Makefile. It also
standardizes the order of some of the targets. It renames vpip_format.c
to vpip_format.cc and fixes the size of the array tables to make room
for the trailing NULL. Found when using a C++ compiler.
2010-10-14 19:11:32 -07:00
Cary R 225ee65c31 Fix some vvp initialization problems found with cppcheck.
This patch adds a few missing initializations to various constructors
in the vvp directory. It also enhances the array alias code to copy
more values from the aliased array.
2010-10-14 17:48:12 -07:00
Cary R eb525b6c2a Fix some initialization problem found with cppcheck.
This patch adds a few missing initializations to various constructors
and reworks the realloc() error handling code in driver-vpi/main.c.
2010-10-14 17:48:02 -07:00
Cary R cb86fb15bf Add error checking definitions for malloc(), realloc() and calloc()
This patch adds defines that translate all malloc(), realloc() and calloc()
calls into ones with error checking when ivl_alloc.h is included.
2010-10-14 17:39:23 -07:00
Jared Casper 93f84535b3 Heed and remove warning issued by autoconf 2.68.
Starting in autoconf 2.68, "the macros AC_PREPROC_IFELSE,
AC_COMPILE_IFELSE, AC_LINK_IFELSE, and AC_RUN_IFELSE now warn if the
first argument failed to use AC_LANG_SOURCE or AC_LANG_PROGRAM to
generate the conftest file contents."
2010-10-14 17:35:55 -07:00
Stephen Williams c545cd3e33 Certain expressions can convert BOOL to LOGIC
A ternary can convert BOOL inputs to LOGIC if the select is LOGIC.
A concat is LOGIC if any of its inputs is LOGIC.
2010-10-13 20:07:44 -07:00
Stephen Williams 67000e46a8 Implement atom2 types with vvp_vector2_t.
This reflects the SystemVerilog intent, and also washes away
the 'bx and 'bz values properly.
2010-10-12 20:49:38 -07:00
Stephen Williams 4643872fc6 Generate .net/2x records for IVL_VT_BOOL type nets.
The code generator writes out the proper .net/2x records for
atom2 types, and the vvp run-time parses and interprets those
records.
2010-10-10 19:39:58 -07:00
Stephen Williams ee25f0f217 IVL_VT_BOOL variables generate .var/2x records.
IVL_VT_BOOL variables at the code generator should generate
.var/2x records so that the run time can do 2-value optimizations
and otherwise support atom2 values.
2010-10-10 10:32:19 -07:00
Stephen Williams dd7fecb577 Add missing sv_vpi_user.h header file. 2010-10-10 10:06:27 -07:00
Stephen Williams 568ee4436f Allow variables to implicitly convert to unresolved nets.
SystemVerilog allows variables to be either variables or unresolved
nets, depending on how they are used. If they are assigned by
procedural code, then they are variables. If they are assigned
by a continuous assignment, they are unresolved nets. Note that
they cannot be both, and when they are unresolved nets they can
only be assigned once.
2010-10-10 10:06:27 -07:00
Stephen Williams 6a0cbc5fa8 VPI access to atom2 types.
Create the .var/2u and .var/2s variable records and give them
basic implementations. Make available to VPI the proper types
for the SystemVerilog types that these variables represent.
2010-10-10 10:06:27 -07:00
Stephen Williams af6fd66648 Tasks functions with atom2 arguments.
Parse 2-value atoms as arguments to functions and tasks.
2010-10-10 10:06:27 -07:00
Stephen Williams e03ff763fb Parse support for SystemVerilog atom2 types. 2010-10-10 10:06:26 -07:00
Stephen Williams f7ce0f3b79 Merge branch 'vhdl2'
This is Nick Gassen's work on the VHDL code generator.
2010-10-07 20:59:16 -07:00
Larry Doolittle eaccf4d64f Add possibility of const-correctness
Follow-up to "Brainless start to const-correct changes"
Still actually does nothing, but now if the #define ICARUS_VPI_CONST
in vpi_user.h is changed to const, Icarus is almost const-correct,
as checked with gcc flags -Wcast-qual -Wwrite-strings.

Choosing when to #define ICARUS_VPI_CONST const is left as an
exercise for the reader.

With these two patches applied, and the const define, there are
still about a dozen const problems left.
2010-10-06 15:12:28 -07:00
Larry Doolittle 5d977cac73 Brainless start to const-correct changes
Results of running
cd vpi
for f in *.c *.h; do sed -i \
  -e "s/_calltf(PLI_BYTE8/_calltf(ICARUS_VPI_CONST PLI_BYTE8/" \
  -e "s/_compiletf(PLI_BYTE8/_compiletf(ICARUS_VPI_CONST PLI_BYTE8/" $f; done
and a trivial patch to vpi_user.h to, among other things, make
ICARUS_VPI_CONST blank.

Thus, this patch does absolutely nothing.  Will be followed by a
(much shorter) patch that makes it do something.  :-)
2010-10-06 15:08:54 -07:00
Cary R 3141ef71d0 Add probe_expr_width() for specparam value.
This patch adds a call to probe_expr_width() before a specparam
value is evaluated. This calculates the expression type/width.
2010-10-06 15:04:11 -07:00
Stephen Williams 0950fbb9a3 Clean up some vvp signal casts. 2010-10-06 15:02:45 -07:00
Nick Gasson 0144b5a2bb Basic parameter support in VHDL target
This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
2010-10-05 20:03:08 +01:00
Nick Gasson 19b592a336 List parameters/values in VHDL entity comment
For example:

  -- Generated from Verilog module child (vhdl_tests/generics.v:30)
  --   MY_VALUE = 3
  entity child is

To make it clear which values were used for this entity.

Conflicts:

	tgt-vhdl/scope.cc
2010-10-05 20:02:49 +01:00
Nick Gasson 249fc93b89 Change VHDL $finish to use report not assert
Changes:

   assert false report "SIMULATION FINISHED" severity failure;

To just:

   report "SIMULATION FINISHED" severity failure;
2010-10-05 20:02:17 +01:00
Nick Gasson a7fe5167e8 Generate VHDL report statements for $display
This changes the implementation of $display/$write to use VHDL
report statements rather the the std.textio functions. The code
produced is simpler and more like what a real VHDL designed would
write. However it no longer exactly matches the Verilog output as
most VHDL simulators prepend the text with simulation time, entity
name, severity level, etc. There is a corresponding change in
ivtest to support this.

Conflicts:

	tgt-vhdl/cast.cc
	tgt-vhdl/display.cc
	tgt-vhdl/vhdl_syntax.cc
	tgt-vhdl/vhdl_target.h
2010-10-05 20:02:04 +01:00
Nick Gasson 9faaf5f817 Add VHDL report statement
Not output yet, but will be used to replace std.textio
implementation of $display.

Conflicts:

	tgt-vhdl/vhdl_syntax.cc
2010-10-05 20:00:16 +01:00
Nick Gasson 2187f30207 Reduce number of 0 ns waits in generated VHDL
Previous we generated a "wait for 0 ns" statement after
every blocking assignment that wasn't the last statement
in the process. While this implements the Verilog semantics,
it generates excessive waits, and cannot usually be synthesised.
This patch only generates "wait for 0 ns" statements when it
cannot be avoid (e.g. when the target of a blocking assignment
is read in the same process).

An example:

  begin
    x = 5;
    if (x == 2)
      y = 7;
  end

Becomes:

  x <= 5;
  wait for 0 ns;    -- Required to implement assignment semantics
  if x = 2 then
    y <= 7;         -- No need for wait here, not read
    -- wait for 0 ns  (previously)
  end if;

Conflicts:

	tgt-vhdl/process.cc
	tgt-vhdl/stmt.cc
	tgt-vhdl/vhdl_target.h
2010-10-05 19:59:25 +01:00
Stephen Williams ec49f10e2d Revert bad merge from vhdl branch 2010-10-02 11:02:27 -07:00
Cary R 7f2cb6afcd Warn the user that synthesis is no longer maintained.
Add code to print a warning if the user tries to use the -S flag.
We need this warning since synthesis is not currently being actively
maintained or supported in any branch after V0.8.
2010-10-02 10:49:37 -07:00
Cary R 3cd928dbe0 Add another missing probe_expr_width() call.
The indexed select width argument was missing a call to
probe_expr_width() and was crashing the compiler.
2010-10-02 10:49:17 -07:00
Stephen Williams 5f64a5ace4 NetCondit may have nil statements when calculating delay types.
It is possible for true clause, false clause, or both, to have
nil statements so the delay_type() method has to account for this.
2010-10-02 10:38:59 -07:00
Stephen Williams c4c7a619ea Merge branch 'vhdl' 2010-10-01 15:13:29 -07:00
Nick Gasson 43f904f793 Add uwire support to VHDL backend
Implemented as std_ulogic which behaves almost identically.
2010-09-30 12:22:39 +01:00
Nick Gasson 419ea8c9ea Merge branch 'generics' into vhdl 2010-09-30 12:16:39 +01:00
Nick Gasson 029fa3fcdf Merge branch 'master' into vhdl 2010-09-30 12:03:56 +01:00
Cary R ea01130ed8 Resize an unsized signed constant if it is less than integer_width.
An unsized signed constant that is smaller than integer_width needs
to be resized up to either the integer_width or the expression width
whichever is smaller.
2010-09-29 17:17:30 -07:00
Larry Doolittle 6388430661 Down payment on const-correctness
Clears out the unambiguous and easy-to-fix const faults,
so we can focus better on the fundamental ones.
2010-09-29 17:15:40 -07:00
Nick Gasson 72f1e5a692 Add find_vars method to VHDL syntax objects
Finds set of read and written variables. For use in
post-processing the syntax tree for cleanup.
2010-09-29 16:57:03 -07:00
Nick Gasson d1314d53bd Reduce superflous parens in generated VHDL
Purely cosmetic, replaces output like:

  if (x + foo(x + (2 * y))) then ...

With:

  if x + foo(x + (2 * y)) then ...
2010-09-29 16:53:45 -07:00
Cary R c71a5f08b9 Fix MinGW specific shadow warning.
This patch removes a MinGW specifc shadow warning.
2010-09-24 15:36:52 -07:00
Cary R 4b16785f16 Fix possible undefined value compiler warning 2010-09-22 13:41:24 -07:00
Larry Doolittle b909c74a20 Spelling fixes
All fixes are in comments, except for one error message (was "iternal error")
2010-09-22 10:43:32 -07:00
Cary R 0dad9e3adb Update fstapi.c to the latest from GTKWave-3.3.12 2010-09-22 09:13:00 -07:00
Cary R cac725ed3d Fix signed/unsigned compare warnings.
Fix all the Icarus files that can be so that we do not have any
signed/unsigned compare warnings. It also removes const as a
return qualifier for two routines in discipline.h.
2010-09-22 09:09:26 -07:00
Cary R f522ca8a9c Pad and sign convert array index expressions as needed.
This patch mimics what was done for vectors, but is simpler since
arrays don't use the endian information. It also needs to address
the fact that .array/port assumes the expression is unsigned so
any signed expression must be padded to make it larger than the
maximum array word when it is converted to unsigned.
2010-09-19 13:41:32 -07:00
Cary R fabde6d1b5 Normalize variable bit/indexed part selects using a fixed routine.
This patch modifies all the variable bit and indexed part selects
to use a common routine. This routine determines the minimum
width needed to calculate the result correctly, pads the expression
if needed and then converts the expression to signed if required to
make the calculation correct.
2010-09-19 13:41:22 -07:00
Cary R dd4fb9b4ef Fix spacing issues.
This patch removes space before a tab and space or tab before end
of line.
2010-09-19 13:21:59 -07:00
Cary R 5ae3e48cdb Fix generation of PS files and hence PDF files on cygwin.
The Cygwin man command requires that you have a / in the path
if you want to avoid looking at the normal search path. This
patch addes ./ before the manual page file name. Which should
work on any system. It also makes the vvp generation create a
PS file like is done in the other Makefiles.

By default we generate normal manual pages. You can then
create PostScript version and from these you can generate a
PDF version.
2010-09-19 13:19:29 -07:00
Cary R acb55916da Resize constants in eval_expr when needed.
If we are given an unsized constant that is smaller then the requested
width then resize the constant to fit.
2010-09-13 16:16:08 -07:00
Cary R 4001c7a27f An if statement is optional and results in no delay.
While checking for an infinite loop in an always block I missed
the case where an if statement does not have a statement. This
was resulting in a segmentation fault.
2010-09-13 14:02:25 -07:00
Nick Gasson d9bf96d8fa Basic parameter support in VHDL target
This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
2010-09-11 12:17:06 +01:00