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7964 Commits

Author SHA1 Message Date
steve b2b8b89cd8 Make configure detect malloc.h 2001-09-15 18:27:04 +00:00
steve 92760f2c5f Support != in virtex code generator. 2001-09-15 05:06:04 +00:00
steve 176be94be9 dead code. 2001-09-14 04:20:49 +00:00
steve 9fda809fa6 Add XOR and XNOR gates. 2001-09-14 04:17:20 +00:00
steve 3c8d598eed Elaborate == to NetCompare instead of XNOR and AND 
gates. This allows code generators to generate
 better code in certain cases.
 2001-09-14 04:16:52 +00:00
steve f2068e83d4 Generate code for identity comparators. 2001-09-14 04:15:46 +00:00
steve 5976e7078c Xilinx uses GROUND and VCC as pin names for the 
GND and VCC devices.

 Connect the top end of the EQ chain to the MUXCY
 instead of to the LUT. The MUXCY has the real output.
 2001-09-12 04:35:25 +00:00
steve da9a84ed84 Use carry mux to implement wide identity compare, 
Place property item in correct place in LUT cell list.
 2001-09-11 05:52:31 +00:00
steve 03b635604a initial structural memory propagation (Stephan Boettcher) 2001-09-11 01:54:58 +00:00
steve 167f94bdbf Add 4 wide identity compare. 2001-09-10 03:48:34 +00:00
steve 4507351d48 Virtex support for mux devices and adders 
with carry chains. Also, make Virtex specific
 implementations of primitive logic.
 2001-09-09 22:23:28 +00:00
steve 0253f92e7e pin down some enumerated constants. 2001-09-09 22:21:57 +00:00
steve 432d4efc9b Connect right ANEB pin when doing NE comparator. 2001-09-09 16:49:04 +00:00
steve 749c3eb5a7 No code for unlinked constants. 2001-09-08 01:23:21 +00:00
steve e933b56507 extend xz from the top character, not the second-from-top. 2001-09-08 01:22:55 +00:00
steve 0c5ce9dfec Redo of_SUBU in a more obvious algorithm, that 
is not significantly slower. Also, clean up the
 implementation of %mov from a constant.

 Fix initial clearing of vector by vector_to_array
 2001-09-07 23:29:28 +00:00
steve acde444439 Separate the virtex and generic-edif code generators. 2001-09-06 04:28:39 +00:00
steve 298a352cbd Add documentation for the code generator. 2001-09-02 23:58:49 +00:00
steve 356552faad Add virtex support for some basic logic, the DFF 
and constant signals.
 2001-09-02 23:53:55 +00:00
steve 5e1e79b3c4 Rearrange the XNF code generator to be generic-xnf 
so that non-XNF code generation is also possible.

 Start into the virtex EDIF output driver.
 2001-09-02 21:33:07 +00:00
steve 2996d2eb19 Generic ADD code. 2001-09-01 04:30:44 +00:00
steve 16023cbbd6 Generate code for MUX devices. 2001-09-01 02:28:42 +00:00
steve 77927972e5 identity compare, and PWR records for constants. 2001-09-01 02:01:30 +00:00
steve d762a320dc Make constants available through the design root 2001-09-01 01:57:31 +00:00
steve a9e54e7553 dead comments. 2001-09-01 00:58:16 +00:00
steve 8b8a3d83e0 Relax pin count restriction on logic gates. 2001-08-31 23:02:13 +00:00
steve 3fbbd4080a synthesize the special case of compare with 0. 2001-08-31 22:59:48 +00:00
steve e79a371f76 Support DFF CE inputs. 2001-08-31 22:58:39 +00:00
steve c507379f09 Handle more path polarity cases. 2001-08-31 21:08:35 +00:00
steve 47031767fa Parse $setuphold statements. 2001-08-31 17:38:41 +00:00
steve af5e68448c Add the fpga target. 2001-08-31 17:28:10 +00:00
steve c1c88f87c6 Many more logic gate types. 2001-08-31 04:17:56 +00:00
steve a9b5c9c037 Add root port SIG records. 2001-08-31 02:59:06 +00:00
steve 03b428b6cb Handle update in place of repeat constants. 2001-08-31 01:37:56 +00:00
steve 271a835305 Bind escaped names with non-escaped equivilents. (PR#256) 2001-08-30 22:40:12 +00:00
steve a3c3019a04 Mangle nexus names. 2001-08-30 04:31:04 +00:00
steve f063bf833f Add the fpga target. 2001-08-28 04:14:20 +00:00
steve 2002c03cef Add some ivl_target convenience functions. 2001-08-28 04:07:17 +00:00
steve b8be5e80cd Generate code for l-value bit selects. 2001-08-26 23:00:13 +00:00
steve c29e11ed36 Add the assign/x0 and set/x opcodes. 2001-08-26 22:59:32 +00:00
steve e35ed6e91c Change the NetAssign_ class to refer to the signal 
instead of link into the netlist. This is faster
 and uses less space. Make the NetAssignNB carry
 the delays instead of the NetAssign_ lval objects.

 Change the vvp code generator to support multiple
 l-values, i.e. concatenations of part selects.
 2001-08-25 23:50:02 +00:00
steve 794ce68a6c Only use fvectors for nets and vars. 2001-08-25 17:22:32 +00:00
steve 31aa85ce7d Handle wide assignment to narrow return value. 2001-08-23 02:54:15 +00:00
steve 15c2b0317d statement ends after while loop labels. 2001-08-16 03:45:17 +00:00
steve 820d8b9edc Support various other string formats for time. 2001-08-16 03:29:31 +00:00
steve a3a0f5f432 Add some missing print escape sequences. 2001-08-16 03:26:04 +00:00
steve a98b5023a8 Describe the new .net behavior. 2001-08-10 04:31:27 +00:00
steve 645c8913f1 Neaten and document the resolv object. 2001-08-10 04:31:09 +00:00
steve 066284d5c2 Make sure arithmetic objects run at time 0. 2001-08-10 00:50:50 +00:00
steve 2802601c44 tgt-vvp generates code that skips nets as inputs. 2001-08-10 00:40:45 +00:00