Class methods belong in a class scope, not the containing module.
So create a lexical scope that carries tasks and functions and
create a PClass to represent classes.
Tasks call arguments may be dropped in favor of default values.
Allow for that in the syntax. This requires a little handling
of the non-SystemVerilog case during elaboration.
Class names can be declared early, before definitions, so that the
name can be used as a type name. This thus allows class definitions
to be separate from the declaration. This creates some complexity in
the parser, since the lexor knows about the class names.
This adds the vector_type_t and real_type_t types to handle
vector and real types in tf_port items. This cleans up a lot
of the parsing for these items.
During parse/pform processing, convert increment statements to
the equivalent compressed assignment statement. This is less weird
for elaboration processing and better expresses what is going on.
This gets me to the point where the parser stashes a defined type,
and the lexical analyzer uses the type names to differentiate
IDENTIFIER and TYPE_IDENTIFIER.
Parse typedefs with structs and enums, but give a sorry message,
because they are not yet supported. Rearrange some of the parse
rules for variables in order to increase comonality with the
typedef rules.
The standard allows a parameter (or localparam) declaration of the
form "parameter signed my_param = ...". The parser currently rejects
this. A small adjustment is also required in the parameter evaluation
code to correctly apply the type.
This patch adds wreal support when in Verilog-AMS mode. It doesn't add
everything that is shown in the Verilog-A standard.
It adds the following:
Declaring a wreal net.
Declaring a wreal net with an initialization.
Declaring a wreal input/output using ANSI syntax.
Declaring a wreal input/output using the old style.
Declaring wreal inout ports are also allowed and parsed, but the
compiler does not know how to handle this. There are other deviations
from what is shown in the Verilog-A standard, but this should get most
of the syntax people actually use.
It is legal for a named block to contain variable definitions and
no statements. This patch fixes this for both style of blocks. It
also organizes the block parsing code to be a bit more clear, adds
an error case for fork/join and changes on check for size() > 0 for
the more efficient ! empty().
This patch fixes a few more bugs in the enumeration code.
It add support for saving the file and line information to make
diagnostic messages better.
It updates some of the compiler warning messages to use the file
and line information.
It passes if the enumeration type is signed all the way to the
code generators.
It fixes the parser to correctly have the range after the signed
designation for the vector types.
It adds a warning that vvp does not currently support a negative
two state enumeration value.
Add a new IVL_PR_FINAL process type.
Add a flag to NetScope in_final_ which is set when elaborating the
statement of a final procedure.
Add checks during statement elaboration for invalid statements in a
final procedure, similar to checks for statements in functions.
Do a final check to make sure no final blocks have delays.
In the vvp runtime, use "$final" as the flag for the thread created by
the final procedure. During compilation, instead of adding such a
thread to the sched_list, add it to a new schedule_final_list that
mirrors the schedule_init_list, but is run at the end of simulation.
This patch adds support for increment/decrement operators as an
expression. The operations on real and vector slices have been
disabled for now.
These operators can be used as in independent statements. However, the
corresponding support is not added in parser.
Changes since V2:
- Additional error checking in elaboration to deny operation on vector
slices and real (suggested by Martin)
Changes since V1:
- Use 'i' and 'I' for increment (suggested by Cary)
- Evaluate sub-expression once (suggested by Cary and Stev)
- Add necessary checks during elaboration to ensure that the
expression is valid (suggested Stev)
- Proper width handling with vectors (suggested by Martin)
Signed-off-by: Prasad Joshi <prasad@canopusconsultancy.com>
This patch adds code to check for a negative or undefined value used in
an enumeration sequence name, it verifies that the count in an enumeration
sequence name is not zero and allows more decimal constant values in the
enumeration sequence name..
SystemVerilog extended the assignments operator support to C-like
assignment operators and special bitwise assignment operators.
For example:
a += 1;
a -= 1;
The list of these operators can be found in SV LRM (1800-2009)
section 11.4.1.
NOTE: I fixed a few parts of this. In particular, the PEBShift
class is used for shift operators.
Acked-and-Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
pow(int, int) is ambiguous since it could use the double version from
the math library or the verinum version. This patch makes it obvious that
we want to use the double version.
SystemVerilog has support for time literals. The time literal for
example #10ns, adds a delay of 10ns no matter the time unit currently
in effect. For more details please refer to
http://iverilog.wikia.com/wiki/Projects#SystemVerilog_Style_Time_Literals
Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Stephen Williams
Cary R
Martin Whitaker
Jared Casper
Prasad Joshi
Prasad Joshi