f001d0001a
Add support for generate loops w/ wires and gates.
2006-04-10 00:37:42 +00:00
368c27c9e4
Handle complex net node delays.
2006-01-03 05:22:14 +00:00
58f182a159
Node delays can be more general expressions in structural contexts.
2006-01-02 05:33:19 +00:00
e4ae832153
Clean up spurious trailing white space.
2004-10-04 01:10:51 +00:00
c6453a0854
primitive ports can bind bi name.
2004-03-08 00:47:44 +00:00
177b6ffb6a
Addtrbute keys are perm_strings.
2004-02-20 18:53:33 +00:00
27af95d402
Use perm_strings for named langiage items.
2004-02-18 17:11:54 +00:00
658706ad8b
lex_strings.add module names earlier.
2003-03-06 04:37:12 +00:00
52bf4e613f
conditional ident string using autoconfig.
2002-08-12 01:34:58 +00:00
e6c0629626
Add language support for Verilog-2001 attribute
...
syntax. Hook this support into existing $attribute
handling, and add number and void value types.
Add to the ivl_target API new functions for access
of complex attributes attached to gates.
2002-05-23 03:08:50 +00:00
82831ea9a5
Use NetScope instead of string for scope path.
2001-11-22 06:20:59 +00:00
9f3e64e11a
Module types in pform are char* instead of string.
2001-10-21 00:42:47 +00:00
6fc556cefc
Method to get the type_ member
2001-10-19 01:55:32 +00:00
66cf3ec8fa
More UDP consolidation from Stephan Boettcher.
2001-04-22 23:09:45 +00:00
ca2fd41bb6
Carry assignment strength to pform.
2000-05-06 15:41:56 +00:00
1db70a0c46
Move signal elaboration to a seperate pass.
2000-05-02 16:27:38 +00:00
d97ab9be23
New and improved combinational primitives.
2000-03-29 04:37:10 +00:00
e7efc2709a
Redesign the implementation of scopes and parameters.
...
I now generate the scopes and notice the parameters
in a separate pass over the pform. Once the scopes
are generated, I can process overrides and evalutate
paremeters before elaboration begins.
2000-03-08 04:36:53 +00:00
b734ecf02f
Macintosh compilers do not support ident.
2000-02-23 02:56:53 +00:00
5b52c384d6
Catch module instantiation arrays.
2000-02-18 05:15:02 +00:00
2de887c2ff
Support named parameter override lists.
2000-01-09 05:50:48 +00:00
3e1738dcec
Fix support for attaching attributes to primitive gates.
1999-12-11 05:45:41 +00:00
8f68a07476
Add support for delayed non-blocking assignments.
1999-09-04 19:11:45 +00:00
9eae940ebd
Parameter overrides support from Peter Monta
...
AND and XOR support wide expressions.
1999-08-23 16:48:39 +00:00
dd8daf40df
elaborate rise/fall/decay for continuous assign.
1999-08-01 21:18:55 +00:00
71d35f32b2
Parse and elaborate rise/fall/decay times
...
for gates, and handle the rules for partial
lists of times.
1999-08-01 16:34:50 +00:00
35893919e0
module parameter bind by name.
1999-05-29 02:36:17 +00:00
5de9b7c9f1
Parse and elaborate the concatenate operator
...
in structural contexts, Replace vector<PExpr*>
and list<PExpr*> with svector<PExpr*>, evaluate
constant expressions with parameters, handle
memories as lvalues.
Parse task declarations, integer types.
1999-05-10 00:16:57 +00:00
e5f5f41515
Elaborate gate ranges.
1999-02-15 02:06:15 +00:00
fb439c78b9
Add the LineInfo class to carry the source file
...
location of things. PGate, Statement and PProcess.
elaborate handles module parameter mismatches,
missing or incorrect lvalues for procedural
assignment, and errors are propogated to the
top of the elaboration call tree.
Attach line numbers to processes, gates and
assignment statements.
1999-01-25 05:45:56 +00:00
e097c999d5
Elaborate UDP devices,
...
Support UDP type attributes, and
pass those attributes to nodes that
are instantiated by elaboration,
Put modules into a map instead of
a simple list.
1998-12-01 00:42:13 +00:00
3fb7a053be
Introduce verilog to CVS.
1998-11-03 23:28:49 +00:00
steve