Cary R
f03033e612
Update flex destroy routines to work for version 2.6 and greater
2017-11-16 19:11:50 -08:00
Cary R
52275deb0e
Fix compile build failure
2015-04-30 10:18:21 -07:00
Cary R
2ac8a555e1
Remove bison warning and make YACC rule match the rest
2015-04-30 10:12:57 -07:00
Cary R
d6b6b76015
Update header files to use a more standard name to prevent rereading
...
This is from github report #16 . There are likely a few more issues
that need to be addressed though this takes care of the major ones.
2014-07-23 13:42:56 -07:00
Cary R
0611135758
Some more cppcheck cleanup/updates
2014-06-29 20:39:40 -07:00
Cary R
0ffd61a835
Remove some cppcheck warnings
2014-06-28 16:56:09 -07:00
Larry Doolittle
be17bfc0e9
Spelling fixes
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Mostly comments.
One user-visible string ("Evalutated to ") changed in the debug_eval_tree case.
2014-01-30 15:34:20 -08:00
Cary R
07cc18284c
Fix print token/argument mismatches and other cppcheck fixes
2013-09-09 13:34:38 -07:00
Cary R
af48acca14
Update tgt-pcb make clean target to remove lex/yacc generated file.
2013-07-22 10:30:39 -07:00
Cary R
9d1084d3c0
Remove reentrant support from tgt-pcb parsing
...
This is just extra overhead since the pcb target does not call the scanner
recursively. This also removes some compile warnings.
2013-07-11 19:19:22 -07:00
Cary R
dec0fa622c
Add CXX warning flag to tgt-pcb and tgt-vhdl and fix warnings
2013-07-11 17:40:57 -07:00
Cary R
dbd05557ca
Fix Makefile and scope.cc in tgt-pcb
2013-07-09 18:54:50 -07:00
Cary R
bcc7973792
Update LDFLAGS usage in tgt-pal and tgt-pcb to match the other directories
2013-01-29 17:28:42 -08:00
Cary R
1305d7659c
Remoce space issues.
2013-01-03 16:21:24 -08:00
Stephen Williams
1b684a4846
Fix build error for tgt-pcb on non-mac systems.
2012-12-26 15:58:12 -08:00
Stephen Williams
3b43fcfc21
Fix pcb.tgt build error.
2012-12-24 17:42:01 -08:00
Stephen Williams
4b3ef8a314
Merge branch 'master' of github.com:steveicarus/iverilog
2012-12-23 12:18:05 -08:00
Arun Persaud
f5aafc32f9
updated FSF-address
2012-08-29 10:12:10 -07:00
Larry Doolittle
befff82655
Spelling fixes
...
Comments and debug messages.
2012-07-27 18:25:32 -07:00
Stephen Williams
f926cbcc59
Merge branch 'master' of github.com:steveicarus/iverilog
2012-04-26 09:03:20 -07:00
Cary R
62b7c52329
Fix a few cppcheck issues and update some suppressions
2012-01-05 18:55:00 -08:00
Cary R
f22b42c2cd
Update tgt-pcb Makefile to handle/clean up config header
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This change matches what is in other header files.
2012-01-03 16:35:03 -08:00
Stephen Williams
5451a4830f
Basic support in tgt-pcb for reading footprint files.
...
When a black-box item requests a specific footprint, we need to
read a file (<footprint>.fp) that contains the actual details
about that footprint. Support parse of that file and use the
loaded Element to generate the footprint for the item.
2011-12-26 23:05:52 -08:00
Cary R
965c77525c
A C++ function passed to C should be declared extern "C"
2011-12-24 11:23:19 -08:00
Cary R
4b96b63166
Fix more tgt-pcb compile problems.
...
On some systems having both %.o: %.c and %.o: %.cc rules confused the
make system. This is directory only has C++ code so remove the %o: %.c
rule. Also the C++ compiler should be used to link C++ object code.
2011-12-24 10:03:15 -08:00
Cary R
37017334af
Fix build issues in tgt-pcb
...
On Ubunto 10.10 (32 bit) tgt-pcb would not build because there were
include file issues. This patch fixes those and uses the C++ include
version where appropriate.
2011-12-24 09:32:19 -08:00
Stephen Williams
a95d64b7de
Add a pcb-s.conf file compatible with the -S flag.
2011-12-24 10:39:41 -05:00
Stephen Williams
a57ce2a709
Add ability to write out Elements in a PCB file.
...
The main .pcb file contains elements, and basic PCB status.
Write out a .pcb file with stub Elements for each of the devices
in the design.
Rearrange the way the files are reported to the code generator
so that we can sensibly express where the output files are.
2011-12-23 17:06:55 -05:00
Stephen Williams
9075326bb7
Introduce PCB code generator.
2011-12-20 14:16:54 -06:00