8e7e3c7493
Remove space issue
2014-07-22 18:59:58 -07:00
588409389e
SV: Add support for var decls in unnamed begin/end blocks.
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SystemVerilog allows variables to be declared in unnamed begin/end
blocks. This patch adds support for this functionality.
2014-07-22 18:58:23 -07:00
14f597acdd
Add support for synthesis translate meta-comments.
2014-07-15 18:03:40 -07:00
0611135758
Some more cppcheck cleanup/updates
2014-06-29 20:39:40 -07:00
734d56ce25
Remove space issue.
2014-04-10 14:37:07 -07:00
c8b20da4be
Merge pull request #21 from toddstrader/master
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package imports in module headers
2014-04-07 14:09:50 -07:00
e55e832ea0
Handle unpacked arrays as output ports.
2014-04-06 08:40:09 -07:00
6caa41cc93
First pass at support for continuous assign of unpacked net arrays.
2014-04-06 08:40:09 -07:00
f8e33b12cd
Clean up pform_module_define_port in preparation for new tricks.
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Get rid of the data_type, signed_flag, and range arguments to the
pform_module_define_port because they add no value within the
parse.y parser. Cleaning these out will hopefully ease the addition
of new functionality.
2014-04-06 08:40:09 -07:00
aaee9989c2
Handle for_variable_declaration
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This can be handled entirely in the parser, where we rewrite the
syntax to me a begin/end block that contains the index variable
declaration and the for loop.
2014-04-06 08:40:08 -07:00
a849249a86
Allow typedefs to override inherited type names.
2014-04-06 08:40:08 -07:00
849ba64cf7
package imports in module headers
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See IEEE 1800-2012 A.1.2 module_nonansi_header and module_ansi_header
2014-04-03 20:11:57 -04:00
a3450bf856
Fixes for GitHub issues 13 and 15.
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The verinum arithmetic operators now observe the standard Verilog
rules for calculating the result width if all operands are sized.
If any operand is unsized, the result is lossless, as before.
They also now all observe the standard rules for handling partially
undefined operands (if any operand bit is 'x', the entire result is
'x').
I've also added the unary '-' operator, and renamed v_not() to be
the unary '~' operator. This has allowed some simplification in
other parts of the compiler.
2014-02-25 20:39:21 +00:00
830083d99b
Merge branch 'x-sizer3'
2014-02-16 17:05:53 -08:00
6902bf44e3
Improved error handling in parser around typedefs.
2014-02-16 17:04:52 -08:00
8f849a9944
Sorry message for unpacked array module ports.
2014-02-16 15:56:32 -08:00
8135f369a5
Fix for GitHub issue 11 : Syntax error on operator attributes.
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Attributes are allowed to be attached to unary, binary, and ternary
operators in expressions. For now just accept and discard them.
2014-02-14 23:29:22 +00:00
52a9fdde8a
Handle packed structs as module outputs.
2014-02-03 19:22:59 -08:00
49cf5556a2
Fix primitive table lexical analysis.
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Sequences of digits in the table of a primitive may be matched
as decimal numbers instead of digits, and this breaks some
primitives.
2014-02-02 10:57:53 -08:00
8a4d769b3d
Type name expressions down to elaboration.
2014-01-11 19:19:15 -08:00
b0491b9c54
Handle typedefs in $root scope.
2014-01-11 19:19:14 -08:00
7669a42cfb
Handle some assertion syntax in the parser.
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Implement some yacc rules for assertion syntax.
Add the -gassertions/-gno-assertions command-line flags to
enable or disable assertions.
2013-12-07 12:20:28 -08:00
49756a8e7a
Unions through pform.
2013-12-07 12:20:28 -08:00
be7d763352
Sorry message for union declarations.
2013-11-22 10:39:48 -08:00
0692cd54e7
Support some simple class initialization assignments.
2013-11-16 17:04:14 -08:00
9bd9c8f301
Implement class extends arguments.
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This implements constructor arguments right after the base class
name in the class extends syntax.
2013-11-10 18:03:19 -08:00
d192f545ac
Chain class instance constructors with arguments.
2013-11-10 18:03:19 -08:00
9f83882bcc
Parse/elaborate class derivation
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This gets us down to working classes, but does not yet implement
calls to the parent constructor, implicitly or explicitly.
2013-11-10 18:03:19 -08:00
97d06b107f
Add support for wait fork to the compiler and code generators
2013-10-22 09:41:03 -07:00
2030e06988
Parse/elaborate some array-patterns down to the ivl_target API.
2013-10-19 15:34:14 -07:00
18c338ad09
Handle array assignment patters through pform.
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This gets us to elaboration. In the process also fix up ivl_type_t
type comparisons to do deep type comparison.
2013-10-19 15:34:14 -07:00
5494c9ae09
Support DARRAY objects as port arguments.
2013-10-19 15:34:14 -07:00
c64b8900ca
Add support for disable fork to the compiler.
2013-10-17 19:34:57 -07:00
a9a1c50268
Support "this" for calling task methods.
2013-09-20 20:44:57 -07:00
5084a23417
Sorry messages for calls to superclass constructor.
2013-09-20 20:44:57 -07:00
46f551073e
Handle default expressions anywhere in port expression list.
2013-09-20 20:44:57 -07:00
9a116498a2
Handle task/function default expressions in parsing/pform.
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This gets it to (but not through) the elaborator.
2013-09-20 20:44:56 -07:00
d8f945be23
Add support for SV do/while
2013-09-16 20:02:09 -07:00
173577d5f7
Merge branch 'work14'
2013-07-03 20:00:22 -07:00
4ef3ac5ca6
Implement const properties of classes.
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This implementation works by detecting assignments
to constant properties in elaboration. Allow initializer
assignments to assign to the constant, error all other
assignments, and otherwise treat the constant like any
other property.
2013-07-02 20:16:47 -07:00
cf47a759d1
Implement the "local" class member protection.
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Test during elaboration that the member really is
accessible in the context where the elaboration
happens.
2013-07-02 20:16:47 -07:00
fbc5557a10
Handle properties that have arbitrary bit widths.
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This fixes the run time handling of arbitrary width
bit vectors as class properties. The vvp code generator
already did the right things.
2013-07-02 20:16:47 -07:00
75b4b94061
Elaborate implicit initializers
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Remaining pform fixup of property initializers, and
elaboration and code generation for implicit constructor.
2013-07-02 20:16:46 -07:00
11e5641089
A real task/function port is also signed.
2013-06-27 13:03:11 -07:00
1b178d56b7
Add support for SystemVerilog return statements.
2013-06-12 14:09:07 -07:00
6364aba975
Fix for br930 - support attributes on old-style port declarations.
2013-05-19 09:16:24 +01:00
71c6193ff1
Finish adding support for end labels in SystemVerilog
2013-05-14 15:01:54 -07:00
7c1638652a
Add support for closing a procedural begin/fork block with a name
2013-05-08 18:34:16 -07:00
51d3c03922
A time variable is always unsigned and pass the integer property
2013-04-30 14:05:19 -07:00
eff6e7a441
Parse to pform shallow copy "new" expressions.
2013-04-21 19:27:57 -07:00
8994ef1483
Implement class constructors.
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Class constructors are the "new" method in a class description.
Elaborate the constructor as an ordinary method, but the only
way to access this method is to implicitly call it. The elaborator
will take the constructor call and generate a naked "new" expression
and implicit constructor method call with the object itself as the
return value.
2013-04-20 16:38:35 -07:00
20ee350601
Generalize user defined function return type handling.
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I'm gonna need functions to return class objects, so generalize
the output types of user defined functions.
2013-04-20 16:38:35 -07:00
632fd006c5
Merge branch 'master' of github.com:steveicarus/iverilog
2013-04-16 16:56:14 -07:00
f536a43e92
Add support for timeunit <time_val> / <time_val>
2013-04-16 14:40:35 -07:00
4dffd97d28
Handle tasks in packages.
2013-04-08 18:20:39 -07:00
eba3d407ca
packages can contain variables.
2013-04-08 18:20:39 -07:00
bae0f1d3a7
Parse more package items
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Rework lexical support for PACKAGE_IDENTIFIER so that the lexor
can help with package scoped identifiers.
Pform package types and package functions up to elaboration.
2013-04-08 18:20:39 -07:00
bdfd5b9b55
Add -g2012 flag and keywords for IEEE 1800-2012.
2013-04-02 14:41:44 -07:00
17330a3073
Elaborate class task and function methods.
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The parse of class methods already works, this patch forms
the methods into their own scopes, and elaborates those scopes.
The "this"
2013-03-24 15:12:35 -07:00
fac5cbca43
Handle this as special identifier strings. / Organize pform class member binding
2013-03-24 15:03:52 -07:00
670601bc2a
Mark class method pforms with their pform class.
2013-03-24 15:03:52 -07:00
25b48fa790
Remove svector template from port handling.
2013-03-24 15:03:52 -07:00
faece5816c
Fix implicit casts in assignments (part 3).
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This patch adds support for bool/bit vector types on the LHS of
a parameter declaration and ensures implicit casts in parameter
declarations are performed where necessary.
2013-03-24 13:50:53 -07:00
b378dccbe9
Update parameter add code to correctly handle a non-Module scope
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A package can have parameters, but it does not have specparams or
keep the order the parameters are defined. This patch skips these
items if the scope is not a Module.
2013-03-08 10:04:46 -08:00
8fa79ceb30
Properly implement import <pkg>::<name>
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This was temporarily implemented to just copy definitions to the
local scope, but the better method is to create a PEIdent that has
the package attached to it.
2013-02-17 17:00:15 -08:00
60cb78e4ab
Add packages and their own scope.
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This makes <pkg>::<name> work properly, and also makes the
package descriptions available through VPI.
2013-02-17 17:00:15 -08:00
99b8086ad2
Import parameters from packages.
2013-02-17 16:59:21 -08:00
77d24cd095
Elaborate class_new and (null) expressions
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This gets the types right for class_new and null expressions, and
elaborate them down to the ivl_target.h API.
2012-12-10 19:13:43 -08:00
55bebc8c39
Stub to pform class properties and null expressions.
2012-12-10 19:13:43 -08:00
0ccb1b4990
Delect class_new and print "sorry" message.
2012-11-03 08:40:03 -07:00
0339f5ed57
Parse package import declarations.
2012-10-21 15:06:23 -07:00
62be9c5b46
Parse (with sorry message) package declarations.
2012-10-21 11:42:19 -07:00
b8093be42f
Rework parse rules to handle more net types.
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This makes the rules for types to be more in line with IEEE1800.
2012-09-03 16:00:10 -07:00
f24d6b055d
Use data_type_t instead of raw type bits.
2012-09-03 16:00:10 -07:00
3d9ed1f0f8
Clean up PWire handling of wire data type. / Reword packed type handling
2012-09-03 16:00:09 -07:00
f5aafc32f9
updated FSF-address
2012-08-29 10:12:10 -07:00
4313fbbf1f
Fix space errors in various files
2012-08-16 11:13:32 -07:00
4af8b03e9d
Fix premature memory delete and missing DLL export definition.
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A couple of errors that showed up in a MinGW build.
2012-08-06 13:31:03 -07:00
5aa97b379d
Add missing semi-colons in parser rules.
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Plus a few minor spelling/formatting fixes.
2012-08-01 15:38:36 -07:00
813f548a4b
Merge branch 'x-mil3'
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Conflicts:
vpi/Makefile.in
vpi/sys_table.c
2012-07-30 17:02:57 -07:00
a5a512758e
Allow a UDP instance to have a simple real delay.
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The parser does not distinguish between module and UDP instances, so
a UDP delay is handled by the rules used for parsing module parameter
overrides. Although these rules had been relaxed to accept the case of
a simple decimal value (e.g. #10 ), they did not allow a simple real
value (e.g. #0.1).
2012-07-27 18:30:09 -07:00
d0e6b24ca2
Support the new[] operator for arrays
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Implement through the ivl core to the ivl_target.h API.
Also draft implementation of creating and storing arrays
in the vvp runtime and code generator.
2012-07-22 10:52:06 -07:00
14f229de30
Parse support for dynamic arrays.
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This includes limited support for dynamic arrays down to the code
generator, and some stubs in the vvp code generator and vvp run time.
2012-07-22 10:52:06 -07:00
d48362b861
First pass at getting strings to work.
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In vvp, create the .var/str variable for representing strings, and
handle strings in the $display system task.
Add to vvp threads the concept of a stack of strings. This is going to
be how complex objects are to me handled in the future: forth-like
operation stacks. Also add the first two instructions to minimally get
strings to work.
In the parser, handle the variable declaration and make it available
to the ivl_target.h code generator. The vvp code generator can use this
information to generate the code for new vvp support.
2012-07-22 10:52:06 -07:00
bef59e0b6c
Fix for pr3534333.
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The parser had been changed to support null statements in sequential
and parallel blocks (a feature introduced in SystemVerilog), but was
not supported in elaboration, leading to a compiler crash. This patch
fixes this by discarding the null statements during parsing.
2012-07-01 12:23:47 -07:00
6a57764e0e
Elaborate fork-join_none and fork-join_any statements.
2012-05-27 18:26:53 -07:00
c0f35cbe62
Disallow modules/gates in program blocks.
2012-05-27 18:26:53 -07:00
8154ce2a4a
Reword how we enforce program block constraints
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Making the scope type NESTED_MODULE was just plain wrong, because
it didn't really encapsulate the meaning of program blocks OR
nested modules. So instead create nested_module() and program_block()
flags and use those to test scope constraints.
2012-05-27 18:26:53 -07:00
dfe7beec31
Allow modules (and program blocks in particular) to nest.
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An important advantage of program blocks is its ability to nest
within a module. This winds up also allowing modules to nest, which
is legal but presumably less used feature.
2012-05-27 18:26:53 -07:00
580c44c015
Prevent non-blocking assignment in program blocks.
2012-05-27 18:26:53 -07:00
0833d9e37a
Basic support for program blocks.
2012-05-27 18:26:53 -07:00
342646264e
Merge branch 'pei1'
2012-05-25 16:32:12 -07:00
6e8aef8262
Get unpacked arrays working.
2012-05-25 15:58:29 -07:00
ceaa60d2f4
Parse (to "sorry") arrays of named types.
2012-05-22 17:31:27 -07:00
2443884779
Parse/sorry nets of named type.
2012-05-22 17:31:27 -07:00
67af96fee7
Module output ports use data_type_or_implicit
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This cleans up the parsing of module output ports, allows for more
complex types on the ports, and fixes some bugs.
2012-05-22 17:31:26 -07:00
b7b633b613
module output ports use data_type_t types.
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This is in place of ad hoc type information passed to the
pform_module_define_port function.
2012-05-22 17:31:26 -07:00
7e202bb5ca
Fix emit of struct ports/declarations.
2012-05-22 17:31:26 -07:00
c7366e65cd
Rework port input and inout to use data_type_or_implicit rule for types.
2012-05-22 17:31:26 -07:00
f7ba954ef7
Fix for pr3527022.
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This patch adds support for an explicit range or type in a parameter
declaration that is part of a module parameter port list.
2012-05-18 13:30:28 -07:00
Cary R
Stephen Williams
Todd Strader (todd.strader@gmail.com)
Martin Whitaker
Arun Persaud
Martin Whitaker