Support IVL_EX_ARRAY_PATTERN in object evaluation for queue-typed class properties: build an empty queue and append pattern elements, matching darray array-pattern object handling. Fix vec4 stack use so %queue/append_word/v is not double-popped. Update class queue locator regression to use direct c.q = '{...} assignment.
Made-with: Cursor
Enable unique and unique_index locator methods with `with (...)` for queues, dynamic arrays, and class dynamic-array properties, including VVP opcode/runtime support and regression coverage.
Made-with: Cursor
Handle IVL_EX_ARRAY_PATTERN in object evaluation by constructing a dynamic-array object and filling elements, so direct class property assignments like c.d = '{...}; codegen correctly without requiring a temporary variable.
Made-with: Cursor
Add class dynamic-array property support for locator methods (find*, unique*, min/max, with predicates) by elaborating dynamic-array property method calls to queue-method sfuns. Extend VVP property paths to treat property values as queue-or-darray sources, not queue-only, and fix object-stack handling in property locator loops so temporary accumulator objects do not hide the class object.
Add regression coverage for class dynamic-array property locators and update locator-method test documentation/listing.
Made-with: Cursor
Add dynamic-array unique() and unique_index() support and extend queue/darray min() and max() to accept locator with(...) predicates. Generate dedicated _with sfuns for min/max, emit VVP code for filtered scans, and reduce through new object-stack min/max opcodes.
Cover the new behavior with ivtest regressions for darray unique and queue/darray min/max with predicates, and update locator method documentation.
Made-with: Cursor
Implement queue and dynamic-array min()/max() for integral vec4 element types, with VVP support for both queue-backed and darray-backed storage and regressions in ivtest. Keep min/max as no-arg methods and document current behavior alongside existing locator tests.
Made-with: Cursor
Implement array locator methods for SystemVerilog queues and dynamic arrays:
find, find_index, find_first, find_first_index, find_last, find_last_index,
unique, and unique_index. Support both value arguments (equality) and
with (predicate) forms using implicit item and index in the iterator scope.
Elaboration returns queue-typed results for first/last/index locators per LRM
(empty queue when no match). Fix assignment compatibility between queues and
dynamic arrays where element types match.
VVP: extend %queue/size, %queue/word, %queue/find*, and %queue/unique* paths
so nets holding vvp_darray (including atom-backed int[]) are handled, not
only vvp_queue_vec4. Queue types still subclass vvp_darray; resolve vec4
queues before plain dynamic arrays. Fall back to the legacy get_queue_object
path for non-vec4 queues. Document opcode and source file touchpoints in
ivtest/ivltests/README_sv_queue_locators.txt.
Add vvp regressions: sv_queue_find*, sv_queue_unique, sv_queue_find_locators_ext,
sv_darray_find_locators.
Made-with: Cursor
Currently nested lvalues are only supported for vector typed properties.
Refactor the code to also support other types.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently assignment operators on queues and dynamic elements trigger an
assert.
Add support for handling this properly. Since the operation for loading an
element for an queue or dynamic array is identical most of the code can be
shared, only writing back the value has to be handled separately.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently assignment operators on object properties are silently
ignored. Make sure that they are handled.
To enable this refactor the code a bit so that the assignment
operator handling can be shared between object property assignments
and scalar value assignments.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Remove implicit casts between vector and real in tgt-vvp. These are not
required since any implicit cast in the source will be converted to an
explicit cast in the elaboration stage.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When multiple words in one array were connected to the same nexus as a
single word array, the code generator was sometimes failing to generate
all the necessary aliases. This was highly dependent on the elaboration
order.
This fix should be more robust, but there are currently no tests in the
test suite that cause the compiler to generate whole-array aliases, and
I can't think of a way to make it do so as we don't yet support unpacked
arrays in module ports, so that branch of the code is currently untested.
When loading a signal into into an index register currently the signedness
of the signal is used when deciding whether sign-extension should be
performed or not. But this can lead to incorrect results, instead the
signedness of the expression must be used as that might be different from
the signal. E.g.
```
reg signed [1:0] = 2'b10;
$display(1 << x[1:0]);
```
gives the wrong result without this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Assignments with an undefined intra-assignment delay should be treated like
assignments with zero delay. For the most part this is implemented
correctly, except for assignments to a part of a vector where the offset
inside the vector is an immediate value. E.g.
```
reg [1:0] x;
integer d = 'x;
...
x[0] <= #d 1'b1
```
Here when loading the delay into the index register flag 4 is updated, but
never cleared afterwards. As a result, if the delay is undefined, the vector
assignment will be skipped. Fix this by making sure flag 4 is always
cleared before the vector assignment instruction.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
For sequences where the tgt-vvp backend generates `%pushi` followed by one
of the operations that have an immediate version replace it with the
immediate version. This is slightly more efficient.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog makes all of the initialisation, condition, and step
components of a for loop optional. We already support this for the
initialisation and step components.
This causes tgt-vvp to use a lower case 'c' instead of an upper case
'C' as the prefix for constant values used to initialise undriven nets.
For use by the following commit.
vvp does not track whether the values stored in a dynamic array or queue
are 2-state or 4-state. Internally the data is always stored as 4-state.
To make sure that the read value is actually 2-state do a cast for 2-state
reads.
E.g. performing an out-of-bounds access on a 2-state dynamic array or queue
will yield a undefined value.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SystemVerilog allows to use assignment patterns to assign values to an
array. E.g. `int a[4] = '{1, 2, 3, 4}`.
Each value is evaluated in the context of the element type of the array.
Nested assignment patterns are supported. E.g. `int a[2][2] = '{'{1, 2},
'{1, 2}};`
Add initial support for array assignment patterns for both continuous as
well as procedural assignments.
For continuous assignments the assignment pattern is synthesized into an
array of nets. Each pin is connected to one of the assignment pattern
values and then the whole net array is connected to target array.
For procedural assignments it is unrolled in the vvp backend. E.g
effectively turning `a = '{1, 2};` into `a[0] = 1; a[1] = 2;`.
Not yet supported are indexed initializers or `default`.
E.g. `int a[10] = '{1:10, default: 20};`
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There are some cases where during an assignment the elaboration step can
generate constructs with the right-hand-side expression being wider than
the left-hand-side expression.
To handle this the tgt-vvp backend inserts a %pad operation when necessary.
One place where this is missing is when writing to an string element. Here
instead an assert is triggered requiring the right-hand-side expression to
be 8 bits wide.
E.g.
```
bit [7:0] x;
bit [8:0] y;
string s;
x = y; // tgt-vvp inserts %pad
s[0] = y; // tgt-vvp triggers assert
```
Long term this should be fixed at the elaboration stage and insert the
proper width cast. But for now solve this the same way as other places in
tgt-vvp and insert the %pad operation for string element assignments if the
width does not match.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently continue and break are supported in most loops. But not in
do-while loops. Add support for them in do-while loops as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This includes support at the parser (pform) through enaboration
and the netlist format for the break and continue statements.
Elaboration actually already worked for for-loops, but since the code
generators need more information, this is a rewire of that support to
be explicit about for-loops. This means they are not rewritten as fancy
while loops. The code generators will have to handle that.
Given the elaboration of for-loops now work, write the vvp code generator
support needed to implement it.
Now that for-loops are presented as for-loops to the code generator, the
vlog95 code generator doesn't need to infer them anymore. Generate the code
more directly.
Also update the tests list so that the vlog95_reg tests all pass.
mjoekhan
Cary R
Lars-Peter Clausen
martinwhitaker
Paul Rigge
mole99
Ethan Sifferman
Stephen Williams