Commit Graph

14 Commits

Author SHA1 Message Date
Stephen Williams 9330b58a3a Merge branch 'master' into work4
Conflicts:
	vhdlpp/lexor.lex
	vhdlpp/parse.y
	vhdlpp/vhdlint.cc
2011-03-14 17:34:57 -07:00
Larry Doolittle e9fda22ad9 Spelling fixes
Mostly then/than confusion.  All comments or README files,
except for one user-visible change in a tgt-vlog95 error message.
2011-03-14 16:28:36 -07:00
Cary R b019c21f46 OpenSolaris portability/bug fixes.
A valarray of an enum does not initialize to 0 so explicitly specify the
value to fill the array with. This was causing the compiler to incorrectly
report that fixed width elements in a concatenation had no size.

The following was done to remove compiler warning when using the native
compiler on OpenSolaris.

Remove the anonymous unions in tgt-vlog95/stmt.c and tgt-vvp/vvp_process.c.

Use UINT_MAX for the maximum unsigned unsigned instead of -1 in
tgt-vvp/draw_net_input.c.

Even though lex defines yywrap() to have no arguments when %option
noyywrp is used it generates a define that takes an argument that is not
used. The compiler warned about this so remove the option and add a
dummy yywrap function.
2011-03-04 10:31:47 -08:00
Cary R 2a0d33608f Fix spacing problems.
This patch fixes spacing problems in the source code, space/tab at
the end of line and space before tab.
2011-03-03 11:21:31 -08:00
Stephen Williams 7d552980a6 Elaborate array subtypes of ports.
There are internal types that are unbounded arrays. Allow subtype
syntax that creates bounded versions of these arrays, and elaborate
them as vectors at port boundaries. This makes some interesting types
work out.

Also start replacing vhdlint and vhdlreal with int64_t and double,
which are reasonable values for universal_integer and universal_real
from the VHDL standard. I need these cleaned up because the ints in
particular are used for the literal expressions in array index constraints.
2011-02-13 19:01:21 -08:00
Stephen Williams 92f6f1058a Identifiers are case-insensitive in VHDL
So translate them to lower case so that internally I don't have to
constantly worry about it. Note that even keywords are case insensitive,
so do the translation BEFORE the keyword check.
2011-02-13 16:52:47 -08:00
Pawel Szostek 77a346ffb1 Added full number, based number (both int and float), string and character literals handling 2011-02-10 18:34:38 -08:00
Pawel Szostek 0395eadbc8 Introductory changes for numbers handling 2011-02-10 18:34:13 -08:00
Pawel Szostek 75203dc121 Minor changes to VHDL lexor 2011-02-10 18:33:53 -08:00
Pawel Szostek d747859a85 New compound VHDL symbols 2011-02-10 18:33:34 -08:00
Stephen Williams ab8f623cea Add file/line information to entities and ports
Include the compiler infrastructure to vhdlpp for collecting the
file and line information and attaching it to entities and ports.
Make the parser store the file name during parse.

Create a libmisc library where I can put source files that are
used by multiple programs within the source tree.
2011-01-18 17:03:51 -08:00
Stephen Williams 02820c9e34 Parse create entities with ports
Create entity objects from entity declarations in the source,
and populate them with ports.
2011-01-18 17:03:51 -08:00
Stephen Williams 04b239a5fb Flesh out VHDL parser engine.
Add enough rules to parse a simple VHDL program:
  Parse library and use clauses,
  Parse entity declarations, and
  Parse architecture bodies.

Add some parser infrastructure:
  Handle syntax errors with useful error messages,
  Include file name and line numbers in parse errors,
  Add some parser debug aids.
2011-01-18 17:03:51 -08:00
Stephen Williams 8cf1fd1820 Introduce shell of vhdlpp program.
Create the makefiles and configuration scripts to hold together
the vhdlpp front-end program. Create a shell main.
2011-01-18 17:03:51 -08:00