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iverilog
mirror of https://github.com/steveicarus/iverilog.git
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53 Commits

Author SHA1 Message Date
steve ebad845fc3 Add procedural while loops, 
Parse procedural for loops,
 Add procedural wait statements,
 Add constant nodes,
 Add XNOR logic gate,
 Make vvm output look a bit prettier.
 1998-11-09 18:55:33 +00:00
steve 5836c8aa4b Properly dump 0 length numbers. 1998-11-07 17:04:48 +00:00
steve 3fb7a053be Introduce verilog to CVS. 1998-11-03 23:28:49 +00:00