256454960c
Add complete list of VHDL reserved words
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make_safe_name now makes sure a VHDL signal is never given a
name that conflicts with any reserved words. If it does, we
just prepend VL_.
(This code was already present, but the full list of reserved
words wasn't.)
2008-11-13 15:45:41 -08:00
5fd32937f2
Fix overly restrictive check for slices
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Fixes some instances of "can only select from a variable reference"
2008-11-12 22:26:44 +00:00
9b640f3114
Shadow reduction part 4
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Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. This patch set covers the tgt-vhdl
directory, and was tested by Nick.
2008-10-30 21:46:44 -07:00
6fe7583784
Cary R.'s additional system functions, real value error messages, etc.
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I've changed the find_entity() error messages to asserts since
this should be fixed by the previous patch.
2008-09-06 12:06:01 +01:00
a34348bb35
Add (temporary) error for ICT_SCOPE_GENERATE
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Generate scopes were previously ignored, and this would cause a segfault
later on. This patch gives an error whenever it encounters a generate
scope. This should be removed once generate statements are implemented.
2008-09-06 11:38:37 +01:00
63a1e25129
Catch case where component name and instance differ only in case
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This causes an error in VHDL (which is case-insensitive). This
patch simply appends _Inst to the instance name if it detects this.
2008-08-22 20:20:17 +01:00
535ef6be38
Change function return value from Verilog_Result to <funcname>_Result
2008-08-21 19:44:12 +01:00
c404b761b7
Change `out' ports to `buffer' when the signal is read
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Previously this was handled by creating an internal
signal that was connected to the output and could also
be read inside the entity. The correct solution is to
make the output `buffer' rather than `out'. However, this
does not work in the case when an output is connected to
an output of a child entity, and that values is read
in the parent. In this case *both* the outputs of the child
and the parent need to be made `buffer'.
2008-08-11 20:48:28 +01:00
7ed8c0915d
Add file/line comments to signal declarations
2008-08-08 20:28:16 +01:00
090ae5fa56
Catch case where signal with same name in task and module
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This fixes task3.14C
2008-08-08 19:47:20 +01:00
13cb81f4bb
Add task signals to containing architecture
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This is necessary to support the in-line expansion of tasks
2008-08-08 19:31:45 +01:00
bb0efda526
Make make_safe_name case insensitive
2008-08-07 17:58:42 +01:00
49a2693357
Add file / line number information to functions
2008-08-03 14:46:57 +01:00
10a5ca199d
Add file / line number comments to instantiations
2008-08-03 14:38:08 +01:00
c2f622327f
Use ivl_scope_def_* for definition file/line numbers
2008-08-03 14:34:41 +01:00
45dfa28dba
Remember signal pin a nexus was attached to
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Also modify nexus_to_var_ref to set the correct array
offset when the signal is an array (the offset comes
from the pin).
2008-08-03 11:41:26 +01:00
c8cbac58f5
Add forward declarations for functions
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This patch adds a forward declaration for every user funciton.
This fixes VHDL compile problems if a function calls another
before it has been declared.
2008-08-03 10:50:31 +01:00
5d0df8d880
Change format of line file/line numbers
2008-08-02 10:42:00 +01:00
bb80b432e6
Add comments file/line number comments
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Added to entities, architectures, and processes
2008-08-01 21:21:42 +01:00
baa2363e85
Split logic device code into separate file
2008-07-30 10:13:08 +01:00
e5b8abfb23
Remove debugging output
2008-07-29 21:15:51 +01:00
9a5b7bb0b0
Connect signals together if joined in a nexus
2008-07-29 21:03:00 +01:00
eaf1cc9120
Fix assertion failure with arrayed signals
2008-07-29 19:47:17 +01:00
3bcd42dc8f
Fix case where logic device has no valid output
2008-07-29 19:39:20 +01:00
744fbed783
Finish re-writing nexus code
2008-07-29 19:33:40 +01:00
c9454b346e
Fix module3.12B
2008-07-29 19:04:41 +01:00
5ec2c37e7e
Get functions working again
2008-07-29 15:29:49 +01:00
25602e487d
Comment
2008-07-29 15:12:51 +01:00
e037ffd952
Create temporaries for LPM outputs
2008-07-29 15:09:58 +01:00
48c1a7982c
Make seen_nexus private
2008-07-29 14:24:04 +01:00
a842b327c7
Generate constant drivers as concurrent assignments
2008-07-29 14:02:05 +01:00
f8034d69ef
Fix constants in nexuses
2008-07-29 13:30:54 +01:00
680c6f0503
Make sure LPMs have valid inputs/outputs
2008-07-29 13:06:21 +01:00
39717989a8
Call set_active_entity in the right places
2008-07-29 13:04:29 +01:00
c26b7ce675
Port maps
2008-07-29 13:02:55 +01:00
c6f6ea7358
Instantiation working again
2008-07-29 12:21:19 +01:00
c0c838f1bc
Logic devices now working again
2008-07-29 12:11:44 +01:00
1a45e9164f
Find signal a logic device is connected to
2008-07-29 12:04:40 +01:00
8a5f129e56
Draw nexus in multiple passes
2008-07-29 12:00:26 +01:00
65c2ceb89d
Build entity hierarchy in separate stages
2008-07-29 11:01:02 +01:00
e4c2400eb2
Refactor the expression->time code into a single function
2008-07-23 16:18:49 +01:00
30fdadc525
Support delays in logic devices
2008-07-23 13:40:42 +01:00
2d79e1a2e0
Store the currently active entity
2008-07-19 14:45:00 +01:00
4d9f029000
Generate correct array bounds
2008-07-17 14:38:07 +01:00
1d3ac6bc1f
Generate VHDL array type declarations of Verilog arrays
2008-07-17 13:08:55 +01:00
c116808fdb
Remove duplicated code
2008-07-17 11:46:36 +01:00
642fbe9fc5
Correct check for arrays
2008-07-17 11:31:06 +01:00
f3753ea9ad
Add warning that arrays are not yet implemented
2008-07-15 18:09:18 +01:00
b8e758edf0
Refactor LPM code
2008-07-15 14:09:24 +01:00
f84f50842c
Support bufif for tri1 nets
2008-07-14 19:13:11 +01:00
Nick Gasson
Larry Doolittle