From fbbff9646d9a4d9b562985d77944882fcb00c975 Mon Sep 17 00:00:00 2001 From: Johan Euphrosine Date: Mon, 23 Oct 2023 16:00:38 +0900 Subject: [PATCH] ivtest: add array_slice_concat --- ivtest/ivltests/array_slice_concat.v | 17 +++++++++++++++++ ivtest/regress-vlg.list | 1 + 2 files changed, 18 insertions(+) create mode 100644 ivtest/ivltests/array_slice_concat.v diff --git a/ivtest/ivltests/array_slice_concat.v b/ivtest/ivltests/array_slice_concat.v new file mode 100644 index 000000000..1421d0733 --- /dev/null +++ b/ivtest/ivltests/array_slice_concat.v @@ -0,0 +1,17 @@ +module ArraySliceWithNarrowStart( + input wire [159:0] a, + input wire start, + output wire [95:0] out +); + wire [31:0] a_unflattened[0:4]; + assign a_unflattened[0] = a[31:0]; + assign a_unflattened[1] = a[63:32]; + assign a_unflattened[2] = a[95:64]; + assign a_unflattened[3] = a[127:96]; + assign a_unflattened[4] = a[159:128]; + wire [31:0] array_slice_6[0:2]; + assign array_slice_6[0] = a_unflattened[{2'h0, start} > 3'h4 ? 3'h4 : {2'h0, start} + 3'h0]; + assign array_slice_6[1] = a_unflattened[{2'h0, start} > 3'h3 ? 3'h4 : {2'h0, start} + 3'h1]; + assign array_slice_6[2] = a_unflattened[{2'h0, start} > 3'h2 ? 3'h4 : {2'h0, start} + 3'h2]; + assign out = {array_slice_6[2], array_slice_6[1], array_slice_6[0]}; +endmodule diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list index 8dd34a0fa..7fd55bf10 100644 --- a/ivtest/regress-vlg.list +++ b/ivtest/regress-vlg.list @@ -157,6 +157,7 @@ array_select_a normal ivltests array_word_check normal ivltests gold=array_word_check.gold array_word_width normal ivltests gold=array_word_width.gold array_word_width2 normal ivltests +array_slice_concat normal ivltests assign3.2A normal ivltests assign3.2B normal ivltests assign3.2C normal ivltests