From faf9bfe158c1817cebdb6e55d64dac3593e7baea Mon Sep 17 00:00:00 2001
From: Martin Whitaker <icarus@martin-whitaker.me.uk>
Date: Sat, 30 Jan 2016 20:11:58 +0000
Subject: [PATCH] Fix for br994 - assertion failure when synthesising a mux.

(cherry-picked from master branch)

The elaborator allows the RHS of assignment to be wider than the
LHS. When using an if statement to represent a mux, this meant the
mux inputs could be different widths, resulting in an assertion
failure during synthesis. The fix is to prune the RHS to match the
LHS for each assignment. This has the benefit of minimising the
mux width.
---
 synth2.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/synth2.cc b/synth2.cc
index aa9dd6389..24fb80a03 100644
--- a/synth2.cc
+++ b/synth2.cc
@@ -226,6 +226,8 @@ bool NetAssignBase::synth_async(Design*des, NetScope*scope,
 	    rsig = tmp;
       }
 
+      rsig = crop_to_width(des, rsig, lsig->vector_width());
+
       if (nex_out.pin_count() > 1) {
 	    NexusSet tmp_set;
 	    nex_output(tmp_set);