From f7162eb5389352a1a2d5def72fdcb76e9e228c8c Mon Sep 17 00:00:00 2001
From: steve <steve>
Date: Wed, 25 Jun 2003 01:49:06 +0000
Subject: [PATCH]  Spelling fixes.

---
 attributes.txt       | 1 -
 tgt-fpga/d-virtex.c  | 7 +++++--
 tgt-fpga/d-virtex2.c | 9 ++++++---
 tgt-fpga/fpga.c      | 8 +++++---
 4 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/attributes.txt b/attributes.txt
index 988f36e0b..3649f0157 100644
--- a/attributes.txt
+++ b/attributes.txt
@@ -43,7 +43,6 @@ warning.)
 
 (* ivl_synthesis_cell *)
 
-    [XXX implementation is started but not complete]
     If this value is attached to a module during synthesis, that
     module will be considered a target architecture primitive, and
     its interior will not be synthesized further.  The module can
diff --git a/tgt-fpga/d-virtex.c b/tgt-fpga/d-virtex.c
index 9d1bda3ed..36e6937a0 100644
--- a/tgt-fpga/d-virtex.c
+++ b/tgt-fpga/d-virtex.c
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: d-virtex.c,v 1.23 2003/06/24 03:55:00 steve Exp $"
+#ident "$Id: d-virtex.c,v 1.24 2003/06/25 01:49:06 steve Exp $"
 #endif
 
 # include  "device.h"
@@ -908,7 +908,7 @@ static void edif_show_virtex_logic(ivl_net_logic_t net)
  * output of the next higher muxcy is guaranteed to be 0, and so on to
  * the final output of the carry chain. If the output from a LUT is ==,
  * then the CI input of the muxcy is selected and the truth of this
- * level depends on lower order bits. The least significan muxcy is
+ * level depends on lower order bits. The least significant muxcy is
  * connected to GND and VCC so that its CO follows the least
  * significant LUT.
  *
@@ -1941,6 +1941,9 @@ const struct device_s d_virtex_edif = {
 
 /*
  * $Log: d-virtex.c,v $
+ * Revision 1.24  2003/06/25 01:49:06  steve
+ *  Spelling fixes.
+ *
  * Revision 1.23  2003/06/24 03:55:00  steve
  *  Add ivl_synthesis_cell support for virtex2.
  *
diff --git a/tgt-fpga/d-virtex2.c b/tgt-fpga/d-virtex2.c
index 1ff4018bf..dcf031472 100644
--- a/tgt-fpga/d-virtex2.c
+++ b/tgt-fpga/d-virtex2.c
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: d-virtex2.c,v 1.12 2003/06/25 01:46:44 steve Exp $"
+#ident "$Id: d-virtex2.c,v 1.13 2003/06/25 01:49:06 steve Exp $"
 #endif
 
 # include  "device.h"
@@ -181,7 +181,7 @@ static void virtex2_show_footer(ivl_design_t des)
 }
 
 /*
- * Make (or retreive) a cell in the external library that reflects the
+ * Make (or retrieve) a cell in the external library that reflects the
  * scope with its ports.
  */
 static void virtex2_show_scope(ivl_scope_t scope)
@@ -832,7 +832,7 @@ static void virtex2_add(ivl_lpm_t net)
  * output of the next higher muxcy is guaranteed to be 0, and so on to
  * the final output of the carry chain. If the output from a LUT is ==,
  * then the CI input of the muxcy is selected and the truth of this
- * level depends on lower order bits. The least significan muxcy is
+ * level depends on lower order bits. The least significant muxcy is
  * connected to GND and VCC so that its CO follows the least
  * significant LUT.
  *
@@ -1139,6 +1139,9 @@ const struct device_s d_virtex2_edif = {
 
 /*
  * $Log: d-virtex2.c,v $
+ * Revision 1.13  2003/06/25 01:49:06  steve
+ *  Spelling fixes.
+ *
  * Revision 1.12  2003/06/25 01:46:44  steve
  *  Virtex support for NOT gates.
  *
diff --git a/tgt-fpga/fpga.c b/tgt-fpga/fpga.c
index d6acde6b6..ea17842b0 100644
--- a/tgt-fpga/fpga.c
+++ b/tgt-fpga/fpga.c
@@ -17,13 +17,13 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: fpga.c,v 1.7 2003/06/24 03:55:00 steve Exp $"
+#ident "$Id: fpga.c,v 1.8 2003/06/25 01:49:06 steve Exp $"
 #endif
 
 # include "config.h"
 
 /*
- * This is a null target module. It does nothing.
+ * This is the FPGA target module.
  */
 
 # include  <ivl_target.h>
@@ -45,7 +45,6 @@ int scope_has_attribute(ivl_scope_t s, const char *name)
       const struct ivl_attribute_s *a;
       for (i=0; i<ivl_scope_attr_cnt(s); i++) {
 	      a = ivl_scope_attr_val(s, i);
-	      fprintf(stderr, "scope attribute key %s\n", a->key);
 	      if (strcmp(a->key,name) == 0)
 		    return 1;
       }
@@ -145,6 +144,9 @@ int target_design(ivl_design_t des)
 
 /*
  * $Log: fpga.c,v $
+ * Revision 1.8  2003/06/25 01:49:06  steve
+ *  Spelling fixes.
+ *
  * Revision 1.7  2003/06/24 03:55:00  steve
  *  Add ivl_synthesis_cell support for virtex2.
  *