From f53a95840ada016a59d70363dfeac83dadfe40ec Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sun, 27 Feb 2022 11:50:32 +0100 Subject: [PATCH] Add regression tests for module output variable type ports Check that a output port that has a explicit data type, but no explicit net type is elaborated as a variable type port. Signed-off-by: Lars-Peter Clausen --- ivtest/ivltests/module_output_port_sv_var1.v | 40 ++++++++++++++++++++ ivtest/ivltests/module_output_port_sv_var2.v | 39 +++++++++++++++++++ ivtest/ivltests/module_output_port_var1.v | 21 ++++++++++ ivtest/ivltests/module_output_port_var2.v | 20 ++++++++++ ivtest/regress-sv.list | 2 + ivtest/regress-vlg.list | 2 + ivtest/regress-vlog95.list | 4 ++ 7 files changed, 128 insertions(+) create mode 100644 ivtest/ivltests/module_output_port_sv_var1.v create mode 100644 ivtest/ivltests/module_output_port_sv_var2.v create mode 100644 ivtest/ivltests/module_output_port_var1.v create mode 100644 ivtest/ivltests/module_output_port_var2.v diff --git a/ivtest/ivltests/module_output_port_sv_var1.v b/ivtest/ivltests/module_output_port_sv_var1.v new file mode 100644 index 000000000..9ff978366 --- /dev/null +++ b/ivtest/ivltests/module_output_port_sv_var1.v @@ -0,0 +1,40 @@ +// Check that ANSI output ports that have a SystemVerilog data type are +// elaborated as variables and be assigned a value. + +typedef struct packed { int x; } T1; +typedef enum { A } T2; +typedef T1 [1:0] T3; + +module test ( + output reg a, + output reg [1:0] b, + output integer c, + output time d, + output bit e, + output logic f, + output shortint g, + output int h, + output longint i, + output real r, + output T1 x, + output T2 y, + output T3 z +); + +initial begin + a = '0; + b = '0; + c = '0; + d = '0; + e = '0; + f = '0; + g = '0; + h = '0; + r = 0.0; + x = '0; + y = A; + z = '0; + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/module_output_port_sv_var2.v b/ivtest/ivltests/module_output_port_sv_var2.v new file mode 100644 index 000000000..5dc0072c8 --- /dev/null +++ b/ivtest/ivltests/module_output_port_sv_var2.v @@ -0,0 +1,39 @@ +// Check that non-ANSI output ports that have a SystemVerilog data type are +// elaborated as variables and be assigned a value. + +typedef struct packed { int x; } T1; +typedef enum { A } T2; +typedef T1 [1:0] T3; + +module test1; +output reg a; +output reg [1:0] b; +output integer c; +output time d; +output bit e; +output logic f; +output shortint g; +output int h; +output longint i; +output real r; +output T1 x; +output T2 y; +output T3 z; + +initial begin + a = '0; + b = '0; + c = '0; + d = '0; + e = '0; + f = '0; + g = '0; + h = '0; + r = 0.0; + x = '0; + y = A; + z = '0; + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/module_output_port_var1.v b/ivtest/ivltests/module_output_port_var1.v new file mode 100644 index 000000000..e093a613b --- /dev/null +++ b/ivtest/ivltests/module_output_port_var1.v @@ -0,0 +1,21 @@ +// Check that ANSI output ports that have a Verilog data type are elaborated as +// variables and be assigned a value. + +module test ( + output reg a, + output reg [1:0] b, + output reg signed [1:0] c, + output integer d, + output time e +); + +initial begin + a = 0; + b = 0; + c = 0; + d = 0; + e = 0; + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/module_output_port_var2.v b/ivtest/ivltests/module_output_port_var2.v new file mode 100644 index 000000000..b9be7dd7e --- /dev/null +++ b/ivtest/ivltests/module_output_port_var2.v @@ -0,0 +1,20 @@ +// Check that non-ANSI output ports that have a Verilog data type are elaborated +// as variables and be assigned a value. + +module test; +output reg a; +output reg [1:0] b; +output reg signed [1:0] c; +output integer d; +output time e; + +initial begin + a = 0; + b = 0; + c = 0; + d = 0; + e = 0; + $display("PASSED"); +end + +endmodule diff --git a/ivtest/regress-sv.list b/ivtest/regress-sv.list index d3c79049f..0532cdabc 100644 --- a/ivtest/regress-sv.list +++ b/ivtest/regress-sv.list @@ -312,6 +312,8 @@ localparam_type2 normal,-g2009 ivltests logical_short_circuit normal,-g2012 ivltests logp2 normal,-g2005-sv ivltests mod_inst_pkg normal,-g2009 ivltests +module_output_port_sv_var1 normal,-g2005-sv ivltests +module_output_port_sv_var2 normal,-g2005-sv ivltests named_begin normal,-g2009 ivltests named_begin_fail CE,-g2009 ivltests named_fork normal,-g2009 ivltests diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list index fd744f42d..ff022cf10 100644 --- a/ivtest/regress-vlg.list +++ b/ivtest/regress-vlg.list @@ -644,6 +644,8 @@ mixed_width_case normal ivltests modparam normal ivltests top # Override parameter via passed down value module3.12A normal ivltests main module3.12B normal ivltests +module_output_port_var1 normal ivltests +module_output_port_var2 normal ivltests modulus normal ivltests # wire % and reg % operators modulus2 normal ivltests # reg % operators monitor normal ivltests gold=monitor.gold diff --git a/ivtest/regress-vlog95.list b/ivtest/regress-vlog95.list index 007beae77..a03185273 100644 --- a/ivtest/regress-vlog95.list +++ b/ivtest/regress-vlog95.list @@ -780,6 +780,10 @@ iuint1 normal,-g2009,-pallowsigned=1 ivltests logp2 normal,-g2009,-pallowsigned=1 ivltests mixed_width_case normal,-pallowsigned=1 ivltests mod_inst_pkg normal,-g2009,-pallowsigned=1 ivltests +module_output_port_sv_var1 normal,-g2005-sv,-pallowsigned=1 ivltests +module_output_port_sv_var2 normal,-g2005-sv,-pallowsigned=1 ivltests +module_output_port_var1 normal,-pallowsigned=1 ivltests +module_output_port_var2 normal,-pallowsigned=1 ivltests packeda normal,-g2009,-pallowsigned=1 ivltests pr1033 normal,-pallowsigned=1 ivltests gold=pr1033.gold pr1380261 normal,-pallowsigned=1 ivltests