From f3cf7ca54665735d28ece001d5fbc52253b057a1 Mon Sep 17 00:00:00 2001 From: Martin Whitaker Date: Sun, 21 Feb 2016 22:39:52 +0000 Subject: [PATCH] Updated comments for synthesis. --- netlist.h | 37 ++++++++++++++++++++++++++----------- synth2.cc | 9 ++++++--- 2 files changed, 32 insertions(+), 14 deletions(-) diff --git a/netlist.h b/netlist.h index 4468b3b2a..2babb174e 100644 --- a/netlist.h +++ b/netlist.h @@ -2618,26 +2618,41 @@ class NetProc : public virtual LineInfo { // process. Most process types are not. virtual bool is_synchronous(); - // Synthesize as asynchronous logic, and return true. The - // nex_out is where this function attaches its output - // results. + // Synthesize as asynchronous logic, and return true on success. + // + // nex_map holds the set of nexuses that are driven by this + // process, nex_out holds the accumulated outputs from this and + // preceeding sequential processes (i.e statements in the same + // block), enables holds the accumulated clock/gate enables, + // and bitmasks holds the accumulated masks that flag which bits + // are unconditionally driven (i.e. driven by every clause in + // every statement). On output, the values passed in to nex_out, + // enables, and bitmasks may either be merged with or replaced + // by the values originating from this process, depending on the + // type of statement this process represents. + // + // The clock/gate enables generated by synthesis operate at a + // vector level (i.e. they are asserted if any bit(s) in the + // vector are driven). typedef vector mask_t; virtual bool synth_async(Design*des, NetScope*scope, NexusSet&nex_map, NetBus&nex_out, NetBus&enables, vector&bitmasks); - // Synthesize as synchronous logic, and return true. That - // means binding the outputs to the data port of a FF, and the - // event inputs to a FF clock. Only some key NetProc sub-types + // Synthesize as synchronous logic, and return true on success. + // That means binding the outputs to the data port of a FF, and + // the event inputs to a FF clock. Only some key NetProc sub-types // that have specific meaning in synchronous statements. The // remainder reduce to a call to synth_async that connects the // output to the Data input of the FF. // - // The events argument is filled in be the NetEvWait - // implementation of this method with the probes that it does - // not itself pick off as a clock. These events should be - // picked off by e.g. condit statements as set/reset inputs to - // the flipflop being generated. + // The nex_map, nex_out, ff_ce, and bitmasks arguments serve + // the same purpose as in the synth_async method (where ff_ce + // is equivalent to enables). The events argument is filled + // in by the NetEvWait implementation of this method with the + // probes that it does not itself pick off as a clock. These + // events should be picked off by e.g. condit statements as + // asynchronous set/reset inputs to the flipflop being generated. virtual bool synth_sync(Design*des, NetScope*scope, bool&ff_negedge, NetNet*ff_clock, NetBus&ff_ce, diff --git a/synth2.cc b/synth2.cc index 1c4070db4..4b4d8f872 100644 --- a/synth2.cc +++ b/synth2.cc @@ -1526,7 +1526,8 @@ bool NetProcTop::synth_async(Design*des) vector bitmasks (nex_set.size()); // Save links to the initial nex_out. These will be used later - // to detect floating mux inputs that need to be tied off. + // to detect floating part-substitute and mux inputs that need + // to be tied off. NetBus nex_in (scope(), nex_out.pin_count()); for (unsigned idx = 0 ; idx < nex_out.pin_count() ; idx += 1) connect(nex_in.pin(idx), nex_out.pin(idx)); @@ -1834,6 +1835,7 @@ bool NetCondit::synth_sync(Design*des, NetScope*scope, } delete expr_input; + #if 0 /* Detect the case that this is a *synchronous* set/reset. It is not asynchronous because we know the condition is not @@ -2042,7 +2044,8 @@ bool NetProcTop::synth_sync(Design*des) vector bitmasks (nex_set.size()); // Save links to the initial nex_d. These will be used later - // to detect floating mux inputs that need to be tied off. + // to detect floating part-substitute and mux inputs that need + // to be tied off. NetBus nex_in (scope(), nex_d.pin_count()); for (unsigned idx = 0 ; idx < nex_in.pin_count() ; idx += 1) connect(nex_in.pin(idx), nex_d.pin(idx)); @@ -2052,7 +2055,7 @@ bool NetProcTop::synth_sync(Design*des) for (unsigned idx = 0 ; idx < nex_q.pin_count() ; idx += 1) connect(nex_q.pin(idx), nex_set[idx].lnk); - // Connect the input later. + // Connect the D of the NetFF devices later. /* Synthesize the input to the DFF. */ bool negedge = false;