From f25b957006cbd71bde3f44a510f240326966b466 Mon Sep 17 00:00:00 2001 From: Prasad Joshi Date: Tue, 28 Jun 2011 16:43:21 +0100 Subject: [PATCH] Add support for variable of primitive data type 'bit' Verilog allows user to define variables of primitive types. The patch adds support for defining variables of type 'bit'. The data type 'bit' is the only primitive data type which supports defining ranges. Signed-off-by: Prasad Joshi --- parse.y | 6 ++++++ vvp/vpi_signal.cc | 1 + 2 files changed, 7 insertions(+) diff --git a/parse.y b/parse.y index 727a40286..0d152149d 100644 --- a/parse.y +++ b/parse.y @@ -605,6 +605,12 @@ block_item_decl if ($1) delete $1; } + | attribute_list_opt K_bit unsigned_signed_opt range_opt + register_variable_list ';' + { + pform_set_net_range($5, $4, $3, IVL_VT_BOOL); + if ($1) delete $1; + } /* Integer atom declarations are simpler in that they do not have all the trappings of a general variable declaration. All of that is implicit in the "integer" of the declaration. */ diff --git a/vvp/vpi_signal.cc b/vvp/vpi_signal.cc index 520b331b5..1c1542d01 100644 --- a/vvp/vpi_signal.cc +++ b/vvp/vpi_signal.cc @@ -515,6 +515,7 @@ struct __vpiSignal* vpip_signal_from_handle(vpiHandle ref) case vpiShortIntVar: case vpiIntVar: case vpiLongIntVar: + case vpiBitVar: return (struct __vpiSignal*)ref; default: