From edf112b9001a320cd7dfbcbd070905b3ff0c1a75 Mon Sep 17 00:00:00 2001
From: Cary R <cygcary@yahoo.com>
Date: Mon, 8 Dec 2014 20:54:04 -0800
Subject: [PATCH] Update all the vvp examples to work correctly

---
 vvp/examples/assign_reg.vvp |  71 ++++++--
 vvp/examples/copy.vvp       |  35 ++--
 vvp/examples/disable.vvp    |  46 ++---
 vvp/examples/edge.vvp       |  40 ++---
 vvp/examples/fork.vvp       |  27 +--
 vvp/examples/hello.vvp      |  26 +--
 vvp/examples/hello2.vvp     |  38 ++--
 vvp/examples/memory.vvp     | 344 ++++++++++++++++++++++--------------
 vvp/examples/set_reg.vvp    |  65 +++++--
 vvp/examples/sum.vvp        |  50 +++---
 vvp/examples/time.vvp       |  28 +--
 vvp/examples/vector.vvp     |  27 ++-
 12 files changed, 489 insertions(+), 308 deletions(-)

diff --git a/vvp/examples/assign_reg.vvp b/vvp/examples/assign_reg.vvp
index 7b787496a..4107272ad 100644
--- a/vvp/examples/assign_reg.vvp
+++ b/vvp/examples/assign_reg.vvp
@@ -1,12 +1,49 @@
+:ivl_version "0.10.0" "vec4-stack";
 :vpi_module "system";
 
+; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
 ;
-; This example demonstrates a simple blocking assignment to a
-; reg vector within a module.
+;    This program is free software; you can redistribute it and/or modify
+;    it under the terms of the GNU General Public License as published by
+;    the Free Software Foundation; either version 2 of the License, or
+;    (at your option) any later version.
 ;
+;    This program is distributed in the hope that it will be useful,
+;    but WITHOUT ANY WARRANTY; without even the implied warranty of
+;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;    GNU General Public License for more details.
+;
+;    You should have received a copy of the GNU General Public License along
+;    with this program; if not, write to the Free Software Foundation, Inc.,
+;    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+;
+; This example demonstrates a simple non-blocking assignment to a
+; reg vector within a module. It is similar to the code that the
+; following Verilog program would generate:
+;
+;    module main;
+;
+;       reg [7:0] test;
+;
+;       initial begin
+;          test <= #2 0;
+;          #3 $display("test = %b", test);
+;
+;          test <= #2 1;
+;          #1 $display("test = %b", test);
+;          #2 $display("test = %b", test);
+;
+;          test <= #2 2;
+;          #3 $display("test = %b", test);
+;
+;          test <= #2 3;
+;          #3 $display("test = %b", test);
+;       end
+;
+;    endmodule
 
 
-main    .scope module, "main" "main";
+main    .scope module, "main" "main" 0 0;
 
 ; This declares a "reg" data type named "test" in the current scope.
 ; The bit range is given for the purposes of VPI access. The range
@@ -14,28 +51,30 @@ main    .scope module, "main" "main";
 ; bit wide vector.
 test	.var	"test", 7 0;
 
-; The %assign/v0 opcode assigns a vector to the .var at the label,
-; with the given delay. The width of the vector from index register0.
+; The %assign/vec4 opcode assigns a vector to the .var at the label,
+; with the given absolute delay.
 
-T0	%ix/load 0, 8 ;  Set the width of the vector to 8.
-
-	%assign/v0	test, 2, 0 ;
+T0	%pushi/vec4 0, 0, 8;
+	%assign/vec4 test, 2;
 	%delay 3, 0;
-	%vpi_call 0 0 "$display", "test = %b", test;
+	%vpi_call 0 0 "$display", "test = %b", test {0 0 0};
 
-	%assign/v0	test, 2, 1 ;
+	%pushi/vec4 1, 0, 8;
+	%assign/vec4 test, 2;
 	%delay 1, 0;
-	%vpi_call 0 0 "$display", "test = %b", test;
+	%vpi_call 0 0 "$display", "test = %b", test {0 0 0};
 	%delay 2, 0;
-	%vpi_call 0 0 "$display", "test = %b", test;
+	%vpi_call 0 0 "$display", "test = %b", test {0 0 0};
 
-	%assign/v0	test, 2, 2 ;
+	%pushi/vec4 2, 0, 8;
+	%assign/vec4 test, 2;
 	%delay 3, 0;
-	%vpi_call 0 0 "$display", "test = %b", test;
+	%vpi_call 0 0 "$display", "test = %b", test {0 0 0};
 
-	%assign/v0	test, 2, 3 ;
+	%pushi/vec4 3, 0, 8;
+	%assign/vec4 test, 2;
 	%delay 3, 0;
-	%vpi_call 0 0 "$display", "test = %b", test;
+	%vpi_call 0 0 "$display", "test = %b", test {0 0 0};
 
 	%end;
 	.thread T0;
diff --git a/vvp/examples/copy.vvp b/vvp/examples/copy.vvp
index 097ad80cf..3e63b97b9 100644
--- a/vvp/examples/copy.vvp
+++ b/vvp/examples/copy.vvp
@@ -1,25 +1,24 @@
+:ivl_version "0.10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2008  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
 ;
-;    This source code is free software; you can redistribute it
-;    and/or modify it in source code form under the terms of the GNU
-;    General Public License as published by the Free Software
-;    Foundation; either version 2 of the License, or (at your option)
-;    any later version.
+;    This program is free software; you can redistribute it and/or modify
+;    it under the terms of the GNU General Public License as published by
+;    the Free Software Foundation; either version 2 of the License, or
+;    (at your option) any later version.
 ;
 ;    This program is distributed in the hope that it will be useful,
 ;    but WITHOUT ANY WARRANTY; without even the implied warranty of
 ;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ;    GNU General Public License for more details.
 ;
-;    You should have received a copy of the GNU General Public License
-;    along with this program; if not, write to the Free Software
-;    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-
+;    You should have received a copy of the GNU General Public License along
+;    with this program; if not, write to the Free Software Foundation, Inc.,
+;    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 
 ; This example is similar to the code that the following Verilog program
-; would make:
+; would generate:
 ;
 ;    module main;
 ;       reg a;
@@ -36,18 +35,20 @@
 ; properly. This is a very trivial functor propagation that is initiated
 ; by the %set instruction.
 
-main	.scope module, "main";
+
+main	.scope module, "main" "main" 0 0;
 
 V_main.a	.var "a", 0 0;
 V_main.b	.net "b", 0 0, V_main.a;
 
-code
-	%set/v V_main.a, 0, 1;
+code	%pushi/vec4 0, 0, 1;
+	%store/vec4 V_main.a, 0, 1;
 	%delay 1, 0;
-	%vpi_call 0 0 "$display", "a=%b, b=%b", V_main.a, V_main.b;
-	%set/v V_main.a, 1, 1;
+	%vpi_call 0 0 "$display", "a=%b, b=%b", V_main.a, V_main.b {0 0 0};
+	%pushi/vec4 1, 0, 1;
+	%store/vec4 V_main.a, 0, 1;
 	%delay 1, 0;
-	%vpi_call 0 0 "$display", "a=%b, b=%b", V_main.a, V_main.b;
+	%vpi_call 0 0 "$display", "a=%b, b=%b", V_main.a, V_main.b {0 0 0};
 	%end;
 
 	.thread	code;
diff --git a/vvp/examples/disable.vvp b/vvp/examples/disable.vvp
index 6de03383f..6ee6622c3 100644
--- a/vvp/examples/disable.vvp
+++ b/vvp/examples/disable.vvp
@@ -1,21 +1,21 @@
+:ivl_version "0.10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2008  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
 ;
-;    This source code is free software; you can redistribute it
-;    and/or modify it in source code form under the terms of the GNU
-;    General Public License as published by the Free Software
-;    Foundation; either version 2 of the License, or (at your option)
-;    any later version.
+;    This program is free software; you can redistribute it and/or modify
+;    it under the terms of the GNU General Public License as published by
+;    the Free Software Foundation; either version 2 of the License, or
+;    (at your option) any later version.
 ;
 ;    This program is distributed in the hope that it will be useful,
 ;    but WITHOUT ANY WARRANTY; without even the implied warranty of
 ;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ;    GNU General Public License for more details.
 ;
-;    You should have received a copy of the GNU General Public License
-;    along with this program; if not, write to the Free Software
-;    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+;    You should have received a copy of the GNU General Public License along
+;    with this program; if not, write to the Free Software Foundation, Inc.,
+;    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 
 
 ; This example is similar to the following Verilog code. The idea is
@@ -26,24 +26,24 @@
 ;
 ;    module main;
 ;       task test;
-;           begin
-;              #5 $display("FAILED...");
-;              $finish;
-;           end
+;          begin
+;             #5 $display("FAILED...");
+;             $finish;
+;          end
 ;       endtask
 ;
 ;       initial begin
-;           fork
-;               test;
-;               #1 disable test;
-;           join
-;           $display("PASSED");
+;          fork
+;             test;
+;             #1 disable test;
+;          join
+;          $display("PASSED");
 ;       end
 ;    endmodule
 ;
 
-S_main .scope module, "main";
-S_test .scope task, "test", S_main;
+S_main .scope module, "main" "main" 0 0;
+S_test .scope task, "test" "test" 0 0, 0 0 0, S_main;
 
 
 ; This code in the implementation of the thread that goes into the
@@ -52,8 +52,8 @@ S_test .scope task, "test", S_main;
     .scope S_test;
 T_0/1 ;
     %delay 5, 0;
-    %vpi_call 0 0 "$display", "FAILED -- thread wasn't disabled";
-    %vpi_call 0 0 "$finish";
+    %vpi_call 0 0 "$display", "FAILED -- thread wasn't disabled" {0 0 0};
+    %vpi_call 0 0 "$finish" {0 0 0};
     %end;
 
 ; This is the main thread. Fork the thread under test, delay for a
@@ -68,7 +68,7 @@ T_0 ;
     %disable S_test ; This is the statement that I'm testing.
 
     %join;
-    %vpi_call 0 0 "$display", "PASSED";
+    %vpi_call 0 0 "$display", "PASSED" {0 0 0};
     %end;
 
     .thread T_0;
diff --git a/vvp/examples/edge.vvp b/vvp/examples/edge.vvp
index 906f7981b..91073dcc1 100644
--- a/vvp/examples/edge.vvp
+++ b/vvp/examples/edge.vvp
@@ -1,53 +1,53 @@
+:ivl_version "0.10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2008  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
 ;
-;    This source code is free software; you can redistribute it
-;    and/or modify it in source code form under the terms of the GNU
-;    General Public License as published by the Free Software
-;    Foundation; either version 2 of the License, or (at your option)
-;    any later version.
+;    This program is free software; you can redistribute it and/or modify
+;    it under the terms of the GNU General Public License as published by
+;    the Free Software Foundation; either version 2 of the License, or
+;    (at your option) any later version.
 ;
 ;    This program is distributed in the hope that it will be useful,
 ;    but WITHOUT ANY WARRANTY; without even the implied warranty of
 ;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ;    GNU General Public License for more details.
 ;
-;    You should have received a copy of the GNU General Public License
-;    along with this program; if not, write to the Free Software
-;    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-
+;    You should have received a copy of the GNU General Public License along
+;    with this program; if not, write to the Free Software Foundation, Inc.,
+;    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 
 ; This example tests the operation of a simple posedge event. The module
 ; that would generate code like this would be:
 ;
 ;    module main;
-;        reg a;
+;       reg a;
 ;
-;        initial begin
+;       initial begin
 ;          a = 0;
 ;          #1 a = 1;
-;        end
+;       end
 ;
-;        always @(posedge a) $display("Got a posedge.");
+;       always @(posedge a) $display("Got a posedge.");
 ;
 ;    endmodule
-;
 
-main	.scope module, "main";
+
+main	.scope module, "main" "main" 0 0;
 
 V_main.a	.var "a", 0 0;
 V_main.b	.event posedge, V_main.a;
 
-code
-	%set/v V_main.a, 0, 1;
+code	%pushi/vec4 0, 0, 1;
+	%store/vec4 V_main.a, 0, 1;
 	%delay 1, 0;
-	%set/v V_main.a, 1, 1;
+	%pushi/vec4 1, 0, 1;
+	%store/vec4 V_main.a, 0, 1;
 	%end;
 	.thread	code;
 
 loop	%wait V_main.b;
-	%vpi_call 0 0 "$display", "Got a posedge.";
+	%vpi_call 0 0 "$display", "Got a posedge." {0 0 0};
 	%jmp loop;
 	.thread loop;
 :file_names 2;
diff --git a/vvp/examples/fork.vvp b/vvp/examples/fork.vvp
index 050134fc3..6bf42f051 100644
--- a/vvp/examples/fork.vvp
+++ b/vvp/examples/fork.vvp
@@ -1,33 +1,34 @@
+:ivl_version "0.10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2008  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
 ;
-;    This source code is free software; you can redistribute it
-;    and/or modify it in source code form under the terms of the GNU
-;    General Public License as published by the Free Software
-;    Foundation; either version 2 of the License, or (at your option)
-;    any later version.
+;    This program is free software; you can redistribute it and/or modify
+;    it under the terms of the GNU General Public License as published by
+;    the Free Software Foundation; either version 2 of the License, or
+;    (at your option) any later version.
 ;
 ;    This program is distributed in the hope that it will be useful,
 ;    but WITHOUT ANY WARRANTY; without even the implied warranty of
 ;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ;    GNU General Public License for more details.
 ;
-;    You should have received a copy of the GNU General Public License
-;    along with this program; if not, write to the Free Software
-;    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+;    You should have received a copy of the GNU General Public License along
+;    with this program; if not, write to the Free Software Foundation, Inc.,
+;    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 
 ; This sample demonstrates the behavior of %fork and %join.
 
-S_main .scope module, "main";
 
-child	%vpi_call 0 0 "$display", "I'm a child";
+S_main .scope module, "main" "main" 0 0;
+
+child	%vpi_call 0 0 "$display", "I'm a child" {0 0 0};
 	%end;
 
 parent	%fork	child, S_main;
-	%vpi_call 0 0 "$display", "I'm a parent";
+	%vpi_call 0 0 "$display", "I'm a parent" {0 0 0};
 	%join;
-	%vpi_call 0 0 "$display", "reaped";
+	%vpi_call 0 0 "$display", "Reaped child" {0 0 0};
 	%end;
 
 	.thread parent;
diff --git a/vvp/examples/hello.vvp b/vvp/examples/hello.vvp
index 4d9dd98e6..79fe3c10c 100644
--- a/vvp/examples/hello.vvp
+++ b/vvp/examples/hello.vvp
@@ -1,37 +1,37 @@
+:ivl_version "0.10.0" "vec4-stack";
 :vpi_module "system";
 
 ; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
 ;
-;    This source code is free software; you can redistribute it
-;    and/or modify it in source code form under the terms of the GNU
-;    General Public License as published by the Free Software
-;    Foundation; either version 2 of the License, or (at your option)
-;    any later version.
+;    This program is free software; you can redistribute it and/or modify
+;    it under the terms of the GNU General Public License as published by
+;    the Free Software Foundation; either version 2 of the License, or
+;    (at your option) any later version.
 ;
 ;    This program is distributed in the hope that it will be useful,
 ;    but WITHOUT ANY WARRANTY; without even the implied warranty of
 ;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ;    GNU General Public License for more details.
 ;
-;    You should have received a copy of the GNU General Public License
-;    along with this program; if not, write to the Free Software
-;    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+;    You should have received a copy of the GNU General Public License along
+;    with this program; if not, write to the Free Software Foundation, Inc.,
+;    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 
 
 ; This example is similar to the code that the following Verilog program
-; would make:
+; would generate:
 ;
 ;    module main;
 ;       initial $display("Hello, World.");
 ;    endmodule
 ;
 ; This tests that a simple %vpi_call works properly. This is very nearly
-; the mode trivial VVP source file that can generate any output.
+; the most trivial VVP source file that can generate any output.
 
-main	.scope module, "main";
 
-code
-	%vpi_call 0 0 "$display", "Hello, World." {0 0 0};
+main	.scope module, "main" "main" 0 0;
+
+code	%vpi_call 0 0 "$display", "Hello, World." {0 0 0};
 	%end;
 	.thread	code;
 :file_names 2;
diff --git a/vvp/examples/hello2.vvp b/vvp/examples/hello2.vvp
index e60a543b3..0750f249b 100644
--- a/vvp/examples/hello2.vvp
+++ b/vvp/examples/hello2.vvp
@@ -1,32 +1,32 @@
+:ivl_version "0.10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2008  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
 ;
-;    This source code is free software; you can redistribute it
-;    and/or modify it in source code form under the terms of the GNU
-;    General Public License as published by the Free Software
-;    Foundation; either version 2 of the License, or (at your option)
-;    any later version.
+;    This program is free software; you can redistribute it and/or modify
+;    it under the terms of the GNU General Public License as published by
+;    the Free Software Foundation; either version 2 of the License, or
+;    (at your option) any later version.
 ;
 ;    This program is distributed in the hope that it will be useful,
 ;    but WITHOUT ANY WARRANTY; without even the implied warranty of
 ;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ;    GNU General Public License for more details.
 ;
-;    You should have received a copy of the GNU General Public License
-;    along with this program; if not, write to the Free Software
-;    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+;    You should have received a copy of the GNU General Public License along
+;    with this program; if not, write to the Free Software Foundation, Inc.,
+;    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 
 ; This example slightly extends the hello.vvp example by adding the
 ; set and display of a reg variable. The Verilog source that would
 ; make this might be:
 ;
 ;    module main;
-;        reg [3:0] value1;
-;        initial begin
-;           value1 = 1;
-;           $display("value = %b", value1);
-;        end
+;       reg [3:0] value1;
+;       initial begin
+;          value1 = 1;
+;          $display("value = %b", value1);
+;       end
 ;    endmodule
 ;
 ; Notice that the var "value1" is placed into the "main" scope simply
@@ -34,14 +34,15 @@
 ; notice that the Vmain.value1 label is automatically converted to a
 ; vpiHandle by the compiler when the %vpi_call statement is compiled.
 
-Smain    .scope module, "main";
+
+Smain    .scope module, "main" "main" 0 0;
 
 Vmain.value1	.var "value1", 3 0;
 
-T00	%movi 8, 1, 4; Load a 4 bit value (1) into location 8.
-	%set/v Vmain.value1, 8, 4;
+T00	%pushi/vec4 1, 0, 4;  Push a 4 bit value (1) on the stack
+        %store/vec4 Vmain.value1, 0, 4;
 
-	%vpi_call 0 0 "$display", "value = %b", Vmain.value1;
+	%vpi_call 0 0 "$display", "value = %b", Vmain.value1 {0 0 0};
 
 	%end;
 
@@ -49,4 +50,3 @@ T00	%movi 8, 1, 4; Load a 4 bit value (1) into location 8.
 :file_names 2;
     "N/A";
     "<interactive>";
-
diff --git a/vvp/examples/memory.vvp b/vvp/examples/memory.vvp
index fa08023d8..65e700d68 100644
--- a/vvp/examples/memory.vvp
+++ b/vvp/examples/memory.vvp
@@ -1,40 +1,33 @@
+:ivl_version "0.10.0" "vec4-stack";
 :vpi_module "system";
 
-
-; IMPORTANT NOTE:
-;
-; This example uses constructs that are no longer supported. It will
-; not run with the current vvp implementation!
-
-
-; Copyright (c) 2001-2008  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
 ; Copyright (c) 2001  Stephan Boettcher <stephan@nevis.columbia.edu>
 ;
-;    This source code is free software; you can redistribute it
-;    and/or modify it in source code form under the terms of the GNU
-;    General Public License as published by the Free Software
-;    Foundation; either version 2 of the License, or (at your option)
-;    any later version.
+;    This program is free software; you can redistribute it and/or modify
+;    it under the terms of the GNU General Public License as published by
+;    the Free Software Foundation; either version 2 of the License, or
+;    (at your option) any later version.
 ;
 ;    This program is distributed in the hope that it will be useful,
 ;    but WITHOUT ANY WARRANTY; without even the implied warranty of
 ;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ;    GNU General Public License for more details.
 ;
-;    You should have received a copy of the GNU General Public License
-;    along with this program; if not, write to the Free Software
-;    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+;    You should have received a copy of the GNU General Public License along
+;    with this program; if not, write to the Free Software Foundation, Inc.,
+;    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 
 ; This sample demonstrates memory,  also including index register
 ; arithmetic.  And a memory write port
 
-main	.scope	"example";
+main	.scope module, "example" "example" 0 0;
 
 ;;; Make a memory.
 ;
 ;   reg [8:2] memory[5:27];
 
-memory	.mem	"memory", 8,2, 27,5 ;
+memory	.array	"memory", 27 5, 8 2;
 
 ;;; The word width is 7 bits [8:2].
 ;;; The memory size is 23 words, 5..27.
@@ -49,42 +42,159 @@ memory	.mem	"memory", 8,2, 27,5 ;
 ;   wire [5:0] d = memory[a][8:3];
 ;   reg [6:0]  m;
 
-a	.var	"a", 4,0;
-we	.var	"we", 0,0;
+a	.var	"a", 4 0;
+we	.var	"we", 0 0;
 wclk	.event	"wclk";
-di	.var	"di", 5,0;
-d	.net	"d", 5,0, mem[0],mem[1],mem[2],mem[3],mem[4],mem[5];
-mem	.mem/port memory, 6,1,
-		5, a[0],a[1],a[2],a[3],a[4],
-		wclk, we, di[0],di[1],di[2],di[3],di[4],di[5];
-m	.var	"m", 6,0;
+di	.var	"di", 5 0;
+d	.net	"d", 5 0, m_part;
+mem_prt	.array/port memory, mem_idx;
+; The memory index is normalized (a-5) using one extra bit to allow negative
+; (wrapped) values to be out of range.
+mem_idx	.arith/sub 6, a_pad, C4<000101>;
+a_pad	.concat [5 1 0 0], a, C4<0>;
+; Select 6 bits from the memory port starting at the second bit.
+m_part	.part mem_prt, 1, 6;
+m	.var	"m", 6 0;
 
 ;;; The data port mem[] does not connect to the LSB of the memory.
 
-;;; Initialize some part of the memory.	 Starting at memory bit [20],
-;;; which is in the middle of the third memory word, memory[7].	 The
-;;; memory words occupy 8 bits each, that is 7 rounded up to the next
-;;; multiple of 4.
+;;; Initialize the last part of the memory. Starting at the middle of the
+;;; the third memory word, memory[7] bit 6.
+;
+;   initial begin
+;      memory[7][8:6] = 8'h55;
+;      memory[8] = 8'h00;
+;      memory[9] = 8'h00;
+;      memory[10] = 8'h50;
+;      memory[11] = 8'h05;
+;      memory[12] = 8'h05;
+;      memory[13] = 8'h50;
+;      memory[14] = 8'h05;
+;      memory[15] = 8'h05;
+;      memory[16] = 8'h00;
+;      memory[17] = 8'h00;
+;      memory[18] = 8'h00;
+;      memory[19] = 8'h01;
+;      memory[20] = 8'h00;
+;      memory[21] = 8'h04;
+;      memory[22] = 8'h00;
+;      memory[23] = 8'h10;
+;      memory[24] = 8'h00;
+;      memory[25] = 8'h40;
+;      memory[26] = 8'h01;
+;      memory[27] = 8'h00;
+;   end
 
-;;; Four bits per byte.	 Word fill bits are included.  Commas are
-;;; optional, there may be a comma after the last byte.
+	.scope main;
+mem_init ;
+	%pushi/vec4 5, 0, 3; value to store
+	%ix/load 4, 2, 0; word index (7 -> zero based)
+	%ix/load 5, 4, 0; bit index (6 -> zero based)
+        %flag_set/imm 4, 0; the index values are defined
+	%store/vec4a memory, 4, 5;
 
-	.mem/init memory[20],
-		     0x55
-		0x00 0x00
-		0x50 0x05
-		0x05 0x50
-		0x05 0x05
-		0x00 0x00
-		0x00 0x01
-		0x00 0x04
-		0x00 0x10
-		0x00 0x40
-		0x01 0x00
-		0x04,0x00,
-		0x10,0x00,
-		0x40,0x00,
-		;
+	%pushi/vec4 0, 0, 7; value to store
+	%ix/load 4, 3, 0; word index (8 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 0, 0, 7; value to store
+	%ix/load 4, 4, 0; word index (9 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 80, 0, 7; value to store
+	%ix/load 4, 5, 0; word index (10 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 5, 0, 7; value to store
+	%ix/load 4, 6, 0; word index (11 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 5, 0, 7; value to store
+	%ix/load 4, 7, 0; word index (12 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 80, 0, 7; value to store
+	%ix/load 4, 8, 0; word index (13 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 5, 0, 7; value to store
+	%ix/load 4, 9, 0; word index (14 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 5, 0, 7; value to store
+	%ix/load 4, 10, 0; word index (15 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 0, 0, 7; value to store
+	%ix/load 4, 11, 0; word index (16 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 0, 0, 7; value to store
+	%ix/load 4, 12, 0; word index (17 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 0, 0, 7; value to store
+	%ix/load 4, 13, 0; word index (18 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 1, 0, 7; value to store
+	%ix/load 4, 14, 0; word index (19 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 0, 0, 7; value to store
+	%ix/load 4, 15, 0; word index (20 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 4, 0, 7; value to store
+	%ix/load 4, 16, 0; word index (21 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 0, 0, 7; value to store
+	%ix/load 4, 17, 0; word index (22 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 16, 0, 7; value to store
+	%ix/load 4, 18, 0; word index (23 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 0, 0, 7; value to store
+	%ix/load 4, 19, 0; word index (24 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 64, 0, 7; value to store
+	%ix/load 4, 20, 0; word index (25 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 1, 0, 7; value to store
+	%ix/load 4, 21, 0; word index (26 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%pushi/vec4 0, 0, 7; value to store
+	%ix/load 4, 22, 0; word index (27 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%store/vec4a memory, 4, 0;
+
+	%end;
+	.thread mem_init;
 
 ;;; Run through the addresses and display the data output.
 ;
@@ -97,33 +207,23 @@ m	.var	"m", 6,0;
 
 	.scope main;
 always ;
-	%delay	5;
+	%delay	5, 0;
 
-	%vpi_call "$display", "a:%b d:%b", a, d;
+	%vpi_call 0 0 "$display", "a:%b d:%b", a, d {0 0 0};
 
-	%set	wclk, 0;
+	%event	wclk;
 
-	%delay	5;
+	%delay	5, 0;
 
-	%load	10, a[0];
-	%load	11, a[1];
-	%load	12, a[2];
-	%load	13, a[3];
-	%load	14, a[4];
-	%mov	20, 1, 1;
-	%mov	21, 0, 4;
-	%add	10, 20, 5;
-	%assign	a[0], 0, 10;
-	%assign a[1], 0, 11;
-	%assign a[2], 0, 12;
-	%assign a[3], 0, 13;
-	%assign a[4], 0, 14;
+	%load/vec4 a;
+	%addi 1, 0, 5;
+	%assign/vec4 a, 0;
 
 	%jmp	always;
 	.thread	always;
 
-;;; Initialize a[], run some cycles, overwrite a memory word, run a
-;;; bit more, read a memory word, finish.
+;;; Initialize the variables, run some cycles, overwrite a memory word, run
+;;; a bit more, read a memory word, finish.
 ;
 ;   initial
 ;     begin
@@ -149,78 +249,58 @@ always ;
 
 	.scope	main;
 initial ;
-	%set	we, 0;
-	%set	di[0], 0;
-	%set	di[1], 1;
-	%set	di[2], 2;
-	%set	di[3], 3;
-	%set	di[4], 0;
-	%set	di[5], 1;
-	%set	a[0], 0;
-	%set	a[1], 0;
-	%set	a[2], 0;
-	%set	a[3], 0;
-	%set	a[4], 0;
+	%pushi/vec4 0, 0, 1;
+	%store/vec4 we, 0, 1;
 
-	%delay	220;
-	%vpi_call "$readmemh", "memory.hex", memory;
-	%delay	30;
-	%set	we, 1;
-	%delay	5;
-	%vpi_call "$display", "write to a=%b", a;
-	%delay	5;
-	%set	we, 0;
-	%delay	60;
+	%pushi/vec4 38, 12, 6;
+	%store/vec4 di, 0, 6;
+
+	%pushi/vec4 0, 0, 5;
+	%store/vec4 a, 0, 5;
+
+	%delay	220, 0;
+
+	%vpi_call 0 0 "$readmemh", "memory.hex", memory {0 0 0};
+
+	%delay	30, 0;
+
+	%pushi/vec4 1, 0, 1;
+	%store/vec4 we, 0, 1;
+
+	%delay	5, 0;
+
+	%vpi_call 0 0 "$display", "write to a=%b", a {0 0 0};
+
+	%delay	5, 0;
+
+	%pushi/vec4 0, 0, 1;
+	%store/vec4 we, 0, 1;
+
+	%delay	60, 0;
 
 ;;; Memories are indexed by index register 3.  The index register
-;;; points to the bit position in the memory.  Each memory word
-;;; occupies a multiple of 4 bits.  Bit position zero is the LSB of
-;;; the first memory word, here: memory[5][2].
+;;; points to the zero based word position in the memory.
 
-	%ix/load 3, 23 ;	memory word index
-	%ix/sub	 3,  5 ;	minus memory root index
-	%ix/mul	 3,  8 ;	times memory word size (rounded up)
-	%assign/m memory, 0, 1;
-	%ix/add	 3, 1 ;		next bit
-	%assign/m memory, 0, 0;
-	%ix/add	 3, 1 ;
-	%assign/m memory, 0, 3;
-	%ix/add	 3, 1 ;
-	%assign/m memory, 0, 2;
-	%ix/add	 3, 1 ;
-	%assign/m memory, 0, 1;
-	%ix/add	 3, 1 ;
-	%assign/m memory, 0, 0;
-	%ix/add	 3, 1 ;
-	%assign/m memory, 0, 0;
+        %pushi/vec4 25, 12, 7;
+	%ix/load 3, 18, 0; memory word index (23 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%assign/vec4/a/d memory, 0, 0;
 
-	%delay	320;
+	%delay	320, 0;
 
-	%ix/load 3,  32 ;	precomputed memory bit index
-	%load/m	 10, memory;
-	%set	 m[0], 10;
-	%ix/add	 3, 1 ;
-	%load/m	 10, memory;
-	%set	 m[1], 10;
-	%ix/add	 3, 1 ;
-	%load/m	 10, memory;
-	%set	 m[2], 10;
-	%ix/add	 3, 1 ;
-	%load/m	 10, memory;
-	%set	 m[3], 10;
-	%ix/add	 3, 1 ;
-	%load/m	 10, memory;
-	%set	 m[4], 10;
-	%ix/add	 3, 1 ;
-	%load/m	 10, memory;
-	%set	 m[5], 10;
-	%ix/add	 3, 1 ;
-	%load/m	 10, memory;
-	%set	 m[6], 10;
-	%vpi_call "$display", "memory[9]=%b", m;
+	%ix/load 4, 4, 0; memory word index (9 -> zero based)
+        %flag_set/imm 4, 0; the index value is defined
+	%load/vec4a memory, 4;
+	%store/vec4 m, 0, 7;
 
-	#1;
-	%vpi_call "$finish";
+	%vpi_call 0 0 "$display", "memory[9]=%b", m {0 0 0};
+
+	%delay 1, 0;
+
+	%vpi_call 0 0 "$finish" {0 0 0};
 
 	%end;
 	.thread initial;
+:file_names 2;
+    "N/A";
+    "<interactive>";
diff --git a/vvp/examples/set_reg.vvp b/vvp/examples/set_reg.vvp
index 9f3bb4803..151a9a8bd 100644
--- a/vvp/examples/set_reg.vvp
+++ b/vvp/examples/set_reg.vvp
@@ -1,35 +1,72 @@
+:ivl_version "0.10.0" "vec4-stack";
 :vpi_module "system";
 
+; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
+;
+;    This program is free software; you can redistribute it and/or modify
+;    it under the terms of the GNU General Public License as published by
+;    the Free Software Foundation; either version 2 of the License, or
+;    (at your option) any later version.
+;
+;    This program is distributed in the hope that it will be useful,
+;    but WITHOUT ANY WARRANTY; without even the implied warranty of
+;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;    GNU General Public License for more details.
+;
+;    You should have received a copy of the GNU General Public License along
+;    with this program; if not, write to the Free Software Foundation, Inc.,
+;    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+
+
+; This example is similar to the code that the following Verilog program
+; would generate:
+;
+;    module main;
+;       reg [7:0] test;
+;
+;       initial begin
+;          test = 8'h00;
+;          $display("test = %b", test);
+;          test = 8'hff;
+;          $display("test = %b", test);
+;          test = 8'hzz;
+;          $display("test = %b", test);
+;          test = 8'hxx;
+;          $display("test = %b", test);
+;       end
+;    endmodule
 ;
 ; This example demonstrates a simple blocking assignment to a
 ; reg vector within a module.
-;
 
 
-main    .scope module, "main" "main";
+main    .scope module, "main" "main" 0 0;
 
 ; This declares a "reg" data type named "test" in the current scope.
 ; The bit range is given for the purposes of VPI access. The range
 ; corresponds to the declaration "reg [7:0] test", so leads to an 8
 ; bit wide vector.
+
 test	.var	"test", 7 0;
 
-; The %set/v opcode writes a value to the target .var vector. The
-; first operand is the label of the .var object. The second and
-; third operands are the base and width of the bit set that is to
-; be made into the vector to write.
+; Push various 8 bit values to the stack, save them to the variable and
+; then print the value of the variable.
 
-T0	%set/v	test, 0, 8 ;
-	%vpi_call 0 0 "$display", "test = %b", test;
+T0	%pushi/vec4 0, 0, 8;  Push 8 bits of 0
+	%store/vec4 test, 0, 8;
+	%vpi_call 0 0 "$display", "test = %b", test {0 0 0};
 
-	%set/v	test, 1, 8 ;
-	%vpi_call 0 0 "$display", "test = %b", test;
+	%pushi/vec4 255, 0, 8;  Push 8 bits of 1
+	%store/vec4 test, 0, 8;
+	%vpi_call 0 0 "$display", "test = %b", test {0 0 0};
 
-	%set/v	test, 2, 8 ;
-	%vpi_call 0 0 "$display", "test = %b", test;
+	%pushi/vec4 0, 255, 8;  Push 8 bits of z
+	%store/vec4 test, 0, 8;
+	%vpi_call 0 0 "$display", "test = %b", test {0 0 0};
 
-	%set/v	test, 3, 8 ;
-	%vpi_call 0 0 "$display", "test = %b", test;
+	%pushi/vec4 255, 255, 8;  Push 8 bits of x
+	%store/vec4 test, 0, 8;
+	%vpi_call 0 0 "$display", "test = %b", test {0 0 0};
 
 	%end;
 	.thread T0;
diff --git a/vvp/examples/sum.vvp b/vvp/examples/sum.vvp
index 32d03b0f9..e436381fa 100644
--- a/vvp/examples/sum.vvp
+++ b/vvp/examples/sum.vvp
@@ -1,34 +1,35 @@
+:ivl_version "0.10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2008  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
 ;
-;    This source code is free software; you can redistribute it
-;    and/or modify it in source code form under the terms of the GNU
-;    General Public License as published by the Free Software
-;    Foundation; either version 2 of the License, or (at your option)
-;    any later version.
+;    This program is free software; you can redistribute it and/or modify
+;    it under the terms of the GNU General Public License as published by
+;    the Free Software Foundation; either version 2 of the License, or
+;    (at your option) any later version.
 ;
 ;    This program is distributed in the hope that it will be useful,
 ;    but WITHOUT ANY WARRANTY; without even the implied warranty of
 ;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ;    GNU General Public License for more details.
 ;
-;    You should have received a copy of the GNU General Public License
-;    along with this program; if not, write to the Free Software
-;    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+;    You should have received a copy of the GNU General Public License along
+;    with this program; if not, write to the Free Software Foundation, Inc.,
+;    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 
-; This example shows how to wire up a simple adder. The code below is
-; like what might be generated from the Verilog:
+
+; This example shows how to wire a simple adder. The code below is like what
+; would be generated from the following Verilog program:
 ;
 ;    module main;
-;      reg [3:0] A, B;
-;      wire [3:0] Q = A + B;
+;       reg [3:0] A, B;
+;       wire [3:0] Q = A + B;
 ;
-;      initial begin
-;        A = 2;
-;        B = 3;
-;        #1 $display("%b  %b = %b", A, B, Q);
-;      end
+;       initial begin
+;          A = 2;
+;          B = 3;
+;          #1 $display("%b + %b = %b", A, B, Q);
+;       end
 ;    endmodule
 ;
 ; Notice the use of the .arith/sum statement, including the specification
@@ -36,7 +37,7 @@
 ; passed to the statement.
 
 
-S_main .scope module, "main";
+S_main .scope module, "main" "main" 0 0;
 
 A    .var	"A", 3 0;
 B    .var	"B", 3 0;
@@ -44,15 +45,14 @@ Q    .net	"Q", 3 0, add;
 
 add  .arith/sum	4, A, B;
 
-
-start	%movi 8, 2, 4; Load a 4 bit value (2) into location 8
-	%set/v	A, 8, 4;
-	%movi 8, 3, 4; Ditto except the value is 3
-	%set/v	B, 8, 4;
+start	%pushi/vec4 2, 0, 4;  Push a 4 bit value (2) on the stack
+	%store/vec4 A, 0, 4;
+	%pushi/vec4 3, 0, 4;  Ditto except the value is 3
+	%store/vec4 B, 0, 4;
 
 	%delay	1, 0;
 
-	%vpi_call 0 0 "$display", "%b + %b == %b", A, B, Q;
+	%vpi_call 0 0 "$display", "%b + %b == %b", A, B, Q {0 0 0};
 	%end;
 	.thread start;
 :file_names 2;
diff --git a/vvp/examples/time.vvp b/vvp/examples/time.vvp
index f96d00654..33b864011 100644
--- a/vvp/examples/time.vvp
+++ b/vvp/examples/time.vvp
@@ -1,25 +1,25 @@
+:ivl_version "0.10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2008  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
 ;
-;    This source code is free software; you can redistribute it
-;    and/or modify it in source code form under the terms of the GNU
-;    General Public License as published by the Free Software
-;    Foundation; either version 2 of the License, or (at your option)
-;    any later version.
+;    This program is free software; you can redistribute it and/or modify
+;    it under the terms of the GNU General Public License as published by
+;    the Free Software Foundation; either version 2 of the License, or
+;    (at your option) any later version.
 ;
 ;    This program is distributed in the hope that it will be useful,
 ;    but WITHOUT ANY WARRANTY; without even the implied warranty of
 ;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ;    GNU General Public License for more details.
 ;
-;    You should have received a copy of the GNU General Public License
-;    along with this program; if not, write to the Free Software
-;    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+;    You should have received a copy of the GNU General Public License along
+;    with this program; if not, write to the Free Software Foundation, Inc.,
+;    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 
 
 ; This example is similar to the code that the following Verilog program
-; would make:
+; would generate:
 ;
 ;    module main;
 ;       initial #45 $display("Hello, Clock: ", $time);
@@ -28,11 +28,11 @@
 ; This tests that the special $time symbol references the vpiHandle for
 ; the system time.
 
-main	.scope module, "main";
 
-code
-	%delay 45, 0;
-	%vpi_call 0 0 "$display", "Hello, Clock: ", $time;
+main	.scope module, "main" "main" 0 0;
+
+code	%delay 45, 0;
+	%vpi_call 0 0 "$display", "Hello, Clock: ", $time {0 0 0};
 	%end;
 	.thread	code;
 :file_names 2;
diff --git a/vvp/examples/vector.vvp b/vvp/examples/vector.vvp
index 8e249d098..2cf37101b 100644
--- a/vvp/examples/vector.vvp
+++ b/vvp/examples/vector.vvp
@@ -1,8 +1,31 @@
+:ivl_version "0.10.0" "vec4-stack";
 :vpi_module "system";
 
-main	.scope module, "main";
+;    This program is free software; you can redistribute it and/or modify
+;    it under the terms of the GNU General Public License as published by
+;    the Free Software Foundation; either version 2 of the License, or
+;    (at your option) any later version.
+;
+;    This program is distributed in the hope that it will be useful,
+;    but WITHOUT ANY WARRANTY; without even the implied warranty of
+;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;    GNU General Public License for more details.
+;
+;    You should have received a copy of the GNU General Public License along
+;    with this program; if not, write to the Free Software Foundation, Inc.,
+;    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 
-T0	%vpi_call 0 0 "$display", "Display the number: %b", 5'b0zx1;
+; This example is similar to the code that the following Verilog program
+; would generate:
+;
+;    module main;
+;       initial $display("Display the number: %b", 5'b0zx1);
+;    endmodule
+
+
+main	.scope module, "main" "main" 0 0;
+
+T0	%vpi_call 0 0 "$display", "Display the number: %b", 5'b0zx1 {0 0 0};
 	%end;
 	.thread T0;
 :file_names 2;