From eceb48e5d61677d053270292806e58fbd9b9973d Mon Sep 17 00:00:00 2001 From: Cary R Date: Wed, 16 Jul 2025 22:37:04 -0700 Subject: [PATCH] Add better error messages for output port elaboration issues --- elab_net.cc | 18 +++++++++++++----- elaborate.cc | 16 +++++++++++----- ivtest/gold/br_gh1222.gold | 16 +++++++++------- ivtest/gold/br_gh127a.gold | 4 ++-- ivtest/gold/br_gh127b.gold | 4 ++-- ivtest/gold/br_gh127c.gold | 4 ++-- ivtest/gold/br_gh127d.gold | 4 ++-- ivtest/gold/br_gh127e.gold | 4 ++-- ivtest/gold/br_gh127f.gold | 4 ++-- ivtest/gold/br_gh939-iverilog-stderr.gold | 4 ++-- ivtest/gold/br_gh956a.gold | 9 +++++++++ ivtest/gold/br_gh956b-fsv.gold | 9 +++++++++ ivtest/gold/br_gh956b.gold | 9 +++++++++ ivtest/gold/pr1833024.gold | 22 +++++++++++++--------- ivtest/gold/pr1866215.gold | 8 ++++---- ivtest/gold/pr1866215b.gold | 8 ++++---- ivtest/gold/pr3190941.gold | 4 ++-- ivtest/ivltests/br_gh956a.v | 15 +++++++++++++++ ivtest/ivltests/br_gh956b.v | 11 +++++++++++ ivtest/regress-fsv.list | 2 ++ ivtest/regress-vlg.list | 2 ++ 21 files changed, 127 insertions(+), 50 deletions(-) create mode 100644 ivtest/gold/br_gh956a.gold create mode 100644 ivtest/gold/br_gh956b-fsv.gold create mode 100644 ivtest/gold/br_gh956b.gold create mode 100644 ivtest/ivltests/br_gh956a.v create mode 100644 ivtest/ivltests/br_gh956b.v diff --git a/elab_net.cc b/elab_net.cc index 077bc1189..7e1174e2d 100644 --- a/elab_net.cc +++ b/elab_net.cc @@ -581,12 +581,20 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope, // Don't allow registers as assign l-values. if (sig->type() == NetNet::REG) { - cerr << get_fileline() << ": error: variable " << sig->name() - << "; cannot be driven by a primitive or continuous assignment"; - if(gn_var_can_be_uwire()) { - cerr << " with non-default strength"; + cerr << get_fileline() << ": error: Variable '" << sig->name() + << "' cannot be driven by a "; + if (var_allowed_in_sv) cerr << "continuous assignment/module"; + else cerr << "primitive"; + if (gn_var_can_be_uwire()) { + cerr << " or continuous assignment with non-default strength." << endl; + } else { + cerr << "." << endl; + if (var_allowed_in_sv) { + cerr << get_fileline() << ": : " + << "This is allowed when SystemVerilog is enabled." + << endl; + } } - cerr << "." << endl; des->errors += 1; return nullptr; } diff --git a/elaborate.cc b/elaborate.cc index 2b5765a18..60aab22a6 100644 --- a/elaborate.cc +++ b/elaborate.cc @@ -782,7 +782,13 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const // The only way this should return zero is if an error // happened, so for that case just return. - if (lval_sigs[idx] == 0) return; + if (lval_sigs[idx] == 0) { + cerr << get_fileline() << ": error: " + << "Failed to elaborate primitive output expression " + << scope_path(scope) << "." << *pin(idx) << "." << endl; + des->errors += 1; + return; + } // For now, assume all the outputs are the same width. ivl_assert(*this, idx == 0 || lval_sigs[idx]->vector_width() == lval_sigs[0]->vector_width()); @@ -1779,12 +1785,12 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const sig = pins[idx]->elaborate_lnet(des, scope, true); if (sig == 0) { cerr << pins[idx]->get_fileline() << ": error: " - << "Output port expression must support " + << "Output port expression must support a " << "continuous assignment." << endl; cerr << pins[idx]->get_fileline() << ": : Port " << (idx+1) << " (" << port_name << ") of " << rmod->mod_name() << " is connected to " - << *pins[idx] << endl; + << scope_path(scope) << "." << *pins[idx] << endl; des->errors += 1; continue; } @@ -1916,9 +1922,9 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const } cerr << get_fileline() << ": warning: Port " << (idx+1) - << " (" << port_name << ") of " + << " (" << port_name << ") of module " << type_ << " expects " << prts_vector_width << - " bits, got " << sig->vector_width() << "." << endl; + " bit(s), given " << sig->vector_width() << "." << endl; // Delete this when inout ports pad correctly. if (ptype == NetNet::PINOUT) { diff --git a/ivtest/gold/br_gh1222.gold b/ivtest/gold/br_gh1222.gold index 3bd179e7d..92ec72be1 100644 --- a/ivtest/gold/br_gh1222.gold +++ b/ivtest/gold/br_gh1222.gold @@ -1,7 +1,9 @@ -./ivltests/br_gh1222.v:6: error: variable rout_ca1; cannot be driven by a primitive or continuous assignment with non-default strength. -./ivltests/br_gh1222.v:6: error: variable rout_ca2; cannot be driven by a primitive or continuous assignment with non-default strength. -./ivltests/br_gh1222.v:7: error: variable lout_ca1; cannot be driven by a primitive or continuous assignment with non-default strength. -./ivltests/br_gh1222.v:7: error: variable lout_ca2; cannot be driven by a primitive or continuous assignment with non-default strength. -./ivltests/br_gh1222.v:12: error: variable rout_gt; cannot be driven by a primitive or continuous assignment with non-default strength. -./ivltests/br_gh1222.v:13: error: variable lout_gt; cannot be driven by a primitive or continuous assignment with non-default strength. -10 error(s) during elaboration. +./ivltests/br_gh1222.v:6: error: Variable 'rout_ca1' cannot be driven by a primitive or continuous assignment with non-default strength. +./ivltests/br_gh1222.v:6: error: Variable 'rout_ca2' cannot be driven by a primitive or continuous assignment with non-default strength. +./ivltests/br_gh1222.v:7: error: Variable 'lout_ca1' cannot be driven by a primitive or continuous assignment with non-default strength. +./ivltests/br_gh1222.v:7: error: Variable 'lout_ca2' cannot be driven by a primitive or continuous assignment with non-default strength. +./ivltests/br_gh1222.v:12: error: Variable 'rout_gt' cannot be driven by a primitive or continuous assignment with non-default strength. +./ivltests/br_gh1222.v:12: error: Failed to elaborate primitive output expression top.rout_gt. +./ivltests/br_gh1222.v:13: error: Variable 'lout_gt' cannot be driven by a primitive or continuous assignment with non-default strength. +./ivltests/br_gh1222.v:13: error: Failed to elaborate primitive output expression top.lout_gt. +12 error(s) during elaboration. diff --git a/ivtest/gold/br_gh127a.gold b/ivtest/gold/br_gh127a.gold index 66a3c75a4..15d5c09a7 100644 --- a/ivtest/gold/br_gh127a.gold +++ b/ivtest/gold/br_gh127a.gold @@ -1,6 +1,6 @@ -./ivltests/br_gh127a.v:21: warning: Port 2 (in) of copy expects 2 bits, got 1. +./ivltests/br_gh127a.v:21: warning: Port 2 (in) of module copy expects 2 bit(s), given 1. ./ivltests/br_gh127a.v:21: : Padding 1 high bits of the port. -./ivltests/br_gh127a.v:23: warning: Port 2 (in) of copy expects 2 bits, got 3. +./ivltests/br_gh127a.v:23: warning: Port 2 (in) of module copy expects 2 bit(s), given 3. ./ivltests/br_gh127a.v:23: : Pruning 1 high bits of the expression. 00 : 0 00 : 00 00 : 000 00 01 : 1 01 : 01 01 : 001 01 diff --git a/ivtest/gold/br_gh127b.gold b/ivtest/gold/br_gh127b.gold index 89670456b..04d1d4528 100644 --- a/ivtest/gold/br_gh127b.gold +++ b/ivtest/gold/br_gh127b.gold @@ -1,6 +1,6 @@ -./ivltests/br_gh127b.v:21: warning: Port 2 (in) of copy expects 2 bits, got 1. +./ivltests/br_gh127b.v:21: warning: Port 2 (in) of module copy expects 2 bit(s), given 1. ./ivltests/br_gh127b.v:21: : Leaving 1 high bits of the port unconnected. -./ivltests/br_gh127b.v:23: warning: Port 2 (in) of copy expects 2 bits, got 3. +./ivltests/br_gh127b.v:23: warning: Port 2 (in) of module copy expects 2 bit(s), given 3. ./ivltests/br_gh127b.v:23: : Leaving 1 high bits of the expression dangling. 00 : 0 z0 : 00 00 : 000 00 01 : 1 z1 : 01 01 : 001 01 diff --git a/ivtest/gold/br_gh127c.gold b/ivtest/gold/br_gh127c.gold index 9a1313cf0..7fc721482 100644 --- a/ivtest/gold/br_gh127c.gold +++ b/ivtest/gold/br_gh127c.gold @@ -1,12 +1,12 @@ ./ivltests/br_gh127c.v:21: warning: input port out is coerced to inout. ./ivltests/br_gh127c.v:21: warning: output port in is coerced to inout. -./ivltests/br_gh127c.v:21: warning: Port 2 (in) of copy expects 2 bits, got 1. +./ivltests/br_gh127c.v:21: warning: Port 2 (in) of module copy expects 2 bit(s), given 1. ./ivltests/br_gh127c.v:21: : Leaving 1 high bits of the port unconnected. ./ivltests/br_gh127c.v:22: warning: input port out is coerced to inout. ./ivltests/br_gh127c.v:22: warning: output port in is coerced to inout. ./ivltests/br_gh127c.v:23: warning: input port out is coerced to inout. ./ivltests/br_gh127c.v:23: warning: output port in is coerced to inout. -./ivltests/br_gh127c.v:23: warning: Port 2 (in) of copy expects 2 bits, got 3. +./ivltests/br_gh127c.v:23: warning: Port 2 (in) of module copy expects 2 bit(s), given 3. ./ivltests/br_gh127c.v:23: : Leaving 1 high bits of the expression dangling. 00 : 0 z0 : 00 00 : 000 00 01 : 1 z1 : 01 01 : 001 01 diff --git a/ivtest/gold/br_gh127d.gold b/ivtest/gold/br_gh127d.gold index 0625cf3b9..1d67b3554 100644 --- a/ivtest/gold/br_gh127d.gold +++ b/ivtest/gold/br_gh127d.gold @@ -1,6 +1,6 @@ -./ivltests/br_gh127d.v:21: warning: Port 1 (out) of copy expects 2 bits, got 1. +./ivltests/br_gh127d.v:21: warning: Port 1 (out) of module copy expects 2 bit(s), given 1. ./ivltests/br_gh127d.v:21: : Padding 1 high bits of the port. -./ivltests/br_gh127d.v:23: warning: Port 1 (out) of copy expects 2 bits, got 3. +./ivltests/br_gh127d.v:23: warning: Port 1 (out) of module copy expects 2 bit(s), given 3. ./ivltests/br_gh127d.v:23: : Padding 1 high bits of the expression. 00 : 00 0 : 00 00 : 00 000 01 : 01 1 : 01 01 : 01 001 diff --git a/ivtest/gold/br_gh127e.gold b/ivtest/gold/br_gh127e.gold index 8ea1d6e3e..638cc8acf 100644 --- a/ivtest/gold/br_gh127e.gold +++ b/ivtest/gold/br_gh127e.gold @@ -1,6 +1,6 @@ -./ivltests/br_gh127e.v:21: warning: Port 1 (out) of copy expects 2 bits, got 1. +./ivltests/br_gh127e.v:21: warning: Port 1 (out) of module copy expects 2 bit(s), given 1. ./ivltests/br_gh127e.v:21: : Leaving 1 high bits of the port unconnected. -./ivltests/br_gh127e.v:23: warning: Port 1 (out) of copy expects 2 bits, got 3. +./ivltests/br_gh127e.v:23: warning: Port 1 (out) of module copy expects 2 bit(s), given 3. ./ivltests/br_gh127e.v:23: : Leaving 1 high bits of the expression dangling. 00 : 00 0 : 00 00 : 00 z00 01 : 01 1 : 01 01 : 01 z01 diff --git a/ivtest/gold/br_gh127f.gold b/ivtest/gold/br_gh127f.gold index 4aee74d31..26de006ef 100644 --- a/ivtest/gold/br_gh127f.gold +++ b/ivtest/gold/br_gh127f.gold @@ -1,11 +1,11 @@ ./ivltests/br_gh127f.v:21: warning: input port out is coerced to inout. -./ivltests/br_gh127f.v:21: warning: Port 1 (out) of copy expects 2 bits, got 1. +./ivltests/br_gh127f.v:21: warning: Port 1 (out) of module copy expects 2 bit(s), given 1. ./ivltests/br_gh127f.v:21: : Leaving 1 high bits of the port unconnected. ./ivltests/br_gh127f.v:21: warning: output port in is coerced to inout. ./ivltests/br_gh127f.v:22: warning: input port out is coerced to inout. ./ivltests/br_gh127f.v:22: warning: output port in is coerced to inout. ./ivltests/br_gh127f.v:23: warning: input port out is coerced to inout. -./ivltests/br_gh127f.v:23: warning: Port 1 (out) of copy expects 2 bits, got 3. +./ivltests/br_gh127f.v:23: warning: Port 1 (out) of module copy expects 2 bit(s), given 3. ./ivltests/br_gh127f.v:23: : Leaving 1 high bits of the expression dangling. ./ivltests/br_gh127f.v:23: warning: output port in is coerced to inout. 00 : 00 0 : 00 00 : 00 z00 diff --git a/ivtest/gold/br_gh939-iverilog-stderr.gold b/ivtest/gold/br_gh939-iverilog-stderr.gold index e7388707a..ab0154af0 100644 --- a/ivtest/gold/br_gh939-iverilog-stderr.gold +++ b/ivtest/gold/br_gh939-iverilog-stderr.gold @@ -1,4 +1,4 @@ ivltests/br_gh939.v:10: error: Net o is not defined in this context. -ivltests/br_gh939.v:10: error: Output port expression must support continuous assignment. -ivltests/br_gh939.v:10: : Port 1 (o) of M is connected to o +ivltests/br_gh939.v:10: error: Output port expression must support a continuous assignment. +ivltests/br_gh939.v:10: : Port 1 (o) of M is connected to test.o 2 error(s) during elaboration. diff --git a/ivtest/gold/br_gh956a.gold b/ivtest/gold/br_gh956a.gold new file mode 100644 index 000000000..55bdab630 --- /dev/null +++ b/ivtest/gold/br_gh956a.gold @@ -0,0 +1,9 @@ +./ivltests/br_gh956a.v:7: error: Variable 'x' cannot be driven by a continuous assignment/module. +./ivltests/br_gh956a.v:7: : This is allowed when SystemVerilog is enabled. +./ivltests/br_gh956a.v:7: error: Output port expression must support a continuous assignment. +./ivltests/br_gh956a.v:7: : Port 1 (o) of ssub is connected to top.i1.x +./ivltests/br_gh956a.v:7: error: Variable 'x' cannot be driven by a continuous assignment/module. +./ivltests/br_gh956a.v:7: : This is allowed when SystemVerilog is enabled. +./ivltests/br_gh956a.v:7: error: Output port expression must support a continuous assignment. +./ivltests/br_gh956a.v:7: : Port 1 (o) of ssub is connected to top.i2.x +4 error(s) during elaboration. diff --git a/ivtest/gold/br_gh956b-fsv.gold b/ivtest/gold/br_gh956b-fsv.gold new file mode 100644 index 000000000..a31725db6 --- /dev/null +++ b/ivtest/gold/br_gh956b-fsv.gold @@ -0,0 +1,9 @@ +./ivltests/br_gh956b.v:3: error: Variable 'y' cannot be driven by a primitive or continuous assignment with non-default strength. +./ivltests/br_gh956b.v:3: error: Failed to elaborate primitive output expression top.i1.y. +./ivltests/br_gh956b.v:4: error: Variable 'z' cannot be driven by a primitive or continuous assignment with non-default strength. +./ivltests/br_gh956b.v:4: error: Failed to elaborate primitive output expression top.i1.z. +./ivltests/br_gh956b.v:3: error: Variable 'y' cannot be driven by a primitive or continuous assignment with non-default strength. +./ivltests/br_gh956b.v:3: error: Failed to elaborate primitive output expression top.i2.y. +./ivltests/br_gh956b.v:4: error: Variable 'z' cannot be driven by a primitive or continuous assignment with non-default strength. +./ivltests/br_gh956b.v:4: error: Failed to elaborate primitive output expression top.i2.z. +8 error(s) during elaboration. diff --git a/ivtest/gold/br_gh956b.gold b/ivtest/gold/br_gh956b.gold new file mode 100644 index 000000000..f7b938db7 --- /dev/null +++ b/ivtest/gold/br_gh956b.gold @@ -0,0 +1,9 @@ +./ivltests/br_gh956b.v:3: error: Variable 'y' cannot be driven by a primitive. +./ivltests/br_gh956b.v:3: error: Failed to elaborate primitive output expression top.i1.y. +./ivltests/br_gh956b.v:4: error: Variable 'z' cannot be driven by a primitive. +./ivltests/br_gh956b.v:4: error: Failed to elaborate primitive output expression top.i1.z. +./ivltests/br_gh956b.v:3: error: Variable 'y' cannot be driven by a primitive. +./ivltests/br_gh956b.v:3: error: Failed to elaborate primitive output expression top.i2.y. +./ivltests/br_gh956b.v:4: error: Variable 'z' cannot be driven by a primitive. +./ivltests/br_gh956b.v:4: error: Failed to elaborate primitive output expression top.i2.z. +8 error(s) during elaboration. diff --git a/ivtest/gold/pr1833024.gold b/ivtest/gold/pr1833024.gold index 56acf5547..32817111d 100644 --- a/ivtest/gold/pr1833024.gold +++ b/ivtest/gold/pr1833024.gold @@ -27,9 +27,13 @@ ./ivltests/pr1833024.v:27: error: can not select part of scalar array word: wsarr[0] ./ivltests/pr1833024.v:28: error: can not select part of scalar array word: wsarr[0] ./ivltests/pr1833024.v:30: error: can not select part of scalar: wsbstr +./ivltests/pr1833024.v:30: error: Failed to elaborate primitive output expression top.wsbstr['sd0]. ./ivltests/pr1833024.v:31: error: can not select part of scalar: wspstr +./ivltests/pr1833024.v:31: error: Failed to elaborate primitive output expression top.wspstr['sd0:'sd0]. ./ivltests/pr1833024.v:32: error: can not select part of scalar: wsuptr +./ivltests/pr1833024.v:32: error: Failed to elaborate primitive output expression top.wsuptr['sd0+:'sd1]. ./ivltests/pr1833024.v:33: error: can not select part of scalar: wsdotr +./ivltests/pr1833024.v:33: error: Failed to elaborate primitive output expression top.wsdotr['sd0-:'sd1]. ./ivltests/pr1833024.v:35: error: can not select part of scalar: wsbstr ./ivltests/pr1833024.v:35: error: Failed to elaborate input port 'arg1' expression (wsbstr['sd0]) in instance top.s1 of module: submod1. ./ivltests/pr1833024.v:35: error: can not select part of scalar: wspstr @@ -39,17 +43,17 @@ ./ivltests/pr1833024.v:35: error: can not select part of scalar: wsdotr ./ivltests/pr1833024.v:35: error: Failed to elaborate input port 'arg4' expression (wsdotr['sd0-:'sd1]) in instance top.s1 of module: submod1. ./ivltests/pr1833024.v:36: error: can not select part of scalar: wsbstr -./ivltests/pr1833024.v:36: error: Output port expression must support continuous assignment. -./ivltests/pr1833024.v:36: : Port 1 (arg1) of submod2 is connected to wsbstr['sd0] +./ivltests/pr1833024.v:36: error: Output port expression must support a continuous assignment. +./ivltests/pr1833024.v:36: : Port 1 (arg1) of submod2 is connected to top.wsbstr['sd0] ./ivltests/pr1833024.v:36: error: can not select part of scalar: wspstr -./ivltests/pr1833024.v:36: error: Output port expression must support continuous assignment. -./ivltests/pr1833024.v:36: : Port 2 (arg2) of submod2 is connected to wspstr['sd0:'sd0] +./ivltests/pr1833024.v:36: error: Output port expression must support a continuous assignment. +./ivltests/pr1833024.v:36: : Port 2 (arg2) of submod2 is connected to top.wspstr['sd0:'sd0] ./ivltests/pr1833024.v:36: error: can not select part of scalar: wsuptr -./ivltests/pr1833024.v:36: error: Output port expression must support continuous assignment. -./ivltests/pr1833024.v:36: : Port 3 (arg3) of submod2 is connected to wsuptr['sd0+:'sd1] +./ivltests/pr1833024.v:36: error: Output port expression must support a continuous assignment. +./ivltests/pr1833024.v:36: : Port 3 (arg3) of submod2 is connected to top.wsuptr['sd0+:'sd1] ./ivltests/pr1833024.v:36: error: can not select part of scalar: wsdotr -./ivltests/pr1833024.v:36: error: Output port expression must support continuous assignment. -./ivltests/pr1833024.v:36: : Port 4 (arg4) of submod2 is connected to wsdotr['sd0-:'sd1] +./ivltests/pr1833024.v:36: error: Output port expression must support a continuous assignment. +./ivltests/pr1833024.v:36: : Port 4 (arg4) of submod2 is connected to top.wsdotr['sd0-:'sd1] ./ivltests/pr1833024.v:37: error: can not select part of scalar: wsbstr ./ivltests/pr1833024.v:37: error: Inout port expression must support continuous assignment. ./ivltests/pr1833024.v:37: : Port 1 (arg1) of submod3 is connected to wsbstr['sd0] @@ -78,4 +82,4 @@ ./ivltests/pr1833024.v:67: error: can not select part of scalar array word: sarr[32'sd0] ./ivltests/pr1833024.v:68: error: can not select part of scalar array word: sarr[32'sd0] ./ivltests/pr1833024.v:69: error: can not select part of scalar array word: sarr[32'sd0] -72 error(s) during elaboration. +76 error(s) during elaboration. diff --git a/ivtest/gold/pr1866215.gold b/ivtest/gold/pr1866215.gold index b4a9b1399..1943332ac 100644 --- a/ivtest/gold/pr1866215.gold +++ b/ivtest/gold/pr1866215.gold @@ -1,9 +1,9 @@ -./ivltests/pr1866215.v:31: warning: Port 1 (CH) of C expects 7 bits, got 6. +./ivltests/pr1866215.v:31: warning: Port 1 (CH) of module C expects 7 bit(s), given 6. ./ivltests/pr1866215.v:31: : Padding 1 high bits of the port. -./ivltests/pr1866215.v:31: warning: Port 3 (SH) of C expects 8 bits, got 7. +./ivltests/pr1866215.v:31: warning: Port 3 (SH) of module C expects 8 bit(s), given 7. ./ivltests/pr1866215.v:31: : Padding 1 high bits of the port. -./ivltests/pr1866215.v:15: warning: Port 1 (CH) of B expects 6 bits, got 7. +./ivltests/pr1866215.v:15: warning: Port 1 (CH) of module B expects 6 bit(s), given 7. ./ivltests/pr1866215.v:15: : Padding 1 high bits of the expression. -./ivltests/pr1866215.v:15: warning: Port 3 (SH) of B expects 7 bits, got 8. +./ivltests/pr1866215.v:15: warning: Port 3 (SH) of module B expects 7 bit(s), given 8. ./ivltests/pr1866215.v:15: : Padding 1 high bits of the expression. C1H=33, {C1L, CL}={1555555, zzzzzzZ5}, S1H=66, {S1L, SL}={2aaaaaa, zzzzzzZa} diff --git a/ivtest/gold/pr1866215b.gold b/ivtest/gold/pr1866215b.gold index 886d18b4e..2659831c3 100644 --- a/ivtest/gold/pr1866215b.gold +++ b/ivtest/gold/pr1866215b.gold @@ -1,9 +1,9 @@ -./ivltests/pr1866215b.v:26: warning: Port 1 (CH) of C expects 7 bits, got 6. +./ivltests/pr1866215b.v:26: warning: Port 1 (CH) of module C expects 7 bit(s), given 6. ./ivltests/pr1866215b.v:26: : Padding 1 high bits of the port. -./ivltests/pr1866215b.v:26: warning: Port 3 (SH) of C expects 8 bits, got 7. +./ivltests/pr1866215b.v:26: warning: Port 3 (SH) of module C expects 8 bit(s), given 7. ./ivltests/pr1866215b.v:26: : Padding 1 high bits of the port. -./ivltests/pr1866215b.v:10: warning: Port 1 (CH) of B expects 6 bits, got 16. +./ivltests/pr1866215b.v:10: warning: Port 1 (CH) of module B expects 6 bit(s), given 16. ./ivltests/pr1866215b.v:10: : Pruning 10 high bits of the expression. -./ivltests/pr1866215b.v:10: warning: Port 3 (SH) of B expects 7 bits, got 16. +./ivltests/pr1866215b.v:10: warning: Port 3 (SH) of module B expects 7 bit(s), given 16. ./ivltests/pr1866215b.v:10: : Pruning 9 high bits of the expression. CH=3f, CL=55555555, SH=7f, SL=aaaaaaaa diff --git a/ivtest/gold/pr3190941.gold b/ivtest/gold/pr3190941.gold index 0b63b4ffd..4fe5716f3 100644 --- a/ivtest/gold/pr3190941.gold +++ b/ivtest/gold/pr3190941.gold @@ -1,4 +1,4 @@ ./ivltests/pr3190941.v:9: error: expression not valid in assign l-value: 4'bxxxx -./ivltests/pr3190941.v:9: error: Output port expression must support continuous assignment. -./ivltests/pr3190941.v:9: : Port 1 (x) of m1 is connected to {4'bxxxx, y} +./ivltests/pr3190941.v:9: error: Output port expression must support a continuous assignment. +./ivltests/pr3190941.v:9: : Port 1 (x) of m1 is connected to tb.{4'bxxxx, y} 2 error(s) during elaboration. diff --git a/ivtest/ivltests/br_gh956a.v b/ivtest/ivltests/br_gh956a.v new file mode 100644 index 000000000..66bf98111 --- /dev/null +++ b/ivtest/ivltests/br_gh956a.v @@ -0,0 +1,15 @@ +module ssub(o); + output o; +endmodule + +module sub; + reg x; + ssub i(x); +endmodule + +module top; + sub i1(); + sub i2(); + // This will work for SystemVerilog + initial $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/br_gh956b.v b/ivtest/ivltests/br_gh956b.v new file mode 100644 index 000000000..7b71876e0 --- /dev/null +++ b/ivtest/ivltests/br_gh956b.v @@ -0,0 +1,11 @@ +module sub; + reg y, z, ctrl; + tranif1(y, ctrl, x); + and(z, ctrl, y); +endmodule + +module top; + sub i1(); + sub i2(); + initial $display("FAILED - should be a compile error"); +endmodule diff --git a/ivtest/regress-fsv.list b/ivtest/regress-fsv.list index 55de4b8a6..afe656c74 100644 --- a/ivtest/regress-fsv.list +++ b/ivtest/regress-fsv.list @@ -74,6 +74,8 @@ br1027e normal ivltests gold=br1027e-fsv.gold br_gh25a normal ivltests br_gh25b normal ivltests br_gh567 normal ivltests +br_gh956a normal ivltests +br_gh956b CE ivltests gold=br_gh956b-fsv.gold br_gh1182 normal ivltests check_constant_3 normal ivltests function4 normal ivltests diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list index 0d75499bc..c8861ab1a 100644 --- a/ivtest/regress-vlg.list +++ b/ivtest/regress-vlg.list @@ -353,6 +353,8 @@ br_gh788 normal,-gno-io-range-error,-Wno-anachronisms ivltests gold=br_gh788.go br_gh793 normal ivltests br_gh827 normal ivltests gold=br_gh827.gold br_gh889 normal,-gspecify ivltests gold=br_gh889.gold +br_gh956a CE ivltests gold=br_gh956a.gold +br_gh956b CE ivltests gold=br_gh956b.gold br_gh1117 CE ivltests gold=br_gh1117.gold br_gh1175a CE ivltests gold=br_gh1175a.gold br_gh1175b CE ivltests gold=br_gh1175b.gold