From e97883b1dbe6a419ee9d9112bcb91c128685aa1f Mon Sep 17 00:00:00 2001
From: Martin Whitaker <icarus@martin-whitaker.me.uk>
Date: Fri, 2 Aug 2019 15:34:31 +0100
Subject: [PATCH] Fix for br1015 : assertion failure when task/function port is
 an array.

This is an error for Verilog and not yet supported for SystemVerilog.
---
 elab_sig.cc | 5 +++++
 parse.y     | 6 +++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/elab_sig.cc b/elab_sig.cc
index efe1997a4..d30bd55ea 100644
--- a/elab_sig.cc
+++ b/elab_sig.cc
@@ -757,6 +757,11 @@ void PTaskFunc::elaborate_sig_ports_(Design*des, NetScope*scope,
 		       << "Function arguments must be input ports." << endl;
 		  des->errors += 1;
 	    }
+	    if (tmp->unpacked_dimensions() != 0) {
+		  cerr << get_fileline() << ": sorry: Subroutine ports with "
+			  "unpacked dimensions are not yet supported." << endl;
+		 des->errors += 1;
+	    }
       }
 }
 
diff --git a/parse.y b/parse.y
index b2c674691..a8cbbfbee 100644
--- a/parse.y
+++ b/parse.y
@@ -2223,7 +2223,11 @@ tf_port_item /* IEEE1800-2005: A.2.7 */
 	      tmp = pform_make_task_ports(@3, use_port_type, $2, ilist);
 	}
 	if ($4 != 0) {
-	      pform_set_reg_idx(name, $4);
+	      if (gn_system_verilog()) {
+		    pform_set_reg_idx(name, $4);
+	      } else {
+		    yyerror(@4, "error: Task/function port with unpacked dimensions requires SystemVerilog.");
+	      }
 	}
 
 	$$ = tmp;