diff --git a/expr_synth.cc b/expr_synth.cc
index 4d30ead55..9e619aa9f 100644
--- a/expr_synth.cc
+++ b/expr_synth.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: expr_synth.cc,v 1.28 2001/10/28 01:14:53 steve Exp $"
+#ident "$Id: expr_synth.cc,v 1.29 2001/11/29 01:58:18 steve Exp $"
 #endif
 
 # include "config.h"
@@ -510,7 +510,7 @@ NetNet* NetETernary::synthesize(Design *des)
 }
 
 /*
- * When synthesizing a signal expressoin, it is usually fine to simply
+ * When synthesizing a signal expression, it is usually fine to simply
  * return the NetNet that it refers to. If this is a part select,
  * though, a bit more work needs to be done. Return a temporary that
  * represents the connections to the selected bits.
@@ -562,6 +562,9 @@ NetNet* NetESignal::synthesize(Design*des)
 
 /*
  * $Log: expr_synth.cc,v $
+ * Revision 1.29  2001/11/29 01:58:18  steve
+ *  Handle part selects in l-values of DFF devices.
+ *
  * Revision 1.28  2001/10/28 01:14:53  steve
  *  NetObj constructor finally requires a scope.
  *
diff --git a/iverilog.conf b/iverilog.conf
index 71d1c048d..6cb1182f8 100644
--- a/iverilog.conf
+++ b/iverilog.conf
@@ -59,7 +59,7 @@
 # be useful and interesting if the -N flag is included.
 
 [-tnull -S]
-<ivl>%B/ivl %[v-v] %y %Y %W %s %[N-N%N] %[T-T%T] -tdll -fDLL=%B/null.tgt -- -
+<ivl>%B/ivl %[v-v] %y %Y %W %s %[N-N%N] %[T-T%T] -tdll -fDLL=%B/null.tgt -Fsynth -Fsyn-rules -- -
 
 [-tnull]
 <ivl>%B/ivl %[v-v] %y %Y %W %s %[N-N%N] %[T-T%T] -tdll -fDLL=%B/null.tgt -- -
diff --git a/netlist.h b/netlist.h
index 32bf7daba..9721a635b 100644
--- a/netlist.h
+++ b/netlist.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: netlist.h,v 1.225 2001/11/19 04:26:46 steve Exp $"
+#ident "$Id: netlist.h,v 1.226 2001/11/29 01:58:18 steve Exp $"
 #endif
 
 /*
@@ -1181,7 +1181,7 @@ class NetAssign_ {
 
 	// Get the width of the r-value that this node expects. This
 	// method accounts for the presence of the mux, so it not
-	// nexessarily the same as the pin_count().
+	// necessarily the same as the pin_count().
       unsigned lwidth() const;
 
 	// Get the name of the underlying object.
@@ -2862,6 +2862,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
 
 /*
  * $Log: netlist.h,v $
+ * Revision 1.226  2001/11/29 01:58:18  steve
+ *  Handle part selects in l-values of DFF devices.
+ *
  * Revision 1.225  2001/11/19 04:26:46  steve
  *  Unary reduction operators are all 1-bit results.
  *
diff --git a/syn-rules.y b/syn-rules.y
index 3aa41e122..7af425c14 100644
--- a/syn-rules.y
+++ b/syn-rules.y
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: syn-rules.y,v 1.15 2001/10/28 01:14:53 steve Exp $"
+#ident "$Id: syn-rules.y,v 1.16 2001/11/29 01:58:18 steve Exp $"
 #endif
 
 # include "config.h"
@@ -150,12 +150,29 @@ static void make_DFF_CE(Design*des, NetProcTop*top, NetEvWait*wclk,
 
       assert(d);
 
+	// FIXME!
+	// asn->l_val(0) is good as far as it goes, that's a
+	// *NetAssign_. Really need to chase the link list to the end,
+	// otherwise we don't assign properly to constructs like {a,b}. 
+	// Should turn asn->l_val(0)->lwidth() below into
+	// asn->lwidth() and follow the linked list of l-values.
       NetFF*ff = new NetFF(top->scope(), asn->l_val(0)->name(),
 			   asn->l_val(0)->lwidth());
 
+	// asn->l_val(0)->sig() is a *NetNet, which doesn't have the
+	// loff_ and lwid_ context.  Add the correction for loff_
+	// ourselves.
+
+	// This extra calculations allows for statments like, for
+	// example:
+	//    lval[7:1] <= foo;
+	// where lval is really a "reg [7:0]". In other words, part
+	// selects in the l-value are handled by loff and the lwidth().
+
+      int loff = asn->l_val(0)->get_loff();
       for (unsigned idx = 0 ;  idx < ff->width() ;  idx += 1) {
 	    connect(ff->pin_Data(idx), d->bit(idx));
-	    connect(ff->pin_Q(idx), asn->l_val(0)->sig()->pin(idx));
+	    connect(ff->pin_Q(idx), asn->l_val(0)->sig()->pin(idx+loff));
       }
 
       connect(ff->pin_Clock(), pclk->pin(0));