From e7098492437b2c55aeedf7e4fea68857977346b0 Mon Sep 17 00:00:00 2001 From: Stephen Williams Date: Thu, 25 Jul 2013 21:03:54 -0700 Subject: [PATCH] Add a README-BLIF.txt file for the blif target. --- tgt-blif/README-BLIF.txt | 44 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 tgt-blif/README-BLIF.txt diff --git a/tgt-blif/README-BLIF.txt b/tgt-blif/README-BLIF.txt new file mode 100644 index 000000000..ce337de06 --- /dev/null +++ b/tgt-blif/README-BLIF.txt @@ -0,0 +1,44 @@ + +BLIF TARGET +----------- + +The BLIF code generator supports emitting the design to a blif format +file as accepted by: + + ABC: A System for Sequential Synthesis and Verification + + +This package contains tools sometimes used by ASIC designers. This +blif target emits .blif file that the ABC system can read int via +the "read_blif" command. + + +USAGE +----- + +This code generator is intended to process structural Verilog source +code. To convert a design to blif, use this command: + + iverilog -tblif -o.blif ... + +The source files can be Verilog, System Verilog, VHDL, whatever Icarus +Verilog supports, so long as it elaborates down to the limited subset +that the code generator supports. In other words, the files must be +structural. + +The root module of the elaborated design becomes the model is +generated. That module may instantiate sub-modules and so on down the +design, completing the design. The output model is flattened, so it +doesn't invoke any subcircuits. Bit vectors are exploded out at the +model ports and internally. This is necessary since blif in particular +and ABC in general processes bits, not vectors. + + +LIMITATIONS +----------- + +Currently, only explicit logic gates and continuous assignments are +supported. + +The design must contain only one root module. The name of that root +module becomes the name of the blif model in the ".model" record.