From e49b796a5157ea0a3cfbcaf3e65ee8a935602756 Mon Sep 17 00:00:00 2001 From: Nick Gasson Date: Sun, 28 Aug 2011 17:10:43 +0100 Subject: [PATCH] Fix for pr3397689. This is caused by a bug in some simple pattern matching the VHDL target does to try and produce more idiomatic code in common cases (e.g. FFs with asynchronous resets in this case). This patch just restricts the kinds of if-statements we use this optimisation for. --- tgt-vhdl/stmt.cc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tgt-vhdl/stmt.cc b/tgt-vhdl/stmt.cc index 1053ed00f..7581113df 100644 --- a/tgt-vhdl/stmt.cc +++ b/tgt-vhdl/stmt.cc @@ -767,6 +767,11 @@ static bool draw_synthesisable_wait(vhdl_process *proc, stmt_container *containe set test_nexuses; get_nexuses_from_expr(ivl_stmt_cond_expr(sub_stmt), test_nexuses); + // If the test is not a simple function of one variable then this + // template will not work + if (test_nexuses.size() != 1) + return false; + // Now subtracting this set from the set of edge triggered events // should leave just one nexus, which is hopefully the clock. // If not, then we fall back on the default draw_wait