diff --git a/ivtest/ivltests/nb_ec_array.v b/ivtest/ivltests/nb_ec_array.v
index eca60ee65..674509e4f 100644
--- a/ivtest/ivltests/nb_ec_array.v
+++ b/ivtest/ivltests/nb_ec_array.v
@@ -78,6 +78,23 @@ module top;
       pass = 1'b0;
     end
 
+    // These should execute as if there was no event control
+    result[0] <= repeat(0) @(posedge clk) 4'h4;
+    #1
+    if ($simtime != 171 || result[0] !== 4'h4) begin
+      $display("Failed @ at %0t, expected 4'h4, got %h",
+               $simtime, result[0]);
+      pass = 1'b0;
+    end
+
+    result[0] <= repeat(-1) @(posedge clk) 4'h5;
+    #1
+    if ($simtime != 172 || result[0] !== 4'h5) begin
+      $display("Failed @ at %0t, expected 4'h5, got %h",
+               $simtime, result[0]);
+      pass = 1'b0;
+    end
+
     if (pass) $display("PASSED");
     $finish;
   end
diff --git a/ivtest/ivltests/nb_ec_array_pv.v b/ivtest/ivltests/nb_ec_array_pv.v
index a23ce06bc..357d96c0f 100644
--- a/ivtest/ivltests/nb_ec_array_pv.v
+++ b/ivtest/ivltests/nb_ec_array_pv.v
@@ -81,6 +81,16 @@ module top;
       pass = 1'b0;
     end
 
+    // These should execute as if there was no event control
+    result[0][3:0] <= repeat(0) @(posedge clk) 4'h3;
+    result[0][7:4] <= repeat(-1) @(posedge clk) 4'h4;
+    #1
+    if ($simtime != 171 || result[0] !== 8'h43) begin
+      $display("Failed @ at %0t, expected 8'h43, got %h",
+               $simtime, result[0]);
+      pass = 1'b0;
+    end
+
     if (pass) $display("PASSED");
     $finish;
   end
diff --git a/ivtest/ivltests/nb_ec_array_pv2.v b/ivtest/ivltests/nb_ec_array_pv2.v
index b8434b5cb..bdb2c930e 100644
--- a/ivtest/ivltests/nb_ec_array_pv2.v
+++ b/ivtest/ivltests/nb_ec_array_pv2.v
@@ -84,6 +84,16 @@ module top;
       pass = 1'b0;
     end
 
+    // These should execute as if there was no event control
+    result[j][i+:4] <= repeat(0) @(posedge clk) 4'h3;
+    result[j][i+4+:4] <= repeat(-1) @(posedge clk) 4'h4;
+    #1
+    if ($simtime != 171 || result[j] !== 8'h43) begin
+      $display("Failed @ at %0t, expected 8'h43, got %h",
+               $simtime, result[j]);
+      pass = 1'b0;
+    end
+
     if (pass) $display("PASSED");
     $finish;
   end
diff --git a/ivtest/ivltests/nb_ec_pv.v b/ivtest/ivltests/nb_ec_pv.v
index 4d65f5fc0..c44cdc3a2 100644
--- a/ivtest/ivltests/nb_ec_pv.v
+++ b/ivtest/ivltests/nb_ec_pv.v
@@ -78,6 +78,16 @@ module top;
       pass = 1'b0;
     end
 
+    // These should execute as if there was no event control
+    result[3:0] <= repeat(0) @(posedge clk) 4'h3;
+    result[7:4] <= repeat(-1) @(posedge clk) 4'h4;
+    #1
+    if ($simtime != 171 || result !== 8'h43) begin
+      $display("Failed @ at %0t, expected 8'h43, got %h",
+               $simtime, result);
+      pass = 1'b0;
+    end
+
     if (pass) $display("PASSED");
     $finish;
   end
diff --git a/ivtest/ivltests/nb_ec_pv2.v b/ivtest/ivltests/nb_ec_pv2.v
index 80260b4a7..112ff0d21 100644
--- a/ivtest/ivltests/nb_ec_pv2.v
+++ b/ivtest/ivltests/nb_ec_pv2.v
@@ -5,6 +5,7 @@ module top;
   reg clk = 0;
   reg [7:0] result;
   reg [3:0] bit;
+  integer count;
 
   always #10 clk = ~clk;
 
@@ -12,6 +13,7 @@ module top;
     // Since the bit is not defined this assignment will not happen.
     // We will check to verify this fact 1 time step after it should
     // happen (50).
+    #0;
     result[bit] <= repeat(3) @(posedge clk) 1'b0;
     if ($simtime != 0 || result !== 8'bx) begin
       $display("Failed repeat(3) blocked at %0t, expected 8'hxx, got %h",
@@ -34,6 +36,41 @@ module top;
       pass = 1'b0;
     end
 
+    // These should execute as if there was no event control
+    count = 0;
+    result[bit] <= repeat(count) @(posedge clk) 1'b1;
+    #1
+    if ($simtime != 71 || result !== 8'bxxxxxxx1) begin
+      $display("Failed @ at %0t, expected 8'bxxxxxxx1, got %h",
+               $simtime, result);
+      pass = 1'b0;
+    end
+
+    count = -1;
+    result[bit+1] <= repeat(count) @(posedge clk) 1'b0;
+    #1
+    if ($simtime != 72 || result !== 8'bxxxxxx01) begin
+      $display("Failed @ at %0t, expected 8'bxxxxxx01, got %h",
+               $simtime, result);
+      pass = 1'b0;
+    end
+
+    result[bit+2] <= repeat(0) @(posedge clk) 1'b1;
+    #1
+    if ($simtime != 73 || result !== 8'bxxxxx101) begin
+      $display("Failed @ at %0t, expected 8'bxxxxx101, got %h",
+               $simtime, result);
+      pass = 1'b0;
+    end
+
+    result[bit+3] <= repeat(-1) @(posedge clk) 1'b0;
+    #1
+    if ($simtime != 74 || result !== 8'bxxxx0101) begin
+      $display("Failed @ at %0t, expected 8'bxxxx0101, got %h",
+               $simtime, result);
+      pass = 1'b0;
+    end
+
     if (pass) $display("PASSED");
     $finish;
   end
diff --git a/ivtest/ivltests/nb_ec_real.v b/ivtest/ivltests/nb_ec_real.v
index 2ceba1a21..3334d247d 100644
--- a/ivtest/ivltests/nb_ec_real.v
+++ b/ivtest/ivltests/nb_ec_real.v
@@ -78,6 +78,23 @@ module top;
       pass = 1'b0;
     end
 
+    // These should execute as if there was no event control
+    result <= repeat(0) @(posedge clk) 4.0;
+    #1
+    if ($simtime != 171 || result != 4.0) begin
+      $display("Failed @ at %0t, expected 4.0, got %f",
+               $simtime, result);
+      pass = 1'b0;
+    end
+
+    result <= repeat(-1) @(posedge clk) 5.0;
+    #1
+    if ($simtime != 172 || result != 5.0) begin
+      $display("Failed @ at %0t, expected 5.0, got %f",
+               $simtime, result);
+      pass = 1'b0;
+    end
+
     if (pass) $display("PASSED");
     $finish;
   end
diff --git a/ivtest/ivltests/nb_ec_vector.v b/ivtest/ivltests/nb_ec_vector.v
index 0c6238a37..5c3dd8b26 100644
--- a/ivtest/ivltests/nb_ec_vector.v
+++ b/ivtest/ivltests/nb_ec_vector.v
@@ -78,6 +78,23 @@ module top;
       pass = 1'b0;
     end
 
+    // These should execute as if there was no event control
+    result <= repeat(0) @(posedge clk) 4'h4;
+    #1
+    if ($simtime != 171 || result !== 4'h4) begin
+      $display("Failed @ at %0t, expected 4'h4, got %h",
+               $simtime, result);
+      pass = 1'b0;
+    end
+
+    result <= repeat(-1) @(posedge clk) 4'h5;
+    #1
+    if ($simtime != 172 || result !== 4'h5) begin
+      $display("Failed @ at %0t, expected 4'h5, got %h",
+               $simtime, result);
+      pass = 1'b0;
+    end
+
     if (pass) $display("PASSED");
     $finish;
   end