From ded0fbe5ef2b91068746f0f74f16cb8b4ffd8ac2 Mon Sep 17 00:00:00 2001 From: Cary R Date: Tue, 15 Jan 2008 13:25:57 -0800 Subject: [PATCH] Fix user functions with right shift argument. A right shift may generate extra bits to preserve the proper shift characteristic. This patch replaces the assert that was forcing the input vector to not be greater than the input port width with code to only select the required lower bits from the vector if it is larger than the input port. --- tgt-vvp/draw_ufunc.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tgt-vvp/draw_ufunc.c b/tgt-vvp/draw_ufunc.c index e5999c5ce..db5ee7dcd 100644 --- a/tgt-vvp/draw_ufunc.c +++ b/tgt-vvp/draw_ufunc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2005-2007 Stephen Williams (steve@icarus.com) + * Copyright (c) 2005-2008 Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU @@ -33,8 +33,10 @@ static void function_argument_logic(ivl_signal_t port, ivl_expr_t exp) assert(ivl_signal_array_count(port) == 1); res = draw_eval_expr_wid(exp, ivl_signal_width(port), 0); - assert(res.wid <= ivl_signal_width(port)); - fprintf(vvp_out, " %%set/v v%p_0, %u, %u;\n", port, res.base, res.wid); + /* We could have extra bits so only select the ones we need. */ + unsigned pwidth = ivl_signal_width(port); + fprintf(vvp_out, " %%set/v v%p_0, %u, %u;\n", port, res.base, + (res.wid > pwidth) ? pwidth : res.wid); clr_vector(res); }