diff --git a/tgt-vhdl/process.cc b/tgt-vhdl/process.cc index d3813caa5..9440b25cf 100644 --- a/tgt-vhdl/process.cc +++ b/tgt-vhdl/process.cc @@ -1,7 +1,7 @@ /* * VHDL code generation for processes. * - * Copyright (C) 2008 Nick Gasson (nick@nickg.me.uk) + * Copyright (C) 2008-2010 Nick Gasson (nick@nickg.me.uk) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -83,7 +83,7 @@ static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc) return 0; } -int draw_process(ivl_process_t proc, void *cd) +extern "C" int draw_process(ivl_process_t proc, void *cd) { ivl_scope_t scope = ivl_process_scope(proc); diff --git a/tgt-vhdl/scope.cc b/tgt-vhdl/scope.cc index b7645d8d7..984b070aa 100644 --- a/tgt-vhdl/scope.cc +++ b/tgt-vhdl/scope.cc @@ -921,7 +921,7 @@ static void create_skeleton_entity_for(ivl_scope_t scope, int depth) * A first pass through the hierarchy: create VHDL entities for * each unique Verilog module type. */ -static int draw_skeleton_scope(ivl_scope_t scope, void *_unused) +extern "C" int draw_skeleton_scope(ivl_scope_t scope, void *_unused) { static int depth = 0; @@ -949,7 +949,7 @@ static int draw_skeleton_scope(ivl_scope_t scope, void *_unused) return rc; } -static int draw_all_signals(ivl_scope_t scope, void *_parent) +extern "C" int draw_all_signals(ivl_scope_t scope, void *_parent) { if (!is_default_scope_instance(scope)) return 0; // Not interested in this instance @@ -981,7 +981,7 @@ static int draw_all_signals(ivl_scope_t scope, void *_parent) /* * Draw all tasks and functions in the hierarchy. */ -static int draw_functions(ivl_scope_t scope, void *_parent) +extern "C" int draw_functions(ivl_scope_t scope, void *_parent) { if (!is_default_scope_instance(scope)) return 0; // Not interested in this instance @@ -1005,7 +1005,7 @@ static int draw_functions(ivl_scope_t scope, void *_parent) * This also has the side effect of generating all the necessary * nexus code. */ -static int draw_constant_drivers(ivl_scope_t scope, void *_parent) +extern "C" int draw_constant_drivers(ivl_scope_t scope, void *_parent) { if (!is_default_scope_instance(scope)) return 0; // Not interested in this instance @@ -1080,7 +1080,7 @@ static int draw_constant_drivers(ivl_scope_t scope, void *_parent) return 0; } -static int draw_all_logic_and_lpm(ivl_scope_t scope, void *_parent) +extern "C" int draw_all_logic_and_lpm(ivl_scope_t scope, void *_parent) { if (!is_default_scope_instance(scope)) return 0; // Not interested in this instance @@ -1100,7 +1100,7 @@ static int draw_all_logic_and_lpm(ivl_scope_t scope, void *_parent) return ivl_scope_children(scope, draw_all_logic_and_lpm, scope); } -static int draw_hierarchy(ivl_scope_t scope, void *_parent) +extern "C" int draw_hierarchy(ivl_scope_t scope, void *_parent) { if (ivl_scope_type(scope) == IVL_SCT_MODULE && _parent) { ivl_scope_t parent = static_cast(_parent); diff --git a/vpi/vcd_priv2.cc b/vpi/vcd_priv2.cc index 1fe4bc43b..bfb22f01d 100644 --- a/vpi/vcd_priv2.cc +++ b/vpi/vcd_priv2.cc @@ -155,7 +155,7 @@ static unsigned current_batch_cnt = 0; static unsigned current_batch_alloc = 0; static unsigned current_batch_base = 0; -void vcd_work_start( void* (*fun) (void*), void*arg ) +extern "C" void vcd_work_start( void* (*fun) (void*), void*arg ) { pthread_create(&work_thread, 0, fun, arg); }