From daad030ce628df1ff3967793db4cd446ef2d399d Mon Sep 17 00:00:00 2001
From: steve <steve>
Date: Wed, 2 Jul 2003 00:25:40 +0000
Subject: [PATCH]  Add xilinx support for bufif1.

---
 tgt-fpga/xilinx.c | 35 ++++++++++++++++++++++++++++++++++-
 tgt-fpga/xilinx.h |  8 ++++++--
 2 files changed, 40 insertions(+), 3 deletions(-)

diff --git a/tgt-fpga/xilinx.c b/tgt-fpga/xilinx.c
index aa4327721..0a5182618 100644
--- a/tgt-fpga/xilinx.c
+++ b/tgt-fpga/xilinx.c
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: xilinx.c,v 1.4 2003/06/28 04:18:47 steve Exp $"
+#ident "$Id: xilinx.c,v 1.5 2003/07/02 00:25:40 steve Exp $"
 #endif
 
 # include  "edif.h"
@@ -41,6 +41,18 @@ edif_cell_t xilinx_cell_buf(edif_xlibrary_t xlib)
       return cell;
 }
 
+edif_cell_t xilinx_cell_bufe(edif_xlibrary_t xlib)
+{
+      static edif_cell_t cell = 0;
+      if (cell) return cell;
+
+      cell = edif_xcell_create(xlib, "BUFE", 3);
+      edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
+      edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
+      edif_cell_portconfig(cell, BUF_T, "E", IVL_SIP_INPUT);
+      return cell;
+}
+
 edif_cell_t xilinx_cell_bufg(edif_xlibrary_t xlib)
 {
       static edif_cell_t cell = 0;
@@ -466,6 +478,24 @@ void xilinx_logic(ivl_net_logic_t net)
 	    edif_add_to_joint(jnt, obj, BUF_T);
 	    break;
 
+	  case IVL_LO_BUFIF1:
+	      /* The Xilinx BUFE devices is a BUF that adds an enable
+		 input. The output is tri-stated if the E input is 0.
+		 In other words, it acts just like bufif1. */
+	    assert(ivl_logic_pins(net) == 3);
+
+	    obj = edif_cellref_create(edf, xilinx_cell_bufe(xlib));
+
+	    jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
+	    edif_add_to_joint(jnt, obj, BUF_O);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
+	    edif_add_to_joint(jnt, obj, BUF_I);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 2));
+	    edif_add_to_joint(jnt, obj, BUF_T);
+	    break;
+
 	  case IVL_LO_NOT:
 	    assert(ivl_logic_pins(net) == 2);
 
@@ -762,6 +792,9 @@ void xilinx_shiftl(ivl_lpm_t net)
 
 /*
  * $Log: xilinx.c,v $
+ * Revision 1.5  2003/07/02 00:25:40  steve
+ *  Add xilinx support for bufif1.
+ *
  * Revision 1.4  2003/06/28 04:18:47  steve
  *  Add support for wide OR/NOR gates.
  *
diff --git a/tgt-fpga/xilinx.h b/tgt-fpga/xilinx.h
index 6eca38d35..ff47bd1de 100644
--- a/tgt-fpga/xilinx.h
+++ b/tgt-fpga/xilinx.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: xilinx.h,v 1.4 2003/06/28 04:18:47 steve Exp $"
+#ident "$Id: xilinx.h,v 1.5 2003/07/02 00:25:40 steve Exp $"
 #endif
 
 /*
@@ -38,6 +38,7 @@
    assignments. The BUF, INV, and certain specialized devices fit in
    this category. */
 extern edif_cell_t xilinx_cell_buf (edif_xlibrary_t xlib);
+extern edif_cell_t xilinx_cell_bufe(edif_xlibrary_t xlib);
 extern edif_cell_t xilinx_cell_bufg(edif_xlibrary_t xlib);
 extern edif_cell_t xilinx_cell_buft(edif_xlibrary_t xlib);
 extern edif_cell_t xilinx_cell_inv (edif_xlibrary_t xlib);
@@ -45,7 +46,7 @@ extern edif_cell_t xilinx_cell_ibuf(edif_xlibrary_t xlib);
 extern edif_cell_t xilinx_cell_obuf(edif_xlibrary_t xlib);
 #define BUF_O 0
 #define BUF_I 1
-  /* Only some buffers have this input. */
+  /* Only bufe and buft buffers have this input. */
 #define BUF_T 2
 
 /* === LUT Devices === */
@@ -113,6 +114,9 @@ extern void xilinx_shiftl(ivl_lpm_t net);
 
 /*
  * $Log: xilinx.h,v $
+ * Revision 1.5  2003/07/02 00:25:40  steve
+ *  Add xilinx support for bufif1.
+ *
  * Revision 1.4  2003/06/28 04:18:47  steve
  *  Add support for wide OR/NOR gates.
  *