From d997397c387726a23487c9e42a23ae03129a628e Mon Sep 17 00:00:00 2001
From: Nick Gasson <nick@nickg.me.uk>
Date: Wed, 25 Jun 2008 21:49:22 +0100
Subject: [PATCH] Generate function calls with parameters

---
 tgt-vhdl/expr.cc        | 10 +++++++++-
 tgt-vhdl/scope.cc       | 17 ++++++++++++-----
 tgt-vhdl/vhdl_syntax.cc |  2 ++
 3 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/tgt-vhdl/expr.cc b/tgt-vhdl/expr.cc
index 485c18206..593c3a6ab 100644
--- a/tgt-vhdl/expr.cc
+++ b/tgt-vhdl/expr.cc
@@ -222,9 +222,17 @@ vhdl_expr *translate_ufunc(ivl_expr_t e)
    assert(fdecl);
    
    vhdl_type *rettype = new vhdl_type(*fdecl->get_type());
-   
    vhdl_fcall *fcall = new vhdl_fcall(funcname, rettype);
 
+   int nparams = ivl_expr_parms(e);
+   for (int i = 0; i < nparams; i++) {
+      vhdl_expr *param = translate_expr(ivl_expr_parm(e, i));
+      if (NULL == param)
+         return NULL;
+
+      fcall->add_expr(param);
+   }
+
    return fcall;
 }
 
diff --git a/tgt-vhdl/scope.cc b/tgt-vhdl/scope.cc
index b5a7de94d..a5ca5d6ff 100644
--- a/tgt-vhdl/scope.cc
+++ b/tgt-vhdl/scope.cc
@@ -404,8 +404,15 @@ int draw_function(ivl_scope_t scope, ivl_scope_t parent)
 
       switch (ivl_signal_port(sig)) {
       case IVL_SIP_OUTPUT:
-         assert(func == NULL);
-         func = new vhdl_function(funcname, sigtype);
+         {
+            assert(func == NULL);
+            func = new vhdl_function(funcname, sigtype);
+
+            // The magic variable Verilog_Result holds the return value
+            signame = "Verilog_Result";
+            func->get_scope()->add_decl
+               (new vhdl_var_decl(signame.c_str(), new vhdl_type(*sigtype)));
+         }
          break;
       case IVL_SIP_INPUT:
          assert(func);
@@ -417,9 +424,9 @@ int draw_function(ivl_scope_t scope, ivl_scope_t parent)
 
       remember_signal(sig, func->get_scope());
       rename_signal(sig, signame);
-   }   
-
-   assert(func);
+   }
+   
+   assert(func); 
    ent->get_arch()->get_scope()->add_decl(func);   
    return 0;
 }
diff --git a/tgt-vhdl/vhdl_syntax.cc b/tgt-vhdl/vhdl_syntax.cc
index 4825b94e5..97fbc2753 100644
--- a/tgt-vhdl/vhdl_syntax.cc
+++ b/tgt-vhdl/vhdl_syntax.cc
@@ -772,6 +772,8 @@ void vhdl_function::emit(std::ofstream &of, int level) const
    emit_children<vhdl_decl>(of, variables_.get_decls(), level);
    of << "begin";
    stmts_.emit(of, level);
+   of << "  return Verilog_Result;";
+   newline(of, level);
    of << "end function;";
 }