diff --git a/elab_expr.cc b/elab_expr.cc
index 8c364c753..fcca11150 100644
--- a/elab_expr.cc
+++ b/elab_expr.cc
@@ -609,6 +609,7 @@ NetExpr* PEFNumber::elaborate_expr(Design*des, NetScope*scope, int, bool) const
 {
       NetECReal*tmp = new NetECReal(*value_);
       tmp->set_line(*this);
+      tmp->set_width(1U, false);
       return tmp;
 }
 
diff --git a/netlist.cc b/netlist.cc
index 17cfc9f76..97e328b80 100644
--- a/netlist.cc
+++ b/netlist.cc
@@ -2188,6 +2188,11 @@ ivl_variable_type_t NetETernary::expr_type() const
       if (tru == IVL_VT_BOOL && fal == IVL_VT_LOGIC)
 	    return IVL_VT_LOGIC;
 
+      if (tru != fal) {
+	    cerr << get_line() << ": internal error:"
+		 << " Unexpected ?: type clash:"
+		 << " tru=" << tru << ", fal=" << fal << endl;
+      }
       ivl_assert(*this, tru == fal);
       return tru;
 }
diff --git a/tgt-vvp/draw_ufunc.c b/tgt-vvp/draw_ufunc.c
index 02b73e55c..2925be79c 100644
--- a/tgt-vvp/draw_ufunc.c
+++ b/tgt-vvp/draw_ufunc.c
@@ -50,6 +50,7 @@ static void function_argument_real(ivl_signal_t port, ivl_expr_t exp)
       assert(ivl_signal_array_count(port) == 1);
 
       fprintf(vvp_out, "   %%set/wr v%p_0, %d;\n", port, res);
+      clr_word(res);
 }
 
 static void draw_function_argument(ivl_signal_t port, ivl_expr_t exp)
diff --git a/tgt-vvp/eval_expr.c b/tgt-vvp/eval_expr.c
index 708104db1..46447f1ac 100644
--- a/tgt-vvp/eval_expr.c
+++ b/tgt-vvp/eval_expr.c
@@ -1608,9 +1608,21 @@ static void draw_signal_dest(ivl_expr_t exp, struct vector_info res)
 	    word = get_number_immediate(ix);
       }
 
-	/* If this is a REG (a variable) then I can do a vector read. */
-      fprintf(vvp_out, "    %%load/v %u, v%p_%u, %u;\n",
-	      res.base, sig, word, swid);
+
+      if (ivl_signal_data_type(sig) == IVL_VT_REAL) {
+
+	    int tmp = allocate_word();
+	    fprintf(vvp_out, " %%load/wr %d, v%p_%u;\n", tmp, sig, word);
+	    fprintf(vvp_out, " %%cvt/vr %u, %d, %u;\n", res.base, tmp, res.wid);
+	    clr_word(tmp);
+
+      } else {
+
+	      /* If this is a REG (a variable) then I can do a vector read. */
+	    fprintf(vvp_out, "    %%load/v %u, v%p_%u, %u;\n",
+		    res.base, sig, word, swid);
+
+      }
 
       pad_expr_in_place(exp, res, swid);
 }
@@ -2231,169 +2243,5 @@ struct vector_info draw_eval_expr(ivl_expr_t exp, int stuff_ok_flag)
 
 /*
  * $Log: eval_expr.c,v $
- * Revision 1.137  2007/04/14 04:43:01  steve
- *  Finish up part select of array words.
- *
- * Revision 1.136  2007/03/22 16:08:18  steve
- *  Spelling fixes from Larry
- *
- * Revision 1.135  2007/02/26 19:49:50  steve
- *  Spelling fixes (larry doolittle)
- *
- * Revision 1.134  2007/02/12 04:37:58  steve
- *  Get padding right when loading array word into big vector.
- *
- * Revision 1.133  2007/01/19 05:24:53  steve
- *  Handle real constants in vector expressions.
- *
- * Revision 1.132  2007/01/17 04:39:18  steve
- *  Remove dead code related to memories.
- *
- * Revision 1.131  2007/01/16 05:44:16  steve
- *  Major rework of array handling. Memories are replaced with the
- *  more general concept of arrays. The NetMemory and NetEMemory
- *  classes are removed from the ivl core program, and the IVL_LPM_RAM
- *  lpm type is removed from the ivl_target API.
- *
- * Revision 1.130  2006/02/02 02:43:59  steve
- *  Allow part selects of memory words in l-values.
- *
- * Revision 1.129  2006/01/02 05:33:20  steve
- *  Node delays can be more general expressions in structural contexts.
- *
- * Revision 1.128  2005/12/22 15:42:22  steve
- *  Pad part selects
- *
- * Revision 1.127  2005/10/11 18:54:10  steve
- *  Remove the $ from signal labels. They do not help.
- *
- * Revision 1.126  2005/10/11 18:30:50  steve
- *  Remove obsolete vvp_memory_label function.
- *
- * Revision 1.125  2005/09/19 21:45:36  steve
- *  Spelling patches from Larry.
- *
- * Revision 1.124  2005/09/19 20:18:20  steve
- *  Fix warnings about uninitialized variables.
- *
- * Revision 1.123  2005/09/17 04:01:32  steve
- *  Improve loading of part selects when easy.
- *
- * Revision 1.122  2005/09/17 01:01:00  steve
- *  More robust use of precalculated expressions, and
- *  Separate lookaside for written variables that can
- *  also be reused.
- *
- * Revision 1.121  2005/09/15 02:49:47  steve
- *  Better reuse of IVL_EX_SELECT expressions.
- *
- * Revision 1.120  2005/09/14 02:53:15  steve
- *  Support bool expressions and compares handle them optimally.
- *
- * Revision 1.119  2005/07/13 04:52:31  steve
- *  Handle functions with real values.
- *
- * Revision 1.118  2005/07/11 16:56:51  steve
- *  Remove NetVariable and ivl_variable_t structures.
- *
- * Revision 1.117  2005/03/12 23:45:33  steve
- *  Handle function/task port vectors.
- *
- * Revision 1.116  2005/03/03 04:34:42  steve
- *  Rearrange how memories are supported as vvp_vector4 arrays.
- *
- * Revision 1.115  2005/02/15 07:12:55  steve
- *  Support constant part select writes to l-values, and large part select reads from signals.
- *
- * Revision 1.114  2005/01/28 05:37:48  steve
- *  Special handling of constant shift 0.
- *
- * Revision 1.113  2005/01/24 05:28:31  steve
- *  Remove the NetEBitSel and combine all bit/part select
- *  behavior into the NetESelect node and IVL_EX_SELECT
- *  ivl_target expression type.
- *
- * Revision 1.112  2005/01/24 05:08:02  steve
- *  Part selects are done in the compiler, not here.
- *
- * Revision 1.111  2004/12/11 02:31:28  steve
- *  Rework of internals to carry vectors through nexus instead
- *  of single bits. Make the ivl, tgt-vvp and vvp initial changes
- *  down this path.
- *
- * Revision 1.110  2004/10/04 01:10:57  steve
- *  Clean up spurious trailing white space.
- *
- * Revision 1.109  2004/09/10 00:14:31  steve
- *  Relaxed width constraint on pad_expression output.
- *
- * Revision 1.108  2004/06/30 03:07:32  steve
- *  Watch out for real compared to constant. Handle as real.
- *
- * Revision 1.107  2004/06/19 16:17:37  steve
- *  Generate signed modulus if appropriate.
- *
- * Revision 1.106  2003/10/01 17:44:20  steve
- *  Slightly more efficient unary minus.
- *
- * Revision 1.105  2003/09/24 20:46:20  steve
- *  Clear expression lookaside after true cause of ternary.
- *
- * Revision 1.104  2003/08/03 03:53:38  steve
- *  Subtract from constant values.
- *
- * Revision 1.103  2003/07/26 03:34:43  steve
- *  Start handling pad of expressions in code generators.
- *
- * Revision 1.102  2003/06/18 03:55:19  steve
- *  Add arithmetic shift operators.
- *
- * Revision 1.101  2003/06/17 19:17:42  steve
- *  Remove short int restrictions from vvp opcodes.
- *
- * Revision 1.100  2003/06/16 22:14:15  steve
- *  Fix fprintf warning.
- *
- * Revision 1.99  2003/06/15 22:49:32  steve
- *  More efficient code for ternary expressions.
- *
- * Revision 1.98  2003/06/14 22:18:54  steve
- *  Sign extend signed vectors.
- *
- * Revision 1.97  2003/06/13 19:10:20  steve
- *  Handle assign of real to vector.
- *
- * Revision 1.96  2003/06/11 02:23:45  steve
- *  Proper pad of signed constants.
- *
- * Revision 1.95  2003/05/10 02:38:49  steve
- *  Proper width handling of || expressions.
- *
- * Revision 1.94  2003/03/25 02:15:48  steve
- *  Use hash code for scope labels.
- *
- * Revision 1.93  2003/03/15 04:45:18  steve
- *  Allow real-valued vpi functions to have arguments.
- *
- * Revision 1.92  2003/02/28 20:21:13  steve
- *  Merge vpi_call and vpi_func draw functions.
- *
- * Revision 1.91  2003/02/07 02:46:16  steve
- *  Handle real value subtract and comparisons.
- *
- * Revision 1.90  2003/01/27 00:14:37  steve
- *  Support in various contexts the $realtime
- *  system task.
- *
- * Revision 1.89  2003/01/26 21:15:59  steve
- *  Rework expression parsing and elaboration to
- *  accommodate real/realtime values and expressions.
- *
- * Revision 1.88  2002/12/20 01:11:14  steve
- *  Evaluate shift index after shift operand because
- *  the chift operand may use the index register itself.
- *
- * Revision 1.87  2002/12/19 23:11:29  steve
- *  Keep bit select subexpression width if it is constant.
  */
 
diff --git a/vvp/vthread.cc b/vvp/vthread.cc
index 283ca5dce..046123471 100644
--- a/vvp/vthread.cc
+++ b/vvp/vthread.cc
@@ -2118,6 +2118,10 @@ bool of_LOAD_VEC(vthread_t thr, vvp_code_t cp)
 	/* For the %load to work, the functor must actually be a
 	   signal functor. Only signals save their vector value. */
       vvp_fun_signal_vec*sig = dynamic_cast<vvp_fun_signal_vec*> (net->fun);
+      if (sig == 0) {
+	    cerr << "%%load/v error: Net arg not a vector signal? "
+		 << typeid(*net->fun).name() << endl;
+      }
       assert(sig);
 
       vvp_vector4_t sig_value = sig->vec4_value();
@@ -3489,214 +3493,5 @@ bool of_JOIN_UFUNC(vthread_t thr, vvp_code_t cp)
 
 /*
  * $Log: vthread.cc,v $
- * Revision 1.166  2007/06/13 01:03:57  steve
- *  Detect and use the nan function.
- *
- * Revision 1.165  2007/06/12 02:36:58  steve
- *  handle constant inf values.
- *
- * Revision 1.164  2007/06/07 03:20:16  steve
- *  Properly handle signed conversion to real
- *
- * Revision 1.163  2007/06/05 21:52:22  steve
- *  int vs long expressions on 64bit arch (ldoolitt)
- *
- * Revision 1.162  2007/04/14 04:43:02  steve
- *  Finish up part select of array words.
- *
- * Revision 1.161  2007/02/14 05:58:14  steve
- *  Add the mov/wr opcode.
- *
- * Revision 1.160  2007/02/05 01:08:10  steve
- *  Handle relink of continuous assignment.
- *
- * Revision 1.159  2007/01/31 22:28:55  steve
- *  Fix missing check for thread bits width in ADDI
- *
- * Revision 1.158  2007/01/16 05:44:16  steve
- *  Major rework of array handling. Memories are replaced with the
- *  more general concept of arrays. The NetMemory and NetEMemory
- *  classes are removed from the ivl core program, and the IVL_LPM_RAM
- *  lpm type is removed from the ivl_target API.
- *
- * Revision 1.157  2006/10/05 01:23:54  steve
- *  Handle non-constant delays on indexed non-blocking assignments.
- *
- * Revision 1.156  2006/08/09 05:19:08  steve
- *  Add support for real valued modulus.
- *
- * Revision 1.155  2006/08/08 05:11:37  steve
- *  Handle 64bit delay constants.
- *
- * Revision 1.154  2006/08/04 04:37:37  steve
- *  Support release of a for/linked reg.
- *
- * Revision 1.153  2006/04/27 04:38:00  steve
- *  schedule takes relative, not absolute, time.
- *
- * Revision 1.152  2006/02/02 05:48:45  steve
- *  real-to-integer conversions round, not truncate.
- *
- * Revision 1.151  2006/02/02 02:44:00  steve
- *  Allow part selects of memory words in l-values.
- *
- * Revision 1.150  2005/11/26 17:16:05  steve
- *  Force instruction that can be indexed.
- *
- * Revision 1.149  2005/11/25 17:55:26  steve
- *  Put vec8 and vec4 nets into seperate net classes.
- *
- * Revision 1.148  2005/09/19 21:45:37  steve
- *  Spelling patches from Larry.
- *
- * Revision 1.147  2005/09/17 04:01:02  steve
- *  Add the load/v.p instruction.
- *
- * Revision 1.146  2005/09/14 02:50:07  steve
- *  Add word integer compares.
- *
- * Revision 1.145  2005/08/30 00:49:21  steve
- *  minor correction to address check in of_MOV1XZ
- *
- * Revision 1.144  2005/08/29 04:46:13  steve
- *  Minor cleanup.
- *
- * Revision 1.143  2005/08/27 03:28:57  steve
- *  Fix bit destination address in of_AND
- *
- * Revision 1.142  2005/08/27 02:34:42  steve
- *  Bring threads into the vvp_vector4_t structure.
- *
- * Revision 1.141  2005/06/26 01:57:22  steve
- *  Make bit masks of vector4_t 64bit aware.
- *
- * Revision 1.140  2005/06/19 18:42:00  steve
- *  Optimize the LOAD_VEC implementation.
- *
- * Revision 1.139  2005/06/14 01:44:10  steve
- *  Add the assign_v0_d instruction.
- *
- * Revision 1.138  2005/06/12 01:25:27  steve
- *  Remove useless references to functor.h
- *
- * Revision 1.137  2005/06/02 16:02:11  steve
- *  Add support for notif0/1 gates.
- *  Make delay nodes support inertial delay.
- *  Add the %force/link instruction.
- *
- * Revision 1.136  2005/05/17 20:51:06  steve
- *  Clean up instruction type reverences to bits.
- *
- * Revision 1.135  2005/05/07 03:15:42  steve
- *  Implement non-blocking part assign.
- *
- * Revision 1.134  2005/05/01 22:05:21  steve
- *  Add cassign/link instruction.
- *
- * Revision 1.133  2005/03/22 05:18:34  steve
- *  The indexed set can write a vector, not just a bit.
- *
- * Revision 1.132  2005/03/06 17:07:48  steve
- *  Non blocking assign to memory words.
- *
- * Revision 1.131  2005/03/05 05:45:18  steve
- *  Check that lead.mv vector width matches word.
- *
- * Revision 1.130  2005/03/03 04:33:10  steve
- *  Rearrange how memories are supported as vvp_vector4 arrays.
- *
- * Revision 1.129  2005/02/14 01:50:23  steve
- *  Signals may receive part vectors from %set/x0
- *  instructions. Re-implement the %set/x0 to do
- *  just that. Remove the useless %set/x0/x instruction.
- *
- * Revision 1.128  2005/02/12 06:13:22  steve
- *  Add debug dumps for vectors, and fix vvp_scaler_t make from BIT4_X values.
- *
- * Revision 1.127  2005/01/28 05:34:25  steve
- *  Add vector4 implementation of .arith/mult.
- *
- * Revision 1.126  2005/01/22 00:58:22  steve
- *  Implement the %load/x instruction.
- *
- * Revision 1.125  2004/12/17 04:47:47  steve
- *  Replace single release with release/net and release/reg.
- *
- * Revision 1.124  2004/12/15 17:17:42  steve
- *  Add the force/v instruction.
- *
- * Revision 1.123  2004/12/11 02:31:30  steve
- *  Rework of internals to carry vectors through nexus instead
- *  of single bits. Make the ivl, tgt-vvp and vvp initial changes
- *  down this path.
- *
- * Revision 1.122  2004/10/04 01:11:00  steve
- *  Clean up spurious trailing white space.
- *
- * Revision 1.121  2004/06/19 16:17:02  steve
- *  Watch type of mak bit matches masked value.
- *
- * Revision 1.120  2004/06/19 15:52:53  steve
- *  Add signed modulus operator.
- *
- * Revision 1.119  2004/06/04 23:26:34  steve
- *  Pick sign bit from the right place in the exponent number.
- *
- * Revision 1.118  2004/05/19 03:26:25  steve
- *  Support delayed/non-blocking assignment to reals and others.
- *
- * Revision 1.117  2003/11/10 20:19:32  steve
- *  Include config.h
- *
- * Revision 1.116  2003/09/26 02:15:15  steve
- *  Slight performance tweaks of scheduler.
- *
- * Revision 1.115  2003/09/01 04:03:38  steve
- *  32bit vs 64bit handling in SUBI.
- *
- * Revision 1.114  2003/08/01 00:58:03  steve
- *  Initialize allocated memory.
- *
- * Revision 1.113  2003/07/21 02:39:15  steve
- *  Overflow of unsigned when calculating unsigned long value.
- *
- * Revision 1.112  2003/07/03 20:03:36  steve
- *  Remove the vvp_cpoint_t indirect code pointer.
- *
- * Revision 1.111  2003/06/18 03:55:19  steve
- *  Add arithmetic shift operators.
- *
- * Revision 1.110  2003/06/17 21:28:59  steve
- *  Remove short int restrictions from vvp opcodes. (part 2)
- *
- * Revision 1.109  2003/06/17 19:17:42  steve
- *  Remove short int restrictions from vvp opcodes.
- *
- * Revision 1.108  2003/05/26 04:44:54  steve
- *  Add the set/x0/x instruction.
- *
- * Revision 1.107  2003/05/07 03:39:12  steve
- *  ufunc calls to functions can have scheduling complexities.
- *
- * Revision 1.106  2003/03/28 02:33:57  steve
- *  Add support for division of real operands.
- *
- * Revision 1.105  2003/03/13 04:36:57  steve
- *  Remove the obsolete functor delete functions.
- *
- * Revision 1.104  2003/02/27 20:36:29  steve
- *  Add the cvt/vr instruction.
- *
- * Revision 1.103  2003/02/22 06:26:58  steve
- *  When checking for stop, remember to reschedule.
- *
- * Revision 1.102  2003/02/22 02:52:06  steve
- *  Check for stopped flag in certain strategic points.
- *
- * Revision 1.101  2003/02/09 23:33:26  steve
- *  Spelling fixes.
- *
- * Revision 1.100  2003/02/06 17:41:47  steve
- *  Add the %sub/wr instruction.
  */