From d3573334d6d92ec0a486302c7203f6a37c38bbcb Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 23 May 2022 11:38:56 +0200 Subject: [PATCH] tgt-vvp: Handle signedness when passing struct member to system function Access to members in packed struct fields is internally implemented using a part select. vvp has a special syntax for passing a part select of a vector to a system function. This special syntax assumes that the part select is unsigned like it is for normal Verilog part selects. As a result passing a signed struct member to a system function will interpret it as unsigned. Add a check to make sure that the expression is actually unsigned. If it is not fall back to evaluating the expression on the vector stack and pass the value on the stack to the system function. Signed-off-by: Lars-Peter Clausen --- tgt-vvp/draw_vpi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tgt-vvp/draw_vpi.c b/tgt-vvp/draw_vpi.c index bbe6b542d..a49ffb308 100644 --- a/tgt-vvp/draw_vpi.c +++ b/tgt-vvp/draw_vpi.c @@ -199,6 +199,11 @@ static int get_vpi_taskfunc_signal_arg(struct args_info *result, if (ivl_expr_value(vexpr) == IVL_VT_DARRAY) return 0; + /* Part select is always unsigned. If the expression is signed + * fallback. */ + if (ivl_expr_signed(expr)) + return 0; + /* The signal is part of an array. */ /* Add &APV<> code here when it is finished. */ bexpr = ivl_expr_oper2(expr);