diff --git a/tgt-vhdl/process.cc b/tgt-vhdl/process.cc
index b8ae4c27d..f400a504b 100644
--- a/tgt-vhdl/process.cc
+++ b/tgt-vhdl/process.cc
@@ -25,6 +25,17 @@
 #include <cassert>
 #include <sstream>
 
+/*
+ * TODO: Explanation here.
+ */
+static string_list_t g_assign_vars;
+
+void blocking_assign_to(std::string var)
+{
+   std::cout << "blocking_assign_to " << var << std::endl;
+}
+
+
 /*
  * Convert a Verilog process to VHDL and add it to the architecture
  * of the given entity.
diff --git a/tgt-vhdl/stmt.cc b/tgt-vhdl/stmt.cc
index 1f5c57a11..c7e6adf59 100644
--- a/tgt-vhdl/stmt.cc
+++ b/tgt-vhdl/stmt.cc
@@ -178,13 +178,9 @@ static int draw_noop(vhdl_process *proc, stmt_container *container,
    return 0;
 }
 
-/*
- * A non-blocking assignment inside a process. The semantics for
- * this are essentially the same as VHDL's non-blocking signal
- * assignment.
- */
-static int draw_nbassign(vhdl_process *proc, stmt_container *container,
-                         ivl_statement_t stmt, vhdl_expr *after = NULL)
+template <class T>
+static int draw_generic_assign(vhdl_process *proc, stmt_container *container,
+                               ivl_statement_t stmt, vhdl_expr *after = NULL)
 {
    int nlvals = ivl_stmt_lvals(stmt);
    if (nlvals != 1) {
@@ -222,10 +218,10 @@ static int draw_nbassign(vhdl_process *proc, stmt_container *container,
          // The type here can be null as it is never actually needed
          vhdl_var_ref *lval_ref = new vhdl_var_ref(signame, NULL);
          
-         vhdl_nbassign_stmt *nbassign = new vhdl_nbassign_stmt(lval_ref, rhs);
+         T *assign = new T(lval_ref, rhs);
          if (after != NULL)
-            nbassign->set_after(after);
-         container->add_stmt(nbassign);
+            assign->set_after(after);
+         container->add_stmt(assign);
       }
    }
    else {
@@ -236,6 +232,26 @@ static int draw_nbassign(vhdl_process *proc, stmt_container *container,
    return 0;
 }
 
+/*
+ * A non-blocking assignment inside a process. The semantics for
+ * this are essentially the same as VHDL's non-blocking signal
+ * assignment.
+ */
+static int draw_nbassign(vhdl_process *proc, stmt_container *container,
+                         ivl_statement_t stmt, vhdl_expr *after = NULL)
+{
+   return draw_generic_assign<vhdl_nbassign_stmt>
+      (proc, container, stmt, after);
+}
+
+static int draw_assign(vhdl_process *proc, stmt_container *container,
+                       ivl_statement_t stmt)
+{
+   
+   
+   return 0;
+}
+
 /*
  * Delay statements are equivalent to the `wait for' form of the
  * VHDL wait statement.
@@ -415,7 +431,8 @@ int draw_stmt(vhdl_process *proc, stmt_container *container,
       return draw_block(proc, container, stmt);
    case IVL_ST_NOOP:
       return draw_noop(proc, container, stmt);
-   case IVL_ST_ASSIGN:   // TODO: remove!
+   case IVL_ST_ASSIGN:
+      return draw_assign(proc, container, stmt);
    case IVL_ST_ASSIGN_NB:
       return draw_nbassign(proc, container, stmt);
    case IVL_ST_DELAY:
diff --git a/tgt-vhdl/vhdl_syntax.cc b/tgt-vhdl/vhdl_syntax.cc
index f3737b20b..3cfcf6c0c 100644
--- a/tgt-vhdl/vhdl_syntax.cc
+++ b/tgt-vhdl/vhdl_syntax.cc
@@ -525,7 +525,7 @@ void vhdl_fcall::emit(std::ofstream &of, int level) const
    exprs_.emit(of, level);
 }
 
-vhdl_nbassign_stmt::~vhdl_nbassign_stmt()
+vhdl_abstract_assign_stmt::~vhdl_abstract_assign_stmt()
 {
    delete lhs_;
    delete rhs_;
diff --git a/tgt-vhdl/vhdl_syntax.hh b/tgt-vhdl/vhdl_syntax.hh
index 48beb159d..30399dfd2 100644
--- a/tgt-vhdl/vhdl_syntax.hh
+++ b/tgt-vhdl/vhdl_syntax.hh
@@ -227,23 +227,35 @@ private:
 };
 
 
+/*
+ * Shared between blocking and non-blocking assignment.
+ */
+class vhdl_abstract_assign_stmt : public vhdl_seq_stmt {
+public:
+   vhdl_abstract_assign_stmt(vhdl_var_ref *lhs, vhdl_expr *rhs)
+      : lhs_(lhs), rhs_(rhs), after_(NULL) {}
+   virtual ~vhdl_abstract_assign_stmt();
+
+   void set_after(vhdl_expr *after) { after_ = after; }
+protected:
+   vhdl_var_ref *lhs_;
+   vhdl_expr *rhs_, *after_;
+};                                                      
+
+
 /*
  * Similar to Verilog non-blocking assignment, except the LHS
  * must be a signal not a variable.
  */
-class vhdl_nbassign_stmt : public vhdl_seq_stmt {
+class vhdl_nbassign_stmt : public vhdl_abstract_assign_stmt {
 public:
    vhdl_nbassign_stmt(vhdl_var_ref *lhs, vhdl_expr *rhs)
-      : lhs_(lhs), rhs_(rhs), after_(NULL) {}
-   ~vhdl_nbassign_stmt();
-
-   void set_after(vhdl_expr *after) { after_ = after; }
+      : vhdl_abstract_assign_stmt(lhs, rhs) {}
+   
    void emit(std::ofstream &of, int level) const;
-private:
-   vhdl_var_ref *lhs_;
-   vhdl_expr *rhs_, *after_;
 };
 
+
 enum vhdl_wait_type_t {
    VHDL_WAIT_INDEF,    // Suspend indefinitely
    VHDL_WAIT_FOR_NS,   // Wait for a constant number of nanoseconds
diff --git a/tgt-vhdl/vhdl_target.h b/tgt-vhdl/vhdl_target.h
index d681afe53..0401c33e3 100644
--- a/tgt-vhdl/vhdl_target.h
+++ b/tgt-vhdl/vhdl_target.h
@@ -31,6 +31,8 @@ void rename_signal(ivl_signal_t sig, const std::string &renamed);
 const vhdl_entity *find_entity_for_signal(ivl_signal_t sig);
 const std::string &get_renamed_signal(ivl_signal_t sig);
 
+void blocking_assign_to(std::string var);
+
 
 #endif /* #ifndef INC_VHDL_TARGET_H */