diff --git a/vhdlpp/expression.h b/vhdlpp/expression.h index 40d352507..cd60165e8 100644 --- a/vhdlpp/expression.h +++ b/vhdlpp/expression.h @@ -279,6 +279,7 @@ class ExpInteger : public Expression { ExpInteger(int64_t val); ~ExpInteger(); + int elaborate_expr(Entity*ent, Architecture*arc, const VType*ltype); int emit(ostream&out, Entity*ent, Architecture*arc); bool is_primary(void) const; bool evaluate(ScopeBase*scope, int64_t&val) const; diff --git a/vhdlpp/expression_elaborate.cc b/vhdlpp/expression_elaborate.cc index 654702934..279fd5264 100644 --- a/vhdlpp/expression_elaborate.cc +++ b/vhdlpp/expression_elaborate.cc @@ -175,6 +175,19 @@ int ExpConditional::elaborate_expr(Entity*ent, Architecture*arc, const VType*lty return errors; } +int ExpInteger::elaborate_expr(Entity*ent, Architecture*arc, const VType*ltype) +{ + int errors = 0; + + if (ltype == 0) { + ltype = probe_type(ent, arc); + } + + assert(ltype != 0); + + return errors; +} + int ExpLogical::elaborate_expr(Entity*ent, Architecture*arc, const VType*ltype) { int errors = 0; diff --git a/vhdlpp/sequential.h b/vhdlpp/sequential.h index 45c9b1ab6..5799a5ea4 100644 --- a/vhdlpp/sequential.h +++ b/vhdlpp/sequential.h @@ -46,6 +46,10 @@ class IfSequential : public SequentialStmt { Elsif(Expression*cond, std::list*tr); ~Elsif(); + int elaborate(Entity*entity, Architecture*arc); + int condition_emit(ostream&out, Entity*entity, Architecture*arc); + int statement_emit(ostream&out, Entity*entity, Architecture*arc); + void dump(ostream&out, int indent) const; private: diff --git a/vhdlpp/sequential_elaborate.cc b/vhdlpp/sequential_elaborate.cc index 4229bc91d..e6f72180c 100644 --- a/vhdlpp/sequential_elaborate.cc +++ b/vhdlpp/sequential_elaborate.cc @@ -36,6 +36,11 @@ int IfSequential::elaborate(Entity*ent, Architecture*arc) errors += (*cur)->elaborate(ent, arc); } + for (list::iterator cur = elsif_.begin() + ; cur != elsif_.end() ; ++cur) { + errors += (*cur)->elaborate(ent, arc); + } + for (list::iterator cur = else_.begin() ; cur != else_.end() ; ++cur) { errors += (*cur)->elaborate(ent, arc); @@ -44,6 +49,20 @@ int IfSequential::elaborate(Entity*ent, Architecture*arc) return errors; } +int IfSequential::Elsif::elaborate(Entity*ent, Architecture*arc) +{ + int errors = 0; + + errors += cond_->elaborate_expr(ent, arc, 0); + + for (list::iterator cur = if_.begin() + ; cur != if_.end() ; ++cur) { + errors += (*cur)->elaborate(ent, arc); + } + + return errors; +} + int SignalSeqAssignment::elaborate(Entity*ent, Architecture*arc) { int errors = 0; diff --git a/vhdlpp/sequential_emit.cc b/vhdlpp/sequential_emit.cc index e2f792124..ede823246 100644 --- a/vhdlpp/sequential_emit.cc +++ b/vhdlpp/sequential_emit.cc @@ -22,7 +22,7 @@ # include # include -int SequentialStmt::emit(ostream&out, Entity*ent, Architecture*arc) +int SequentialStmt::emit(ostream&out, Entity*, Architecture*) { out << " // " << get_fileline() << ": internal error: " << "I don't know how to emit this sequential statement! " @@ -39,14 +39,22 @@ int IfSequential::emit(ostream&out, Entity*ent, Architecture*arc) for (list::iterator cur = if_.begin() ; cur != if_.end() ; ++cur) - (*cur)->emit(out, ent, arc); + errors += (*cur)->emit(out, ent, arc); + + for (list::iterator cur = elsif_.begin() + ; cur != elsif_.end() ; ++cur) { + out << "end else if ("; + errors += (*cur)->condition_emit(out, ent, arc); + out << ") begin" << endl; + errors += (*cur)->statement_emit(out, ent, arc); + } if (else_.size() > 0) { out << "end else begin" << endl; for (list::iterator cur = else_.begin() ; cur != else_.end() ; ++cur) - (*cur)->emit(out, ent, arc); + errors += (*cur)->emit(out, ent, arc); } @@ -54,6 +62,23 @@ int IfSequential::emit(ostream&out, Entity*ent, Architecture*arc) return errors; } +int IfSequential::Elsif::condition_emit(ostream&out, Entity*ent, Architecture*arc) +{ + return cond_->emit(out, ent, arc); +} + +int IfSequential::Elsif::statement_emit(ostream&out, Entity*ent, Architecture*arc) +{ + int errors = 0; + + for (list::iterator cur = if_.begin() + ; cur != if_.end() ; ++cur) + errors += (*cur)->emit(out, ent, arc); + + return errors; +} + + int SignalSeqAssignment::emit(ostream&out, Entity*ent, Architecture*arc) { int errors = 0;