From fbbff9646d9a4d9b562985d77944882fcb00c975 Mon Sep 17 00:00:00 2001 From: Johan Euphrosine Date: Mon, 23 Oct 2023 16:00:38 +0900 Subject: [PATCH 1/5] ivtest: add array_slice_concat --- ivtest/ivltests/array_slice_concat.v | 17 +++++++++++++++++ ivtest/regress-vlg.list | 1 + 2 files changed, 18 insertions(+) create mode 100644 ivtest/ivltests/array_slice_concat.v diff --git a/ivtest/ivltests/array_slice_concat.v b/ivtest/ivltests/array_slice_concat.v new file mode 100644 index 000000000..1421d0733 --- /dev/null +++ b/ivtest/ivltests/array_slice_concat.v @@ -0,0 +1,17 @@ +module ArraySliceWithNarrowStart( + input wire [159:0] a, + input wire start, + output wire [95:0] out +); + wire [31:0] a_unflattened[0:4]; + assign a_unflattened[0] = a[31:0]; + assign a_unflattened[1] = a[63:32]; + assign a_unflattened[2] = a[95:64]; + assign a_unflattened[3] = a[127:96]; + assign a_unflattened[4] = a[159:128]; + wire [31:0] array_slice_6[0:2]; + assign array_slice_6[0] = a_unflattened[{2'h0, start} > 3'h4 ? 3'h4 : {2'h0, start} + 3'h0]; + assign array_slice_6[1] = a_unflattened[{2'h0, start} > 3'h3 ? 3'h4 : {2'h0, start} + 3'h1]; + assign array_slice_6[2] = a_unflattened[{2'h0, start} > 3'h2 ? 3'h4 : {2'h0, start} + 3'h2]; + assign out = {array_slice_6[2], array_slice_6[1], array_slice_6[0]}; +endmodule diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list index 8dd34a0fa..7fd55bf10 100644 --- a/ivtest/regress-vlg.list +++ b/ivtest/regress-vlg.list @@ -157,6 +157,7 @@ array_select_a normal ivltests array_word_check normal ivltests gold=array_word_check.gold array_word_width normal ivltests gold=array_word_width.gold array_word_width2 normal ivltests +array_slice_concat normal ivltests assign3.2A normal ivltests assign3.2B normal ivltests assign3.2C normal ivltests From 0b22810a257ed2b5c72a2f31ba440ff78311539b Mon Sep 17 00:00:00 2001 From: Johan Euphrosine Date: Thu, 26 Oct 2023 11:30:56 +0900 Subject: [PATCH 2/5] ivtests/array_slice_contact: add tb --- ivtest/ivltests/array_slice_concat.v | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/ivtest/ivltests/array_slice_concat.v b/ivtest/ivltests/array_slice_concat.v index 1421d0733..7fca2417d 100644 --- a/ivtest/ivltests/array_slice_concat.v +++ b/ivtest/ivltests/array_slice_concat.v @@ -15,3 +15,21 @@ module ArraySliceWithNarrowStart( assign array_slice_6[2] = a_unflattened[{2'h0, start} > 3'h2 ? 3'h4 : {2'h0, start} + 3'h2]; assign out = {array_slice_6[2], array_slice_6[1], array_slice_6[0]}; endmodule + +module top; + reg [159:0] a; + reg start; + wire [95:0] out; + + ArraySliceWithNarrowStart dut(.a(a), .start(start), .out(out)); + + initial begin + a = {32'h44444444, 32'h33333333, 32'h22222222, 32'h11111111}; + start = 1; + if (out !== 96'h444444443333333322222222) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end +endmodule From 2e00a7d48211d9d538d9a14ff46b28c642783dc8 Mon Sep 17 00:00:00 2001 From: Johan Euphrosine Date: Mon, 30 Oct 2023 18:25:46 +0900 Subject: [PATCH 3/5] ivtests/array_slice_contact: add test manifest --- ivtest/regress-vlg.list | 1 - ivtest/vvp_tests/array_slice_concat.json | 4 ++++ 2 files changed, 4 insertions(+), 1 deletion(-) create mode 100644 ivtest/vvp_tests/array_slice_concat.json diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list index 7fd55bf10..8dd34a0fa 100644 --- a/ivtest/regress-vlg.list +++ b/ivtest/regress-vlg.list @@ -157,7 +157,6 @@ array_select_a normal ivltests array_word_check normal ivltests gold=array_word_check.gold array_word_width normal ivltests gold=array_word_width.gold array_word_width2 normal ivltests -array_slice_concat normal ivltests assign3.2A normal ivltests assign3.2B normal ivltests assign3.2C normal ivltests diff --git a/ivtest/vvp_tests/array_slice_concat.json b/ivtest/vvp_tests/array_slice_concat.json new file mode 100644 index 000000000..f152dc00d --- /dev/null +++ b/ivtest/vvp_tests/array_slice_concat.json @@ -0,0 +1,4 @@ +{ + "type" : "normal", + "source" : "array_slice_concat.v" +} From 0a53b52ed0455e39f4a7c7d790c3eab6851de0c7 Mon Sep 17 00:00:00 2001 From: Johan Euphrosine Date: Wed, 20 Dec 2023 22:18:56 +0900 Subject: [PATCH 4/5] ivtest/regress-vvp: add array_slice_concat --- ivtest/regress-vvp.list | 1 + 1 file changed, 1 insertion(+) diff --git a/ivtest/regress-vvp.list b/ivtest/regress-vvp.list index 81a6d9fec..0dccca4a7 100644 --- a/ivtest/regress-vvp.list +++ b/ivtest/regress-vvp.list @@ -7,6 +7,7 @@ always4B vvp_tests/always4B.json analog1 vvp_tests/analog1.json analog2 vvp_tests/analog2.json array_packed_write_read vvp_tests/array_packed_write_read.json +array_slice_concat vvp_tests/array_slice_concat.json automatic_error11 vvp_tests/automatic_error11.json automatic_error12 vvp_tests/automatic_error12.json automatic_error13 vvp_tests/automatic_error13.json From 724a88f5233739a6b1378d3aac6422891aef4c96 Mon Sep 17 00:00:00 2001 From: Cary R Date: Mon, 1 Jan 2024 11:01:19 -0800 Subject: [PATCH 5/5] Update array_slice_concat.v Add delay to avoid race in TB code and DUT code --- ivtest/ivltests/array_slice_concat.v | 1 + 1 file changed, 1 insertion(+) diff --git a/ivtest/ivltests/array_slice_concat.v b/ivtest/ivltests/array_slice_concat.v index 7fca2417d..ced19865b 100644 --- a/ivtest/ivltests/array_slice_concat.v +++ b/ivtest/ivltests/array_slice_concat.v @@ -26,6 +26,7 @@ module top; initial begin a = {32'h44444444, 32'h33333333, 32'h22222222, 32'h11111111}; start = 1; + #1; if (out !== 96'h444444443333333322222222) begin $display("FAILED"); $finish;