diff --git a/main.cc b/main.cc
index ba17f19cb..ec6132e28 100644
--- a/main.cc
+++ b/main.cc
@@ -19,7 +19,7 @@ const char COPYRIGHT[] =
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: main.cc,v 1.38 2000/09/12 01:17:40 steve Exp $"
+#ident "$Id: main.cc,v 1.39 2000/11/22 20:48:32 steve Exp $"
 #endif
 
 const char NOTICE[] =
@@ -247,6 +247,11 @@ int main(int argc, char*argv[])
 	    return rc;
       }
 
+
+	/* If the user did not give a specific module to start with,
+	   then look for the single module that has no ports. If there
+	   are multiple modules with no ports, then give up. */
+
       if (start_module == "") {
 	    for (map<string,Module*>::iterator mod = modules.begin()
 		       ; mod != modules.end()
@@ -263,20 +268,36 @@ int main(int argc, char*argv[])
 	    }
       }
 
-	/* Select a root module, and elaborate the design. */
+	/* If the previous attempt to find a start module failed, but
+	   there is only one module, then just let the user get away
+	   with it. */
+
+      if ((start_module == "") && (modules.size() == 1)) {
+	    map<string,Module*>::iterator mod = modules.begin();
+	    Module*cur = (*mod).second;
+	    start_module = cur->get_name();
+      }
+
+	/* If there is *still* no guess for the root module, then give
+	   up completely, and complain. */
+
       if (start_module == "") {
 	    cerr << "No top level modules, and no -s option." << endl;
 	    return 1;
       }
 
+
+	/* On with the process of elaborating the module. */
       Design*des = elaborate(modules, primitives, start_module);
       if (des == 0) {
-	    cerr << "Unable to elaborate module " << start_module <<
-		  "." << endl;
+	    cerr << start_module << ": error: "
+		 << "Unable to elaborate module." << endl;
 	    return 1;
       }
+
       if (des->errors) {
-	    cerr << des->errors << " error(s) elaborating design." << endl;
+	    cerr << start_module << ": error: " << des->errors
+		 << " elaborating module." << endl;
 	    return des->errors;
       }
 
@@ -306,6 +327,9 @@ int main(int argc, char*argv[])
 
 /*
  * $Log: main.cc,v $
+ * Revision 1.39  2000/11/22 20:48:32  steve
+ *  Allow sole module to be a root.
+ *
  * Revision 1.38  2000/09/12 01:17:40  steve
  *  Version information for vlog_vpi_info.
  *
@@ -337,93 +361,5 @@ int main(int argc, char*argv[])
  *  Get synthesis working with the NetEvWait class,
  *  and get started supporting multiple events in a
  *  wait in vvm.
- *
- * Revision 1.30  2000/03/17 21:50:25  steve
- *  Switch to control warnings.
- *
- * Revision 1.29  2000/02/23 02:56:54  steve
- *  Macintosh compilers do not support ident.
- *
- * Revision 1.28  2000/01/13 05:11:25  steve
- *  Support for multiple VPI modules.
- *
- * Revision 1.27  1999/12/30 17:37:14  steve
- *  Remove the now useless sigfold functor.
- *
- * Revision 1.26  1999/11/29 17:02:21  steve
- *  include getopt if present.
- *
- * Revision 1.25  1999/11/18 03:52:19  steve
- *  Turn NetTmp objects into normal local NetNet objects,
- *  and add the nodangle functor to clean up the local
- *  symbols generated by elaboration and other steps.
- *
- * Revision 1.24  1999/11/01 02:07:40  steve
- *  Add the synth functor to do generic synthesis
- *  and add the LPM_FF device to handle rows of
- *  flip-flops.
- *
- * Revision 1.23  1999/09/22 16:57:23  steve
- *  Catch parallel blocks in vvm emit.
- *
- * Revision 1.22  1999/08/03 04:14:49  steve
- *  Parse into pform arbitrarily complex module
- *  port declarations.
- *
- * Revision 1.21  1999/07/18 05:52:46  steve
- *  xnfsyn generates DFF objects for XNF output, and
- *  properly rewrites the Design netlist in the process.
- *
- * Revision 1.20  1999/07/17 22:01:13  steve
- *  Add the functor interface for functor transforms.
- *
- * Revision 1.19  1999/07/10 23:29:21  steve
- *  pform even on parse errors.
- *
- * Revision 1.18  1999/06/19 03:46:42  steve
- *  Add the -v switch.
- *
- * Revision 1.17  1999/06/17 05:33:12  steve
- *  Redundant declaration of pform_parse.
- *
- * Revision 1.16  1999/06/15 03:44:53  steve
- *  Get rid of the STL vector template.
- *
- * Revision 1.15  1999/05/05 03:27:15  steve
- *  More intelligent selection of module to elaborate.
- *
- * Revision 1.14  1999/04/23 04:34:32  steve
- *  Make debug output file parameters.
- *
- * Revision 1.13  1999/02/01 00:26:49  steve
- *  Carry some line info to the netlist,
- *  Dump line numbers for processes.
- *  Elaborate prints errors about port vector
- *  width mismatch
- *  Emit better handles null statements.
- *
- * Revision 1.12  1999/01/24 01:35:36  steve
- *  Support null target for generating no output.
- *
- * Revision 1.11  1998/12/20 02:05:41  steve
- *  Function to calculate wire initial value.
- *
- * Revision 1.10  1998/12/09 04:02:47  steve
- *  Support the include directive.
- *
- * Revision 1.9  1998/12/07 04:53:17  steve
- *  Generate OBUF or IBUF attributes (and the gates
- *  to garry them) where a wire is a pad. This involved
- *  figuring out enough of the netlist to know when such
- *  was needed, and to generate new gates and signales
- *  to handle what's missing.
- *
- * Revision 1.8  1998/12/02 04:37:13  steve
- *  Add the nobufz function to eliminate bufz objects,
- *  Object links are marked with direction,
- *  constant propagation is more careful will wide links,
- *  Signal folding is aware of attributes, and
- *  the XNF target can dump UDP objects based on LCA
- *  attributes.
  */