diff --git a/driver/iverilog.man b/driver/iverilog.man index e795ee8f5..38bcedff5 100644 --- a/driver/iverilog.man +++ b/driver/iverilog.man @@ -24,7 +24,7 @@ types are added as code generators are implemented. The \fIiverilog\fP program uses external programs and configuration files to preprocess and compile the Verilog source. Normally, the path used to locate these tools is built into the \fIiverilog\fP -program. However, the \fB-B\fP switch allows the user to select a +program. However, the \fB\-B\fP switch allows the user to select a different set of programs. The path given is used to locate \fIivlpp\fP, \fIivl\fP, code generators and the VPI modules. .TP 8 @@ -43,7 +43,7 @@ Verilog source. Defines macro \fImacro\fP as \fIdefn\fP. .TP 8 .B -d\fIname\fP -Activate a class of compiler debugging messages. The \fB-d\fP switch may +Activate a class of compiler debugging messages. The \fB\-d\fP switch may be used as often as necessary to activate all the desired messages. Supported names are scopes, eval_tree, elaborate, and synth2; any other names are ignored. @@ -56,16 +56,16 @@ Verilog source for use by other compilers. .TP 8 .B -g1995\fI|\fP-g2001\fI|\fP-g2001-noconfig\fI|\fP-g2005 Select the Verilog language \fIgeneration\fP to support in the -compiler. This selects between \fIIEEE1364-1995\fP, -\fIIEEE1364-2001\fP, or \fIIEEE1364-2005\fP. Normally, +compiler. This selects between \fIIEEE1364\-1995\fP, +\fIIEEE1364\-2001\fP, or \fIIEEE1364\-2005\fP. Normally, Icarus Verilog defaults to the latest known generation of the language. This flag is most useful to restrict the language to a set supported by tools of specific generations, for compatibility with other tools. .TP 8 .B -gverilog-ams\fI|\fP-gno-verilog-ams -Enable or disable (default) support for Verilog-AMS. -Very little Verilog-AMS specific functionality is currently supported. +Enable or disable (default) support for Verilog\-AMS. +Very little Verilog\-AMS specific functionality is currently supported. .TP 8 .B -gsystem-verilog\fI|\fP-gno-system-verilog Enable or disable (default) support for SystemVerilog. @@ -104,7 +104,7 @@ The standards requires that a vectored port have matching ranges for its port declaration as well as any net/register declaration. It was common practice in the past to only specify the range for the net/register declaration and some tools still allow this. By default any mismatch is -reported as a error. Using \fB-gno-io-range-error\fP will produce a +reported as a error. Using \fB\-gno\-io\-range\-error\fP will produce a warning instead of a fatal error for the case of a vectored net/register and a scalar port declaration. .TP 8 @@ -115,17 +115,17 @@ default, parts of the expression that do not depend on the changed input value(s) are not re-evaluated. If an expression contains a call to a function that doesn't depend solely on its input values or that has side effects, the resulting behavior will differ from that -required by the standard. Using \fI-gstrict-ca-eval\fP will force +required by the standard. Using \fI\-gstrict\-ca\-eval\fP will force standard compliant behavior (with some loss in performance). .TP 8 .B -I\fIincludedir\fP Append directory \fIincludedir\fP to list of directories searched -for Verilog include files. The \fB-I\fP switch may be used many times +for Verilog include files. The \fB\-I\fP switch may be used many times to specify several directories to search, the directories are searched in the order they appear on the command line. .TP 8 .B -M\fIpath\fP -This is equivalent to \fB-Mall=path\fP. Preserved for backwards +This is equivalent to \fB\-Mall=path\fP. Preserved for backwards compatibility. .TP 8 .B -M\fImode=path\fP @@ -159,7 +159,7 @@ Place output in the file \fIfilename\fP. If no output file name is specified, \fIiverilog\fP uses the default name \fBa.out\fP. .TP 8 .B -p\fIflag=value\fP -Assign a value to a target specific flag. The \fB-p\fP switch may be +Assign a value to a target specific flag. The \fB\-p\fP switch may be used as often as necessary to specify all the desired flags. The flags that are used depend on the target that is selected, and are described in target specific documentation. Flags that are not used are ignored. @@ -167,15 +167,15 @@ in target specific documentation. Flags that are not used are ignored. .B -S Synthesize. Normally, if the target can accept behavioral descriptions the compiler will leave processes in behavioral -form. The \fB-S\fP switch causes the compiler to perform synthesis +form. The \fB\-S\fP switch causes the compiler to perform synthesis even if it is not necessary for the target. If the target type is a -netlist format, the \fB-S\fP switch is unnecessary and has no effect. +netlist format, the \fB\-S\fP switch is unnecessary and has no effect. .TP 8 .B -s \fItopmodule\fP Specify the top level module to elaborate. Icarus Verilog will by default choose modules that are not instantiated in any other modules, but sometimes that is not sufficient, or instantiates too many modules. If -the user specifies one or more root modules with \fB-s\fP flags, then +the user specifies one or more root modules with \fB\-s\fP flags, then they will be used as root modules instead. .TP 8 .B -T\fImin|typ|max\fP @@ -205,7 +205,7 @@ Print the version of the compiler, and exit. .B -W\fIclass\fP Turn on different classes of warnings. See the \fBWARNING TYPES\fP section below for descriptions of the different warning groups. If -multiple \fB-W\fP switches are used, the warning set is the union of +multiple \fB\-W\fP switches are used, the warning set is the union of all the requested classes. .TP 8 .B -y\fIlibdir\fP @@ -235,7 +235,7 @@ library or in the main design. .SH TARGETS The Icarus Verilog compiler supports a variety of targets, for -different purposes, and the \fB-t\fP switch is used to select the +different purposes, and the \fB\-t\fP switch is used to select the desired target. .TP 8 @@ -253,7 +253,7 @@ This is a synthesis target that supports a variety of fpga devices, mostly by EDIF format output. The Icarus Verilog fpga code generator can generate complete designs or EDIF macros that can in turn be imported into larger designs by other tools. The \fBfpga\fP target -implies the synthesis \fB-S\fP flag. +implies the synthesis \fB\-S\fP flag. .TP 8 .B vhdl This target produces a VHDL translation of the Verilog netlist. The @@ -262,15 +262,15 @@ the modules in the Verilog source code. Note that only a subset of the Verilog language is supported. See the wiki for more information. .SH "WARNING TYPES" -These are the types of warnings that can be selected by the \fB-W\fP +These are the types of warnings that can be selected by the \fB\-W\fP switch. All the warning types (other than \fBall\fP) can also be -prefixed with \fBno-\fP to turn off that warning. This is most useful -after a \fB-Wall\fP argument to suppress isolated warning types. +prefixed with \fBno\-\fP to turn off that warning. This is most useful +after a \fB\-Wall\fP argument to suppress isolated warning types. .TP 8 .B all -This enables the implicit, portbind, select-range, timescale, and -sensitivity-entire-array warning categories. +This enables the implicit, portbind, select\-range, timescale, and +sensitivity\-entire\-array warning categories. .TP 8 .B implicit @@ -302,7 +302,7 @@ and dependent on compilation order. .B infloop This enables warnings for \fRalways\fP statements that may have runtime infinite loops (has paths with no or zero delay). This class of warnings -is not included in \fB-Wall\fP and hence does not have a \fBno-\fP variant. +is not included in \fB\-Wall\fP and hence does not have a \fBno\-\fP variant. A fatal error message will always be printed when the compiler can determine that there will definitely be an infinite loop (all paths have no or zero delay). @@ -370,14 +370,14 @@ character. Variables are substituted in file names. .TP 8 .B -c\ \fIcmdfile\fP -f\ \fIcmdfile\fP -A \fB-c\fP or \fB-f\fP token prefixes a command file, exactly like it +A \fB\-c\fP or \fB\-f\fP token prefixes a command file, exactly like it does on the command line. The cmdfile may be on the same line or the next non-comment line. .TP 8 .B -y\ \fIlibdir\fP -A \fB-y\fP token prefixes a library directory in the command file, -exactly like it does on the command line. The parameter to the \fB-y\fP +A \fB\-y\fP token prefixes a library directory in the command file, +exactly like it does on the command line. The parameter to the \fB\-y\fP flag may be on the same line or the next non-comment line. Variables in the \fIlibdir\fP are substituted. @@ -385,7 +385,7 @@ Variables in the \fIlibdir\fP are substituted. .TP 8 .B +incdir+\fIincludedir\fP The \fB+incdir+\fP token in command files gives directories to search -for include files in much the same way that \fB-I\fP flags work on the +for include files in much the same way that \fB\-I\fP flags work on the command line. The difference is that multiple \fI+includedir\fP directories are valid parameters to a single \fB+incdir+\fP token, although you may also have multiple \fB+incdir+\fP lines. @@ -396,7 +396,7 @@ Variables in the \fIincludedir\fP are substituted. .B +libext+\fIext\fP The \fB+libext\fP token in command files fives file extensions to try when looking for a library file. This is useful in conjunction with -\fB-y\fP flags to list suffixes to try in each directory before moving +\fB\-y\fP flags to list suffixes to try in each directory before moving on to the next library directory. .TP 8 @@ -413,7 +413,7 @@ letters are correct. For example, "foo" matches "Foo.v" but not .TP 8 .B +define+\fINAME\fP=\fIvalue\fP -The \fB+define+\fP token is the same as the \fB-D\fP option on the +The \fB+define+\fP token is the same as the \fB\-D\fP option on the command line. The value part of the token is optional. .TP 8 @@ -425,7 +425,7 @@ become munged. .TP 8 .B +tolower-filename\fP -This is similar to the \fB+toupper-filename\fP hack described above. +This is similar to the \fB+toupper\-filename\fP hack described above. .TP 8 .B +integer-width+\fIvalue\fP @@ -455,7 +455,7 @@ This is defined always when compiling with Icarus Verilog. .TP 8 .B __VAMS_ENABLE__ = 1\fp -This is defined if Verilog-AMS is enabled. +This is defined if Verilog\-AMS is enabled. .SH EXAMPLES These examples assume that you have a Verilog source file called hello.v in @@ -486,7 +486,7 @@ Tips on using, debugging, and developing the compiler can be found at .SH COPYRIGHT .nf -Copyright \(co 2002-2009 Stephen Williams +Copyright \(co 2002\-2009 Stephen Williams This document can be freely redistributed according to the terms of the GNU General Public License version 2.0 diff --git a/iverilog-vpi.man b/iverilog-vpi.man index 53797e2cb..f6e40aa4a 100644 --- a/iverilog-vpi.man +++ b/iverilog-vpi.man @@ -9,7 +9,7 @@ iverilog-vpi - Compile front end for VPI modules .SH DESCRIPTION .PP -\fIiverilog-vpi\fP is a tool to simplify the compilation of VPI +\fIiverilog\-vpi\fP is a tool to simplify the compilation of VPI modules for use with Icarus Verilog. It takes on the command line a list of C or C++ source files, and generates as output a linked VPI module. See the \fBvvp\fP(1) man page for a description of how the @@ -20,7 +20,7 @@ first source file is named \fIfoo.c\fP, the output becomes \fIfoo.vpi\fP. .SH OPTIONS -\fIiverilog-vpi\fP accepts the following options: +\fIiverilog\-vpi\fP accepts the following options: .TP 8 .B -l\fIlibrary\fP Include the named library in the link of the VPI module. This allows @@ -53,7 +53,7 @@ These flags provide compile time information. .SH "PC-ONLY OPTIONS" -The PC port of \fIiverilog-vpi\fP includes two special flags needed to +The PC port of \fIiverilog\-vpi\fP includes two special flags needed to support the more intractable development environment. These flags help the program locate parts that it needs. @@ -61,7 +61,7 @@ the program locate parts that it needs. .B -mingw=\fIpath\fP Tell the program the root of the Mingw compiler tool suite. The \fBvvp\fP runtime is compiled with this compiler, and this is the -compiler that \fIiverilog-vpi\fP expects to use to compile your source +compiler that \fIiverilog\-vpi\fP expects to use to compile your source code. This is normally not needed, and if you do use it, it is only needed once. The compiler will save the \fIpath\fP in the registry for use later. @@ -75,7 +75,7 @@ stored in the registry for future use. .SH "UNIX-ONLY OPTIONS" -The UNIX version of \fIiverilog-vpi\fP includes additional flags to +The UNIX version of \fIiverilog\-vpi\fP includes additional flags to let Makefile gurus peek at the configuration of the \fIiverilog\fP installation. This way, Makefiles can be written that handle complex VPI builds natively, and without hard-coding values that depend on the @@ -128,7 +128,7 @@ iverilog(1), vvp(1), .SH COPYRIGHT .nf -Copyright \(co 2002-2008 Stephen Williams +Copyright \(co 2002\-2009 Stephen Williams This document can be freely redistributed according to the terms of the GNU General Public License version 2.0 diff --git a/tgt-fpga/iverilog-fpga.man b/tgt-fpga/iverilog-fpga.man index a9f263a9c..6459ceaf9 100644 --- a/tgt-fpga/iverilog-fpga.man +++ b/tgt-fpga/iverilog-fpga.man @@ -1,6 +1,6 @@ .TH iverilog-fpga 1 "$Date: 2004/10/04 01:10:57 $" Version "$Date: 2004/10/04 01:10:57 $" .SH NAME -iverilog-fpga \- FPGA code generator for Icarus Verilog +iverilog-fpga - FPGA code generator for Icarus Verilog .SH SYNOPSIS .B iverilog -tfpga @@ -14,20 +14,19 @@ of the device, and the detailed part name. The architecture is used to select library primitives, and the detailed part name is written into the generated file for the use of downstream tools. -The code generator is invoked with the -tfpga flag to iverilog. It +The code generator is invoked with the \-tfpga flag to iverilog. It understands the part= and the arch= parameters, which can be set with -the -p flag of iverilog: +the \-p flag of iverilog: - iverilog -parch=virtex -ppart=v50-pq240-6 -tfpga foo.vl + iverilog \-parch=virtex \-ppart=v50\-pq240\-6 \-tfpga foo.vl This example selects the Virtex architecture, and give the detailed -part number as v50-pq240-6. The output is written into a.out unless a -different output file is specified with the -o flag. +part number as v50\-pq240\-6. The output is written into a.out unless a +different output file is specified with the \-o flag. .SH OPTIONS -.l -\fIiverilog -tfpga\fP accepts the following options: +\fIiverilog \-tfpga\fP accepts the following options: .TP 8 .B -parch=\fIfamily\fP The \fIfamily\fP setting further specifies the target device @@ -63,7 +62,7 @@ should work properly for any Virtex part. .TP 8 .B virtex2 If this is selected, then the output is EDIF 2 0 0 suitable for -Virtex-II and Virtex-II Pro devices. It uses the VIRTEX2 library, but +Virtex\-II and Virtex\-II Pro devices. It uses the VIRTEX2 library, but is very similar to the Virtex target. .SH "EDIF ROOT PORTS" @@ -74,7 +73,7 @@ definition into the design. (This is *not* the same as the PADS of a part.) The generated EDIF interface section contains port definitions, including the proper direction marks. -With the (rename ...) s-exp in EDIF, it is possible to assign +With the (rename ...) s\-exp in EDIF, it is possible to assign arbitrary text to port names. The EDIF code generator therefore does not resort to the mangling that is needed for internal symbols. The base name of the signal that is an input or output is used as the name @@ -123,7 +122,7 @@ example: .fi In this example, port ``out'' is assigned to pin 10, and port ``in'' -is assigned to pins 20-22. If the architecture supports it, a pin +is assigned to pins 20\-22. If the architecture supports it, a pin number of 0 means let the back end tools choose a pin. The format of the pin number depends on the architecture family being targeted, so for example Xilinx family devices take the name that is associated @@ -164,11 +163,11 @@ device pins are connected. Compile a single-file design with command line tools like so: .nf - % iverilog -parch=virtex -o foo.edf foo.vl + % iverilog \-parch=virtex \-o foo.edf foo.vl % edif2ngd foo.edf foo.ngo - % ngdbuild -p v50-pq240 foo.ngo foo.ngd - % map -o map.ncd foo.ngd - % par -w map.ncd foo.ncd + % ngdbuild \-p v50\-pq240 foo.ngo foo.ngd + % map \-o map.ncd foo.ngd + % par \-w map.ncd foo.ncd .fi .SH "AUTHOR" diff --git a/vvp/vvp.man b/vvp/vvp.man index c53c4fd0c..3524bc02e 100644 --- a/vvp/vvp.man +++ b/vvp/vvp.man @@ -18,7 +18,7 @@ command is not by itself executable on any platform. Instead, the .TP 8 .B -l\fIlogfile\fP This flag specifies a logfile where all MCI output goes. -Specify logfile as '-' to send log output to . $display and +Specify logfile as '\-' to send log output to . $display and friends send their output both to and . .TP 8 .B -M\fIpath\fP @@ -41,12 +41,12 @@ character, then the search path is not scanned and the name is assumed to be a complete file name. .TP 8 .B -n -This flag makes $stop or a a synonym for $finish. +This flag makes $stop or a a synonym for $finish. It can be used to give the program a more meaningful interface when running in a non-interactive environment. .TP 8 .B -N -This flag does the same thing as -n, but results in an exit code +This flag does the same thing as \-n, but results in an exit code of 1 if the stimulation calls $stop. It can be used to indicate a simulation failure when running a testbench. .TP 8 @@ -89,9 +89,9 @@ maximally compatible with third party tools that read waveform dumps. .TP 8 .B -lxt\fR|\fP-lxt-speed\fR|\fP-lxt-space These extended arguments set the wave dump format to lxt, possibly with -format optimizations. The \fB-lxt-space\fP flag sets the output +format optimizations. The \fB\-lxt\-space\fP flag sets the output format to lxt with full compression enabled. The resulting files are -quite small. The \fB-lxt-speed\fP chooses the lxt compression mode +quite small. The \fB\-lxt\-speed\fP chooses the lxt compression mode that leads to the best execution time and the fastest read time, at the expense of some file size. @@ -138,7 +138,7 @@ output, a time-saver for regression tests. .SH INTERACTIVE MODE .PP The simulation engine supports an interactive mode. The user may -interrupt the simulation (typically by typing Ctrl-C) to get to the +interrupt the simulation (typically by typing ) to get to the interactive prompt. From that prompt, the \fIhelp\fP command prints a brief summary of the available commands. .PP @@ -153,12 +153,12 @@ Steve Williams (steve@icarus.com) .SH SEE ALSO iverilog(1), -iverilog-vpi(1), +iverilog\-vpi(1), .BR "" .SH COPYRIGHT .nf -Copyright \(co 2001-2008 Stephen Williams +Copyright \(co 2001\-2009 Stephen Williams This document can be freely redistributed according to the terms of the GNU General Public License version 2.0