diff --git a/tgt-vhdl/support.hh b/tgt-vhdl/support.hh
index 2f55416e1..1487cb036 100644
--- a/tgt-vhdl/support.hh
+++ b/tgt-vhdl/support.hh
@@ -1,7 +1,7 @@
 /*
  *  Support functions for VHDL output.
  *
- *  Copyright (C) 2008  Nick Gasson (nick@nickg.me.uk)
+ *  Copyright (C) 2008-2010  Nick Gasson (nick@nickg.me.uk)
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -36,7 +36,7 @@ enum support_function_t {
    SF_TERNARY_SIGNED,
    SF_LOGIC_TO_INTEGER,
    SF_SIGNED_TO_LOGIC,
-   SF_UNSIGNED_TO_LOGIC,
+   SF_UNSIGNED_TO_LOGIC
 };
 
 class support_function : public vhdl_function {
diff --git a/tgt-vhdl/vhdl_syntax.hh b/tgt-vhdl/vhdl_syntax.hh
index 2b596a227..9253eeff1 100644
--- a/tgt-vhdl/vhdl_syntax.hh
+++ b/tgt-vhdl/vhdl_syntax.hh
@@ -1,7 +1,7 @@
 /*
  *  VHDL abstract syntax elements.
  *
- *  Copyright (C) 2008-2009  Nick Gasson (nick@nickg.me.uk)
+ *  Copyright (C) 2008-2010  Nick Gasson (nick@nickg.me.uk)
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -96,7 +96,7 @@ enum vhdl_binop_t {
    VHDL_BINOP_DIV,
    VHDL_BINOP_MOD,
    VHDL_BINOP_POWER,
-   VHDL_BINOP_SRA,
+   VHDL_BINOP_SRA
 };
 
 /*
@@ -123,7 +123,7 @@ private:
 
 enum vhdl_unaryop_t {
    VHDL_UNARYOP_NOT,
-   VHDL_UNARYOP_NEG,
+   VHDL_UNARYOP_NEG
 };
 
 class vhdl_unaryop_expr : public vhdl_expr {
@@ -206,7 +206,7 @@ enum time_unit_t {
    TIME_UNIT_PS,
    TIME_UNIT_NS,
    TIME_UNIT_US,
-   TIME_UNIT_MS,
+   TIME_UNIT_MS
 };
 
 class vhdl_const_time : public vhdl_expr {
@@ -397,7 +397,7 @@ enum vhdl_wait_type_t {
    VHDL_WAIT_FOR,    // Wait for a constant amount of time
    VHDL_WAIT_FOR0,   // Special wait for zero time
    VHDL_WAIT_UNTIL,  // Wait on an expression
-   VHDL_WAIT_ON,     // Wait on a sensitivity list
+   VHDL_WAIT_ON      // Wait on a sensitivity list
 };
 
 /*
@@ -657,7 +657,7 @@ enum vhdl_port_mode_t {
    VHDL_PORT_IN,
    VHDL_PORT_OUT,
    VHDL_PORT_INOUT,
-   VHDL_PORT_BUFFER,
+   VHDL_PORT_BUFFER
 };
 
 /*
diff --git a/tgt-vhdl/vhdl_type.hh b/tgt-vhdl/vhdl_type.hh
index f3bfb2211..3d551a3f2 100644
--- a/tgt-vhdl/vhdl_type.hh
+++ b/tgt-vhdl/vhdl_type.hh
@@ -1,7 +1,7 @@
 /*
  *  VHDL variable and signal types.
  *
- *  Copyright (C) 2008  Nick Gasson (nick@nickg.me.uk)
+ *  Copyright (C) 2008-2010  Nick Gasson (nick@nickg.me.uk)
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -34,7 +34,7 @@ enum vhdl_type_name_t {
    VHDL_TYPE_SIGNED,
    VHDL_TYPE_UNSIGNED,
    VHDL_TYPE_TIME,
-   VHDL_TYPE_ARRAY,
+   VHDL_TYPE_ARRAY
 };
 
 /*