From f2c1e21ad3d6f8b31278541f907213a0ba208a08 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sat, 5 Feb 2022 15:04:29 +0100 Subject: [PATCH 1/2] Allow unnamed parallel block with only variable declarations While it is not a particular useful construct it is legal to have a parallel block with just variable declarations and no statements. E.g. ``` fork int x; join ``` At the moment there is a special rule for completely empty parallel blocks. Remove that rule and change the statement_or_null_list in the fork/join parser section to a statement_or_null_list_opt. This way it covers both completely empty parallel blocks as well as parallel blocks with only variable declarations. Note that this already works as expected for named parallel blocks. Signed-off-by: Lars-Peter Clausen --- parse.y | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/parse.y b/parse.y index ca4aa26cb..977cfa3de 100644 --- a/parse.y +++ b/parse.y @@ -6652,11 +6652,6 @@ statement_item /* This is roughly statement_item in the LRM */ need to do is remember that this is a parallel block so that the code generator can do the right thing. */ - | K_fork join_keyword - { PBlock*tmp = new PBlock($2); - FILE_NAME(tmp, @1); - $$ = tmp; - } /* In SystemVerilog an unnamed block can contain variable declarations. */ | K_fork { PBlock*tmp = pform_push_block_scope(@1, 0, PBlock::BL_PAR); @@ -6677,7 +6672,7 @@ statement_item /* This is roughly statement_item in the LRM */ delete tmp; } } - statement_or_null_list join_keyword + statement_or_null_list_opt join_keyword { PBlock*tmp; if ($3) { pform_pop_scope(); From 4a9200f5f2a6c30652c4d4b861695c58cba05f51 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sun, 6 Feb 2022 13:57:48 +0100 Subject: [PATCH 2/2] Add regression test for variable declarations in unnamed forks SystemVerilog supports variable declarations in unnamed forks, while Verilog does not. Add a regression test that checks for this. Signed-off-by: Lars-Peter Clausen --- ivtest/ivltests/unnamed_fork_var_decl.v | 29 +++++++++++++++++++++++++ ivtest/regress-fsv.list | 1 + ivtest/regress-vlg.list | 1 + 3 files changed, 31 insertions(+) create mode 100644 ivtest/ivltests/unnamed_fork_var_decl.v diff --git a/ivtest/ivltests/unnamed_fork_var_decl.v b/ivtest/ivltests/unnamed_fork_var_decl.v new file mode 100644 index 000000000..9debd1b07 --- /dev/null +++ b/ivtest/ivltests/unnamed_fork_var_decl.v @@ -0,0 +1,29 @@ +// Check variable declarations in unnamed forks +// All of these should pass in SystemVerilog and all should fail in Verilog + +module test; + +initial fork + integer x; +join + +initial fork + integer x; + integer y; +join + +initial fork + integer x, y; +join + +initial fork + integer x; + integer y; + x = y; +join + +initial begin + $display("PASSED"); +end + +endmodule diff --git a/ivtest/regress-fsv.list b/ivtest/regress-fsv.list index 6181d0388..92e6b7751 100644 --- a/ivtest/regress-fsv.list +++ b/ivtest/regress-fsv.list @@ -83,6 +83,7 @@ resetall normal,-Wtimescale ivltests gold=resetall-fsv.gold scope2b normal ivltests sys_func_task_error RE ivltests gold=sys_func_task_error-fsv.gold unnamed_block_var_decl normal ivltests +unnamed_fork_var_decl normal ivltests # We do not run synthesis when forcing SystemVerilog so these pass br995 normal ivltests diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list index 89075234c..263b2ff9e 100644 --- a/ivtest/regress-vlg.list +++ b/ivtest/regress-vlg.list @@ -1677,6 +1677,7 @@ undef_lval_select4c CE ivltests undef_lval_select5 normal ivltests undefined_shift normal ivltests unnamed_block_var_decl CE ivltests +unnamed_fork_var_decl CE ivltests urand_r normal ivltests gold=urand_r.gold urand_r2 normal ivltests gold=urand_r.gold urand_r3 normal ivltests gold=urand_r.gold