diff --git a/ivtest/ivltests/module_output_port_list_def.v b/ivtest/ivltests/module_output_port_list_def.v index d40f453fe..6777e5b31 100644 --- a/ivtest/ivltests/module_output_port_list_def.v +++ b/ivtest/ivltests/module_output_port_list_def.v @@ -2,7 +2,7 @@ // output port declaration list. module M ( - output [31:0] x = 1, y = 2 + output reg [31:0] x = 1, y = 2 ); `define check(val, exp) \ diff --git a/ivtest/ivltests/module_port_array_init1.v b/ivtest/ivltests/module_port_array_init1.v new file mode 100644 index 000000000..f08462927 --- /dev/null +++ b/ivtest/ivltests/module_port_array_init1.v @@ -0,0 +1,23 @@ +// Check that initializers values are supported for module array ports + +module M ( + input [31:0] x[0:1] = '{1, 2}, + output reg [31:0] y[0:1] = '{3, 4} +); + + initial begin + #1 + if (x[0] === 1 && x[1] === 2 && y[0] === 3 && y[1] === 4) begin + $display("PASSED"); + end else begin + $display("FAILED"); + end + end + +endmodule + +module test; + + M i_m (); + +endmodule diff --git a/ivtest/regress-vvp.list b/ivtest/regress-vvp.list index 41501aaa6..8ab931c1a 100644 --- a/ivtest/regress-vvp.list +++ b/ivtest/regress-vvp.list @@ -35,6 +35,7 @@ memsynth1 vvp_tests/memsynth1.json module_ordered_list1 vvp_tests/module_ordered_list1.json module_ordered_list2 vvp_tests/module_ordered_list2.json module_port_array1 vvp_tests/module_port_array1.json +module_port_array_init1 vvp_tests/module_port_array_init1.json param-width vvp_tests/param-width.json param-width-vlog95 vvp_tests/param-width-vlog95.json pr1388974 vvp_tests/pr1388974.json diff --git a/ivtest/vvp_tests/module_port_array_init1.json b/ivtest/vvp_tests/module_port_array_init1.json new file mode 100644 index 000000000..ec34b89b7 --- /dev/null +++ b/ivtest/vvp_tests/module_port_array_init1.json @@ -0,0 +1,5 @@ +{ + "type" : "normal", + "source" : "module_port_array_init1.v", + "iverilog-args" : [ "-g2005-sv" ] +} diff --git a/parse.y b/parse.y index 5c98f4fb1..0178a3131 100644 --- a/parse.y +++ b/parse.y @@ -4448,10 +4448,13 @@ list_of_port_declarations ; port_declaration - : attribute_list_opt K_input net_type_or_var_opt data_type_or_implicit IDENTIFIER dimensions_opt - { Module::port_t*ptmp; + : attribute_list_opt K_input net_type_or_var_opt data_type_or_implicit IDENTIFIER dimensions_opt initializer_opt + { if ($7) + pform_requires_sv(@7, "Input port default value"); + Module::port_t*ptmp; perm_string name = lex_strings.make($5); ptmp = pform_module_port_reference(@2, name); + ptmp->default_value = $7; pform_module_define_port(@2, name, NetNet::PINPUT, $3, $4, $6, nullptr, $1); port_declaration_context.port_type = NetNet::PINPUT; @@ -4475,21 +4478,6 @@ port_declaration delete[]$4; $$ = ptmp; } - | attribute_list_opt K_input net_type_or_var_opt data_type_or_implicit IDENTIFIER '=' expression - { pform_requires_sv(@6, "Default port value"); - Module::port_t*ptmp; - perm_string name = lex_strings.make($5); - data_type_t*use_type = $4; - ptmp = pform_module_port_reference(@2, name); - ptmp->default_value = $7; - pform_module_define_port(@2, name, NetNet::PINPUT, $3, use_type, - nullptr, $1); - port_declaration_context.port_type = NetNet::PINPUT; - port_declaration_context.port_net_type = $3; - port_declaration_context.data_type = $4; - delete[]$5; - $$ = ptmp; - } | attribute_list_opt K_inout net_type_opt data_type_or_implicit IDENTIFIER dimensions_opt { Module::port_t*ptmp; perm_string name = lex_strings.make($5); @@ -4521,7 +4509,7 @@ port_declaration delete[]$4; $$ = ptmp; } - | attribute_list_opt K_output net_type_or_var_opt data_type_or_implicit IDENTIFIER dimensions_opt + | attribute_list_opt K_output net_type_or_var_opt data_type_or_implicit IDENTIFIER dimensions_opt initializer_opt { Module::port_t*ptmp; perm_string name = lex_strings.make($5); NetNet::Type use_type = $3; @@ -4545,6 +4533,9 @@ port_declaration port_declaration_context.port_type = NetNet::POUTPUT; port_declaration_context.port_net_type = use_type; port_declaration_context.data_type = $4; + + if ($7) + pform_make_var_init(@5, name, $7); delete[]$5; $$ = ptmp; } @@ -4563,25 +4554,6 @@ port_declaration delete[]$4; $$ = ptmp; } - | attribute_list_opt K_output net_type_or_var_opt data_type_or_implicit IDENTIFIER '=' expression - { Module::port_t*ptmp; - perm_string name = lex_strings.make($5); - NetNet::Type use_type = $3; - if (use_type == NetNet::IMPLICIT) { - use_type = NetNet::IMPLICIT_REG; - } - ptmp = pform_module_port_reference(@2, name); - pform_module_define_port(@2, name, NetNet::POUTPUT, use_type, $4, - nullptr, $1); - port_declaration_context.port_type = NetNet::POUTPUT; - port_declaration_context.port_net_type = use_type; - port_declaration_context.data_type = $4; - - pform_make_var_init(@5, name, $7); - - delete[]$5; - $$ = ptmp; - } ; /*