From b8eb21b3acc49b8b6b9f9ba7284de9dbec4b4348 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 6 Jun 2023 06:45:30 -0700 Subject: [PATCH] Allow to omit trailing module ports in ordered list connection The current implementation expects that for a module instantiation with a ordered list connection all ports are supplied. But there doesn't seem to be such a requirement in the LRMs. The Verilog LRM doesn't mention anything in this regard and the SystemVerilog LRM mentions in section 23.3.2.1 that a blank or omitted port connection is either left unconnected or uses the default value of the port. Update the implementation so that it allows to omit trailing ports and only generates an error message if too many ports are specified in the ordered port list. Signed-off-by: Lars-Peter Clausen --- elaborate.cc | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/elaborate.cc b/elaborate.cc index 86e48a388..25932456c 100644 --- a/elaborate.cc +++ b/elaborate.cc @@ -1317,22 +1317,20 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const } else { /* Otherwise, this is a positional list of port - connections. In this case, the port count must be - right. Check that is is, the get the pin list. */ + connections. Use as many ports as provided. Trailing + missing ports will be left unconnect or use the default + value if one is available */ - if (pin_count() != rmod->port_count()) { + if (pin_count() > rmod->port_count()) { cerr << get_fileline() << ": error: Wrong number " - "of ports. Expecting " << rmod->port_count() << + "of ports. Expecting at most " << rmod->port_count() << ", got " << pin_count() << "." << endl; des->errors += 1; return; } - // No named bindings, just use the positional list I - // already have. - assert(pin_count() == rmod->port_count()); - pins = get_pins(); + std::copy(get_pins().begin(), get_pins().end(), pins.begin()); } // Elaborate these instances of the module. The recursive