From b82ca281907363c23d3b3103c46fc4f3525b7121 Mon Sep 17 00:00:00 2001 From: Nick Gasson Date: Mon, 30 Jun 2008 16:18:55 +0100 Subject: [PATCH] Add XOR logic type and fix part select --- tgt-vhdl/lpm.cc | 8 +++++++- tgt-vhdl/scope.cc | 3 +++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/tgt-vhdl/lpm.cc b/tgt-vhdl/lpm.cc index 00f7240e1..6ce6d04a6 100644 --- a/tgt-vhdl/lpm.cc +++ b/tgt-vhdl/lpm.cc @@ -63,8 +63,14 @@ int draw_part_select_lpm(vhdl_arch *arch, ivl_lpm_t lpm) vhdl_var_ref *selfrom = nexus_to_var_ref(arch->get_scope(), ivl_lpm_data(lpm, 0)); if (NULL == selfrom) return 1; + + vhdl_expr *off = NULL; + ivl_nexus_t base = ivl_lpm_data(lpm, 1); + if (base != NULL) + off = nexus_to_var_ref(arch->get_scope(), base); + else + off = new vhdl_const_int(ivl_lpm_base(lpm)); - vhdl_expr *off = nexus_to_var_ref(arch->get_scope(), ivl_lpm_data(lpm, 1)); if (NULL == off) return 1; diff --git a/tgt-vhdl/scope.cc b/tgt-vhdl/scope.cc index 2fbcae7a0..142c2d535 100644 --- a/tgt-vhdl/scope.cc +++ b/tgt-vhdl/scope.cc @@ -112,6 +112,9 @@ static void declare_logic(vhdl_arch *arch, ivl_scope_t scope) case IVL_LO_OR: rhs = inputs_to_expr(arch, VHDL_BINOP_OR, log); break; + case IVL_LO_XOR: + rhs = inputs_to_expr(arch, VHDL_BINOP_XOR, log); + break; default: error("Don't know how to translate logic type = %d", ivl_logic_type(log));