diff --git a/vvp/Makefile.in b/vvp/Makefile.in index c80ddd462..3f453b7cf 100644 --- a/vvp/Makefile.in +++ b/vvp/Makefile.in @@ -16,7 +16,7 @@ # 59 Temple Place - Suite 330 # Boston, MA 02111-1307, USA # -#ident "$Id: Makefile.in,v 1.67 2005/04/28 04:59:53 steve Exp $" +#ident "$Id: Makefile.in,v 1.68 2005/05/24 01:43:27 steve Exp $" # # SHELL = /bin/sh @@ -82,7 +82,7 @@ vpi_memory.o vpi_vthr_vector.o vpip_bin.o vpip_hex.o vpip_oct.o \ vpip_to_dec.o vpip_format.o vvp_vpi.o O = main.o parse.o parse_misc.o lexor.o arith.o bufif.o compile.o concat.o \ -dff.o functor.o npmos.o part.o reduce.o resolv.o stop.o symbols.o \ +dff.o extend.o functor.o npmos.o part.o reduce.o resolv.o stop.o symbols.o \ ufunc.o codes.o \ vthread.o schedule.o statistics.o tables.o udp.o vvp_net.o memory.o \ event.o logic.o delay.o words.o $V diff --git a/vvp/README.txt b/vvp/README.txt index 0aa9c93e4..2becd6c4d 100644 --- a/vvp/README.txt +++ b/vvp/README.txt @@ -1,7 +1,7 @@ /* * Copyright (c) 2001 Stephen Williams (steve@icarus.com) * - * $Id: README.txt,v 1.66 2005/05/08 23:40:14 steve Exp $ + * $Id: README.txt,v 1.67 2005/05/24 01:43:27 steve Exp $ */ VVP SIMULATION ENGINE @@ -524,6 +524,16 @@ the device has a single input, which is a vector of any width. The device performs the logic on all the bits of the vector (a la Verilog) and produces and propagates a single bit width vector. +EXPANSION LOGIC + +Sign extension nodes are the opposite of reduction logic, in that they +take a narrow vector, or single bit, and pad it out to a wider +vector. + +