diff --git a/.cvsignore b/.cvsignore
index 7c9626e07..eb555c269 100644
--- a/.cvsignore
+++ b/.cvsignore
@@ -6,6 +6,7 @@ ivl
 dep
 configure
 Makefile
+verilog
 config.status
 config.log
 config.cache
diff --git a/Makefile.in b/Makefile.in
index 517c6a9ef..1ea55e562 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -18,7 +18,7 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.13 1999/08/15 02:20:06 steve Exp $"
+#ident "$Id: Makefile.in,v 1.14 1999/08/17 15:57:43 steve Exp $"
 #
 #
 SHELL = /bin/sh
@@ -45,7 +45,7 @@ CPPFLAGS = @CPPFLAGS@ @DEFS@
 CXXFLAGS = @CXXFLAGS@
 LDFLAGS = @LDFLAGS@
 
-all: ivl
+all: ivl verilog
 	cd vpi ; make all
 	cd vvm ; make all
 	cd ivlpp ; make all
@@ -68,6 +68,14 @@ $(FF) $(TT)
 Makefile: Makefile.in config.status
 	./config.status
 
+# Make the actual verilog program from the script template. This
+# simply invloves editing the substitution strings in the script into
+# the configured copy.
+tmp1 = bindir
+tmp2 = libdir
+verilog: $(srcdir)/verilog.sh
+	sed -e 's;@$(tmp1)@;@bindir@;' -e 's;@$(tmp2)@;@libdir@;' < $< > $@
+
 ivl: $O
 	$(CXX) $(CXXFLAGS) -o ivl $O
 
@@ -88,11 +96,14 @@ parse.h parse.cc: parse.y
 lexor.cc: lexor.lex
 	flex -PVL -s -olexor.cc lexor.lex
 
-install: all installdirs $(bindir)/ivl
+install: all installdirs $(bindir)/verilog $(bindir)/ivl
 	cd vpi ; make install
 	cd vvm ; make install
 	cd ivlpp ; make install
 
+$(bindir)/verilog: ./verilog
+	$(INSTALL_PROGRAM) ./verilog $(bindir)/verilog
+
 $(bindir)/ivl: ivl
 	$(INSTALL_PROGRAM) ./ivl $(bindir)/ivl
 
@@ -101,6 +112,7 @@ installdirs: mkinstalldirs
 
 uninstall:
 	rm -f $(bindir)/ivl
+	rm -f $(bindir)/verilog
 	cd vpi ; make uninstall
 	cd vvm ; make uninstall
 	cd ivlpp ; make uninstall
diff --git a/verilog.sh b/verilog.sh
new file mode 100644
index 000000000..308e118de
--- /dev/null
+++ b/verilog.sh
@@ -0,0 +1,98 @@
+#!/bin/sh
+
+# verilog - A wrapper shell script for ivl
+# Copyright (C) 1999 Stefan Petersen (spe@geda.seul.org)
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+
+# Setup variables
+execPath=@bindir@
+execIVLPP=${execPath}/ivlpp
+execIVL=${execPath}/ivl
+execCpp=/usr/bin/g++
+
+target="-t vvm"
+
+tmpDir=/tmp
+tmpPPFile=${tmpDir}/ivl$$.pp
+tmpCCFile=${tmpDir}/ivl$$.cc
+
+VPIModulePath=@libdir@/ivl:.
+
+outputRequested=0
+
+
+# If VPI module path aren't set up, setup default
+# Humm, doesn't work as intended ... silly silly me
+if test -z "${VPI_MODULE_PATH}" ; then
+  VPI_MODULE_PATH=${VPIModulePath} ;
+  export VPI_MODULE_PATH ;
+fi
+
+
+# Try to extract given parameters
+for parameter in $*; do 
+
+#  echo ${parameter} ;
+
+  if test ${outputRequested} -eq 1 ; then
+    outputFile=${parameter};
+    outputRequested=0;
+  else
+    case "${parameter}" in
+      -D*) extDefines="${extDefines} ${parameter}" ;;
+      -I*) extIncPath="${extIncPath} -I ${parameter:2}";;
+      -l*) extLibPath="${extLibPath} ${parameter}" ;;
+      -o)  outputRequested=1 ;;
+      *)   verilogFile=${parameter};;
+    esac
+  fi
+
+done
+
+
+# If no output file is given should we guess one or...?
+if test -z "${outputFile}" ; then 
+  outputFile=`echo ${verilogFile} | sed -e 's/\(.*\)\..*/\1/'`;
+fi
+
+
+# Preprocess
+${execIVLPP} ${extDefines} ${extIncPath} -L -o ${tmpPPFile} ${verilogFile}
+if test $? -ne 0 ; then
+  echo "Preprocessing failed. Terminating compilation."
+  rm -f ${tmpPPFile}
+  exit -1
+fi
+
+
+# Compile preprocessed verilog file
+${execIVL} ${target} -o ${tmpCCFile} ${tmpPPFile}
+if test $? -ne  0 ; then
+  echo "Verilog compilation failed. Terminating compilation."
+  rm -f ${tmpCCFile}
+  exit -1
+fi
+rm -f ${tmpPPFile}
+
+# Compile generated C++ code
+${execCpp} -rdynamic ${tmpCCFile} -o ${outputFile} -lvvm -ldl
+if test $? -ne 0 ; then
+  echo "C++ compilation failed. Terminating compilation."
+  rm -f ${tmpCCFile}
+  exit -1
+fi
+rm -f ${tmpCCFile}