diff --git a/ivtest/ivltests/sdf_interconnect1.sdf b/ivtest/ivltests/sdf_interconnect1.sdf
index 914b011ef..101295e83 100644
--- a/ivtest/ivltests/sdf_interconnect1.sdf
+++ b/ivtest/ivltests/sdf_interconnect1.sdf
@@ -13,7 +13,7 @@
 
   (CELL
     (CELLTYPE "my_design")
-    (INSTANCE)   
+    (INSTANCE)
     (DELAY
       (ABSOLUTE
         (INTERCONNECT a buffer0.in (0.010:0.020:0.030) (0.010:0.020:0.030))
@@ -33,7 +33,7 @@
       )
     )
   )
-  
+
   (CELL
     (CELLTYPE "buffer")
     (INSTANCE buffer1)
@@ -43,7 +43,7 @@
       )
     )
   )
-  
+
   (CELL
     (CELLTYPE "buffer")
     (INSTANCE buffer2)
diff --git a/ivtest/ivltests/sdf_interconnect1.v b/ivtest/ivltests/sdf_interconnect1.v
index 122556220..91f500539 100644
--- a/ivtest/ivltests/sdf_interconnect1.v
+++ b/ivtest/ivltests/sdf_interconnect1.v
@@ -46,10 +46,10 @@ module top;
         $sdf_annotate("ivltests/sdf_interconnect1.sdf", my_design_inst);
         $monitor("time=%0t a=%h b=%h", $realtime, a, b);
     end
-  
+
     reg a;
     wire b;
-    
+
     initial begin
         #5;
         a <= 1'b0;
@@ -58,7 +58,7 @@ module top;
         #10;
         $finish;
     end
-  
+
     my_design my_design_inst (
         .a (a),
         .b (b)
diff --git a/ivtest/ivltests/sdf_interconnect2.sdf b/ivtest/ivltests/sdf_interconnect2.sdf
index eef3b95cd..4f298ae04 100644
--- a/ivtest/ivltests/sdf_interconnect2.sdf
+++ b/ivtest/ivltests/sdf_interconnect2.sdf
@@ -13,7 +13,7 @@
 
   (CELL
     (CELLTYPE "my_design")
-    (INSTANCE)   
+    (INSTANCE)
     (DELAY
       (ABSOLUTE
         (INTERCONNECT a buffer0.in (0.000:0.010:0.000) (0.000:0.010:0.000))
@@ -32,7 +32,7 @@
       )
     )
   )
-  
+
   (CELL
     (CELLTYPE "buffer")
     (INSTANCE buffer1)
@@ -42,7 +42,7 @@
       )
     )
   )
-  
+
   (CELL
     (CELLTYPE "buffer")
     (INSTANCE buffer2)
diff --git a/ivtest/ivltests/sdf_interconnect2.v b/ivtest/ivltests/sdf_interconnect2.v
index 296416fbd..c35523a41 100644
--- a/ivtest/ivltests/sdf_interconnect2.v
+++ b/ivtest/ivltests/sdf_interconnect2.v
@@ -37,7 +37,7 @@ module my_design (
         .in (a),
         .out (w3)
     );
-    
+
     assign b = w1 & w2 & w3;
 
 endmodule
@@ -48,10 +48,10 @@ module top;
         $sdf_annotate("ivltests/sdf_interconnect2.sdf", my_design_inst);
         $monitor("time=%0t a=%h b=%h", $realtime, a, b);
     end
-  
+
     reg a;
     wire b;
-    
+
     initial begin
         #5;
         a <= 1'b0;
@@ -60,7 +60,7 @@ module top;
         #10;
         $finish;
     end
-  
+
     my_design my_design_inst (
         .a (a),
         .b (b)
diff --git a/ivtest/ivltests/sdf_interconnect3.sdf b/ivtest/ivltests/sdf_interconnect3.sdf
index a6fa94626..a15b3a1fb 100644
--- a/ivtest/ivltests/sdf_interconnect3.sdf
+++ b/ivtest/ivltests/sdf_interconnect3.sdf
@@ -13,7 +13,7 @@
 
   (CELL
     (CELLTYPE "my_design")
-    (INSTANCE)   
+    (INSTANCE)
     (DELAY
       (ABSOLUTE
         (INTERCONNECT a             buffer0.in  (0.000:0.010:0.000) (0.000:0.010:0.000))
@@ -42,7 +42,7 @@
       )
     )
   )
-  
+
   (CELL
     (CELLTYPE "buffer")
     (INSTANCE buffer1)
@@ -52,7 +52,7 @@
       )
     )
   )
-  
+
   (CELL
     (CELLTYPE "buffer")
     (INSTANCE buffer2)
@@ -62,7 +62,7 @@
       )
     )
   )
-  
+
   (CELL
     (CELLTYPE "buffer")
     (INSTANCE buffer3)
@@ -72,7 +72,7 @@
       )
     )
   )
-  
+
   (CELL
     (CELLTYPE "my_xor")
     (INSTANCE my_xor0)
@@ -83,7 +83,7 @@
       )
     )
   )
-  
+
   (CELL
     (CELLTYPE "my_xor")
     (INSTANCE my_xor1)
@@ -94,7 +94,7 @@
       )
     )
   )
-  
+
   (CELL
     (CELLTYPE "my_xor")
     (INSTANCE my_xor2)
@@ -105,7 +105,7 @@
       )
     )
   )
-  
+
   (CELL
     (CELLTYPE "my_xor")
     (INSTANCE my_xor3)
diff --git a/ivtest/ivltests/sdf_interconnect3.v b/ivtest/ivltests/sdf_interconnect3.v
index c62d7e8d7..fc501f641 100644
--- a/ivtest/ivltests/sdf_interconnect3.v
+++ b/ivtest/ivltests/sdf_interconnect3.v
@@ -49,7 +49,7 @@ module my_design (
         .b (c),
         .out (w2)
     );
-    
+
     my_xor my_xor1 (
         .a (w1),
         .b (b),
@@ -60,24 +60,24 @@ module my_design (
         .in (w2),
         .out (w4)
     );
-    
+
     my_xor my_xor2 (
         .a (w3),
         .b (w4),
         .out (w5)
     );
-    
+
     buffer buffer2 (
         .in (c),
         .out (w6)
     );
-    
+
     my_xor my_xor3 (
         .a (w5),
         .b (w6),
         .out (w7)
     );
-    
+
     buffer buffer3 (
         .in (w7),
         .out (d)
@@ -91,10 +91,10 @@ module top;
         $sdf_annotate("ivltests/sdf_interconnect3.sdf", my_design_inst);
         $monitor("time=%0t a=%h b=%h c=%h d=%h", $realtime, a, b, c, d);
     end
-  
+
     reg a, b, c;
     wire d;
-    
+
     initial begin
         #10;
         a <= 1'b0;
@@ -131,7 +131,7 @@ module top;
         #10;
         $finish;
     end
-  
+
     my_design my_design_inst (
         .a (a),
         .b (b),
diff --git a/ivtest/ivltests/sv_immediate_assert.v b/ivtest/ivltests/sv_immediate_assert.v
index 742b3c3be..9331c79be 100644
--- a/ivtest/ivltests/sv_immediate_assert.v
+++ b/ivtest/ivltests/sv_immediate_assert.v
@@ -14,11 +14,11 @@ initial begin
   assert(i == 0) $display("Check 8 : this shouldn't be displayed");
     else $display("Check 8 : this should be displayed");
 
-  a_i_is_non_0 : assert(i == 0) 
+  a_i_is_non_0 : assert(i == 0)
     $display("Check 9 : this shouldn't be displayed");
     else $error("Check 9 : this should be displayed");
 
-  a_i_is_1 : assert(i == 1) 
+  a_i_is_1 : assert(i == 1)
     $display("Check 10 : this should be displayed");
     else $error("Check 10 : this shouldn't be displayed i: %0d", i);
 
diff --git a/ivtest/ivltests/sv_immediate_assume.v b/ivtest/ivltests/sv_immediate_assume.v
index 1390298f3..489192427 100644
--- a/ivtest/ivltests/sv_immediate_assume.v
+++ b/ivtest/ivltests/sv_immediate_assume.v
@@ -14,11 +14,11 @@ initial begin
   assume(i == 0) $display("Check 8 : this shouldn't be displayed");
     else $display("Check 8 : this should be displayed");
 
-  a_i_is_non_0 : assume(i == 0) 
+  a_i_is_non_0 : assume(i == 0)
     $display("Check 9 : this shouldn't be displayed");
     else $error("Check 9 : this should be displayed");
 
-  a_i_is_1 : assume(i == 1) 
+  a_i_is_1 : assume(i == 1)
     $display("Check 10 : this should be displayed");
     else $error("Check 10 : this shouldn't be displayed i: %0d", i);
 
diff --git a/ivtest/ivltests/timing_check_delayed_signals.v b/ivtest/ivltests/timing_check_delayed_signals.v
index 9c0542ce6..245104bd9 100644
--- a/ivtest/ivltests/timing_check_delayed_signals.v
+++ b/ivtest/ivltests/timing_check_delayed_signals.v
@@ -27,9 +27,9 @@ module test;
     */
 
   endspecify
-  
+
   initial begin
-  
+
       if (del_sig1 == 1'b0 && del_sig2 == 1'b1 && del_sig3 == 1'b0 && del_sig4 == 1'b1)
         $display("PASSED");
       else
diff --git a/ivtest/ivltests/timing_check_syntax.v b/ivtest/ivltests/timing_check_syntax.v
index c43347f01..fb91d2865 100644
--- a/ivtest/ivltests/timing_check_syntax.v
+++ b/ivtest/ivltests/timing_check_syntax.v
@@ -5,7 +5,7 @@ module test;
   initial begin
       $display("PASSED");
   end
-  
+
   wire sig1, sig2, del_sig1, del_sig2, notifier, cond1, cond2;
 
   specify