From b40b6fb50d469f0602f1a834c2217f10eb349b4a Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Sat, 7 Mar 2009 17:16:13 -0800 Subject: [PATCH] Spelling fixes Mostly comments, but includes user-visible debug messages. (cherry picked from commit b0c4a87133a01e3c8de770496a841693b3ddbc7c) --- elab_expr.cc | 4 ++-- eval_tree.cc | 2 +- tgt-vhdl/stmt.cc | 2 +- tgt-vvp/eval_expr.c | 4 ++-- vvp/vvp_net.cc | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/elab_expr.cc b/elab_expr.cc index 9e2bf21fb..1075133c3 100644 --- a/elab_expr.cc +++ b/elab_expr.cc @@ -686,7 +686,7 @@ NetExpr* PEBinary::elaborate_expr_base_rshift_(Design*des, } // Special case: shift is negative (so do a left shift) - // and is greater then the output width. Replace the + // and is greater than the output width. Replace the // expression with a constant-0. if (shift < 0 && (0-shift) >= use_wid) { if (debug_elaborate) @@ -2265,7 +2265,7 @@ NetExpr* PEIdent::elaborate_expr_param_part_(Design*des, NetScope*scope, if (! parts_defined_flag) { if (debug_elaborate) - cerr << get_fileline() << ": debug: Part select of paramter " + cerr << get_fileline() << ": debug: Part select of parameter " << "has x/z bits, so resorting to 'bx result." << endl; long wid = 1 + labs(par_msv-par_lsv); diff --git a/eval_tree.cc b/eval_tree.cc index d9a51fc1d..668213d62 100644 --- a/eval_tree.cc +++ b/eval_tree.cc @@ -133,7 +133,7 @@ NetExpr* NetEBAdd::eval_tree(int prune_to_width) if (debug_eval_tree) { cerr << get_fileline() << ": debug: " - << "Partially evalutate " << *this + << "Partially evaluate " << *this << " using (a+2)-1 --> (a+1) transform." << endl; } diff --git a/tgt-vhdl/stmt.cc b/tgt-vhdl/stmt.cc index f0a5efdb2..ec0cec8b9 100644 --- a/tgt-vhdl/stmt.cc +++ b/tgt-vhdl/stmt.cc @@ -552,7 +552,7 @@ static void get_nexuses_from_expr(ivl_expr_t expr, set &out) /* * Attempt to identify common forms of wait statements and produce * more idiomatic VHDL than would be produced by the generic - * draw_wait funciton. The main application of this is a input to + * draw_wait function. The main application of this is a input to * synthesis tools that don't synthesise the full VHDL language. * If none of these patterns are matched, the function returns false * and the default draw_wait is used. diff --git a/tgt-vvp/eval_expr.c b/tgt-vvp/eval_expr.c index d3477f026..f9c72b1ef 100644 --- a/tgt-vvp/eval_expr.c +++ b/tgt-vvp/eval_expr.c @@ -1853,7 +1853,7 @@ static struct vector_info draw_number_expr(ivl_expr_t exp, unsigned wid) /* * This little helper function generates the instructions to pad a - * vector in place. It is assumed that the calling functio has set up + * vector in place. It is assumed that the calling function has set up * the first sub_sidth bits of the dest vector, and the signed_flag is * true if the extension is to be signed. */ @@ -2456,7 +2456,7 @@ static void draw_select_expr_dest(ivl_expr_t exp, struct vector_info dest, /* If the shift expression is not present, then this is really a pad expression, and that can be handled pretty - easily. Evalutate the subexpression into the destination, + easily. Evaluate the subexpression into the destination, then pad in place. */ if (shift == 0) { struct vector_info subv; diff --git a/vvp/vvp_net.cc b/vvp/vvp_net.cc index 2be14fbba..088ff6024 100644 --- a/vvp/vvp_net.cc +++ b/vvp/vvp_net.cc @@ -3399,7 +3399,7 @@ ostream& operator <<(ostream&out, vvp_scalar_t a) /* * This function is only called if the actual interface function rules - * out some of the eazy cases. If we get here, we can assume that + * out some of the easy cases. If we get here, we can assume that * neither of the values is HiZ, and the values are not exactly equal. */ vvp_scalar_t fully_featured_resolv_(vvp_scalar_t a, vvp_scalar_t b)