diff --git a/tgt-vhdl/scope.cc b/tgt-vhdl/scope.cc
index 5f03f20b4..2642648e5 100644
--- a/tgt-vhdl/scope.cc
+++ b/tgt-vhdl/scope.cc
@@ -404,18 +404,16 @@ int draw_function(ivl_scope_t scope, ivl_scope_t parent)
       std::string signame = make_safe_name(sig);
 
       switch (ivl_signal_port(sig)) {
+      case IVL_SIP_INPUT:
+         func->add_param(new vhdl_param_decl(signame.c_str(), sigtype));
+         break;
       case IVL_SIP_OUTPUT:
          // The magic variable Verilog_Result holds the return value
          signame = "Verilog_Result";
          func->set_type(sigtype);
+      default:
          func->get_scope()->add_decl
             (new vhdl_var_decl(signame.c_str(), new vhdl_type(*sigtype)));
-         break;
-      case IVL_SIP_INPUT:
-         func->add_param(new vhdl_param_decl(signame.c_str(), sigtype));
-         break;
-      default:
-         assert(false);
       }
       
       remember_signal(sig, func->get_scope());