From 74f7dacc866099010cd43c6b038f9ff815e4708a Mon Sep 17 00:00:00 2001 From: Stephen Williams Date: Sat, 15 Jan 2022 10:18:50 -0800 Subject: [PATCH 1/3] Add ivtest to the iverilog source tree By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature. --- .github/test.sh | 4 +- ivtest/.gitattributes | 5 + ivtest/.gitignore | 33 + ivtest/COPYING | 339 + ivtest/README | 120 + ivtest/blif.list | 21 + ivtest/blif/blif01a.v | 66 + ivtest/blif/blif01a_tb.v | 40 + ivtest/blif/blif01b.v | 9 + ivtest/blif/blif01b_tb.v | 34 + ivtest/blif/blif01c.v | 11 + ivtest/blif/blif01c_tb.v | 40 + ivtest/blif/blif01d.v | 11 + ivtest/blif/blif01d_tb.v | 40 + ivtest/blif/blif01e.v | 14 + ivtest/blif/blif01e_tb.v | 53 + ivtest/blif/blif01f.v | 11 + ivtest/blif/blif01f_tb.v | 32 + ivtest/blif/blif01g.v | 14 + ivtest/blif/blif01g_tb.v | 44 + ivtest/blif/blif01h.v | 9 + ivtest/blif/blif01h_tb.v | 33 + ivtest/blif/blif01i.v | 12 + ivtest/blif/blif01i_tb.v | 25 + ivtest/blif/blif02a.v | 40 + ivtest/blif/blif02a_tb.v | 40 + ivtest/blif/blif02b.v | 11 + ivtest/blif/blif02b_tb.v | 34 + ivtest/blif/blif02c.v | 11 + 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ivtest/vpi_gold/br_gh117.gold create mode 100644 ivtest/vpi_gold/br_gh141.gold create mode 100644 ivtest/vpi_gold/br_gh169a.gold create mode 100644 ivtest/vpi_gold/br_gh169b.gold create mode 100644 ivtest/vpi_gold/br_gh184.gold create mode 100644 ivtest/vpi_gold/br_gh235.gold create mode 100644 ivtest/vpi_gold/br_gh308.gold create mode 100644 ivtest/vpi_gold/br_gh317.gold create mode 100644 ivtest/vpi_gold/br_gh496.gold create mode 100644 ivtest/vpi_gold/br_gh59.gold create mode 100644 ivtest/vpi_gold/br_gh73a.gold create mode 100644 ivtest/vpi_gold/br_gh73b.gold create mode 100644 ivtest/vpi_gold/br_ml20191013.gold create mode 100644 ivtest/vpi_gold/by_index.gold create mode 100644 ivtest/vpi_gold/by_name-std.log create mode 100644 ivtest/vpi_gold/by_name.log create mode 100644 ivtest/vpi_gold/callback1.log create mode 100644 ivtest/vpi_gold/celldefine.gold create mode 100644 ivtest/vpi_gold/check_version.gold create mode 100644 ivtest/vpi_gold/display_array.gold create mode 100644 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mode 100644 ivtest/vpi_gold/putvalue.log create mode 100644 ivtest/vpi_gold/range1.gold create mode 100644 ivtest/vpi_gold/realcb.log create mode 100644 ivtest/vpi_gold/realtime.log create mode 100644 ivtest/vpi_gold/realtime2.log create mode 100644 ivtest/vpi_gold/ro_synch.gold create mode 100644 ivtest/vpi_gold/scanmem.log create mode 100644 ivtest/vpi_gold/scanmem2.log create mode 100644 ivtest/vpi_gold/scanmem3.log create mode 100644 ivtest/vpi_gold/scopes-std.log create mode 100644 ivtest/vpi_gold/scopes.log create mode 100644 ivtest/vpi_gold/spec_delays.log create mode 100644 ivtest/vpi_gold/start_of_simtime1.log create mode 100644 ivtest/vpi_gold/timescale.log create mode 100755 ivtest/vpi_reg.pl create mode 100644 ivtest/vpi_regress.list create mode 100755 ivtest/vvp_reg.pl diff --git a/.github/test.sh b/.github/test.sh index b8ffd2149..3c4929a97 100755 --- a/.github/test.sh +++ b/.github/test.sh @@ -1,6 +1,8 @@ #!/usr/bin/env sh -git clone https://github.com/steveicarus/ivtest.git || exit 1 +echo "Using the bundled ivtest to run regression tests." +echo " pwd = $(pwd)" + cd ivtest version=v11 diff --git a/ivtest/.gitattributes b/ivtest/.gitattributes new file mode 100644 index 000000000..3dae916a6 --- /dev/null +++ b/ivtest/.gitattributes @@ -0,0 +1,5 @@ +# This test is sensitive to the number of bytes in the text file. +ivltests/pr1819452.txt text eol=lf + +# MSY2 expected results require LF line endings. +regression_report-msys2.txt text eol=lf diff --git a/ivtest/.gitignore b/ivtest/.gitignore new file mode 100644 index 000000000..21462303a --- /dev/null +++ b/ivtest/.gitignore @@ -0,0 +1,33 @@ +# Lines that start with '#' are comments. +# +# This file is for the development branch of Icarus Verilog. +# +# The following files will be ignored by git. + +# The log and work directories +ivl_vhdl_work/ +log/ +work/ +vpi_log/ +vhdl/ + +# The normal regression output files. + +regression_report.txt +vhdl_regression_report.txt + +# These should be cleaned up, but ignore them as well. +*~ +*.o +*.vpi +*.tmp +src/vcddiff +vsim +vlog95.v +tmp_blif.blif +tmp_blif.v +tmp_blif.vvp + +# Some tests do not work out of the work directory, so +# ignore these files that they leave in the home directory. +dump.vcd diff --git a/ivtest/COPYING b/ivtest/COPYING new file mode 100644 index 000000000..916d1f0f2 --- /dev/null +++ b/ivtest/COPYING @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) 19yy + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) 19yy name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/ivtest/README b/ivtest/README new file mode 100644 index 000000000..c99d767ae --- /dev/null +++ b/ivtest/README @@ -0,0 +1,120 @@ +#################### +# +# Main test script +# +#################### + +There are a group of tests that are meant to exercise the compiler +and the run time. To run them just type: + +./regress + +or + +perl vvp_reg.pl + +or if perl is located in /usr/bin + +./vvp_reg.pl + +The output from these tests are displayed on the screen +and are also placed in the regression_report.txt file. +The expected output for the current development release +is located in the regression_report-devel.txt file. The +expected output for stable (released) versions can be +found in files named regression_report-v.txt. + +The results from individual tests can be found in the +log directory and gold files, when needed, are in the +gold directory. The source files can be found in the +ivltests and contrib directories. The list of tests +and how they are run are in the regress-*.list files. + +To check a specific suffixed version of Icarus Verilog +use the --suffix= flag to tell the script which +version to run e.g.(--suffix=-10 will test iverilog-10, +etc.). You can also run the test with valgrind (very very +slow) by giving the script the --with-valgrind flag. + + +#################### +# +# VPI test script +# +#################### + +To test the VPI interface type: + +perl vpi_reg.pl + +or if perl is located in /usr/bin + +./vpi_reg.pl + +All these tests should pass for V11.devel. There are +some expected failures for V10, which are flagged as +Not Implemented + +The individual test results are found in the vpi_log +directory and the gold files are in the vpi_gold +directory. The source files are in the vpi directory. +The vpi_regress.list file has the tests to perform. + +This script also takes the --suffix= and the +--with-valgrind flags described above. + + +#################### +# +# VHDL test script +# +#################### + +** Note this is no longer maintained ** + +This test script require that ghdl be installed in your +path and is used to test the Verilog to VHDL translation. + +perl vhdl_reg.pl + +or if perl is located in /usr/bin + +./vhdl_reg.pl + +The expected output for V0.10.devel and V0.9 is located +in the vhdl_regression_report-devel.txt file. V0.8 does +not support converting Verilog to VHDL. + +This script also takes the --suffix= and the +--with-valgrind flags described above. + + +#################### +# +# BLIF test script +# +#################### + +This test script require that abc be installed in your +path and is used to test the Verilog to VHDL translation. + +python blif_reg.py + +There is no expected output as of yet so to check for +regressions simply run with and without your patches. + + +#################### +# +# Windows (MinGW) test issues +# +#################### + +When running under Windows using a MinGW build in a MSYS2 +shell, the expected output from vvp_reg.pl can be found in +regression_report-msys2.txt. The MinGW/MSYS2 specific test +exceptions can be found in regress-msys2.list. Exceptions +for the VPI tests can be found in the vpi_regress.list file. + +With Windows 10 and MSYS2, there are now very few differences +between the Windows and Linux builds. diff --git a/ivtest/blif.list b/ivtest/blif.list new file mode 100644 index 000000000..6a0d10731 --- /dev/null +++ b/ivtest/blif.list @@ -0,0 +1,21 @@ +blif01a +blif01b +blif01c +blif01d +blif01e +blif01f +blif01g +blif01h +blif01i +blif02a +blif02b +blif02c +blif02d +blif02e +blif02f +blif02g +blif02h +blif02i +blif02j +blif02k +blif_shift diff --git a/ivtest/blif/blif01a.v b/ivtest/blif/blif01a.v new file mode 100644 index 000000000..259c406b5 --- /dev/null +++ b/ivtest/blif/blif01a.v @@ -0,0 +1,66 @@ + +/* + * Generate a combinational adder of any width. The width parameter can + * be any integer value >0. The A and B inputs have WID bits, and the Q + * output has WID+1 bits to include the overflow. + */ +module addN + #(parameter WID = 4) + (input wire [WID-1:0] A, + input wire [WID-1:0] B, + output wire [WID:0] Q + /* */); + + wire [WID-1:0] Cout; + + /* The least significant slice has no Cin */ + add1 U0 (.A(A[0]), .B(B[0]), .Cin(1'b0), .Q(Q[0]), .Cout(Cout[0])); + + /* Generate all the remaining slices */ + genvar i; + for (i = 1 ; i < WID ; i = i+1) begin : U + add1 Un (.A(A[i]), .B(B[i]), .Cin(Cout[i-1]), .Q(Q[i]), .Cout(Cout[i])); + end + + assign Q[WID] = Cout[WID-1]; + +endmodule // add + +/* + * This is a single-bit combinational adder used by the addH module + * above. + */ +module add1(input A, input B, input Cin, output Q, output Cout); + + assign Q = A ^ B ^ Cin; + assign Cout = A&B | A&Cin | B&Cin; + +endmodule // hadd + +`ifdef TEST_BENCH +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire [WID:0] Q; + + addN #(.WID(WID)) usum (.A(A), .B(B), .Q(Q)); + + int adx; + int bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin + for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin + A <= adx[WID-1:0]; + B <= bdx[WID-1:0]; + #1 if (Q !== (adx+bdx)) begin + $display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q); + $finish; + end + end + end + $display("PASSED"); + end + +endmodule // main +`endif diff --git a/ivtest/blif/blif01a_tb.v b/ivtest/blif/blif01a_tb.v new file mode 100644 index 000000000..c1c37775d --- /dev/null +++ b/ivtest/blif/blif01a_tb.v @@ -0,0 +1,40 @@ + +/* + * This is a post-wynthesis test for the blif01a.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif01a.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire [WID:0] Q; + + addN usum(.\A[3] (A[3]), .\A[2] (A[2]), .\A[1] (A[1]), .\A[0] (A[0]), + .\B[3] (B[3]), .\B[2] (B[2]), .\B[1] (B[1]), .\B[0] (B[0]), + .\Q[4] (Q[4]), .\Q[3] (Q[3]), .\Q[2] (Q[2]), .\Q[1] (Q[1]), .\Q[0] (Q[0])); + + int adx; + int bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin + for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin + A <= adx[WID-1:0]; + B <= bdx[WID-1:0]; + #1 if (Q !== (adx+bdx)) begin + $display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q); + $finish; + end + end + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/blif/blif01b.v b/ivtest/blif/blif01b.v new file mode 100644 index 000000000..72ab3cfa9 --- /dev/null +++ b/ivtest/blif/blif01b.v @@ -0,0 +1,9 @@ + +module test_logic(input A, B, output q_nand, q_nor, q_xnor, q_not); + + assign q_nand = A ~& B; + assign q_nor = A ~| B; + assign q_xnor = A ~^ B; + assign q_not = ~A; + +endmodule // test_logic diff --git a/ivtest/blif/blif01b_tb.v b/ivtest/blif/blif01b_tb.v new file mode 100644 index 000000000..5eaace6b1 --- /dev/null +++ b/ivtest/blif/blif01b_tb.v @@ -0,0 +1,34 @@ + +module main; + + reg [2:0] X; + wire q_nand, q_nor, q_xnor, q_not; + + test_logic DUT(.A(X[0]), .B(X[1]), .q_nand(q_nand), .q_nor(q_nor), + .q_xnor(q_xnor), .q_not(q_not)); + + initial begin + for (X = 0 ; X < 4 ; X = X+1) begin + #1 /* Let gates settle. */; + if (q_nand !== (X[0] ~& X[1])) begin + $display("FAILED -- q_nand=%b, X=%b", q_nand, X[1:0]); + $finish; + end + if (q_nor !== (X[0] ~| X[1])) begin + $display("FAILED -- q_nor=%b, X=%b", q_nor, X[1:0]); + $finish; + end + if (q_xnor !== (X[0] ~^ X[1])) begin + $display("FAILED -- q_xnor=%b, X=%b", q_xnor, X[1:0]); + $finish; + end + if (q_not !== (~X[0])) begin + $display("FAILED -- q_not=%b, X=%b", q_not, X[0]); + $finish; + end + + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/blif/blif01c.v b/ivtest/blif/blif01c.v new file mode 100644 index 000000000..4a2749952 --- /dev/null +++ b/ivtest/blif/blif01c.v @@ -0,0 +1,11 @@ + +module addN + #(parameter WID = 4) + (input wire [WID-1:0] A, + input wire [WID-1:0] B, + output wire [WID:0] Q + /* */); + + assign Q = A + B; + +endmodule // add diff --git a/ivtest/blif/blif01c_tb.v b/ivtest/blif/blif01c_tb.v new file mode 100644 index 000000000..c1c37775d --- /dev/null +++ b/ivtest/blif/blif01c_tb.v @@ -0,0 +1,40 @@ + +/* + * This is a post-wynthesis test for the blif01a.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif01a.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire [WID:0] Q; + + addN usum(.\A[3] (A[3]), .\A[2] (A[2]), .\A[1] (A[1]), .\A[0] (A[0]), + .\B[3] (B[3]), .\B[2] (B[2]), .\B[1] (B[1]), .\B[0] (B[0]), + .\Q[4] (Q[4]), .\Q[3] (Q[3]), .\Q[2] (Q[2]), .\Q[1] (Q[1]), .\Q[0] (Q[0])); + + int adx; + int bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin + for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin + A <= adx[WID-1:0]; + B <= bdx[WID-1:0]; + #1 if (Q !== (adx+bdx)) begin + $display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q); + $finish; + end + end + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/blif/blif01d.v b/ivtest/blif/blif01d.v new file mode 100644 index 000000000..03efca342 --- /dev/null +++ b/ivtest/blif/blif01d.v @@ -0,0 +1,11 @@ + +module subN + #(parameter WID = 4) + (input wire [WID-1:0] A, + input wire [WID-1:0] B, + output wire [WID:0] Q + /* */); + + assign Q = A - B; + +endmodule // add diff --git a/ivtest/blif/blif01d_tb.v b/ivtest/blif/blif01d_tb.v new file mode 100644 index 000000000..cc38885cc --- /dev/null +++ b/ivtest/blif/blif01d_tb.v @@ -0,0 +1,40 @@ + +/* + * This is a post-wynthesis test for the blif01a.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif01a.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire [WID:0] Q; + + subN usum(.\A[3] (A[3]), .\A[2] (A[2]), .\A[1] (A[1]), .\A[0] (A[0]), + .\B[3] (B[3]), .\B[2] (B[2]), .\B[1] (B[1]), .\B[0] (B[0]), + .\Q[4] (Q[4]), .\Q[3] (Q[3]), .\Q[2] (Q[2]), .\Q[1] (Q[1]), .\Q[0] (Q[0])); + + int adx; + int bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin + for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin + A <= adx[WID-1:0]; + B <= bdx[WID-1:0]; + #1 if (Q !== (adx[WID-1:0]-bdx[WID-1:0])) begin + $display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q); + $finish; + end + end + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/blif/blif01e.v b/ivtest/blif/blif01e.v new file mode 100644 index 000000000..72eac47ac --- /dev/null +++ b/ivtest/blif/blif01e.v @@ -0,0 +1,14 @@ + +module cmpN + #(parameter WID = 4) + (input wire [WID-1:0] A, + input wire [WID-1:0] B, + output wire QE, QN, QGT, QGE + /* */); + + assign QE = A == B; + assign QN = A != B; + assign QGT = A > B; + assign QGE = A >= B; + +endmodule // add diff --git a/ivtest/blif/blif01e_tb.v b/ivtest/blif/blif01e_tb.v new file mode 100644 index 000000000..a0b364ddb --- /dev/null +++ b/ivtest/blif/blif01e_tb.v @@ -0,0 +1,53 @@ + +/* + * This is a post-synthesis test for the blif01a.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif01a.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire QE, QN, QGT, QGE; + + cmpN ucmp(.\A[3] (A[3]), .\A[2] (A[2]), .\A[1] (A[1]), .\A[0] (A[0]), + .\B[3] (B[3]), .\B[2] (B[2]), .\B[1] (B[1]), .\B[0] (B[0]), + .QE(QE), .QN(QN), .QGT(QGT), .QGE(QGE)); + + int adx; + int bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin + for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin + A <= adx[WID-1:0]; + B <= bdx[WID-1:0]; + #1 ; + if (QE !== (adx[WID-1:0]==bdx[WID-1:0])) begin + $display("FAILED -- A=%b, B=%b, QE=%b", A, B, QE); + $finish; + end + if (QN !== (adx[WID-1:0]!=bdx[WID-1:0])) begin + $display("FAILED -- A=%b, B=%b, QN=%b", A, B, QN); + $finish; + end + if (QGT !== (adx[WID-1:0] > bdx[WID-1:0])) begin + $display("FAILED -- A=%b, B=%b, QGT=%b", A, B, QGT); + $finish; + end + if (QGE !== (adx[WID-1:0] >= bdx[WID-1:0])) begin + $display("FAILED -- A=%b, B=%b, QGE=%b", A, B, QGE); + $finish; + end + end + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/blif/blif01f.v b/ivtest/blif/blif01f.v new file mode 100644 index 000000000..07055204c --- /dev/null +++ b/ivtest/blif/blif01f.v @@ -0,0 +1,11 @@ + +module muxN + #(parameter WID = 4, parameter SWID = 2) + (input wire [WID-1:0] D, + input wire [SWID-1:0] S, + output wire Q + /* */); + + assign Q = D[S]; + +endmodule // add diff --git a/ivtest/blif/blif01f_tb.v b/ivtest/blif/blif01f_tb.v new file mode 100644 index 000000000..4d8c1b0e9 --- /dev/null +++ b/ivtest/blif/blif01f_tb.v @@ -0,0 +1,32 @@ + +module main; + + parameter WID = 4; + parameter SWID = 2; + + reg [WID-1:0] D; + reg [SWID-1:0] S; + wire Q; + + muxN dut(.\D[3] (D[3]), .\D[2] (D[2]), .\D[1] (D[1]), .\D[0] (D[0]), + .\S[1] (S[1]), .\S[0] (S[0]), + .Q(Q)); + + integer idx, sdx; + initial begin + for (idx = 0 ; idx < 50 ; idx += 1) begin + D = $random; + + for (sdx = 0 ; sdx < (1<0. The A and B inputs have WID bits, and the Q + * output has WID+1 bits to include the overflow. + */ +module addN + #(parameter WID = 4) + (input wire [WID-1:0] A, + input wire [WID-1:0] B, + output wire [WID:0] Q + /* */); + + wire [WID-1:0] Cout; + + /* The least significant slice has no Cin */ + add1 U0 (.A(A[0]), .B(B[0]), .Cin(1'b0), .Q(Q[0]), .Cout(Cout[0])); + + /* Generate all the remaining slices */ + genvar i; + for (i = 1 ; i < WID ; i = i+1) begin : U + add1 Un (.A(A[i]), .B(B[i]), .Cin(Cout[i-1]), .Q(Q[i]), .Cout(Cout[i])); + end + + assign Q[WID] = Cout[WID-1]; + +endmodule // add + +/* + * This is a single-bit combinational adder used by the addH module + * above. + */ +module add1(input A, input B, input Cin, output reg Q, output reg Cout); + + always @* begin + Q = A ^ B ^ Cin; + Cout = A&B | A&Cin | B&Cin; + end + +endmodule // hadd diff --git a/ivtest/blif/blif02a_tb.v b/ivtest/blif/blif02a_tb.v new file mode 100644 index 000000000..c1c37775d --- /dev/null +++ b/ivtest/blif/blif02a_tb.v @@ -0,0 +1,40 @@ + +/* + * This is a post-wynthesis test for the blif01a.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif01a.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire [WID:0] Q; + + addN usum(.\A[3] (A[3]), .\A[2] (A[2]), .\A[1] (A[1]), .\A[0] (A[0]), + .\B[3] (B[3]), .\B[2] (B[2]), .\B[1] (B[1]), .\B[0] (B[0]), + .\Q[4] (Q[4]), .\Q[3] (Q[3]), .\Q[2] (Q[2]), .\Q[1] (Q[1]), .\Q[0] (Q[0])); + + int adx; + int bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin + for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin + A <= adx[WID-1:0]; + B <= bdx[WID-1:0]; + #1 if (Q !== (adx+bdx)) begin + $display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q); + $finish; + end + end + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/blif/blif02b.v b/ivtest/blif/blif02b.v new file mode 100644 index 000000000..d8a416571 --- /dev/null +++ b/ivtest/blif/blif02b.v @@ -0,0 +1,11 @@ + +module test_logic(input A, B, output reg q_nand, q_nor, q_xnor, q_not); + + always @(A, B) begin + q_nand = A ~& B; + q_nor = A ~| B; + q_xnor = A ~^ B; + q_not = ~A; + end + +endmodule // test_logic diff --git a/ivtest/blif/blif02b_tb.v b/ivtest/blif/blif02b_tb.v new file mode 100644 index 000000000..5eaace6b1 --- /dev/null +++ b/ivtest/blif/blif02b_tb.v @@ -0,0 +1,34 @@ + +module main; + + reg [2:0] X; + wire q_nand, q_nor, q_xnor, q_not; + + test_logic DUT(.A(X[0]), .B(X[1]), .q_nand(q_nand), .q_nor(q_nor), + .q_xnor(q_xnor), .q_not(q_not)); + + initial begin + for (X = 0 ; X < 4 ; X = X+1) begin + #1 /* Let gates settle. */; + if (q_nand !== (X[0] ~& X[1])) begin + $display("FAILED -- q_nand=%b, X=%b", q_nand, X[1:0]); + $finish; + end + if (q_nor !== (X[0] ~| X[1])) begin + $display("FAILED -- q_nor=%b, X=%b", q_nor, X[1:0]); + $finish; + end + if (q_xnor !== (X[0] ~^ X[1])) begin + $display("FAILED -- q_xnor=%b, X=%b", q_xnor, X[1:0]); + $finish; + end + if (q_not !== (~X[0])) begin + $display("FAILED -- q_not=%b, X=%b", q_not, X[0]); + $finish; + end + + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/blif/blif02c.v b/ivtest/blif/blif02c.v new file mode 100644 index 000000000..0ddbf94f2 --- /dev/null +++ b/ivtest/blif/blif02c.v @@ -0,0 +1,11 @@ + +module addN + #(parameter WID = 4) + (input wire [WID-1:0] A, + input wire [WID-1:0] B, + output reg [WID:0] Q + /* */); + + always @* Q = A + B; + +endmodule // add diff --git a/ivtest/blif/blif02c_tb.v b/ivtest/blif/blif02c_tb.v new file mode 100644 index 000000000..c1c37775d --- /dev/null +++ b/ivtest/blif/blif02c_tb.v @@ -0,0 +1,40 @@ + +/* + * This is a post-wynthesis test for the blif01a.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif01a.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire [WID:0] Q; + + addN usum(.\A[3] (A[3]), .\A[2] (A[2]), .\A[1] (A[1]), .\A[0] (A[0]), + .\B[3] (B[3]), .\B[2] (B[2]), .\B[1] (B[1]), .\B[0] (B[0]), + .\Q[4] (Q[4]), .\Q[3] (Q[3]), .\Q[2] (Q[2]), .\Q[1] (Q[1]), .\Q[0] (Q[0])); + + int adx; + int bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin + for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin + A <= adx[WID-1:0]; + B <= bdx[WID-1:0]; + #1 if (Q !== (adx+bdx)) begin + $display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q); + $finish; + end + end + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/blif/blif02d.v b/ivtest/blif/blif02d.v new file mode 100644 index 000000000..ec4e09bf6 --- /dev/null +++ b/ivtest/blif/blif02d.v @@ -0,0 +1,11 @@ + +module subN + #(parameter WID = 4) + (input wire [WID-1:0] A, + input wire [WID-1:0] B, + output reg [WID:0] Q + /* */); + + always @(A or B) Q = A - B; + +endmodule // add diff --git a/ivtest/blif/blif02d_tb.v b/ivtest/blif/blif02d_tb.v new file mode 100644 index 000000000..cc38885cc --- /dev/null +++ b/ivtest/blif/blif02d_tb.v @@ -0,0 +1,40 @@ + +/* + * This is a post-wynthesis test for the blif01a.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif01a.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire [WID:0] Q; + + subN usum(.\A[3] (A[3]), .\A[2] (A[2]), .\A[1] (A[1]), .\A[0] (A[0]), + .\B[3] (B[3]), .\B[2] (B[2]), .\B[1] (B[1]), .\B[0] (B[0]), + .\Q[4] (Q[4]), .\Q[3] (Q[3]), .\Q[2] (Q[2]), .\Q[1] (Q[1]), .\Q[0] (Q[0])); + + int adx; + int bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin + for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin + A <= adx[WID-1:0]; + B <= bdx[WID-1:0]; + #1 if (Q !== (adx[WID-1:0]-bdx[WID-1:0])) begin + $display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q); + $finish; + end + end + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/blif/blif02e.v b/ivtest/blif/blif02e.v new file mode 100644 index 000000000..c48685751 --- /dev/null +++ b/ivtest/blif/blif02e.v @@ -0,0 +1,27 @@ + +module cmpN + #(parameter WID = 4) + (input wire [WID-1:0] A, + input wire [WID-1:0] B, + output reg QE, QN, QGT, QGE + /* */); + + always @(A, B) + if (A > B) begin + QE = 0; + QN = 1; + QGT = 1; + QGE = 1; + end else if (A == B) begin + QE = 1; + QN = 0; + QGT = 0; + QGE = 1; + end else begin + QE = 0; + QN = 1; + QGT = 0; + QGE = 0; + end + +endmodule // add diff --git a/ivtest/blif/blif02e_tb.v b/ivtest/blif/blif02e_tb.v new file mode 100644 index 000000000..a0b364ddb --- /dev/null +++ b/ivtest/blif/blif02e_tb.v @@ -0,0 +1,53 @@ + +/* + * This is a post-synthesis test for the blif01a.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif01a.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire QE, QN, QGT, QGE; + + cmpN ucmp(.\A[3] (A[3]), .\A[2] (A[2]), .\A[1] (A[1]), .\A[0] (A[0]), + .\B[3] (B[3]), .\B[2] (B[2]), .\B[1] (B[1]), .\B[0] (B[0]), + .QE(QE), .QN(QN), .QGT(QGT), .QGE(QGE)); + + int adx; + int bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin + for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin + A <= adx[WID-1:0]; + B <= bdx[WID-1:0]; + #1 ; + if (QE !== (adx[WID-1:0]==bdx[WID-1:0])) begin + $display("FAILED -- A=%b, B=%b, QE=%b", A, B, QE); + $finish; + end + if (QN !== (adx[WID-1:0]!=bdx[WID-1:0])) begin + $display("FAILED -- A=%b, B=%b, QN=%b", A, B, QN); + $finish; + end + if (QGT !== (adx[WID-1:0] > bdx[WID-1:0])) begin + $display("FAILED -- A=%b, B=%b, QGT=%b", A, B, QGT); + $finish; + end + if (QGE !== (adx[WID-1:0] >= bdx[WID-1:0])) begin + $display("FAILED -- A=%b, B=%b, QGE=%b", A, B, QGE); + $finish; + end + end + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/blif/blif02f.v b/ivtest/blif/blif02f.v new file mode 100644 index 000000000..7c598cf3c --- /dev/null +++ b/ivtest/blif/blif02f.v @@ -0,0 +1,11 @@ + +module muxN + #(parameter WID = 4, parameter SWID = 2) + (input wire [WID-1:0] D, + input wire [SWID-1:0] S, + output reg Q + /* */); + + always @* Q = D[S]; + +endmodule // add diff --git a/ivtest/blif/blif02f_tb.v b/ivtest/blif/blif02f_tb.v new file mode 100644 index 000000000..830df3080 --- /dev/null +++ b/ivtest/blif/blif02f_tb.v @@ -0,0 +1,32 @@ + +module main; + + parameter WID = 4; + parameter SWID = 2; + + reg [WID-1:0] D; + reg [SWID-1:0] S; + wire Q; + + muxN dut(.\D[3] (D[3]), .\D[2] (D[2]), .\D[1] (D[1]), .\D[0] (D[0]), + .\S[1] (S[1]), .\S[0] (S[0]), + .Q(Q)); + + integer idx, sdx; + initial begin + for (idx = 0 ; idx < 50 ; idx += 1) begin + D = $random; + + for (sdx = 0 ; sdx < (1< B) + QGT = 1; + else + QGT = 0; + + always @(A, B) + if (A >= B) + QGE = 1; + else + QGE = 0; + + always @(A, B) + if (A == B) + QE = 1; + else + QE = 0; + + always @(A, B) + if (A != B) + QN = 1; + else + QN = 0; + + +/* + always @(A, B) + if (A > B) begin + QE = 0; + QN = 1; + QGT = 1; + QGE = 1; + end else if (A == B) begin + QE = 1; + QN = 0; + QGT = 0; + QGE = 1; + end else begin + QE = 0; + QN = 1; + QGT = 0; + QGE = 0; + end +*/ +endmodule // add diff --git a/ivtest/blif/blif02i_tb.v b/ivtest/blif/blif02i_tb.v new file mode 100644 index 000000000..a0b364ddb --- /dev/null +++ b/ivtest/blif/blif02i_tb.v @@ -0,0 +1,53 @@ + +/* + * This is a post-synthesis test for the blif01a.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif01a.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter WID = 4; + reg [WID-1:0] A, B; + wire QE, QN, QGT, QGE; + + cmpN ucmp(.\A[3] (A[3]), .\A[2] (A[2]), .\A[1] (A[1]), .\A[0] (A[0]), + .\B[3] (B[3]), .\B[2] (B[2]), .\B[1] (B[1]), .\B[0] (B[0]), + .QE(QE), .QN(QN), .QGT(QGT), .QGE(QGE)); + + int adx; + int bdx; + initial begin + for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin + for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin + A <= adx[WID-1:0]; + B <= bdx[WID-1:0]; + #1 ; + if (QE !== (adx[WID-1:0]==bdx[WID-1:0])) begin + $display("FAILED -- A=%b, B=%b, QE=%b", A, B, QE); + $finish; + end + if (QN !== (adx[WID-1:0]!=bdx[WID-1:0])) begin + $display("FAILED -- A=%b, B=%b, QN=%b", A, B, QN); + $finish; + end + if (QGT !== (adx[WID-1:0] > bdx[WID-1:0])) begin + $display("FAILED -- A=%b, B=%b, QGT=%b", A, B, QGT); + $finish; + end + if (QGE !== (adx[WID-1:0] >= bdx[WID-1:0])) begin + $display("FAILED -- A=%b, B=%b, QGE=%b", A, B, QGE); + $finish; + end + end + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/blif/blif02j.v b/ivtest/blif/blif02j.v new file mode 100644 index 000000000..b7918dfbf --- /dev/null +++ b/ivtest/blif/blif02j.v @@ -0,0 +1,17 @@ + +module test_mux + (input wire [1:0] D0, D1, + input wire [1:0] S, + output reg [1:0] Q); + + always @(*) begin + if (S[1]==1'b0) + case (S[0]) + 1'b0: Q = D0; + 1'b1: Q = D1; + endcase // case (S[0]) + else + Q = 2'b0; + end + +endmodule // test_mux diff --git a/ivtest/blif/blif02j_tb.v b/ivtest/blif/blif02j_tb.v new file mode 100644 index 000000000..6a17d9f0f --- /dev/null +++ b/ivtest/blif/blif02j_tb.v @@ -0,0 +1,33 @@ + +module main; + + reg [1:0] D0, D1; + reg sel; + wire [1:0] Q; + + test_mux DUT(.\S[1] (1'b0), .\S[0] (sel), + .\D0[1] (D0[1]), .\D0[0] (D0[0]), + .\D1[1] (D1[1]), .\D1[0] (D1[0]), + .\Q[1] (Q[1]), .\Q[0] (Q[0])); + + initial begin + D0 = 'b01; + D1 = 'b10; + sel = 0; + #1 ; + if (Q !== D0) begin + $display("FAILED -- D0=%b, D1=%b, S=%b, Q=%b", D0, D1, sel, Q); + $finish; + end + + sel = 1; + #1 ; + if (Q !== D1) begin + $display("FAILED -- D0=%b, D1=%b, S=%b, Q=%b", D0, D1, sel, Q); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/blif/blif02k.v b/ivtest/blif/blif02k.v new file mode 100644 index 000000000..546da1d91 --- /dev/null +++ b/ivtest/blif/blif02k.v @@ -0,0 +1,25 @@ + +module test_mux + (input wire [1:0] D0, D1, + input wire [1:0] S, + output reg [1:0] Q, R); + + always @(*) begin + if (S[1]==1'b0) + case (S[0]) + 1'b0: Q = D0; + 1'b1: Q = D1; + endcase // case (S[0]) + else + Q = 2'b0; + + case (S[1]) + 1'b0: if (S[0]) + R = D1; + else + R = D0; + 1'b1: R = 2'b00; + endcase + end + +endmodule // test_mux diff --git a/ivtest/blif/blif02k_tb.v b/ivtest/blif/blif02k_tb.v new file mode 100644 index 000000000..fc3b2aec2 --- /dev/null +++ b/ivtest/blif/blif02k_tb.v @@ -0,0 +1,52 @@ + +module main; + + reg [1:0] D0, D1; + reg [1:0] sel; + wire [1:0] Q, R; + + test_mux DUT(.\S[1] (sel[1]), .\S[0] (sel[0]), + .\D0[1] (D0[1]), .\D0[0] (D0[0]), + .\D1[1] (D1[1]), .\D1[0] (D1[0]), + .\Q[1] (Q[1]), .\Q[0] (Q[0]), + .\R[1] (R[1]), .\R[0] (R[0])); + + initial begin + D0 = 'b01; + D1 = 'b10; + sel = 0; + #1 ; + if (Q !== D0) begin + $display("FAILED -- D0=%b, D1=%b, S=%b, Q=%b", D0, D1, sel, Q); + $finish; + end + if (R !== D0) begin + $display("FAILED -- D0=%b, D1=%b, S=%b, R=%b", D0, D1, sel, R); + $finish; + end + + sel = 1; + #1 ; + if (Q !== D1) begin + $display("FAILED -- D0=%b, D1=%b, S=%b, Q=%b", D0, D1, sel, Q); + $finish; + end + if (R !== D1) begin + $display("FAILED -- D0=%b, D1=%b, S=%b, R=%b", D0, D1, sel, R); + $finish; + end + + sel = 2; + #1 ; + if (Q !== 'b00) begin + $display("FAILED -- D0=%b, D1=%b, S=%b, Q=%b", D0, D1, sel, Q); + $finish; + end + if (R !== 'b00) begin + $display("FAILED -- D0=%b, D1=%b, S=%b, R=%b", D0, D1, sel, R); + $finish; + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/blif/blif_shift.v b/ivtest/blif/blif_shift.v new file mode 100644 index 000000000..a45017d07 --- /dev/null +++ b/ivtest/blif/blif_shift.v @@ -0,0 +1,25 @@ + +/* + * Generate a barrel shifter of arbitrary width. + * T can be 0 for <<, 1 for >>, 2 for <<< or 3 for >>>. + */ +module shift + #(parameter WI = 4, WS = 4, parameter WO = 6) + (input wire [WI-1:0] D, + input wire [WS-1:0] S, + output wire [WO-1:0] SHL, + output wire [WO-1:0] SHR, + output wire signed [WO-1:0] ASHL, + output wire signed [WO-1:0] ASHR + /* */); + + wire signed [WI-1:0] DS; + assign DS = D; + + assign SHL = D << S ; + assign SHR = D >> S ; + assign ASHL = DS <<< S ; + assign ASHR = DS >>> S ; + +endmodule + diff --git a/ivtest/blif/blif_shift_tb.v b/ivtest/blif/blif_shift_tb.v new file mode 100644 index 000000000..e765fc8a3 --- /dev/null +++ b/ivtest/blif/blif_shift_tb.v @@ -0,0 +1,79 @@ + +/* + * This is a post-synthesis test for the blif_shift.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif_shift.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif_shift_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter W=3; + reg [W:0] D; + reg [W:0] S; + + parameter WO=5; + wire [WO:0] SHL; + wire [WO:0] SHR; + wire [WO:0] ASHL; + wire [WO:0] ASHR; + reg [WO:0] shl; + reg [WO:0] shr; + reg [WO:0] ashl; + reg [WO:0] ashr; + +`ifdef DUMMY + shift ss(.D (D), .S (S), .SHL (SHL), .SHR (SHR), .ASHL (ASHL), .ASHR (ASHR)); +`else + shift ss(.\D[3] (D[3]), .\D[2] (D[2]), .\D[1] (D[1]), .\D[0] (D[0]), + .\S[3] (S[3]), .\S[2] (S[2]), .\S[1] (S[1]), .\S[0] (S[0]), + .\SHL[5] (SHL[5]), .\SHL[4] (SHL[4]), .\SHL[3] (SHL[3]), .\SHL[2] (SHL[2]), .\SHL[1] (SHL[1]), .\SHL[0] (SHL[0]), + .\SHR[5] (SHR[5]), .\SHR[4] (SHR[4]), .\SHR[3] (SHR[3]), .\SHR[2] (SHR[2]), .\SHR[1] (SHR[1]), .\SHR[0] (SHR[0]), + .\ASHL[5] (ASHL[5]), .\ASHL[4] (ASHL[4]), .\ASHL[3] (ASHL[3]), .\ASHL[2] (ASHL[2]), .\ASHL[1] (ASHL[1]), .\ASHL[0] (ASHL[0]), + .\ASHR[5] (ASHR[5]), .\ASHR[4] (ASHR[4]), .\ASHR[3] (ASHR[3]), .\ASHR[2] (ASHR[2]), .\ASHR[1] (ASHR[1]), .\ASHR[0] (ASHR[0])); +`endif + + int ddx; + int sdx; + initial begin + for (ddx = 0 ; ddx < 1 << (W+1) ; ddx = ddx+1) + for (sdx = 0 ; sdx < WO + 2 ; sdx = sdx+1) begin + D = ddx[W:0]; + S = sdx[W:0]; + + shl = D << S; + shr = D >> S; + ashl = $signed(D) <<< S; + ashr = $signed(D) >>> S; + +// $display("D = %b, S = %b", D, S); +// $display("shl = %b, shr = %b", shl, shr); +// $display("ashl = %b, ashr = %b", ashl, ashr); + + #1; + if (SHL !== shl) begin + $display("FAILED -- D=%b, S=%b, SHL=%b (should be %b)", D, S, SHL, shl); + $finish; + end + if (SHR !== shr) begin + $display("FAILED -- D=%b, S=%b, SHR=%b (should be %b)", D, S, SHR, shr); + $finish; + end + if (ASHL !== ashl) begin + $display("FAILED -- D=%b, S=%b, ASHL=%b (should be %b)", D, S, ASHL, ashl); + $finish; + end + if (ASHR !== ashr) begin + $display("FAILED -- D=%b, S=%b, SHL=%b (should be %b)", D, S, ASHR, ashr); + $finish; + end + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/blif/blif_sign_ext.v b/ivtest/blif/blif_sign_ext.v new file mode 100644 index 000000000..db58aa589 --- /dev/null +++ b/ivtest/blif/blif_sign_ext.v @@ -0,0 +1,15 @@ + +/* + * Sign extend input + * T can be 0 for <<, 1 for >>, 2 for <<< or 3 for >>>. + */ +module sign_ext + #(parameter WI = 4, WO = 6) + (input wire signed [WI-1:0] D, + output wire signed [WO-1:0] Q + /* */); + + assign Q = D; + +endmodule + diff --git a/ivtest/blif/blif_sign_ext_tb.v b/ivtest/blif/blif_sign_ext_tb.v new file mode 100644 index 000000000..5a8e372e3 --- /dev/null +++ b/ivtest/blif/blif_sign_ext_tb.v @@ -0,0 +1,41 @@ + +/* + * This is a post-synthesis test for the blif_sign_ext.v test. Run this + * simulation in these steps: + * + * $ iverilog -tblif -o foo.blif blif_sign_ext.v + * $ abc + * abc 01> read_blif foo.blif + * abc 02> write_verilog foo.v + * abc 03> quit + * $ iverilog -g2009 -o foo.vvp blif_sign_ext_tb.v foo.v + * $ vvp foo.vvp + */ +module main; + + parameter W=3, WO=5; + reg signed [W:0] D; + reg signed [WO:0] q; + wire [WO:0] Q; + + sign_ext se(.\D[3] (D[3]), .\D[2] (D[2]), .\D[1] (D[1]), .\D[0] (D[0]), + .\Q[5] (Q[5]), .\Q[4] (Q[4]), .\Q[3] (Q[3]), .\Q[2] (Q[2]), .\Q[1] (Q[1]), .\Q[0] (Q[0])); + + int ddx; + initial begin + for (ddx = 0 ; ddx < 1 << (W+1) ; ddx = ddx+1) begin + D = ddx[W:0]; + q = D; + + $display("D = %b, q = %b", D, q); + + #1; + if (Q !== q) begin + $display("FAILED -- D=%b, Q=%b (should be %b)", D, Q, q); + $finish; + end + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/blif_reg.py b/ivtest/blif_reg.py new file mode 100644 index 000000000..e3cefcefa --- /dev/null +++ b/ivtest/blif_reg.py @@ -0,0 +1,86 @@ +# +# This is a python script for testing the blif code generator with +# programs specifically set aside for it. The general pattern is that +# the test program comes in two parts: the test bench and the device +# to be tested. The files blif/*_tb.v are the test benches for the +# corresponding files blif/*.v. +# +# This script requires the "abc" command available here: +# +# +# Run this script with the command: python blif_reg.py +# + +import os +import subprocess +import re + +# This is the name of the iverilog command and vvp command. These may +# vary in different installations. +iverilog = "iverilog" +vvp = "vvp" + +list_file = open("blif.list") + +# The list file contains a list of test names. The first word in the +# line is the name of the test. +match_prog = re.compile(r"^([a-zA-Z0-9_.]+).*$") + +tests = [] +for line in list_file: + if line[0] == "#": + continue + match = match_prog.search(line) + if match: + tests.append(match.group(1)) + +list_file.close() + +def run_test(test): + global count_passed, count_failed + + # Assemble the paths for the test-bench and DUT. + dut = "blif/" + test + ".v" + tb = "blif/" + test + "_tb.v" + + redirect = "log/" + test + ".log 2>&1" + + # Process the DUT into a .blif file + ivl_blif_cmd = iverilog + " -g2009 -tblif -otmp_blif.blif " + dut + " > " + redirect + rc = subprocess.call(ivl_blif_cmd, shell=True) + + if rc == 0: + # Use ABC to convert the .blif file to Verilog + abc_cmd = "abc -c 'read_blif tmp_blif.blif ; write_verilog tmp_blif.v' >> " + redirect + rc = subprocess.call(abc_cmd, shell=True); + + if rc == 0: + # Compile + ivl_blif_tb_cmd = iverilog + " -g2009 -otmp_blif.vvp " + tb + " tmp_blif.v >> " + redirect + rc = subprocess.call(ivl_blif_tb_cmd, shell=True) + + if rc == 0: + # Now simulate to make sure the tranlation worked properly. + vvp_cmd = vvp + " tmp_blif.vvp" + output = subprocess.check_output(vvp_cmd, shell=True) + rc = 0 if output == "PASSED\n" else 1 + + if rc == 0: + print test, "PASSED" + count_passed = count_passed + 1 + else: + print test, "FAILED" + count_failed = count_failed + 1 + + for tmp in ["tmp_blif.blif", "tmp_blif.v", "tmp_blif.vvp"]: + if os.path.exists(tmp): + os.remove(tmp) + +count_passed = 0 +count_failed = 0 + +for test in tests: + run_test(test) + +print +print count_passed, "tests passed,", count_failed, "tests failed." diff --git a/ivtest/contrib/TEST9.ROM b/ivtest/contrib/TEST9.ROM new file mode 100644 index 000000000..daa9dd39f --- /dev/null +++ b/ivtest/contrib/TEST9.ROM @@ -0,0 +1,2048 @@ +CFF +005 +040 +006 +007 +069 +C14 +028 +209 +002 +027 +201 +026 +2E8 +A0B +2A9 +C07 +169 +A06 +FFF +FFF +FFF +FFF +FFF +FFF +FFF +FFF +FFF +FFF +FFF +FFF +FFF +FFF +FFF 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+FFF +FFF +FFF +FFF +FFF +FFF +FFF +FFF +FFF +FFF +FFF +FFF +FFF +A00 diff --git a/ivtest/contrib/add32.v b/ivtest/contrib/add32.v new file mode 100644 index 000000000..70bed4067 --- /dev/null +++ b/ivtest/contrib/add32.v @@ -0,0 +1,48 @@ +module add32(sum, cOut, clock, a, b, cIn); + + input clock; + input a, b, cIn; + output sum, cOut; + + reg [31:0] a, b; + reg cIn; + wire [31:0] sum; + wire cOut; + + always @(posedge clock) + //{cOut, sum} = a + b + cIn; + assign sum = a + b + cIn; + +endmodule + +////////////////////////// + +module main; + + reg CLOCK; + reg [31:0] A, B; + reg C_IN; + reg [31:0] SUM; + wire C_OUT; + + + add32 myAdder(SUM, C_OUT, CLOCK, A, B, C_OUT); + + always #1 CLOCK = ~ CLOCK; + + initial + begin + $monitor($time,, " CLOCK=%d, A=%x, B=%x, C_IN=%d -- SUM=%x, C_OUT=%d", +CLOCK, A, B, C_IN, SUM, C_OUT); + end + + initial + begin + CLOCK = 0; + A = 32'h00000001; + B = 32'h00000002; + C_IN = 1'b0; + #20 $finish; + end + +endmodule diff --git a/ivtest/contrib/div16.v b/ivtest/contrib/div16.v new file mode 100644 index 000000000..46a043676 --- /dev/null +++ b/ivtest/contrib/div16.v @@ -0,0 +1,260 @@ +// +// Copyright (c) 1999 Thomas Coonan (tcoonan@mindspring.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// Integer Multicycle Divide circuit (divide a 16-bit number by a 16-bit number in 16 cycles). +// +// a / b = q with remainder r +// +// Where a is 16-bits, +// Where b is 16 bits +// +// Module is actually parameterized if you want other widths. +// +// *** Test the ranges of values for which you'll use this. For example, you +// can't divide FFFF by FF without underflow (overflow?). Mess with +// the testbench. You may need to widen some thing. *** +// +// The answer is 16-bits and the remainder is also 16-bits. +// After the start pulse, the module requires 16 cycles to complete. +// The q/r outputs stay the same until next start pulse. +// Start pulse should be a single cycle. +// Division by zero results in a quotient equal to FFFF and remainder equal to 'a'. +// +// +// Written by tom coonan. +// +// Notes: +// - This ain't fancy. I wanted something straight-forward quickly. Go study +// more elaborate algorithms if you want to optimize area or speed. If you +// have an isolated divide and can spare N cycles for N bits; this may meet your needs. +// - You might want to think more about the sizes of things. I wanted a basic estimate +// of gates plus I specifically needed to divide 16-bits (not even full range) +// by 8-bits. +// - Handle divide by zero at higher level.. +// - I needed a remainder so I could easily to truncate and rounding stuff, +// but remove this to save gates if you don't need a remainder. +// - This is about 800 asic gates (0.25um, Standard Cell, 27Mhz). 27Mhz +// is my system clock and NOT the maximum it can go.. +// - I tried to keep everything parameterized by N, but I only worked through +// the N=16 case because that's what I needed... +// +module div16 (clk, resetb, start, a, b, q, r, done); + +parameter N = 16; // a/b = q remainder r, where all operands are N wide. + +input clk; +input resetb; // Asynchronous, active low reset. +input start; // Pulse this to start the division. +input [N-1:0] a; // This is the number we are dividing (the dividend) +input [N-1:0] b; // This is the 'divisor' +output [N-1:0] q; // This is the 'quotient' +output [N-1:0] r; // Here is the remainder. +output done; // Will be asserted when q and r are available. + +// Registered q +reg [N-1:0] q; +reg done; + +// Power is the current 2^n bit we are considering. Power is a shifting +// '1' that starts at the highest power of 2 and goes all the way down +// to ...00001 Shift this until it is zero at which point we stop. +// +reg [N-1:0] power; + +// This is the accumulator. We are start with the accumulator set to 'a' (the dividend). +// For each (divisor*2^N) term, we see if we can subtract (divisor*2^N) from the accumulator. +// We subtract these terms as long as adding in the term doesn't cause the accumulator +// to exceed a. When we are done, whatever is left in the accumulator is the remainder. +// +reg [N-1:0] accum; + +// This is the divisor*2^N term. Essentually, we are taking the divisor ('b'), initially +// shifting it all the way to the left, and shifting it 1 bit at a time to the right. +// +reg [(2*N-1):0] bpower; + +// Remainder will be whatever is left in the accumulator. +assign r = accum; + +// Do this addition here for resource sharing. +// ** Note that 'accum' is N bits wide, but bpower is 2*N-1 bits wide ** +// +wire [2*N-1:0] accum_minus_bpower = accum - bpower; + +always @(posedge clk or negedge resetb) begin + if (~resetb) begin + q <= 0; + accum <= 0; + power <= 0; + bpower <= 0; + done <= 0; + end + else begin + if (start) begin + // Reinitialize the divide circuit. + q <= 0; + accum <= a; // Accumulator initially gets the dividend. + power[N-1] <= 1'b1; // We start with highest power of 2 (which is a '1' in MSB) + bpower <= b << N-1; // Start with highest bpower, which is (divisor * 2^(N-1)) + done <= 0; + end + else begin + // Go until power is zero. + // + if (power != 0) begin + // + // Can we add this divisor*2^(power) to the accumulator without going negative? + // Just test the MSB of the subtraction. If it is '1', then it must be negative. + // + if ( ~accum_minus_bpower[2*N-1]) begin + // Yes! Set this power of 2 in the quotieny and + // then actually comitt to the subtraction from our accumulator. + // + q <= q | power; + accum <= accum_minus_bpower; + end + // Regardless, always go to next lower power of 2. + // + power <= power >> 1; + bpower <= bpower >> 1; + end + else begin + // We're done. Set done flag. + done <= 1; + end + end + end +end +endmodule + +// synopsys translate_off +module test_div16; +reg clk; +reg resetb; +reg start; +reg [15:0] a; +reg [15:0] b; +wire [15:0] q; +wire [15:0] r; +wire done; + +integer num_errors; + +div16 div16 ( + .clk(clk), + .resetb(resetb), + .start(start), + .a(a), + .b(b), + .q(q), + .r(r), + .done(done) +); + +initial begin + num_errors = 0; + + start = 0; + + // Wait till reset is completely over. + #200; + + // Do some divisions where divisor is constrained to 8-bits and dividend is 16-bits + $display ("16-bit Dividend, 8-bit divisor"); + repeat (25) begin + do_divide ($random, $random & 255); + end + + // Do some divisions where divisor is constrained to 12-bits and dividend is 16-bits + $display ("\n16-bit Dividend, 12-bit divisor"); + repeat (25) begin + do_divide ($random, $random & 4095); + end + + // Do some divisions where both divisor and dividend is 16-bits + $display ("\n16-bit Dividend, 16-bit divisor"); + repeat (25) begin + do_divide ($random, $random); + end + + // Special cases + $display ("\nSpecial Cases:"); + do_divide (16'hFFFF, 16'hFFFF); // largest possible quotient + do_divide (312, 1); // divide by 1 + do_divide ( 0, 42); // divide 0 by something else + do_divide (312, 0); // divide by zero + + // That's all. Summarize the test. + if (num_errors === 0) begin + $display ("\n\nPASSED"); + end + else begin + $display ("\n\nFAILED - There were %0d Errors.", num_errors); + end + + $finish; +end + +task do_divide; + input [15:0] arga; + input [15:0] argb; + + begin + a = arga; + b = argb; + @(posedge clk); + #1 start = 1; + @(posedge clk); + #1 start = 0; + while (~done) @(posedge clk); + #1; + + $display ("Circuit: %0d / %0d = %0d, rem = %0d\t\t......... Reality: %0d, rem = %0d", arga, argb, q, r, a/b, a%b); + if (b !== 0) begin + if (q !== a/b) begin + $display (" Error! Unexpected Quotient\n\n"); + num_errors = num_errors + 1; + end + if (r !== a % b) begin + $display (" Error! Unexpected Remainder\n\n"); + num_errors = num_errors + 1; + end + end + end +endtask + +initial begin + clk = 0; + forever begin + #10 clk = 1; + #10 clk = 0; + end +end + +initial begin + resetb = 0; + #133 resetb = 1; +end + +//initial begin +// $dumpfile ("test_div16.vcd"); +// $dumpvars (0,test_div16); +//end + +endmodule diff --git a/ivtest/contrib/fifo.v b/ivtest/contrib/fifo.v new file mode 100644 index 000000000..eba210fc5 --- /dev/null +++ b/ivtest/contrib/fifo.v @@ -0,0 +1,375 @@ +`begin_keywords "1364-2005" +// +// Copyright (c) 1999 Thomas Coonan (tcoonan@mindspring.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// Synchronous FIFO. 4 x 16 bit words. +// +// Modified by SDW to print out PASSED only if DEBUG not defined. +// Also changed TEST1 so that it is "self checking" by adding a +// passed in value to read_word. +// +module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp); +input clk; +input rstp; +input [15:0] din; +input readp; +input writep; +output [15:0] dout; +output emptyp; +output fullp; + +// Defines sizes in terms of bits. +// +parameter DEPTH = 3, // 2 bits, e.g. 4 words in the FIFO. + MAX_COUNT = 3'b111; // topmost address in FIFO. + +reg emptyp; +reg fullp; + +// Registered output. +reg [15:0] dout; + +// Define the FIFO pointers. A FIFO is essentially a circular queue. +// +reg [(DEPTH-1):0] tail; +reg [(DEPTH-1):0] head; + +// Define the FIFO counter. Counts the number of entries in the FIFO which +// is how we figure out things like Empty and Full. +// +reg [(DEPTH-1):0] count; + +// Define our regsiter bank. This is actually synthesizable! +// +reg [15:0] fifomem[0:MAX_COUNT]; + +// Dout is registered and gets the value that tail points to RIGHT NOW. +// +always @(posedge clk) + begin + if (rstp == 1) + dout <= 16'h0000; + else + dout <= fifomem[tail]; + end + + +// Update FIFO memory. +always @(posedge clk) begin + if (rstp == 1'b0 && writep == 1'b1 && fullp == 1'b0) begin + fifomem[head] <= din; + end +end + +// Update the head register. +// +always @(posedge clk) begin + if (rstp == 1'b1) begin + head <= 2'b00; + end + else begin + if (writep == 1'b1 && fullp == 1'b0) begin + // WRITE + head <= head + 1; + end + end +end + +// Update the tail register. +// +always @(posedge clk) begin + if (rstp == 1'b1) begin + tail <= 2'b00; + end + else begin + if (readp == 1'b1 && emptyp == 1'b0) begin + // READ + tail <= tail + 1; + end + end +end + +// Update the count regsiter. +// +always @(posedge clk) begin + if (rstp == 1'b1) begin + count <= 2'b00; + end + else begin + case ({readp, writep}) + 2'b00: count <= count; + 2'b01: + // WRITE + if (count != MAX_COUNT) + count <= count + 1; + 2'b10: + // READ + if (count != 2'b00) + count <= count - 1; + 2'b11: + // Concurrent read and write.. no change in count + count <= count; + endcase + end +end + + +// *** Update the flags +// +// First, update the empty flag. +// +always @(count) begin + if (count == 2'b00) + emptyp <= 1'b1; + else + emptyp <= 1'b0; +end + + +// Update the full flag +// +always @(count) begin + if (count == MAX_COUNT) + fullp <= 1'b1; + else + fullp <= 1'b0; +end + +endmodule + +// synopsys translate_off + +`define TEST_FIFO +// synopsys translate_off +`ifdef TEST_FIFO + + +module test_fifo; + +reg clk; +reg rstp; +reg [15:0] din; +reg readp; +reg writep; +wire [15:0] dout; +wire emptyp; +wire fullp; +reg error ; + +reg [15:0] value; + +fifo U1 ( + .clk (clk), + .rstp (rstp), + .din (din), + .readp (readp), + .writep (writep), + .dout (dout), + .emptyp (emptyp), + .fullp (fullp) +); + +// +// SDW Added self testing aspect here.. +// +task read_word; +input [15:0] expect; +begin + @(negedge clk); + readp = 1; + @(posedge clk) #5; +`ifdef DEBUG + $display ("Expect %0h, Read %0h from FIFO", +`endif // DEBUG + if(expect !== dout) + begin + $display ("FAILED - Expect %0h, Read %0h from FIFO", + expect,dout); + error = 1; + end + readp = 0; +end +endtask + +task write_word; +input [15:0] value; +begin + @(negedge clk); + din = value; + writep = 1; + @(posedge clk); +`ifdef DEBUG + $display ("Write %0h to FIFO", din); +`endif // DEBUG + #5; + din = 16'hzzzz; + writep = 0; +end +endtask + +initial begin + clk = 0; + forever begin + #10 clk = 1; + #10 clk = 0; + end +end + +initial begin + error = 0; // Set error to zero here. +`ifdef DEBUG + $dumpfile("test.vcd"); + $dumpvars(0,test_fifo); +`endif // DEBUG + test1; + //test2; + + if(error == 0) + $display("PASSED"); + $finish; +end + +task test1; +begin + din = 16'hzzzz; + writep = 0; + readp = 0; + + // Reset + rstp = 1; + #50; + rstp = 0; + #50; + + // ** Write 3 values. + write_word (16'h1111); + write_word (16'h2222); + write_word (16'h3333); + + // ** Read 2 values + read_word(16'h1111); + read_word(16'h2222); + + // ** Write one more + write_word (16'h4444); + + // ** Read a bunch of values + read_word(16'h3333); + + // *** Write a bunch more values + write_word (16'h0001); + write_word (16'h0002); + write_word (16'h0003); + write_word (16'h0004); + write_word (16'h0005); + write_word (16'h0006); + write_word (16'h0007); + write_word (16'h0008); + + // ** Read a bunch of values + read_word(16'h4444); + read_word(16'h0001); + read_word(16'h0002); + read_word(16'h0003); + read_word(16'h0004); + read_word(16'h0005); + read_word(16'h0006); +end +endtask +`ifdef TEST2 +// TEST2 +// +// This test will operate the FIFO in an orderly manner the way it normally works. +// 2 threads are forked; a reader and a writer. The writer writes a counter to +// the FIFO and obeys the fullp flag and delays randomly. The reader likewise +// obeys the emptyp flag and reads at random intervals. The result should be that +// the reader reads the incrementing counter out of the FIFO. The empty/full flags +// should bounce around depending on the random delays. The writer repeats some +// fixed number of times and then terminates both threads and kills the sim. +// +task test2; +reg [15:0] writer_counter; +begin + writer_counter = 16'h0001; + din = 16'hzzzz; + writep = 0; + readp = 0; + + // Reset + rstp = 1; + #50; + rstp = 0; + #50; + + fork + // Writer + begin + repeat (500) begin + @(negedge clk); + if (fullp == 1'b0) begin + write_word (writer_counter); + #5; + writer_counter = writer_counter + 1; + end + else begin + $display ("WRITER is waiting.."); + end + // Delay a random amount of time between 0ns and 100ns + #22 ; + end + $display ("Done with WRITER fork.."); + $finish; + end + + // Reader + begin + forever begin + @(negedge clk); + if (emptyp == 1'b0) begin + read_word; + end + else begin + $display ("READER is waiting.."); + end + // Delay a random amount of time between 0ns and 100ns + #50; + end + end + join +end +endtask + +/* +always @(fullp) + $display ("fullp = %0b", fullp); + +always @(emptyp) + $display ("emptyp = %0b", emptyp); + +always @(U1.head) + $display ("head = %0h", U1.head); + +always @(U1.tail) + $display ("tail = %0h", U1.tail); +*/ + +`endif // TEST2 + +endmodule +`endif +`end_keywords diff --git a/ivtest/contrib/gencrc.v b/ivtest/contrib/gencrc.v new file mode 100644 index 000000000..c571e0285 --- /dev/null +++ b/ivtest/contrib/gencrc.v @@ -0,0 +1,301 @@ +`begin_keywords "1364-2005" +// +// Copyright (c) 1999 Thomas Coonan (tcoonan@mindspring.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// Behavioral Verilog for CRC16 and CRC32 for use in a testbench. +// +// The specific polynomials and conventions regarding bit-ordering etc. +// are specific to the Cable Modem DOCSIS protocol, but the general scheme +// should be reusable for other types of CRCs with some fiddling. +// +// This CRC code works for a specific type of network protocol, and it +// must do certain byte swappings, etc. You may need to play with it +// for your protocol. Also, make sure the polynomials are what you +// really want. This is obviously, not synthesizable - I just used this +// in a testbench at one point. +// +// These tasks are crude and rely on some global parameters. They should +// also read from a file, yada yada yada. It is probably better to do this +// with a PLI call, but here it is anyway.. +// +// The test case includes a golden DOCSIS (Cable Modem) test message that +// was captured in a lab. +// +// tom coonan, 1999. +// +module test_gencrc; + +// *** Buffer for the Golden Message *** +reg [7:0] test_packet[0:54]; + +// *** Global parameter block for the CRC32 calculator. +// +parameter CRC32_POLY = 32'h04C11DB7; +reg [ 7:0] crc32_packet[0:255]; +integer crc32_length; +reg [31:0] crc32_result; + +// *** Global parameter block for the CRC16 calculator. +// +parameter CRC16_POLY = 16'h1020; +reg [ 7:0] crc16_packet[0:255]; +integer crc16_length; +reg [15:0] crc16_result; + +`define TEST_GENCRC +`ifdef TEST_GENCRC +// Call the main test task and then quit. +// +initial begin + main_test; + $finish; +end +`endif + +// **************************************************************** +// * +// * GOLDEN MESSAGE +// * +// * The golden message is a DOCSIS frame that was captured off +// * the Broadcom reference design. It is a MAP message. It +// * includes a HCS (crc 16) and a CRC32. +// * +// * +// **************************************************************** +// +task initialize_test_packet; + begin + test_packet[00] = 8'hC2; // FC. HCS coverage starts here. + test_packet[01] = 8'h00; // MACPARAM + test_packet[02] = 8'h00; // MAC LEN + test_packet[03] = 8'h30; // MAC LEN. HCS Coverage includes this byte and ends here. + test_packet[04] = 8'hF2; // CRC16 (also known as HCS) + test_packet[05] = 8'hCF; // CRC16 cont.. + test_packet[06] = 8'h01; // Start of the IEEE payload. CRC32 covererage starts here. This is the DA field + test_packet[07] = 8'hE0; // DA field cont.. + test_packet[08] = 8'h2F; // DA field cont.. + test_packet[09] = 8'h00; // DA field cont.. + test_packet[10] = 8'h00; // DA field cont.. + test_packet[11] = 8'h01; // DA field cont.. + test_packet[12] = 8'h00; // SA field + test_packet[13] = 8'h80; // SA field cont.. + test_packet[14] = 8'h42; // SA field cont.. + test_packet[15] = 8'h42; // SA field cont.. + test_packet[16] = 8'h20; // SA field cont.. + test_packet[17] = 8'h9E; // SA field cont.. + test_packet[18] = 8'h00; // IEEE LEN field + test_packet[19] = 8'h1E; // IEEE LEN field cont. + test_packet[20] = 8'h00; // LLC field. + test_packet[21] = 8'h00; // LLC field cont... + test_packet[22] = 8'h03; // LLC field cont... + test_packet[23] = 8'h01; // LLC field cont... + test_packet[24] = 8'h03; // LLC field cont... This is also the TYPE, which indicates MAP. + test_packet[25] = 8'h00; // LLC field cont... + test_packet[26] = 8'h01; // Start of MAP message payload. + test_packet[27] = 8'h01; // MAP message payload.. + test_packet[28] = 8'h02; // MAP message payload.. + test_packet[29] = 8'h00; // MAP message payload.. + test_packet[30] = 8'h00; // MAP message payload.. + test_packet[31] = 8'h18; // MAP message payload.. + test_packet[32] = 8'hAA; // MAP message payload.. + test_packet[33] = 8'h58; // MAP message payload.. + test_packet[34] = 8'h00; // MAP message payload.. + test_packet[35] = 8'h18; // MAP message payload.. + test_packet[36] = 8'hA8; // MAP message payload.. + test_packet[37] = 8'hA0; // MAP message payload.. + test_packet[38] = 8'h02; // MAP message payload.. + test_packet[39] = 8'h03; // MAP message payload.. + test_packet[40] = 8'h03; // MAP message payload.. + test_packet[41] = 8'h08; // MAP message payload.. + test_packet[42] = 8'hFF; // MAP message payload.. + test_packet[43] = 8'hFC; // MAP message payload.. + test_packet[44] = 8'h40; // MAP message payload.. + test_packet[45] = 8'h00; // MAP message payload.. + test_packet[46] = 8'h00; // MAP message payload.. + test_packet[47] = 8'h01; // MAP message payload.. + test_packet[48] = 8'hC0; // MAP message payload.. + test_packet[49] = 8'h14; // Last byte of MAP payload, last byte covered by CRC32. + test_packet[50] = 8'hDD; // CRC32 Starts here + test_packet[51] = 8'hBF; // CRC32 cont.. + test_packet[52] = 8'hC1; // CRC32 cont.. + test_packet[53] = 8'h2E; // Last byte of CRC32, last byte of DOCSIS. + end +endtask + +// ************************************************************************* +// * +// * Main test task. +// * +// * Use our primary "golden packet". Copy into the generic global +// * variables that the low-level 'gencrc16' and 'gencrc32' tasks use. +// * Comare against the expected values and report SUCCESS or FAILURE. +// * +// ************************************************************************* +// +task main_test; + integer i, j; + integer num_errors; + reg [15:0] crc16_expected; + reg [31:0] crc32_expected; + begin + + num_errors = 0; + + // Initialize the Golden Message! + // + initialize_test_packet; + + // **** TEST CRC16 + // + // + // Copy golden test_packet into the main crc16 buffer.. + for (i=0; i<4; i=i+1) begin + crc16_packet[i] = test_packet[i]; + end + crc16_expected = {test_packet[4], test_packet[5]}; + crc16_length = 4; // Must tell test function the length + gencrc16; // Call main test function + if (crc16_result !== crc16_expected) + begin + num_errors = num_errors + 1; + $display ("FAILED - Actual crc16_result = %h, Expected = %h", + crc16_result, crc16_expected); + end + + // **** TEST CRC16 + // + j = 0; + for (i=6; i<50; i=i+1) begin + crc32_packet[j] = test_packet[i]; + j = j + 1; + end + crc32_expected = {test_packet[50], test_packet[51], test_packet[52], test_packet[53]}; + crc32_length = 44; + gencrc32; + if (crc32_result !== crc32_expected) + begin + $display ("FAILED - Actual crc32_result = %h, Expected = %h", + crc32_result, crc32_expected); + num_errors = num_errors + 1; + end + + if(num_errors == 0) + $display("PASSED"); +end + +endtask + + +// **************************************************************** +// * +// * Main working CRC tasks are: gencrc16, gencrc32. +// * +// * These tasks rely on some globals (see front of program). +// * +// **************************************************************** + + +// Generate a (DOCSIS) CRC16. +// +// Uses the GLOBAL variables: +// +// Globals referenced: +// parameter CRC16_POLY = 16'h1020; +// reg [ 7:0] crc16_packet[0:255]; +// integer crc16_length; +// +// Globals modified: +// reg [15:0] crc16_result; +// +task gencrc16; + integer byte, bit; + reg msb; + reg [7:0] current_byte; + reg [15:0] temp; + begin + crc16_result = 16'hffff; + for (byte = 0; byte < crc16_length; byte = byte + 1) begin + current_byte = crc16_packet[byte]; + for (bit = 0; bit < 8; bit = bit + 1) begin + msb = crc16_result[15]; + crc16_result = crc16_result << 1; + if (msb != current_byte[bit]) begin + crc16_result = crc16_result ^ CRC16_POLY; + crc16_result[0] = 1; + end + end + end + + // Last step is to "mirror" every bit, swap the 2 bytes, and then complement each bit. + // + // Mirror: + for (bit = 0; bit < 16; bit = bit + 1) + temp[15-bit] = crc16_result[bit]; + + // Swap and Complement: + crc16_result = ~{temp[7:0], temp[15:8]}; + end +endtask + + +// Generate a (DOCSIS) CRC32. +// +// Uses the GLOBAL variables: +// +// Globals referenced: +// parameter CRC32_POLY = 32'h04C11DB7; +// reg [ 7:0] crc32_packet[0:255]; +// integer crc32_length; +// +// Globals modified: +// reg [31:0] crc32_result; +// + +task gencrc32; + integer byte, bit; + reg msb; + reg [7:0] current_byte; + reg [31:0] temp; + begin + crc32_result = 32'hffffffff; + for (byte = 0; byte < crc32_length; byte = byte + 1) begin + current_byte = crc32_packet[byte]; + for (bit = 0; bit < 8; bit = bit + 1) begin + msb = crc32_result[31]; + crc32_result = crc32_result << 1; + if (msb != current_byte[bit]) begin + crc32_result = crc32_result ^ CRC32_POLY; + crc32_result[0] = 1; + end + end + end + + // Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit. + // + // Mirror: + for (bit = 0; bit < 32; bit = bit + 1) + temp[31-bit] = crc32_result[bit]; + + // Swap and Complement: + crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]}; + end +endtask + +endmodule +`end_keywords diff --git a/ivtest/contrib/mult16.v b/ivtest/contrib/mult16.v new file mode 100644 index 000000000..9be2733ed --- /dev/null +++ b/ivtest/contrib/mult16.v @@ -0,0 +1,173 @@ +// +// Copyright (c) 1999 Thomas Coonan (tcoonan@mindspring.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// **** Here's a simple, sequential multiplier. Very simple, unsigned.. +// Not very well tested, play with testbench, use at your own risk, blah blah blah.. +// + +// +// Unsigned 16-bit multiply (multiply two 16-bit inputs to get a 32-bit output) +// +// Present data and assert start synchronous with clk. +// Assert start for ONLY one cycle. +// Wait N cycles for answer (at most). Answer will remain stable until next start. +// You may use DONE signal as handshake. +// +// Written by tom coonan +// +module mult16 (clk, resetb, start, done, ain, bin, yout); +parameter N = 16; +input clk; +input resetb; +input start; // Register the ain and bin inputs (they can change afterwards) +//input [N-1:0] ain; +//input [N-1:0] bin; +//output [2*N-1:0] yout; +input [15:0] ain; +input [15:0] bin; +output [31:0] yout; + +output done; + +//reg [2*N-1:0] a; +//reg [N-1:0] b; +//reg [2*N-1:0] yout; +reg [31:0] a; +reg [15:0] b; +reg [31:0] yout; + +reg done; + +always @(posedge clk or negedge resetb) begin + if (~resetb) begin + a <= 0; + b <= 0; + yout <= 0; + done <= 1'b1; + end + else begin + // Load will register the input and clear the counter. + if (start) begin + a <= ain; + b <= bin; + yout <= 0; + done <= 0; + end + else begin + // Go until b is zero + if (~done) begin + if (b != 0) begin + // If '1' then add a to sum + if (b[0]) begin + yout <= yout + a; + end + b <= b >> 1; + a <= a << 1; + $display ("a = %h, b = %h, yout = %h", a,b,yout); + end + else begin + done <= 1'b1; + end + end + end + end +end +endmodule + + +module mul16; +reg clk, resetb, start; +reg [15:0] a; +reg [15:0] b; +wire [31:0] y; +wire done; + +mult16 mult16inst (clk, resetb, start, done, a, b, y); + +initial begin + clk = 0; + forever begin + #10 clk = ~clk; + end +end + +initial begin + resetb = 0; + #30 resetb = 1; +end + +integer num_errors; +parameter MAX_TRIALS = 10; + +initial begin +// $dumpfile ("multdiv.vcd"); +// $dumpvars (0,a); +// $dumpvars (0,b); +// $dumpvars (0,y); +// $dumpvars (0,resetb); +// $dumpvars (0,done); + num_errors = 0; + + #100; + + // Do a bunch of random multiplies + repeat (MAX_TRIALS) begin + test_multiply ($random, $random); + end + + // Special cases + test_multiply ($random, 1); + test_multiply (1, $random); + test_multiply ($random, 0); + test_multiply (0, $random); + + $display ("Done. %0d Errors", num_errors); + if(num_errors == 0) + $display("PASSED"); + #800; + $finish; +end + +task test_multiply; + input [15:0] aarg; + input [15:0] barg; + + integer expected_answer; + + begin + if (~done) begin + $display ("Multiplier is Busy!!"); + end + else begin + @(negedge clk); + start = 1; + a = aarg; + b = barg; + @(negedge clk) start = 0; + @(posedge done); + expected_answer = a*b; + $display ("%0d * %0d = %0h, Reality = %0h", a, b, y, expected_answer); + if (y !== expected_answer) begin + $display (" FAILED!"); + num_errors = num_errors + 1; + end + end + end +endtask + +endmodule diff --git a/ivtest/contrib/onehot.v b/ivtest/contrib/onehot.v new file mode 100644 index 000000000..1191cbb5f --- /dev/null +++ b/ivtest/contrib/onehot.v @@ -0,0 +1,257 @@ +// +// Copyright (c) 1999 Thomas Coonan (tcoonan@mindspring.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// Just a little demo of some FSM techniques, including One-Hot and +// using 'default' settings and the case statements to selectively +// update registers (sort of like J-K flip-flops). +// +// tom coonan, 12/98. +// +// SDW - modified test to check final X and Y value... and print out +// PASSED if it's okay. +// +module onehot (clk, resetb, a, b, x, y); + +input clk; +input resetb; +input [7:0] a; +input [7:0] b; +output [7:0] x; +output [7:0] y; + +// Use One-Hot encoding. There will be 16 states. +// +reg [15:0] state, next_state; + +// These are working registers. Declare the register itself (e.g. 'x') and then +// the input bus used to load in a new value (e.g. 'x_in'). The 'x_in' bus will +// physically be a wire bus and 'x' will be the flip-flop register ('x_in' must +// be declared 'reg' because it's used in an always block. +// +reg [7:0] x, x_in; +reg [7:0] y, y_in; + +// Update state. 'state' is the actual flip-flop register and next_state is the combinatorial +// bus used to update 'state''s value. Check for the ZERO state which means an unexpected +// next state was computed. If this occurs, jump to our initialization state; state[0]. +// +// It is considered good practice by many designers to seperate the combinatorial +// and sequential aspects of state registers, and often registers in general. +// +always @(posedge clk or negedge resetb) begin + if (~resetb) state = 0; + else begin + if (next_state == 0) begin + state = 16'h0001; + end + else begin + state = next_state; + end + end +end + +// Implement the X flip-flop register. Always load the input bus into the register. +// Reset to zero. +// +always @(posedge clk or negedge resetb) begin + if (~resetb) x = 0; + else x = x_in; +end + +// Implement the Y flip-flop register. Always load the input bus into the register. +// Reset to zero. +// +always @(posedge clk or negedge resetb) begin + if (~resetb) y = 0; + else y = y_in; +end + +// Generate the next_state function. Also, based on the current state, generate +// any new values for X and Y. +// +always @(state or a or b or x or y) begin + // *** Establish defaults. + + // Working registers by default retain their current value. If any particular + // state does NOT need to change a register, then it doesn't have to reference + // the register at all. In these cases, the default below takes affect. This + // turns out to be a pretty succinct way to control stuff from the FSM. + // + x_in = x; + y_in = y; + + // State by default will be cleared. If we somehow ever got into an unknown + // state, then the default would throw state machine back to zero. Look + // at the sequential 'always' block for state to see how this is handled. + // + next_state = 0; + + // One-Hot State Machine Encoding. + // + // *** Using a 1'b1 in the case statement is the trick to doing One-Hot... + // DON'T include a 'default' clause within the case because we want to + // establish the defaults above. *** + // + case (1'b1) // synopsys parallel_case + + // Initialization state. Set X and Y register to some interesting starting values. + // + state[0]: + begin + x_in = 8'd20; + y_in = 8'd100; + next_state[1] = 1'b1; + end + + // Just for fun.. Jump through states.. + state[1]: next_state[2] = 1'b1; + state[2]: next_state[3] = 1'b1; + state[3]: next_state[4] = 1'b1; + state[4]: next_state[5] = 1'b1; + state[5]: next_state[6] = 1'b1; + state[6]: next_state[7] = 1'b1; + + // Conditionally decrement Y register. + state[7]: + begin + if (a == 1) begin + y_in = y - 1; + next_state[1] = 1'b1; + end + else begin + next_state[8] = 1'b1; + end + end + + // Just for fun.. Jump through states.. + state[8]: next_state[9] = 1'b1; + state[9]: next_state[10] = 1'b1; + state[10]: next_state[11] = 1'b1; + + // Conditionally increment X register. + state[11]: + begin + if (b == 1) begin + x_in = x + 1; + next_state[1] = 1'b1; + end + else begin + next_state[12] = 1'b1; + end + end + + // Just for fun.. Jump through states.. + state[12]: next_state[13] = 1'b1; + state[13]: next_state[14] = 1'b1; + state[14]: next_state[15] = 1'b1; + state[15]: next_state[1] = 1'b1; // Don't go back to our + // initialization state, but state + // following that one. + endcase +end +endmodule + +// synopsys translate_off +module test_onehot; +reg clk, resetb; +reg [7:0] a; +reg [7:0] b; +wire [7:0] x; +wire [7:0] y; +reg error; + +// Instantiate module. +// +onehot onehot ( + .clk(clk), + .resetb(resetb), + .a(a), + .b(b), + .x(x), + .y(y) +); + +// Generate clock. +// +initial +begin + clk = 0; + forever begin + #10 clk = ~clk; + end +end + +// Reset.. +// +initial begin + resetb = 0; + #33 resetb = 1; +end + +// Here's the test. +// +// Should see X and Y get initially loaded with their starting values. +// As long as a and b are zero, nothing should change. +// When a is asserted, Y should slowly decrement. When b is asserted, X should +// slowly increment. That's it. +// +initial begin +`ifdef DEBUG + $dumpfile("test.vcd"); + $dumpvars(0,test_onehot); +`endif // DEBUG + error = 0; + a = 0; + b = 0; + repeat (64) @(posedge clk); + #1 + + // Y should be decremented.. + a = 1; + b = 0; + repeat (256) @(posedge clk); + #1 + + // X should be incremented.. + a = 0; + b = 1; + repeat (256) @(posedge clk); + + if (x !== 8'd43) + begin + error = 1; + $display("FAILED - X Expected value 43, is %d",x); + end + + if (y !== 8'd64) + begin + error = 1; + $display("FAILED - Y Expected value 63, is %d",y); + end + + if(error == 0) + $display("PASSED"); + + $finish; +end + +// Monitor the module. +// + +endmodule diff --git a/ivtest/contrib/pic.v b/ivtest/contrib/pic.v new file mode 100644 index 000000000..3444fdb76 --- /dev/null +++ b/ivtest/contrib/pic.v @@ -0,0 +1,2262 @@ +// +// Copyright (c) 1999 Thomas Coonan (tcoonan@mindspring.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SYNTHETIC PIC 2.0 4/23/98 +// +// This is a synthesizable Microchip 16C57 compatible +// microcontroller. This core is not intended as a high fidelity model of +// the PIC, but simply a way to offer a simple processor core to people +// familiar with the PIC who also have PIC tools. +// +// pictest.v - top-level testbench (NOT SYNTHESIZABLE) +// piccpu.v - top-level synthesizable module +// picregs.v - register file instantiated under piccpu +// picalu.v - ALU instantiated under piccpu +// picidec.v - Instruction Decoder instantiated under piccpu +// hex2rom.c - C program used to translate MPLAB's INTEL HEX output +// into the Verilog $readmemh compatible file +// test*.asm - (note the wildcard..) Several test programs used +// to help debug the verilog. I used MPLAB and the simulator +// to develop these programs and get the expected results. +// Then, I ran them on Verilog-XL where they appeared to +// match. +// +// Copyright, Tom Coonan, '97. +// Use freely, but not for resale as is. You may use this in your +// own projects as desired. Just don't try to sell it as is! +// +// +module picalu ( + op, + a, + b, + y, + cin, + cout, + zout +); + +input [3:0] op; // ALU Operation +input [7:0] a; // 8-bit Input a +input [7:0] b; // 8-bit Input b +output [7:0] y; // 8-bit Output +input cin; +output cout; +output zout; + +// Reg declarations for outputs +reg cout; +reg zout; +reg [7:0] y; + +// Internal declarations +reg addercout; // Carry out straight from the adder itself. + +parameter ALUOP_ADD = 4'b0000; +parameter ALUOP_SUB = 4'b1000; +parameter ALUOP_AND = 4'b0001; +parameter ALUOP_OR = 4'b0010; +parameter ALUOP_XOR = 4'b0011; +parameter ALUOP_COM = 4'b0100; +parameter ALUOP_ROR = 4'b0101; +parameter ALUOP_ROL = 4'b0110; +parameter ALUOP_SWAP = 4'b0111; + + +always @(a or b or cin or op) begin + case (op) // synopsys full_case parallel_case + ALUOP_ADD: {addercout, y} <= a + b; + ALUOP_SUB: {addercout, y} <= a - b; // Carry out is really "borrow" + ALUOP_AND: {addercout, y} <= {1'b0, a & b}; + ALUOP_OR: {addercout, y} <= {1'b0, a | b}; + ALUOP_XOR: {addercout, y} <= {1'b0, a ^ b}; + ALUOP_COM: {addercout, y} <= {1'b0, ~a}; + ALUOP_ROR: {addercout, y} <= {a[0], cin, a[7:1]}; + ALUOP_ROL: {addercout, y} <= {a[7], a[6:0], cin}; + ALUOP_SWAP: {addercout, y} <= {1'b0, a[3:0], a[7:4]}; + default: {addercout, y} <= {1'b0, 8'h00}; + endcase +end + +always @(y) + zout <= (y == 8'h00); + +always @(addercout or op) + if (op == ALUOP_SUB) cout <= ~addercout; // Invert adder's carry to get borrow + else cout <= addercout; + +endmodule +// +// SYNTHETIC PIC 2.0 4/23/98 +// +// This is a synthesizable Microchip 16C57 compatible +// microcontroller. This core is not intended as a high fidelity model of +// the PIC, but simply a way to offer a simple processor core to people +// familiar with the PIC who also have PIC tools. +// +// pictest.v - top-level testbench (NOT SYNTHESIZABLE) +// piccpu.v - top-level synthesizable module +// picregs.v - register file instantiated under piccpu +// picalu.v - ALU instantiated under piccpu +// picidec.v - Instruction Decoder instantiated under piccpu +// hex2rom.c - C program used to translate MPLAB's INTEL HEX output +// into the Verilog $readmemh compatible file +// test*.asm - (note the wildcard..) Several test programs used +// to help debug the verilog. I used MPLAB and the simulator +// to develop these programs and get the expected results. +// Then, I ran them on Verilog-XL where they appeared to +// match. +// +// Copyright, Tom Coonan, '97. +// Use freely, but not for resale as is. You may use this in your +// own projects as desired. Just don't try to sell it as is! +// +// +module piccpu ( + clk, + reset, + paddr, + pdata, + portain, + portbout, + portcout, + + debugw, + debugpc, + debuginst, + debugstatus +); + +input clk; +input reset; +output [8:0] paddr; +input [11:0] pdata; +input [7:0] portain; +output [7:0] portbout; +output [7:0] portcout; + +output [7:0] debugw; +output [8:0] debugpc; +output [11:0] debuginst; +output [7:0] debugstatus; + +// Register declarations for outputs +reg [8:0] paddr; +reg [7:0] portbout; +reg [7:0] portcout; + +// This should be set to the ROM location where our restart vector is. +// As set here, we have 512 words of program space. +// +parameter RESET_VECTOR = 9'h1FF; + +parameter INDF_ADDRESS = 3'h0, + TMR0_ADDRESS = 3'h1, + PCL_ADDRESS = 3'h2, + STATUS_ADDRESS = 3'h3, + FSR_ADDRESS = 3'h4, + PORTA_ADDRESS = 3'h5, + PORTB_ADDRESS = 3'h6, + PORTC_ADDRESS = 3'h7; + +// Experimental custom peripheral, "Lil Adder (a 4-bit adder)" is at this address. +// +parameter EXPADDRESS_LILADDER = 7'h7F; + +// ********* Special internal registers + +// Instruction Register +reg [11:0] inst; + +// Program Counter +reg [8:0] pc; +reg [8:0] pcplus1; // Output of the pc incrementer. + +// Stack Registers and Stack "levels" register. +reg [ 1:0] stacklevel; +reg [ 8:0] stack1; +reg [ 8:0] stack2; + +// W Register +reg [ 7:0] w; + +// The STATUS register (#3) is 8 bits wide, however, we only currently use 2 bits +// of it; the C and Z bit. +// +// bit 0 - C +// bit 2 - Z +// +reg [ 7:0] status; + +// The FSR register is the pointer register used for Indirect addressing (e.g. using INDF). +reg [ 7:0] fsr; + +// Timer 0 +reg [ 7:0] tmr0; +reg [ 7:0] prescaler; + +// Option Register +reg [7:0] option; + +// Tristate Control registers. We do not neccessarily support bidirectional ports, but +// will save a place for these registers and the TRIS instruction. Use for debug. +reg [7:0] trisa; +reg [7:0] trisb; +reg [7:0] trisc; + +// I/O Port registers +// +reg [7:0] porta; // Input PORT +reg [7:0] portb; // Output PORT +reg [7:0] portc; // Output PORT + +// ********** Instruction Related signals ****** + +reg skip; // When HI force a NOP (all zeros) into inst + +reg [2:0] pcinsel; + +// Derive special sub signals from inst register +wire [ 7:0] k; +wire [ 4:0] fsel; +wire [ 8:0] longk; +wire d; +wire [ 2:0] b; + +// ********** File Address ************ +// +// This is the 7-bit Data Address that includes the lower 5-bit fsel, the +// FSR bits and any indirect addressing. +// Use this bus to address the Register File as well as all special registers, etc. +// +reg [6:0] fileaddr; + +// Address Selects +reg specialsel; +reg regfilesel; +reg expsel; + +// ****** Instruction Decoder Outputs ************** + +// Write enable for the actual ZERO and CARRY bits within the status register. +// Generated by the Instruction Decoder. +// +wire [1:0] aluasel; +wire [1:0] alubsel; +wire [3:0] aluop; + +wire zwe; +wire cwe; + +wire isoption; +wire istris; + +wire fwe; // High if any "register" is being written to at all. +wire wwe; // Write Enable for the W register. Produced by Instruction Decoder. + +// ************* Internal Busses, mux connections, etc. ******************** + +// Bit decoder bits. +reg [7:0] bd; // Final decoder value after any polarity inversion. +reg [7:0] bdec; // e.g. "Bit Decoded" + +// Data in and out of the and out of the register file +// +reg [7:0] regfilein; // Input into Register File, is connected to the dbus. +wire [7:0] regfileout; // Path leaving the register file, goes to SBUS Mux +reg regfilewe; // Write Enable +reg regfilere; // Read Enable + +// +// The dbus (Destination Bus) comes out of the ALU. It is available to all +// writable registers. +// +// The sbus (Source Bus) comes from all readable registers as well as the output +// of the Register File. It is one of the primary inputs into the ALU muxes. +// +// The ebus (Expansion Bus) comes from any of our custom modules. They must +// all coordinate to place whoever's data onto ebus. +// +reg [7:0] dbus; +reg [7:0] sbus; +reg [7:0] ebus; + + +// ALU Signals +// +reg [7:0] alua; +reg [7:0] alub; +wire [7:0] aluout; +wire alucin; +wire alucout; +wire aluz; + +// ALU A and B mux selects. +// +parameter ALUASEL_W = 2'b00, + ALUASEL_SBUS = 2'b01, + ALUASEL_K = 2'b10, + ALUASEL_BD = 2'b11; + +parameter ALUBSEL_W = 2'b00, + ALUBSEL_SBUS = 2'b01, + ALUBSEL_K = 2'b10, + ALUBSEL_1 = 2'b11; + +// ALU Operation codes. +// +parameter ALUOP_ADD = 4'b0000; +parameter ALUOP_SUB = 4'b1000; +parameter ALUOP_AND = 4'b0001; +parameter ALUOP_OR = 4'b0010; +parameter ALUOP_XOR = 4'b0011; +parameter ALUOP_COM = 4'b0100; +parameter ALUOP_ROR = 4'b0101; +parameter ALUOP_ROL = 4'b0110; +parameter ALUOP_SWAP = 4'b0111; + + +// Instantiate each of our subcomponents +// +picregs regs ( + .clk (clk), + .reset (reset), + .we (regfilewe), + .re (regfilere), + .bank (fileaddr[6:5]), + .location (fileaddr[4:0]), + .din (regfilein), + .dout (regfileout) +); + +// Instatiate the ALU. +// +picalu alu ( + .op (aluop), + .a (alua), + .b (alub), + .y (aluout), + .cin (status[0]), + .cout (alucout), + .zout (aluz) +); + +// Instantiate the Instruction Decoder. This is really just a lookup table. +// Given the instruction, generate all the signals we need. +// +// For example, each instruction implies a specific ALU operation. Some of +// these are obvious such as the ADDW uses an ADD alu op. Less obvious is +// that a mov instruction uses an OR op which lets us do a simple copy. +// +// Data has to funnel through the ALU, which sometimes makes for contrived +// ALU ops. +// +picidec idec ( + .inst (inst), + .aluasel (aluasel), + .alubsel (alubsel), + .aluop (aluop), + .wwe (wwe), + .fwe (fwe), + .zwe (zwe), + .cwe (cwe), + .bdpol (bdpol), + .option (isoption), + .tris (istris) +); + +// *********** Debug **************** +assign debugw = w; +assign debugpc = pc; +assign debuginst = inst; +assign debugstatus = status; + +// *********** REGISTER FILE Addressing **************** +// +// We implement the following: +// - The 5-bit fsel address is within a "BANK" which is 32 bytes. +// - The FSR bits 6:5 are the BANK select, so there are 4 BANKS, a +// total of 128 bytes. Minus the 8 special registers, that's +// really 120 bytes. +// - The INDF register is for indirect addressing. Referencing INDF +// uses FSR as the pointer. Therefore, using INDF/FSR you address +// 7-bits of memory. +// We DO NOT currently implement the PAGE for program (e.g. STATUS register +// bits 6:5) +// +// The fsel address *may* be zero in which case, we are to do indirect +// addressing, using FSR register as the 8-bit pointer. +// +// Otherwise, use the 5-bits of FSEL (from the Instruction itself) and +// 2 bank bits from the FSR register (bits 6:5). +// +always @(fsel or fsr) begin + if (fsel == INDF_ADDRESS) begin + // The INDEX register is addressed. There really is no INDEX register. + // Use the FSR as an index, e.g. the FSR contents are the fsel. + // + fileaddr <= fsr[6:0]; + end + else begin + // Use FSEL field and status bank select bits + // + fileaddr <= {fsr[6:5], fsel}; + end +end + +// Write Enable to Register File. +// Assert this when the general fwe (write enable to *any* register) is true AND Register File +// address range is specified. +// +always @(regfilesel or fwe) + regfilewe <= regfilesel & fwe; + +// Read Enable (this if nothing else, helps in debug.) +// Assert if Register File address range is specified AND the ALU is actually using some +// data off the SBUS. +// +always @(regfilesel or aluasel or alubsel) + regfilere <= regfilesel & ((aluasel == ALUASEL_SBUS) | (alubsel == ALUBSEL_SBUS)); + +// *********** Address Decodes ************** +// +// Generate 3 selects: specialsel, regfilesel and expsel +always @(fileaddr) begin + casex (fileaddr) + 7'bXX00XXX: // The SPECIAL Registers are lower 8 addresses, in ALL BANKS + begin + specialsel <= 1'b1; + regfilesel <= 1'b0; + expsel <= 1'b0; + end + 7'b1111111: // EXPANSION Registers are the top (1) addresses + begin + specialsel <= 1'b0; + regfilesel <= 1'b0; + expsel <= 1'b1; + end + default: // Anything else must be in the Register File + begin + specialsel <= 1'b0; + regfilesel <= 1'b1; + expsel <= 1'b0; + end + endcase +end + +// *********** SBUS ************** +// The sbus (Source Bus) is the output of a multiplexor that takes +// inputs from the Register File, and all other special registers +// and input ports. The Source Bus then, one of the inputs to the ALU + + +// First MUX selects from all the special regsiters +// +always @(fsel or fsr or tmr0 or pc or status + or porta or portb or portc or regfileout or ebus + or specialsel or regfilesel or expsel) begin + + // For our current mix of registers and peripherals, only the first 8 addresses + // are "special" registers (e.g. not in the Register File). As more peripheral + // registers are added, they must be muxed into this MUX as well. + // + // We currently prohibit tristates. + // + // + if (specialsel) begin + // Special register + case (fsel[2:0]) // synopsys parallel_case full_case + 3'h0: sbus <= fsr; + 3'h1: sbus <= tmr0; + 3'h2: sbus <= pc[7:0]; + 3'h3: sbus <= status; + 3'h4: sbus <= fsr; + 3'h5: sbus <= porta; // PORTA is an input-only port + 3'h6: sbus <= portb; // PORTB is an output-only port + 3'h7: sbus <= portc; // PORTC is an output-only port + endcase + end + else begin + // + // Put whatever address equation is neccessary here. Remember to remove unnecessary + // memory elements from Register File (picregs.v). It'll still work, but they'd be + // wasted flip-flops. + // + if (expsel) begin + sbus <= ebus; + end + else begin + if (regfilesel) begin + // Final Priority is Choose the register file + sbus <= regfileout; + end + else begin + sbus <= 8'h00; + end + end + end +end + +// ************** DBUS ****** +// The Destination bus is just the output of the ALU. +// +always @(aluout) + dbus <= aluout; + +always @(dbus) + regfilein <= dbus; + +// Drive the ROM address bus straight from the PC +// +always @(pc) + paddr = pc; + + +// Define sub-signals out of inst +// +assign k = inst[7:0]; +assign fsel = inst[4:0]; +assign longk = inst[8:0]; +assign d = inst[5]; +assign b = inst[7:5]; + +// Bit Decoder. +// +// Simply take the 3-bit b field in the PIC instruction and create the +// expanded 8-bit decoder field, which is used as a mask. +// + + +always @(b) begin + case (b) + 3'b000: bdec <= 8'b00000001; + 3'b001: bdec <= 8'b00000010; + 3'b010: bdec <= 8'b00000100; + 3'b011: bdec <= 8'b00001000; + 3'b100: bdec <= 8'b00010000; + 3'b101: bdec <= 8'b00100000; + 3'b110: bdec <= 8'b01000000; + 3'b111: bdec <= 8'b10000000; + endcase +end + +always @(bdec or bdpol) + bd <= bdec ^ bdpol; + +// Instruction regsiter usually get the ROM data as its input, but +// sometimes for branching, the skip signal must cause a NOP. +// +always @(posedge clk) begin + if (reset) begin + inst <= 12'h000; + end + else begin + if (skip == 1'b1) begin + inst <= 12'b000000000000; // FORCE NOP + end + else begin + inst <= pdata; + end + end +end + +// SKIP signal. +// +// We want to insert the NOP instruction for the following conditions: +// GOTO,CALL and RETLW instructions (All have inst[11:10] = 2'b10 +// BTFSS instruction when aluz is HI ( +// BTFSC instruction when aluz is LO +// +always @(inst or aluz) begin + casex ({inst, aluz}) + 13'b10??_????_????_?: // A GOTO, CALL or RETLW instructions + skip <= 1'b1; + + 13'b0110_????_????_1: // BTFSC instruction and aluz == 1 + skip <= 1'b1; + + 13'b0111_????_????_0: // BTFSS instruction and aluz == 0 + skip <= 1'b1; + + 13'b0010_11??_????_1: // DECFSZ instruction and aluz == 1 + skip <= 1'b1; + + 13'b0011_11??_????_1: // INCFSZ instruction and aluz == 1 + skip <= 1'b1; + + default: + skip <= 1'b0; + endcase +end + +// 4:1 Data MUX into alua +// +// +always @(aluasel or w or sbus or k or bd) begin + case (aluasel) + 2'b00: alua <= w; + 2'b01: alua <= sbus; + 2'b10: alua <= k; + 2'b11: alua <= bd; + endcase +end + +// 4:1 Data MUX into alub +// +// +always @(alubsel or w or sbus or k) begin + case (alubsel) + 2'b00: alub <= w; + 2'b01: alub <= sbus; + 2'b10: alub <= k; + 2'b11: alub <= 8'b00000001; + endcase +end + +// W Register +always @(posedge clk) begin + if (reset) begin + w <= 8'h00; + end + else begin + if (wwe) begin + w <= dbus; + end + end +end + +// ************ Writes to various Special Registers (fsel between 0 and 7) + +// INDF Register (Register #0) +// +// Not a real register. This is the Indirect Addressing mode register. +// See the regfileaddr logic. + +// TMR0 Register (Register #1) +// +// Timer0 is currently only a free-running timer clocked by the main system clock. +// +always @(posedge clk) begin + if (reset) begin + tmr0 <= 8'h00; + end + else begin + // See if the status register is actually being written to + if (fwe & specialsel & (fsel == TMR0_ADDRESS)) begin + // Yes, so just update the register from the dbus + tmr0 <= dbus; + end + else begin + // Mask off the prescaler value based on desired divide ratio. + // Whenever this is zero, then that is our divided pulse. Increment + // the final timer value when it's zero. + // + case (option[2:0]) // synopsys parallel_case full_case + 3'b000: if (~|(prescaler & 8'b00000001)) tmr0 <= tmr0 + 1; + 3'b001: if (~|(prescaler & 8'b00000011)) tmr0 <= tmr0 + 1; + 3'b010: if (~|(prescaler & 8'b00000111)) tmr0 <= tmr0 + 1; + 3'b011: if (~|(prescaler & 8'b00001111)) tmr0 <= tmr0 + 1; + 3'b100: if (~|(prescaler & 8'b00011111)) tmr0 <= tmr0 + 1; + 3'b101: if (~|(prescaler & 8'b00111111)) tmr0 <= tmr0 + 1; + 3'b110: if (~|(prescaler & 8'b01111111)) tmr0 <= tmr0 + 1; + 3'b111: if (~|(prescaler & 8'b11111111)) tmr0 <= tmr0 + 1; + endcase + end + end +end + +// The prescaler is always counting from 00 to FF +always @(posedge clk) begin + if (reset) begin + prescaler <= 8'h00; + end + else begin + // See if the status register is actually being written to + prescaler <= prescaler + 1; + end +end + + +// PCL Register (Register #2) +// +// PC Lower 8 bits. This is handled in the PC section below... + + +// STATUS Register (Register #3) +// +always @(posedge clk) begin + if (reset) begin + status <= 8'h00; + end + else begin + // See if the status register is actually being written to + if (fwe & specialsel & (fsel == STATUS_ADDRESS)) begin + // Yes, so just update the register from the dbus + status <= dbus; + end + else begin + // Update status register on a bit-by-bit basis. + // + // For the carry and zero flags, each instruction has its own rule as + // to whether to update this flag or not. The instruction decoder is + // providing us with an enable for C and Z. Use this to decide whether + // to retain the existing value, or update with the new alu status output. + // + status <= { + status[7], // BIT 7: Undefined.. (maybe use for debugging) + status[6], // BIT 6: Program Page, HI bit + status[5], // BIT 5: Program Page, LO bit + status[4], // BIT 4: Time Out bit (not implemented at this time) + status[3], // BIT 3: Power Down bit (not implemented at this time) + (zwe) ? aluz : status[2], // BIT 2: Z + status[1], // BIT 1: DC + (cwe) ? alucout : status[0] // BIT 0: C + }; + end + end +end + +// FSR Register (Register #4) +// +always @(posedge clk) begin + if (reset) begin + fsr <= 8'h00; + end + else begin + // See if the status register is actually being written to + if (fwe & specialsel & (fsel == FSR_ADDRESS)) begin + fsr <= dbus; + end + end +end + +// OPTION Register +// +// The special OPTION instruction should move W into the OPTION register. +always @(posedge clk) begin + if (reset) begin + option <= 8'h00; + end + else begin + if (isoption) + option <= dbus; + end +end + +// PORTA Input Port (Register #5) +// +// Register anything on the module's porta input on every single clock. +// +always @(posedge clk) begin + if (reset) begin + porta <= 8'h00; + end + else begin + porta <= portain; + end +end + +// PORTB Output Port (Register #6) +always @(posedge clk) begin + if (reset) begin + portb <= 8'h00; + end + else begin + if (fwe & specialsel & (fsel == PORTB_ADDRESS) & ~istris) begin + portb <= dbus; + end + end +end + +// Connect the output ports to the register output. +always @(portb) + portbout <= portb; + +// PORTC Output Port (Register #7) +always @(posedge clk) begin + if (reset) begin + portc <= 8'h00; + end + else begin + if (fwe & specialsel & (fsel == PORTC_ADDRESS) & ~istris) begin + portc <= dbus; + end + end +end + +// Connect the output ports to the register output. +always @(portc) + portcout <= portc; + +// TRIS Registers +always @(posedge clk) begin + if (reset) begin + trisa <= 8'hff; // Default is to tristate them + end + else begin + if (fwe & specialsel & (fsel == PORTA_ADDRESS) & istris) begin + trisa <= dbus; + end + end +end + +always @(posedge clk) begin + if (reset) begin + trisb <= 8'hff; // Default is to tristate them + end + else begin + if (fwe & specialsel & (fsel == PORTB_ADDRESS) & istris) begin + trisb <= dbus; + end + end +end + +always @(posedge clk) begin + if (reset) begin + trisc <= 8'hff; // Default is to tristate them + end + else begin + if (fwe & specialsel & (fsel == PORTC_ADDRESS) & istris) begin + trisc <= dbus; + end + end +end + + +// ********** PC AND STACK ************************* +// +// There are 4 ways to change the PC. They are: +// GOTO 101k_kkkk_kkkk +// CALL 1001_kkkk_kkkk +// RETLW 1000_kkkk_kkkk +// MOVF 0010_0010_0010 (e.g. a write to reg #2) +// +// Remember that the skip instructions work by inserting +// a NOP instruction or not into program stream and don't +// change the PC. +// + +// We need pc + 1 in several places, so lets define this incrementor and +// its output signal it in one place so that we never get redundant adders. +// +always @(pc) + pcplus1 <= pc + 1; + +parameter PC_SELECT_PCPLUS1 = 3'b000, + PC_SELECT_K = 3'b001, + PC_SELECT_STACK1 = 3'b010, + PC_SELECT_STACK2 = 3'b011, + PC_SELECT_DBUS = 3'b100, + PC_SELECT_RESET_VECTOR = 3'b101; + +// 8:1 Data MUX into PC +always @(posedge clk) begin + case (pcinsel) // synopsys parallel_case full_case + 3'b000: pc <= pcplus1; + 3'b001: pc <= k; + 3'b010: pc <= stack1; + 3'b011: pc <= stack2; + 3'b100: pc <= dbus; + 3'b101: pc <= RESET_VECTOR; + + // Don't really carry about these... + 3'b110: pc <= pc; + 3'b111: pc <= pc; + endcase +end + +// Select for the MUX going into the PC. +// +// +always @(inst or stacklevel or reset) begin + if (reset == 1'b1) begin + pcinsel <= PC_SELECT_RESET_VECTOR; + end + else begin + casex ({inst, stacklevel}) + 14'b101?_????_????_??: pcinsel <= PC_SELECT_K; // GOTO + 14'b1001_????_????_??: pcinsel <= PC_SELECT_K; // CALL + 14'b1000_????_????_00: pcinsel <= PC_SELECT_STACK1; // RETLW + 14'b1000_????_????_01: pcinsel <= PC_SELECT_STACK1; // RETLW + 14'b1000_????_????_10: pcinsel <= PC_SELECT_STACK2; // RETLW + 14'b1000_????_????_11: pcinsel <= PC_SELECT_STACK2; // RETLW + 14'b0010_0010_0010_??: pcinsel <= PC_SELECT_DBUS; // MOVF where f=PC + default: + pcinsel <= PC_SELECT_PCPLUS1; + endcase + end +end + + +// Implement STACK1 and STACK2 registers +// +// The Stack registers are only fed from the PC itself! +// +always @(posedge clk) begin + if (reset) begin + stack1 <= 9'h000; + end + else begin + // CALL instruction + if (inst[11:8] == 4'b1001) begin + case (stacklevel) + 2'b00: + // No previous CALLs + begin + stack1 <= pc; + $display ("Write to STACK1: %0h", pc); + end + 2'b01: + // ONE previous CALL + begin + stack2 <= pc; + $display ("Write to STACK2: %0h", pc); + end + 2'b10: + // TWO previous CALLs -- This is illegal on the 16C5X! + begin + $display ("Too many CALLs!!"); + end + 2'b11: + begin + $display ("Too many CALLs!!"); + end + endcase + end + end +end + +// Write to stacklevel +// +// The stacklevel register keeps track of the current stack depth. On this +// puny processor, there are only 2 levels (you could fiddle with this and +// increase the stack depth). There are two stack registers, stack1 and stack2. +// The stack1 register is used first (e.g. the first time a call is performed), +// then stack2. As CALLs are done, stacklevel increments. Conversely, as +// RETs are done, stacklevel goes down. + +always @(posedge clk) begin + if (reset == 1'b1) begin + stacklevel <= 2'b00; // On reset, there should be no CALLs in progress + end + else begin + casex ({inst, stacklevel}) + // Call instructions + 14'b1001_????_????_00: stacklevel <= 2'b01; // Record 1st CALL + 14'b1001_????_????_01: stacklevel <= 2'b10; // Record 2nd CALL + 14'b1001_????_????_10: stacklevel <= 2'b10; // Already 2! Ignore + 14'b1001_????_????_11: stacklevel <= 2'b00; // {shouldn't happen} + + // Return instructions + 14'b1000_????_????_00: stacklevel <= 2'b00; // {shouldn't happen} + 14'b1000_????_????_01: stacklevel <= 2'b00; // Go back to no CALL in progress + 14'b1000_????_????_10: stacklevel <= 2'b01; // Go back to 1 CALL in progress + 14'b1000_????_????_11: stacklevel <= 2'b10; // {shouldn't happen} sort of like, Go back to 2 calls in progress + default: + stacklevel <= stacklevel; + endcase + end +end + + + +// ************ EXPANSION ************************* +// +// The following is an example of customization. +// +// Example: Create a read/write port located at address 7F. It'll be 8-bits, where +// the upper 4 bits are outputs and the lower 4 bits are inputs. +// Use indirect addressing to access it (INDF/FSR). Just for fun, let's +// attach a special loop-back circuit between the outputs and inputs. +// Let's attach... say... a 4-bit adder. +// + +reg [3:0] special_peripheral_writeable_bits; +reg [3:0] special_peripheral_readeable_bits; + +// Implement the writeable bits. +// +always @(posedge clk) begin + if (reset) begin + special_peripheral_writeable_bits <= 4'b0000; + end + else begin + if (fwe & expsel & (fileaddr == EXPADDRESS_LILADDER)) begin + special_peripheral_writeable_bits <= dbus; + end + end +end + +// Implement the special peripheral function (the 4-bit adder for this example). +always @(special_peripheral_writeable_bits) begin + special_peripheral_readeable_bits <= special_peripheral_writeable_bits + 1; +end + +// Drive the ebus. With only one custom address, no more muxing needs to be +// done, but if there are multiple custom circuits, everyone needs to cooperate +// and drive ebus properly. +// +always @(fileaddr or special_peripheral_readeable_bits) begin + if (fileaddr == EXPADDRESS_LILADDER) + ebus <= special_peripheral_readeable_bits; + else + ebus <= 8'hff; +end + +endmodule +// +// SYNTHETIC PIC 2.0 4/23/98 +// +// This is a synthesizable Microchip 16C57 compatible +// microcontroller. This core is not intended as a high fidelity model of +// the PIC, but simply a way to offer a simple processor core to people +// familiar with the PIC who also have PIC tools. +// +// pictest.v - top-level testbench (NOT SYNTHESIZABLE) +// piccpu.v - top-level synthesizable module +// picregs.v - register file instantiated under piccpu +// picalu.v - ALU instantiated under piccpu +// picidec.v - Instruction Decoder instantiated under piccpu +// hex2rom.c - C program used to translate MPLAB's INTEL HEX output +// into the Verilog $readmemh compatible file +// test*.asm - (note the wildcard..) Several test programs used +// to help debug the verilog. I used MPLAB and the simulator +// to develop these programs and get the expected results. +// Then, I ran them on Verilog-XL where they appeared to +// match. +// +// Copyright, Tom Coonan, '97. +// Use freely, but not for resale as is. You may use this in your +// own projects as desired. Just don't try to sell it as is! +// +// +// This is the PIC Instruction Decoder. +// +// The 12-bit PIC instruction must result in a set of control +// signals to the ALU, register write enables and other wires. +// This is purely combinatorial. This can physically be +// implemented as a ROM, or, in this implementation a Verilog +// casex statement is used to directly synthesize the signals. +// This approach is more portable, and hopefully much reduction +// occurs in the equations. +// +// The Synthetic PIC Manual contains a table that better shows +// all the required signals per instruction. I basically +// took that table and created the Verilog implementation below. +// + +module picidec ( + inst, + aluasel, + alubsel, + aluop, + wwe, + fwe, + zwe, + cwe, + bdpol, + option, + tris +); + +input [11:0] inst; + +output [1:0] aluasel; +output [1:0] alubsel; +output [3:0] aluop; +output wwe; +output fwe; +output zwe; +output cwe; +output bdpol; +output option; +output tris; + +reg [14:0] decodes; + +// For reference, the ALU Op codes are: +// +// ADD 0000 +// SUB 1000 +// AND 0001 +// OR 0010 +// XOR 0011 +// COM 0100 +// ROR 0101 +// ROL 0110 +// SWAP 0111 + +assign { aluasel, // Select source for ALU A input. 00=W, 01=SBUS, 10=K, 11=BD + alubsel, // Select source for ALU B input. 00=W, 01=SBUS, 10=K, 11="1" + aluop, // ALU Operation (see comments above for these codes) + wwe, // W register Write Enable + fwe, // File Register Write Enable + zwe, // Status register Z bit update + cwe, // Status register Z bit update + bdpol, // Polarity on bit decode vector (0=no inversion, 1=invert) + tris, // Instruction is an TRIS instruction + option // Instruction is an OPTION instruction + } = decodes; + +// This is a large combinatorial decoder. +// I use the casex statement. + +always @(inst) begin + casex (inst) + // *** Byte-Oriented File Register Operations + // + // A A ALU W F Z C B T O + // L L O W W W W D R P + // U U P E E E E P I T + // A B O S + // L + 12'b0000_0000_0000: decodes <= 15'b00_00_0000_0_0_0_0_0_0_0; // NOP + 12'b0000_001X_XXXX: decodes <= 15'b00_00_0010_0_1_0_0_0_0_0; // MOVWF + 12'b0000_0100_0000: decodes <= 15'b00_00_0011_1_0_1_0_0_0_0; // CLRW + 12'b0000_011X_XXXX: decodes <= 15'b00_00_0011_0_1_1_0_0_0_0; // CLRF + 12'b0000_100X_XXXX: decodes <= 15'b01_00_1000_1_0_1_1_0_0_0; // SUBWF (d=0) + 12'b0000_101X_XXXX: decodes <= 15'b01_00_1000_0_1_1_1_0_0_0; // SUBWF (d=1) + 12'b0000_110X_XXXX: decodes <= 15'b01_11_1000_1_0_1_0_0_0_0; // DECF (d=0) + 12'b0000_111X_XXXX: decodes <= 15'b01_11_1000_0_1_1_0_0_0_0; // DECF (d=1) + 12'b0001_000X_XXXX: decodes <= 15'b00_01_0010_1_0_1_0_0_0_0; // IORWF (d=0) + 12'b0001_001X_XXXX: decodes <= 15'b00_01_0010_0_1_1_0_0_0_0; // IORWF (d=1) + 12'b0001_010X_XXXX: decodes <= 15'b00_01_0001_1_0_1_0_0_0_0; // ANDWF (d=0) + 12'b0001_011X_XXXX: decodes <= 15'b00_01_0001_0_1_1_0_0_0_0; // ANDWF (d=1) + 12'b0001_100X_XXXX: decodes <= 15'b00_01_0011_1_0_1_0_0_0_0; // XORWF (d=0) + 12'b0001_101X_XXXX: decodes <= 15'b00_01_0011_0_1_1_0_0_0_0; // XORWF (d=1) + 12'b0001_110X_XXXX: decodes <= 15'b00_01_0000_1_0_1_1_0_0_0; // ADDWF (d=0) + 12'b0001_111X_XXXX: decodes <= 15'b00_01_0000_0_1_1_1_0_0_0; // ADDWF (d=1) + 12'b0010_000X_XXXX: decodes <= 15'b01_01_0010_1_0_1_0_0_0_0; // MOVF (d=0) + 12'b0010_001X_XXXX: decodes <= 15'b01_01_0010_0_1_1_0_0_0_0; // MOVF (d=1) + 12'b0010_010X_XXXX: decodes <= 15'b01_01_0100_1_0_1_0_0_0_0; // COMF (d=0) + 12'b0010_011X_XXXX: decodes <= 15'b01_01_0100_0_1_1_0_0_0_0; // COMF (d=1) + 12'b0010_100X_XXXX: decodes <= 15'b01_11_0000_1_0_1_0_0_0_0; // INCF (d=0) + 12'b0010_101X_XXXX: decodes <= 15'b01_11_0000_0_1_1_0_0_0_0; // INCF (d=1) + 12'b0010_110X_XXXX: decodes <= 15'b01_11_1000_1_0_0_0_0_0_0; // DECFSZ(d=0) + 12'b0010_111X_XXXX: decodes <= 15'b01_11_1000_0_1_0_0_0_0_0; // DECFSZ(d=1) + 12'b0011_000X_XXXX: decodes <= 15'b01_01_0101_1_0_0_1_0_0_0; // RRF (d=0) + 12'b0011_001X_XXXX: decodes <= 15'b01_01_0101_0_1_0_1_0_0_0; // RRF (d=1) + 12'b0011_010X_XXXX: decodes <= 15'b01_01_0110_1_0_0_1_0_0_0; // RLF (d=0) + 12'b0011_011X_XXXX: decodes <= 15'b01_01_0110_0_1_0_1_0_0_0; // RLF (d=1) + 12'b0011_100X_XXXX: decodes <= 15'b01_01_0111_1_0_0_0_0_0_0; // SWAPF (d=0) + 12'b0011_101X_XXXX: decodes <= 15'b01_01_0111_0_1_0_0_0_0_0; // SWAPF (d=1) + 12'b0011_110X_XXXX: decodes <= 15'b01_11_0000_1_0_0_0_0_0_0; // INCFSZ(d=0) + 12'b0011_111X_XXXX: decodes <= 15'b01_11_0000_0_1_0_0_0_0_0; // INCFSZ(d=1) + + // *** Bit-Oriented File Register Operations + // + // A A ALU W F Z C B T O + // L L O W W W W D R P + // U U P E E E E P I T + // A B O S + // L + 12'b0100_XXXX_XXXX: decodes <= 15'b11_01_0001_0_1_0_0_1_0_0; // BCF + 12'b0101_XXXX_XXXX: decodes <= 15'b11_01_0010_0_1_0_0_0_0_0; // BSF + 12'b0110_XXXX_XXXX: decodes <= 15'b11_01_0001_0_0_0_0_0_0_0; // BTFSC + 12'b0111_XXXX_XXXX: decodes <= 15'b11_01_0001_0_0_0_0_0_0_0; // BTFSS + + // *** Literal and Control Operations + // + // A A ALU W F Z C B T O + // L L O W W W W D R P + // U U P E E E E P I T + // A B O S + // L + 12'b0000_0000_0010: decodes <= 15'b00_00_0010_0_1_0_0_0_0_1; // OPTION + 12'b0000_0000_0011: decodes <= 15'b00_00_0000_0_0_0_0_0_0_0; // SLEEP + 12'b0000_0000_0100: decodes <= 15'b00_00_0000_0_0_0_0_0_0_0; // CLRWDT + 12'b0000_0000_0101: decodes <= 15'b00_00_0000_0_1_0_0_0_1_0; // TRIS 5 + 12'b0000_0000_0110: decodes <= 15'b00_00_0010_0_1_0_0_0_1_0; // TRIS 6 + 12'b0000_0000_0111: decodes <= 15'b00_00_0010_0_1_0_0_0_1_0; // TRIS 7 + // + // A A ALU W F Z C B T O + // L L O W W W W D R P + // U U P E E E E P I T + // A B O S + // L + 12'b1000_XXXX_XXXX: decodes <= 15'b10_10_0010_1_0_0_0_0_0_0; // RETLW + 12'b1001_XXXX_XXXX: decodes <= 15'b10_10_0010_0_0_0_0_0_0_0; // CALL + 12'b101X_XXXX_XXXX: decodes <= 15'b10_10_0010_0_0_0_0_0_0_0; // GOTO + 12'b1100_XXXX_XXXX: decodes <= 15'b10_10_0010_1_0_0_0_0_0_0; // MOVLW + 12'b1101_XXXX_XXXX: decodes <= 15'b00_10_0010_1_0_1_0_0_0_0; // IORLW + 12'b1110_XXXX_XXXX: decodes <= 15'b00_10_0001_1_0_1_0_0_0_0; // ANDLW + 12'b1111_XXXX_XXXX: decodes <= 15'b00_10_0011_1_0_1_0_0_0_0; // XORLW + + default: + decodes <= 15'b00_00_0000_0_0_0_0_0_0_0; + endcase +end + +endmodule + + +// +// SYNTHETIC PIC 2.0 4/23/98 +// +// This is a synthesizable Microchip 16C57 compatible +// microcontroller. This core is not intended as a high fidelity model of +// the PIC, but simply a way to offer a simple processor core to people +// familiar with the PIC who also have PIC tools. +// +// pictest.v - top-level testbench (NOT SYNTHESIZABLE) +// piccpu.v - top-level synthesizable module +// picregs.v - register file instantiated under piccpu +// picalu.v - ALU instantiated under piccpu +// picidec.v - Instruction Decoder instantiated under piccpu +// hex2rom.c - C program used to translate MPLAB's INTEL HEX output +// into the Verilog $readmemh compatible file +// test*.asm - (note the wildcard..) Several test programs used +// to help debug the verilog. I used MPLAB and the simulator +// to develop these programs and get the expected results. +// Then, I ran them on Verilog-XL where they appeared to +// match. +// +// Copyright, Tom Coonan, '97. +// Use freely, but not for resale as is. You may use this in your +// own projects as desired. Just don't try to sell it as is! +// +// + +//`define DEBUG_SHOWREADS +//`define DEBUG_SHOWWRITES + +// Memory Map: +// +// PIC Data Memory addressing is complicated. See the Data Book for full explanation.. +// +// Basically, each BANK contains 32 locations. The lowest 16 locations in ALL Banks +// are really all mapped to the same bank (bank #0). The first 8 locations are the Special +// registers like the STATUS and PC registers. The upper 16 words in each bank, really are +// unique to each bank. The smallest PIC (16C54) only has the one bank #0. +// +// So, as a programmer, what you get is this. No matter what bank you are in (FSR[6:5]) +// you always have access to your special registers and also to registers 8-15. You can +// change to a 1 of 4 banks by setting FSR[6:5] and get 4 different sets of registers +// 16-31. +// +// For numbering purposes, I've numbered the registers as if they are one linear memory +// space, just like in the Data Book (see Figure 4-15 "Direct/Indirect Addressing"). +// So, the unique 16 registers in bank #1 are named r48 - r63 (I use decimal). The +// unique registers in bank #3 are therefore r112 - r127. There is no r111 because, +// remember, the lower 16 registers each each bank are all reall the same registers 0-15. +// +// Confused?! The Data Book explains it better than I can. +// +// bank location +// XX 00rrr - The special registers are not implemented in this register file. +// XX 01rrr - The 8 common words, just above the Special Regs, same for all Banks +// 00 1rrrr - The 16 words unique to Bank #0 +// 01 1rrrr - The 16 words unique to Bank #1 +// 10 1rrrr - The 16 words unique to Bank #2 +// 11 1rrrr - The 16 words unique to Bank #3 +// +// So, +// Special Regs are location[4:3] == 00 +// Common Regs are location[4:3] == 01 +// Words in banks location[4] == 1 +// +// +// I had problems trying to use simple register file declarations that +// would always, always work right, were synthesizable and allowed +// me to easily remove locations from the memory space. SOOOooo... I +// did the brute force thing and enumerated all the locations.. +// +// Much larger spaces will probably need a RAM and whatever I do would need +// custom hacking anyway.. I don't see an obvious solution to all this, but +// welcome suggestions.. +// +module picregs (clk, reset, we, re, bank, location, din, dout); + +input clk; +input reset; +input we; +input re; +input [1:0] bank; // Bank 0,1,2,3 +input [4:0] location; // Location +input [7:0] din; // Input +output [7:0] dout; // Output + +//parameter MAX_ADDRESS = 127; + +reg [7:0] dout; + +integer index; + +// Declare the major busses in and out of each block. +// +reg [7:0] commonblockout; // Data Memory common across all banks +reg [7:0] highblock0out; // Upper 16 bytes in BANK #0 +reg [7:0] highblock1out; // Upper 16 bytes in BANK #1 +reg [7:0] highblock2out; // Upper 16 bytes in BANK #2 +reg [7:0] highblock3out; // Upper 16 bytes in BANK #3 + +reg [7:0] commonblockin; // Data Memory common across all banks +reg [7:0] highblock0in; // Upper 16 bytes in BANK #0 +reg [7:0] highblock1in; // Upper 16 bytes in BANK #1 +reg [7:0] highblock2in; // Upper 16 bytes in BANK #2 +reg [7:0] highblock3in; // Upper 16 bytes in BANK #3 + +reg commonblocksel; // Select +reg highblock0sel; // Select +reg highblock1sel; // Select +reg highblock2sel; // Select +reg highblock3sel; // Select +// synopsys translate_off +integer cycle_counter; +initial cycle_counter = 0; +always @(negedge clk) begin + if (re) begin +`ifdef DEBUG_SHOWREADS + $display ("[%0d] Read: data = %0h(hex), from bank #%0d(dec) location %0h", cycle_counter, dout, bank, location); +`endif + end + if (we) begin +`ifdef DEBUG_SHOWWRITES + $display ("[%0d] Write: data = %0h(hex), to bank #%0d(dec) location %0h", cycle_counter, din, bank, location); +`endif + end + if (~reset) cycle_counter = cycle_counter + 1; +end +// synopsys translate_on + +// READ the Register File +// +always @(bank or location or re + or commonblockout + or highblock0out + or highblock1out + or highblock2out + or highblock3out) begin + if (re) begin + if (location[4:3] == 2'b01) begin + // This is the lower 8 words, common to all banks, just above special registers + dout <= commonblockout; // Access to first 8 locations past Special Registers + end + else begin + if (location[4]) begin + // Address is in the upper 16 words on one of the 4 banks + case (bank) // synopsys full_case parallel_case + 2'b00: dout <= highblock0out; // Upper 16 words of Bank #0 + 2'b01: dout <= highblock1out; // Upper 16 words of Bank #1 + 2'b10: dout <= highblock2out; // Upper 16 words of Bank #2 + 2'b11: dout <= highblock3out; // Upper 16 words of Bank #3 + endcase + end + else begin + dout <= 8'hff; + end + end + end + else begin + dout <= 8'hff; + end +end + +// Initial Write logic. +// +// Generate the specific write enables based on the PIC's bank/location rules. +// The individual memory blocks will do the actual synchronous write. +// +always @(we or bank or location or reset) begin + if (reset) begin + commonblocksel <= 1'b0; + highblock0sel <= 1'b0; + highblock1sel <= 1'b0; + highblock2sel <= 1'b0; + highblock3sel <= 1'b0; + end + else begin + if (we) begin + if (location[4:3] == 2'b01) begin + // This is the lower 8 words, common to all banks, just above special registers + commonblocksel <= 1'b1; + highblock0sel <= 1'b0; + highblock1sel <= 1'b0; + highblock2sel <= 1'b0; + highblock3sel <= 1'b0; + end + else begin + if (location[4]) begin + // Address is in the upper 16 words on one of the 4 banks + commonblocksel <= 1'b0; + case (bank) // synopsys full_case parallel_case + 2'b00: {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b1000; // Upper 16 words of Bank #0 + 2'b01: {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b0100; // Upper 16 words of Bank #1 + 2'b10: {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b0010; // Upper 16 words of Bank #2 + 2'b11: {highblock0sel, highblock1sel, highblock2sel, highblock3sel} <= 4'b0001; // Upper 16 words of Bank #3 + endcase + end + else begin + commonblocksel <= 1'b0; + highblock0sel <= 1'b0; + highblock1sel <= 1'b0; + highblock2sel <= 1'b0; + highblock3sel <= 1'b0; + end + end + end + else begin + commonblocksel <= 1'b0; + highblock0sel <= 1'b0; + highblock1sel <= 1'b0; + highblock2sel <= 1'b0; + highblock3sel <= 1'b0; + end + end +end + +// *** Buses feeding the memory blocks are driven directly from din. + +always @(din) + commonblockin <= din; + +always @(din) + highblock0in <= din; + +always @(din) + highblock1in <= din; + +always @(din) + highblock2in <= din; + +always @(din) + highblock3in <= din; + +// ****************** Common Block ************* + +reg [7:0] r8, r9, r10, r11, r12, r13, r14, r15; + +// Read from common block +always @(location or + r8 or r9 or r10 or r11 or r12 or r13 or r14 or r15) begin + case (location[2:0]) + 3'h0: commonblockout <= r8; + 3'h1: commonblockout <= r9; + 3'h2: commonblockout <= r10; + 3'h3: commonblockout <= r11; + 3'h4: commonblockout <= r12; + 3'h5: commonblockout <= r13; + 3'h6: commonblockout <= r14; + 3'h7: commonblockout <= r15; + endcase +end + +// Write to common block +always @(posedge clk) begin + if (we & commonblocksel) begin + case (location[2:0]) + 3'h0: r8 <= commonblockin; + 3'h1: r9 <= commonblockin; + 3'h2: r10 <= commonblockin; + 3'h3: r11 <= commonblockin; + 3'h4: r12 <= commonblockin; + 3'h5: r13 <= commonblockin; + 3'h6: r14 <= commonblockin; + 3'h7: r15 <= commonblockin; + endcase + end +end + +// **************** Highblock0 **************** + +reg [7:0] r16, r17, r18, r19, r20, r21, r22, r23; +reg [7:0] r24, r25, r26, r27, r28, r29, r30, r31; + +// Read from high block bank0 +always @(location or + r16 or r17 or r18 or r19 or r20 or r21 or r22 or r23 or + r24 or r25 or r26 or r27 or r28 or r29 or r30 or r31 +) begin + case (location[3:0]) + 4'h0: highblock0out <= r16; + 4'h1: highblock0out <= r17; + 4'h2: highblock0out <= r18; + 4'h3: highblock0out <= r19; + 4'h4: highblock0out <= r20; + 4'h5: highblock0out <= r21; + 4'h6: highblock0out <= r22; + 4'h7: highblock0out <= r23; + 4'h8: highblock0out <= r24; + 4'h9: highblock0out <= r25; + 4'hA: highblock0out <= r26; + 4'hB: highblock0out <= r27; + 4'hC: highblock0out <= r28; + 4'hD: highblock0out <= r29; + 4'hE: highblock0out <= r30; + 4'hF: highblock0out <= r31; + endcase +end + +// Write to high block bank 0 +always @(posedge clk) begin + if (we & highblock0sel) begin + case (location[3:0]) + 4'h0: r16 <= highblock0in; + 4'h1: r17 <= highblock0in; + 4'h2: r18 <= highblock0in; + 4'h3: r19 <= highblock0in; + 4'h4: r20 <= highblock0in; + 4'h5: r21 <= highblock0in; + 4'h6: r22 <= highblock0in; + 4'h7: r23 <= highblock0in; + 4'h8: r24 <= highblock0in; + 4'h9: r25 <= highblock0in; + 4'hA: r26 <= highblock0in; + 4'hB: r27 <= highblock0in; + 4'hC: r28 <= highblock0in; + 4'hD: r29 <= highblock0in; + 4'hE: r30 <= highblock0in; + 4'hF: r31 <= highblock0in; + endcase + end +end + +// **************** Highblock1 **************** + +reg [7:0] r48, r49, r50, r51, r52, r53, r54, r55; +reg [7:0] r56, r57, r58, r59, r60, r61, r62, r63; + +// Read +always @(location or + r48 or r49 or r50 or r51 or r52 or r53 or r54 or r55 or + r56 or r57 or r58 or r59 or r60 or r61 or r62 or r63 +) begin + case (location[3:0]) + 4'h0: highblock1out <= r48; + 4'h1: highblock1out <= r49; + 4'h2: highblock1out <= r50; + 4'h3: highblock1out <= r51; + 4'h4: highblock1out <= r52; + 4'h5: highblock1out <= r53; + 4'h6: highblock1out <= r54; + 4'h7: highblock1out <= r55; + 4'h8: highblock1out <= r56; + 4'h9: highblock1out <= r57; + 4'hA: highblock1out <= r58; + 4'hB: highblock1out <= r59; + 4'hC: highblock1out <= r60; + 4'hD: highblock1out <= r61; + 4'hE: highblock1out <= r62; + 4'hF: highblock1out <= r63; + endcase +end + +// Write +always @(posedge clk) begin + if (we & highblock1sel) begin + case (location[3:0]) + 4'h0: r48 <= highblock1in; + 4'h1: r49 <= highblock1in; + 4'h2: r50 <= highblock1in; + 4'h3: r51 <= highblock1in; + 4'h4: r52 <= highblock1in; + 4'h5: r53 <= highblock1in; + 4'h6: r54 <= highblock1in; + 4'h7: r55 <= highblock1in; + 4'h8: r56 <= highblock1in; + 4'h9: r57 <= highblock1in; + 4'hA: r58 <= highblock1in; + 4'hB: r59 <= highblock1in; + 4'hC: r60 <= highblock1in; + 4'hD: r61 <= highblock1in; + 4'hE: r62 <= highblock1in; + 4'hF: r63 <= highblock1in; + endcase + end +end + + +// **************** Highblock2 **************** + +reg [7:0] r80, r81, r82, r83, r84, r85, r86, r87; +reg [7:0] r88, r89, r90, r91, r92, r93, r94, r95; + +// Read +always @(location or + r80 or r81 or r82 or r83 or r84 or r85 or r86 or r87 or + r88 or r89 or r90 or r91 or r92 or r93 or r94 or r95 +) begin + case (location[3:0]) + 4'h0: highblock2out <= r80; + 4'h1: highblock2out <= r81; + 4'h2: highblock2out <= r82; + 4'h3: highblock2out <= r83; + 4'h4: highblock2out <= r84; + 4'h5: highblock2out <= r85; + 4'h6: highblock2out <= r86; + 4'h7: highblock2out <= r87; + 4'h8: highblock2out <= r88; + 4'h9: highblock2out <= r89; + 4'hA: highblock2out <= r90; + 4'hB: highblock2out <= r91; + 4'hC: highblock2out <= r92; + 4'hD: highblock2out <= r93; + 4'hE: highblock2out <= r94; + 4'hF: highblock2out <= r95; + endcase +end + +// Write +always @(posedge clk) begin + if (we & highblock2sel) begin + case (location[3:0]) + 4'h0: r80 <= highblock2in; + 4'h1: r81 <= highblock2in; + 4'h2: r82 <= highblock2in; + 4'h3: r83 <= highblock2in; + 4'h4: r84 <= highblock2in; + 4'h5: r85 <= highblock2in; + 4'h6: r86 <= highblock2in; + 4'h7: r87 <= highblock2in; + 4'h8: r88 <= highblock2in; + 4'h9: r89 <= highblock2in; + 4'hA: r90 <= highblock2in; + 4'hB: r91 <= highblock2in; + 4'hC: r92 <= highblock2in; + 4'hD: r93 <= highblock2in; + 4'hE: r94 <= highblock2in; + 4'hF: r95 <= highblock2in; + endcase + end +end + +// **************** Highblock3 **************** + +// *** The Following Registers are removed because of CUSTOM Hardware (see piccpu.v) ** +// +// r129 (or 7E) +// +// ********** +reg [7:0] r112, r113, r114, r115, r116, r117, r118, r119; +reg [7:0] r120, r121, r122, r123, r124, r125, r126 /*, r127*/ ; + +// Read +always @(location or + r112 or r113 or r114 or r115 or r116 or r117 or r118 or r119 or + r120 or r121 or r122 or r123 or r124 or r125 or r126 /* or r127 */ +) begin + case (location[3:0]) + 4'h0: highblock3out <= r112; + 4'h1: highblock3out <= r113; + 4'h2: highblock3out <= r114; + 4'h3: highblock3out <= r115; + 4'h4: highblock3out <= r116; + 4'h5: highblock3out <= r117; + 4'h6: highblock3out <= r118; + 4'h7: highblock3out <= r119; + 4'h8: highblock3out <= r120; + 4'h9: highblock3out <= r121; + 4'hA: highblock3out <= r122; + 4'hB: highblock3out <= r123; + 4'hC: highblock3out <= r124; + 4'hD: highblock3out <= r125; + 4'hE: highblock3out <= r126; + 4'hF: highblock3out <= 8'hff /* r127*/ ; + endcase +end + +// Write +always @(posedge clk) begin + if (we & highblock3sel) begin + case (location[3:0]) + 4'h0: r112 <= highblock3in; + 4'h1: r113 <= highblock3in; + 4'h2: r114 <= highblock3in; + 4'h3: r115 <= highblock3in; + 4'h4: r116 <= highblock3in; + 4'h5: r117 <= highblock3in; + 4'h6: r118 <= highblock3in; + 4'h7: r119 <= highblock3in; + 4'h8: r120 <= highblock3in; + 4'h9: r121 <= highblock3in; + 4'hA: r122 <= highblock3in; + 4'hB: r123 <= highblock3in; + 4'hC: r124 <= highblock3in; + 4'hD: r125 <= highblock3in; + 4'hE: r126 <= highblock3in; + 4'hF: /* r127 <= highblock3in */; + endcase + end +end + +// synopsys translate_off +`define CLEAR_MEMORY +`ifdef CLEAR_MEMORY +initial +begin + $display ("Clearing SRAM."); + clear_memory; +end +task clear_memory; +begin + // Common registers + r8 = 0; + r9 = 0; + r10 = 0; + r11 = 0; + r12 = 0; + r13 = 0; + r14 = 0; + r15 = 0; + + // Bank #0 + r16 = 0; + r17 = 0; + r18 = 0; + r19 = 0; + r20 = 0; + r21 = 0; + r22 = 0; + r23 = 0; + r24 = 0; + r25 = 0; + r26 = 0; + r27 = 0; + r28 = 0; + r29 = 0; + r30 = 0; + r31 = 0; + + // Bank #1 + r48 = 0; + r49 = 0; + r50 = 0; + r51 = 0; + r52 = 0; + r53 = 0; + r54 = 0; + r55 = 0; + r56 = 0; + r57 = 0; + r58 = 0; + r59 = 0; + r60 = 0; + r61 = 0; + r62 = 0; + r63 = 0; + + // Bank #2 + r80 = 0; + r94 = 0; + + // Bank #3 + r112 = 0; + r126 = 0; + +end +endtask +`endif +// synopsys translate_on +endmodule +// +// SYNTHETIC PIC 2.0 4/23/98 +// +// This is a synthesizable Microchip 16C57 compatible +// microcontroller. This core is not intended as a high fidelity model of +// the PIC, but simply a way to offer a simple processor core to people +// familiar with the PIC who also have PIC tools. +// +// pictest.v - top-level testbench (NOT SYNTHESIZABLE) +// piccpu.v - top-level synthesizable module +// picregs.v - register file instantiated under piccpu +// picalu.v - ALU instantiated under piccpu +// picidec.v - Instruction Decoder instantiated under piccpu +// hex2rom.c - C program used to translate MPLAB's INTEL HEX output +// into the Verilog $readmemh compatible file +// test*.asm - (note the wildcard..) Several test programs used +// to help debug the verilog. I used MPLAB and the simulator +// to develop these programs and get the expected results. +// Then, I ran them on Verilog-XL where they appeared to +// match. +// +// Copyright, Tom Coonan, '97. +// Use freely, but not for resale as is. You may use this in your +// own projects as desired. Just don't try to sell it as is! +// +// + +module pictest; + +// Select which test to run HERE.. +parameter TEST_NUMBER = 9; + +// *** Testing variables +// Debug flags. +integer dbg_showporta; // Are set in an 'initial' for default values, +integer dbg_showportb; // override in specific tests... +integer dbg_showportc; // Setting to 1 will cause variable to be displayed. +integer dbg_showinst; +integer dbg_showrom; +integer dbg_showw; +integer dbg_showpc; + +// cycles counter variables +integer dbg_showcycles; // Set to 1 to see cycles +integer dbg_limitcycles;// Set to one to enable maxcycles check +integer dbg_maxcycles; // Limit simulation to some number of cycles. +integer cycles; // Cycles counter. + + + +// *** Interface to the PICCPU +reg clk; +reg reset; +reg [7:0] porta; +wire [7:0] portb; +wire [7:0] portc; + +reg [11:0] rom[0:511]; +wire [8:0] romaddr; +reg [11:0] romdata; + +// ROM Interface +always @(romaddr) begin + romdata = rom[romaddr]; +end + +reg [7:0] last_debugw; +reg [8:0] last_debugpc; +reg [11:0] last_debuginst; +reg [7:0] last_debugstatus; +wire [7:0] debugw; +wire [8:0] debugpc; +wire [11:0] debuginst; +wire [7:0] debugstatus; + +// Instantiate one PICCPU to be tested. +piccpu piccpu_inst ( + .clk (clk), + .reset (reset), + .paddr (romaddr), + .pdata (romdata), + .portain (porta), + .portbout (portb), + .portcout (portc), + .debugw (debugw), + .debugpc (debugpc), + .debuginst (debuginst), + .debugstatus (debugstatus) +); + + +// Reset +initial begin +// $dumpfile("pic.vcd"); +// $dumpvars(0,pictest); + reset = 1; + #200; + reset = 0; +end + + +// Drive the clock input +initial begin + clk = 0; + forever begin + #50 clk = 1; + #50 clk = 0; + end +end + +// Debug defaults. Override in individual test tasks. +// +initial begin + dbg_showporta = 0; + dbg_showportb = 0; + dbg_showportc = 0; + dbg_showinst = 0; + dbg_showrom = 0; + dbg_showw = 0; + dbg_showpc = 0; + dbg_showcycles = 0; + + dbg_limitcycles = 1; + dbg_maxcycles = 50000; +end + +// Call the appropriate test task based on the TEST_NUMBER parameter set at top. +// +initial begin + case (TEST_NUMBER) + 1: test1; + 2: test2; + 3: test3; + 4: test4; + 5: test5; + 6: test6; + 7: test7; + 8: test8; + 9: test9; + default: + begin + $display ("ERROR: Unknown Test Number: %0d", TEST_NUMBER); + $finish; + end + endcase +end + +task test1; +begin + $display ("SYNTHETIC PIC 2.0. This is TEST #1"); + #1; + + // Only Watch Port B + dbg_showportb = 1; + dbg_showcycles = 1; + + $readmemh ("TEST1.ROM",rom); + dbg_limitcycles = 1; + dbg_maxcycles = 500; +end +endtask + +task test2; +begin + $display ("SYNTHETIC PIC 2.0. This is TEST #2"); + #1; + + // Only Watch Port B + dbg_showportb = 1; + + $readmemh ("TEST2.ROM", rom); + dbg_limitcycles = 1; + dbg_maxcycles = 500; +end +endtask + +task test3; +begin + $display ("SYNTHETIC PIC 2.0. This is TEST #3"); + #1; + + // Only Watch Port B + dbg_showportb = 1; + + $readmemh ("TEST3.ROM", rom); + dbg_limitcycles = 1; + dbg_maxcycles = 500; +end +endtask + +task test4; +begin + $display ("SYNTHETIC PIC 2.0. This is TEST #4"); + #1; + + // Only Watch Port B + dbg_showportb = 1; + + $readmemh ("TEST4.ROM", rom); + dbg_limitcycles = 1; + dbg_maxcycles = 500; +end +endtask + +task test5; +begin + $display ("SYNTHETIC PIC 2.0. This is TEST #5"); + #1; + + // Only Watch Port B + dbg_showportb = 1; + + $readmemh ("TEST5.ROM", rom); + dbg_limitcycles = 1; + dbg_maxcycles = 500; +end +endtask + +task test6; +begin + $display ("SYNTHETIC PIC 2.0. This is TEST #6"); + #1; + + // Watch Port B and C + dbg_showportb = 1; + dbg_showportc = 1; + dbg_limitcycles = 0; + + $readmemh ("TEST6.ROM", rom); + #200; + + repeat (20) begin + porta = $random; + #10000; + end + + $finish; +end +endtask + +task test7; +begin + $display ("SYNTHETIC PIC 2.0. This is TEST #7"); + #1; + + // Only Watch Port B + dbg_showportb = 1; + + $readmemh ("TEST7.ROM", rom); + dbg_limitcycles = 1; + dbg_maxcycles = 500; +end +endtask + +task test8; +begin + $display ("SYNTHETIC PIC 2.0. This is TEST #8"); + #1; + + // Watch All ports + dbg_showporta = 1; + dbg_showportb = 1; + dbg_showportc = 1; + + $readmemh ("TEST8.ROM", rom); + dbg_limitcycles = 1; + dbg_maxcycles = 500; +end +endtask + +task test9; +begin + $display ("SYNTHETIC PIC 2.0. This is TEST #9"); + #1; + + // Watch All ports + dbg_showportb = 1; + dbg_showportc = 1; + + $readmemh ("contrib/TEST9.ROM", rom); + dbg_limitcycles = 1; + dbg_maxcycles = 2000; +end +endtask + +// ******** END Of TEST TASKS + +// Cycles counter +// +initial begin + cycles = 0; + #1; + // Don't start counting until after reset. + @(negedge reset); + + forever begin + @(posedge clk); + cycles = cycles + 1; + if ((cycles % 256) == 0) begin + if (dbg_showcycles) begin + $display ("#Cycles = %0d", cycles); + end + end + + if (dbg_limitcycles) begin + if (cycles > dbg_maxcycles) begin + $display ("Maximum cycles (%0d) Exceeded. Halting simulation.", dbg_maxcycles); + $finish(0); + end + end + end +end + +always @(romaddr) begin + if (dbg_showrom) + $display ("ROM Address = %h, Data = %h", romaddr, romdata); +end + +always @(porta) begin + if (dbg_showporta) + $display ("%d: porta changes to: %h", $time, porta); +end + +always @(portb) begin + if (dbg_showportb) + $display ("%d: portb changes to: %h", $time, portb); +end + +always @(portc) begin + if (dbg_showportc) + $display ("%d: portc changes to: %h", $time, portc); +end + +initial begin + if (dbg_showw) begin + forever begin + @(negedge clk); + if (debugw != last_debugw) begin + $display ("W = %0h", debugw); + end + last_debugw = debugw; + end + end +end + +initial begin + if (dbg_showpc) begin + forever begin + @(negedge clk); + $display ("PC = %0h", debugpc); + end + end +end + + + +reg [11:0] last_pc; + +always @(posedge clk) begin + last_pc = debugpc; +end + +initial begin + if (dbg_showinst) begin + forever begin + @(negedge clk); + + if (debuginst[11:0] == 12'b0000_0000_0000) begin + $display ("%h NOP", last_pc); + end + else if (debuginst[11:5] == 7'b0000_001) begin + $display ("%h MOVWF f=0x%0h", last_pc, debuginst[4:0]); + end + else if (debuginst == 12'b0000_0100_0000) begin + $display ("%h CLRW", last_pc); + end + else if (debuginst[11:5] == 7'b0000_011) begin + $display ("%h CLRF f=0x%0h", last_pc, debuginst[4:0]); + end + else if (debuginst[11:6] == 7'b0000_10) begin + if (piccpu_inst.d == 0) $display ("%h SUBWF f=0x%0h, W", last_pc, debuginst[4:0]); + else $display ("%h SUBWF f=0x%0h, f", last_pc, debuginst[4:0]); + end + + else if (debuginst[11:6] == 7'b0000_11) begin + if (piccpu_inst.d == 0) $display ("%h DECF f=0x%0h, W", last_pc, debuginst[4:0]); + else $display ("%h DECF f=0x%0h, f", last_pc, debuginst[4:0]); + end + else if (debuginst[11:6] == 7'b0001_00) begin + if (piccpu_inst.d == 0) $display ("%h IORWF f=0x%0h, W", last_pc, debuginst[4:0]); + else $display ("%h IORWF f=0x%0h, f", last_pc, debuginst[4:0]); + end + else if (debuginst[11:6] == 7'b0001_01) begin + if (piccpu_inst.d == 0) $display ("%h ANDWF f=0x%0h, W", last_pc, debuginst[4:0]); + else $display ("%h ANDWF f=0x%0h, f", last_pc, debuginst[4:0]); + end + else if (debuginst[11:6] == 7'b0001_10) begin + if (piccpu_inst.d == 0) $display ("XORWF f=0x%0h, W", last_pc, debuginst[4:0]); + else $display ("%h XORWF f=0x%0h, f", last_pc, debuginst[4:0]); + end + else if (debuginst[11:6] == 7'b0001_11) begin + if (piccpu_inst.d == 0) $display ("%h ADDWF f=0x%0h, W", last_pc, debuginst[4:0]); + else $display ("%h ADDWF f=0x%0h, f", last_pc, debuginst[4:0]); + end + else if (debuginst[11:6] == 7'b0010_00) begin + if (piccpu_inst.d == 0) $display ("%h MOVF f=0x%0h, W", last_pc, debuginst[4:0]); + else $display ("%h MOVF f=0x%0h, f", last_pc, debuginst[4:0]); + end + else if (debuginst[11:6] == 7'b0010_01) begin + if (piccpu_inst.d == 0) $display ("%h COMF f=0x%0h, W", last_pc, debuginst[4:0]); + else $display ("%h COMF f=0x%0h, f", last_pc, debuginst[4:0]); + end + else if (debuginst[11:6] == 7'b0010_10) begin + if (piccpu_inst.d == 0) $display ("%h INCF f=0x%0h, W", last_pc, debuginst[4:0]); + else $display ("%h INCF f=0x%0h, f", last_pc, debuginst[4:0]); + end + else if (debuginst[11:6] == 7'b0010_11) begin + if (piccpu_inst.d == 0) $display ("%h DECFSZ f=0x%0h, W", last_pc, debuginst[4:0]); + else $display ("%h DECFSZ f=0x%0h, f", last_pc, debuginst[4:0]); + end + else if (debuginst[11:6] == 7'b0011_00) begin + if (piccpu_inst.d == 0) $display ("%h RRF f=0x%0h, W", last_pc, debuginst[4:0]); + else $display ("%h RRF f=0x%0h, f", last_pc, debuginst[4:0]); + end + else if (debuginst[11:6] == 7'b0011_01) begin + if (piccpu_inst.d == 0) $display ("%h RLF f=0x%0h, W", last_pc, debuginst[4:0]); + else $display ("%h RLF f=0x%0h, f", last_pc, debuginst[4:0]); + end + else if (debuginst[11:6] == 7'b0011_10) begin + if (piccpu_inst.d == 0) $display ("%h SWAPF f=0x%0h, W", last_pc, debuginst[4:0]); + else $display ("%h SWAPF f=0x%0h, f", last_pc, debuginst[4:0]); + end + else if (debuginst[11:6] == 7'b0011_11) begin + if (piccpu_inst.d == 0) $display ("%h INCFSZ f=0x%0h, W", last_pc, debuginst[4:0]); + else $display ("%h INCFSZ f=0x%0h, f", last_pc, debuginst[4:0]); + end + + // Bit-Oriented File Register Operations + else if (debuginst[11:8] == 4'b0100) begin + $display ("%h BCF f=0x%0h, bit=%0d", last_pc, debuginst[4:0], piccpu_inst.b); + end + else if (debuginst[11:8] == 4'b0101) begin + $display ("%h BCF f=0x%0h, bit=%0d", last_pc, debuginst[4:0], piccpu_inst.b); + end + else if (debuginst[11:8] == 4'b0110) begin + if (piccpu_inst.skip) $display ("%h BTFSC f=0x%0h, bit=%0d {Will Skip..}", last_pc, debuginst[4:0], piccpu_inst.b); + else $display ("%h BTFSC f=0x%0h, bit=%0d {Will NOT Skip..}", last_pc, debuginst[4:0], piccpu_inst.b); + end + else if (debuginst[11:8] == 4'b0111) begin + if (piccpu_inst.skip) $display ("%h BTFSS f=0x%0h, bit=%0d {Will Skip..}", last_pc, debuginst[4:0], piccpu_inst.b); + else $display ("%h BTFSS f=0x%0h, bit=%0d {Will NOT Skip..}", last_pc, debuginst[4:0], piccpu_inst.b); + end + + // Literal and Control Operations + else if (debuginst[11:0] == 16'b0000_0000_0010) begin + $display ("%h OPTION", last_pc); + end + else if (debuginst[11:0] == 16'b0000_0000_0011) begin + $display ("%h SLEEP", last_pc); + end + else if (debuginst[11:0] == 16'b0000_0000_0100) begin + $display ("%h CLRWDT", last_pc); + end + else if (debuginst[11:3] == 13'b0000_0000_0) begin + $display ("%h TRIS, f=0x%0h", last_pc, debuginst[2:0]); + end + else if (debuginst[11:8] == 4'b1000) begin + $display ("%h RETLW, k=0x%0h", last_pc, debuginst[7:0]); + end + else if (debuginst[11:8] == 4'b1001) begin + $display ("%h CALL, k=0x%0h", last_pc, debuginst[7:0]); + end + else if (debuginst[11:9] == 3'b101) begin + $display ("%h GOTO, k=0x%0h", last_pc, debuginst[8:0]); + end + else if (debuginst[11:8] == 4'b1100) begin + $display ("%h MOVLW, k=0x%0h", last_pc, debuginst[7:0]); + end + else if (debuginst[11:8] == 4'b1101) begin + $display ("%h IORLW, k=0x%0h", last_pc, debuginst[7:0]); + end + else if (debuginst[11:8] == 4'b1110) begin + $display ("%h ANDLW, k=0x%0h", last_pc, debuginst[7:0]); + end + else if (debuginst[11:8] == 4'b1111) begin + $display ("%h XORLW, k=0x%0h", last_pc, debuginst[7:0]); + end + else begin + $display ("Hmmm! instruction not recognized?! %0h", debuginst); + end + end + end +end + + +endmodule diff --git a/ivtest/find_valg_all b/ivtest/find_valg_all new file mode 100755 index 000000000..ecb9cac60 --- /dev/null +++ b/ivtest/find_valg_all @@ -0,0 +1,37 @@ +#!/bin/sh +echo "VVP valgrind errors." +echo "-------------------------" +fgrep "ERROR SUMMARY" log/*.log | fgrep -v " 0 errors" || echo "No Errors." + +tail -n8 log/*.log | fgrep "definitely lost" | fgrep -v " 0 bytes" || \ + echo "No \"definitely lost\" memory in vvp." + +tail -n8 log/*.log | fgrep "indirectly lost" | fgrep -v " 0 bytes" || \ + echo "No \"indirectly lost\" memory in vvp." + +tail -n8 log/*.log | fgrep "possibly lost" | fgrep -v " 0 bytes" || \ + echo "No \"possibly lost\" memory in vvp." + +tail -n8 log/*.log | fgrep "still reachable" | fgrep -v " 0 bytes" || \ + echo "No \"still reachable\" memory in vvp." + +# egrep "^\*\*[0-9]+\*\*" log/*.log || echo "No \"missed deletes\" in vvp." + +echo "" +echo "VPI valgrind errors." +echo "-------------------------" +fgrep "ERROR SUMMARY" vpi_log/*.log | fgrep -v " 0 errors" || echo "No Errors." + +tail -n8 vpi_log/*.log | fgrep "definitely lost" | fgrep -v " 0 bytes" || \ + echo "No \"definitely lost\" memory in vvp." + +tail -n8 vpi_log/*.log | fgrep "indirectly lost" | fgrep -v " 0 bytes" || \ + echo "No \"indirectly lost\" memory in vvp." + +tail -n8 vpi_log/*.log | fgrep "possibly lost" | fgrep -v " 0 bytes" || \ + echo "No \"possibly lost\" memory in vvp." + +tail -n8 vpi_log/*.log | fgrep "still reachable" | fgrep -v " 0 bytes" || \ + echo "No \"still reachable\" memory in vvp." + +# egrep "^\*\*[0-9]+\*\*" vpi_log/*.log || echo "No \"missed deletes\" in vvp." diff --git a/ivtest/find_valg_errs b/ivtest/find_valg_errs new file mode 100755 index 000000000..9652876bf --- /dev/null +++ b/ivtest/find_valg_errs @@ -0,0 +1,31 @@ +#!/bin/sh +echo "VVP valgrind errors." +echo "-------------------------" +fgrep "ERROR SUMMARY" log/*.log | fgrep -v " 0 errors" || echo "No Errors." + +tail -n8 log/*.log | fgrep "definitely lost" | fgrep -v " 0 bytes" || \ + echo "No \"definitely lost\" memory in vvp." + +tail -n8 log/*.log | fgrep "indirectly lost" | fgrep -v " 0 bytes" || \ + echo "No \"indirectly lost\" memory in vvp." + +tail -n8 log/*.log | fgrep "possibly lost" | fgrep -v " 0 bytes" || \ + echo "No \"possibly lost\" memory in vvp." + +# egrep "^\*\*[0-9]+\*\*" log/*.log || echo "No \"missed deletes\" in vvp." + +echo "" +echo "VPI valgrind errors." +echo "-------------------------" +fgrep "ERROR SUMMARY" vpi_log/*.log | fgrep -v " 0 errors" || echo "No Errors." + +tail -n8 vpi_log/*.log | fgrep "definitely lost" | fgrep -v " 0 bytes" || \ + echo "No \"definitely lost\" memory in vvp." + +tail -n8 vpi_log/*.log | fgrep "indirectly lost" | fgrep -v " 0 bytes" || \ + echo "No \"indirectly lost\" memory in vvp." + +tail -n8 vpi_log/*.log | fgrep "possibly lost" | fgrep -v " 0 bytes" || \ + echo "No \"possibly lost\" memory in vvp." + +# egrep "^\*\*[0-9]+\*\*" vpi_log/*.log || echo "No \"missed deletes\" in vvp." diff --git a/ivtest/fpga_tests/.cvsignore b/ivtest/fpga_tests/.cvsignore new file mode 100644 index 000000000..311ba5bcd --- /dev/null +++ b/ivtest/fpga_tests/.cvsignore @@ -0,0 +1,2 @@ +fpga_log +fpga_tmp diff --git a/ivtest/fpga_tests/bufifab.v b/ivtest/fpga_tests/bufifab.v new file mode 100644 index 000000000..05e1be251 --- /dev/null +++ b/ivtest/fpga_tests/bufifab.v @@ -0,0 +1,6 @@ +module bufifab (output Out0, output Out1, input I, input E); + + bufif0 (Out0, I, E); + bufif1 (Out1, I, E); + +endmodule diff --git a/ivtest/fpga_tests/bufifab_tb.v b/ivtest/fpga_tests/bufifab_tb.v new file mode 100644 index 000000000..18160272b --- /dev/null +++ b/ivtest/fpga_tests/bufifab_tb.v @@ -0,0 +1,31 @@ +module main; + + reg [2:0] i; + wire out0, out1; + wire ref0, ref1; + + bufifab dut(.Out0(out0), .Out1(out1), .I(i[0]), .E(i[1])); + + bufif0 (ref0, i[0], i[1]); + bufif1 (ref1, i[0], i[1]); + initial begin + i = 0; + + for (i = 0 ; i[2] == 0 ; i = i+1) begin + #1 $display("I=%b, E=%b, Out0=%b, Out1=%b", i[0], i[1], out0, out1); + + if (out0 !== ref0) begin + $display("FAILED -- ref0=%b, out0=%b", ref0, out0); + $finish; + end + + if (out1 !== ref1) begin + $display("FAILED -- ref1=%b, out1=%b", ref1, out1); + $finish; + end + end // for (i = 0 ; i[2] == 0 ; i = i+1) + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/fpga_tests/cell_ld.v b/ivtest/fpga_tests/cell_ld.v new file mode 100644 index 000000000..1ac49857c --- /dev/null +++ b/ivtest/fpga_tests/cell_ld.v @@ -0,0 +1,15 @@ +`timescale 100 ps / 10 ps + +(* ivl_synthesis_cell *) +module LD (Q, D, G); + + output Q; + reg q_out; + + input D, G; + + buf b1 (Q, q_out); + + always @(D or G) if (G) q_out <= D; + +endmodule diff --git a/ivtest/fpga_tests/cell_ld_tb.v b/ivtest/fpga_tests/cell_ld_tb.v new file mode 100755 index 000000000..4e5b24271 --- /dev/null +++ b/ivtest/fpga_tests/cell_ld_tb.v @@ -0,0 +1,45 @@ +`timescale 100 ps / 10 ps + +module main; + + wire Q; + reg D, G; + + LD u1 (.Q(Q), .D(D), .G(G)); + + initial begin + D = 0; + G = 1; + #1 if (Q !== 0) begin + $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q); + $finish; + end + + D = 1; + #1 if (Q !== 1) begin + $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q); + $finish; + end + + G = 0; + #1 if (Q !== 1) begin + $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q); + $finish; + end + + D = 0; + #1 if (Q !== 1) begin + $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q); + $finish; + end + + G = 1; + #1 if (Q !== 0) begin + $display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/fpga_tests/eqne.v b/ivtest/fpga_tests/eqne.v new file mode 100644 index 000000000..0cc28b520 --- /dev/null +++ b/ivtest/fpga_tests/eqne.v @@ -0,0 +1,13 @@ +module eqne(output wire eq1, output wire ne1, + output wire eq2, output wire ne2, + output wire eq5, output wire ne5, + input wire [7:0] x, input wire [7:0] y); + + assign eq1 = x[0] == y[0]; + assign ne1 = x[0] != y[0]; + assign eq2 = x[1:0] == y[1:0]; + assign ne2 = x[1:0] != y[1:0]; + assign eq5 = x[4:0] == y[4:0]; + assign ne5 = x[4:0] != y[4:0]; + +endmodule // eqne diff --git a/ivtest/fpga_tests/eqne_tb.v b/ivtest/fpga_tests/eqne_tb.v new file mode 100644 index 000000000..03589b30d --- /dev/null +++ b/ivtest/fpga_tests/eqne_tb.v @@ -0,0 +1,52 @@ +module main; + + wire eq1, eq2, eq5; + wire ne1, ne2, ne5; + + reg [7:0] x, y; + + eqne dut(.eq1(eq1), .eq2(eq2), .eq5(eq5), + .ne1(ne1), .ne2(ne2), .ne5(ne5), + .x(x), .y(y)); + + initial begin + for (x = 0 ; x < 'h20 ; x = x+1) + for (y = 0 ; y < 'h20 ; y = y+1) begin + #1 $display("x=%h, y=%h: ", x, y, + "eq1=%b, eq2=%b, eq5=%b, ", eq1, eq2, eq5, + "ne1=%b, ne2=%b, ne5=%b", ne1, ne2, ne5); + if (eq1 !== (x[0] == y[0])) begin + $display("FAILED"); + $finish; + end + + if (eq2 !== (x[1:0] == y[1:0])) begin + $display("FAILED"); + $finish; + end + + if (eq5 !== (x[4:0] == y[4:0])) begin + $display("FAILED"); + $finish; + end + + if (ne1 !== (x[0] != y[0])) begin + $display("FAILED"); + $finish; + end + + if (ne2 !== (x[1:0] != y[1:0])) begin + $display("FAILED"); + $finish; + end + + if (ne5 !== (x[4:0] != y[4:0])) begin + $display("FAILED"); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/fpga_tests/fpga_reg.list b/ivtest/fpga_tests/fpga_reg.list new file mode 100644 index 000000000..30b96ef46 --- /dev/null +++ b/ivtest/fpga_tests/fpga_reg.list @@ -0,0 +1,20 @@ +# test testbench arch=? part=? gold_file +eqne eqne_tb virtex XC2S15-VQ100 - +eqne eqne_tb virtex2 XC2V40 - +ge2 ge2_tb virtex XC2S15-VQ100 ge2.gold +ge2 ge2_tb virtex2 XC2V40 ge2.gold +ge8 ge8_tb virtex XC2S15-VQ100 - +ge8 ge8_tb virtex2 XC2V40 - +onehot16 onehot16_tb virtex XC2S15-VQ100 - +onehot16 onehot16_tb virtex2 XC2V40 - +sub8 sub8_tb virtex XC2S15-VQ100 - +sub8 sub8_tb virtex2 XC2V40 - +sqrt sqrt_tb virtex XC2S15-VQ100 - +sqrt sqrt_tb virtex2 XC2V40-CS144 - +timer timer_tb virtex XC2S15 - +timer timer_tb virtex2 XC2V40 - +cell_ld cell_ld_tb virtex2 XC2V40 - +ornor4 ornor4_tb virtex XC2S15-VQ100 - +ornor7 ornor7_tb virtex XC2S15-VQ100 - +ornor8 ornor8_tb virtex XC2S15-VQ100 - +bufifab bufifab_tb virtex XC2S15-VQ100 - diff --git a/ivtest/fpga_tests/fpga_reg.sh b/ivtest/fpga_tests/fpga_reg.sh new file mode 100755 index 000000000..ad0905c5a --- /dev/null +++ b/ivtest/fpga_tests/fpga_reg.sh @@ -0,0 +1,141 @@ +#!/bin/sh + +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# Library General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU Library General Public License for more details. +# +# You should have received a copy of the GNU Library General Public +# License along with this program; if not, write to the Free +# Software Foundation, Inc., +# 59 Temple Place - Suite 330 +# Boston, MA 02111-1307, USA +# +#ident "$Id: fpga_reg.sh,v 1.5 2004/01/13 03:37:04 stevewilliams Exp $" + +# This script runs the synthesis tests listed in the fpga_reg.list +# list file. The script uses Icarus Verilog from the path, and also +# gets ngdbuild and ngd2ver from the path. The XILINX variable needs +# to point to the XILINX install directory so that the simprims +# can be found. The run test uses these to generate a simulation +# from the synthesized file. +# +# Usage: sh ./fpga_reg.sh [select] +# +# If there is no select, then run all the tests. If there is a select, +# then only run the tests that match the select regular expression. +# + +# This is a diff command for comparing log with gold files. +diff="diff --strip-trailing-cr -aq" + +# This is the output file. +status_file=fpga_reg.txt +true > $status_file + +if ! test -d fpga_log +then + mkdir fpga_log +fi + +if ! test -d fpga_tmp +then + mkdir fpga_tmp +fi + +if test "X$1" = "X"; then + match='.*' +else + match="$1" +fi + +cat fpga_reg.list | + sed -e 's/#.*//' | + while read test tb arch part gold junk + do + if test "X$test" = "X" -o 0 = `expr X$test : X$match` + then + : skip a comment + else + if test "X$part" != "X-" + then + part="-ppart=$part" + else + part= + fi + + true > fpga_log/$test-$arch.log 2>&1 + EDIF="$test-$arch.edf" + + synth="iverilog -ofpga_tmp/$EDIF -tfpga -parch=$arch $part $test.v" + echo "synth=$synth" + eval "$synth" > fpga_log/$test-$arch-synth.log 2>&1 + if test $? != 0 + then + echo "$test-$arch: FAILED -- Synthesis error" >> $status_file + continue + fi + + ngdbuild="ngdbuild $EDIF $test.ngd" + echo "ngdbuild=$ngdbuild" + (eval "cd fpga_tmp; $ngdbuild") > fpga_log/$test-$arch-build.log 2>&1 + if test $? != 0 + then + echo "$test-$arch: FAILED -- ngdbuild error" >> $status_file + continue + fi + + ngd2ver="ngd2ver -w $test.ngd $test.edf.v" + echo "ngd2ver=$ngd2ver" + (eval "cd fpga_tmp; $ngd2ver") > fpga_log/$test-$arch-ngd2ver.log 2>&1 + if test $? != 0 + then + echo "$test-$arch: FAILED -- ngd2ver error" >> $status_file + continue + fi + + iverilog -oa.out -Ttyp $tb.v fpga_tmp/$test.edf.v $XILINX/verilog/src/glbl.v -y $XILINX/verilog/src/simprims + if test $? != 0 + then + echo "$test-$arch: FAILED -- compiling test bench" >> $status_file + continue + fi + + vvp a.out > fpga_log/$test-$arch.log 2>&1 + if test "X$gold" != "X-" ; then + if $diff $gold fpga_log/$test-$arch.log > /dev/null + then + echo "$test-$arch: PASSED -- Correct output." >> $status_file + else + echo "$test-$arch: FAILED -- Incorrect output." >> $status_file + fi + else + if grep -a -q PASSED fpga_log/$test-$arch.log + then + echo "$test-$arch: PASSED" >> $status_file + else + echo "$test-$arch: FAILED" >> $status_file + fi + fi + rm a.out + fi + done + +PASSED=`grep ': PASSED' $status_file | wc -l` +FAILED=`grep ': FAILED' $status_file | wc -l` +echo "PASSED=$PASSED, FAILED=$FAILED" >> $status_file + +# $Log: fpga_reg.sh,v $ +# Revision 1.5 2004/01/13 03:37:04 stevewilliams +# Cope with dos line-ends while comparing gold files. +# +# Revision 1.4 2003/04/01 05:58:36 stevewilliams +# Add a select argument. +# diff --git a/ivtest/fpga_tests/ge2.gold b/ivtest/fpga_tests/ge2.gold new file mode 100644 index 000000000..3e830dc9b --- /dev/null +++ b/ivtest/fpga_tests/ge2.gold @@ -0,0 +1,16 @@ +00 >= 00: 1 +00 >= 01: 0 +00 >= 10: 0 +00 >= 11: 0 +01 >= 00: 1 +01 >= 01: 1 +01 >= 10: 0 +01 >= 11: 0 +10 >= 00: 1 +10 >= 01: 1 +10 >= 10: 1 +10 >= 11: 0 +11 >= 00: 1 +11 >= 01: 1 +11 >= 10: 1 +11 >= 11: 1 diff --git a/ivtest/fpga_tests/ge2.v b/ivtest/fpga_tests/ge2.v new file mode 100644 index 000000000..c2d8abc28 --- /dev/null +++ b/ivtest/fpga_tests/ge2.v @@ -0,0 +1,5 @@ +module ge2(output wire out, input wire [1:0] A, input wire [1:0] B); + + assign out = A >= B; + +endmodule // ge2 diff --git a/ivtest/fpga_tests/ge2_tb.v b/ivtest/fpga_tests/ge2_tb.v new file mode 100644 index 000000000..8f7ada6cb --- /dev/null +++ b/ivtest/fpga_tests/ge2_tb.v @@ -0,0 +1,62 @@ +module main; + + wire out; + reg [1:0] A, B; + + ge2 dut(.out(out), .A(A), .B(B)); + + initial begin + A = 0; + B = 0; + #1 $display("%b >= %b: %b", A, B, out); + + B = 1; + #1 $display("%b >= %b: %b", A, B, out); + + B = 2; + #1 $display("%b >= %b: %b", A, B, out); + + B = 3; + #1 $display("%b >= %b: %b", A, B, out); + + A = 1; + B = 0; + #1 $display("%b >= %b: %b", A, B, out); + + B = 1; + #1 $display("%b >= %b: %b", A, B, out); + + B = 2; + #1 $display("%b >= %b: %b", A, B, out); + + B = 3; + #1 $display("%b >= %b: %b", A, B, out); + + A = 2; + B = 0; + #1 $display("%b >= %b: %b", A, B, out); + + B = 1; + #1 $display("%b >= %b: %b", A, B, out); + + B = 2; + #1 $display("%b >= %b: %b", A, B, out); + + B = 3; + #1 $display("%b >= %b: %b", A, B, out); + + A = 3; + B = 0; + #1 $display("%b >= %b: %b", A, B, out); + + B = 1; + #1 $display("%b >= %b: %b", A, B, out); + + B = 2; + #1 $display("%b >= %b: %b", A, B, out); + + B = 3; + #1 $display("%b >= %b: %b", A, B, out); + + end // initial begin +endmodule // main diff --git a/ivtest/fpga_tests/ge8.v b/ivtest/fpga_tests/ge8.v new file mode 100644 index 000000000..2ae9596b1 --- /dev/null +++ b/ivtest/fpga_tests/ge8.v @@ -0,0 +1,5 @@ +module ge8(output wire out, input wire [7:0] A, input wire [7:0] B); + + assign out = A >= B; + +endmodule diff --git a/ivtest/fpga_tests/ge8_tb.v b/ivtest/fpga_tests/ge8_tb.v new file mode 100644 index 000000000..5f2683ddb --- /dev/null +++ b/ivtest/fpga_tests/ge8_tb.v @@ -0,0 +1,54 @@ +/* + * Exhaustive check of all the compare results. + */ +module main; + + wire out; + reg [7:0] A, B; + + ge8 dut(.out(out), .A(A), .B(B)); + + reg error = 0; + integer adx, bdx; + + initial begin + A = 0; + B = 0; + #1 $display("%b >= %b: %b", A, B, out); + + for (adx = 0 ; adx < 256 ; adx = adx + 1) begin + A = adx; + for (bdx = 0 ; bdx < 256 ; bdx = bdx + 1) begin + B = bdx; + #1 $write("%b >= %b: %b", A, B, out); + if (out === 1) begin + if (A < B) begin + $display(" ERROR"); + error = 1; + end else begin + $display(" OK"); + end + + end else if (out === 0) begin + if (A < B) begin + $display(" OK"); + end else begin + $display(" ERROR"); + error = 1; + end + + end else begin + $display(" ERROR"); + error = 1; + end // else: !if(out === 0) + + end // for (bdx = 0 ; bdx < 256 ; bdx += 1) + end // for (adx = 0 ; adx < 256 ; adx = adx + 1) + + if (error == 0) + $display("PASSED"); + else + $display("FAILED"); + + end // initial begin +endmodule // main diff --git a/ivtest/fpga_tests/onehot16.v b/ivtest/fpga_tests/onehot16.v new file mode 100644 index 000000000..39758bcbb --- /dev/null +++ b/ivtest/fpga_tests/onehot16.v @@ -0,0 +1,5 @@ +module onehot16(output wire [15:0] out, input wire [3:0] A); + + assign out = 1 << A; + +endmodule diff --git a/ivtest/fpga_tests/onehot16_tb.v b/ivtest/fpga_tests/onehot16_tb.v new file mode 100644 index 000000000..cab141c61 --- /dev/null +++ b/ivtest/fpga_tests/onehot16_tb.v @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + * $Id: onehot16_tb.v,v 1.1 2003/03/31 01:35:05 stevewilliams Exp $ + */ + +/* + * Exhaustive check of all the subtract results. + */ +module main; + + wire [15:0] out; + reg [3:0] A; + + onehot16 dut(.out(out), .A(A)); + + reg error = 0; + integer adx; + + initial begin + A = 0; + + for (adx = 0 ; adx < 16 ; adx = adx + 1) begin + A = adx; + #1 $write("onehot(%b): %b", A, out); + if (out !== (1 << adx)) begin + $display(" ERROR"); + error = 1; + end else begin + $display(" OK"); + end + + end // for (adx = 0 ; adx < 256 ; adx = adx + 1) + + if (error == 0) + $display("PASSED"); + else + $display("FAILED"); + + end // initial begin +endmodule // main diff --git a/ivtest/fpga_tests/ornor4.v b/ivtest/fpga_tests/ornor4.v new file mode 100644 index 000000000..c5f5ec968 --- /dev/null +++ b/ivtest/fpga_tests/ornor4.v @@ -0,0 +1,7 @@ +module ornor4(output wire O_OR, output wire O_NOR, + input wire I0, I1, I2, I3); + + assign O_OR = | {I0, I1, I2, I3}; + assign O_NOR = ~| {I0, I1, I2, I3}; + +endmodule // ornor4 diff --git a/ivtest/fpga_tests/ornor4_tb.v b/ivtest/fpga_tests/ornor4_tb.v new file mode 100644 index 000000000..325d6266d --- /dev/null +++ b/ivtest/fpga_tests/ornor4_tb.v @@ -0,0 +1,24 @@ +module main; + + reg [4:0] val; + + ornor4 dut (.O_OR(o_or), .O_NOR(o_nor), + .I0(val[0]), .I1(val[1]), .I2(val[2]), .I3(val[3])); + + initial begin + for (val = 0 ; val[4] == 0 ; val = val+1) begin + #1 if (o_or !== |val[3:0]) begin + $display("FAILED -- |%b --> %b", val[3:0], o_or); + $finish; + end + + if (o_nor !== ~|val[3:0]) begin + $display("FAILED -- ~|%b --> %b", val[3:0], o_nor); + $finish; + end + end // for (val = 0 ; val[4] == 0 ; val = val+1) + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/fpga_tests/ornor7.v b/ivtest/fpga_tests/ornor7.v new file mode 100644 index 000000000..ed7804af3 --- /dev/null +++ b/ivtest/fpga_tests/ornor7.v @@ -0,0 +1,7 @@ +module ornor7(output wire O_OR, output wire O_NOR, + input wire I0, I1, I2, I3, I4, I5, I6); + + assign O_OR = | {I0, I1, I2, I3, I4, I5, I6}; + assign O_NOR = ~| {I0, I1, I2, I3, I4, I5, I6}; + +endmodule diff --git a/ivtest/fpga_tests/ornor7_tb.v b/ivtest/fpga_tests/ornor7_tb.v new file mode 100755 index 000000000..2167042b0 --- /dev/null +++ b/ivtest/fpga_tests/ornor7_tb.v @@ -0,0 +1,25 @@ +module main; + + reg [7:0] val; + + ornor7 dut (.O_OR(o_or), .O_NOR(o_nor), + .I0(val[0]), .I1(val[1]), .I2(val[2]), .I3(val[3]), + .I4(val[4]), .I5(val[5]), .I6(val[6])); + + initial begin + for (val = 0 ; val[7] == 0 ; val = val+1) begin + #1 if (o_or !== |val[6:0]) begin + $display("FAILED -- |%b --> %b", val[6:0], o_or); + $finish; + end + + if (o_nor !== ~|val[6:0]) begin + $display("FAILED -- ~|%b --> %b", val[6:0], o_nor); + $finish; + end + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/fpga_tests/ornor8.v b/ivtest/fpga_tests/ornor8.v new file mode 100644 index 000000000..2cfd1e666 --- /dev/null +++ b/ivtest/fpga_tests/ornor8.v @@ -0,0 +1,7 @@ +module ornor8(output wire O_OR, output wire O_NOR, + input wire I0, I1, I2, I3, I4, I5, I6, I7); + + assign O_OR = | {I0, I1, I2, I3, I4, I5, I6, I7}; + assign O_NOR = ~| {I0, I1, I2, I3, I4, I5, I6, I7}; + +endmodule diff --git a/ivtest/fpga_tests/ornor8_tb.v b/ivtest/fpga_tests/ornor8_tb.v new file mode 100644 index 000000000..9e8abde75 --- /dev/null +++ b/ivtest/fpga_tests/ornor8_tb.v @@ -0,0 +1,25 @@ +module main; + + reg [8:0] val; + + ornor8 dut (.O_OR(o_or), .O_NOR(o_nor), + .I0(val[0]), .I1(val[1]), .I2(val[2]), .I3(val[3]), + .I4(val[4]), .I5(val[5]), .I6(val[6]), .I7(val[7])); + + initial begin + for (val = 0 ; val[8] == 0 ; val = val+1) begin + #1 if (o_or !== |val[7:0]) begin + $display("FAILED -- |%b --> %b", val[7:0], o_or); + $finish; + end + + if (o_nor !== ~|val[7:0]) begin + $display("FAILED -- ~|%b --> %b", val[7:0], o_nor); + $finish; + end + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/fpga_tests/sqrt.v b/ivtest/fpga_tests/sqrt.v new file mode 100644 index 000000000..3994a180d --- /dev/null +++ b/ivtest/fpga_tests/sqrt.v @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + * $Id: sqrt.v,v 1.1 2003/03/30 03:54:48 stevewilliams Exp $" + */ + + /* + * This module approximates the square root of an unsigned 32bit + * number. The algorithm works by doing a bit-wise binary search. + * Starting from the most significant bit, the accumulated value + * tries to put a 1 in the bit position. If that makes the square + * too big for the input, the bit is left zero, otherwise it is set + * in the result. This continues for each bit, decreasing in + * significance, until all the bits are calculated or all the + * remaining bits are zero. + * + * Since the result is an integer, this function really calculates + * value of the expression: + * + * x = floor(sqrt(y)) + * + * where sqrt(y) is the exact square root of y and floor(N) is the + * largest integer <= N. + * + * For 32bit numbers, this will never run more then 16 iterations, + * which amounts to 16 clocks. + */ + +module sqrt32(clk, rdy, reset, x, .y(acc)); + input clk; + output rdy; + input reset; + + input [31:0] x; + output [15:0] acc; + + + // acc holds the accumulated result, and acc2 is the accumulated + // square of the accumulated result. + reg [15:0] acc; + reg [31:0] acc2; + + // Keep track of which bit I'm working on. + reg [4:0] bitl; + wire [15:0] bit = 1 << bitl; + wire [31:0] bit2 = 1 << (bitl << 1); + + // The output is ready when the bitl counter underflows. + wire rdy = bitl[4]; + + // guess holds the potential next values for acc, and guess2 holds + // the square of that guess. The guess2 calculation is a little bit + // subtle. The idea is that: + // + // guess2 = (acc + bit) * (acc + bit) + // = (acc * acc) + 2*acc*bit + bit*bit + // = acc2 + 2*acc*bit + bit2 + // = acc2 + 2 * (acc< ((y + 1)*(y + 1))) begin + $display("ERROR: y is too small"); + $finish; + end + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/fpga_tests/sub8.v b/ivtest/fpga_tests/sub8.v new file mode 100644 index 000000000..2e0847f0b --- /dev/null +++ b/ivtest/fpga_tests/sub8.v @@ -0,0 +1,5 @@ +module sub8(output wire [7:0] out, input wire [7:0] A, input wire [7:0] B); + + assign out = A - B; + +endmodule diff --git a/ivtest/fpga_tests/sub8_tb.v b/ivtest/fpga_tests/sub8_tb.v new file mode 100644 index 000000000..e507cac38 --- /dev/null +++ b/ivtest/fpga_tests/sub8_tb.v @@ -0,0 +1,39 @@ +/* + * Exhaustive check of all the subtract results. + */ +module main; + + wire [7:0] out; + reg [7:0] A, B; + + sub8 dut(.out(out), .A(A), .B(B)); + + reg error = 0; + integer adx, bdx; + + initial begin + A = 0; + B = 0; + + for (adx = 0 ; adx < 256 ; adx = adx + 1) begin + A = adx; + for (bdx = 0 ; bdx < 256 ; bdx = bdx + 1) begin + B = bdx; + #1 $write("%b - %b: %b", A, B, out); + if (out !== (A - B)) begin + $display(" ERROR"); + error = 1; + end else begin + $display(" OK"); + end + + end // for (bdx = 0 ; bdx < 256 ; bdx += 1) + end // for (adx = 0 ; adx < 256 ; adx = adx + 1) + + if (error == 0) + $display("PASSED"); + else + $display("FAILED"); + + end // initial begin +endmodule // main diff --git a/ivtest/fpga_tests/timer.v b/ivtest/fpga_tests/timer.v new file mode 100644 index 000000000..f041b96c0 --- /dev/null +++ b/ivtest/fpga_tests/timer.v @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + * $Id: timer.v,v 1.1 2003/04/01 05:55:24 stevewilliams Exp $ + */ + +module timer(output wire rdy, input wire clk, input wire reset); + + reg [4:0] count; + assign rdy = count[4]; + + always @(posedge clk or posedge reset) + if (reset) + count <= 5'h0f; + else + count <= count - 1; + +endmodule // timer diff --git a/ivtest/fpga_tests/timer_tb.v b/ivtest/fpga_tests/timer_tb.v new file mode 100644 index 000000000..f50abc79f --- /dev/null +++ b/ivtest/fpga_tests/timer_tb.v @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + * $Id: timer_tb.v,v 1.1 2003/04/01 05:55:24 stevewilliams Exp $ + */ + +`timescale 1us / 1us + +module main; + + wire rdy; + reg reset, clk; + + timer dut(.rdy(rdy), .clk(clk), .reset(reset)); + + always begin + #5 clk = 1; + #5 clk = 0; + end + + initial begin + $dumpvars(0, main); + #7 reset = 1; + #1 if (rdy !== 0) begin + $display("FAILED: reset did not clear rdy. rdy=%b", rdy); + $finish; + end + #6 reset = 0; + end + + always @(posedge clk) + if (rdy === 1) begin + $display("rdy=%b at time=%0d", rdy, $time); + if ($time != 175) begin + $display("FAILED: timer ran out incorrectly."); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/gold/always_comb_no_sens.gold b/ivtest/gold/always_comb_no_sens.gold new file mode 100644 index 000000000..dcdce3b63 --- /dev/null +++ b/ivtest/gold/always_comb_no_sens.gold @@ -0,0 +1,2 @@ +./ivltests/always_comb_no_sens.v:5: warning: always_comb process has no sensitivities. +PASSED diff --git a/ivtest/gold/always_comb_warn.gold b/ivtest/gold/always_comb_warn.gold new file mode 100644 index 000000000..5503190fa --- /dev/null +++ b/ivtest/gold/always_comb_warn.gold @@ -0,0 +1,55 @@ +./ivltests/always_comb_warn.v:20: warning: An event (int2) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:20: warning: An event (int1) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:21: warning: A non-integral variable (intrl) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:22: warning: A non-blocking assignment should not be used in an always_comb process. +./ivltests/always_comb_warn.v:23: warning: An event trigger statement cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:24: warning: Assinging to a non-integral variable (rl) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:25: warning: A non-blocking assignment should not be used in an always_comb process. +./ivltests/always_comb_warn.v:25: warning: Assinging to a non-integral variable (rl) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:26: warning: Assinging to a non-integral variable (ar) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:27: warning: A for statement must have a constant initial value to be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:27: warning: A for statement must compare against a constant value to be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:27: warning: A for statement must have a constant step value to be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:27: warning: System task ($display) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:28: warning: A for statement must use the index (idx) in the condition expression to be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:28: warning: A for statement must use the index (idx) in the step expression to be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:28: warning: System task ($display) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:29: warning: A for statement step must be an assignment to the index variable (idx) to be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:29: warning: System task ($display) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:30: warning: A for statement step must be a simple assignment statement to be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:30: warning: System task ($display) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:31: warning: A for statement step does not support operator 'l' it must be +/- to be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:31: warning: System task ($display) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:32: warning: A for statement step must be a simple binary +/- to be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:32: warning: System task ($display) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:33: warning: System task ($display) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:34: warning: Dynamic array delete method cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:35: warning: System task ($display) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:14: warning: An event (tevt) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:13: warning: A non-integral variable (trl) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:12: warning: user task (a_task) must be automatic to be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:16: warning: System task ($display) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:37: warning: A procedural assign statement cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:38: warning: A procedural deassign statement cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:39: warning: A do/while statement cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:39: warning: System task ($display) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:41: warning: A force statement cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:42: warning: A release statement cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:43: warning: A while statement cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:44: warning: System task ($display) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:47: warning: A repeat statement cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:47: warning: System task ($display) cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:48: warning: A disable statement can only be synthesized when disabling an enclosing block in an always_comb process. +./ivltests/always_comb_warn.v:49: warning: A forever statement cannot be synthesized in an always_comb process. +./ivltests/always_comb_warn.v:50: warning: System task ($display) cannot be synthesized in an always_comb process. +For: 0 +array size: 2 +array size: 0 +user task +do/while +while +repeat +repeat +forever +Expect compile warnings! +PASSED diff --git a/ivtest/gold/always_ff_warn.gold b/ivtest/gold/always_ff_warn.gold new file mode 100644 index 000000000..211ee43c0 --- /dev/null +++ b/ivtest/gold/always_ff_warn.gold @@ -0,0 +1,53 @@ +./ivltests/always_ff_warn.v:21: warning: An event (int2) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:21: warning: An event (int1) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:22: warning: A non-integral variable (intrl) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:24: warning: An event trigger statement cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:25: warning: Assinging to a non-integral variable (rl) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:26: warning: Assinging to a non-integral variable (rl) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:27: warning: Assinging to a non-integral variable (ar) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:28: warning: A for statement must have a constant initial value to be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:28: warning: A for statement must compare against a constant value to be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:28: warning: A for statement must have a constant step value to be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:28: warning: System task ($display) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:29: warning: A for statement must use the index (idx) in the condition expression to be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:29: warning: A for statement must use the index (idx) in the step expression to be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:29: warning: System task ($display) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:30: warning: A for statement step must be an assignment to the index variable (idx) to be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:30: warning: System task ($display) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:31: warning: A for statement step must be a simple assignment statement to be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:31: warning: System task ($display) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:32: warning: A for statement step does not support operator 'l' it must be +/- to be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:32: warning: System task ($display) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:33: warning: A for statement step must be a simple binary +/- to be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:33: warning: System task ($display) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:34: warning: System task ($display) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:35: warning: Dynamic array delete method cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:36: warning: System task ($display) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:15: warning: An event (tevt) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:14: warning: A non-integral variable (trl) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:13: warning: user task (a_task) must be automatic to be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:17: warning: System task ($display) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:38: warning: A procedural assign statement cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:39: warning: A procedural deassign statement cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:40: warning: A do/while statement cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:40: warning: System task ($display) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:42: warning: A force statement cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:43: warning: A release statement cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:44: warning: A while statement cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:45: warning: System task ($display) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:48: warning: A repeat statement cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:48: warning: System task ($display) cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:49: warning: A disable statement can only be synthesized when disabling an enclosing block in an always_ff process. +./ivltests/always_ff_warn.v:50: warning: A forever statement cannot be synthesized in an always_ff process. +./ivltests/always_ff_warn.v:51: warning: System task ($display) cannot be synthesized in an always_ff process. +For: 0 +array size: 2 +array size: 0 +user task +do/while +while +repeat +repeat +forever +Expect compile warnings! +PASSED diff --git a/ivtest/gold/always_ff_warn_sens.gold b/ivtest/gold/always_ff_warn_sens.gold new file mode 100644 index 000000000..6b46c4dff --- /dev/null +++ b/ivtest/gold/always_ff_warn_sens.gold @@ -0,0 +1,9 @@ +./ivltests/always_ff_warn_sens.v:53 warning: Synthesis wants the sensitivity list expressions for 'posedge rst' to be a single bit. +./ivltests/always_ff_warn_sens.v:45 warning: Synthesis requires the sensitivity list of an always_ff process to only be edge sensitive. &rst is missing a pos/negedge. +./ivltests/always_ff_warn_sens.v:37 warning: Synthesis requires the sensitivity list of an always_ff process to only be edge sensitive. ~rst[] is missing a pos/negedge. +./ivltests/always_ff_warn_sens.v:29 warning: Synthesis requires the sensitivity list of an always_ff process to only be edge sensitive. ~|rst is missing a pos/negedge. +./ivltests/always_ff_warn_sens.v:21 warning: Synthesis requires the sensitivity list of an always_ff process to only be edge sensitive. rst[] is missing a pos/negedge. +./ivltests/always_ff_warn_sens.v:13 warning: Synthesis requires the sensitivity list of an always_ff process to only be edge sensitive. rst[] is missing a pos/negedge. +./ivltests/always_ff_warn_sens.v:8 warning: Synthesis requires the sensitivity list of an always_ff process to only be edge sensitive. clk is missing a pos/negedge. +Expect compile warnings! +PASSED diff --git a/ivtest/gold/always_latch_warn.gold b/ivtest/gold/always_latch_warn.gold new file mode 100644 index 000000000..20b7a3e04 --- /dev/null +++ b/ivtest/gold/always_latch_warn.gold @@ -0,0 +1,53 @@ +./ivltests/always_latch_warn.v:20: warning: An event (int2) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:20: warning: An event (int1) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:21: warning: A non-integral variable (intrl) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:23: warning: An event trigger statement cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:24: warning: Assinging to a non-integral variable (rl) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:25: warning: Assinging to a non-integral variable (rl) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:26: warning: Assinging to a non-integral variable (ar) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:27: warning: A for statement must have a constant initial value to be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:27: warning: A for statement must compare against a constant value to be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:27: warning: A for statement must have a constant step value to be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:27: warning: System task ($display) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:28: warning: A for statement must use the index (idx) in the condition expression to be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:28: warning: A for statement must use the index (idx) in the step expression to be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:28: warning: System task ($display) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:29: warning: A for statement step must be an assignment to the index variable (idx) to be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:29: warning: System task ($display) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:30: warning: A for statement step must be a simple assignment statement to be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:30: warning: System task ($display) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:31: warning: A for statement step does not support operator 'l' it must be +/- to be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:31: warning: System task ($display) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:32: warning: A for statement step must be a simple binary +/- to be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:32: warning: System task ($display) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:33: warning: System task ($display) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:34: warning: Dynamic array delete method cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:35: warning: System task ($display) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:14: warning: An event (tevt) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:13: warning: A non-integral variable (trl) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:12: warning: user task (a_task) must be automatic to be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:16: warning: System task ($display) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:37: warning: A procedural assign statement cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:38: warning: A procedural deassign statement cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:39: warning: A do/while statement cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:39: warning: System task ($display) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:41: warning: A force statement cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:42: warning: A release statement cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:43: warning: A while statement cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:44: warning: System task ($display) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:47: warning: A repeat statement cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:47: warning: System task ($display) cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:48: warning: A disable statement can only be synthesized when disabling an enclosing block in an always_latch process. +./ivltests/always_latch_warn.v:49: warning: A forever statement cannot be synthesized in an always_latch process. +./ivltests/always_latch_warn.v:50: warning: System task ($display) cannot be synthesized in an always_latch process. +For: 0 +array size: 2 +array size: 0 +user task +do/while +while +repeat +repeat +forever +Expect compile warnings! +PASSED diff --git a/ivtest/gold/always_star_array_lval.gold b/ivtest/gold/always_star_array_lval.gold new file mode 100644 index 000000000..87408cb09 --- /dev/null +++ b/ivtest/gold/always_star_array_lval.gold @@ -0,0 +1,5 @@ +0 1 2 3 +4 1 2 3 +4 5 2 3 +4 5 6 3 +4 5 6 7 diff --git a/ivtest/gold/array_dump.vcd.gold b/ivtest/gold/array_dump.vcd.gold new file mode 100644 index 000000000..da8c9312d --- /dev/null +++ b/ivtest/gold/array_dump.vcd.gold @@ -0,0 +1,29 @@ +$date + Tue Apr 21 18:40:22 2009 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module top $end +$var reg 8 ! \array[0] [7:0] $end +$upscope $end +$scope module top $end +$var reg 8 " \array[1] [7:0] $end +$upscope $end +$scope module top $end +$var reg 8 # \array[2] [7:0] $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +bx # +bx " +bx ! +$end +#1 +b1010101 # +b0 " +b11111111 ! diff --git a/ivtest/gold/array_packed_2d.gold b/ivtest/gold/array_packed_2d.gold new file mode 100644 index 000000000..6e6bf61f1 --- /dev/null +++ b/ivtest/gold/array_packed_2d.gold @@ -0,0 +1,36 @@ +02040608 + 2 + 4 + 6 + 8 + 2 + 4 + 6 + 8 +02040608 + 2 + 4 + 6 + 8 + 2 + 4 + 6 + 8 +08060402 + 2 + 4 + 6 + 8 + 2 + 4 + 6 + 8 +08060402 + 2 + 4 + 6 + 8 + 2 + 4 + 6 + 8 diff --git a/ivtest/gold/array_word_check.gold b/ivtest/gold/array_word_check.gold new file mode 100644 index 000000000..5673dc6fc --- /dev/null +++ b/ivtest/gold/array_word_check.gold @@ -0,0 +1,3 @@ +VCD info: dumpfile work/dup.vcd opened for output. +VCD warning: array word top.array[0] will conflict with an escaped identifier. +VCD warning: array word top.array[1] will conflict with an escaped identifier. diff --git a/ivtest/gold/array_word_width.gold b/ivtest/gold/array_word_width.gold new file mode 100644 index 000000000..1ce74b6b0 --- /dev/null +++ b/ivtest/gold/array_word_width.gold @@ -0,0 +1 @@ +0003 diff --git a/ivtest/gold/automatic_error11.gold b/ivtest/gold/automatic_error11.gold new file mode 100644 index 000000000..722f3b08d --- /dev/null +++ b/ivtest/gold/automatic_error11.gold @@ -0,0 +1 @@ +ERROR: ./ivltests/automatic_error11.v:9: $monitor argument "local" is an automatic variable. diff --git a/ivtest/gold/automatic_error12.gold b/ivtest/gold/automatic_error12.gold new file mode 100644 index 000000000..30fc605f2 --- /dev/null +++ b/ivtest/gold/automatic_error12.gold @@ -0,0 +1 @@ +ERROR: ./ivltests/automatic_error12.v:10: $strobe argument "local" is an automatic variable. diff --git a/ivtest/gold/automatic_error13.gold b/ivtest/gold/automatic_error13.gold new file mode 100644 index 000000000..27402e9c1 --- /dev/null +++ b/ivtest/gold/automatic_error13.gold @@ -0,0 +1 @@ +ERROR: ./ivltests/automatic_error13.v:10: $fstrobe argument "local" is an automatic variable. diff --git a/ivtest/gold/automatic_events.gold b/ivtest/gold/automatic_events.gold new file mode 100644 index 000000000..9ea03a329 --- /dev/null +++ b/ivtest/gold/automatic_events.gold @@ -0,0 +1,40 @@ +task 1 triggered: 00000 00001 00001 22 +task 2 triggered: 00000 00001 00001 24 +task 1 triggered: 00000 00001 00000 32 +task 2 triggered: 00000 00001 00000 34 +task 1 triggered: 00000 00010 00010 62 +task 2 triggered: 00000 00010 00010 64 +task 1 triggered: 00000 00010 00000 72 +task 2 triggered: 00000 00010 00000 74 +task 1 triggered: 00000 00100 00100 102 +task 2 triggered: 00000 00100 00100 104 +task 1 triggered: 00000 00100 00000 112 +task 2 triggered: 00000 00100 00000 114 +task 1 triggered: 00000 01000 01000 142 +task 2 triggered: 00000 01000 01000 144 +task 1 triggered: 00000 01000 00000 152 +task 2 triggered: 00000 01000 00000 154 +task 1 triggered: 00000 10000 10000 182 +task 2 triggered: 00000 10000 10000 184 +task 1 triggered: 00000 10000 00000 192 +task 2 triggered: 00000 10000 00000 194 +task 1 triggered: 00001 00000 00000 211 +task 2 triggered: 00001 00000 00000 212 +task 1 triggered: 00000 00000 00000 221 +task 2 triggered: 00000 00000 00000 222 +task 1 triggered: 00010 00000 00000 231 +task 2 triggered: 00010 00000 00000 232 +task 1 triggered: 00000 00000 00000 241 +task 2 triggered: 00000 00000 00000 242 +task 1 triggered: 00100 00000 00000 251 +task 2 triggered: 00100 00000 00000 252 +task 1 triggered: 00000 00000 00000 261 +task 2 triggered: 00000 00000 00000 262 +task 1 triggered: 01000 00000 00000 271 +task 2 triggered: 01000 00000 00000 272 +task 1 triggered: 00000 00000 00000 281 +task 2 triggered: 00000 00000 00000 282 +task 1 triggered: 10000 00000 00000 291 +task 2 triggered: 10000 00000 00000 292 +task 1 triggered: 00000 00000 00000 301 +task 2 triggered: 00000 00000 00000 302 diff --git a/ivtest/gold/automatic_events3.gold b/ivtest/gold/automatic_events3.gold new file mode 100644 index 000000000..97f08681a --- /dev/null +++ b/ivtest/gold/automatic_events3.gold @@ -0,0 +1,24 @@ +Time 20 : Source[0] rise +Time 20 : Source[0] edge +Time 25 : Source[1] rise +Time 25 : Source[1] edge +Time 35 : Source[1] rise +Time 35 : Source[1] edge +Time 40 : Source[0] fall +Time 40 : Source[0] edge +Time 45 : Source[1] fall +Time 45 : Source[1] edge +Time 55 : Source[1] fall +Time 55 : Source[1] edge +Time 60 : Source[0] rise +Time 60 : Source[0] edge +Time 65 : Source[1] rise +Time 65 : Source[1] edge +Time 75 : Source[1] rise +Time 75 : Source[1] edge +Time 80 : Source[0] fall +Time 80 : Source[0] edge +Time 85 : Source[1] fall +Time 85 : Source[1] edge +Time 95 : Source[1] fall +Time 95 : Source[1] edge diff --git a/ivtest/gold/automatic_task.gold b/ivtest/gold/automatic_task.gold new file mode 100644 index 000000000..b0eb80ad9 --- /dev/null +++ b/ivtest/gold/automatic_task.gold @@ -0,0 +1,8 @@ + 1 x x x + 2 x x x + 1 1 x x + 2 2 x x + 1 1 1 x + 2 2 2 x + 1 1 1 1 + 2 2 2 2 diff --git a/ivtest/gold/automatic_task2.gold b/ivtest/gold/automatic_task2.gold new file mode 100644 index 000000000..b0eb80ad9 --- /dev/null +++ b/ivtest/gold/automatic_task2.gold @@ -0,0 +1,8 @@ + 1 x x x + 2 x x x + 1 1 x x + 2 2 x x + 1 1 1 x + 2 2 2 x + 1 1 1 1 + 2 2 2 2 diff --git a/ivtest/gold/automatic_task3.gold b/ivtest/gold/automatic_task3.gold new file mode 100644 index 000000000..d62de3115 --- /dev/null +++ b/ivtest/gold/automatic_task3.gold @@ -0,0 +1,16 @@ + 1 x x x + 1 x x x + 2 x x x + 2 x x x + 2 1 x x + 2 1 x x + 2 2 x x + 2 2 x x + 2 2 1 x + 2 2 1 x + 2 2 2 x + 2 2 2 x + 2 2 2 1 + 2 2 2 1 + 2 2 2 2 + 2 2 2 2 diff --git a/ivtest/gold/bitsel.gold b/ivtest/gold/bitsel.gold new file mode 100644 index 000000000..fe558cabf --- /dev/null +++ b/ivtest/gold/bitsel.gold @@ -0,0 +1,8 @@ +1 +0 +0 +1 +0 +1 +1 +0 diff --git a/ivtest/gold/br1003a-v10.gold b/ivtest/gold/br1003a-v10.gold new file mode 100644 index 000000000..b395832ec --- /dev/null +++ b/ivtest/gold/br1003a-v10.gold @@ -0,0 +1,5 @@ +Time scale of (top) is 1ns / 1ps +Time scale of (top) is 1ns / 1ps +Time scale of (testclass) is 100ps / 10ps +50 5 +PASSED diff --git a/ivtest/gold/br1003a.gold b/ivtest/gold/br1003a.gold new file mode 100644 index 000000000..12fc0c554 --- /dev/null +++ b/ivtest/gold/br1003a.gold @@ -0,0 +1,5 @@ +Time scale of (top) is 1ns / 1ps +Time scale of (top) is 1ns / 1ps +Time scale of ($unit) is 100ps / 10ps +50 5 +PASSED diff --git a/ivtest/gold/br1003b-v10.gold b/ivtest/gold/br1003b-v10.gold new file mode 100644 index 000000000..7e2305be0 --- /dev/null +++ b/ivtest/gold/br1003b-v10.gold @@ -0,0 +1,5 @@ +Time scale of (top) is 1ns / 1ps +Time scale of (top) is 1ns / 1ps +Time scale of (delay) is 100ps / 10ps +50 5 +PASSED diff --git a/ivtest/gold/br1003b-vlog95.gold b/ivtest/gold/br1003b-vlog95.gold new file mode 100644 index 000000000..22eb8ee58 --- /dev/null +++ b/ivtest/gold/br1003b-vlog95.gold @@ -0,0 +1,5 @@ +Time scale of (top) is 1ns / 1ps +Time scale of (top) is 1ns / 1ps +Time scale of (ivl_package_$unit) is 100ps / 10ps +50 5 +PASSED diff --git a/ivtest/gold/br1003b.gold b/ivtest/gold/br1003b.gold new file mode 100644 index 000000000..12fc0c554 --- /dev/null +++ b/ivtest/gold/br1003b.gold @@ -0,0 +1,5 @@ +Time scale of (top) is 1ns / 1ps +Time scale of (top) is 1ns / 1ps +Time scale of ($unit) is 100ps / 10ps +50 5 +PASSED diff --git a/ivtest/gold/br1003c-v10.gold b/ivtest/gold/br1003c-v10.gold new file mode 100644 index 000000000..7e2305be0 --- /dev/null +++ b/ivtest/gold/br1003c-v10.gold @@ -0,0 +1,5 @@ +Time scale of (top) is 1ns / 1ps +Time scale of (top) is 1ns / 1ps +Time scale of (delay) is 100ps / 10ps +50 5 +PASSED diff --git a/ivtest/gold/br1003c-vlog95.gold b/ivtest/gold/br1003c-vlog95.gold new file mode 100644 index 000000000..22eb8ee58 --- /dev/null +++ b/ivtest/gold/br1003c-vlog95.gold @@ -0,0 +1,5 @@ +Time scale of (top) is 1ns / 1ps +Time scale of (top) is 1ns / 1ps +Time scale of (ivl_package_$unit) is 100ps / 10ps +50 5 +PASSED diff --git a/ivtest/gold/br1003c.gold b/ivtest/gold/br1003c.gold new file mode 100644 index 000000000..12fc0c554 --- /dev/null +++ b/ivtest/gold/br1003c.gold @@ -0,0 +1,5 @@ +Time scale of (top) is 1ns / 1ps +Time scale of (top) is 1ns / 1ps +Time scale of ($unit) is 100ps / 10ps +50 5 +PASSED diff --git a/ivtest/gold/br1003d-vlog95.gold b/ivtest/gold/br1003d-vlog95.gold new file mode 100644 index 000000000..266a8b0b1 --- /dev/null +++ b/ivtest/gold/br1003d-vlog95.gold @@ -0,0 +1,5 @@ +Time scale of (top) is 1ns / 1ps +Time scale of (top) is 1ns / 1ps +Time scale of (ivl_package_testpackage) is 100ps / 10ps +50 5 +PASSED diff --git a/ivtest/gold/br1003d.gold b/ivtest/gold/br1003d.gold new file mode 100644 index 000000000..4b6e070f0 --- /dev/null +++ b/ivtest/gold/br1003d.gold @@ -0,0 +1,5 @@ +Time scale of (top) is 1ns / 1ps +Time scale of (top) is 1ns / 1ps +Time scale of (testpackage) is 100ps / 10ps +50 5 +PASSED diff --git a/ivtest/gold/br1005.gold b/ivtest/gold/br1005.gold new file mode 100644 index 000000000..84d510850 --- /dev/null +++ b/ivtest/gold/br1005.gold @@ -0,0 +1,2 @@ +./ivltests/br1005.v:2: sorry: SV queues inside classes are not yet supported. +2 error(s) during elaboration. diff --git a/ivtest/gold/br1007-vlog95.gold b/ivtest/gold/br1007-vlog95.gold new file mode 100644 index 000000000..8b91e9f26 --- /dev/null +++ b/ivtest/gold/br1007-vlog95.gold @@ -0,0 +1,10 @@ +./ivltests/br1007.v:15: warning: bit select value[5] is out of range. +./ivltests/br1007.v:20: warning: Part select value[5:5] is out of range. +./ivltests/br1007.v:25: warning: Part select value[5:4] is out of range. +vlog95.v:17: warning: bit select value[5] is out of range. +vlog95.v:20: warning: bit select value[5] is out of range. +vlog95.v:23: warning: Part select value[5:4] is out of range. +0000 +0000 +1000 +PASSED diff --git a/ivtest/gold/br1007.gold b/ivtest/gold/br1007.gold new file mode 100644 index 000000000..b9e6ae562 --- /dev/null +++ b/ivtest/gold/br1007.gold @@ -0,0 +1,7 @@ +./ivltests/br1007.v:15: warning: bit select value[5] is out of range. +./ivltests/br1007.v:20: warning: Part select value[5:5] is out of range. +./ivltests/br1007.v:25: warning: Part select value[5:4] is out of range. +0000 +0000 +1000 +PASSED diff --git a/ivtest/gold/br1008.gold b/ivtest/gold/br1008.gold new file mode 100644 index 000000000..4ce4dfafe --- /dev/null +++ b/ivtest/gold/br1008.gold @@ -0,0 +1 @@ +b = [zzzz 0000] diff --git a/ivtest/gold/br1027a-fsv.gold b/ivtest/gold/br1027a-fsv.gold new file mode 100644 index 000000000..6e8183b72 --- /dev/null +++ b/ivtest/gold/br1027a-fsv.gold @@ -0,0 +1 @@ +0 1 diff --git a/ivtest/gold/br1027a.gold b/ivtest/gold/br1027a.gold new file mode 100644 index 000000000..dc6440404 --- /dev/null +++ b/ivtest/gold/br1027a.gold @@ -0,0 +1,2 @@ +./ivltests/br1027a.v:1: error: missing task/function port direction. +./ivltests/br1027a.v:1: error: missing task/function port direction. diff --git a/ivtest/gold/br1027b.gold b/ivtest/gold/br1027b.gold new file mode 100644 index 000000000..6e8183b72 --- /dev/null +++ b/ivtest/gold/br1027b.gold @@ -0,0 +1 @@ +0 1 diff --git a/ivtest/gold/br1027c-fsv.gold b/ivtest/gold/br1027c-fsv.gold new file mode 100644 index 000000000..2833e3911 --- /dev/null +++ b/ivtest/gold/br1027c-fsv.gold @@ -0,0 +1 @@ + 0 1 diff --git a/ivtest/gold/br1027c.gold b/ivtest/gold/br1027c.gold new file mode 100644 index 000000000..80d6309f4 --- /dev/null +++ b/ivtest/gold/br1027c.gold @@ -0,0 +1 @@ +./ivltests/br1027c.v:1: error: missing task/function port direction. diff --git a/ivtest/gold/br1027d.gold b/ivtest/gold/br1027d.gold new file mode 100644 index 000000000..2833e3911 --- /dev/null +++ b/ivtest/gold/br1027d.gold @@ -0,0 +1 @@ + 0 1 diff --git a/ivtest/gold/br1027e-fsv.gold b/ivtest/gold/br1027e-fsv.gold new file mode 100644 index 000000000..2833e3911 --- /dev/null +++ b/ivtest/gold/br1027e-fsv.gold @@ -0,0 +1 @@ + 0 1 diff --git a/ivtest/gold/br1027e.gold b/ivtest/gold/br1027e.gold new file mode 100644 index 000000000..39b8bbdb1 --- /dev/null +++ b/ivtest/gold/br1027e.gold @@ -0,0 +1 @@ +./ivltests/br1027e.v:1: error: missing task/function port direction. diff --git a/ivtest/gold/br1027f.gold b/ivtest/gold/br1027f.gold new file mode 100644 index 000000000..2833e3911 --- /dev/null +++ b/ivtest/gold/br1027f.gold @@ -0,0 +1 @@ + 0 1 diff --git a/ivtest/gold/br1029a.gold b/ivtest/gold/br1029a.gold new file mode 100644 index 000000000..e86fb9692 --- /dev/null +++ b/ivtest/gold/br1029a.gold @@ -0,0 +1,12 @@ +a: 0.4 0 0 0 +b: 0.5 1 1 1 +c: 0.6 1 1 1 +d: 2.4 2 2 10 +e: 2.5 3 3 11 +f: 2.6 3 3 11 +a: -0.4 -0 0 0 +b: -0.5 -1 ffffffffffffffff 1111111111111111111111111111111111111111111111111111111111111111 +c: -0.6 -1 ffffffffffffffff 1111111111111111111111111111111111111111111111111111111111111111 +d: -2.4 -2 fffffffffffffffe 1111111111111111111111111111111111111111111111111111111111111110 +e: -2.5 -3 fffffffffffffffd 1111111111111111111111111111111111111111111111111111111111111101 +f: -2.6 -3 fffffffffffffffd 1111111111111111111111111111111111111111111111111111111111111101 diff --git a/ivtest/gold/br1029c.gold b/ivtest/gold/br1029c.gold new file mode 100644 index 000000000..b6fd6b709 --- /dev/null +++ b/ivtest/gold/br1029c.gold @@ -0,0 +1,2 @@ +./ivltests/br1029c.v:3: error: The argument to $signed must be a vector type. +Elaboration failed diff --git a/ivtest/gold/br916a-vlog95.gold b/ivtest/gold/br916a-vlog95.gold new file mode 100644 index 000000000..4424c4809 --- /dev/null +++ b/ivtest/gold/br916a-vlog95.gold @@ -0,0 +1,4 @@ +SORRY: vlog95.v:15: currently only simple signals or constant expressions may be passed to $strobe. +NOTE: You can work around this by assigning the desired expression to an + intermediate net (using a continuous assignment) and passing that net + to $strobe. diff --git a/ivtest/gold/br916a.gold b/ivtest/gold/br916a.gold new file mode 100644 index 000000000..5b964e1c4 --- /dev/null +++ b/ivtest/gold/br916a.gold @@ -0,0 +1,4 @@ +SORRY: ./ivltests/br916a.v:6: currently only simple signals or constant expressions may be passed to $strobe. +NOTE: You can work around this by assigning the desired expression to an + intermediate net (using a continuous assignment) and passing that net + to $strobe. diff --git a/ivtest/gold/br916b-vlog95.gold b/ivtest/gold/br916b-vlog95.gold new file mode 100644 index 000000000..0c7ba09d4 --- /dev/null +++ b/ivtest/gold/br916b-vlog95.gold @@ -0,0 +1,4 @@ +SORRY: vlog95.v:13: currently only simple signals or constant expressions may be passed to $monitor. +NOTE: You can work around this by assigning the desired expression to an + intermediate net (using a continuous assignment) and passing that net + to $monitor. diff --git a/ivtest/gold/br916b.gold b/ivtest/gold/br916b.gold new file mode 100644 index 000000000..0e1d748fd --- /dev/null +++ b/ivtest/gold/br916b.gold @@ -0,0 +1,4 @@ +SORRY: ./ivltests/br916b.v:4: currently only simple signals or constant expressions may be passed to $monitor. +NOTE: You can work around this by assigning the desired expression to an + intermediate net (using a continuous assignment) and passing that net + to $monitor. diff --git a/ivtest/gold/br921.gold b/ivtest/gold/br921.gold new file mode 100644 index 000000000..10ccd84ad --- /dev/null +++ b/ivtest/gold/br921.gold @@ -0,0 +1,2 @@ +./ivltests/br921.v:6: warning: User function 'test_fcn' is being called as a task. +PASSED diff --git a/ivtest/gold/br947.gold b/ivtest/gold/br947.gold new file mode 100644 index 000000000..f779a2d11 --- /dev/null +++ b/ivtest/gold/br947.gold @@ -0,0 +1,6 @@ + 0 x x x x + 100 1 x x 1 + 200 1 1 x 1 + 250 1 1 x x + 300 1 1 1 1 +PASSED diff --git a/ivtest/gold/br960a.gold b/ivtest/gold/br960a.gold new file mode 100644 index 000000000..1adaa30be --- /dev/null +++ b/ivtest/gold/br960a.gold @@ -0,0 +1,16 @@ +Max (X->Z) +0.00 x=0 0 +0.30 z=0 0 +Fall (Z->0) +10.00 z=0 1 +11.30 0=0 1 +Rise (0->Z) +20.00 0=0 0 +21.20 z=0 0 +25.00 z=1 0 +Rise (Z->1) +30.00 z=1 1 +31.20 1=1 1 +Fall (1->Z) +40.00 1=1 0 +41.30 z=1 0 diff --git a/ivtest/gold/br960b.gold b/ivtest/gold/br960b.gold new file mode 100644 index 000000000..888ff592f --- /dev/null +++ b/ivtest/gold/br960b.gold @@ -0,0 +1,16 @@ +Max (X->Z) +0.00 x=0 0 +0.40 z=0 0 +Fall (Z->0) +10.00 z=0 1 +11.30 0=0 1 +To High-Z (0->Z) +20.00 0=0 0 +21.40 z=0 0 +25.00 z=1 0 +Rise (Z->1) +30.00 z=1 1 +31.20 1=1 1 +To High-Z (1->Z) +40.00 1=1 0 +41.40 z=1 0 diff --git a/ivtest/gold/br960c.gold b/ivtest/gold/br960c.gold new file mode 100644 index 000000000..730d4b629 --- /dev/null +++ b/ivtest/gold/br960c.gold @@ -0,0 +1,16 @@ +Max (X->Z) +0.00 x=0 0 +0.40 z=0 0 +Z->0 +10.00 z=0 1 +11.50 0=0 1 +0->Z +20.00 0=0 0 +21.20 z=0 0 +25.00 z=1 0 +Z->1 +30.00 z=1 1 +31.30 1=1 1 +1->Z +40.00 1=1 0 +41.40 z=1 0 diff --git a/ivtest/gold/br960d.gold b/ivtest/gold/br960d.gold new file mode 100644 index 000000000..12b5c3b90 --- /dev/null +++ b/ivtest/gold/br960d.gold @@ -0,0 +1,16 @@ +Max (X->Z) +0.00 x=0 0 +0.20 z=0 0 +Fall (Z->0) +10.00 z=0 1 +11.20 0=0 1 +Rise (0->Z) +20.00 0=0 0 +21.20 z=0 0 +25.00 z=1 0 +Rise (Z->1) +30.00 z=1 1 +31.20 1=1 1 +Fall (1->Z) +40.00 1=1 0 +41.20 z=1 0 diff --git a/ivtest/gold/br975-v10.gold b/ivtest/gold/br975-v10.gold new file mode 100644 index 000000000..7c20799ee --- /dev/null +++ b/ivtest/gold/br975-v10.gold @@ -0,0 +1,4 @@ +./ivltests/br975.v:12: error: duplicate declaration for net or variable 'w1' in 'bug'. +./ivltests/br975.v:15: error: duplicate declaration for net or variable 'd1' in 'bug'. +./ivltests/br975.v:18: error: duplicate declaration for net or variable 'e1' in 'bug'. +./ivltests/br975.v:21: error: duplicate declaration for net or variable 'r1' in 'bug'. diff --git a/ivtest/gold/br975.gold b/ivtest/gold/br975.gold new file mode 100644 index 000000000..1bf6a7240 --- /dev/null +++ b/ivtest/gold/br975.gold @@ -0,0 +1,8 @@ +./ivltests/br975.v:12: error: 'w1' has already been declared in this scope. +./ivltests/br975.v:11: : It was declared here as a net. +./ivltests/br975.v:15: error: 'd1' has already been declared in this scope. +./ivltests/br975.v:14: : It was declared here as a variable. +./ivltests/br975.v:18: error: 'e1' has already been declared in this scope. +./ivltests/br975.v:17: : It was declared here as a variable. +./ivltests/br975.v:21: error: 'r1' has already been declared in this scope. +./ivltests/br975.v:20: : It was declared here as a variable. diff --git a/ivtest/gold/br991b.gold b/ivtest/gold/br991b.gold new file mode 100644 index 000000000..62402f37d --- /dev/null +++ b/ivtest/gold/br991b.gold @@ -0,0 +1,11 @@ +./ivltests/br991b.v:23: error: always process does not have any delay. +./ivltests/br991b.v:23: : A runtime infinite loop will occur. +./ivltests/br991b.v:19: error: always process does not have any delay. +./ivltests/br991b.v:19: : A runtime infinite loop will occur. +./ivltests/br991b.v:15: error: always process does not have any delay. +./ivltests/br991b.v:15: : A runtime infinite loop will occur. +./ivltests/br991b.v:11: error: always process does not have any delay. +./ivltests/br991b.v:11: : A runtime infinite loop will occur. +./ivltests/br991b.v:7: error: always process does not have any delay. +./ivltests/br991b.v:7: : A runtime infinite loop will occur. +Elaboration failed diff --git a/ivtest/gold/br_gh105a.gold b/ivtest/gold/br_gh105a.gold new file mode 100644 index 000000000..802992c42 --- /dev/null +++ b/ivtest/gold/br_gh105a.gold @@ -0,0 +1 @@ +Hello world diff --git a/ivtest/gold/br_gh105b.gold b/ivtest/gold/br_gh105b.gold new file mode 100644 index 000000000..1c304d8b0 --- /dev/null +++ b/ivtest/gold/br_gh105b.gold @@ -0,0 +1,3 @@ +No args +Args = hello +Args = 123, hello diff --git a/ivtest/gold/br_gh127a.gold b/ivtest/gold/br_gh127a.gold new file mode 100644 index 000000000..66a3c75a4 --- /dev/null +++ b/ivtest/gold/br_gh127a.gold @@ -0,0 +1,9 @@ +./ivltests/br_gh127a.v:21: warning: Port 2 (in) of copy expects 2 bits, got 1. +./ivltests/br_gh127a.v:21: : Padding 1 high bits of the port. +./ivltests/br_gh127a.v:23: warning: Port 2 (in) of copy expects 2 bits, got 3. +./ivltests/br_gh127a.v:23: : Pruning 1 high bits of the expression. +00 : 0 00 : 00 00 : 000 00 +01 : 1 01 : 01 01 : 001 01 +10 : 0 00 : 10 10 : 010 10 +11 : 1 01 : 11 11 : 011 11 +PASSED diff --git a/ivtest/gold/br_gh127b.gold b/ivtest/gold/br_gh127b.gold new file mode 100644 index 000000000..89670456b --- /dev/null +++ b/ivtest/gold/br_gh127b.gold @@ -0,0 +1,9 @@ +./ivltests/br_gh127b.v:21: warning: Port 2 (in) of copy expects 2 bits, got 1. +./ivltests/br_gh127b.v:21: : Leaving 1 high bits of the port unconnected. +./ivltests/br_gh127b.v:23: warning: Port 2 (in) of copy expects 2 bits, got 3. +./ivltests/br_gh127b.v:23: : Leaving 1 high bits of the expression dangling. +00 : 0 z0 : 00 00 : 000 00 +01 : 1 z1 : 01 01 : 001 01 +10 : 0 z0 : 10 10 : 010 10 +11 : 1 z1 : 11 11 : 011 11 +PASSED diff --git a/ivtest/gold/br_gh127c.gold b/ivtest/gold/br_gh127c.gold new file mode 100644 index 000000000..9a1313cf0 --- /dev/null +++ b/ivtest/gold/br_gh127c.gold @@ -0,0 +1,15 @@ +./ivltests/br_gh127c.v:21: warning: input port out is coerced to inout. +./ivltests/br_gh127c.v:21: warning: output port in is coerced to inout. +./ivltests/br_gh127c.v:21: warning: Port 2 (in) of copy expects 2 bits, got 1. +./ivltests/br_gh127c.v:21: : Leaving 1 high bits of the port unconnected. +./ivltests/br_gh127c.v:22: warning: input port out is coerced to inout. +./ivltests/br_gh127c.v:22: warning: output port in is coerced to inout. +./ivltests/br_gh127c.v:23: warning: input port out is coerced to inout. +./ivltests/br_gh127c.v:23: warning: output port in is coerced to inout. +./ivltests/br_gh127c.v:23: warning: Port 2 (in) of copy expects 2 bits, got 3. +./ivltests/br_gh127c.v:23: : Leaving 1 high bits of the expression dangling. +00 : 0 z0 : 00 00 : 000 00 +01 : 1 z1 : 01 01 : 001 01 +10 : 0 z0 : 10 10 : 010 10 +11 : 1 z1 : 11 11 : 011 11 +PASSED diff --git a/ivtest/gold/br_gh127d.gold b/ivtest/gold/br_gh127d.gold new file mode 100644 index 000000000..0625cf3b9 --- /dev/null +++ b/ivtest/gold/br_gh127d.gold @@ -0,0 +1,9 @@ +./ivltests/br_gh127d.v:21: warning: Port 1 (out) of copy expects 2 bits, got 1. +./ivltests/br_gh127d.v:21: : Padding 1 high bits of the port. +./ivltests/br_gh127d.v:23: warning: Port 1 (out) of copy expects 2 bits, got 3. +./ivltests/br_gh127d.v:23: : Padding 1 high bits of the expression. +00 : 00 0 : 00 00 : 00 000 +01 : 01 1 : 01 01 : 01 001 +10 : 10 0 : 10 10 : 10 010 +11 : 11 1 : 11 11 : 11 011 +PASSED diff --git a/ivtest/gold/br_gh127e.gold b/ivtest/gold/br_gh127e.gold new file mode 100644 index 000000000..8ea1d6e3e --- /dev/null +++ b/ivtest/gold/br_gh127e.gold @@ -0,0 +1,9 @@ +./ivltests/br_gh127e.v:21: warning: Port 1 (out) of copy expects 2 bits, got 1. +./ivltests/br_gh127e.v:21: : Leaving 1 high bits of the port unconnected. +./ivltests/br_gh127e.v:23: warning: Port 1 (out) of copy expects 2 bits, got 3. +./ivltests/br_gh127e.v:23: : Leaving 1 high bits of the expression dangling. +00 : 00 0 : 00 00 : 00 z00 +01 : 01 1 : 01 01 : 01 z01 +10 : 10 0 : 10 10 : 10 z10 +11 : 11 1 : 11 11 : 11 z11 +PASSED diff --git a/ivtest/gold/br_gh127f.gold b/ivtest/gold/br_gh127f.gold new file mode 100644 index 000000000..4aee74d31 --- /dev/null +++ b/ivtest/gold/br_gh127f.gold @@ -0,0 +1,15 @@ +./ivltests/br_gh127f.v:21: warning: input port out is coerced to inout. +./ivltests/br_gh127f.v:21: warning: Port 1 (out) of copy expects 2 bits, got 1. +./ivltests/br_gh127f.v:21: : Leaving 1 high bits of the port unconnected. +./ivltests/br_gh127f.v:21: warning: output port in is coerced to inout. +./ivltests/br_gh127f.v:22: warning: input port out is coerced to inout. +./ivltests/br_gh127f.v:22: warning: output port in is coerced to inout. +./ivltests/br_gh127f.v:23: warning: input port out is coerced to inout. +./ivltests/br_gh127f.v:23: warning: Port 1 (out) of copy expects 2 bits, got 3. +./ivltests/br_gh127f.v:23: : Leaving 1 high bits of the expression dangling. +./ivltests/br_gh127f.v:23: warning: output port in is coerced to inout. +00 : 00 0 : 00 00 : 00 z00 +01 : 01 1 : 01 01 : 01 z01 +10 : 10 0 : 10 10 : 10 z10 +11 : 11 1 : 11 11 : 11 z11 +PASSED diff --git a/ivtest/gold/br_gh13a.gold b/ivtest/gold/br_gh13a.gold new file mode 100644 index 000000000..a4c6cbb08 --- /dev/null +++ b/ivtest/gold/br_gh13a.gold @@ -0,0 +1,3 @@ +./ivltests/br_gh13a.v:7: warning: Unsized expression (('sd1)<<(~(40'b0000000000000000000000000000000000000000))) expanded beyond and was clipped to 65568 bits. Try using sized operands. +0 +PASSED diff --git a/ivtest/gold/br_gh157.gold b/ivtest/gold/br_gh157.gold new file mode 100644 index 000000000..46ba98b2f --- /dev/null +++ b/ivtest/gold/br_gh157.gold @@ -0,0 +1,2 @@ +./ivltests/br_gh157.v:13: warning: parameter x not found in test.dut. +2 diff --git a/ivtest/gold/br_gh165.gold b/ivtest/gold/br_gh165.gold new file mode 100644 index 000000000..dabf6bfcb --- /dev/null +++ b/ivtest/gold/br_gh165.gold @@ -0,0 +1,7 @@ +main thread started at time 0 +main thread continued at time 5 +task 1 finished at time 1001 +task 2 finished at time 1002 +task 3 finished at time 1006 +main thread finished at time 1006 +task 4 finished at time 1007 diff --git a/ivtest/gold/br_gh198.gold b/ivtest/gold/br_gh198.gold new file mode 100644 index 000000000..bc6178395 --- /dev/null +++ b/ivtest/gold/br_gh198.gold @@ -0,0 +1,37 @@ +00 +01 +02 +03 +04 +05 +06 +07 +10 +20 +30 +40 +50 +60 +70 +17 +26 +35 +44 +53 +62 +71 + +00 +01 +02 +03 +04 +05 +06 +07 +10 +20 +30 +17 +26 +35 diff --git a/ivtest/gold/br_gh209.dat b/ivtest/gold/br_gh209.dat new file mode 100644 index 0000000000000000000000000000000000000000..eaf36c1daccfdf325514461cd1a2ffbc139b5464 GIT binary patch literal 4 LcmZQzWMT#Y01f~L literal 0 HcmV?d00001 diff --git a/ivtest/gold/br_gh230-vlog95.gold b/ivtest/gold/br_gh230-vlog95.gold new file mode 100644 index 000000000..678c5c791 --- /dev/null +++ b/ivtest/gold/br_gh230-vlog95.gold @@ -0,0 +1 @@ +ERROR: vlog95.v:13: $dumpvars cannot dump a vpiPartSelect. diff --git a/ivtest/gold/br_gh230.gold b/ivtest/gold/br_gh230.gold new file mode 100644 index 000000000..11357c1c0 --- /dev/null +++ b/ivtest/gold/br_gh230.gold @@ -0,0 +1 @@ +ERROR: ./ivltests/br_gh230.v:6: $dumpvars cannot dump a vpiPartSelect. diff --git a/ivtest/gold/br_gh265.gold b/ivtest/gold/br_gh265.gold new file mode 100644 index 000000000..74907c4de --- /dev/null +++ b/ivtest/gold/br_gh265.gold @@ -0,0 +1,2 @@ +./ivltests/br_gh265.v:8: error: The expression '(8'd1)<<('sd4)' cannot be implicitly cast to the target type. +Elaboration failed diff --git a/ivtest/gold/br_gh289d.gold b/ivtest/gold/br_gh289d.gold new file mode 100644 index 000000000..5eebefa0c --- /dev/null +++ b/ivtest/gold/br_gh289d.gold @@ -0,0 +1,2 @@ +m.p1 1 2 11 +m.p2 1 4 1111 diff --git a/ivtest/gold/br_gh33.gold b/ivtest/gold/br_gh33.gold new file mode 100644 index 000000000..db60bdfa0 --- /dev/null +++ b/ivtest/gold/br_gh33.gold @@ -0,0 +1,4 @@ +a= 7, b= 0, c= 1 -> old= x, new= 1 +a=15, b= 0, c= 2 -> old= x, new= 2 +a= 7, b= 0, c= 3 -> old= 1, new= 3 +a=15, b= 0, c= 4 -> old= 2, new= 4 diff --git a/ivtest/gold/br_gh365.gold b/ivtest/gold/br_gh365.gold new file mode 100644 index 000000000..176840608 --- /dev/null +++ b/ivtest/gold/br_gh365.gold @@ -0,0 +1,2 @@ +DIRECT ASSIGNED STRING is WORKING +Controller's new state is IDLE diff --git a/ivtest/gold/br_gh366.gold b/ivtest/gold/br_gh366.gold new file mode 100644 index 000000000..3dfd150d0 --- /dev/null +++ b/ivtest/gold/br_gh366.gold @@ -0,0 +1 @@ +/usr/local/bin/ diff --git a/ivtest/gold/br_gh368.gold b/ivtest/gold/br_gh368.gold new file mode 100644 index 000000000..b835564fc --- /dev/null +++ b/ivtest/gold/br_gh368.gold @@ -0,0 +1,4 @@ +Process #1 +Process #2 +Process #1 -- completes +Test task completes diff --git a/ivtest/gold/br_gh374.gold b/ivtest/gold/br_gh374.gold new file mode 100644 index 000000000..a911b5ae1 --- /dev/null +++ b/ivtest/gold/br_gh374.gold @@ -0,0 +1,2 @@ +opt1 +opt2 diff --git a/ivtest/gold/br_gh377-vlog95.gold b/ivtest/gold/br_gh377-vlog95.gold new file mode 100644 index 000000000..fbb055fad --- /dev/null +++ b/ivtest/gold/br_gh377-vlog95.gold @@ -0,0 +1,2 @@ +: error: invalid value specified for defparam: test.name +: error: invalid value specified for defparam: test.name diff --git a/ivtest/gold/br_gh377.gold b/ivtest/gold/br_gh377.gold new file mode 100644 index 000000000..d730fc109 --- /dev/null +++ b/ivtest/gold/br_gh377.gold @@ -0,0 +1 @@ +: error: invalid value specified for defparam: test.name diff --git a/ivtest/gold/br_gh383a.gold b/ivtest/gold/br_gh383a.gold new file mode 100644 index 000000000..766396a01 --- /dev/null +++ b/ivtest/gold/br_gh383a.gold @@ -0,0 +1,3 @@ + 1 2 3 4 + 4 3 2 1 + 8 7 6 5 diff --git a/ivtest/gold/br_gh383b.gold b/ivtest/gold/br_gh383b.gold new file mode 100644 index 000000000..766396a01 --- /dev/null +++ b/ivtest/gold/br_gh383b.gold @@ -0,0 +1,3 @@ + 1 2 3 4 + 4 3 2 1 + 8 7 6 5 diff --git a/ivtest/gold/br_gh383c.gold b/ivtest/gold/br_gh383c.gold new file mode 100644 index 000000000..a64e6e3a8 --- /dev/null +++ b/ivtest/gold/br_gh383c.gold @@ -0,0 +1,3 @@ +a b c d +d c b a +h g f e diff --git a/ivtest/gold/br_gh383d-ivl.gold b/ivtest/gold/br_gh383d-ivl.gold new file mode 100644 index 000000000..e7e6bcfc1 --- /dev/null +++ b/ivtest/gold/br_gh383d-ivl.gold @@ -0,0 +1,3 @@ +1.00000 2.00000 3.00000 4.00000 +4.00000 3.00000 2.00000 1.00000 +8.00000 7.00000 6.00000 5.00000 diff --git a/ivtest/gold/br_gh383d.gold b/ivtest/gold/br_gh383d.gold new file mode 100644 index 000000000..b08356e0b --- /dev/null +++ b/ivtest/gold/br_gh383d.gold @@ -0,0 +1,3 @@ +1 2 3 4 +4 3 2 1 +8 7 6 5 diff --git a/ivtest/gold/br_gh388.gold b/ivtest/gold/br_gh388.gold new file mode 100644 index 000000000..8270b371d --- /dev/null +++ b/ivtest/gold/br_gh388.gold @@ -0,0 +1,5 @@ +new uvm_object +new uvm_object +new uvm_report_object +u_0 +r_0 diff --git a/ivtest/gold/br_gh390b.gold b/ivtest/gold/br_gh390b.gold new file mode 100644 index 000000000..fab6928a5 --- /dev/null +++ b/ivtest/gold/br_gh390b.gold @@ -0,0 +1,5 @@ +Hello World +uvm_object::new(uvm_object) +uvm_object::Print: m_name=uvm_object +uvm_object::new(uvm_report_object) +uvm_object::Print: m_name=uvm_report_object diff --git a/ivtest/gold/br_gh391.gold b/ivtest/gold/br_gh391.gold new file mode 100644 index 000000000..2bd8ea639 --- /dev/null +++ b/ivtest/gold/br_gh391.gold @@ -0,0 +1,2 @@ +building +running diff --git a/ivtest/gold/br_gh433.gold b/ivtest/gold/br_gh433.gold new file mode 100644 index 000000000..f5df77e10 --- /dev/null +++ b/ivtest/gold/br_gh433.gold @@ -0,0 +1,4 @@ +./ivltests/br_gh433.v:8: warning: method function 'pop_back' is being called as a task. +./ivltests/br_gh433.v:16: warning: method function 'pop_front' is being called as a task. +./ivltests/br_gh433.v:22: warning: method function 'size' is being called as a task. +PASSED diff --git a/ivtest/gold/br_gh436.gold b/ivtest/gold/br_gh436.gold new file mode 100644 index 000000000..75fad0721 --- /dev/null +++ b/ivtest/gold/br_gh436.gold @@ -0,0 +1,6 @@ +m_argv[0] = str0 +LARGE: 4 +LARGE: 4 (2) +m_argv[1] = str1 +LARGE: 4 +LARGE: 4 (2) diff --git a/ivtest/gold/br_gh440-v11.gold b/ivtest/gold/br_gh440-v11.gold new file mode 100644 index 000000000..6363e0102 --- /dev/null +++ b/ivtest/gold/br_gh440-v11.gold @@ -0,0 +1,7 @@ +./ivltests/br_gh440.v:44: error: Class/null is not allowed with the '|' operator. +./ivltests/br_gh440.v:45: error: Class/null is not allowed with the '<<(<)' operator. +./ivltests/br_gh440.v:46: error: Class/null is not allowed with the '<<(<)' operator. +./ivltests/br_gh440.v:48: error: Class/null is not allowed with the '<=' operator. +./ivltests/br_gh440.v:49: error: Class/null is not allowed with the '<=' operator. +./ivltests/br_gh440.v:50: error: Class/null is not allowed with the '!' operator. +6 error(s) during elaboration. diff --git a/ivtest/gold/br_gh440.gold b/ivtest/gold/br_gh440.gold new file mode 100644 index 000000000..771009f7e --- /dev/null +++ b/ivtest/gold/br_gh440.gold @@ -0,0 +1,13 @@ +./ivltests/br_gh440.v:4: Error: Class/null r-value not allowed in this context. +./ivltests/br_gh440.v:30: Error: Class/null r-value not allowed in this context. +./ivltests/br_gh440.v:43: error: Both arguments (logic, class) must be class/null for '==' operator. +./ivltests/br_gh440.v:44: error: Class/null is not allowed with the '|' operator. +./ivltests/br_gh440.v:45: error: Class/null is not allowed with the '<<(<)' operator. +./ivltests/br_gh440.v:46: error: Class/null is not allowed with the '<<(<)' operator. +./ivltests/br_gh440.v:46: Error: Class/null r-value not allowed in this context. +./ivltests/br_gh440.v:48: error: Class/null is not allowed with the '<=' operator. +./ivltests/br_gh440.v:49: error: Class/null is not allowed with the '<=' operator. +./ivltests/br_gh440.v:50: error: Class/null is not allowed with the '!' operator. +./ivltests/br_gh440.v:51: Error: Class/null r-value not allowed in this context. +./ivltests/br_gh440.v:52: Error: Class/null r-value not allowed in this context. +12 error(s) during elaboration. diff --git a/ivtest/gold/br_gh451.gold b/ivtest/gold/br_gh451.gold new file mode 100644 index 000000000..c0085aebb --- /dev/null +++ b/ivtest/gold/br_gh451.gold @@ -0,0 +1,3 @@ +foo=4 +bar=2 +math=8 diff --git a/ivtest/gold/br_gh497b.gold b/ivtest/gold/br_gh497b.gold new file mode 100644 index 000000000..c1ef5f520 --- /dev/null +++ b/ivtest/gold/br_gh497b.gold @@ -0,0 +1,13 @@ +./ivltests/br_gh497b.v:12: error: Part-select [-2+:2] exceeds the declared bounds for array1. +./ivltests/br_gh497b.v:15: error: Part-select [4+:2] exceeds the declared bounds for array1. +./ivltests/br_gh497b.v:17: error: Part-select [-1+:2] exceeds the declared bounds for array1. +./ivltests/br_gh497b.v:19: error: Part-select [3+:2] exceeds the declared bounds for array2. +./ivltests/br_gh497b.v:21: error: Part-select [-1-:2] exceeds the declared bounds for array3. +./ivltests/br_gh497b.v:24: error: Part-select [5-:2] exceeds the declared bounds for array3. +./ivltests/br_gh497b.v:26: error: Part-select [0-:2] exceeds the declared bounds for array4. +./ivltests/br_gh497b.v:28: error: Part-select [4-:2] exceeds the declared bounds for array4. +./ivltests/br_gh497b.v:30: error: Part-select [-1:-2] exceeds the declared bounds for array5. +./ivltests/br_gh497b.v:33: error: Part-select [5:4] exceeds the declared bounds for array5. +./ivltests/br_gh497b.v:35: error: Part-select [0:-1] exceeds the declared bounds for array6. +./ivltests/br_gh497b.v:37: error: Part-select [4:3] exceeds the declared bounds for array6. +12 error(s) during elaboration. diff --git a/ivtest/gold/br_gh497d.gold b/ivtest/gold/br_gh497d.gold new file mode 100644 index 000000000..9430e0d65 --- /dev/null +++ b/ivtest/gold/br_gh497d.gold @@ -0,0 +1,13 @@ +./ivltests/br_gh497d.v:16: error: Part-select [-2+:2] exceeds the declared bounds for array1. +./ivltests/br_gh497d.v:19: error: Part-select [4+:2] exceeds the declared bounds for array1. +./ivltests/br_gh497d.v:21: error: Part-select [-1+:2] exceeds the declared bounds for array1. +./ivltests/br_gh497d.v:23: error: Part-select [3+:2] exceeds the declared bounds for array2. +./ivltests/br_gh497d.v:25: error: Part-select [-1-:2] exceeds the declared bounds for array3. +./ivltests/br_gh497d.v:28: error: Part-select [5-:2] exceeds the declared bounds for array3. +./ivltests/br_gh497d.v:30: error: Part-select [0-:2] exceeds the declared bounds for array4. +./ivltests/br_gh497d.v:32: error: Part-select [4-:2] exceeds the declared bounds for array4. +./ivltests/br_gh497d.v:34: error: Part-select [-1:-2] exceeds the declared bounds for array5. +./ivltests/br_gh497d.v:37: error: Part-select [5:4] exceeds the declared bounds for array5. +./ivltests/br_gh497d.v:39: error: Part-select [0:-1] exceeds the declared bounds for array6. +./ivltests/br_gh497d.v:41: error: Part-select [4:3] exceeds the declared bounds for array6. +12 error(s) during elaboration. diff --git a/ivtest/gold/br_gh497f.gold b/ivtest/gold/br_gh497f.gold new file mode 100644 index 000000000..ac0be76ed --- /dev/null +++ b/ivtest/gold/br_gh497f.gold @@ -0,0 +1,37 @@ +./ivltests/br_gh497f.v:12: error: Part-select [-2+:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:12: error: Part-select [-2+:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:12: error: Unable to elaborate condition expression. +./ivltests/br_gh497f.v:13: error: Part-select [-1+:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:13: error: Part-select [-1+:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:13: error: Unable to elaborate condition expression. +./ivltests/br_gh497f.v:17: error: Part-select [3+:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:17: error: Part-select [3+:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:17: error: Unable to elaborate condition expression. +./ivltests/br_gh497f.v:18: error: Part-select [4+:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:18: error: Part-select [4+:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:18: error: Unable to elaborate condition expression. +./ivltests/br_gh497f.v:20: error: Part-select [-1-:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:20: error: Part-select [-1-:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:20: error: Unable to elaborate condition expression. +./ivltests/br_gh497f.v:21: error: Part-select [0-:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:21: error: Part-select [0-:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:21: error: Unable to elaborate condition expression. +./ivltests/br_gh497f.v:25: error: Part-select [4-:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:25: error: Part-select [4-:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:25: error: Unable to elaborate condition expression. +./ivltests/br_gh497f.v:26: error: Part-select [5-:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:26: error: Part-select [5-:2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:26: error: Unable to elaborate condition expression. +./ivltests/br_gh497f.v:28: error: Part-select [-1:-2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:28: error: Part-select [-1:-2] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:28: error: Unable to elaborate condition expression. +./ivltests/br_gh497f.v:29: error: Part-select [0:-1] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:29: error: Part-select [0:-1] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:29: error: Unable to elaborate condition expression. +./ivltests/br_gh497f.v:33: error: Part-select [4:3] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:33: error: Part-select [4:3] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:33: error: Unable to elaborate condition expression. +./ivltests/br_gh497f.v:34: error: Part-select [5:4] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:34: error: Part-select [5:4] exceeds the declared bounds for array. +./ivltests/br_gh497f.v:34: error: Unable to elaborate condition expression. +36 error(s) during elaboration. diff --git a/ivtest/gold/br_gh531.gold b/ivtest/gold/br_gh531.gold new file mode 100644 index 000000000..a7feb3df2 --- /dev/null +++ b/ivtest/gold/br_gh531.gold @@ -0,0 +1,6 @@ +C1 01 +C2 x01x +C3 01 +C4 x01x +C5 01 +C6 x01x diff --git a/ivtest/gold/br_gh567.gold b/ivtest/gold/br_gh567.gold new file mode 100644 index 000000000..029e18e58 --- /dev/null +++ b/ivtest/gold/br_gh567.gold @@ -0,0 +1,7 @@ +./ivltests/br_gh567.v:7: warning: A negative value (-1) has been assigned to genvar 'i'. +./ivltests/br_gh567.v:7: : This is illegal in Verilog-2001. Use at least -g2005 to remove this warning. + 3 + 2 + 1 + 0 +PASSED diff --git a/ivtest/gold/br_gh62.gold b/ivtest/gold/br_gh62.gold new file mode 100644 index 000000000..b6b787515 --- /dev/null +++ b/ivtest/gold/br_gh62.gold @@ -0,0 +1,8 @@ +./ivltests/br_gh62.v:13: error: the number of indices (3) is greater than the number of dimensions (2). +./ivltests/br_gh62.v:14: error: the number of indices (3) is greater than the number of dimensions (2). +./ivltests/br_gh62.v:15: error: the number of indices (3) is greater than the number of dimensions (2). +./ivltests/br_gh62.v:16: error: the number of indices (2) is greater than the number of dimensions (1). +./ivltests/br_gh62.v:17: error: the number of indices (2) is greater than the number of dimensions (1). +./ivltests/br_gh62.v:18: error: the number of indices (2) is greater than the number of dimensions (1). +./ivltests/br_gh62.v:19: error: the number of indices (2) is greater than the number of dimensions (1). +7 error(s) during elaboration. diff --git a/ivtest/gold/br_gh72a.gold b/ivtest/gold/br_gh72a.gold new file mode 100644 index 000000000..0a90a988a --- /dev/null +++ b/ivtest/gold/br_gh72a.gold @@ -0,0 +1,9 @@ +d1 +1 +d1 d2 +1 d2 +1 2 +d1 d2 +1 d2 +1 2 +d1 2 diff --git a/ivtest/gold/br_gh72b.gold b/ivtest/gold/br_gh72b.gold new file mode 100644 index 000000000..85f57a368 --- /dev/null +++ b/ivtest/gold/br_gh72b.gold @@ -0,0 +1,2 @@ +1 +1 2 diff --git a/ivtest/gold/br_gh72b_fail.gold b/ivtest/gold/br_gh72b_fail.gold new file mode 100644 index 000000000..57f44c49c --- /dev/null +++ b/ivtest/gold/br_gh72b_fail.gold @@ -0,0 +1,6 @@ +./ivltests/br_gh72b_fail.v:5: error: too many arguments for `macro1 +./ivltests/br_gh72b_fail.v:6: error: too many arguments for `macro1 +./ivltests/br_gh72b_fail.v:8: error: too few arguments for `macro2 +./ivltests/br_gh72b_fail.v:9: error: too few arguments for `macro2 +./ivltests/br_gh72b_fail.v:10: error: too many arguments for `macro2 +Preprocessor failed with 5 errors. diff --git a/ivtest/gold/br_gh79.gold b/ivtest/gold/br_gh79.gold new file mode 100644 index 000000000..8f510dc1c --- /dev/null +++ b/ivtest/gold/br_gh79.gold @@ -0,0 +1,16 @@ +./ivltests/br_gh79.v:6: syntax error +./ivltests/br_gh79.v:6: error: malformed statement +./ivltests/br_gh79.v:7: syntax error +./ivltests/br_gh79.v:7: error: malformed statement +./ivltests/br_gh79.v:9: syntax error +./ivltests/br_gh79.v:9: error: malformed statement +./ivltests/br_gh79.v:10: syntax error +./ivltests/br_gh79.v:10: error: malformed statement +./ivltests/br_gh79.v:12: syntax error +./ivltests/br_gh79.v:12: error: malformed statement +./ivltests/br_gh79.v:13: syntax error +./ivltests/br_gh79.v:13: error: malformed statement +./ivltests/br_gh79.v:15: syntax error +./ivltests/br_gh79.v:15: error: malformed statement +./ivltests/br_gh79.v:16: syntax error +./ivltests/br_gh79.v:16: error: malformed statement diff --git a/ivtest/gold/br_ml20190814.gold b/ivtest/gold/br_ml20190814.gold new file mode 100644 index 000000000..e69de29bb diff --git a/ivtest/gold/br_ml_20150315.gold b/ivtest/gold/br_ml_20150315.gold new file mode 100644 index 000000000..59a2a898d --- /dev/null +++ b/ivtest/gold/br_ml_20150315.gold @@ -0,0 +1 @@ +At time 1, field 1 = 1, field 2 = 2 diff --git a/ivtest/gold/busbug.gold b/ivtest/gold/busbug.gold new file mode 100644 index 000000000..1c147c091 --- /dev/null +++ b/ivtest/gold/busbug.gold @@ -0,0 +1 @@ +01=01 diff --git a/ivtest/gold/ca_64delay.gold b/ivtest/gold/ca_64delay.gold new file mode 100644 index 000000000..6d946ec1e --- /dev/null +++ b/ivtest/gold/ca_64delay.gold @@ -0,0 +1,10 @@ +dl:ls32b- 1 ps +rl:ls32b- 1 ps +rg:ls32b- 2 ps +ar:ls32b- 3 ps +ps:ls32b- 4 ps +dl:gt32b- 1000000000000 ps +rl:gt32b- 1000000000000 ps +rg:gt32b- 2000000000000 ps +ar:gt32b- 3000000000000 ps +ps:gt32b- 4000000000000 ps diff --git a/ivtest/gold/ca_mult.gold b/ivtest/gold/ca_mult.gold new file mode 100644 index 000000000..7c1bc11e8 --- /dev/null +++ b/ivtest/gold/ca_mult.gold @@ -0,0 +1,3 @@ + -2 -1.00000 + 0 0.00000 + 2 1.00000 diff --git a/ivtest/gold/ca_time.gold b/ivtest/gold/ca_time.gold new file mode 100644 index 000000000..673bf3f28 --- /dev/null +++ b/ivtest/gold/ca_time.gold @@ -0,0 +1,5 @@ + 0 0 + 1 1 + 0 0 + 3 3 + 0 0 diff --git a/ivtest/gold/ca_time_real-ivl.gold b/ivtest/gold/ca_time_real-ivl.gold new file mode 100644 index 000000000..50d89b99f --- /dev/null +++ b/ivtest/gold/ca_time_real-ivl.gold @@ -0,0 +1,5 @@ +0.00000 +1.00000 +0.00000 +3.00000 +0.00000 diff --git a/ivtest/gold/ca_time_real.gold b/ivtest/gold/ca_time_real.gold new file mode 100644 index 000000000..cd9f8cd4a --- /dev/null +++ b/ivtest/gold/ca_time_real.gold @@ -0,0 +1,5 @@ +0 +1 +0 +3 +0 diff --git a/ivtest/gold/ca_time_smtm.gold b/ivtest/gold/ca_time_smtm.gold new file mode 100644 index 000000000..cca1fd0ad --- /dev/null +++ b/ivtest/gold/ca_time_smtm.gold @@ -0,0 +1,5 @@ + 0 + 1 + 0 + 3 + 0 diff --git a/ivtest/gold/case_priority-vlog95.gold b/ivtest/gold/case_priority-vlog95.gold new file mode 100644 index 000000000..05926a9e4 --- /dev/null +++ b/ivtest/gold/case_priority-vlog95.gold @@ -0,0 +1,4 @@ +case 0 +case 1 +case 3 +PASSED diff --git a/ivtest/gold/case_priority.gold b/ivtest/gold/case_priority.gold new file mode 100644 index 000000000..e8aab45fc --- /dev/null +++ b/ivtest/gold/case_priority.gold @@ -0,0 +1,6 @@ +case 0 +case 1 +WARNING: ./ivltests/case_priority.v:12: value is unhandled for priority or unique case statement + Time: 50000 Scope: main +case 3 +PASSED diff --git a/ivtest/gold/case_unique-vlog95.gold b/ivtest/gold/case_unique-vlog95.gold new file mode 100644 index 000000000..05926a9e4 --- /dev/null +++ b/ivtest/gold/case_unique-vlog95.gold @@ -0,0 +1,4 @@ +case 0 +case 1 +case 3 +PASSED diff --git a/ivtest/gold/case_unique.gold b/ivtest/gold/case_unique.gold new file mode 100644 index 000000000..6eeca32f1 --- /dev/null +++ b/ivtest/gold/case_unique.gold @@ -0,0 +1,7 @@ +./ivltests/case_unique.v:12: vvp.tgt sorry: Case unique/unique0 qualities are ignored. +case 0 +case 1 +WARNING: ./ivltests/case_unique.v:12: value is unhandled for priority or unique case statement + Time: 50000 Scope: main +case 3 +PASSED diff --git a/ivtest/gold/casesynth7.gold b/ivtest/gold/casesynth7.gold new file mode 100644 index 000000000..01097fe12 --- /dev/null +++ b/ivtest/gold/casesynth7.gold @@ -0,0 +1,3 @@ +./ivltests/casesynth7.v:17: warning: A latch has been inferred for 'o'. +./ivltests/casesynth7.v:17: warning: The latch enable is connected to a synthesized expression. The latch may be sensitive to glitches. +PASSED diff --git a/ivtest/gold/cmos.gold b/ivtest/gold/cmos.gold new file mode 100644 index 000000000..3056d56cc --- /dev/null +++ b/ivtest/gold/cmos.gold @@ -0,0 +1,24 @@ +zz HiZ HiZ 0 0 1 +00 St0 St0 0 1 0 +00 St0 St0 0 1 1 +00 St0 St0 0 0 0 +00 St0 St0 0 x 0 +00 St0 St0 0 1 x +xx StL StL 0 x 1 +xx StL StL 0 0 x +xx StL StL 0 x x +zz HiZ HiZ 1 0 1 +11 St1 St1 1 1 0 +11 St1 St1 1 1 1 +11 St1 St1 1 0 0 +11 St1 St1 1 x 0 +11 St1 St1 1 1 x +xx StH StH 1 x 1 +xx StH StH 1 0 x +xx StH StH 1 x x +zz HiZ HiZ x 0 1 +xx StX StX x 1 0 +xx StX StX x x x +zz HiZ HiZ z 0 1 +zz HiZ HiZ z 1 0 +zz HiZ HiZ z x x diff --git a/ivtest/gold/comp1000.gold b/ivtest/gold/comp1000.gold new file mode 100644 index 000000000..eb2cc9044 --- /dev/null +++ b/ivtest/gold/comp1000.gold @@ -0,0 +1,255 @@ +r0 = 0011110100100100 +r1 = 0000000000000000000000000 +r2 = 0000000000000000000000000100 +r3 = 1011 +r4 = 0000000100000100010101 +r5 = 0000000000000000000000000000000 +r6 = 00 +r7 = xxxxxxxxxxxxxxxxxxxxxx +r8 = 0000000000000000x +r9 = 00000000000000001 +r10 = 01010110011 +r11 = 000000000000000000000111101001 +r12 = 111111111111111111111111111100 +r13 = 0000000000000011111101101111 +r14 = 000100101 +r15 = 000000000000 +r16 = 1100110 +r17 = 000000000000010100001011 +r18 = 0000000000000000001111110011 +r19 = 00000000000000000111111110111111 +r20 = 1 +r21 = 000000000 +r22 = 000000000000000 +r23 = 0101 +r24 = 1010010001000 +r25 = 00000000000000000000100101010110 +r26 = 00000000000000000000000001 +r27 = 000000000000001 +r28 = 00000000000000110010010100 +r29 = 0000000000000x0xx00xx0xx0 +r30 = 00000000000000000000000000000000 +r31 = 10 +r32 = 0000000000000000000000000000000 +r33 = 0000000000000100010101110110 +r34 = xxxxxxxxxxxxxxxxx +r35 = 1100101001100 +r36 = 0001 +r37 = 000000000000000000000000000000 +r38 = 0011100 +r39 = 111101001 +r40 = 000000000110110010111011 +r41 = 00000000000000000100100000100101 +r42 = 10111000111 +r43 = 0000000000000000000000000000x +r44 = 00000000000000000000000000 +r45 = 0000000000001 +r46 = 000000000000001 +r47 = 000000000000100101111111111 +r48 = 000100001000001001 +r49 = 000000000000000000000000000001 +r50 = 0000111010100000010 +r51 = 00 +r52 = 00000000000011000101100 +r53 = 000000000110011001010000 +r54 = 111 +r55 = 0000000000000000000000000001 +r56 = 101111011 +r57 = 1111111111 +r58 = 00000000000000000000x +r59 = 00000000000000000000101111000010 +r60 = 0000000000000000000001 +r61 = 00000000000000001 +r62 = 0010010101011 +r63 = 000000000000001 +r64 = 00000000100110111110000 +r65 = 0000000100110001001110 +r66 = 000000000000100000011010010 +r67 = 000000000111010100010110 +r68 = 000000001010010110 +r69 = 000000000001 +r70 = 0000000000011101111000000 +r71 = 0000000110110010110101 +r72 = 000000000110110011111111 +r73 = 000000101111100000000 +r74 = 0100100100011001 +r75 = 100111011001010 +r76 = 011110 +r77 = 00000000000000000000000000000 +r78 = 000100011001100001 +r79 = 000000110111111110101 +r80 = 000000 +r81 = 000000000000000001000101100 +r82 = 0000000000000000100000000010000 +r83 = 0100100 +r84 = 10110010010010 +r85 = 000000011110110110110 +r86 = xxx +r87 = 111011111111111 +r88 = 00000000000000100011110110000 +r89 = 00000000000000000000000000 +r90 = 00000000000000000000 +r91 = 100 +r92 = 011 +r93 = 10111001 +r94 = 0000000101111100000000 +r95 = 110111 +r96 = 000000000000000000000011 +r97 = 000001 +r98 = 0000000000110001110100010 +r99 = 0111011 +r100 = x +r101 = 000000001 +r102 = 000000000000000000000001 +r103 = 000000000000000000000000000000 +r104 = 00000101010101010 +r105 = 00000000000000001 +r106 = 0000000000000000000000000 +r107 = 00000000000000000000 +r108 = 0010 +r109 = 00000010000 +r110 = 000000000000000000 +r111 = 00000010110101010010100000 +r112 = 000 +r113 = 011111011010010 +r114 = 00000000000000000101110010110111 +r115 = 111111110101100 +r116 = 00011 +r117 = 1 +r118 = 0000000000000000 +r119 = 0000000000000011101101101000 +r120 = 0110001101 +r121 = 000000010110111011 +r122 = 000000000110001011101100 +r123 = xxxxxxxxxxxxxxxxxxxxxxxxxx +r124 = 0 +r125 = 000000000000000001011110000111 +r126 = 0000000000000000000000010101 +r127 = 10110110 +r128 = 0 +r129 = 0100110011000 +r130 = 000000000001 +r131 = 000000000011111101010101 +r132 = 00000000000000000 +r133 = 000000000000000000001 +r134 = 000 +r135 = 1 +r136 = 00 +r137 = 00000100100100100110 +r138 = 0000000x +r139 = 110011101110 +r140 = 000000000000001001 +r141 = 000000000100110111110000 +r142 = 11100111001000 +r143 = 0100010101 +r144 = 101001111 +r145 = 0000000000000000000000001 +r146 = 0000000001110000000111 +r147 = 0000000000111010100000010 +r148 = 00000000000000000000000000001 +r149 = 0000000000000000000000000000 +r150 = 000000000 +r151 = 00010 +r152 = 0000000000000000 +r153 = 0000000000000001 +r154 = 0 +r155 = 100 +r156 = 000110111001010 +r157 = 000000000000000000 +r158 = 0000000000000000000000000000000 +r159 = 000000111100010000111 +r160 = 0000000100000000010 +r161 = 00001000011 +r162 = 00000000000000000001 +r163 = 00000000000 +r164 = 10 +r165 = 111001100001000 +r166 = 000000000000000000000000000 +r167 = 0000000000000000001000001110000 +r168 = 001011001101 +r169 = 000000000000000000000000000000 +r170 = 000000000000000000000000000 +r171 = 0000000001100101010010 +r172 = 00000000000000001 +r173 = 0010 +r174 = 00000001 +r175 = 0100 +r176 = 00000000110110010110101 +r177 = 000000000000001100001111101 +r178 = 00000000000000000000000000000100 +r179 = 111010 +r180 = 0000000011011111111011 +r181 = 000000 +r182 = 0101100101111110 +r183 = 11111110 +r184 = 000000000000000 +r185 = 000000000000000000001 +r186 = 00000000000000 +r187 = 000000000000000000000000000000 +r188 = 01101011110101 +r189 = 100010 +r190 = 000000000000000000000000000000x +r191 = 1000100000011 +r192 = 00000000000010 +r193 = 11111111111111111010111111111000 +r194 = 00000110100001100 +r195 = xx +r196 = 0000011000011000011 +r197 = 000000000000101000000001 +r198 = 00000000000000000000000000000000 +r199 = 00000000000100110010010 +r200 = 000000000000001 +r201 = 0000000000000x +r202 = 0000101100100100010 +r203 = 0000010111101100001 +r204 = 00000000000000000101110001000100 +r205 = 000000000000000 +r206 = 000000000000000000000000000001 +r207 = 000000010 +r208 = 000000000000001 +r209 = 000000000000000000x +r210 = 1111111111111111111111111111111 +r211 = 0000000101010011000100 +r212 = 0000000000000000 +r213 = 000000000000000000000000000000 +r214 = xxx +r215 = 11101 +r216 = 000001 +r217 = 0 +r218 = 1 +r219 = 0111010010001 +r220 = 000000000000000000000000000001 +r221 = 000000000000000000000001 +r222 = 000000000000000000000110001 +r223 = 000000001100010 +r224 = 00000000000000000 +r225 = 01111001010 +r226 = 00 +r227 = 00000000000000000000000000x +r228 = 01011 +r229 = 1111111111110011 +r230 = 00000000000000000 +r231 = 1111110010 +r232 = 10011011000 +r233 = 11100 +r234 = 0000000000000000 +r235 = 001 +r236 = 00000000000000000000000000000000 +r237 = 000000000000000011101011 +r238 = 0000000000000000 +r239 = 0000000000000000000000000 +r240 = 10110111100101 +r241 = 01 +r242 = 0000000000000000001 +r243 = 011101011 +r244 = 00100100100 +r245 = 00000 +r246 = 100 +r247 = 000000000000000100110001001110 +r248 = 0000000001101011110101 +r249 = 0000000000000000001 +r250 = 000000000011100101101010 +r251 = 10001010101110 +r252 = 0000000000000000000000000000000 +r253 = 000000001 +r254 = 00000100110101100110 diff --git a/ivtest/gold/comp1001.gold b/ivtest/gold/comp1001.gold new file mode 100644 index 000000000..3d7d802c4 --- /dev/null +++ b/ivtest/gold/comp1001.gold @@ -0,0 +1,255 @@ +r0 = 0000010111011101100 +r1 = 00000000000000000001010110000100 +r2 = 000000000100011111100101 +r3 = 11 +r4 = 00000000000000000x +r5 = 000000000011101001 +r6 = 1 +r7 = 00111010011 +r8 = 00000000000000000000000 +r9 = 000000000000000001 +r10 = 000000000000000101010111011111 +r11 = 1111111111111111111101 +r12 = 10101011 +r13 = 10101011 +r14 = 0000000000000000000 +r15 = 00000000000000000000000001 +r16 = 00000 +r17 = 0000000000000000000000000 +r18 = 00 +r19 = 1011010001 +r20 = 0000000110000 +r21 = 111100 +r22 = 0100 +r23 = 000000000000000000001 +r24 = 00000000000000000000000001 +r25 = 011100110010 +r26 = xxxxxxxxxxxxxxxxxxxx +r27 = 000000 +r28 = 11 +r29 = 110 +r30 = 011 +r31 = xxx +r32 = 00000000111011010100111 +r33 = 0 +r34 = 11 +r35 = 010000100001010 +r36 = 000000 +r37 = 0000000110100101101001 +r38 = 000000000000000000100010111011 +r39 = 0010111101 +r40 = 00000000000000110001000010 +r41 = 000000000000000 +r42 = 00000000000000000111100010101 +r43 = xxxxxxxxxxxxxx +r44 = 000000000000000000000001 +r45 = 0000000000000000000001 +r46 = 0010 +r47 = 111111111111111110 +r48 = 00 +r49 = 00000000000001 +r50 = 0000000000000000000 +r51 = 000000001 +r52 = 0000000101001111010100 +r53 = 0000000000000001100100111 +r54 = 00010 +r55 = 01 +r56 = 00001110011010 +r57 = 00000000000000000001 +r58 = 000000000000000000 +r59 = 01100100 +r60 = 00000000000000000110100110010110 +r61 = 000000000010111101000000 +r62 = 000111110011000 +r63 = 1 +r64 = 11111111111111101111011001101 +r65 = 000000000000000000000000x +r66 = xxxxxxxxxx +r67 = 0000000000000001 +r68 = 00000000000000000001 +r69 = 000000001 +r70 = 00000000000000001 +r71 = 000000101001000011111 +r72 = 00000000000001 +r73 = 00000000000000000001 +r74 = 1001100100 +r75 = 0000000000 +r76 = 000000000000000001 +r77 = 001 +r78 = 000000000000000000000010000 +r79 = 000000 +r80 = 0 +r81 = xxxxxxxxxxxxxxxxxxxxxxxxxx +r82 = 1 +r83 = 0000000000000000000000000000 +r84 = 000000000000011110011110 +r85 = 0000000000000000000000000001 +r86 = 000000000000000000000000001 +r87 = 000000000000000000000000000 +r88 = 0000000000000000001 +r89 = 11000 +r90 = 000000000000000010101001001111 +r91 = 00110111010110 +r92 = 110000 +r93 = 1100011111000 +r94 = 00000000000000000000000000000001 +r95 = 000000000000111010100100000 +r96 = 11100 +r97 = 0000000000 +r98 = 0100100110101110 +r99 = 1111x +r100 = 000000000000000000000000001 +r101 = 011011101101 +r102 = 00000000000000000000000000 +r103 = 000000000000 +r104 = 0xxxxxxxxxxxxxxxxxxx +r105 = 00000000000000000100011001111001 +r106 = 00101 +r107 = 0000001001 +r108 = 0000000111010010001010 +r109 = 110000101111001 +r110 = 00000000001010110010011 +r111 = 0000000000101110111000 +r112 = 1 +r113 = 0000000000000000110110000100111 +r114 = 11001100110001 +r115 = 100 +r116 = 000000000010000010110 +r117 = 010001000010011 +r118 = 000011 +r119 = 00000000000000000000100010101100 +r120 = 1110100011 +r121 = 00000000000000011100000100111 +r122 = 000000000100011011011101 +r123 = 00000000100001101001100 +r124 = 00000000110010010010111 +r125 = 0x +r126 = 00000000101110110110001 +r127 = 0100111010110111 +r128 = 00011001111001 +r129 = 000000000000000000 +r130 = 0000001001000010110 +r131 = 00000000001100 +r132 = 0000000000000001111101100010 +r133 = 000000000000000000000001100111 +r134 = 000000000000000000000000 +r135 = 01100011111110 +r136 = 001001111111 +r137 = 00000010110110111110 +r138 = 00000000000001 +r139 = 0000000000001 +r140 = 000 +r141 = 0000000000000000001100110111 +r142 = 0000000000110011101101100 +r143 = 0 +r144 = 000 +r145 = 000000000000000011110001100 +r146 = 000000000000000000000000 +r147 = 00000000000000111100111001110 +r148 = 0011111100 +r149 = 00011011001000011 +r150 = 11001000 +r151 = 0000000000000001 +r152 = 0000001101011100110 +r153 = 00000000000000111010100100000 +r154 = 00000000000000000011110000001010 +r155 = 0000 +r156 = 00011000111100011 +r157 = 0000000000000000000001 +r158 = 00000000000000000001 +r159 = 1 +r160 = 000000000000000000000000x +r161 = 000000000000000000 +r162 = 00000000000000000001 +r163 = 0101111101 +r164 = 00000000000000000000001 +r165 = 1 +r166 = 0000000000001 +r167 = 00000000000000010110110100101 +r168 = 0000000000000000000000 +r169 = 0001000111101010 +r170 = 00100 +r171 = 00000110110101000100 +r172 = 00000000000000000000000000 +r173 = 01001011 +r174 = 0 +r175 = 01101000 +r176 = 0000010 +r177 = 00111000010000 +r178 = 00000000000000000000000000000000 +r179 = 00000000111 +r180 = 00000000000000000000000001 +r181 = 0001 +r182 = 0000000000000000000000000000000 +r183 = 000000000001 +r184 = 0000000000000 +r185 = 00110 +r186 = 00000001110111001100x +r187 = 000000011110011101010 +r188 = 0000000000000000000001 +r189 = 0011111001 +r190 = 00000000000000000000xxx +r191 = 00000010101111 +r192 = 111001 +r193 = 000000000 +r194 = 0000100010110000001 +r195 = 00000000000000010000010101 +r196 = 000000000001 +r197 = xxxxxxxxxxxxxxxxxxx +r198 = 00000000000000000000001 +r199 = 0000000101010111110001 +r200 = 00000001111101001 +r201 = 0000000011011110100 +r202 = 000000000 +r203 = 0000000000000000000010111010010 +r204 = 000000000000000000000000001 +r205 = 00000000000000000000 +r206 = 00100110101110 +r207 = 01001001000 +r208 = 0000000000001 +r209 = 00000000000001011110100011 +r210 = 011011 +r211 = 0100110101110 +r212 = 1001 +r213 = 000001 +r214 = 000000000000 +r215 = 00000000000000000000 +r216 = 0000000000110100101000011 +r217 = xxxxxxxxxxxxxxxxxxxx +r218 = 000000000011110110010010 +r219 = 0000010110 +r220 = 0110 +r221 = 000000000000000000000000000000 +r222 = 000000000000000000000000000000x +r223 = 00000000000110101010010 +r224 = 00000011101110110111 +r225 = 0000000000000111100101000 +r226 = 0001000000000100 +r227 = 000000000000000000000000001010 +r228 = 00000000000000000010101010 +r229 = 000000000000000000000 +r230 = 0000000000111101111000 +r231 = 0000000000000000000000000000 +r232 = 000000000000000000000000000000 +r233 = 0000000000000000000101100001110 +r234 = 000000000000100011011011101 +r235 = 00000000000000 +r236 = 110100 +r237 = 00000000000000000000000000000000 +r238 = 0 +r239 = 1101111100 +r240 = 00000101110101110111 +r241 = 00000000000000000110111010100 +r242 = 001111100 +r243 = 001 +r244 = 0000000 +r245 = 00000000000101010110100 +r246 = 000000000000001 +r247 = 0000001 +r248 = 00000000000000000000001 +r249 = 10000111010 +r250 = 101110111 +r251 = 001 +r252 = 000000000000101111101101000 +r253 = 000110010010011110 +r254 = 0000011111011 diff --git a/ivtest/gold/dcomp1.gold b/ivtest/gold/dcomp1.gold new file mode 100644 index 000000000..1e2974985 --- /dev/null +++ b/ivtest/gold/dcomp1.gold @@ -0,0 +1,61 @@ +0 x 0 4 0 +got here +0 0 0 4 4 +1 0 0 4 200 +got here +1 1 0 4 204 +0 1 0 4 400 +got here +0 0 0 4 404 +1 0 0 4 600 +got here +1 1 0 4 604 +0 1 0 4 800 +got here +0 0 0 4 804 +1 0 0 4 1000 +got here +1 1 0 4 1004 +0 1 0 4 1200 +got here +0 0 0 4 1204 +1 0 0 4 1400 +got here +1 1 0 4 1404 +0 1 0 4 1600 +got here +0 0 0 4 1604 +1 0 0 4 1800 +got here +1 1 0 4 1804 +0 1 13 17 2000 +got here +0 0 13 17 2017 +1 0 13 17 2200 +got here +1 1 13 17 2217 +0 1 13 17 2400 +got here +0 0 13 17 2417 +1 0 13 17 2600 +got here +1 1 13 17 2617 +0 1 13 17 2800 +got here +0 0 13 17 2817 +1 0 13 17 3000 +got here +1 1 13 17 3017 +0 1 13 17 3200 +got here +0 0 13 17 3217 +1 0 13 17 3400 +got here +1 1 13 17 3417 +0 1 13 17 3600 +got here +0 0 13 17 3617 +1 0 13 17 3800 +got here +1 1 13 17 3817 +0 1 13 17 4000 diff --git a/ivtest/gold/def_nettype_none.gold b/ivtest/gold/def_nettype_none.gold new file mode 100644 index 000000000..4e91195d3 --- /dev/null +++ b/ivtest/gold/def_nettype_none.gold @@ -0,0 +1,2 @@ +./ivltests/def_nettype_none.v:16: error: Net b is not defined in this context. +1 error(s) during elaboration. diff --git a/ivtest/gold/defparam2.gold b/ivtest/gold/defparam2.gold new file mode 100644 index 000000000..6eb9d98b6 --- /dev/null +++ b/ivtest/gold/defparam2.gold @@ -0,0 +1,5 @@ +main.xx.U[0]: number=0 +main.xx.U[1]: number=1 +main.xx.U[2]: number=2 +main.xx.U[3]: number=3 +main.xx.U[4]: number=4 diff --git a/ivtest/gold/defparam3.gold b/ivtest/gold/defparam3.gold new file mode 100644 index 000000000..3eb3fbe3a --- /dev/null +++ b/ivtest/gold/defparam3.gold @@ -0,0 +1,5 @@ +main.xx.sub[0].U: number=0 +main.xx.sub[1].U: number=1 +main.xx.sub[2].U: number=2 +main.xx.sub[3].U: number=3 +main.xx.sub[4].U: number=4 diff --git a/ivtest/gold/defparam4.gold b/ivtest/gold/defparam4.gold new file mode 100644 index 000000000..b7098b4a9 --- /dev/null +++ b/ivtest/gold/defparam4.gold @@ -0,0 +1,5 @@ +main.D.xx.sub[0].U: number=0 +main.D.xx.sub[1].U: number=1 +main.D.xx.sub[2].U: number=2 +main.D.xx.sub[3].U: number=3 +main.D.xx.sub[4].U: number=4 diff --git a/ivtest/gold/delay.gold b/ivtest/gold/delay.gold new file mode 100644 index 000000000..43aefaab2 --- /dev/null +++ b/ivtest/gold/delay.gold @@ -0,0 +1,12 @@ +time=510, cat1=1 +time=0052, cat2=1 +time=0053, cat3=1 +time=0054, cat4=1 +time=0055, foo1=1 +time=0056, foo2=1 +time=0057, foo3=1 +time=0058, foo4=1 +time=0059, bar1=1 +time=0059, bar2=1 +time=0059, bar3=1 +time=0059, bar4=1 diff --git a/ivtest/gold/delay_var.gold b/ivtest/gold/delay_var.gold new file mode 100644 index 000000000..e9c29e310 --- /dev/null +++ b/ivtest/gold/delay_var.gold @@ -0,0 +1,19 @@ +0.0 x x x x x x x x +Should be 1.0: 1.0 +1.0 1 x x x 1 x x x +Should be 1.001: 1.001 +Should be 1.1: 1.1 +1.1 1 1 x x 1 1 x x +Should be 1.2: 1.2 +1.2 1 1 1 x 1 1 1 x +Should be 1.3: 1.3 +1.3 1 1 1 1 1 1 1 1 +3.0 0 1 1 1 0 1 1 1 +3.1 0 0 1 1 0 0 1 1 +3.2 0 0 0 1 0 0 0 1 +3.3 0 0 0 0 0 0 0 0 +7.0 1 0 0 0 1 0 0 0 +7.1 1 1 0 0 1 1 0 0 +7.2 1 1 1 0 1 1 1 0 +Large delay: 18446744073709552.0 +18446744073709552.0 1 1 1 1 1 1 1 1 diff --git a/ivtest/gold/delayed_sfunc-ivl.gold b/ivtest/gold/delayed_sfunc-ivl.gold new file mode 100644 index 000000000..73c0a0da7 --- /dev/null +++ b/ivtest/gold/delayed_sfunc-ivl.gold @@ -0,0 +1,4 @@ +0 0.00000 x x 10 +1 0.00000 4 4 10 +5 0.00000 4 4 20 +6 0.00000 5 5 20 diff --git a/ivtest/gold/delayed_sfunc.gold b/ivtest/gold/delayed_sfunc.gold new file mode 100644 index 000000000..4d6a07d77 --- /dev/null +++ b/ivtest/gold/delayed_sfunc.gold @@ -0,0 +1,4 @@ +0 0 x x 10 +1 0 4 4 10 +5 0 4 4 20 +6 0 5 5 20 diff --git a/ivtest/gold/disblock2.gold b/ivtest/gold/disblock2.gold new file mode 100644 index 000000000..11f81af32 --- /dev/null +++ b/ivtest/gold/disblock2.gold @@ -0,0 +1,3 @@ +hello world, 'b1 +Byte enable is 'h1 +Byte enable is 'h0 diff --git a/ivtest/gold/disp_dec.gold b/ivtest/gold/disp_dec.gold new file mode 100644 index 000000000..8f932e16b --- /dev/null +++ b/ivtest/gold/disp_dec.gold @@ -0,0 +1,6 @@ +4'bxxxx = x +4'bzzxx = X +4'bzzzz = z +4'b00zz = Z +4'b0000 = 0 +4'b0011 = 3 diff --git a/ivtest/gold/disp_dec2.gold b/ivtest/gold/disp_dec2.gold new file mode 100644 index 000000000..cf97e653a --- /dev/null +++ b/ivtest/gold/disp_dec2.gold @@ -0,0 +1 @@ +-1 (should be -1) diff --git a/ivtest/gold/disp_leading_z.gold b/ivtest/gold/disp_leading_z.gold new file mode 100644 index 000000000..49b542977 --- /dev/null +++ b/ivtest/gold/disp_leading_z.gold @@ -0,0 +1,4 @@ +|0000000011| +|11| +|0000000000| +|0| diff --git a/ivtest/gold/disp_parm.gold b/ivtest/gold/disp_parm.gold new file mode 100644 index 000000000..b81aaa268 --- /dev/null +++ b/ivtest/gold/disp_parm.gold @@ -0,0 +1,2 @@ +decimal GEORGE: 5, HARRY: 10 +binary GEORGE: 'b101, HARRY: 'b1010 diff --git a/ivtest/gold/disp_part.gold b/ivtest/gold/disp_part.gold new file mode 100644 index 000000000..f07da8731 --- /dev/null +++ b/ivtest/gold/disp_part.gold @@ -0,0 +1,5 @@ +1001 +0100 +0010 +1001 +1100 diff --git a/ivtest/gold/display_bug.gold b/ivtest/gold/display_bug.gold new file mode 100644 index 000000000..ebc35e3f5 --- /dev/null +++ b/ivtest/gold/display_bug.gold @@ -0,0 +1,6 @@ +ab +a b +cd +c d +ab +a b diff --git a/ivtest/gold/drive_strength2.gold b/ivtest/gold/drive_strength2.gold new file mode 100644 index 000000000..5668da763 --- /dev/null +++ b/ivtest/gold/drive_strength2.gold @@ -0,0 +1,4 @@ +1 0 1 +0 0 1 +1 0 1 +0 0 1 diff --git a/ivtest/gold/dummy7.gold b/ivtest/gold/dummy7.gold new file mode 100644 index 000000000..8f901d612 --- /dev/null +++ b/ivtest/gold/dummy7.gold @@ -0,0 +1,6 @@ +should be 00 -- data1=00 data2=00 data3=00 data4=00 + +should be 11 -- data1=11 data2=11 data3=11 data4=11 + +should be 22 -- data1=22 data2=22 data3=22 data4=22 + diff --git a/ivtest/gold/dump_memword.vcd b/ivtest/gold/dump_memword.vcd new file mode 100644 index 000000000..03de017d5 --- /dev/null +++ b/ivtest/gold/dump_memword.vcd @@ -0,0 +1,19 @@ +$date + Wed Jun 4 10:37:42 2008 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module top $end +$var reg 8 ! \arr[4] [7:0] $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b0 ! +$end +#1 +b11111111 ! diff --git a/ivtest/gold/enum_dims_invalid.gold b/ivtest/gold/enum_dims_invalid.gold new file mode 100644 index 000000000..a145f8ae0 --- /dev/null +++ b/ivtest/gold/enum_dims_invalid.gold @@ -0,0 +1,8 @@ +ivltests/enum_dims_invalid.v:13: error: An unsized dimension is not allowed here. +ivltests/enum_dims_invalid.v:17: error: Dimension size must be greater than zero. +ivltests/enum_dims_invalid.v:17 : This size expression violates the rule: -('sd1) +ivltests/enum_dims_invalid.v:9: error: A queue dimension is not allowed here. +ivltests/enum_dims_invalid.v:21: error: Dimension size must be greater than zero. +ivltests/enum_dims_invalid.v:21 : This size expression violates the rule: 'sd0 +ivltests/enum_dims_invalid.v:25: error: Enum type must not have more than 1 packed dimension. +6 error(s) during elaboration. diff --git a/ivtest/gold/eofmt_percent-v11.gold b/ivtest/gold/eofmt_percent-v11.gold new file mode 100644 index 000000000..2fd0895ac --- /dev/null +++ b/ivtest/gold/eofmt_percent-v11.gold @@ -0,0 +1 @@ +The following should be a single percent: % diff --git a/ivtest/gold/eofmt_percent-vlog95.gold b/ivtest/gold/eofmt_percent-vlog95.gold new file mode 100644 index 000000000..071f69b8c --- /dev/null +++ b/ivtest/gold/eofmt_percent-vlog95.gold @@ -0,0 +1,2 @@ +WARNING: vlog95.v:11: a single % at the end of format string $display<%> will be displayed as '%'. +The following should be a single percent: % diff --git a/ivtest/gold/eofmt_percent.gold b/ivtest/gold/eofmt_percent.gold new file mode 100644 index 000000000..0ab0c8074 --- /dev/null +++ b/ivtest/gold/eofmt_percent.gold @@ -0,0 +1,2 @@ +WARNING: ./ivltests/eofmt_percent.v:2: a single % at the end of format string $display<%> will be displayed as '%'. +The following should be a single percent: % diff --git a/ivtest/gold/escaped_macro_name.gold b/ivtest/gold/escaped_macro_name.gold new file mode 100644 index 000000000..6ade160de --- /dev/null +++ b/ivtest/gold/escaped_macro_name.gold @@ -0,0 +1,9 @@ +simple name +simple name +escaped name +escaped name +backtick name +backtick +"text" +"text" +escaped quote diff --git a/ivtest/gold/event3.gold b/ivtest/gold/event3.gold new file mode 100644 index 000000000..ea1f23647 --- /dev/null +++ b/ivtest/gold/event3.gold @@ -0,0 +1,12 @@ +T= 0, a= 10, b= 20, x= x, y= x +T= 10, a= 30, b= 20, x= x, y= x +T= 20, a= 30, b= 40, x= x, y= x +T= 30, a= 50, b= 40, x= x, y= x +T= 31, a= 50, b= 40, x= 50, y= x +T= 33, a= 50, b= 40, x= 50, y= 40 +T= 40, a= 50, b= 60, x= 50, y= 40 +T= 43, a= 50, b= 60, x= 50, y= 60 +T= 50, a= 70, b= 80, x= 50, y= 60 +T= 51, a= 70, b= 80, x= 70, y= 60 +T= 53, a= 70, b= 80, x= 70, y= 80 +T= 60, a= 90, b= 80, x= 70, y= 80 diff --git a/ivtest/gold/event_list3.gold b/ivtest/gold/event_list3.gold new file mode 100644 index 000000000..5ce1cf7c9 --- /dev/null +++ b/ivtest/gold/event_list3.gold @@ -0,0 +1,6 @@ + 20 +combinatorial process 0 time: 30 +combinatorial process 1 time: 30 + 40 + 60 + 80 diff --git a/ivtest/gold/fatal_et_al-vlog95.gold b/ivtest/gold/fatal_et_al-vlog95.gold new file mode 100644 index 000000000..786707eb7 --- /dev/null +++ b/ivtest/gold/fatal_et_al-vlog95.gold @@ -0,0 +1,7 @@ +INFO: vlog95.v:12: This is the $info message. + Time: 1 Scope: top +WARNING: vlog95.v:13: This is the $warning message. + Time: 2 Scope: top +ERROR: vlog95.v:14: This is the $error message. + Time: 3 Scope: top +Check that the messages are correct. diff --git a/ivtest/gold/fatal_et_al.gold b/ivtest/gold/fatal_et_al.gold new file mode 100644 index 000000000..cd2b85bbc --- /dev/null +++ b/ivtest/gold/fatal_et_al.gold @@ -0,0 +1,7 @@ +INFO: ./ivltests/fatal_et_al.v:3: This is the $info message. + Time: 1 Scope: top +WARNING: ./ivltests/fatal_et_al.v:4: This is the $warning message. + Time: 2 Scope: top +ERROR: ./ivltests/fatal_et_al.v:5: This is the $error message. + Time: 3 Scope: top +Check that the messages are correct. diff --git a/ivtest/gold/fatal_et_al2.gold b/ivtest/gold/fatal_et_al2.gold new file mode 100644 index 000000000..47c3ad0fb --- /dev/null +++ b/ivtest/gold/fatal_et_al2.gold @@ -0,0 +1,8 @@ +INFO: ./ivltests/fatal_et_al2.v:3: This is the $info message. + Time: 1 Scope: top +WARNING: ./ivltests/fatal_et_al2.v:4: This is the $warning message. + Time: 2 Scope: top +ERROR: ./ivltests/fatal_et_al2.v:5: This is the $error message. + Time: 3 Scope: top +FATAL: ./ivltests/fatal_et_al2.v:6: This is the $fatal message. + Time: 4 Scope: top diff --git a/ivtest/gold/fdisplay1.gold b/ivtest/gold/fdisplay1.gold new file mode 100644 index 000000000..881cfd210 --- /dev/null +++ b/ivtest/gold/fdisplay1.gold @@ -0,0 +1,5 @@ +message to stdout (from $display) + +another message (via fwrite) to stdout + (via fdisplay) +a = 01011010 at 5 diff --git a/ivtest/gold/fdisplay2.out b/ivtest/gold/fdisplay2.out new file mode 100644 index 000000000..ab1aeda93 --- /dev/null +++ b/ivtest/gold/fdisplay2.out @@ -0,0 +1,2 @@ +hello, world +a = 'hac = 'b10101100 diff --git a/ivtest/gold/fdisplay3-vlog95.gold b/ivtest/gold/fdisplay3-vlog95.gold new file mode 100644 index 000000000..6888aa8d1 --- /dev/null +++ b/ivtest/gold/fdisplay3-vlog95.gold @@ -0,0 +1 @@ +ERROR: vlog95.v:12: $fdisplay's file descriptor/MCD must be numeric. diff --git a/ivtest/gold/fdisplay3.gold b/ivtest/gold/fdisplay3.gold new file mode 100644 index 000000000..3705f9334 --- /dev/null +++ b/ivtest/gold/fdisplay3.gold @@ -0,0 +1 @@ +ERROR: ./ivltests/fdisplay3.v:28: $fdisplay's file descriptor/MCD must be numeric. diff --git a/ivtest/gold/fdisplay_fail_fd-v10.gold b/ivtest/gold/fdisplay_fail_fd-v10.gold new file mode 100644 index 000000000..45bf9f8a0 --- /dev/null +++ b/ivtest/gold/fdisplay_fail_fd-v10.gold @@ -0,0 +1 @@ +WARNING: ./ivltests/fdisplay_fail_fd.v:4: invalid file descriptor/MCD (0x8000000f) given to $fdisplay. diff --git a/ivtest/gold/fdisplay_fail_fd-vlog95.gold b/ivtest/gold/fdisplay_fail_fd-vlog95.gold new file mode 100644 index 000000000..cc2c41dd6 --- /dev/null +++ b/ivtest/gold/fdisplay_fail_fd-vlog95.gold @@ -0,0 +1 @@ +WARNING: vlog95.v:11: invalid file descriptor (0x8000000f) given to $fdisplay(). diff --git a/ivtest/gold/fdisplay_fail_fd.gold b/ivtest/gold/fdisplay_fail_fd.gold new file mode 100644 index 000000000..9cef473bd --- /dev/null +++ b/ivtest/gold/fdisplay_fail_fd.gold @@ -0,0 +1 @@ +WARNING: ./ivltests/fdisplay_fail_fd.v:4: invalid file descriptor (0x8000000f) given to $fdisplay(). diff --git a/ivtest/gold/fdisplay_fail_mcd-v10.gold b/ivtest/gold/fdisplay_fail_mcd-v10.gold new file mode 100644 index 000000000..130194d45 --- /dev/null +++ b/ivtest/gold/fdisplay_fail_mcd-v10.gold @@ -0,0 +1 @@ +WARNING: ./ivltests/fdisplay_fail_mcd.v:4: invalid file descriptor/MCD (0x40000000) given to $fdisplay. diff --git a/ivtest/gold/fdisplay_fail_mcd-vlog95.gold b/ivtest/gold/fdisplay_fail_mcd-vlog95.gold new file mode 100644 index 000000000..500fddff9 --- /dev/null +++ b/ivtest/gold/fdisplay_fail_mcd-vlog95.gold @@ -0,0 +1 @@ +WARNING: vlog95.v:11: invalid MCD (0x40000000) given to $fdisplay(). diff --git a/ivtest/gold/fdisplay_fail_mcd.gold b/ivtest/gold/fdisplay_fail_mcd.gold new file mode 100644 index 000000000..eb20577f4 --- /dev/null +++ b/ivtest/gold/fdisplay_fail_mcd.gold @@ -0,0 +1 @@ +WARNING: ./ivltests/fdisplay_fail_mcd.v:4: invalid MCD (0x40000000) given to $fdisplay(). diff --git a/ivtest/gold/fileio.gold b/ivtest/gold/fileio.gold new file mode 100644 index 000000000..ac176f409 --- /dev/null +++ b/ivtest/gold/fileio.gold @@ -0,0 +1,2 @@ +From the write. +From the append. diff --git a/ivtest/gold/fileline.gold b/ivtest/gold/fileline.gold new file mode 100644 index 000000000..ea42e9993 --- /dev/null +++ b/ivtest/gold/fileline.gold @@ -0,0 +1,2 @@ +./ivltests/fileline.v +PASSED diff --git a/ivtest/gold/fileline2.gold b/ivtest/gold/fileline2.gold new file mode 100644 index 000000000..abb9bbf86 --- /dev/null +++ b/ivtest/gold/fileline2.gold @@ -0,0 +1,4 @@ +1 -> ./ivltests/fileline2.v:1003 +2 -> imaginary-include-file:2003 +3 -> ./ivltests/fileline2.v:3003 +PASSED diff --git a/ivtest/gold/final.gold b/ivtest/gold/final.gold new file mode 100644 index 000000000..e2b786190 --- /dev/null +++ b/ivtest/gold/final.gold @@ -0,0 +1 @@ +x = 3, PASSED diff --git a/ivtest/gold/final2.gold b/ivtest/gold/final2.gold new file mode 100644 index 000000000..de1c8de15 --- /dev/null +++ b/ivtest/gold/final2.gold @@ -0,0 +1,2 @@ +Final in t +Final in t2 diff --git a/ivtest/gold/format-vlog95.gold b/ivtest/gold/format-vlog95.gold new file mode 100644 index 000000000..007a01872 --- /dev/null +++ b/ivtest/gold/format-vlog95.gold @@ -0,0 +1,6 @@ +>16< +> 16< +>010< +> 010< +WARNING: vlog95.v:21: missing argument for $display<%d>. + 16, <%d> diff --git a/ivtest/gold/format.gold b/ivtest/gold/format.gold new file mode 100644 index 000000000..392bb30fd --- /dev/null +++ b/ivtest/gold/format.gold @@ -0,0 +1,6 @@ +>16< +> 16< +>010< +> 010< +WARNING: ./ivltests/format.v:12: missing argument for $display<%d>. + 16, <%d> diff --git a/ivtest/gold/fread-error-vlog95.gold b/ivtest/gold/fread-error-vlog95.gold new file mode 100644 index 000000000..9913184d6 --- /dev/null +++ b/ivtest/gold/fread-error-vlog95.gold @@ -0,0 +1,7 @@ +ERROR: vlog95.v:17: $fread's first argument must be a reg or memory. +ERROR: vlog95.v:18: $fread requires a second (file descriptor) argument. +ERROR: vlog95.v:19: $fread's second argument must be numeric. +ERROR: vlog95.v:20: $fread's third argument must be numeric. +ERROR: vlog95.v:21: $fread's fourth argument must be numeric. +ERROR: vlog95.v:22: $fread takes at most four arguments. + Found 1 extra argument. diff --git a/ivtest/gold/fread-error.gold b/ivtest/gold/fread-error.gold new file mode 100644 index 000000000..fbbc83715 --- /dev/null +++ b/ivtest/gold/fread-error.gold @@ -0,0 +1,7 @@ +ERROR: ./ivltests/fread-error.v:7: $fread's first argument must be a reg or memory. +ERROR: ./ivltests/fread-error.v:8: $fread requires a second (file descriptor) argument. +ERROR: ./ivltests/fread-error.v:9: $fread's second argument must be numeric. +ERROR: ./ivltests/fread-error.v:10: $fread's third argument must be numeric. +ERROR: ./ivltests/fread-error.v:11: $fread's fourth argument must be numeric. +ERROR: ./ivltests/fread-error.v:12: $fread takes at most four arguments. + Found 1 extra argument. diff --git a/ivtest/gold/fscanf_u_warn-vlog95.gold b/ivtest/gold/fscanf_u_warn-vlog95.gold new file mode 100644 index 000000000..2ebd4848b --- /dev/null +++ b/ivtest/gold/fscanf_u_warn-vlog95.gold @@ -0,0 +1,8 @@ +WARNING: vlog95.v:27: $fscanf() only found 2 of 4 bytes needed by %u format code. +WARNING: vlog95.v:38: $fscanf() only found 2 of 8 bytes needed by %u format code. +WARNING: vlog95.v:49: $fscanf() only found 4 of 8 bytes needed by %u format code. +WARNING: vlog95.v:60: $fscanf() only found 6 of 8 bytes needed by %u format code. +WARNING: vlog95.v:71: $fscanf() only found 2 of 4 bytes needed by %u format code. +WARNING: vlog95.v:83: $fscanf() only found 2 of 4 bytes needed by %u format code. +WARNING: vlog95.v:110: $fscanf() only found 2 of 4 bytes needed by %u format code. +PASSED diff --git a/ivtest/gold/fscanf_u_warn.gold b/ivtest/gold/fscanf_u_warn.gold new file mode 100644 index 000000000..466a9edd6 --- /dev/null +++ b/ivtest/gold/fscanf_u_warn.gold @@ -0,0 +1,8 @@ +WARNING: ./ivltests/fscanf_u_warn.v:16: $fscanf() only found 2 of 4 bytes needed by %u format code. +WARNING: ./ivltests/fscanf_u_warn.v:29: $fscanf() only found 2 of 8 bytes needed by %u format code. +WARNING: ./ivltests/fscanf_u_warn.v:42: $fscanf() only found 4 of 8 bytes needed by %u format code. +WARNING: ./ivltests/fscanf_u_warn.v:55: $fscanf() only found 6 of 8 bytes needed by %u format code. +WARNING: ./ivltests/fscanf_u_warn.v:68: $fscanf() only found 2 of 4 bytes needed by %u format code. +WARNING: ./ivltests/fscanf_u_warn.v:82: $fscanf() only found 2 of 4 bytes needed by %u format code. +WARNING: ./ivltests/fscanf_u_warn.v:110: $fscanf() only found 2 of 4 bytes needed by %u format code. +PASSED diff --git a/ivtest/gold/fscanf_z_warn-vlog95.gold b/ivtest/gold/fscanf_z_warn-vlog95.gold new file mode 100644 index 000000000..e85d9cf61 --- /dev/null +++ b/ivtest/gold/fscanf_z_warn-vlog95.gold @@ -0,0 +1,8 @@ +WARNING: vlog95.v:26: $fscanf() only found 4 of 8 bytes needed by %z format code. +WARNING: vlog95.v:37: $fscanf() only found 4 of 16 bytes needed by %z format code. +WARNING: vlog95.v:48: $fscanf() only found 8 of 16 bytes needed by %z format code. +WARNING: vlog95.v:59: $fscanf() only found 12 of 16 bytes needed by %z format code. +WARNING: vlog95.v:70: $fscanf() only found 4 of 8 bytes needed by %z format code. +WARNING: vlog95.v:81: $fscanf() only found 4 of 8 bytes needed by %z format code. +WARNING: vlog95.v:108: $fscanf() only found 4 of 8 bytes needed by %z format code. +PASSED diff --git a/ivtest/gold/fscanf_z_warn.gold b/ivtest/gold/fscanf_z_warn.gold new file mode 100644 index 000000000..1a0fa820c --- /dev/null +++ b/ivtest/gold/fscanf_z_warn.gold @@ -0,0 +1,8 @@ +WARNING: ./ivltests/fscanf_z_warn.v:16: $fscanf() only found 4 of 8 bytes needed by %z format code. +WARNING: ./ivltests/fscanf_z_warn.v:29: $fscanf() only found 4 of 16 bytes needed by %z format code. +WARNING: ./ivltests/fscanf_z_warn.v:42: $fscanf() only found 8 of 16 bytes needed by %z format code. +WARNING: ./ivltests/fscanf_z_warn.v:55: $fscanf() only found 12 of 16 bytes needed by %z format code. +WARNING: ./ivltests/fscanf_z_warn.v:68: $fscanf() only found 4 of 8 bytes needed by %z format code. +WARNING: ./ivltests/fscanf_z_warn.v:81: $fscanf() only found 4 of 8 bytes needed by %z format code. +WARNING: ./ivltests/fscanf_z_warn.v:109: $fscanf() only found 4 of 8 bytes needed by %z format code. +PASSED diff --git a/ivtest/gold/function1.gold b/ivtest/gold/function1.gold new file mode 100644 index 000000000..f6c238624 --- /dev/null +++ b/ivtest/gold/function1.gold @@ -0,0 +1,2 @@ +0008 = sum(0003, 0005) +PASSED diff --git a/ivtest/gold/function12.gold b/ivtest/gold/function12.gold new file mode 100644 index 000000000..607393a15 --- /dev/null +++ b/ivtest/gold/function12.gold @@ -0,0 +1,7 @@ +loop 0 +loop 1 +loop 2 +loop 3 +loop 4 +loop 5 +PASS diff --git a/ivtest/gold/gate_connect2.gold b/ivtest/gold/gate_connect2.gold new file mode 100644 index 000000000..3b2a03f72 --- /dev/null +++ b/ivtest/gold/gate_connect2.gold @@ -0,0 +1,4 @@ +./ivltests/gate_connect2.v:10: error: Expression width 32 does not match width 1 of logic gate array port 2. +./ivltests/gate_connect2.v:11: error: Expression width 2 does not match width 1 of logic gate array port 2. +./ivltests/gate_connect2.v:12: error: Expression width 2 does not match width 1 of logic gate array port 2. +3 error(s) during elaboration. diff --git a/ivtest/gold/generate_multi_loop.gold b/ivtest/gold/generate_multi_loop.gold new file mode 100644 index 000000000..430a93e45 --- /dev/null +++ b/ivtest/gold/generate_multi_loop.gold @@ -0,0 +1,3 @@ +byte_value = 00010010 00110100 01010110 01111000 +bit_value = 00010010 00110100 01010110 01111000 +Test passed diff --git a/ivtest/gold/idiv3.gold b/ivtest/gold/idiv3.gold new file mode 100644 index 000000000..217fc1f3a --- /dev/null +++ b/ivtest/gold/idiv3.gold @@ -0,0 +1 @@ + -8 -1 diff --git a/ivtest/gold/indef_width_concat.gold b/ivtest/gold/indef_width_concat.gold new file mode 100644 index 000000000..feceb2623 --- /dev/null +++ b/ivtest/gold/indef_width_concat.gold @@ -0,0 +1,2 @@ +./ivltests/indef_width_concat.v:4: error: Concatenation operand "'sd2" has indefinite width. +1 error(s) during elaboration. diff --git a/ivtest/gold/initmod.gold b/ivtest/gold/initmod.gold new file mode 100644 index 000000000..53e3f03d9 --- /dev/null +++ b/ivtest/gold/initmod.gold @@ -0,0 +1,10 @@ +0 x 0 x : xxxx : x x x x : xxxx : x x x x +1 0 0 1 : 0x0x : 0 x 0 x : 0x0x : 0 x 0 x +0 1 1 1 : 1001 : 1 0 0 1 : 1001 : 1 0 0 1 +1 0 1 0 : 0111 : 0 1 1 1 : 0111 : 0 1 1 1 +0 1 0 0 : 1010 : 1 0 1 0 : 1010 : 1 0 1 0 +1 0 0 1 : 0100 : 0 1 0 0 : 0100 : 0 1 0 0 +0 1 1 1 : 1001 : 1 0 0 1 : 1001 : 1 0 0 1 +1 0 1 0 : 0111 : 0 1 1 1 : 0111 : 0 1 1 1 +0 1 0 0 : 1010 : 1 0 1 0 : 1010 : 1 0 1 0 +1 0 0 1 : 0100 : 0 1 0 0 : 0100 : 0 1 0 0 diff --git a/ivtest/gold/initmod2.gold b/ivtest/gold/initmod2.gold new file mode 100644 index 000000000..3d8f0fdcc --- /dev/null +++ b/ivtest/gold/initmod2.gold @@ -0,0 +1,3 @@ +z z x 1 x x x : x 1 1 : x z +z z x 1 x x x : x 1 1 : x z +PASSED diff --git a/ivtest/gold/int_not_signext.gold b/ivtest/gold/int_not_signext.gold new file mode 100644 index 000000000..60e044f0d --- /dev/null +++ b/ivtest/gold/int_not_signext.gold @@ -0,0 +1,3 @@ +16 + -1 = 4294967311, 4294967311, 4294967311, 15, -1 = 4294967310 +16 + 0 = 16, 16, 16, 16, -1 = 15 +16 + 1 = 17, 17, 17, 17, -1 = 16 diff --git a/ivtest/gold/itor_rtoi.gold b/ivtest/gold/itor_rtoi.gold new file mode 100644 index 000000000..2a5158acb --- /dev/null +++ b/ivtest/gold/itor_rtoi.gold @@ -0,0 +1,51 @@ +Testing $itor() in a constant context. + $itor(10) = 10 + $itor(1'bx) = 0 + $itor(1'bx) = 0 + $itor(10.4) = 10 + $itor(10.5) = 11 + $itor(-1.4) = -1 + $itor(-1.5) = -2 + $itor(NaN) = 0 + $itor(+inf) = 0 + $itor(-inf) = 0 + +Testing $itor() in a variable context. + $itor(10) = 10 + $itor(1'bx) = 0 + $itor(1'bx) = 0 + $itor(10.4) = 10 + $itor(10.5) = 11 + $itor(-1.4) = -1 + $itor(-1.5) = -2 + $itor(NaN) = 0 + $itor(+inf) = 0 + $itor(-inf) = 0 + +Testing $rtoi() in a constant context. + $rtoi(1.1) = 1 + $rtoi(1.9) = 1 + $rtoi(-1.1) = -1 + $rtoi(-1.9) = -1 + Overflow(0) = 0 + Overflow(1) = 1 + $rtoi(NaN) = x + $rtoi(+inf) = x + $rtoi(-inf) = x + $rtoi(1) = 1 + $rtoi(1'bx) = 0 + $rtoi(1'bz) = 0 + +Testing $rtoi() in a variable context. + $rtoi(1.1) = 1 + $rtoi(1.9) = 1 + $rtoi(-1.1) = -1 + $rtoi(-1.9) = -1 + Overflow(0) = 0 + Overflow(1) = 1 + $rtoi(NaN) = x + $rtoi(+inf) = x + $rtoi(-inf) = x + $rtoi(1) = 1 + $rtoi(1'bx) = 0 + $rtoi(1'bz) = 0 diff --git a/ivtest/gold/ivlh_event.gold b/ivtest/gold/ivlh_event.gold new file mode 100644 index 000000000..3724baa52 --- /dev/null +++ b/ivtest/gold/ivlh_event.gold @@ -0,0 +1,4 @@ +1: EVENT on a +2: EVENT on b +3: EVENT on a +4: EVENT on b diff --git a/ivtest/gold/ivlh_rising_falling.gold b/ivtest/gold/ivlh_rising_falling.gold new file mode 100644 index 000000000..c5027965d --- /dev/null +++ b/ivtest/gold/ivlh_rising_falling.gold @@ -0,0 +1,8 @@ +1: rising_edge(a) +2: rising_edge(b) +3: falling_edge(a) +4: falling_edge(b) +7: rising_edge(a) +8: rising_edge(b) +11: falling_edge(a) +12: falling_edge(b) diff --git a/ivtest/gold/land4.gold b/ivtest/gold/land4.gold new file mode 100644 index 000000000..f74c5ce05 --- /dev/null +++ b/ivtest/gold/land4.gold @@ -0,0 +1,7 @@ +clk=0: ena=0, enb=0, wea=0, web=0 --> out=0 +clk=1: ena=0, enb=0, wea=0, web=0 --> out=0 +clk=0: ena=1, enb=1, wea=0, web=0 --> out=0 +clk=1: ena=1, enb=1, wea=0, web=0 --> out=0 +clk=0: ena=1, enb=1, wea=1, web=1 --> out=0 +clk=1: ena=1, enb=1, wea=1, web=1 --> out=1 +clk=0: ena=1, enb=1, wea=1, web=1 --> out=1 diff --git a/ivtest/gold/lh_memcat.gold b/ivtest/gold/lh_memcat.gold new file mode 100644 index 000000000..76ba4b234 --- /dev/null +++ b/ivtest/gold/lh_memcat.gold @@ -0,0 +1,4 @@ + +<< BEGIN >> + +<< END >> diff --git a/ivtest/gold/line_directive.gold b/ivtest/gold/line_directive.gold new file mode 100644 index 000000000..e96b3f99e --- /dev/null +++ b/ivtest/gold/line_directive.gold @@ -0,0 +1,6 @@ +file ./ivltests/line_directive.v line 8 +file real_source.v line 1 +file ./ivltests/line_directive_inc.v line 1 +file real_source.v line 3 +file real_source.v line 4 +file real_source.v line 5 diff --git a/ivtest/gold/long_div.gold b/ivtest/gold/long_div.gold new file mode 100644 index 000000000..54c0c835d --- /dev/null +++ b/ivtest/gold/long_div.gold @@ -0,0 +1,7 @@ +Using normal math routines. +Result: 1 +Modulus: 00000000 + +Using wide math routines. +Result: 1 +Modulus: 00000000000000000 diff --git a/ivtest/gold/macro_redefinition.gold b/ivtest/gold/macro_redefinition.gold new file mode 100644 index 000000000..926e9f77b --- /dev/null +++ b/ivtest/gold/macro_redefinition.gold @@ -0,0 +1,2 @@ +./ivltests/macro_redefinition.v:4: warning: redefinition of macro MACRO from value '1' to '1' +./ivltests/macro_redefinition.v:5: warning: redefinition of macro MACRO from value '1' to '2' diff --git a/ivtest/gold/macro_replacement.gold b/ivtest/gold/macro_replacement.gold new file mode 100644 index 000000000..4b31bf2b6 --- /dev/null +++ b/ivtest/gold/macro_replacement.gold @@ -0,0 +1 @@ +./ivltests/macro_replacement.v:5: warning: redefinition of macro MACRO from value '1' to '2' diff --git a/ivtest/gold/macro_str_esc.gold b/ivtest/gold/macro_str_esc.gold new file mode 100644 index 000000000..4d2928711 --- /dev/null +++ b/ivtest/gold/macro_str_esc.gold @@ -0,0 +1,12 @@ +Using ``celldefine gives: `celldefine +Plain ``celldefine gives: `celldefine +Using `DEF1 gives: string1 +Using ``DEF1 gives: "string1" +Plain ``DEF1 gives: "string1" +Using `DEF2 gives: string2" +Using ``DEF2 gives: "string2\"" +Plain ``DEF2 gives: "string2\"" +Using ``DEF3 gives: a\b +Plain ``DEF3 gives: a\b +Using ``DEF4("tmp") gives: "tmp" +Plain ``DEF4("tmp") gives: "tmp" diff --git a/ivtest/gold/macro_with_args.gold b/ivtest/gold/macro_with_args.gold new file mode 100644 index 000000000..c13571aa5 --- /dev/null +++ b/ivtest/gold/macro_with_args.gold @@ -0,0 +1,4 @@ +first..last first,last last..first +(a)..(c) (a,b,c) (c)..(a) +sumsqr(3,4) = 25 +sumsqr(5,12) = 169 diff --git a/ivtest/gold/mcl1.gold b/ivtest/gold/mcl1.gold new file mode 100644 index 000000000..1ce556c22 --- /dev/null +++ b/ivtest/gold/mcl1.gold @@ -0,0 +1,65536 @@ +0 0 00 000 +1 0 00 000 +2 0 00 000 +3 0 00 000 +4 0 00 000 +5 0 00 000 +6 0 00 000 +7 0 00 000 +8 0 00 000 +9 0 00 000 +a 0 00 000 +b 0 00 000 +c 0 00 000 +d 0 00 000 +e 0 00 000 +f 0 00 000 +0 1 00 000 +1 1 00 001 +2 1 00 002 +3 1 00 003 +4 1 00 004 +5 1 00 005 +6 1 00 006 +7 1 00 007 +8 1 00 1f8 +9 1 00 1f9 +a 1 00 1fa +b 1 00 1fb +c 1 00 1fc +d 1 00 1fd +e 1 00 1fe +f 1 00 1ff +0 2 00 000 +1 2 00 002 +2 2 00 004 +3 2 00 006 +4 2 00 008 +5 2 00 00a +6 2 00 00c +7 2 00 00e +8 2 00 1f0 +9 2 00 1f2 +a 2 00 1f4 +b 2 00 1f6 +c 2 00 1f8 +d 2 00 1fa +e 2 00 1fc +f 2 00 1fe +0 3 00 000 +1 3 00 003 +2 3 00 006 +3 3 00 009 +4 3 00 00c +5 3 00 00f +6 3 00 012 +7 3 00 015 +8 3 00 1e8 +9 3 00 1eb +a 3 00 1ee +b 3 00 1f1 +c 3 00 1f4 +d 3 00 1f7 +e 3 00 1fa +f 3 00 1fd +0 4 00 000 +1 4 00 004 +2 4 00 008 +3 4 00 00c +4 4 00 010 +5 4 00 014 +6 4 00 018 +7 4 00 01c +8 4 00 1e0 +9 4 00 1e4 +a 4 00 1e8 +b 4 00 1ec +c 4 00 1f0 +d 4 00 1f4 +e 4 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+9 6 be 194 +a 6 be 19a +b 6 be 1a0 +c 6 be 1a6 +d 6 be 1ac +e 6 be 1b2 +f 6 be 1b8 +0 7 be 1be +1 7 be 1c5 +2 7 be 1cc +3 7 be 1d3 +4 7 be 1da +5 7 be 1e1 +6 7 be 1e8 +7 7 be 1ef +8 7 be 186 +9 7 be 18d +a 7 be 194 +b 7 be 19b +c 7 be 1a2 +d 7 be 1a9 +e 7 be 1b0 +f 7 be 1b7 +0 8 be 1be +1 8 be 1b6 +2 8 be 1ae +3 8 be 1a6 +4 8 be 19e +5 8 be 196 +6 8 be 18e +7 8 be 186 +8 8 be 1fe +9 8 be 1f6 +a 8 be 1ee +b 8 be 1e6 +c 8 be 1de +d 8 be 1d6 +e 8 be 1ce +f 8 be 1c6 +0 9 be 1be +1 9 be 1b7 +2 9 be 1b0 +3 9 be 1a9 +4 9 be 1a2 +5 9 be 19b +6 9 be 194 +7 9 be 18d +8 9 be 1f6 +9 9 be 1ef +a 9 be 1e8 +b 9 be 1e1 +c 9 be 1da +d 9 be 1d3 +e 9 be 1cc +f 9 be 1c5 +0 a be 1be +1 a be 1b8 +2 a be 1b2 +3 a be 1ac +4 a be 1a6 +5 a be 1a0 +6 a be 19a +7 a be 194 +8 a be 1ee +9 a be 1e8 +a a be 1e2 +b a be 1dc +c a be 1d6 +d a be 1d0 +e a be 1ca +f a be 1c4 +0 b be 1be +1 b be 1b9 +2 b be 1b4 +3 b be 1af +4 b be 1aa +5 b be 1a5 +6 b be 1a0 +7 b be 19b +8 b be 1e6 +9 b be 1e1 +a b be 1dc +b b be 1d7 +c b be 1d2 +d b be 1cd +e b be 1c8 +f b be 1c3 +0 c be 1be +1 c be 1ba +2 c be 1b6 +3 c be 1b2 +4 c be 1ae +5 c be 1aa +6 c be 1a6 +7 c be 1a2 +8 c be 1de +9 c be 1da +a c be 1d6 +b c be 1d2 +c c be 1ce +d c be 1ca +e c be 1c6 +f c be 1c2 +0 d be 1be +1 d be 1bb +2 d be 1b8 +3 d be 1b5 +4 d be 1b2 +5 d be 1af +6 d be 1ac +7 d be 1a9 +8 d be 1d6 +9 d be 1d3 +a d be 1d0 +b d be 1cd +c d be 1ca +d d be 1c7 +e d be 1c4 +f d be 1c1 +0 e be 1be +1 e be 1bc +2 e be 1ba +3 e be 1b8 +4 e be 1b6 +5 e be 1b4 +6 e be 1b2 +7 e be 1b0 +8 e be 1ce +9 e be 1cc +a e be 1ca +b e be 1c8 +c e be 1c6 +d e be 1c4 +e e be 1c2 +f e be 1c0 +0 f be 1be +1 f be 1bd +2 f be 1bc +3 f be 1bb +4 f be 1ba +5 f be 1b9 +6 f be 1b8 +7 f be 1b7 +8 f be 1c6 +9 f be 1c5 +a f be 1c4 +b f be 1c3 +c f be 1c2 +d f be 1c1 +e f be 1c0 +f f be 1bf +0 0 bf 1bf +1 0 bf 1bf +2 0 bf 1bf +3 0 bf 1bf +4 0 bf 1bf +5 0 bf 1bf +6 0 bf 1bf +7 0 bf 1bf +8 0 bf 1bf +9 0 bf 1bf +a 0 bf 1bf +b 0 bf 1bf +c 0 bf 1bf +d 0 bf 1bf +e 0 bf 1bf +f 0 bf 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1c1 +4 0 c1 1c1 +5 0 c1 1c1 +6 0 c1 1c1 +7 0 c1 1c1 +8 0 c1 1c1 +9 0 c1 1c1 +a 0 c1 1c1 +b 0 c1 1c1 +c 0 c1 1c1 +d 0 c1 1c1 +e 0 c1 1c1 +f 0 c1 1c1 +0 1 c1 1c1 +1 1 c1 1c2 +2 1 c1 1c3 +3 1 c1 1c4 +4 1 c1 1c5 +5 1 c1 1c6 +6 1 c1 1c7 +7 1 c1 1c8 +8 1 c1 1b9 +9 1 c1 1ba +a 1 c1 1bb +b 1 c1 1bc +c 1 c1 1bd +d 1 c1 1be +e 1 c1 1bf +f 1 c1 1c0 +0 2 c1 1c1 +1 2 c1 1c3 +2 2 c1 1c5 +3 2 c1 1c7 +4 2 c1 1c9 +5 2 c1 1cb +6 2 c1 1cd +7 2 c1 1cf +8 2 c1 1b1 +9 2 c1 1b3 +a 2 c1 1b5 +b 2 c1 1b7 +c 2 c1 1b9 +d 2 c1 1bb +e 2 c1 1bd +f 2 c1 1bf +0 3 c1 1c1 +1 3 c1 1c4 +2 3 c1 1c7 +3 3 c1 1ca +4 3 c1 1cd +5 3 c1 1d0 +6 3 c1 1d3 +7 3 c1 1d6 +8 3 c1 1a9 +9 3 c1 1ac +a 3 c1 1af +b 3 c1 1b2 +c 3 c1 1b5 +d 3 c1 1b8 +e 3 c1 1bb +f 3 c1 1be +0 4 c1 1c1 +1 4 c1 1c5 +2 4 c1 1c9 +3 4 c1 1cd +4 4 c1 1d1 +5 4 c1 1d5 +6 4 c1 1d9 +7 4 c1 1dd +8 4 c1 1a1 +9 4 c1 1a5 +a 4 c1 1a9 +b 4 c1 1ad +c 4 c1 1b1 +d 4 c1 1b5 +e 4 c1 1b9 +f 4 c1 1bd +0 5 c1 1c1 +1 5 c1 1c6 +2 5 c1 1cb +3 5 c1 1d0 +4 5 c1 1d5 +5 5 c1 1da +6 5 c1 1df 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+d f cf 1d2 +e f cf 1d1 +f f cf 1d0 +0 0 d0 1d0 +1 0 d0 1d0 +2 0 d0 1d0 +3 0 d0 1d0 +4 0 d0 1d0 +5 0 d0 1d0 +6 0 d0 1d0 +7 0 d0 1d0 +8 0 d0 1d0 +9 0 d0 1d0 +a 0 d0 1d0 +b 0 d0 1d0 +c 0 d0 1d0 +d 0 d0 1d0 +e 0 d0 1d0 +f 0 d0 1d0 +0 1 d0 1d0 +1 1 d0 1d1 +2 1 d0 1d2 +3 1 d0 1d3 +4 1 d0 1d4 +5 1 d0 1d5 +6 1 d0 1d6 +7 1 d0 1d7 +8 1 d0 1c8 +9 1 d0 1c9 +a 1 d0 1ca +b 1 d0 1cb +c 1 d0 1cc +d 1 d0 1cd +e 1 d0 1ce +f 1 d0 1cf +0 2 d0 1d0 +1 2 d0 1d2 +2 2 d0 1d4 +3 2 d0 1d6 +4 2 d0 1d8 +5 2 d0 1da +6 2 d0 1dc +7 2 d0 1de +8 2 d0 1c0 +9 2 d0 1c2 +a 2 d0 1c4 +b 2 d0 1c6 +c 2 d0 1c8 +d 2 d0 1ca +e 2 d0 1cc +f 2 d0 1ce +0 3 d0 1d0 +1 3 d0 1d3 +2 3 d0 1d6 +3 3 d0 1d9 +4 3 d0 1dc +5 3 d0 1df +6 3 d0 1e2 +7 3 d0 1e5 +8 3 d0 1b8 +9 3 d0 1bb +a 3 d0 1be +b 3 d0 1c1 +c 3 d0 1c4 +d 3 d0 1c7 +e 3 d0 1ca +f 3 d0 1cd +0 4 d0 1d0 +1 4 d0 1d4 +2 4 d0 1d8 +3 4 d0 1dc +4 4 d0 1e0 +5 4 d0 1e4 +6 4 d0 1e8 +7 4 d0 1ec +8 4 d0 1b0 +9 4 d0 1b4 +a 4 d0 1b8 +b 4 d0 1bc +c 4 d0 1c0 +d 4 d0 1c4 +e 4 d0 1c8 +f 4 d0 1cc +0 5 d0 1d0 +1 5 d0 1d5 +2 5 d0 1da +3 5 d0 1df +4 5 d0 1e4 +5 5 d0 1e9 +6 5 d0 1ee +7 5 d0 1f3 +8 5 d0 1a8 +9 5 d0 1ad +a 5 d0 1b2 +b 5 d0 1b7 +c 5 d0 1bc +d 5 d0 1c1 +e 5 d0 1c6 +f 5 d0 1cb +0 6 d0 1d0 +1 6 d0 1d6 +2 6 d0 1dc +3 6 d0 1e2 +4 6 d0 1e8 +5 6 d0 1ee +6 6 d0 1f4 +7 6 d0 1fa +8 6 d0 1a0 +9 6 d0 1a6 +a 6 d0 1ac +b 6 d0 1b2 +c 6 d0 1b8 +d 6 d0 1be +e 6 d0 1c4 +f 6 d0 1ca +0 7 d0 1d0 +1 7 d0 1d7 +2 7 d0 1de +3 7 d0 1e5 +4 7 d0 1ec +5 7 d0 1f3 +6 7 d0 1fa +7 7 d0 001 +8 7 d0 198 +9 7 d0 19f +a 7 d0 1a6 +b 7 d0 1ad +c 7 d0 1b4 +d 7 d0 1bb +e 7 d0 1c2 +f 7 d0 1c9 +0 8 d0 1d0 +1 8 d0 1c8 +2 8 d0 1c0 +3 8 d0 1b8 +4 8 d0 1b0 +5 8 d0 1a8 +6 8 d0 1a0 +7 8 d0 198 +8 8 d0 010 +9 8 d0 008 +a 8 d0 000 +b 8 d0 1f8 +c 8 d0 1f0 +d 8 d0 1e8 +e 8 d0 1e0 +f 8 d0 1d8 +0 9 d0 1d0 +1 9 d0 1c9 +2 9 d0 1c2 +3 9 d0 1bb +4 9 d0 1b4 +5 9 d0 1ad +6 9 d0 1a6 +7 9 d0 19f +8 9 d0 008 +9 9 d0 001 +a 9 d0 1fa +b 9 d0 1f3 +c 9 d0 1ec +d 9 d0 1e5 +e 9 d0 1de +f 9 d0 1d7 +0 a d0 1d0 +1 a d0 1ca +2 a d0 1c4 +3 a d0 1be +4 a d0 1b8 +5 a d0 1b2 +6 a d0 1ac +7 a d0 1a6 +8 a d0 000 +9 a d0 1fa +a a d0 1f4 +b a d0 1ee +c a d0 1e8 +d a d0 1e2 +e a d0 1dc +f a d0 1d6 +0 b d0 1d0 +1 b d0 1cb +2 b d0 1c6 +3 b d0 1c1 +4 b d0 1bc +5 b d0 1b7 +6 b d0 1b2 +7 b d0 1ad +8 b d0 1f8 +9 b d0 1f3 +a b d0 1ee +b b d0 1e9 +c b d0 1e4 +d b d0 1df +e b d0 1da +f b d0 1d5 +0 c d0 1d0 +1 c d0 1cc +2 c d0 1c8 +3 c d0 1c4 +4 c d0 1c0 +5 c d0 1bc +6 c d0 1b8 +7 c d0 1b4 +8 c d0 1f0 +9 c d0 1ec +a c d0 1e8 +b c d0 1e4 +c c d0 1e0 +d c d0 1dc +e c d0 1d8 +f c d0 1d4 +0 d d0 1d0 +1 d d0 1cd +2 d d0 1ca +3 d d0 1c7 +4 d d0 1c4 +5 d d0 1c1 +6 d d0 1be +7 d d0 1bb +8 d d0 1e8 +9 d d0 1e5 +a d d0 1e2 +b d d0 1df +c d d0 1dc +d d d0 1d9 +e d d0 1d6 +f d d0 1d3 +0 e d0 1d0 +1 e d0 1ce +2 e d0 1cc +3 e d0 1ca +4 e d0 1c8 +5 e d0 1c6 +6 e d0 1c4 +7 e d0 1c2 +8 e d0 1e0 +9 e d0 1de +a e d0 1dc +b e d0 1da +c e d0 1d8 +d e d0 1d6 +e e d0 1d4 +f e d0 1d2 +0 f d0 1d0 +1 f d0 1cf +2 f d0 1ce +3 f d0 1cd +4 f d0 1cc +5 f d0 1cb +6 f d0 1ca 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d1 1b9 +b 4 d1 1bd +c 4 d1 1c1 +d 4 d1 1c5 +e 4 d1 1c9 +f 4 d1 1cd +0 5 d1 1d1 +1 5 d1 1d6 +2 5 d1 1db +3 5 d1 1e0 +4 5 d1 1e5 +5 5 d1 1ea +6 5 d1 1ef +7 5 d1 1f4 +8 5 d1 1a9 +9 5 d1 1ae +a 5 d1 1b3 +b 5 d1 1b8 +c 5 d1 1bd +d 5 d1 1c2 +e 5 d1 1c7 +f 5 d1 1cc +0 6 d1 1d1 +1 6 d1 1d7 +2 6 d1 1dd +3 6 d1 1e3 +4 6 d1 1e9 +5 6 d1 1ef +6 6 d1 1f5 +7 6 d1 1fb +8 6 d1 1a1 +9 6 d1 1a7 +a 6 d1 1ad +b 6 d1 1b3 +c 6 d1 1b9 +d 6 d1 1bf +e 6 d1 1c5 +f 6 d1 1cb +0 7 d1 1d1 +1 7 d1 1d8 +2 7 d1 1df +3 7 d1 1e6 +4 7 d1 1ed +5 7 d1 1f4 +6 7 d1 1fb +7 7 d1 002 +8 7 d1 199 +9 7 d1 1a0 +a 7 d1 1a7 +b 7 d1 1ae +c 7 d1 1b5 +d 7 d1 1bc +e 7 d1 1c3 +f 7 d1 1ca +0 8 d1 1d1 +1 8 d1 1c9 +2 8 d1 1c1 +3 8 d1 1b9 +4 8 d1 1b1 +5 8 d1 1a9 +6 8 d1 1a1 +7 8 d1 199 +8 8 d1 011 +9 8 d1 009 +a 8 d1 001 +b 8 d1 1f9 +c 8 d1 1f1 +d 8 d1 1e9 +e 8 d1 1e1 +f 8 d1 1d9 +0 9 d1 1d1 +1 9 d1 1ca +2 9 d1 1c3 +3 9 d1 1bc +4 9 d1 1b5 +5 9 d1 1ae +6 9 d1 1a7 +7 9 d1 1a0 +8 9 d1 009 +9 9 d1 002 +a 9 d1 1fb +b 9 d1 1f4 +c 9 d1 1ed +d 9 d1 1e6 +e 9 d1 1df +f 9 d1 1d8 +0 a d1 1d1 +1 a d1 1cb +2 a d1 1c5 +3 a d1 1bf +4 a d1 1b9 +5 a d1 1b3 +6 a d1 1ad +7 a d1 1a7 +8 a d1 001 +9 a d1 1fb +a a d1 1f5 +b a d1 1ef +c a d1 1e9 +d a d1 1e3 +e a d1 1dd +f a d1 1d7 +0 b d1 1d1 +1 b d1 1cc +2 b d1 1c7 +3 b d1 1c2 +4 b d1 1bd +5 b d1 1b8 +6 b d1 1b3 +7 b d1 1ae +8 b d1 1f9 +9 b d1 1f4 +a b d1 1ef +b b d1 1ea +c b d1 1e5 +d b d1 1e0 +e b d1 1db +f b d1 1d6 +0 c d1 1d1 +1 c d1 1cd +2 c d1 1c9 +3 c d1 1c5 +4 c d1 1c1 +5 c d1 1bd +6 c d1 1b9 +7 c d1 1b5 +8 c d1 1f1 +9 c d1 1ed +a c d1 1e9 +b c d1 1e5 +c c d1 1e1 +d c d1 1dd +e c d1 1d9 +f c d1 1d5 +0 d d1 1d1 +1 d d1 1ce +2 d d1 1cb +3 d d1 1c8 +4 d d1 1c5 +5 d d1 1c2 +6 d d1 1bf +7 d d1 1bc +8 d d1 1e9 +9 d d1 1e6 +a d d1 1e3 +b d d1 1e0 +c d d1 1dd +d d d1 1da +e d d1 1d7 +f d d1 1d4 +0 e d1 1d1 +1 e d1 1cf +2 e d1 1cd +3 e d1 1cb +4 e d1 1c9 +5 e d1 1c7 +6 e d1 1c5 +7 e d1 1c3 +8 e d1 1e1 +9 e d1 1df +a e d1 1dd +b e d1 1db +c e d1 1d9 +d e d1 1d7 +e e d1 1d5 +f e d1 1d3 +0 f d1 1d1 +1 f d1 1d0 +2 f d1 1cf +3 f d1 1ce +4 f d1 1cd +5 f d1 1cc +6 f d1 1cb +7 f d1 1ca +8 f d1 1d9 +9 f d1 1d8 +a f d1 1d7 +b f d1 1d6 +c f d1 1d5 +d f d1 1d4 +e f d1 1d3 +f f d1 1d2 +0 0 d2 1d2 +1 0 d2 1d2 +2 0 d2 1d2 +3 0 d2 1d2 +4 0 d2 1d2 +5 0 d2 1d2 +6 0 d2 1d2 +7 0 d2 1d2 +8 0 d2 1d2 +9 0 d2 1d2 +a 0 d2 1d2 +b 0 d2 1d2 +c 0 d2 1d2 +d 0 d2 1d2 +e 0 d2 1d2 +f 0 d2 1d2 +0 1 d2 1d2 +1 1 d2 1d3 +2 1 d2 1d4 +3 1 d2 1d5 +4 1 d2 1d6 +5 1 d2 1d7 +6 1 d2 1d8 +7 1 d2 1d9 +8 1 d2 1ca +9 1 d2 1cb +a 1 d2 1cc +b 1 d2 1cd +c 1 d2 1ce +d 1 d2 1cf +e 1 d2 1d0 +f 1 d2 1d1 +0 2 d2 1d2 +1 2 d2 1d4 +2 2 d2 1d6 +3 2 d2 1d8 +4 2 d2 1da +5 2 d2 1dc +6 2 d2 1de +7 2 d2 1e0 +8 2 d2 1c2 +9 2 d2 1c4 +a 2 d2 1c6 +b 2 d2 1c8 +c 2 d2 1ca +d 2 d2 1cc +e 2 d2 1ce +f 2 d2 1d0 +0 3 d2 1d2 +1 3 d2 1d5 +2 3 d2 1d8 +3 3 d2 1db +4 3 d2 1de +5 3 d2 1e1 +6 3 d2 1e4 +7 3 d2 1e7 +8 3 d2 1ba +9 3 d2 1bd +a 3 d2 1c0 +b 3 d2 1c3 +c 3 d2 1c6 +d 3 d2 1c9 +e 3 d2 1cc +f 3 d2 1cf +0 4 d2 1d2 +1 4 d2 1d6 +2 4 d2 1da +3 4 d2 1de +4 4 d2 1e2 +5 4 d2 1e6 +6 4 d2 1ea +7 4 d2 1ee +8 4 d2 1b2 +9 4 d2 1b6 +a 4 d2 1ba +b 4 d2 1be +c 4 d2 1c2 +d 4 d2 1c6 +e 4 d2 1ca +f 4 d2 1ce +0 5 d2 1d2 +1 5 d2 1d7 +2 5 d2 1dc +3 5 d2 1e1 +4 5 d2 1e6 +5 5 d2 1eb +6 5 d2 1f0 +7 5 d2 1f5 +8 5 d2 1aa +9 5 d2 1af +a 5 d2 1b4 +b 5 d2 1b9 +c 5 d2 1be +d 5 d2 1c3 +e 5 d2 1c8 +f 5 d2 1cd +0 6 d2 1d2 +1 6 d2 1d8 +2 6 d2 1de +3 6 d2 1e4 +4 6 d2 1ea +5 6 d2 1f0 +6 6 d2 1f6 +7 6 d2 1fc +8 6 d2 1a2 +9 6 d2 1a8 +a 6 d2 1ae +b 6 d2 1b4 +c 6 d2 1ba +d 6 d2 1c0 +e 6 d2 1c6 +f 6 d2 1cc +0 7 d2 1d2 +1 7 d2 1d9 +2 7 d2 1e0 +3 7 d2 1e7 +4 7 d2 1ee +5 7 d2 1f5 +6 7 d2 1fc +7 7 d2 003 +8 7 d2 19a +9 7 d2 1a1 +a 7 d2 1a8 +b 7 d2 1af +c 7 d2 1b6 +d 7 d2 1bd +e 7 d2 1c4 +f 7 d2 1cb +0 8 d2 1d2 +1 8 d2 1ca +2 8 d2 1c2 +3 8 d2 1ba +4 8 d2 1b2 +5 8 d2 1aa +6 8 d2 1a2 +7 8 d2 19a +8 8 d2 012 +9 8 d2 00a +a 8 d2 002 +b 8 d2 1fa +c 8 d2 1f2 +d 8 d2 1ea +e 8 d2 1e2 +f 8 d2 1da +0 9 d2 1d2 +1 9 d2 1cb +2 9 d2 1c4 +3 9 d2 1bd +4 9 d2 1b6 +5 9 d2 1af +6 9 d2 1a8 +7 9 d2 1a1 +8 9 d2 00a +9 9 d2 003 +a 9 d2 1fc +b 9 d2 1f5 +c 9 d2 1ee +d 9 d2 1e7 +e 9 d2 1e0 +f 9 d2 1d9 +0 a d2 1d2 +1 a d2 1cc +2 a d2 1c6 +3 a d2 1c0 +4 a d2 1ba +5 a d2 1b4 +6 a d2 1ae +7 a d2 1a8 +8 a d2 002 +9 a d2 1fc +a a d2 1f6 +b a d2 1f0 +c a d2 1ea +d a d2 1e4 +e a d2 1de +f a d2 1d8 +0 b d2 1d2 +1 b d2 1cd +2 b d2 1c8 +3 b d2 1c3 +4 b d2 1be +5 b d2 1b9 +6 b d2 1b4 +7 b d2 1af +8 b d2 1fa +9 b d2 1f5 +a b d2 1f0 +b b d2 1eb +c b d2 1e6 +d b d2 1e1 +e b d2 1dc +f b d2 1d7 +0 c d2 1d2 +1 c d2 1ce +2 c d2 1ca +3 c d2 1c6 +4 c d2 1c2 +5 c d2 1be +6 c d2 1ba +7 c d2 1b6 +8 c d2 1f2 +9 c d2 1ee +a c d2 1ea +b c d2 1e6 +c c d2 1e2 +d c d2 1de +e c d2 1da +f c d2 1d6 +0 d d2 1d2 +1 d d2 1cf +2 d d2 1cc +3 d d2 1c9 +4 d d2 1c6 +5 d d2 1c3 +6 d d2 1c0 +7 d d2 1bd +8 d d2 1ea +9 d d2 1e7 +a d d2 1e4 +b d d2 1e1 +c d d2 1de +d d d2 1db +e d d2 1d8 +f d d2 1d5 +0 e d2 1d2 +1 e d2 1d0 +2 e d2 1ce +3 e d2 1cc +4 e d2 1ca +5 e d2 1c8 +6 e d2 1c6 +7 e d2 1c4 +8 e d2 1e2 +9 e d2 1e0 +a e d2 1de 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+2 f 1ff1 +3 f 1fd9 +4 f 1fc1 +5 f 1fa9 +6 f 1f91 +7 f 1f79 +8 f 00e1 +9 f 00c9 +a f 00b1 +b f 0099 +c f 0081 +d f 0069 +e f 0051 +f f 0039 diff --git a/ivtest/gold/mem1-vlog95.gold b/ivtest/gold/mem1-vlog95.gold new file mode 100644 index 000000000..1d1e1a389 --- /dev/null +++ b/ivtest/gold/mem1-vlog95.gold @@ -0,0 +1,33 @@ +WARNING: vlog95.v:24: $readmemb: The behaviour for reg[...] mem[N:0]; $readmemb("...", mem); changed in the 1364-2005 standard. To avoid ambiguity, use mem[0:N] or explicit range parameters $readmemb("...", mem, start, stop);. Defaulting to 1364-2005 behavior. +mem[ 0] = 000100 +mem[ 1] = 000200 +mem[ 2] = 000400 +mem[ 3] = 000801 +mem[ 4] = 001000 +mem[ 5] = 002000 +mem[ 6] = 004000 +mem[ 7] = 008000 +mem[ 8] = 010000 +mem[ 9] = 020000 +mem[ 10] = 040000 +mem[ 11] = 080000 +mem[ 12] = 100000 +mem[ 13] = 200002 +mem[ 14] = 400000 +mem[ 15] = 800000 + 0 000100 + 1 000200 + 2 000400 + 3 000801 + 4 001000 + 5 002000 + 6 004000 + 7 008000 + 8 010000 + 9 020000 + 10 040000 + 11 080000 + 12 100000 + 13 200002 + 14 400000 + 15 800000 diff --git a/ivtest/gold/mem1.gold b/ivtest/gold/mem1.gold new file mode 100644 index 000000000..f35da35d7 --- /dev/null +++ b/ivtest/gold/mem1.gold @@ -0,0 +1,33 @@ +WARNING: ./ivltests/mem1.v:42: $readmemb: The behaviour for reg[...] mem[N:0]; $readmemb("...", mem); changed in the 1364-2005 standard. To avoid ambiguity, use mem[0:N] or explicit range parameters $readmemb("...", mem, start, stop);. Defaulting to 1364-2005 behavior. +mem[ 0] = 000100 +mem[ 1] = 000200 +mem[ 2] = 000400 +mem[ 3] = 000801 +mem[ 4] = 001000 +mem[ 5] = 002000 +mem[ 6] = 004000 +mem[ 7] = 008000 +mem[ 8] = 010000 +mem[ 9] = 020000 +mem[ 10] = 040000 +mem[ 11] = 080000 +mem[ 12] = 100000 +mem[ 13] = 200002 +mem[ 14] = 400000 +mem[ 15] = 800000 + 0 000100 + 1 000200 + 2 000400 + 3 000801 + 4 001000 + 5 002000 + 6 004000 + 7 008000 + 8 010000 + 9 020000 + 10 040000 + 11 080000 + 12 100000 + 13 200002 + 14 400000 + 15 800000 diff --git a/ivtest/gold/monitor.gold b/ivtest/gold/monitor.gold new file mode 100644 index 000000000..73e6cd2eb --- /dev/null +++ b/ivtest/gold/monitor.gold @@ -0,0 +1,13 @@ + 0 clk=0 + 5 clk=1 + 10 clk=0 + 15 clk=1 + 20 clk=0 + 25 clk=1 + 30 clk=0 + 35 clk=1 + 40 clk=0 + 45 clk=1 + 50 clk=0 + 55 clk=1 + 60 clk=0 diff --git a/ivtest/gold/monitor2.gold b/ivtest/gold/monitor2.gold new file mode 100644 index 000000000..4e5e0651b --- /dev/null +++ b/ivtest/gold/monitor2.gold @@ -0,0 +1,3 @@ +Time = 0 a = 0 +Time = 1 a = 1 +Time = 2 a = 0 diff --git a/ivtest/gold/monitor3.gold b/ivtest/gold/monitor3.gold new file mode 100644 index 000000000..c2e6b82cf --- /dev/null +++ b/ivtest/gold/monitor3.gold @@ -0,0 +1,5 @@ + 0: x=0.000000, y=0.000000 + 1: x=1.000000, y=0.000000 + 2: x=1.000000, y=2.000000 + 3: x=1.500000, y=2.000000 + 4: x=1.500000, y=5.100000 diff --git a/ivtest/gold/multi_bit_strength.gold b/ivtest/gold/multi_bit_strength.gold new file mode 100644 index 000000000..d26405109 --- /dev/null +++ b/ivtest/gold/multi_bit_strength.gold @@ -0,0 +1,5 @@ +All three lines should match: +----------------------------- +St0_Pu1_Pu1_St0 (reference) +St0_Pu1_Pu1_St0 (display) +St0_Pu1_Pu1_St0 (swrite) diff --git a/ivtest/gold/multi_bit_strength_std.gold b/ivtest/gold/multi_bit_strength_std.gold new file mode 100644 index 000000000..7d54b231e --- /dev/null +++ b/ivtest/gold/multi_bit_strength_std.gold @@ -0,0 +1,5 @@ +All three lines should match: +----------------------------- +St0_Pu1_Pu1_St0 (reference) +{St0,Pu1,Pu1,St0} (display) +{St0,Pu1,Pu1,St0} (swrite) diff --git a/ivtest/gold/negvalue.gold b/ivtest/gold/negvalue.gold new file mode 100644 index 000000000..18d588d94 --- /dev/null +++ b/ivtest/gold/negvalue.gold @@ -0,0 +1 @@ + 8 (should be 8) diff --git a/ivtest/gold/neq1.gold b/ivtest/gold/neq1.gold new file mode 100644 index 000000000..0f64df377 --- /dev/null +++ b/ivtest/gold/neq1.gold @@ -0,0 +1,63 @@ +a=0 + 0 1 0 + 1 0 1 + 2 0 1 + 3 0 1 + 4 0 1 + 5 0 1 + 6 0 1 + 7 0 1 +a=1 + 0 0 1 + 1 1 0 + 2 0 1 + 3 0 1 + 4 0 1 + 5 0 1 + 6 0 1 + 7 0 1 +a=2 + 0 0 1 + 1 0 1 + 2 1 0 + 3 0 1 + 4 0 1 + 5 0 1 + 6 0 1 + 7 0 1 +a=3 + 0 0 1 + 1 0 1 + 2 0 1 + 3 1 0 + 4 0 1 + 5 0 1 + 6 0 1 + 7 0 1 +a=4 + 0 0 1 + 1 0 1 + 2 0 1 + 3 0 1 + 4 1 0 + 5 0 1 + 6 0 1 + 7 0 1 +a=5 + 0 0 1 + 1 0 1 + 2 0 1 + 3 0 1 + 4 0 1 + 5 1 0 + 6 0 1 + 7 0 1 +a=6 + 0 0 1 + 1 0 1 + 2 0 1 + 3 0 1 + 4 0 1 + 5 0 1 + 6 1 0 + 7 0 1 diff --git a/ivtest/gold/nested_func.gold b/ivtest/gold/nested_func.gold new file mode 100644 index 000000000..cb3d02e7e --- /dev/null +++ b/ivtest/gold/nested_func.gold @@ -0,0 +1,3 @@ +sum of 2 to 5 = 14 +sum of 3 to 6 = 18 +sum of 4 to 7 = 22 diff --git a/ivtest/gold/nested_func_std.gold b/ivtest/gold/nested_func_std.gold new file mode 100644 index 000000000..9c291781d --- /dev/null +++ b/ivtest/gold/nested_func_std.gold @@ -0,0 +1,3 @@ +sum of 2 to 5 = 14 +sum of 3 to 6 = 18 +sum of 4 to 7 = 22 diff --git a/ivtest/gold/nested_impl_event1.gold b/ivtest/gold/nested_impl_event1.gold new file mode 100644 index 000000000..5aa6976c5 --- /dev/null +++ b/ivtest/gold/nested_impl_event1.gold @@ -0,0 +1,4 @@ +Triggered 1 at 30 +Triggered 2 at 50 +Triggered 1 at 60 +Triggered 2 at 70 diff --git a/ivtest/gold/nested_impl_event2.gold b/ivtest/gold/nested_impl_event2.gold new file mode 100644 index 000000000..263dd2356 --- /dev/null +++ b/ivtest/gold/nested_impl_event2.gold @@ -0,0 +1,2 @@ +./ivltests/nested_impl_event2.v:9: warning: @* found no sensitivities so it will never trigger. +Triggered 1 at 30 diff --git a/ivtest/gold/packed_dims_invalid_class.gold b/ivtest/gold/packed_dims_invalid_class.gold new file mode 100644 index 000000000..c0acee293 --- /dev/null +++ b/ivtest/gold/packed_dims_invalid_class.gold @@ -0,0 +1,19 @@ +ivltests/packed_dims_invalid_class.v:10: error: A queue dimension is not allowed here. +ivltests/packed_dims_invalid_class.v:4: error: An unsized dimension is not allowed here. +ivltests/packed_dims_invalid_class.v:12: error: A queue dimension is not allowed here. +ivltests/packed_dims_invalid_class.v:14: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_class.v:14 : This size expression violates the rule: 'sd0 +ivltests/packed_dims_invalid_class.v:5: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_class.v:5 : This size expression violates the rule: 'sd0 +ivltests/packed_dims_invalid_class.v:16: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_class.v:16 : This size expression violates the rule: 'sd0 +ivltests/packed_dims_invalid_class.v:18: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_class.v:18 : This size expression violates the rule: -('sd1) +ivltests/packed_dims_invalid_class.v:6: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_class.v:6 : This size expression violates the rule: -('sd1) +ivltests/packed_dims_invalid_class.v:20: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_class.v:20 : This size expression violates the rule: -('sd1) +ivltests/packed_dims_invalid_class.v:22: error: A queue dimension is not allowed here. +ivltests/packed_dims_invalid_class.v:7: error: A queue dimension is not allowed here. +ivltests/packed_dims_invalid_class.v:24: error: A queue dimension is not allowed here. +13 error(s) during elaboration. diff --git a/ivtest/gold/packed_dims_invalid_module.gold b/ivtest/gold/packed_dims_invalid_module.gold new file mode 100644 index 000000000..b39ad2b4c --- /dev/null +++ b/ivtest/gold/packed_dims_invalid_module.gold @@ -0,0 +1,31 @@ +ivltests/packed_dims_invalid_module.v:15: error: A queue dimension is not allowed here. +ivltests/packed_dims_invalid_module.v:16: error: An unsized dimension is not allowed here. +ivltests/packed_dims_invalid_module.v:17: error: A queue dimension is not allowed here. +ivltests/packed_dims_invalid_module.v:4: error: An unsized dimension is not allowed here. +ivltests/packed_dims_invalid_module.v:19: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_module.v:19 : This size expression violates the rule: 'sd0 +ivltests/packed_dims_invalid_module.v:5: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_module.v:5 : This size expression violates the rule: 'sd0 +ivltests/packed_dims_invalid_module.v:21: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_module.v:21 : This size expression violates the rule: 'sd0 +ivltests/packed_dims_invalid_module.v:5: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_module.v:5 : This size expression violates the rule: 'sd0 +ivltests/packed_dims_invalid_module.v:23: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_module.v:23 : This size expression violates the rule: -('sd1) +ivltests/packed_dims_invalid_module.v:6: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_module.v:6 : This size expression violates the rule: -('sd1) +ivltests/packed_dims_invalid_module.v:25: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_module.v:25 : This size expression violates the rule: -('sd1) +ivltests/packed_dims_invalid_module.v:6: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_module.v:6 : This size expression violates the rule: -('sd1) +ivltests/packed_dims_invalid_module.v:27: error: A queue dimension is not allowed here. +ivltests/packed_dims_invalid_module.v:28: error: A queue dimension is not allowed here. +ivltests/packed_dims_invalid_module.v:29: error: A queue dimension is not allowed here. +ivltests/packed_dims_invalid_module.v:7: error: A queue dimension is not allowed here. +ivltests/packed_dims_invalid_module.v:10: error: An unsized dimension is not allowed here. +ivltests/packed_dims_invalid_module.v:11: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_module.v:11 : This size expression violates the rule: 'sd0 +ivltests/packed_dims_invalid_module.v:12: error: Dimension size must be greater than zero. +ivltests/packed_dims_invalid_module.v:12 : This size expression violates the rule: -('sd1) +ivltests/packed_dims_invalid_module.v:13: error: A queue dimension is not allowed here. +20 error(s) during elaboration. diff --git a/ivtest/gold/param-width-ivl.gold b/ivtest/gold/param-width-ivl.gold new file mode 100644 index 000000000..2b52f89ca --- /dev/null +++ b/ivtest/gold/param-width-ivl.gold @@ -0,0 +1,4 @@ +1001 +1001 +0101 +101 diff --git a/ivtest/gold/param-width.gold b/ivtest/gold/param-width.gold new file mode 100644 index 000000000..bae403336 --- /dev/null +++ b/ivtest/gold/param-width.gold @@ -0,0 +1,4 @@ +1001 +001 +0101 +01 diff --git a/ivtest/gold/param_test1.gold b/ivtest/gold/param_test1.gold new file mode 100644 index 000000000..a3b1f384e --- /dev/null +++ b/ivtest/gold/param_test1.gold @@ -0,0 +1,15 @@ +OKAY: dat = 00000000, exp_dat = 0 +OKAY: dat = 00000001, exp_dat = 1 +OKAY: dat = 00000002, exp_dat = 2 +OKAY: dat = 00000003, exp_dat = 3 +OKAY: dat = 00000004, exp_dat = 4 +OKAY: dat = 00000005, exp_dat = 5 +OKAY: dat = 00000006, exp_dat = 6 +OKAY: dat = 00000007, exp_dat = 7 +OKAY: dat = 00000008, exp_dat = 8 +OKAY: dat = 00000009, exp_dat = 9 +OKAY: dat = 0000000a, exp_dat = a +OKAY: dat = 0000000b, exp_dat = b +OKAY: dat = 0000000c, exp_dat = c +OKAY: dat = 0000000d, exp_dat = d +OKAY: dat = 0000000e, exp_dat = e diff --git a/ivtest/gold/param_test2.gold b/ivtest/gold/param_test2.gold new file mode 100644 index 000000000..a5574d2eb --- /dev/null +++ b/ivtest/gold/param_test2.gold @@ -0,0 +1 @@ +foo = ffffffffffffffffffffffffffffffffffffffffffffffff diff --git a/ivtest/gold/param_test3.gold b/ivtest/gold/param_test3.gold new file mode 100644 index 000000000..7b702b567 --- /dev/null +++ b/ivtest/gold/param_test3.gold @@ -0,0 +1,2 @@ +./ivltests/param_test3.v:25: warning: ignoring 3 extra parameter override(s) for instance 'am' of module 'm' which expects 0 parameter(s). +PASSED diff --git a/ivtest/gold/parameter_type-ivl.gold b/ivtest/gold/parameter_type-ivl.gold new file mode 100644 index 000000000..66d1da166 --- /dev/null +++ b/ivtest/gold/parameter_type-ivl.gold @@ -0,0 +1,8 @@ +Implicit real: -1.00000 +Implicit integer: -1 +Unsigned: 255 +Signed: -1 +Real: -1.00000 +Real time: -1.00000 +Integer: -1 +Time: 18446744073709551615 diff --git a/ivtest/gold/parameter_type-vlog95.gold b/ivtest/gold/parameter_type-vlog95.gold new file mode 100644 index 000000000..69ed40473 --- /dev/null +++ b/ivtest/gold/parameter_type-vlog95.gold @@ -0,0 +1,8 @@ +Implicit real: -1.00000 +Implicit integer: -1 +Unsigned: 255 +Signed: -1 +Real: -1.00000 +Real time: -1.00000 +Integer: -1 +Time: 18446744073709551615 diff --git a/ivtest/gold/parameter_type.gold b/ivtest/gold/parameter_type.gold new file mode 100644 index 000000000..68d3e1733 --- /dev/null +++ b/ivtest/gold/parameter_type.gold @@ -0,0 +1,8 @@ +Implicit real: -1 +Implicit integer: -1 +Unsigned: 255 +Signed: -1 +Real: -1 +Real time: -1 +Integer: -1 +Time: 18446744073709551615 diff --git a/ivtest/gold/pic-vlog95.gold b/ivtest/gold/pic-vlog95.gold new file mode 100644 index 000000000..7f322df95 --- /dev/null +++ b/ivtest/gold/pic-vlog95.gold @@ -0,0 +1,201 @@ +Clearing SRAM. +SYNTHETIC PIC 2.0. This is TEST #9 +WARNING: vlog95.v:283: $readmemh(contrib/TEST9.ROM): Too many words in the file for the requested range [0:511]. + 50: portc changes to: 00 + 50: portb changes to: 00 + 1650: portb changes to: 07 + 2150: portb changes to: 09 + 2650: portb changes to: 0c + 3150: portb changes to: 0e + 3650: portb changes to: 11 + 4150: portb changes to: 13 + 4650: portb changes to: 16 + 5150: portb changes to: 18 + 5650: portb changes to: 1b + 6150: portb changes to: 1d + 6650: portb changes to: 20 + 7150: portb changes to: 22 + 7650: portb changes to: 25 + 8150: portb changes to: 27 + 8650: portb changes to: 2a + 9150: portb changes to: 2c + 9650: portb changes to: 2f + 10150: portb changes to: 31 + 10650: portb changes to: 34 + 11150: portb changes to: 36 + 12350: portc changes to: 01 + 12550: portb changes to: 3d + 13050: portb changes to: 3e + 13550: portb changes to: 3f + 14050: portb changes to: 41 + 14550: portb changes to: 42 + 15050: portb changes to: 43 + 15550: portb changes to: 44 + 16050: portb changes to: 46 + 16550: portb changes to: 47 + 17050: portb changes to: 48 + 17550: portb changes to: 49 + 18050: portb changes to: 4b + 18550: portb changes to: 4c + 19050: portb changes to: 4d + 19550: portb changes to: 4e + 20050: portb changes to: 50 + 20550: portb changes to: 51 + 21050: portb changes to: 52 + 21550: portb changes to: 53 + 22050: portb changes to: 55 + 23250: portc changes to: 02 + 23450: portb changes to: 58 + 23950: portb changes to: 59 + 24450: portb changes to: 5a + 25450: portb changes to: 5b + 26450: portb changes to: 5c + 26950: portb changes to: 5d + 27950: portb changes to: 5e + 28450: portb changes to: 5f + 29450: portb changes to: 60 + 30450: portb changes to: 61 + 30950: portb changes to: 62 + 31950: portb changes to: 63 + 32450: portb changes to: 64 + 34150: portc changes to: 03 + 34350: portb changes to: 66 + 35850: portb changes to: 67 + 37350: portb changes to: 68 + 38850: portb changes to: 69 + 40850: portb changes to: 6a + 42350: portb changes to: 6b + 43850: portb changes to: 6c + 45050: portc changes to: 04 + 45250: portb changes to: 6d + 48750: portb changes to: 6e + 51750: portb changes to: 6f + 55950: portc changes to: 05 + 56150: portb changes to: 70 + 58150: portb changes to: 71 + 64650: portb changes to: 72 + 66850: portc changes to: 06 + 77750: portc changes to: 07 + 77950: portb changes to: 73 + 88650: portc changes to: 00 + 88850: portb changes to: 74 + 89350: portb changes to: 76 + 89850: portb changes to: 79 + 90350: portb changes to: 7b + 90850: portb changes to: 7e + 91350: portb changes to: 80 + 91850: portb changes to: 83 + 92350: portb changes to: 85 + 92850: portb changes to: 88 + 93350: portb changes to: 8a + 93850: portb changes to: 8d + 94350: portb changes to: 8f + 94850: portb changes to: 92 + 95350: portb changes to: 94 + 95850: portb changes to: 97 + 96350: portb changes to: 99 + 96850: portb changes to: 9c + 97350: portb changes to: 9e + 97850: portb changes to: a1 + 98350: portb changes to: a3 + 99550: portc changes to: 01 + 99750: portb changes to: aa + 100250: portb changes to: ab + 100750: portb changes to: ac + 101250: portb changes to: ae + 101750: portb changes to: af + 102250: portb changes to: b0 + 102750: portb changes to: b1 + 103250: portb changes to: b3 + 103750: portb changes to: b4 + 104250: portb changes to: b5 + 104750: portb changes to: b6 + 105250: portb changes to: b8 + 105750: portb changes to: b9 + 106250: portb changes to: ba + 106750: portb changes to: bb + 107250: portb changes to: bd + 107750: portb changes to: be + 108250: portb changes to: bf + 108750: portb changes to: c0 + 109250: portb changes to: c2 + 110450: portc changes to: 02 + 110650: portb changes to: c5 + 111150: portb changes to: c6 + 111650: portb changes to: c7 + 112650: portb changes to: c8 + 113650: portb changes to: c9 + 114150: portb changes to: ca + 115150: portb changes to: cb + 115650: portb changes to: cc + 116650: portb changes to: cd + 117650: portb changes to: ce + 118150: portb changes to: cf + 119150: portb changes to: d0 + 119650: portb changes to: d1 + 121350: portc changes to: 03 + 121550: portb changes to: d3 + 122050: portb changes to: d4 + 124050: portb changes to: d5 + 125550: portb changes to: d6 + 127050: portb changes to: d7 + 128550: portb changes to: d8 + 130050: portb changes to: d9 + 132250: portc changes to: 04 + 132450: portb changes to: da + 134950: portb changes to: db + 138450: portb changes to: dc + 141450: portb changes to: dd + 143150: portc changes to: 05 + 147850: portb changes to: de + 154050: portc changes to: 06 + 154250: portb changes to: df + 164950: portc changes to: 07 + 175850: portc changes to: 00 + 176050: portb changes to: e0 + 176550: portb changes to: e2 + 177050: portb changes to: e5 + 177550: portb changes to: e7 + 178050: portb changes to: ea + 178550: portb changes to: ec + 179050: portb changes to: ef + 179550: portb changes to: f1 + 180050: portb changes to: f4 + 180550: portb changes to: f6 + 181050: portb changes to: f9 + 181550: portb changes to: fb + 182050: portb changes to: fe + 182550: portb changes to: 00 + 183050: portb changes to: 03 + 183550: portb changes to: 05 + 184050: portb changes to: 08 + 184550: portb changes to: 0a + 185050: portb changes to: 0d + 185550: portb changes to: 0f + 186750: portc changes to: 01 + 186950: portb changes to: 16 + 187450: portb changes to: 17 + 187950: portb changes to: 18 + 188450: portb changes to: 1a + 188950: portb changes to: 1b + 189450: portb changes to: 1c + 189950: portb changes to: 1d + 190450: portb changes to: 1f + 190950: portb changes to: 20 + 191450: portb changes to: 21 + 191950: portb changes to: 22 + 192450: portb changes to: 24 + 192950: portb changes to: 25 + 193450: portb changes to: 26 + 193950: portb changes to: 27 + 194450: portb changes to: 29 + 194950: portb changes to: 2a + 195450: portb changes to: 2b + 195950: portb changes to: 2c + 196450: portb changes to: 2e + 197650: portc changes to: 02 + 197850: portb changes to: 31 + 198350: portb changes to: 32 + 198850: portb changes to: 33 + 199850: portb changes to: 34 +Maximum cycles (2000) Exceeded. Halting simulation. diff --git a/ivtest/gold/pic.gold b/ivtest/gold/pic.gold new file mode 100644 index 000000000..b0bf7b057 --- /dev/null +++ b/ivtest/gold/pic.gold @@ -0,0 +1,201 @@ +Clearing SRAM. +SYNTHETIC PIC 2.0. This is TEST #9 +WARNING: ./contrib/pic.v:2046: $readmemh(contrib/TEST9.ROM): Too many words in the file for the requested range [0:511]. + 50: portc changes to: 00 + 50: portb changes to: 00 + 1650: portb changes to: 07 + 2150: portb changes to: 09 + 2650: portb changes to: 0c + 3150: portb changes to: 0e + 3650: portb changes to: 11 + 4150: portb changes to: 13 + 4650: portb changes to: 16 + 5150: portb changes to: 18 + 5650: portb changes to: 1b + 6150: portb changes to: 1d + 6650: portb changes to: 20 + 7150: portb changes to: 22 + 7650: portb changes to: 25 + 8150: portb changes to: 27 + 8650: portb changes to: 2a + 9150: portb changes to: 2c + 9650: portb changes to: 2f + 10150: portb changes to: 31 + 10650: portb changes to: 34 + 11150: portb changes to: 36 + 12350: portc changes to: 01 + 12550: portb changes to: 3d + 13050: portb changes to: 3e + 13550: portb changes to: 3f + 14050: portb changes to: 41 + 14550: portb changes to: 42 + 15050: portb changes to: 43 + 15550: portb changes to: 44 + 16050: portb changes to: 46 + 16550: portb changes to: 47 + 17050: portb changes to: 48 + 17550: portb changes to: 49 + 18050: portb changes to: 4b + 18550: portb changes to: 4c + 19050: portb changes to: 4d + 19550: portb changes to: 4e + 20050: portb changes to: 50 + 20550: portb changes to: 51 + 21050: portb changes to: 52 + 21550: portb changes to: 53 + 22050: portb changes to: 55 + 23250: portc changes to: 02 + 23450: portb changes to: 58 + 23950: portb changes to: 59 + 24450: portb changes to: 5a + 25450: portb changes to: 5b + 26450: portb changes to: 5c + 26950: portb changes to: 5d + 27950: portb changes to: 5e + 28450: portb changes to: 5f + 29450: portb changes to: 60 + 30450: portb changes to: 61 + 30950: portb changes to: 62 + 31950: portb changes to: 63 + 32450: portb changes to: 64 + 34150: portc changes to: 03 + 34350: portb changes to: 66 + 35850: portb changes to: 67 + 37350: portb changes to: 68 + 38850: portb changes to: 69 + 40850: portb changes to: 6a + 42350: portb changes to: 6b + 43850: portb changes to: 6c + 45050: portc changes to: 04 + 45250: portb changes to: 6d + 48750: portb changes to: 6e + 51750: portb changes to: 6f + 55950: portc changes to: 05 + 56150: portb changes to: 70 + 58150: portb changes to: 71 + 64650: portb changes to: 72 + 66850: portc changes to: 06 + 77750: portc changes to: 07 + 77950: portb changes to: 73 + 88650: portc changes to: 00 + 88850: portb changes to: 74 + 89350: portb changes to: 76 + 89850: portb changes to: 79 + 90350: portb changes to: 7b + 90850: portb changes to: 7e + 91350: portb changes to: 80 + 91850: portb changes to: 83 + 92350: portb changes to: 85 + 92850: portb changes to: 88 + 93350: portb changes to: 8a + 93850: portb changes to: 8d + 94350: portb changes to: 8f + 94850: portb changes to: 92 + 95350: portb changes to: 94 + 95850: portb changes to: 97 + 96350: portb changes to: 99 + 96850: portb changes to: 9c + 97350: portb changes to: 9e + 97850: portb changes to: a1 + 98350: portb changes to: a3 + 99550: portc changes to: 01 + 99750: portb changes to: aa + 100250: portb changes to: ab + 100750: portb changes to: ac + 101250: portb changes to: ae + 101750: portb changes to: af + 102250: portb changes to: b0 + 102750: portb changes to: b1 + 103250: portb changes to: b3 + 103750: portb changes to: b4 + 104250: portb changes to: b5 + 104750: portb changes to: b6 + 105250: portb changes to: b8 + 105750: portb changes to: b9 + 106250: portb changes to: ba + 106750: portb changes to: bb + 107250: portb changes to: bd + 107750: portb changes to: be + 108250: portb changes to: bf + 108750: portb changes to: c0 + 109250: portb changes to: c2 + 110450: portc changes to: 02 + 110650: portb changes to: c5 + 111150: portb changes to: c6 + 111650: portb changes to: c7 + 112650: portb changes to: c8 + 113650: portb changes to: c9 + 114150: portb changes to: ca + 115150: portb changes to: cb + 115650: portb changes to: cc + 116650: portb changes to: cd + 117650: portb changes to: ce + 118150: portb changes to: cf + 119150: portb changes to: d0 + 119650: portb changes to: d1 + 121350: portc changes to: 03 + 121550: portb changes to: d3 + 122050: portb changes to: d4 + 124050: portb changes to: d5 + 125550: portb changes to: d6 + 127050: portb changes to: d7 + 128550: portb changes to: d8 + 130050: portb changes to: d9 + 132250: portc changes to: 04 + 132450: portb changes to: da + 134950: portb changes to: db + 138450: portb changes to: dc + 141450: portb changes to: dd + 143150: portc changes to: 05 + 147850: portb changes to: de + 154050: portc changes to: 06 + 154250: portb changes to: df + 164950: portc changes to: 07 + 175850: portc changes to: 00 + 176050: portb changes to: e0 + 176550: portb changes to: e2 + 177050: portb changes to: e5 + 177550: portb changes to: e7 + 178050: portb changes to: ea + 178550: portb changes to: ec + 179050: portb changes to: ef + 179550: portb changes to: f1 + 180050: portb changes to: f4 + 180550: portb changes to: f6 + 181050: portb changes to: f9 + 181550: portb changes to: fb + 182050: portb changes to: fe + 182550: portb changes to: 00 + 183050: portb changes to: 03 + 183550: portb changes to: 05 + 184050: portb changes to: 08 + 184550: portb changes to: 0a + 185050: portb changes to: 0d + 185550: portb changes to: 0f + 186750: portc changes to: 01 + 186950: portb changes to: 16 + 187450: portb changes to: 17 + 187950: portb changes to: 18 + 188450: portb changes to: 1a + 188950: portb changes to: 1b + 189450: portb changes to: 1c + 189950: portb changes to: 1d + 190450: portb changes to: 1f + 190950: portb changes to: 20 + 191450: portb changes to: 21 + 191950: portb changes to: 22 + 192450: portb changes to: 24 + 192950: portb changes to: 25 + 193450: portb changes to: 26 + 193950: portb changes to: 27 + 194450: portb changes to: 29 + 194950: portb changes to: 2a + 195450: portb changes to: 2b + 195950: portb changes to: 2c + 196450: portb changes to: 2e + 197650: portc changes to: 02 + 197850: portb changes to: 31 + 198350: portb changes to: 32 + 198850: portb changes to: 33 + 199850: portb changes to: 34 +Maximum cycles (2000) Exceeded. Halting simulation. diff --git a/ivtest/gold/pr1002.gold b/ivtest/gold/pr1002.gold new file mode 100644 index 000000000..6337e916f --- /dev/null +++ b/ivtest/gold/pr1002.gold @@ -0,0 +1,9 @@ +datain = 4095 dataout = 1023 expected = 1023 ... CHECK PASSED +datain = 0 dataout = 0 expected = 0 ... CHECK PASSED +datain = 8191 dataout = 2047 expected = 2047 ... CHECK PASSED +datain = 4096 dataout = 1024 expected = 1024 ... CHECK PASSED +datain = -4097 dataout = -1025 expected = -1025 ... CHECK PASSED +datain = -8192 dataout = -2048 expected = -2048 ... CHECK PASSED +datain = -1 dataout = -1 expected = -1 ... CHECK PASSED +datain = -4096 dataout = -1024 expected = -1024 ... CHECK PASSED +TEST PASSED :-) diff --git a/ivtest/gold/pr1002_std.gold b/ivtest/gold/pr1002_std.gold new file mode 100644 index 000000000..7654f9e91 --- /dev/null +++ b/ivtest/gold/pr1002_std.gold @@ -0,0 +1,9 @@ +datain = 4095 dataout = 1023 expected = 1023 ... CHECK PASSED +datain = 0 dataout = 0 expected = 0 ... CHECK PASSED +datain = 8191 dataout = 2047 expected = 2047 ... CHECK PASSED +datain = 4096 dataout = 1024 expected = 1024 ... CHECK PASSED +datain = -4097 dataout = -1025 expected = -1025 ... CHECK PASSED +datain = -8192 dataout = -2048 expected = -2048 ... CHECK PASSED +datain = -1 dataout = -1 expected = -1 ... CHECK PASSED +datain = -4096 dataout = -1024 expected = -1024 ... CHECK PASSED +TEST PASSED :-) diff --git a/ivtest/gold/pr1002a.gold b/ivtest/gold/pr1002a.gold new file mode 100644 index 000000000..ac667ee62 --- /dev/null +++ b/ivtest/gold/pr1002a.gold @@ -0,0 +1,10 @@ +datain = x dataout = X expected = X ... CHECK PASSED +datain = 4095 dataout = 16380 expected = 16380 ... CHECK PASSED +datain = 0 dataout = 0 expected = 0 ... CHECK PASSED +datain = 8191 dataout = 32764 expected = 32764 ... CHECK PASSED +datain = 4096 dataout = 16384 expected = 16384 ... CHECK PASSED +datain = -4097 dataout = -16388 expected = -16388 ... CHECK PASSED +datain = -8192 dataout = -32768 expected = -32768 ... CHECK PASSED +datain = -1 dataout = -4 expected = -4 ... CHECK PASSED +datain = -4096 dataout = -16384 expected = -16384 ... CHECK PASSED +TEST PASSED :-) diff --git a/ivtest/gold/pr1002a_std.gold b/ivtest/gold/pr1002a_std.gold new file mode 100644 index 000000000..07253eb99 --- /dev/null +++ b/ivtest/gold/pr1002a_std.gold @@ -0,0 +1,10 @@ +datain = x dataout = X expected = X ... CHECK PASSED +datain = 4095 dataout = 16380 expected = 16380 ... CHECK PASSED +datain = 0 dataout = 0 expected = 0 ... CHECK PASSED +datain = 8191 dataout = 32764 expected = 32764 ... CHECK PASSED +datain = 4096 dataout = 16384 expected = 16384 ... CHECK PASSED +datain = -4097 dataout = -16388 expected = -16388 ... CHECK PASSED +datain = -8192 dataout = -32768 expected = -32768 ... CHECK PASSED +datain = -1 dataout = -4 expected = -4 ... CHECK PASSED +datain = -4096 dataout = -16384 expected = -16384 ... CHECK PASSED +TEST PASSED :-) diff --git a/ivtest/gold/pr1008.gold b/ivtest/gold/pr1008.gold new file mode 100644 index 000000000..4baa557cc --- /dev/null +++ b/ivtest/gold/pr1008.gold @@ -0,0 +1,4 @@ +b = x +b = 0 +b = 1 +b = 0 diff --git a/ivtest/gold/pr1026.gold b/ivtest/gold/pr1026.gold new file mode 100644 index 000000000..34382cfa2 --- /dev/null +++ b/ivtest/gold/pr1026.gold @@ -0,0 +1,31 @@ +index= 0, foo=00000000000000000000000000000001 +index= 1, foo=00000000000000000000000000000010 +index= 2, foo=00000000000000000000000000000100 +index= 3, foo=00000000000000000000000000001000 +index= 4, foo=00000000000000000000000000010000 +index= 5, foo=00000000000000000000000000100000 +index= 6, foo=00000000000000000000000001000000 +index= 7, foo=00000000000000000000000010000000 +index= 8, foo=00000000000000000000000100000000 +index= 9, foo=00000000000000000000001000000000 +index=10, foo=00000000000000000000010000000000 +index=11, foo=00000000000000000000100000000000 +index=12, foo=00000000000000000001000000000000 +index=13, foo=00000000000000000010000000000000 +index=14, foo=00000000000000000100000000000000 +index=15, foo=00000000000000001000000000000000 +index=16, foo=00000000000000010000000000000000 +index=17, foo=00000000000000100000000000000000 +index=18, foo=00000000000001000000000000000000 +index=19, foo=00000000000010000000000000000000 +index=20, foo=00000000000100000000000000000000 +index=21, foo=00000000001000000000000000000000 +index=22, foo=00000000010000000000000000000000 +index=23, foo=00000000100000000000000000000000 +index=24, foo=00000001000000000000000000000000 +index=25, foo=00000010000000000000000000000000 +index=26, foo=00000100000000000000000000000000 +index=27, foo=00001000000000000000000000000000 +index=28, foo=00010000000000000000000000000000 +index=29, foo=00100000000000000000000000000000 +index=30, foo=01000000000000000000000000000000 diff --git a/ivtest/gold/pr1033.gold b/ivtest/gold/pr1033.gold new file mode 100644 index 000000000..e44f557c5 --- /dev/null +++ b/ivtest/gold/pr1033.gold @@ -0,0 +1,10 @@ +7ffffff5 7ffffffa = 7ffffff5 +7ffffff6 7ffffffb = 7ffffff6 +7ffffff7 7ffffffc = 7ffffff7 +7ffffff8 7ffffffd = 7ffffff8 +7ffffff9 7ffffffe = 7ffffff9 +7ffffffa 7fffffff = 7ffffffa +7ffffffb 80000000 = 80000000 +7ffffffc 80000001 = 80000001 +7ffffffd 80000002 = 80000002 +7ffffffe 80000003 = 80000003 diff --git a/ivtest/gold/pr1065.gold b/ivtest/gold/pr1065.gold new file mode 100644 index 000000000..1ce2d4f1b --- /dev/null +++ b/ivtest/gold/pr1065.gold @@ -0,0 +1,3 @@ +Execution started. +BBCDBBCD +Execution finished. diff --git a/ivtest/gold/pr1077.gold b/ivtest/gold/pr1077.gold new file mode 100644 index 000000000..8a1df2ee0 --- /dev/null +++ b/ivtest/gold/pr1077.gold @@ -0,0 +1,6 @@ +one +y = x +one +y = 1 +one +y = 1 diff --git a/ivtest/gold/pr1403406.gold b/ivtest/gold/pr1403406.gold new file mode 100644 index 000000000..359768c6f --- /dev/null +++ b/ivtest/gold/pr1403406.gold @@ -0,0 +1,3 @@ +Time scale of (top) is 1s / 1s +Time scale of (other) is 1ms / 1ms +Time scale of (other2) is 1s / 1s diff --git a/ivtest/gold/pr1403406a.gold b/ivtest/gold/pr1403406a.gold new file mode 100644 index 000000000..3fc09e818 --- /dev/null +++ b/ivtest/gold/pr1403406a.gold @@ -0,0 +1,3 @@ +Time scale of (top) is 1ns / 1ns +Time scale of (other) is 1ms / 1ms +Time scale of (other2) is 1ns / 1ns diff --git a/ivtest/gold/pr1403406b.gold b/ivtest/gold/pr1403406b.gold new file mode 100644 index 000000000..5ef521ff1 --- /dev/null +++ b/ivtest/gold/pr1403406b.gold @@ -0,0 +1,5 @@ +Command File: Warning: default timescale is being set multiple times. + : using the last valid +timescale found. +Time scale of (top) is 1ns / 1ps +Time scale of (other) is 1ms / 1ms +Time scale of (other2) is 1ns / 1ps diff --git a/ivtest/gold/pr1476440.gold b/ivtest/gold/pr1476440.gold new file mode 100644 index 000000000..088830e6d --- /dev/null +++ b/ivtest/gold/pr1476440.gold @@ -0,0 +1,6 @@ +tval = 0 +tval = 2 +tval = 6 +tval = 10 +tval = 14 +tval = 18 diff --git a/ivtest/gold/pr1492075.gold b/ivtest/gold/pr1492075.gold new file mode 100644 index 000000000..779b208ab --- /dev/null +++ b/ivtest/gold/pr1492075.gold @@ -0,0 +1,11 @@ +clkb=0 at 0 +clkb=1 at 900 +clkb=0 at 2100 +clkb=1 at 2900 +clkb=0 at 4100 +clkb=1 at 4900 +clkb=0 at 6100 +clkb=1 at 6900 +clkb=0 at 8100 +clkb=1 at 8900 +clkb=0 at 10100 diff --git a/ivtest/gold/pr1494799.gold b/ivtest/gold/pr1494799.gold new file mode 100644 index 000000000..7426ca4ee --- /dev/null +++ b/ivtest/gold/pr1494799.gold @@ -0,0 +1,7 @@ +a = ffffb -5 +b = 00000 0 +c = 0000008 8 +z = 1ffffff, -1, 1111111111111111111111111 +y = 1ffffff, -1, 1111111111111111111111111 +w = 1ffffff, -1, 1111111111111111111111111 +1 1 1 1 diff --git a/ivtest/gold/pr1574175.gold b/ivtest/gold/pr1574175.gold new file mode 100644 index 000000000..f458fb921 --- /dev/null +++ b/ivtest/gold/pr1574175.gold @@ -0,0 +1 @@ +Both of these should be the same (3): 3, 3 diff --git a/ivtest/gold/pr1587669.gold b/ivtest/gold/pr1587669.gold new file mode 100644 index 000000000..12bb0ad39 --- /dev/null +++ b/ivtest/gold/pr1587669.gold @@ -0,0 +1,36 @@ +time=0: em=x, pz=0, p=00000 +time=1000: em=1, pz=0, p=00000 +time=10000: em=1, pz=0, p=00001 +time=11000: em=0, pz=0, p=00001 +time=20000: em=0, pz=0, p=00010 +time=21000: em=1, pz=0, p=00010 +time=21000: em=0, pz=0, p=00010 +time=30000: em=0, pz=0, p=00011 +time=40000: em=0, pz=0, p=00100 +time=50000: em=0, pz=0, p=00101 +time=60000: em=0, pz=0, p=00110 +time=70000: em=0, pz=0, p=00111 +time=80000: em=0, pz=0, p=01000 +time=90000: em=0, pz=0, p=01001 +time=100000: em=0, pz=0, p=01010 +time=110000: em=0, pz=0, p=01011 +time=120000: em=0, pz=0, p=01100 +time=130000: em=0, pz=0, p=01101 +time=140000: em=0, pz=0, p=01110 +time=150000: em=0, pz=0, p=01111 +time=160000: em=0, pz=0, p=10000 +time=170000: em=0, pz=0, p=10001 +time=180000: em=0, pz=0, p=10010 +time=190000: em=0, pz=0, p=10011 +time=200000: em=0, pz=0, p=10100 +time=210000: em=0, pz=0, p=10101 +time=220000: em=0, pz=0, p=10110 +time=230000: em=0, pz=0, p=10111 +time=240000: em=0, pz=0, p=11000 +time=250000: em=0, pz=0, p=11001 +time=260000: em=0, pz=0, p=11010 +time=270000: em=0, pz=0, p=11011 +time=280000: em=0, pz=0, p=11100 +time=290000: em=0, pz=0, p=11101 +time=300000: em=0, pz=0, p=11110 +time=310000: em=0, pz=0, p=11111 diff --git a/ivtest/gold/pr1589497.gold b/ivtest/gold/pr1589497.gold new file mode 100644 index 000000000..b0a3c58ee --- /dev/null +++ b/ivtest/gold/pr1589497.gold @@ -0,0 +1,11 @@ +mydata = -5 +mydata = -4 +mydata = -3 +mydata = -2 +mydata = -1 +mydata = 0 +mydata = 1 +mydata = 2 +mydata = 3 +mydata = 4 +mydata = 5 diff --git a/ivtest/gold/pr1623097.gold b/ivtest/gold/pr1623097.gold new file mode 100644 index 000000000..409d71392 --- /dev/null +++ b/ivtest/gold/pr1623097.gold @@ -0,0 +1,9 @@ + 0 clk=0, data=1111, clear=1111, state=0000 + 10 clk=0, data=1111, clear=0000, state=0000 + 20 clk=1, data=1111, clear=0000, state=0000 + 21 clk=1, data=1111, clear=0000, state=1111 + 30 clk=0, data=1111, clear=0010, state=1101 + 40 clk=0, data=1010, clear=0000, state=1101 + 50 clk=1, data=1010, clear=0000, state=1101 + 51 clk=1, data=1010, clear=0000, state=1010 + 60 clk=0, data=1010, clear=0000, state=1010 diff --git a/ivtest/gold/pr1628288.gold b/ivtest/gold/pr1628288.gold new file mode 100644 index 000000000..7d12ee6b9 --- /dev/null +++ b/ivtest/gold/pr1628288.gold @@ -0,0 +1,36 @@ + Reading bit 7 + Reading bit 6 + Reading bit 5 + Reading bit 4 + Reading bit 3 + Reading bit 2 + Reading bit 1 + Reading bit 0 +Read(0) 01010101 from the bit stream. + Reading bit 7 + Reading bit 6 + Reading bit 5 + Reading bit 4 + Reading bit 3 + Reading bit 2 + Reading bit 1 + Reading bit 0 +Read(1) 10101010 from the bit stream. + Reading bit 7 + Reading bit 6 + Reading bit 5 + Reading bit 4 + Reading bit 3 + Reading bit 2 + Reading bit 1 + Reading bit 0 +Read(2) 01010101 from the bit stream. + Reading bit 7 + Reading bit 6 + Reading bit 5 + Reading bit 4 + Reading bit 3 + Reading bit 2 + Reading bit 1 + Reading bit 0 +Read(3) 10101010 from the bit stream. diff --git a/ivtest/gold/pr1628300.gold b/ivtest/gold/pr1628300.gold new file mode 100644 index 000000000..5509bbea3 --- /dev/null +++ b/ivtest/gold/pr1628300.gold @@ -0,0 +1 @@ +sin(2) is not really 3.14159 diff --git a/ivtest/gold/pr1629683.gold b/ivtest/gold/pr1629683.gold new file mode 100644 index 000000000..1fa2c3516 --- /dev/null +++ b/ivtest/gold/pr1629683.gold @@ -0,0 +1,2 @@ +Printing the byte 01010101 with a header. +Bad - 1x01010101, ok - 1x01010101. diff --git a/ivtest/gold/pr1632861.gold b/ivtest/gold/pr1632861.gold new file mode 100644 index 000000000..43275f46e --- /dev/null +++ b/ivtest/gold/pr1632861.gold @@ -0,0 +1,7 @@ +At 1 value is 0000000000 +At 2 value is 00000xxxxx +At 3 value is 1111111111 +At 4 value is 00000xxxxx +At 5 value is 0000000000 +At 6 value is 00xxxxxxxx +At 7 value is 0000000000 diff --git a/ivtest/gold/pr1634526.gold b/ivtest/gold/pr1634526.gold new file mode 100644 index 000000000..6e976c0b0 --- /dev/null +++ b/ivtest/gold/pr1634526.gold @@ -0,0 +1,4 @@ +Working: This (255) should be 255. +Broken: This (255) should be 255 +Broken: This (255) should be 255. + started with 256. diff --git a/ivtest/gold/pr1636409.gold b/ivtest/gold/pr1636409.gold new file mode 100644 index 000000000..e666d3c7a --- /dev/null +++ b/ivtest/gold/pr1636409.gold @@ -0,0 +1,6 @@ +fail=x0x0, good=x0x0, en=0 at 1 +fail=0000, good=0000, en=0 at 2 +fail=0000, good=0000, en=1 at 11 +fail=0101, good=0101, en=1 at 12 +fail=1010, good=1010, en=0 at 31 +fail=0000, good=0000, en=0 at 32 diff --git a/ivtest/gold/pr1638985.gold b/ivtest/gold/pr1638985.gold new file mode 100644 index 000000000..9ceff52d1 --- /dev/null +++ b/ivtest/gold/pr1638985.gold @@ -0,0 +1,5 @@ +Hello, World +Positive x is 1.000000 +-1.0 * x is -1.000000 +0.0 - x is -1.000000 +-x is -1.000000 diff --git a/ivtest/gold/pr1639060.gold b/ivtest/gold/pr1639060.gold new file mode 100644 index 000000000..22984dcbd --- /dev/null +++ b/ivtest/gold/pr1639060.gold @@ -0,0 +1,2 @@ +1. The result is 10.0 +2. The result is 10.0 diff --git a/ivtest/gold/pr1639064.gold b/ivtest/gold/pr1639064.gold new file mode 100644 index 000000000..39bd64e69 --- /dev/null +++ b/ivtest/gold/pr1639064.gold @@ -0,0 +1,5 @@ +1. The value is 100 +2. The value is 100 +3. The value is 100 +4. The value is 100 +5. The value is 100 diff --git a/ivtest/gold/pr1639064b.gold b/ivtest/gold/pr1639064b.gold new file mode 100644 index 000000000..2d5b0189a --- /dev/null +++ b/ivtest/gold/pr1639064b.gold @@ -0,0 +1,5 @@ +1. The value is 100000000 +2. The value is 100000000 +3. The value is 100 +4. The value is 100 +5. The value is 276447232 diff --git a/ivtest/gold/pr1639968.gold b/ivtest/gold/pr1639968.gold new file mode 100644 index 000000000..ce818c6cf --- /dev/null +++ b/ivtest/gold/pr1639968.gold @@ -0,0 +1,3 @@ + 0 rf[0] is ffff ffff + 10 rf[0] is 0000 0000 + 20 rf[0] is beef beef diff --git a/ivtest/gold/pr1639971.gold b/ivtest/gold/pr1639971.gold new file mode 100644 index 000000000..1b75891d3 --- /dev/null +++ b/ivtest/gold/pr1639971.gold @@ -0,0 +1,3 @@ + 0 rf and slice: ffff f + 10 rf and slice: 0000 0 + 20 rf and slice: beef f diff --git a/ivtest/gold/pr1645277.gold b/ivtest/gold/pr1645277.gold new file mode 100644 index 000000000..d0e19304d --- /dev/null +++ b/ivtest/gold/pr1645277.gold @@ -0,0 +1 @@ +expected 5; got 5 diff --git a/ivtest/gold/pr1645518.gold b/ivtest/gold/pr1645518.gold new file mode 100644 index 000000000..16f19ddba --- /dev/null +++ b/ivtest/gold/pr1645518.gold @@ -0,0 +1,7 @@ + 0 A = x B = x C = x D = x, eSeg = x + 10 A = 0 B = 0 C = 0 D = 0, eSeg = x + 12 A = 0 B = 0 C = 0 D = 0, eSeg = 1 + 20 A = 0 B = 0 C = 0 D = 1, eSeg = 1 + 22 A = 0 B = 0 C = 0 D = 1, eSeg = 0 + 30 A = 0 B = 0 C = 1 D = 0, eSeg = 0 + 32 A = 0 B = 0 C = 1 D = 0, eSeg = 1 diff --git a/ivtest/gold/pr1648365.gold b/ivtest/gold/pr1648365.gold new file mode 100644 index 000000000..b869ab0f3 --- /dev/null +++ b/ivtest/gold/pr1648365.gold @@ -0,0 +1,2 @@ + 0 w0=xxxxxxxx, w1=xxxxxxxx + 31 w0=19999999, w1=2aaaaaaa diff --git a/ivtest/gold/pr1661640.gold b/ivtest/gold/pr1661640.gold new file mode 100644 index 000000000..f9e7a0f92 --- /dev/null +++ b/ivtest/gold/pr1661640.gold @@ -0,0 +1,9 @@ +Hello world! +Hello world! + +hello1; escaped NL: +Hello world! +0048656c6c6f20776f726c64210a +hello2; octal NL: +Hello world! +0048656c6c6f20776f726c64210a diff --git a/ivtest/gold/pr1661640_std.gold b/ivtest/gold/pr1661640_std.gold new file mode 100644 index 000000000..b6d8667d6 --- /dev/null +++ b/ivtest/gold/pr1661640_std.gold @@ -0,0 +1,9 @@ +Hello world! +Hello world! + +hello1; escaped NL: +Hello world! +0048656c6c6f20776f726c64210a +hello2; octal NL: +Hello world! +0048656c6c6f20776f726c64210a diff --git a/ivtest/gold/pr1664684.gold b/ivtest/gold/pr1664684.gold new file mode 100644 index 000000000..a49238da9 --- /dev/null +++ b/ivtest/gold/pr1664684.gold @@ -0,0 +1,2 @@ + 0 x x0 x 0 + 40 0 00 0 0 diff --git a/ivtest/gold/pr1687193.gold b/ivtest/gold/pr1687193.gold new file mode 100644 index 000000000..e1fcc0c5b --- /dev/null +++ b/ivtest/gold/pr1687193.gold @@ -0,0 +1,5 @@ + Line 1 matches 3 args: 00000000 00000001 00000002 + Line 2 matches 3 args: 00000003 00000004 00000005 + Line 3 matches 2 args: 00000006 00000007 00000005 + Line 4 matches 0 args: 00000006 00000007 00000005 + Line 5 matches 3 args: 00000009 0000000a 0000000b diff --git a/ivtest/gold/pr1688717.gold b/ivtest/gold/pr1688717.gold new file mode 100644 index 000000000..c92c409e9 --- /dev/null +++ b/ivtest/gold/pr1688717.gold @@ -0,0 +1,2 @@ +Orig = 123456, Second = 34, Minus Indexed = 34, Plus Indexed = 34 +Orig = 123456, Second = 34, Minus Indexed = 34, Plus Indexed = 34 diff --git a/ivtest/gold/pr1698499.gold b/ivtest/gold/pr1698499.gold new file mode 100644 index 000000000..2cc703680 --- /dev/null +++ b/ivtest/gold/pr1698499.gold @@ -0,0 +1,3 @@ +reset +reset done +OK: 662372300238342615234 * -6 + -662372300237642615234 == -4636606101667698306638 diff --git a/ivtest/gold/pr1698658.gold b/ivtest/gold/pr1698658.gold new file mode 100644 index 000000000..ed8a7f6bb --- /dev/null +++ b/ivtest/gold/pr1698658.gold @@ -0,0 +1,2 @@ +The time is 0 uS +The time is 1 uS diff --git a/ivtest/gold/pr1698659.gold b/ivtest/gold/pr1698659.gold new file mode 100644 index 000000000..d1dd903d3 --- /dev/null +++ b/ivtest/gold/pr1698659.gold @@ -0,0 +1,7 @@ +top var is (0) +top.lwr var is (1) +top.lwr.elwr var is (0) +Up reference to me (0) +Up reference to parent (1) +Up reference is (1) +othertop var is (1) diff --git a/ivtest/gold/pr1698820-v10.gold b/ivtest/gold/pr1698820-v10.gold new file mode 100644 index 000000000..e3cb7d143 --- /dev/null +++ b/ivtest/gold/pr1698820-v10.gold @@ -0,0 +1,8 @@ +The variable is 10 +The variable is 01010 +The variable is 12 +The variable is 0a +The variable is 10 +The variable is 01010 +The variable is 12 +The variable is 0a diff --git a/ivtest/gold/pr1698820-vlog95.gold b/ivtest/gold/pr1698820-vlog95.gold new file mode 100644 index 000000000..bcbff310d --- /dev/null +++ b/ivtest/gold/pr1698820-vlog95.gold @@ -0,0 +1,9 @@ +The variable is 10 +The variable is 01010 +The variable is 12 +The variable is 0a +The variable is 10 +The variable is 01010 +The variable is 12 +The variable is 0a +WARNING: vlog95.v:25: could not close MCD STDOUT (0x1) in $fclose(). diff --git a/ivtest/gold/pr1698820.gold b/ivtest/gold/pr1698820.gold new file mode 100644 index 000000000..c79d8480f --- /dev/null +++ b/ivtest/gold/pr1698820.gold @@ -0,0 +1,9 @@ +The variable is 10 +The variable is 01010 +The variable is 12 +The variable is 0a +The variable is 10 +The variable is 01010 +The variable is 12 +The variable is 0a +WARNING: ./ivltests/pr1698820.v:17: could not close MCD STDOUT (0x1) in $fclose(). diff --git a/ivtest/gold/pr1699444.gold b/ivtest/gold/pr1699444.gold new file mode 100644 index 000000000..10fefeaf4 --- /dev/null +++ b/ivtest/gold/pr1699444.gold @@ -0,0 +1,2 @@ +Output a slash \. +Output a double slash \\. diff --git a/ivtest/gold/pr1699519.gold b/ivtest/gold/pr1699519.gold new file mode 100644 index 000000000..b77e314c2 --- /dev/null +++ b/ivtest/gold/pr1699519.gold @@ -0,0 +1,4 @@ +Checking h and H: a5, a5 +Checking x and X: a5, a5 +Checking g and G: 1.23457e+09, 1.23457E+09 +Checking e and E: 1.234568e+09, 1.234568E+09 diff --git a/ivtest/gold/pr1701855.gold b/ivtest/gold/pr1701855.gold new file mode 100644 index 000000000..65dc0e7d3 --- /dev/null +++ b/ivtest/gold/pr1701855.gold @@ -0,0 +1,5 @@ +Time scale of (top) is 1us / 1ns +Time scale of (top) is 1us / 1ns +Time scale of (top.dut) is 10ns / 10ps +Time scale of (top.dut.dut) is 1ns / 10ps +Time scale of (othertop) is 1ms / 1us diff --git a/ivtest/gold/pr1701855b.gold b/ivtest/gold/pr1701855b.gold new file mode 100644 index 000000000..5b777c985 --- /dev/null +++ b/ivtest/gold/pr1701855b.gold @@ -0,0 +1,25 @@ +Time scale of (dummy) is 100ns / 100ps +Time scale of (dummy.ipval) is 100ns / 100ps +Time scale of (top) is 1us / 1ns +Time scale of (top.ipval) is 1us / 1ns +Time scale of (top.spval) is 1us / 1ns +Time scale of (top.rpval) is 1us / 1ns +Time scale of (top.evt) is 1us / 1ns +Time scale of (top.rgval) is 1us / 1ns +Time scale of (top.rgval[0:0]) is 1us / 1ns +Time scale of (top.rgarr) is 1us / 1ns +Time scale of (top.rgarr[0]) is 1us / 1ns +Time scale of (top.wval) is 1us / 1ns +Time scale of (top.wval[0:0]) is 1us / 1ns +Time scale of (top.warr) is 1us / 1ns +Time scale of (top.warr[0]) is 1us / 1ns +Time scale of (top.ival) is 1us / 1ns +Time scale of (top.ival[1:1]) is 1us / 1ns +Time scale of (top.rval) is 1us / 1ns +Time scale of (top.rarr) is 1us / 1ns +Time scale of (top.rarr[0]) is 1us / 1ns +Time scale of (top.tval) is 1us / 1ns +Time scale of (top.blk) is 1us / 1ns +Time scale of (top.frk) is 1us / 1ns +Time scale of (top.tsk) is 1us / 1ns +Time scale of (top.fnc) is 1us / 1ns diff --git a/ivtest/gold/pr1701889.gold b/ivtest/gold/pr1701889.gold new file mode 100644 index 000000000..d9abd962d --- /dev/null +++ b/ivtest/gold/pr1701889.gold @@ -0,0 +1,15 @@ +----- Using real times ----- +The time one unit ago was : 0 +The time one unit ago was : 0 +The time now is : 1 +One time unit from now it will be: 2 +The time at 20 will be : 20 +The time at 40 will be : 40 + +----- Using integer times ----- +The time one unit ago was : 100 +The time one unit ago was : 100 +The time now is : 101 +One time unit from now it will be: 102 +The time at 120 will be : 120 +The time at 140 will be : 140 diff --git a/ivtest/gold/pr1701890-ivl.gold b/ivtest/gold/pr1701890-ivl.gold new file mode 100644 index 000000000..7dc1c401c --- /dev/null +++ b/ivtest/gold/pr1701890-ivl.gold @@ -0,0 +1 @@ +rval1=1.00000 rval2=2.00000 rtval=1.00000 diff --git a/ivtest/gold/pr1701890.gold b/ivtest/gold/pr1701890.gold new file mode 100644 index 000000000..4d7f677a5 --- /dev/null +++ b/ivtest/gold/pr1701890.gold @@ -0,0 +1 @@ +rval1=1 rval2=2 rtval=1 diff --git a/ivtest/gold/pr1702593.gold b/ivtest/gold/pr1702593.gold new file mode 100644 index 000000000..057ca6d19 --- /dev/null +++ b/ivtest/gold/pr1702593.gold @@ -0,0 +1,2 @@ +The value is -1.00 +The value is -1.00 diff --git a/ivtest/gold/pr1703120.gold b/ivtest/gold/pr1703120.gold new file mode 100644 index 000000000..12b06cfba --- /dev/null +++ b/ivtest/gold/pr1703120.gold @@ -0,0 +1,19 @@ +--- Printing as real --- +1/0 is 0.000000. (Should be 0 -- x prints as 0) +1/0.0 is inf. (Should be inf) +1.0/0 is inf. (Should be inf) +1.0/0.0 is inf. (should be inf) +1/integer zero is 0.000000. (Should be 0 -- x prints as 0) +1/real zero is inf. (should be inf) +1.0/integer zero is inf. (Should be inf) +1.0/real zero is inf. + +--- Printing as integer --- +1/0 is x (Should be x) +1/0.0 is inf +1.0/0 is inf +1.0/0.0 is inf +1/integer zero is x. (Should be x) +1/real zero is inf. +1.0/integer zero is inf. +1.0/real zero is inf. diff --git a/ivtest/gold/pr1704726a-v10.gold b/ivtest/gold/pr1704726a-v10.gold new file mode 100644 index 000000000..101864e94 --- /dev/null +++ b/ivtest/gold/pr1704726a-v10.gold @@ -0,0 +1,14 @@ +./ivltests/pr1704726a.v:8: error: duplicate definition for parameter 'name_pp' in 'top'. +./ivltests/pr1704726a.v:11: error: parameter and localparam in 'top' have the same name 'name_pl'. +./ivltests/pr1704726a.v:14: error: localparam and parameter in 'top' have the same name 'name_lp'. +./ivltests/pr1704726a.v:17: error: duplicate definition for localparam 'name_ll' in 'top'. +./ivltests/pr1704726a.v:24: error: genvar 'name_vv' has already been declared. +./ivltests/pr1704726a.v:23: the previous declaration is here. +./ivltests/pr1704726a.v:33: error: duplicate definition for task 'name_tt' in 'top'. +./ivltests/pr1704726a.v:43: error: duplicate definition for task 'name_tt' in 'top' (generate). +./ivltests/pr1704726a.v:39: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726a.v:57: error: duplicate definition for function 'name_ff' in 'top'. +./ivltests/pr1704726a.v:69: error: duplicate definition for function 'name_ff' in 'top' (generate). +./ivltests/pr1704726a.v:64: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726a.v:81: error: duplicate definition for named event 'name_ee' in 'top'. +./ivltests/pr1704726a.v:87: error: duplicate definition for specparam 'name_ss' in 'top'. diff --git a/ivtest/gold/pr1704726a.gold b/ivtest/gold/pr1704726a.gold new file mode 100644 index 000000000..ff3d4d107 --- /dev/null +++ b/ivtest/gold/pr1704726a.gold @@ -0,0 +1,26 @@ +./ivltests/pr1704726a.v:8: error: 'name_pp' has already been declared in this scope. +./ivltests/pr1704726a.v:7: : It was declared here as a parameter. +./ivltests/pr1704726a.v:11: error: 'name_pl' has already been declared in this scope. +./ivltests/pr1704726a.v:10: : It was declared here as a parameter. +./ivltests/pr1704726a.v:14: error: 'name_lp' has already been declared in this scope. +./ivltests/pr1704726a.v:13: : It was declared here as a parameter. +./ivltests/pr1704726a.v:17: error: 'name_ll' has already been declared in this scope. +./ivltests/pr1704726a.v:16: : It was declared here as a parameter. +./ivltests/pr1704726a.v:24: error: 'name_vv' has already been declared in this scope. +./ivltests/pr1704726a.v:23: : It was declared here as a genvar. +./ivltests/pr1704726a.v:33: error: 'name_tt' has already been declared in this scope. +./ivltests/pr1704726a.v:30: : It was declared here as a task. +./ivltests/pr1704726a.v:43: error: 'name_tt' has already been declared in this scope. +./ivltests/pr1704726a.v:40: : It was declared here as a task. +./ivltests/pr1704726a.v:39: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726a.v:57: error: 'name_ff' has already been declared in this scope. +./ivltests/pr1704726a.v:53: : It was declared here as a function. +./ivltests/pr1704726a.v:64: error: 'task_blk' has already been declared in this scope. +./ivltests/pr1704726a.v:39: : It was declared here as a generate block. +./ivltests/pr1704726a.v:69: error: 'name_ff' has already been declared in this scope. +./ivltests/pr1704726a.v:65: : It was declared here as a function. +./ivltests/pr1704726a.v:64: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726a.v:81: error: 'name_ee' has already been declared in this scope. +./ivltests/pr1704726a.v:80: : It was declared here as an event. +./ivltests/pr1704726a.v:87: error: 'name_ss' has already been declared in this scope. +./ivltests/pr1704726a.v:86: : It was declared here as a parameter. diff --git a/ivtest/gold/pr1704726c-v10.gold b/ivtest/gold/pr1704726c-v10.gold new file mode 100644 index 000000000..1a9001c9a --- /dev/null +++ b/ivtest/gold/pr1704726c-v10.gold @@ -0,0 +1,66 @@ +./ivltests/pr1704726c.v:517: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:527: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:538: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:551: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:559: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:569: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:577: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:584: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:589: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:4: error: parameter and genvar in 'top' have the same name 'name_v'. +./ivltests/pr1704726c.v:5: error: localparam and genvar in 'top' have the same name 'name_lpv'. +./ivltests/pr1704726c.v:46: error: task and parameter in 'top' have the same name 'name_t'. +./ivltests/pr1704726c.v:60: error: task and genvar in 'top' have the same name 'name_tv'. +./ivltests/pr1704726c.v:68: error: function and parameter in 'top' have the same name 'name_f'. +./ivltests/pr1704726c.v:77: error: function and task in 'top' have the same name 'name_ft'. +./ivltests/pr1704726c.v:92: error: function and genvar in 'top' have the same name 'name_fv'. +./ivltests/pr1704726c.v:101: error: module instance and parameter in 'top' have the same name 'name_i'. +./ivltests/pr1704726c.v:107: error: module instance and task in 'top' have the same name 'name_it'. +./ivltests/pr1704726c.v:114: error: module instance and function in 'top' have the same name 'name_if'. +./ivltests/pr1704726c.v:123: error: module instance and genvar in 'top' have the same name 'name_iv'. +./ivltests/pr1704726c.v:127: error: module instance and module instance in 'top' have the same name 'name_ii'. +./ivltests/pr1704726c.v:133: error: named block and parameter in 'top' have the same name 'name_b'. +./ivltests/pr1704726c.v:141: error: named block and task in 'top' have the same name 'name_bt'. +./ivltests/pr1704726c.v:150: error: named block and function in 'top' have the same name 'name_bf'. +./ivltests/pr1704726c.v:161: error: named block and genvar in 'top' have the same name 'name_bv'. +./ivltests/pr1704726c.v:167: error: named block and module instance in 'top' have the same name 'name_bi'. +./ivltests/pr1704726c.v:175: error: named block and sequential block in 'top' have the same name 'name_bb'. +./ivltests/pr1704726c.v:183: error: named event and parameter in 'top' have the same name 'name_e'. +./ivltests/pr1704726c.v:215: error: named event and sequential block in 'top' have the same name 'name_eb'. +./ivltests/pr1704726c.v:196: error: named event and function in 'top' have the same name 'name_ef'. +./ivltests/pr1704726c.v:209: error: named event and module instance in 'top' have the same name 'name_ei'. +./ivltests/pr1704726c.v:189: error: named event and task in 'top' have the same name 'name_et'. +./ivltests/pr1704726c.v:205: error: named event and genvar in 'top' have the same name 'name_ev'. +./ivltests/pr1704726c.v:226: error: generate "loop" and parameter in 'top' have the same name 'name_gl'. +./ivltests/pr1704726c.v:236: error: generate "loop" and task in 'top' have the same name 'name_glt'. +./ivltests/pr1704726c.v:247: error: generate "loop" and function in 'top' have the same name 'name_glf'. +./ivltests/pr1704726c.v:260: error: generate "loop" and genvar in 'top' have the same name 'name_glv'. +./ivltests/pr1704726c.v:268: error: generate "loop" and module instance in 'top' have the same name 'name_gli'. +./ivltests/pr1704726c.v:278: error: generate "loop" and sequential block in 'top' have the same name 'name_glb'. +./ivltests/pr1704726c.v:286: error: generate "loop" and named event in 'top' have the same name 'name_gle'. +./ivltests/pr1704726c.v:298: error: generate "loop" and generate block in 'top' have the same name 'name_glgl'. +./ivltests/pr1704726c.v:308: error: generate "if" and parameter in 'top' have the same name 'name_gi'. +./ivltests/pr1704726c.v:318: error: generate "if" and task in 'top' have the same name 'name_git'. +./ivltests/pr1704726c.v:329: error: generate "if" and function in 'top' have the same name 'name_gif'. +./ivltests/pr1704726c.v:342: error: generate "if" and genvar in 'top' have the same name 'name_giv'. +./ivltests/pr1704726c.v:350: error: generate "if" and module instance in 'top' have the same name 'name_gii'. +./ivltests/pr1704726c.v:360: error: generate "if" and sequential block in 'top' have the same name 'name_gib'. +./ivltests/pr1704726c.v:368: error: generate "if" and named event in 'top' have the same name 'name_gie'. +./ivltests/pr1704726c.v:380: error: generate "if" and generate block in 'top' have the same name 'name_gigi'. +./ivltests/pr1704726c.v:390: error: generate "case" and parameter in 'top' have the same name 'name_gc'. +./ivltests/pr1704726c.v:405: error: generate "case" and task in 'top' have the same name 'name_gct'. +./ivltests/pr1704726c.v:421: error: generate "case" and function in 'top' have the same name 'name_gcf'. +./ivltests/pr1704726c.v:439: error: generate "case" and genvar in 'top' have the same name 'name_gcv'. +./ivltests/pr1704726c.v:452: error: generate "case" and module instance in 'top' have the same name 'name_gci'. +./ivltests/pr1704726c.v:467: error: generate "case" and sequential block in 'top' have the same name 'name_gcb'. +./ivltests/pr1704726c.v:480: error: generate "case" and named event in 'top' have the same name 'name_gce'. +./ivltests/pr1704726c.v:502: error: generate "case" and generate block in 'top' have the same name 'name_gcgc'. +./ivltests/pr1704726c.v:517: error: generate "block" and parameter in 'top' have the same name 'name_gb'. +./ivltests/pr1704726c.v:527: error: generate "block" and task in 'top' have the same name 'name_gbt'. +./ivltests/pr1704726c.v:538: error: generate "block" and function in 'top' have the same name 'name_gbf'. +./ivltests/pr1704726c.v:551: error: generate "block" and genvar in 'top' have the same name 'name_gbv'. +./ivltests/pr1704726c.v:559: error: generate "block" and module instance in 'top' have the same name 'name_gbi'. +./ivltests/pr1704726c.v:569: error: generate "block" and sequential block in 'top' have the same name 'name_gbb'. +./ivltests/pr1704726c.v:577: error: generate "block" and named event in 'top' have the same name 'name_gbe'. +./ivltests/pr1704726c.v:589: error: generate "block" and generate block in 'top' have the same name 'name_gbgb'. +57 error(s) during elaboration. diff --git a/ivtest/gold/pr1704726c.gold b/ivtest/gold/pr1704726c.gold new file mode 100644 index 000000000..87875f43e --- /dev/null +++ b/ivtest/gold/pr1704726c.gold @@ -0,0 +1,121 @@ +./ivltests/pr1704726c.v:24: error: 'name_v' has already been declared in this scope. +./ivltests/pr1704726c.v:4: : It was declared here as a parameter. +./ivltests/pr1704726c.v:32: error: 'name_lpv' has already been declared in this scope. +./ivltests/pr1704726c.v:5: : It was declared here as a parameter. +./ivltests/pr1704726c.v:46: error: 'name_t' has already been declared in this scope. +./ivltests/pr1704726c.v:7: : It was declared here as a parameter. +./ivltests/pr1704726c.v:60: error: 'name_tv' has already been declared in this scope. +./ivltests/pr1704726c.v:54: : It was declared here as a genvar. +./ivltests/pr1704726c.v:68: error: 'name_f' has already been declared in this scope. +./ivltests/pr1704726c.v:8: : It was declared here as a parameter. +./ivltests/pr1704726c.v:77: error: 'name_ft' has already been declared in this scope. +./ivltests/pr1704726c.v:74: : It was declared here as a task. +./ivltests/pr1704726c.v:92: error: 'name_fv' has already been declared in this scope. +./ivltests/pr1704726c.v:86: : It was declared here as a genvar. +./ivltests/pr1704726c.v:101: error: 'name_i' has already been declared in this scope. +./ivltests/pr1704726c.v:9: : It was declared here as a parameter. +./ivltests/pr1704726c.v:107: error: 'name_it' has already been declared in this scope. +./ivltests/pr1704726c.v:104: : It was declared here as a task. +./ivltests/pr1704726c.v:114: error: 'name_if' has already been declared in this scope. +./ivltests/pr1704726c.v:110: : It was declared here as a function. +./ivltests/pr1704726c.v:123: error: 'name_iv' has already been declared in this scope. +./ivltests/pr1704726c.v:117: : It was declared here as a genvar. +./ivltests/pr1704726c.v:127: error: 'name_ii' has already been declared in this scope. +./ivltests/pr1704726c.v:126: : It was declared here as an instance name. +./ivltests/pr1704726c.v:133: error: 'name_b' has already been declared in this scope. +./ivltests/pr1704726c.v:10: : It was declared here as a parameter. +./ivltests/pr1704726c.v:141: error: 'name_bt' has already been declared in this scope. +./ivltests/pr1704726c.v:138: : It was declared here as a task. +./ivltests/pr1704726c.v:150: error: 'name_bf' has already been declared in this scope. +./ivltests/pr1704726c.v:146: : It was declared here as a function. +./ivltests/pr1704726c.v:161: error: 'name_bv' has already been declared in this scope. +./ivltests/pr1704726c.v:155: : It was declared here as a genvar. +./ivltests/pr1704726c.v:167: error: 'name_bi' has already been declared in this scope. +./ivltests/pr1704726c.v:166: : It was declared here as an instance name. +./ivltests/pr1704726c.v:175: error: 'name_bb' has already been declared in this scope. +./ivltests/pr1704726c.v:172: : It was declared here as a named block. +./ivltests/pr1704726c.v:183: error: 'name_e' has already been declared in this scope. +./ivltests/pr1704726c.v:15: : It was declared here as a parameter. +./ivltests/pr1704726c.v:189: error: 'name_et' has already been declared in this scope. +./ivltests/pr1704726c.v:186: : It was declared here as a task. +./ivltests/pr1704726c.v:196: error: 'name_ef' has already been declared in this scope. +./ivltests/pr1704726c.v:192: : It was declared here as a function. +./ivltests/pr1704726c.v:205: error: 'name_ev' has already been declared in this scope. +./ivltests/pr1704726c.v:199: : It was declared here as a genvar. +./ivltests/pr1704726c.v:209: error: 'name_ei' has already been declared in this scope. +./ivltests/pr1704726c.v:208: : It was declared here as an instance name. +./ivltests/pr1704726c.v:215: error: 'name_eb' has already been declared in this scope. +./ivltests/pr1704726c.v:212: : It was declared here as a named block. +./ivltests/pr1704726c.v:226: error: 'name_gl' has already been declared in this scope. +./ivltests/pr1704726c.v:11: : It was declared here as a parameter. +./ivltests/pr1704726c.v:236: error: 'name_glt' has already been declared in this scope. +./ivltests/pr1704726c.v:232: : It was declared here as a task. +./ivltests/pr1704726c.v:247: error: 'name_glf' has already been declared in this scope. +./ivltests/pr1704726c.v:242: : It was declared here as a function. +./ivltests/pr1704726c.v:260: error: 'name_glv' has already been declared in this scope. +./ivltests/pr1704726c.v:253: : It was declared here as a genvar. +./ivltests/pr1704726c.v:268: error: 'name_gli' has already been declared in this scope. +./ivltests/pr1704726c.v:266: : It was declared here as an instance name. +./ivltests/pr1704726c.v:278: error: 'name_glb' has already been declared in this scope. +./ivltests/pr1704726c.v:274: : It was declared here as a named block. +./ivltests/pr1704726c.v:286: error: 'name_gle' has already been declared in this scope. +./ivltests/pr1704726c.v:284: : It was declared here as an event. +./ivltests/pr1704726c.v:298: error: 'name_glgl' has already been declared in this scope. +./ivltests/pr1704726c.v:293: : It was declared here as a generate block. +./ivltests/pr1704726c.v:308: error: 'name_gi' has already been declared in this scope. +./ivltests/pr1704726c.v:12: : It was declared here as a parameter. +./ivltests/pr1704726c.v:318: error: 'name_git' has already been declared in this scope. +./ivltests/pr1704726c.v:314: : It was declared here as a task. +./ivltests/pr1704726c.v:329: error: 'name_gif' has already been declared in this scope. +./ivltests/pr1704726c.v:324: : It was declared here as a function. +./ivltests/pr1704726c.v:342: error: 'name_giv' has already been declared in this scope. +./ivltests/pr1704726c.v:335: : It was declared here as a genvar. +./ivltests/pr1704726c.v:350: error: 'name_gii' has already been declared in this scope. +./ivltests/pr1704726c.v:348: : It was declared here as an instance name. +./ivltests/pr1704726c.v:360: error: 'name_gib' has already been declared in this scope. +./ivltests/pr1704726c.v:356: : It was declared here as a named block. +./ivltests/pr1704726c.v:368: error: 'name_gie' has already been declared in this scope. +./ivltests/pr1704726c.v:366: : It was declared here as an event. +./ivltests/pr1704726c.v:380: error: 'name_gigi' has already been declared in this scope. +./ivltests/pr1704726c.v:375: : It was declared here as a generate block. +./ivltests/pr1704726c.v:391: error: 'name_gc' has already been declared in this scope. +./ivltests/pr1704726c.v:13: : It was declared here as a parameter. +./ivltests/pr1704726c.v:406: error: 'name_gct' has already been declared in this scope. +./ivltests/pr1704726c.v:401: : It was declared here as a task. +./ivltests/pr1704726c.v:422: error: 'name_gcf' has already been declared in this scope. +./ivltests/pr1704726c.v:416: : It was declared here as a function. +./ivltests/pr1704726c.v:440: error: 'name_gcv' has already been declared in this scope. +./ivltests/pr1704726c.v:432: : It was declared here as a genvar. +./ivltests/pr1704726c.v:453: error: 'name_gci' has already been declared in this scope. +./ivltests/pr1704726c.v:450: : It was declared here as an instance name. +./ivltests/pr1704726c.v:468: error: 'name_gcb' has already been declared in this scope. +./ivltests/pr1704726c.v:463: : It was declared here as a named block. +./ivltests/pr1704726c.v:481: error: 'name_gce' has already been declared in this scope. +./ivltests/pr1704726c.v:478: : It was declared here as an event. +./ivltests/pr1704726c.v:503: error: 'name_gcgc' has already been declared in this scope. +./ivltests/pr1704726c.v:493: : It was declared here as a generate block. +./ivltests/pr1704726c.v:517: error: 'name_gb' has already been declared in this scope. +./ivltests/pr1704726c.v:14: : It was declared here as a parameter. +./ivltests/pr1704726c.v:517: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:527: error: 'name_gbt' has already been declared in this scope. +./ivltests/pr1704726c.v:523: : It was declared here as a task. +./ivltests/pr1704726c.v:527: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:538: error: 'name_gbf' has already been declared in this scope. +./ivltests/pr1704726c.v:533: : It was declared here as a function. +./ivltests/pr1704726c.v:538: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:551: error: 'name_gbv' has already been declared in this scope. +./ivltests/pr1704726c.v:544: : It was declared here as a genvar. +./ivltests/pr1704726c.v:551: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:559: error: 'name_gbi' has already been declared in this scope. +./ivltests/pr1704726c.v:557: : It was declared here as an instance name. +./ivltests/pr1704726c.v:559: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:569: error: 'name_gbb' has already been declared in this scope. +./ivltests/pr1704726c.v:565: : It was declared here as a named block. +./ivltests/pr1704726c.v:569: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:577: error: 'name_gbe' has already been declared in this scope. +./ivltests/pr1704726c.v:575: : It was declared here as an event. +./ivltests/pr1704726c.v:577: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:584: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726c.v:589: error: 'name_gbgb' has already been declared in this scope. +./ivltests/pr1704726c.v:584: : It was declared here as a generate block. +./ivltests/pr1704726c.v:589: warning: Anachronistic use of named begin/end to surround generate schemes. diff --git a/ivtest/gold/pr1704726d-v10.gold b/ivtest/gold/pr1704726d-v10.gold new file mode 100644 index 000000000..36ab5999e --- /dev/null +++ b/ivtest/gold/pr1704726d-v10.gold @@ -0,0 +1,13 @@ +./ivltests/pr1704726d.v:82: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726d.v:12: error: signal and parameter in 'top' have the same name 'name0_s'. +./ivltests/pr1704726d.v:21: error: signal and genvar in 'top' have the same name 'name0_v'. +./ivltests/pr1704726d.v:27: error: signal and task in 'top' have the same name 'name1_st'. +./ivltests/pr1704726d.v:34: error: signal and function in 'top' have the same name 'name2_sf'. +./ivltests/pr1704726d.v:38: error: signal and module instance in 'top' have the same name 'name3_si'. +./ivltests/pr1704726d.v:44: error: signal and sequential block in 'top' have the same name 'name4_sb'. +./ivltests/pr1704726d.v:48: error: signal and named event in 'top' have the same name 'name5_se'. +./ivltests/pr1704726d.v:57: error: signal and generate block in 'top' have the same name 'name6_sgl'. +./ivltests/pr1704726d.v:65: error: signal and generate block in 'top' have the same name 'name7_sgi'. +./ivltests/pr1704726d.v:78: error: signal and generate block in 'top' have the same name 'name8_sgc'. +./ivltests/pr1704726d.v:86: error: signal and generate block in 'top' have the same name 'name9_sgb'. +11 error(s) during elaboration. diff --git a/ivtest/gold/pr1704726d.gold b/ivtest/gold/pr1704726d.gold new file mode 100644 index 000000000..9fd4e258f --- /dev/null +++ b/ivtest/gold/pr1704726d.gold @@ -0,0 +1,23 @@ +./ivltests/pr1704726d.v:12: error: 'name0_s' has already been declared in this scope. +./ivltests/pr1704726d.v:4: : It was declared here as a parameter. +./ivltests/pr1704726d.v:21: error: 'name0_v' has already been declared in this scope. +./ivltests/pr1704726d.v:15: : It was declared here as a genvar. +./ivltests/pr1704726d.v:27: error: 'name1_st' has already been declared in this scope. +./ivltests/pr1704726d.v:24: : It was declared here as a task. +./ivltests/pr1704726d.v:34: error: 'name2_sf' has already been declared in this scope. +./ivltests/pr1704726d.v:30: : It was declared here as a function. +./ivltests/pr1704726d.v:38: error: 'name3_si' has already been declared in this scope. +./ivltests/pr1704726d.v:37: : It was declared here as an instance name. +./ivltests/pr1704726d.v:44: error: 'name4_sb' has already been declared in this scope. +./ivltests/pr1704726d.v:41: : It was declared here as a named block. +./ivltests/pr1704726d.v:48: error: 'name5_se' has already been declared in this scope. +./ivltests/pr1704726d.v:47: : It was declared here as an event. +./ivltests/pr1704726d.v:57: error: 'name6_sgl' has already been declared in this scope. +./ivltests/pr1704726d.v:53: : It was declared here as a generate block. +./ivltests/pr1704726d.v:65: error: 'name7_sgi' has already been declared in this scope. +./ivltests/pr1704726d.v:61: : It was declared here as a generate block. +./ivltests/pr1704726d.v:78: error: 'name8_sgc' has already been declared in this scope. +./ivltests/pr1704726d.v:70: : It was declared here as a generate block. +./ivltests/pr1704726d.v:82: warning: Anachronistic use of named begin/end to surround generate schemes. +./ivltests/pr1704726d.v:86: error: 'name9_sgb' has already been declared in this scope. +./ivltests/pr1704726d.v:82: : It was declared here as a generate block. diff --git a/ivtest/gold/pr1719055.gold b/ivtest/gold/pr1719055.gold new file mode 100644 index 000000000..0a84ed104 --- /dev/null +++ b/ivtest/gold/pr1719055.gold @@ -0,0 +1,17 @@ + +*** module array_assign ************************************** + 10 ar_reg=1 w_assign=1 + 10 ar_reg[0]=3'b001 ar_reg[1]=3'b001 + 10 as_wr=5'b00001 + 10 ar_reg=1 w_assign=1 + 10 ar_reg[0]=3'b001 ar_reg[1]=3'b001 + 10 as_wr=5'b00001 + + + + 20 ar_reg=0 w_assign=0 + 20 ar_reg[0]=3'b000 ar_reg[1]=3'b000 + 20 as_wr=5'b00000 + 20 ar_reg=0 w_assign=0 + 20 ar_reg[0]=3'b000 ar_reg[1]=3'b000 + 20 as_wr=5'b00000 diff --git a/ivtest/gold/pr1723367.gold b/ivtest/gold/pr1723367.gold new file mode 100644 index 000000000..4b17f0295 --- /dev/null +++ b/ivtest/gold/pr1723367.gold @@ -0,0 +1,43 @@ +./ivltests/pr1723367.v:131: warning: Scalar port ``a'' has a vectored net declaration [7:0]. +./ivltests/pr1723367.v:138: warning: Scalar port ``a'' has a vectored net declaration [7:0]. +./ivltests/pr1723367.v:141: warning: Scalar port ``b'' has a vectored net declaration [15:0]. +./ivltests/pr1723367.v:148: warning: Scalar port ``a'' has a vectored net declaration [7:0]. +./ivltests/pr1723367.v:156: warning: Scalar port ``a'' has a vectored net declaration [7:0]. +./ivltests/pr1723367.v:167: warning: Scalar port ``a'' has a vectored net declaration [7:0]. +./ivltests/pr1723367.v:174: warning: Scalar port ``a'' has a vectored net declaration [7:0]. +./ivltests/pr1723367.v:177: warning: Scalar port ``b'' has a vectored net declaration [15:0]. +./ivltests/pr1723367.v:184: warning: Scalar port ``a'' has a vectored net declaration [7:0]. +./ivltests/pr1723367.v:192: warning: Scalar port ``a'' has a vectored net declaration [7:0]. +./ivltests/pr1723367.v:203: warning: Scalar port ``a'' has a vectored net declaration [7:0]. +./ivltests/pr1723367.v:212: warning: Scalar port ``a'' has a vectored net declaration [7:0]. +./ivltests/pr1723367.v:215: warning: Scalar port ``b'' has a vectored net declaration [31:0]. +./ivltests/pr1723367.v:246: warning: Scalar port ``a'' has a vectored net declaration [15:0]. +./ivltests/pr1723367.v:253: warning: Scalar port ``a'' has a vectored net declaration [7:0]. +./ivltests/pr1723367.v:256: warning: Scalar port ``b'' has a vectored net declaration [31:0]. +./ivltests/pr1723367.v:282: warning: Scalar port ``a'' has a vectored net declaration [15:0]. +./ivltests/pr1723367.v:289: warning: Scalar port ``a'' has a vectored net declaration [7:0]. +./ivltests/pr1723367.v:292: warning: Scalar port ``b'' has a vectored net declaration [15:0]. +./ivltests/pr1723367.v:307: warning: Scalar port ``a'' has a vectored net declaration [15:0]. +sum[ 1] = 0101010101100000 +sum[ 2] = 0101010101100000 +sum[ 3] = 0101010101100000 +sum[ 4] = 0101010101100000 +sum[ 5] = 0101010101100000 +sum[ 6] = 0101010101100000 +sum[ 7] = 0101010101100000 +sum[ 8] = 0101010101100000 +sum[ 9] = 0101010101100000 +sum[ 10] = 0101010101100000 +sum[ 11] = 0101010101100000 +sum[ 12] = 0101010101100000 +sum[ 13] = 0101010101100000 +sum[ 14] = 0101010101100000 +sum[ 15] = 0101010101100000 +sum[ 16] = 0101010101100000 +sum[ 17] = 0101010101100000 +sum[ 18] = 0101010101100000 +sum[ 19] = 0101010101100000 +sum[ 20] = 0101010101100000 +sum[ 21] = 0101010101100000 +sum[ 22] = 0101010101100000 +sum[ 23] = 0101010101100000 diff --git a/ivtest/gold/pr1735836.gold b/ivtest/gold/pr1735836.gold new file mode 100644 index 000000000..a3c9ca559 --- /dev/null +++ b/ivtest/gold/pr1735836.gold @@ -0,0 +1,4 @@ + 0 out=z + 1 out=1 + 2 out=2 + 3 out=z diff --git a/ivtest/gold/pr1741212.gold b/ivtest/gold/pr1741212.gold new file mode 100644 index 000000000..e64ce54ee --- /dev/null +++ b/ivtest/gold/pr1741212.gold @@ -0,0 +1,36 @@ +cos(MATH_PI_OVER_3): 0.500000 +sin(MATH_PI_OVER_3): 0.866025 +sign(-10): 1.000000 +realmax(MATH_PI,MATH_E): 3.141593 +realmin(MATH_PI,MATH_E): 2.718282 +mod(MATH_PI,MATH_E): 0.423311 +ceil(-MATH_PI): -3.000000 +ceil(4.0): 4.000000 +ceil(3.99999999999999): 4.000000 +pow(MATH_PI,2): 9.869604 +gaussian(1.0,1.0): 0.694156 +round(MATH_PI): 3.000000 +trunc(-MATH_PI): -3.000000 +ceil(-MATH_PI): -3.000000 +floor(MATH_PI): 3.000000 +round(e): 3.000000 +ceil(-e): -2.000000 +exp(MATH_PI): 23.140693 +log2(MATH_PI): 1.651496 +log_base(pow(2,32),2): 32.000000 +ln(0.1): -2.302585 +cbrt(7): 1.912931 +cos(6.2831853071): -1.000000 +sin(-6.2831853071): 0.000000 +sinh(2.7182818284): 7.544137 +cosh(6.2831853071): 267.746761 +arctan_xy(-4,3): 2.498092 +arctan(MATH_PI): 1.262627 +arctan(-MATH_E/2): -0.936472 +arctan(MATH_PI_OVER_2): 1.003885 +arctan(1/7) = 0.141897 +arctan(3/79) = 0.037956 +pi/4 ?= 0.785398 +arcsin(1.0): 1.570796 +cos(pi/2): 0.000000 +arccos(cos(pi/2)): 1.570796 diff --git a/ivtest/gold/pr1746848.gold b/ivtest/gold/pr1746848.gold new file mode 100644 index 000000000..0fa06c90e --- /dev/null +++ b/ivtest/gold/pr1746848.gold @@ -0,0 +1,10 @@ +i= 4 +i= 3 +i= 2 +i= 1 +i= 0 +j= 4 +j= 3 +j= 2 +j= 1 +j= 0 diff --git a/ivtest/gold/pr1752823a.gold b/ivtest/gold/pr1752823a.gold new file mode 100644 index 000000000..2e6760939 --- /dev/null +++ b/ivtest/gold/pr1752823a.gold @@ -0,0 +1 @@ ++0=0.000000 and -0=-0.000000. diff --git a/ivtest/gold/pr1752823b.gold b/ivtest/gold/pr1752823b.gold new file mode 100644 index 000000000..91874378b --- /dev/null +++ b/ivtest/gold/pr1752823b.gold @@ -0,0 +1 @@ ++0=0.000000, -0=-0.000000, inf=inf and minf=-inf. diff --git a/ivtest/gold/pr1758122.gold b/ivtest/gold/pr1758122.gold new file mode 100644 index 000000000..d35bde99d --- /dev/null +++ b/ivtest/gold/pr1758122.gold @@ -0,0 +1,3 @@ +x + x = x +0 + 2 = 2 +1 + 3 = 4 diff --git a/ivtest/gold/pr1758135.gold b/ivtest/gold/pr1758135.gold new file mode 100644 index 000000000..94ebaf900 --- /dev/null +++ b/ivtest/gold/pr1758135.gold @@ -0,0 +1,4 @@ +1 +2 +3 +4 diff --git a/ivtest/gold/pr1770199.gold b/ivtest/gold/pr1770199.gold new file mode 100644 index 000000000..1cf69eab9 --- /dev/null +++ b/ivtest/gold/pr1770199.gold @@ -0,0 +1 @@ +The strength is: Pu1: diff --git a/ivtest/gold/pr1771903.gold b/ivtest/gold/pr1771903.gold new file mode 100644 index 000000000..711b04762 --- /dev/null +++ b/ivtest/gold/pr1771903.gold @@ -0,0 +1,3 @@ +Real :1.23456: has a width of 1. +Parameter real :1.23456: has a width of 1. +Real constant :1.23456: has a width of 1. diff --git a/ivtest/gold/pr1780480.gold b/ivtest/gold/pr1780480.gold new file mode 100644 index 000000000..f0be6225e --- /dev/null +++ b/ivtest/gold/pr1780480.gold @@ -0,0 +1,4 @@ +0 a(0) +20 a(1) +40 a(0) +60 a(1) diff --git a/ivtest/gold/pr1787394a.gold b/ivtest/gold/pr1787394a.gold new file mode 100644 index 000000000..ee97cb41f --- /dev/null +++ b/ivtest/gold/pr1787394a.gold @@ -0,0 +1,6 @@ +These should all produce: +x StL x StL +----------- +c=x(StL), d=x(StL), b=0, nctl=0, pctl=x +c=x(StL), d=x(StL), b=0, nctl=x, pctl=x +c=x(StH), d=x(StH), b=1, nctl=x, pctl=x diff --git a/ivtest/gold/pr1787423.gold b/ivtest/gold/pr1787423.gold new file mode 100644 index 000000000..a2e87c590 --- /dev/null +++ b/ivtest/gold/pr1787423.gold @@ -0,0 +1,3 @@ +00 11 00 11 0 +11 00 00 11 1 +00 11 00 11 0 diff --git a/ivtest/gold/pr1792108.gold b/ivtest/gold/pr1792108.gold new file mode 100644 index 000000000..5b6fe1012 --- /dev/null +++ b/ivtest/gold/pr1792108.gold @@ -0,0 +1,3 @@ + 0 y1 = x, y2 = x, y3 = x, a = x + 1 y1 = 1, y2 = 1, y3 = 1, a = 1 + 2 y1 = 0, y2 = 0, y3 = 0, a = 0 diff --git a/ivtest/gold/pr1792152.gold b/ivtest/gold/pr1792152.gold new file mode 100644 index 000000000..8d42bfcd6 --- /dev/null +++ b/ivtest/gold/pr1792152.gold @@ -0,0 +1,2 @@ +./ivltests/pr1792152.v:2: warning: choosing typ expression. + 2 diff --git a/ivtest/gold/pr1792734.gold b/ivtest/gold/pr1792734.gold new file mode 100644 index 000000000..e0431c765 --- /dev/null +++ b/ivtest/gold/pr1792734.gold @@ -0,0 +1,7 @@ + 7'dx: xxxxxxx, 7'dz: zzzzzzz, 7'd?: zzzzzzz + 'dx: xxxxxxx, 'dz: zzzzzzz, 'd?: zzzzzzz + 2'dx: 00000xx, 2'dz: 00000zz, 2'd?: 00000zz +7'sdx: xxxxxxx, 7'sdz: zzzzzzz, 7'sd?: zzzzzzz + 'sdx: xxxxxxx, 'sdz: zzzzzzz, 'sd?: zzzzzzz +2'sdx: xxxxxxx, 2'sdz: zzzzzzz, 2'sd?: zzzzzzz +7'dx_: xxxxxxx, 7'dz_: zzzzzzz, 7'd?_: zzzzzzz diff --git a/ivtest/gold/pr1793157.gold b/ivtest/gold/pr1793157.gold new file mode 100644 index 000000000..42bacd95b --- /dev/null +++ b/ivtest/gold/pr1793157.gold @@ -0,0 +1 @@ +x1: abcde; x2: ffffffff diff --git a/ivtest/gold/pr1793749.gold b/ivtest/gold/pr1793749.gold new file mode 100644 index 000000000..7ae47644c --- /dev/null +++ b/ivtest/gold/pr1793749.gold @@ -0,0 +1,4 @@ + 9 + 32 + 9 + 9 diff --git a/ivtest/gold/pr1793749b.gold b/ivtest/gold/pr1793749b.gold new file mode 100644 index 000000000..83fb29ce5 --- /dev/null +++ b/ivtest/gold/pr1793749b.gold @@ -0,0 +1 @@ +i, j, k, l: '10100', '11110100', '11110100', '11110100' diff --git a/ivtest/gold/pr1795005a.gold b/ivtest/gold/pr1795005a.gold new file mode 100644 index 000000000..792e34c0f --- /dev/null +++ b/ivtest/gold/pr1795005a.gold @@ -0,0 +1,4 @@ +< : N +<=: Y +> : N +>=: Y diff --git a/ivtest/gold/pr1795005b.gold b/ivtest/gold/pr1795005b.gold new file mode 100644 index 000000000..51276a26c --- /dev/null +++ b/ivtest/gold/pr1795005b.gold @@ -0,0 +1,4 @@ +< : N +<=: N +> : Y +>=: Y diff --git a/ivtest/gold/pr1799904.gold b/ivtest/gold/pr1799904.gold new file mode 100644 index 000000000..b23d583b6 --- /dev/null +++ b/ivtest/gold/pr1799904.gold @@ -0,0 +1,2 @@ +00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 +00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 diff --git a/ivtest/gold/pr1804877.gold b/ivtest/gold/pr1804877.gold new file mode 100644 index 000000000..034335441 --- /dev/null +++ b/ivtest/gold/pr1804877.gold @@ -0,0 +1,2 @@ +String is test_counter +String is test_counter diff --git a/ivtest/gold/pr1805837.gold b/ivtest/gold/pr1805837.gold new file mode 100644 index 000000000..0d40175b5 --- /dev/null +++ b/ivtest/gold/pr1805837.gold @@ -0,0 +1,3 @@ +Should be: +x01 x10 x0z x1z xz1 xz0 x0z0 xxx +x01 x10 x0z x1z xz1 xz0 x0z0 xxx diff --git a/ivtest/gold/pr1819452-vlog95.gold b/ivtest/gold/pr1819452-vlog95.gold new file mode 100644 index 000000000..2a58a0656 --- /dev/null +++ b/ivtest/gold/pr1819452-vlog95.gold @@ -0,0 +1,21 @@ +Found: in_0 currently at byte 5 +Found: in_1 currently at byte 10 +Found: in_2 currently at byte 15 +Found: in_3 currently at byte 20 +Found: in_4 currently at byte 25 +Found: in_5 currently at byte 30 +Found: in_6 currently at byte 35 +Found: in_7 currently at byte 40 +Found: in_8 currently at byte 45 +Found: in_9 currently at byte 50 +Found: in_10 currently at byte 56 +Found: in_0 currently at byte 5 +Found: in_0 currently at byte 5 +Found: 10 currently at byte 56 +Found: in_10 currently at byte 56 +WARNING: vlog95.v:40: invalid file descriptor (0xffffffff) given to $fseek. +Check fseek EOF = -1 +WARNING: vlog95.v:42: invalid file descriptor (0xffffffff) given to $ftell. +Check ftell EOF = -1 +WARNING: vlog95.v:44: invalid file descriptor (0xffffffff) given to $rewind. +Check rewind EOF = -1 diff --git a/ivtest/gold/pr1819452.gold b/ivtest/gold/pr1819452.gold new file mode 100644 index 000000000..e45a25f24 --- /dev/null +++ b/ivtest/gold/pr1819452.gold @@ -0,0 +1,21 @@ +Found: in_0 currently at byte 5 +Found: in_1 currently at byte 10 +Found: in_2 currently at byte 15 +Found: in_3 currently at byte 20 +Found: in_4 currently at byte 25 +Found: in_5 currently at byte 30 +Found: in_6 currently at byte 35 +Found: in_7 currently at byte 40 +Found: in_8 currently at byte 45 +Found: in_9 currently at byte 50 +Found: in_10 currently at byte 56 +Found: in_0 currently at byte 5 +Found: in_0 currently at byte 5 +Found: 10 currently at byte 56 +Found: in_10 currently at byte 56 +WARNING: ./ivltests/pr1819452.v:34: invalid file descriptor (0xffffffff) given to $fseek. +Check fseek EOF = -1 +WARNING: ./ivltests/pr1819452.v:37: invalid file descriptor (0xffffffff) given to $ftell. +Check ftell EOF = -1 +WARNING: ./ivltests/pr1819452.v:40: invalid file descriptor (0xffffffff) given to $rewind. +Check rewind EOF = -1 diff --git a/ivtest/gold/pr1820472.gold b/ivtest/gold/pr1820472.gold new file mode 100644 index 000000000..cf6303f43 --- /dev/null +++ b/ivtest/gold/pr1820472.gold @@ -0,0 +1,8 @@ +out[0]: zz0110 +out[1]: 000010 +out[2]: xx01xx +out[3]: xx10xx +out[1]-0: xxxxxx +out[1]-1: 000010 +out[1]-2: xx01xx +out[1]-3: xx10xx diff --git a/ivtest/gold/pr1823732.gold b/ivtest/gold/pr1823732.gold new file mode 100644 index 000000000..c7c2718b0 --- /dev/null +++ b/ivtest/gold/pr1823732.gold @@ -0,0 +1,2 @@ +i is '1'; j is '111'; k is '0' +runtime ; j is '111'; k is '0' diff --git a/ivtest/gold/pr1828642.gold b/ivtest/gold/pr1828642.gold new file mode 100644 index 000000000..49688f73d --- /dev/null +++ b/ivtest/gold/pr1828642.gold @@ -0,0 +1,16 @@ +01 +02 +03 +04 +11 +12 +13 +14 +21 +22 +23 +24 +31 +32 +33 +34 diff --git a/ivtest/gold/pr1830834.gold b/ivtest/gold/pr1830834.gold new file mode 100644 index 000000000..10672eb9c --- /dev/null +++ b/ivtest/gold/pr1830834.gold @@ -0,0 +1,4 @@ +SORRY: ./ivltests/pr1830834.v:22: currently only simple signals or constant expressions may be passed to $strobe. +NOTE: You can work around this by assigning the desired expression to an + intermediate net (using a continuous assignment) and passing that net + to $strobe. diff --git a/ivtest/gold/pr1831724.gold b/ivtest/gold/pr1831724.gold new file mode 100644 index 000000000..ac52d1ba4 --- /dev/null +++ b/ivtest/gold/pr1831724.gold @@ -0,0 +1 @@ +tmp1: '0000000xxx000000'; tmp2: '0000000xxx000000' diff --git a/ivtest/gold/pr1833024.gold b/ivtest/gold/pr1833024.gold new file mode 100644 index 000000000..ed0c711cf --- /dev/null +++ b/ivtest/gold/pr1833024.gold @@ -0,0 +1,81 @@ +./ivltests/pr1833024.v:43: error: can not select part of scalar: a +./ivltests/pr1833024.v:44: error: can not select part of scalar: a +./ivltests/pr1833024.v:45: error: can not select part of scalar: a +./ivltests/pr1833024.v:46: error: can not select part of scalar: a +./ivltests/pr1833024.v:10: error: can not select part of scalar: svar +./ivltests/pr1833024.v:10: error: Unable to elaborate r-value: svar['sd0] +./ivltests/pr1833024.v:11: error: can not select part of scalar: svar +./ivltests/pr1833024.v:11: error: Unable to elaborate r-value: svar['sd0:'sd0] +./ivltests/pr1833024.v:12: error: can not select part of scalar: svar +./ivltests/pr1833024.v:12: error: Unable to elaborate r-value: svar['sd0+:'sd1] +./ivltests/pr1833024.v:13: error: can not select part of scalar: svar +./ivltests/pr1833024.v:13: error: Unable to elaborate r-value: svar['sd0-:'sd1] +./ivltests/pr1833024.v:15: error: can not select part of scalar array word: sarr[32'sd0] +./ivltests/pr1833024.v:15: error: Unable to elaborate r-value: sarr['sd0]['sd0] +./ivltests/pr1833024.v:16: error: can not select part of scalar array word: sarr[32'sd0] +./ivltests/pr1833024.v:16: error: Unable to elaborate r-value: sarr['sd0]['sd0:'sd0] +./ivltests/pr1833024.v:17: error: can not select part of scalar array word: sarr[32'sd0] +./ivltests/pr1833024.v:17: error: Unable to elaborate r-value: sarr['sd0]['sd0+:'sd1] +./ivltests/pr1833024.v:18: error: can not select part of scalar array word: sarr[32'sd0] +./ivltests/pr1833024.v:18: error: Unable to elaborate r-value: sarr['sd0]['sd0-:'sd1] +./ivltests/pr1833024.v:20: error: can not select part of scalar: wsbslv +./ivltests/pr1833024.v:21: error: can not select part of scalar: wspslv +./ivltests/pr1833024.v:22: error: can not select part of scalar: wsuplv +./ivltests/pr1833024.v:23: error: can not select part of scalar: wsdolv +./ivltests/pr1833024.v:25: error: can not select part of scalar array word: wsarr[0] +./ivltests/pr1833024.v:26: error: can not select part of scalar array word: wsarr[0] +./ivltests/pr1833024.v:27: error: can not select part of scalar array word: wsarr[0] +./ivltests/pr1833024.v:28: error: can not select part of scalar array word: wsarr[0] +./ivltests/pr1833024.v:30: error: can not select part of scalar: wsbstr +./ivltests/pr1833024.v:31: error: can not select part of scalar: wspstr +./ivltests/pr1833024.v:32: error: can not select part of scalar: wsuptr +./ivltests/pr1833024.v:33: error: can not select part of scalar: wsdotr +./ivltests/pr1833024.v:35: error: can not select part of scalar: wsbstr +./ivltests/pr1833024.v:35: error: Failed to elaborate port expression. +./ivltests/pr1833024.v:35: error: can not select part of scalar: wspstr +./ivltests/pr1833024.v:35: error: Failed to elaborate port expression. +./ivltests/pr1833024.v:35: error: can not select part of scalar: wsuptr +./ivltests/pr1833024.v:35: error: Failed to elaborate port expression. +./ivltests/pr1833024.v:35: error: can not select part of scalar: wsdotr +./ivltests/pr1833024.v:35: error: Failed to elaborate port expression. +./ivltests/pr1833024.v:36: error: can not select part of scalar: wsbstr +./ivltests/pr1833024.v:36: error: Output port expression must support continuous assignment. +./ivltests/pr1833024.v:36: : Port 1 (arg1) of submod2 is connected to wsbstr['sd0] +./ivltests/pr1833024.v:36: error: can not select part of scalar: wspstr +./ivltests/pr1833024.v:36: error: Output port expression must support continuous assignment. +./ivltests/pr1833024.v:36: : Port 2 (arg2) of submod2 is connected to wspstr['sd0:'sd0] +./ivltests/pr1833024.v:36: error: can not select part of scalar: wsuptr +./ivltests/pr1833024.v:36: error: Output port expression must support continuous assignment. +./ivltests/pr1833024.v:36: : Port 3 (arg3) of submod2 is connected to wsuptr['sd0+:'sd1] +./ivltests/pr1833024.v:36: error: can not select part of scalar: wsdotr +./ivltests/pr1833024.v:36: error: Output port expression must support continuous assignment. +./ivltests/pr1833024.v:36: : Port 4 (arg4) of submod2 is connected to wsdotr['sd0-:'sd1] +./ivltests/pr1833024.v:37: error: can not select part of scalar: wsbstr +./ivltests/pr1833024.v:37: error: Inout port expression must support continuous assignment. +./ivltests/pr1833024.v:37: : Port 1 (arg1) of submod3 is connected to wsbstr['sd0] +./ivltests/pr1833024.v:37: error: can not select part of scalar: wspstr +./ivltests/pr1833024.v:37: error: Inout port expression must support continuous assignment. +./ivltests/pr1833024.v:37: : Port 2 (arg2) of submod3 is connected to wspstr['sd0:'sd0] +./ivltests/pr1833024.v:37: error: can not select part of scalar: wsuptr +./ivltests/pr1833024.v:37: error: Inout port expression must support continuous assignment. +./ivltests/pr1833024.v:37: : Port 3 (arg3) of submod3 is connected to wsuptr['sd0+:'sd1] +./ivltests/pr1833024.v:37: error: can not select part of scalar: wsdotr +./ivltests/pr1833024.v:37: error: Inout port expression must support continuous assignment. +./ivltests/pr1833024.v:37: : Port 4 (arg4) of submod3 is connected to wsdotr['sd0-:'sd1] +./ivltests/pr1833024.v:51: error: can not select part of scalar: svar +./ivltests/pr1833024.v:52: error: can not select part of scalar: svar +./ivltests/pr1833024.v:53: error: can not select part of scalar: svar +./ivltests/pr1833024.v:54: error: can not select part of scalar: svar +./ivltests/pr1833024.v:56: error: can not select part of scalar array word: sarr[32'sd0] +./ivltests/pr1833024.v:57: error: can not select part of scalar array word: sarr[32'sd0] +./ivltests/pr1833024.v:58: error: can not select part of scalar array word: sarr[32'sd0] +./ivltests/pr1833024.v:59: error: can not select part of scalar array word: sarr[32'sd0] +./ivltests/pr1833024.v:61: error: can not select part of scalar: sout +./ivltests/pr1833024.v:62: error: can not select part of scalar: sout +./ivltests/pr1833024.v:63: error: can not select part of scalar: sout +./ivltests/pr1833024.v:64: error: can not select part of scalar: sout +./ivltests/pr1833024.v:66: error: can not select part of scalar array word: sarr[32'sd0] +./ivltests/pr1833024.v:67: error: can not select part of scalar array word: sarr[32'sd0] +./ivltests/pr1833024.v:68: error: can not select part of scalar array word: sarr[32'sd0] +./ivltests/pr1833024.v:69: error: can not select part of scalar array word: sarr[32'sd0] +72 error(s) during elaboration. diff --git a/ivtest/gold/pr1841300.gold b/ivtest/gold/pr1841300.gold new file mode 100644 index 000000000..e70fe4209 --- /dev/null +++ b/ivtest/gold/pr1841300.gold @@ -0,0 +1 @@ +a is '14'; b is 'fffffff4'; c is 'fffffff4' diff --git a/ivtest/gold/pr1845683.gold b/ivtest/gold/pr1845683.gold new file mode 100644 index 000000000..e71004984 --- /dev/null +++ b/ivtest/gold/pr1845683.gold @@ -0,0 +1 @@ +res1: '00101010'; res2: '00101010'; res3: '00101010' diff --git a/ivtest/gold/pr1851310.gold b/ivtest/gold/pr1851310.gold new file mode 100644 index 000000000..6ab23b107 --- /dev/null +++ b/ivtest/gold/pr1851310.gold @@ -0,0 +1,2 @@ +Flag1 = 1, FlagI = 1 +Flag1 = 0, FlagI = 0 diff --git a/ivtest/gold/pr1855504.gold b/ivtest/gold/pr1855504.gold new file mode 100644 index 000000000..3856b4b9f --- /dev/null +++ b/ivtest/gold/pr1855504.gold @@ -0,0 +1 @@ +op1 = 0da0, op2 = 0a, prod = 0640 diff --git a/ivtest/gold/pr1861212.gold b/ivtest/gold/pr1861212.gold new file mode 100644 index 000000000..af9764ae4 --- /dev/null +++ b/ivtest/gold/pr1861212.gold @@ -0,0 +1,3 @@ +Real value is 3.300000 at 0 +Real value is 4.577600 at 1000 +Real value is -4.000000 at 2000 diff --git a/ivtest/gold/pr1862744b.gold b/ivtest/gold/pr1862744b.gold new file mode 100644 index 000000000..afc246684 --- /dev/null +++ b/ivtest/gold/pr1862744b.gold @@ -0,0 +1,67 @@ +./ivltests/pr1862744b.v:56: warning: condition expression of for-loop is constant. +./ivltests/pr1862744b.v:59: warning: condition expression of for-loop is constant. +./ivltests/pr1862744b.v:119: error: always process does not have any delay. +./ivltests/pr1862744b.v:119: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:104: warning: always process may not have any delay. +./ivltests/pr1862744b.v:104: : A runtime infinite loop may be possible. +./ivltests/pr1862744b.v:103: error: always process does not have any delay. +./ivltests/pr1862744b.v:103: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:102: error: always process does not have any delay. +./ivltests/pr1862744b.v:102: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:95: warning: always process may not have any delay. +./ivltests/pr1862744b.v:95: : A runtime infinite loop may be possible. +./ivltests/pr1862744b.v:89: warning: always process may not have any delay. +./ivltests/pr1862744b.v:89: : A runtime infinite loop may be possible. +./ivltests/pr1862744b.v:86: warning: always process may not have any delay. +./ivltests/pr1862744b.v:86: : A runtime infinite loop may be possible. +./ivltests/pr1862744b.v:83: error: always process does not have any delay. +./ivltests/pr1862744b.v:83: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:80: warning: always process may not have any delay. +./ivltests/pr1862744b.v:80: : A runtime infinite loop may be possible. +./ivltests/pr1862744b.v:77: error: always process does not have any delay. +./ivltests/pr1862744b.v:77: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:74: error: always process does not have any delay. +./ivltests/pr1862744b.v:74: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:71: warning: always process may not have any delay. +./ivltests/pr1862744b.v:71: : A runtime infinite loop may be possible. +./ivltests/pr1862744b.v:68: error: always process does not have any delay. +./ivltests/pr1862744b.v:68: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:65: error: always process does not have any delay. +./ivltests/pr1862744b.v:65: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:62: error: always process does not have any delay. +./ivltests/pr1862744b.v:62: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:59: error: always process does not have any delay. +./ivltests/pr1862744b.v:59: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:56: error: always process does not have any delay. +./ivltests/pr1862744b.v:56: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:53: warning: always process may not have any delay. +./ivltests/pr1862744b.v:53: : A runtime infinite loop may be possible. +./ivltests/pr1862744b.v:50: error: always process does not have any delay. +./ivltests/pr1862744b.v:50: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:47: error: always process does not have any delay. +./ivltests/pr1862744b.v:47: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:44: warning: always process may not have any delay. +./ivltests/pr1862744b.v:44: : A runtime infinite loop may be possible. +./ivltests/pr1862744b.v:41: error: always process does not have any delay. +./ivltests/pr1862744b.v:41: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:38: error: always process does not have any delay. +./ivltests/pr1862744b.v:38: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:35: warning: always process may not have any delay. +./ivltests/pr1862744b.v:35: : A runtime infinite loop may be possible. +./ivltests/pr1862744b.v:32: warning: always process may not have any delay. +./ivltests/pr1862744b.v:32: : A runtime infinite loop may be possible. +./ivltests/pr1862744b.v:29: warning: always process may not have any delay. +./ivltests/pr1862744b.v:29: : A runtime infinite loop may be possible. +./ivltests/pr1862744b.v:26: error: always process does not have any delay. +./ivltests/pr1862744b.v:26: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:23: error: always process does not have any delay. +./ivltests/pr1862744b.v:23: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:20: error: always process does not have any delay. +./ivltests/pr1862744b.v:20: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:17: warning: always process may not have any delay. +./ivltests/pr1862744b.v:17: : A runtime infinite loop may be possible. +./ivltests/pr1862744b.v:14: error: always process does not have any delay. +./ivltests/pr1862744b.v:14: : A runtime infinite loop will occur. +./ivltests/pr1862744b.v:11: error: always process does not have any delay. +./ivltests/pr1862744b.v:11: : A runtime infinite loop will occur. +Elaboration failed diff --git a/ivtest/gold/pr1864110a-ivl.gold b/ivtest/gold/pr1864110a-ivl.gold new file mode 100644 index 000000000..8228a1d36 --- /dev/null +++ b/ivtest/gold/pr1864110a-ivl.gold @@ -0,0 +1 @@ +3.00000 -3.00000 diff --git a/ivtest/gold/pr1864110a.gold b/ivtest/gold/pr1864110a.gold new file mode 100644 index 000000000..9e74b2216 --- /dev/null +++ b/ivtest/gold/pr1864110a.gold @@ -0,0 +1 @@ +3 -3 diff --git a/ivtest/gold/pr1864110b-ivl.gold b/ivtest/gold/pr1864110b-ivl.gold new file mode 100644 index 000000000..c353e2156 --- /dev/null +++ b/ivtest/gold/pr1864110b-ivl.gold @@ -0,0 +1,3 @@ +-3.00000 3.00000 +-4.00000 4.00000 +-6.00000 6.00000 diff --git a/ivtest/gold/pr1864110b.gold b/ivtest/gold/pr1864110b.gold new file mode 100644 index 000000000..ae46f1fe3 --- /dev/null +++ b/ivtest/gold/pr1864110b.gold @@ -0,0 +1,3 @@ +-3 3 +-4 4 +-6 6 diff --git a/ivtest/gold/pr1864110c.gold b/ivtest/gold/pr1864110c.gold new file mode 100644 index 000000000..e555b09de --- /dev/null +++ b/ivtest/gold/pr1864110c.gold @@ -0,0 +1,2 @@ +0 0000000000000000 +2 3fffffffffffffff diff --git a/ivtest/gold/pr1864115-ivl.gold b/ivtest/gold/pr1864115-ivl.gold new file mode 100644 index 000000000..cedfe0c3a --- /dev/null +++ b/ivtest/gold/pr1864115-ivl.gold @@ -0,0 +1,2 @@ +0.00000 0 0.00000 +2.00000 4611686018427387904 2.00000 diff --git a/ivtest/gold/pr1864115.gold b/ivtest/gold/pr1864115.gold new file mode 100644 index 000000000..1b917e756 --- /dev/null +++ b/ivtest/gold/pr1864115.gold @@ -0,0 +1,2 @@ +0 0 0 +2 4611686018427387904 2 diff --git a/ivtest/gold/pr1866215.gold b/ivtest/gold/pr1866215.gold new file mode 100644 index 000000000..b4a9b1399 --- /dev/null +++ b/ivtest/gold/pr1866215.gold @@ -0,0 +1,9 @@ +./ivltests/pr1866215.v:31: warning: Port 1 (CH) of C expects 7 bits, got 6. +./ivltests/pr1866215.v:31: : Padding 1 high bits of the port. +./ivltests/pr1866215.v:31: warning: Port 3 (SH) of C expects 8 bits, got 7. +./ivltests/pr1866215.v:31: : Padding 1 high bits of the port. +./ivltests/pr1866215.v:15: warning: Port 1 (CH) of B expects 6 bits, got 7. +./ivltests/pr1866215.v:15: : Padding 1 high bits of the expression. +./ivltests/pr1866215.v:15: warning: Port 3 (SH) of B expects 7 bits, got 8. +./ivltests/pr1866215.v:15: : Padding 1 high bits of the expression. +C1H=33, {C1L, CL}={1555555, zzzzzzZ5}, S1H=66, {S1L, SL}={2aaaaaa, zzzzzzZa} diff --git a/ivtest/gold/pr1866215b.gold b/ivtest/gold/pr1866215b.gold new file mode 100644 index 000000000..886d18b4e --- /dev/null +++ b/ivtest/gold/pr1866215b.gold @@ -0,0 +1,9 @@ +./ivltests/pr1866215b.v:26: warning: Port 1 (CH) of C expects 7 bits, got 6. +./ivltests/pr1866215b.v:26: : Padding 1 high bits of the port. +./ivltests/pr1866215b.v:26: warning: Port 3 (SH) of C expects 8 bits, got 7. +./ivltests/pr1866215b.v:26: : Padding 1 high bits of the port. +./ivltests/pr1866215b.v:10: warning: Port 1 (CH) of B expects 6 bits, got 16. +./ivltests/pr1866215b.v:10: : Pruning 10 high bits of the expression. +./ivltests/pr1866215b.v:10: warning: Port 3 (SH) of B expects 7 bits, got 16. +./ivltests/pr1866215b.v:10: : Pruning 9 high bits of the expression. +CH=3f, CL=55555555, SH=7f, SL=aaaaaaaa diff --git a/ivtest/gold/pr1867161a.gold b/ivtest/gold/pr1867161a.gold new file mode 100644 index 000000000..439361705 --- /dev/null +++ b/ivtest/gold/pr1867161a.gold @@ -0,0 +1,7 @@ +Value[0]: 2 +Value[1]: 3 +Value[2]: 4 +Value[3]: 5 +Value[4]: 6 +Value[5]: 7 +Value[6]: 8 diff --git a/ivtest/gold/pr1867161b.gold b/ivtest/gold/pr1867161b.gold new file mode 100644 index 000000000..ec3d86f01 --- /dev/null +++ b/ivtest/gold/pr1867161b.gold @@ -0,0 +1,6 @@ + 0 8 + 1 8 + 1 9 + 2 9 + 2 10 + 3 10 diff --git a/ivtest/gold/pr1873372.gold b/ivtest/gold/pr1873372.gold new file mode 100644 index 000000000..c7efeeb69 --- /dev/null +++ b/ivtest/gold/pr1873372.gold @@ -0,0 +1 @@ +big: 1e+20, small: 1e-20, precision: 0.12345678900 diff --git a/ivtest/gold/pr1876798.gold b/ivtest/gold/pr1876798.gold new file mode 100644 index 000000000..bc856dafa --- /dev/null +++ b/ivtest/gold/pr1876798.gold @@ -0,0 +1,4 @@ +0 +1 +2 +3 diff --git a/ivtest/gold/pr1885847.gold b/ivtest/gold/pr1885847.gold new file mode 100644 index 000000000..1ad8ca951 --- /dev/null +++ b/ivtest/gold/pr1885847.gold @@ -0,0 +1 @@ +P3 = 32 diff --git a/ivtest/gold/pr1887168.gold b/ivtest/gold/pr1887168.gold new file mode 100644 index 000000000..d1eea064e --- /dev/null +++ b/ivtest/gold/pr1887168.gold @@ -0,0 +1,4 @@ + 3 3 4 3 3 4 -3 -3 -4 -3 -3 -4 3 3 4 + 3 3 4 3 3 4 -3 -3 -4 -3 -3 -4 3 3 4 + 1 2 0 1 2 0 -1 -2 0 1 2 0 -1 -2 0 + 1 2 0 1 2 0 -1 -2 0 1 2 0 -1 -2 0 diff --git a/ivtest/gold/pr1898983.gold b/ivtest/gold/pr1898983.gold new file mode 100644 index 000000000..3263a84fa --- /dev/null +++ b/ivtest/gold/pr1898983.gold @@ -0,0 +1,2 @@ +In top.sm[0] at 1 +In top.sm[1] at 2 diff --git a/ivtest/gold/pr1903343.gold b/ivtest/gold/pr1903343.gold new file mode 100644 index 000000000..9a732ed0d --- /dev/null +++ b/ivtest/gold/pr1903343.gold @@ -0,0 +1,2 @@ +OK: 256 +Main: 4 diff --git a/ivtest/gold/pr1912112.gold b/ivtest/gold/pr1912112.gold new file mode 100644 index 000000000..b4252126a --- /dev/null +++ b/ivtest/gold/pr1912112.gold @@ -0,0 +1 @@ +The `test definition is: `define Hello World diff --git a/ivtest/gold/pr1936363.gold b/ivtest/gold/pr1936363.gold new file mode 100644 index 000000000..1397b7bfe --- /dev/null +++ b/ivtest/gold/pr1936363.gold @@ -0,0 +1,3 @@ + x x + 42 21 + x x diff --git a/ivtest/gold/pr1949025.gold b/ivtest/gold/pr1949025.gold new file mode 100644 index 000000000..962464321 --- /dev/null +++ b/ivtest/gold/pr1949025.gold @@ -0,0 +1,7 @@ +0 00000040 +1 00000020 +2 00000010 +3 00000008 +4 00000004 +5 00000002 +6 00000001 diff --git a/ivtest/gold/pr1960545.gold b/ivtest/gold/pr1960545.gold new file mode 100644 index 000000000..1f04036de --- /dev/null +++ b/ivtest/gold/pr1960545.gold @@ -0,0 +1 @@ +B is 1 diff --git a/ivtest/gold/pr1960548.gold b/ivtest/gold/pr1960548.gold new file mode 100644 index 000000000..3bc7902df --- /dev/null +++ b/ivtest/gold/pr1960548.gold @@ -0,0 +1 @@ +B`x diff --git a/ivtest/gold/pr1960558.gold b/ivtest/gold/pr1960558.gold new file mode 100644 index 000000000..6df7511c9 --- /dev/null +++ b/ivtest/gold/pr1960558.gold @@ -0,0 +1 @@ +expected 1; got 1 diff --git a/ivtest/gold/pr1960575.gold b/ivtest/gold/pr1960575.gold new file mode 100644 index 000000000..b3fa4188f --- /dev/null +++ b/ivtest/gold/pr1960575.gold @@ -0,0 +1 @@ +expected x; got x diff --git a/ivtest/gold/pr1960596.gold b/ivtest/gold/pr1960596.gold new file mode 100644 index 000000000..35f889bc1 --- /dev/null +++ b/ivtest/gold/pr1960596.gold @@ -0,0 +1,2 @@ +expected 32'h55555552; got 32'h55555552 +expected 1; got 1 diff --git a/ivtest/gold/pr1960619.gold b/ivtest/gold/pr1960619.gold new file mode 100644 index 000000000..904cd9621 --- /dev/null +++ b/ivtest/gold/pr1960619.gold @@ -0,0 +1 @@ +a is 14; b is fffffff4; c is 14; d is fffffff4 diff --git a/ivtest/gold/pr1963240.gold b/ivtest/gold/pr1963240.gold new file mode 100644 index 000000000..e338e3641 --- /dev/null +++ b/ivtest/gold/pr1963240.gold @@ -0,0 +1,2 @@ +expected 52; got 52 +expected fffffff7; got fffffff7 diff --git a/ivtest/gold/pr1963962-fsv.gold b/ivtest/gold/pr1963962-fsv.gold new file mode 100644 index 000000000..47d9fb2e2 --- /dev/null +++ b/ivtest/gold/pr1963962-fsv.gold @@ -0,0 +1,2 @@ +VCD info: dumpfile work/dumptest.vcd opened for output. +VCD warning: $dumpvars: Package ($unit) is not dumpable with VCD. diff --git a/ivtest/gold/pr1963962.gold b/ivtest/gold/pr1963962.gold new file mode 100644 index 000000000..66c526021 --- /dev/null +++ b/ivtest/gold/pr1963962.gold @@ -0,0 +1 @@ +VCD info: dumpfile work/dumptest.vcd opened for output. diff --git a/ivtest/gold/pr1985582.gold b/ivtest/gold/pr1985582.gold new file mode 100644 index 000000000..5c2c0148f --- /dev/null +++ b/ivtest/gold/pr1985582.gold @@ -0,0 +1,5 @@ + 0 0.00 0, 0 0.00 0, 0 0.00, 0 0.00, 0 0.00, 0 0.000 +1000 1.00 1, 1000 1.00 1, 600 0.60, 600 0.60, 600 0.60, 1 0.600 +1000 1.00 1, 1000 1.00 1, 1200 1.20, 1200 1.20, 1200 1.20, 1 1.200 +2000 2.00 2, 2000 2.00 2, 1800 1.80, 1800 1.80, 1800 1.80, 2 1.800 +2000 2.00 2, 2000 2.00 2, 2400 2.40, 2400 2.40, 2400 2.40, 2 2.400 diff --git a/ivtest/gold/pr1985582_std.gold b/ivtest/gold/pr1985582_std.gold new file mode 100644 index 000000000..2633689f0 --- /dev/null +++ b/ivtest/gold/pr1985582_std.gold @@ -0,0 +1,5 @@ + 0 0.00 0, 0 0.00 0, 0 0.00, 0 0.00, 0 0.00, 0 0 + 1000 1.00 1, 1000 1.00 1, 600 0.60, 600 0.60, 600 0.60, 1 0.6 + 1000 1.00 1, 1000 1.00 1, 1200 1.20, 1200 1.20, 1200 1.20, 1 1.2 + 2000 2.00 2, 2000 2.00 2, 1800 1.80, 1800 1.80, 1800 1.80, 2 1.8 + 2000 2.00 2, 2000 2.00 2, 2400 2.40, 2400 2.40, 2400 2.40, 2 2.4 diff --git a/ivtest/gold/pr1993479.gold b/ivtest/gold/pr1993479.gold new file mode 100644 index 000000000..a5ca7a1ed --- /dev/null +++ b/ivtest/gold/pr1993479.gold @@ -0,0 +1,17 @@ + 0 10100101 10100101 + -1 0100101x 0100101x + -2 100101xx 100101xx + -3 00101xxx 00101xxx + -4 0101xxxx 0101xxxx + -5 101xxxxx 101xxxxx + -6 01xxxxxx 01xxxxxx + -7 1xxxxxxx 1xxxxxxx + + 1 x1010010 x1010010 + 0 10100101 10100101 + -1 0100101x 0100101x + -2 100101xx 100101xx + -3 00101xxx 00101xxx + -4 0101xxxx 0101xxxx + -5 101xxxxx 101xxxxx + -6 01xxxxxx 01xxxxxx diff --git a/ivtest/gold/pr2001162.gold b/ivtest/gold/pr2001162.gold new file mode 100644 index 000000000..cc6c4a0e3 --- /dev/null +++ b/ivtest/gold/pr2001162.gold @@ -0,0 +1,9 @@ +test2 increment; reading counter as 0 +test1 increment; reading counter as 1 +test2 increment; reading counter as 2 +test1 increment; reading counter as 3 +test2 increment; reading counter as 4 +test1 increment; reading counter as 5 +test2 increment; reading counter as 6 +test1 increment; reading counter as 7 +time 52; the counter is 8 diff --git a/ivtest/gold/pr2001162_std.gold b/ivtest/gold/pr2001162_std.gold new file mode 100644 index 000000000..fb2bd1ed8 --- /dev/null +++ b/ivtest/gold/pr2001162_std.gold @@ -0,0 +1,9 @@ +test1 increment; reading counter as 0 +test2 increment; reading counter as 1 +test1 increment; reading counter as 2 +test2 increment; reading counter as 3 +test1 increment; reading counter as 4 +test2 increment; reading counter as 5 +test1 increment; reading counter as 6 +test2 increment; reading counter as 7 +time 52; the counter is 8 diff --git a/ivtest/gold/pr2029336.gold b/ivtest/gold/pr2029336.gold new file mode 100644 index 000000000..a92619fd9 --- /dev/null +++ b/ivtest/gold/pr2029336.gold @@ -0,0 +1,7 @@ +# x = 1073741824 +# x = 2147483648 +# x = 4294967296 + 0 +1073741824 +2147483648 +4294967296 diff --git a/ivtest/gold/pr2039694.gold b/ivtest/gold/pr2039694.gold new file mode 100644 index 000000000..8d2b7f231 --- /dev/null +++ b/ivtest/gold/pr2039694.gold @@ -0,0 +1,6 @@ +testcase_defparam.test_defparam_a.U_test foo = 2 +testcase_defparam.test_defparam_b.U_test foo = 2 +testcase_defparam.test_defparam_c.U_test foo = 2 +testcase_inline.test_inline_a.U_test foo = 2 +testcase_inline.test_inline_b.U_test foo = 2 +testcase_inline.test_inline_c.U_test foo = 2 diff --git a/ivtest/gold/pr2043585.gold b/ivtest/gold/pr2043585.gold new file mode 100644 index 000000000..770a81d18 --- /dev/null +++ b/ivtest/gold/pr2043585.gold @@ -0,0 +1,20 @@ +./ivltests/pr2043585.v:27: warning: @* is sensitive to all 4 words in array 'Data'. +./ivltests/pr2043585.v:28: warning: @* is sensitive to all 4 words in array 'Data'. +./ivltests/pr2043585.v:29: warning: @* is sensitive to all 4 words in array 'Data'. +./ivltests/pr2043585.v:30: warning: @* is sensitive to all 4 words in array 'Data'. +0 +1 +2 +3 +1 +2 +3 +0 +2 +3 +0 +1 +3 +0 +1 +2 diff --git a/ivtest/gold/pr2043585_std.gold b/ivtest/gold/pr2043585_std.gold new file mode 100644 index 000000000..5afd27d55 --- /dev/null +++ b/ivtest/gold/pr2043585_std.gold @@ -0,0 +1,15 @@ +1 +2 +3 +1 +2 +3 +0 +2 +3 +0 +1 +3 +0 +1 +2 diff --git a/ivtest/gold/pr2053944.gold b/ivtest/gold/pr2053944.gold new file mode 100644 index 000000000..467255932 --- /dev/null +++ b/ivtest/gold/pr2053944.gold @@ -0,0 +1 @@ + 1 2 diff --git a/ivtest/gold/pr2076391.gold b/ivtest/gold/pr2076391.gold new file mode 100644 index 000000000..299987092 --- /dev/null +++ b/ivtest/gold/pr2076391.gold @@ -0,0 +1,3 @@ +iindex[0] = -1 +rindex[0] = -1 +windex[0] = -1 diff --git a/ivtest/gold/pr2091455.gold b/ivtest/gold/pr2091455.gold new file mode 100644 index 000000000..41238e6a7 --- /dev/null +++ b/ivtest/gold/pr2091455.gold @@ -0,0 +1,2 @@ +I am in main.X, case foo=2 +I am in main.genblk1, case foo=2 diff --git a/ivtest/gold/pr2119622.gold b/ivtest/gold/pr2119622.gold new file mode 100644 index 000000000..6770f6fbf --- /dev/null +++ b/ivtest/gold/pr2119622.gold @@ -0,0 +1 @@ +1 << 32 = 0000000000000000000000000000000100000000000000000000000000000000 diff --git a/ivtest/gold/pr2132552.gold b/ivtest/gold/pr2132552.gold new file mode 100644 index 000000000..55bf894a0 --- /dev/null +++ b/ivtest/gold/pr2132552.gold @@ -0,0 +1,16 @@ +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 diff --git a/ivtest/gold/pr2136787.gold b/ivtest/gold/pr2136787.gold new file mode 100644 index 000000000..16a14c804 --- /dev/null +++ b/ivtest/gold/pr2136787.gold @@ -0,0 +1,4 @@ +a = 1010 +b = 0000 +y = 11111010 +z = 11111010 diff --git a/ivtest/gold/pr2138682.gold b/ivtest/gold/pr2138682.gold new file mode 100644 index 000000000..e44da9aff --- /dev/null +++ b/ivtest/gold/pr2138682.gold @@ -0,0 +1,8 @@ +Block 0 value = 7 +Block 1 value = 6 +Block 2 value = 5 +Block 3 value = 4 +Block 4 value = 3 +Block 5 value = 2 +Block 6 value = 1 +Block 7 value = 0 diff --git a/ivtest/gold/pr2138979b.gold b/ivtest/gold/pr2138979b.gold new file mode 100644 index 000000000..197449b05 --- /dev/null +++ b/ivtest/gold/pr2138979b.gold @@ -0,0 +1,10 @@ +a = 10110110 +b = 10010010 +yuu = 0000000010110110 +zuu = 0000000010110110 +yus = 0000000010110110 +zus = 0000000010110110 +ysu = 0000000010110110 +zsu = 0000000010110110 +yss = 1111111110110110 +zss = 1111111110110110 diff --git a/ivtest/gold/pr2138979c.gold b/ivtest/gold/pr2138979c.gold new file mode 100644 index 000000000..b3cd990ef --- /dev/null +++ b/ivtest/gold/pr2138979c.gold @@ -0,0 +1,3 @@ +a = 10110110 +y = 1111111110110110 +z = 1111111110110110 diff --git a/ivtest/gold/pr2138979d.gold b/ivtest/gold/pr2138979d.gold new file mode 100644 index 000000000..4f5635bee --- /dev/null +++ b/ivtest/gold/pr2138979d.gold @@ -0,0 +1,2200 @@ +sel = 0 +a = 10000001 +b = 00001001 +c = 100011 +y_mux_uu = 0000000000001001 y_mux_us = 0000000000001001 y_mux_su = 0000000000001001 y_mux_ss = 0000000000001001 +z_mux_uu = 0000000000001001 z_mux_us = 0000000000001001 z_mux_su = 0000000000001001 z_mux_ss = 0000000000001001 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111011100 y_sgn_s = 0000000000011100 +z_sgn_u = 1111111111011100 z_sgn_s = 0000000000011100 +y_add_uu = 0000000010100100 y_add_us = 0000000010100100 y_add_su = 0000000010100100 y_add_ss = 1111111101100100 +z_add_uu = 0000000010100100 z_add_us = 0000000010100100 z_add_su = 0000000010100100 z_add_ss = 1111111101100100 +y_sub_uu = 0000000001011110 y_sub_us = 0000000001011110 y_sub_su = 0000000001011110 y_sub_ss = 1111111110011110 +z_sub_uu = 0000000001011110 z_sub_us = 0000000001011110 z_sub_su = 0000000001011110 z_sub_ss = 1111111110011110 +y_mul_uu = 0001000110100011 y_mul_us = 0001000110100011 y_mul_su = 0001000110100011 y_mul_ss = 0000111001100011 +z_mul_uu = 0001000110100011 z_mul_us = 0001000110100011 z_mul_su = 0001000110100011 z_mul_ss = 0000111001100011 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 10001101 +b = 01100101 +c = 010010 +y_mux_uu = 0000000010001101 y_mux_us = 0000000010001101 y_mux_su = 0000000010001101 y_mux_ss = 1111111110001101 +z_mux_uu = 0000000010001101 z_mux_us = 0000000010001101 z_mux_su = 0000000010001101 z_mux_ss = 1111111110001101 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111101101 y_sgn_s = 1111111111101101 +z_sgn_u = 1111111111101101 z_sgn_s = 1111111111101101 +y_add_uu = 0000000010011111 y_add_us = 0000000010011111 y_add_su = 0000000010011111 y_add_ss = 1111111110011111 +z_add_uu = 0000000010011111 z_add_us = 0000000010011111 z_add_su = 0000000010011111 z_add_ss = 1111111110011111 +y_sub_uu = 0000000001111011 y_sub_us = 0000000001111011 y_sub_su = 0000000001111011 y_sub_ss = 1111111101111011 +z_sub_uu = 0000000001111011 z_sub_us = 0000000001111011 z_sub_su = 0000000001111011 z_sub_ss = 1111111101111011 +y_mul_uu = 0000100111101010 y_mul_us = 0000100111101010 y_mul_su = 0000100111101010 y_mul_ss = 1111011111101010 +z_mul_uu = 0000100111101010 z_mul_us = 0000100111101010 z_mul_su = 0000100111101010 z_mul_ss = 1111011111101010 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 00001101 +b = 01110110 +c = 111101 +y_mux_uu = 0000000000001101 y_mux_us = 0000000000001101 y_mux_su = 0000000000001101 y_mux_ss = 0000000000001101 +z_mux_uu = 0000000000001101 z_mux_us = 0000000000001101 z_mux_su = 0000000000001101 z_mux_ss = 0000000000001101 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000010 y_sgn_s = 0000000000000010 +z_sgn_u = 1111111111000010 z_sgn_s = 0000000000000010 +y_add_uu = 0000000001001010 y_add_us = 0000000001001010 y_add_su = 0000000001001010 y_add_ss = 0000000000001010 +z_add_uu = 0000000001001010 z_add_us = 0000000001001010 z_add_su = 0000000001001010 z_add_ss = 0000000000001010 +y_sub_uu = 1111111111010000 y_sub_us = 1111111111010000 y_sub_su = 1111111111010000 y_sub_ss = 0000000000010000 +z_sub_uu = 1111111111010000 z_sub_us = 1111111111010000 z_sub_su = 1111111111010000 z_sub_ss = 0000000000010000 +y_mul_uu = 0000001100011001 y_mul_us = 0000001100011001 y_mul_su = 0000001100011001 y_mul_ss = 1111111111011001 +z_mul_uu = 0000001100011001 z_mul_us = 0000001100011001 z_mul_su = 0000001100011001 z_mul_ss = 1111111111011001 +y_ltn_uu = 1 y_ltn_us = 1 y_ltn_su = 1 y_ltn_ss = 0 +z_ltn_uu = 1 z_ltn_us = 1 z_ltn_su = 1 z_ltn_ss = 0 +y_leq_uu = 1 y_leq_us = 1 y_leq_su = 1 y_leq_ss = 0 +z_leq_uu = 1 z_leq_us = 1 z_leq_su = 1 z_leq_ss = 0 +sel = 1 +a = 10001100 +b = 11111001 +c = 000110 +y_mux_uu = 0000000010001100 y_mux_us = 0000000010001100 y_mux_su = 0000000010001100 y_mux_ss = 1111111110001100 +z_mux_uu = 0000000010001100 z_mux_us = 0000000010001100 z_mux_su = 0000000010001100 z_mux_ss = 1111111110001100 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111111001 y_sgn_s = 1111111111111001 +z_sgn_u = 1111111111111001 z_sgn_s = 1111111111111001 +y_add_uu = 0000000010010010 y_add_us = 0000000010010010 y_add_su = 0000000010010010 y_add_ss = 1111111110010010 +z_add_uu = 0000000010010010 z_add_us = 0000000010010010 z_add_su = 0000000010010010 z_add_ss = 1111111110010010 +y_sub_uu = 0000000010000110 y_sub_us = 0000000010000110 y_sub_su = 0000000010000110 y_sub_ss = 1111111110000110 +z_sub_uu = 0000000010000110 z_sub_us = 0000000010000110 z_sub_su = 0000000010000110 z_sub_ss = 1111111110000110 +y_mul_uu = 0000001101001000 y_mul_us = 0000001101001000 y_mul_su = 0000001101001000 y_mul_ss = 1111110101001000 +z_mul_uu = 0000001101001000 z_mul_us = 0000001101001000 z_mul_su = 0000001101001000 z_mul_ss = 1111110101001000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 10101010 +b = 11100101 +c = 110111 +y_mux_uu = 0000000010101010 y_mux_us = 0000000010101010 y_mux_su = 0000000010101010 y_mux_ss = 1111111110101010 +z_mux_uu = 0000000010101010 z_mux_us = 0000000010101010 z_mux_su = 0000000010101010 z_mux_ss = 1111111110101010 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111001000 y_sgn_s = 0000000000001000 +z_sgn_u = 1111111111001000 z_sgn_s = 0000000000001000 +y_add_uu = 0000000011100001 y_add_us = 0000000011100001 y_add_su = 0000000011100001 y_add_ss = 1111111110100001 +z_add_uu = 0000000011100001 z_add_us = 0000000011100001 z_add_su = 0000000011100001 z_add_ss = 1111111110100001 +y_sub_uu = 0000000001110011 y_sub_us = 0000000001110011 y_sub_su = 0000000001110011 y_sub_ss = 1111111110110011 +z_sub_uu = 0000000001110011 z_sub_us = 0000000001110011 z_sub_su = 0000000001110011 z_sub_ss = 1111111110110011 +y_mul_uu = 0010010010000110 y_mul_us = 0010010010000110 y_mul_su = 0010010010000110 y_mul_ss = 0000001100000110 +z_mul_uu = 0010010010000110 z_mul_us = 0010010010000110 z_mul_su = 0010010010000110 z_mul_ss = 0000001100000110 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 10001111 +b = 11110010 +c = 001110 +y_mux_uu = 0000000011110010 y_mux_us = 0000000011110010 y_mux_su = 0000000011110010 y_mux_ss = 1111111111110010 +z_mux_uu = 0000000011110010 z_mux_us = 0000000011110010 z_mux_su = 0000000011110010 z_mux_ss = 1111111111110010 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110001 y_sgn_s = 1111111111110001 +z_sgn_u = 1111111111110001 z_sgn_s = 1111111111110001 +y_add_uu = 0000000010011101 y_add_us = 0000000010011101 y_add_su = 0000000010011101 y_add_ss = 1111111110011101 +z_add_uu = 0000000010011101 z_add_us = 0000000010011101 z_add_su = 0000000010011101 z_add_ss = 1111111110011101 +y_sub_uu = 0000000010000001 y_sub_us = 0000000010000001 y_sub_su = 0000000010000001 y_sub_ss = 1111111110000001 +z_sub_uu = 0000000010000001 z_sub_us = 0000000010000001 z_sub_su = 0000000010000001 z_sub_ss = 1111111110000001 +y_mul_uu = 0000011111010010 y_mul_us = 0000011111010010 y_mul_su = 0000011111010010 y_mul_ss = 1111100111010010 +z_mul_uu = 0000011111010010 z_mul_us = 0000011111010010 z_mul_su = 0000011111010010 z_mul_ss = 1111100111010010 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 11000101 +b = 01011100 +c = 111101 +y_mux_uu = 0000000001011100 y_mux_us = 0000000001011100 y_mux_su = 0000000001011100 y_mux_ss = 0000000001011100 +z_mux_uu = 0000000001011100 z_mux_us = 0000000001011100 z_mux_su = 0000000001011100 z_mux_ss = 0000000001011100 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000010 y_sgn_s = 0000000000000010 +z_sgn_u = 1111111111000010 z_sgn_s = 0000000000000010 +y_add_uu = 0000000100000010 y_add_us = 0000000100000010 y_add_su = 0000000100000010 y_add_ss = 1111111111000010 +z_add_uu = 0000000100000010 z_add_us = 0000000100000010 z_add_su = 0000000100000010 z_add_ss = 1111111111000010 +y_sub_uu = 0000000010001000 y_sub_us = 0000000010001000 y_sub_su = 0000000010001000 y_sub_ss = 1111111111001000 +z_sub_uu = 0000000010001000 z_sub_us = 0000000010001000 z_sub_su = 0000000010001000 z_sub_ss = 1111111111001000 +y_mul_uu = 0010111011110001 y_mul_us = 0010111011110001 y_mul_su = 0010111011110001 y_mul_ss = 0000000010110001 +z_mul_uu = 0010111011110001 z_mul_us = 0010111011110001 z_mul_su = 0010111011110001 z_mul_ss = 0000000010110001 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 01100101 +b = 01100011 +c = 001010 +y_mux_uu = 0000000001100101 y_mux_us = 0000000001100101 y_mux_su = 0000000001100101 y_mux_ss = 0000000001100101 +z_mux_uu = 0000000001100101 z_mux_us = 0000000001100101 z_mux_su = 0000000001100101 z_mux_ss = 0000000001100101 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110101 y_sgn_s = 1111111111110101 +z_sgn_u = 1111111111110101 z_sgn_s = 1111111111110101 +y_add_uu = 0000000001101111 y_add_us = 0000000001101111 y_add_su = 0000000001101111 y_add_ss = 0000000001101111 +z_add_uu = 0000000001101111 z_add_us = 0000000001101111 z_add_su = 0000000001101111 z_add_ss = 0000000001101111 +y_sub_uu = 0000000001011011 y_sub_us = 0000000001011011 y_sub_su = 0000000001011011 y_sub_ss = 0000000001011011 +z_sub_uu = 0000000001011011 z_sub_us = 0000000001011011 z_sub_su = 0000000001011011 z_sub_ss = 0000000001011011 +y_mul_uu = 0000001111110010 y_mul_us = 0000001111110010 y_mul_su = 0000001111110010 y_mul_ss = 0000001111110010 +z_mul_uu = 0000001111110010 z_mul_us = 0000001111110010 z_mul_su = 0000001111110010 z_mul_ss = 0000001111110010 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 00100000 +b = 10101010 +c = 011101 +y_mux_uu = 0000000010101010 y_mux_us = 0000000010101010 y_mux_su = 0000000010101010 y_mux_ss = 1111111110101010 +z_mux_uu = 0000000010101010 z_mux_us = 0000000010101010 z_mux_su = 0000000010101010 z_mux_ss = 1111111110101010 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111100010 y_sgn_s = 1111111111100010 +z_sgn_u = 1111111111100010 z_sgn_s = 1111111111100010 +y_add_uu = 0000000000111101 y_add_us = 0000000000111101 y_add_su = 0000000000111101 y_add_ss = 0000000000111101 +z_add_uu = 0000000000111101 z_add_us = 0000000000111101 z_add_su = 0000000000111101 z_add_ss = 0000000000111101 +y_sub_uu = 0000000000000011 y_sub_us = 0000000000000011 y_sub_su = 0000000000000011 y_sub_ss = 0000000000000011 +z_sub_uu = 0000000000000011 z_sub_us = 0000000000000011 z_sub_su = 0000000000000011 z_sub_ss = 0000000000000011 +y_mul_uu = 0000001110100000 y_mul_us = 0000001110100000 y_mul_su = 0000001110100000 y_mul_ss = 0000001110100000 +z_mul_uu = 0000001110100000 z_mul_us = 0000001110100000 z_mul_su = 0000001110100000 z_mul_ss = 0000001110100000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 00010011 +b = 00001101 +c = 010011 +y_mux_uu = 0000000000001101 y_mux_us = 0000000000001101 y_mux_su = 0000000000001101 y_mux_ss = 0000000000001101 +z_mux_uu = 0000000000001101 z_mux_us = 0000000000001101 z_mux_su = 0000000000001101 z_mux_ss = 0000000000001101 +y_eql_uu = 1 y_eql_us = 1 y_eql_su = 1 y_eql_ss = 1 +z_eql_uu = 1 z_eql_us = 1 z_eql_su = 1 z_eql_ss = 1 +y_neq_uu = 0 y_neq_us = 0 y_neq_su = 0 y_neq_ss = 0 +z_neq_uu = 0 z_neq_us = 0 z_neq_su = 0 z_neq_ss = 0 +y_sgn_u = 1111111111101100 y_sgn_s = 1111111111101100 +z_sgn_u = 1111111111101100 z_sgn_s = 1111111111101100 +y_add_uu = 0000000000100110 y_add_us = 0000000000100110 y_add_su = 0000000000100110 y_add_ss = 0000000000100110 +z_add_uu = 0000000000100110 z_add_us = 0000000000100110 z_add_su = 0000000000100110 z_add_ss = 0000000000100110 +y_sub_uu = 0000000000000000 y_sub_us = 0000000000000000 y_sub_su = 0000000000000000 y_sub_ss = 0000000000000000 +z_sub_uu = 0000000000000000 z_sub_us = 0000000000000000 z_sub_su = 0000000000000000 z_sub_ss = 0000000000000000 +y_mul_uu = 0000000101101001 y_mul_us = 0000000101101001 y_mul_su = 0000000101101001 y_mul_ss = 0000000101101001 +z_mul_uu = 0000000101101001 z_mul_us = 0000000101101001 z_mul_su = 0000000101101001 z_mul_ss = 0000000101101001 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 1 y_leq_us = 1 y_leq_su = 1 y_leq_ss = 1 +z_leq_uu = 1 z_leq_us = 1 z_leq_su = 1 z_leq_ss = 1 +sel = 1 +a = 11010101 +b = 00000010 +c = 101110 +y_mux_uu = 0000000011010101 y_mux_us = 0000000011010101 y_mux_su = 0000000011010101 y_mux_ss = 1111111111010101 +z_mux_uu = 0000000011010101 z_mux_us = 0000000011010101 z_mux_su = 0000000011010101 z_mux_ss = 1111111111010101 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111010001 y_sgn_s = 0000000000010001 +z_sgn_u = 1111111111010001 z_sgn_s = 0000000000010001 +y_add_uu = 0000000100000011 y_add_us = 0000000100000011 y_add_su = 0000000100000011 y_add_ss = 1111111111000011 +z_add_uu = 0000000100000011 z_add_us = 0000000100000011 z_add_su = 0000000100000011 z_add_ss = 1111111111000011 +y_sub_uu = 0000000010100111 y_sub_us = 0000000010100111 y_sub_su = 0000000010100111 y_sub_ss = 1111111111100111 +z_sub_uu = 0000000010100111 z_sub_us = 0000000010100111 z_sub_su = 0000000010100111 z_sub_ss = 1111111111100111 +y_mul_uu = 0010011001000110 y_mul_us = 0010011001000110 y_mul_su = 0010011001000110 y_mul_ss = 0000001100000110 +z_mul_uu = 0010011001000110 z_mul_us = 0010011001000110 z_mul_su = 0010011001000110 z_mul_ss = 0000001100000110 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 11001111 +b = 00100011 +c = 001010 +y_mux_uu = 0000000011001111 y_mux_us = 0000000011001111 y_mux_su = 0000000011001111 y_mux_ss = 1111111111001111 +z_mux_uu = 0000000011001111 z_mux_us = 0000000011001111 z_mux_su = 0000000011001111 z_mux_ss = 1111111111001111 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110101 y_sgn_s = 1111111111110101 +z_sgn_u = 1111111111110101 z_sgn_s = 1111111111110101 +y_add_uu = 0000000011011001 y_add_us = 0000000011011001 y_add_su = 0000000011011001 y_add_ss = 1111111111011001 +z_add_uu = 0000000011011001 z_add_us = 0000000011011001 z_add_su = 0000000011011001 z_add_ss = 1111111111011001 +y_sub_uu = 0000000011000101 y_sub_us = 0000000011000101 y_sub_su = 0000000011000101 y_sub_ss = 1111111111000101 +z_sub_uu = 0000000011000101 z_sub_us = 0000000011000101 z_sub_su = 0000000011000101 z_sub_ss = 1111111111000101 +y_mul_uu = 0000100000010110 y_mul_us = 0000100000010110 y_mul_su = 0000100000010110 y_mul_ss = 1111111000010110 +z_mul_uu = 0000100000010110 z_mul_us = 0000100000010110 z_mul_su = 0000100000010110 z_mul_ss = 1111111000010110 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 00111100 +b = 11110010 +c = 001010 +y_mux_uu = 0000000011110010 y_mux_us = 0000000011110010 y_mux_su = 0000000011110010 y_mux_ss = 1111111111110010 +z_mux_uu = 0000000011110010 z_mux_us = 0000000011110010 z_mux_su = 0000000011110010 z_mux_ss = 1111111111110010 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110101 y_sgn_s = 1111111111110101 +z_sgn_u = 1111111111110101 z_sgn_s = 1111111111110101 +y_add_uu = 0000000001000110 y_add_us = 0000000001000110 y_add_su = 0000000001000110 y_add_ss = 0000000001000110 +z_add_uu = 0000000001000110 z_add_us = 0000000001000110 z_add_su = 0000000001000110 z_add_ss = 0000000001000110 +y_sub_uu = 0000000000110010 y_sub_us = 0000000000110010 y_sub_su = 0000000000110010 y_sub_ss = 0000000000110010 +z_sub_uu = 0000000000110010 z_sub_us = 0000000000110010 z_sub_su = 0000000000110010 z_sub_ss = 0000000000110010 +y_mul_uu = 0000001001011000 y_mul_us = 0000001001011000 y_mul_su = 0000001001011000 y_mul_ss = 0000001001011000 +z_mul_uu = 0000001001011000 z_mul_us = 0000001001011000 z_mul_su = 0000001001011000 z_mul_ss = 0000001001011000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 1 +a = 11011000 +b = 01111000 +c = 001001 +y_mux_uu = 0000000011011000 y_mux_us = 0000000011011000 y_mux_su = 0000000011011000 y_mux_ss = 1111111111011000 +z_mux_uu = 0000000011011000 z_mux_us = 0000000011011000 z_mux_su = 0000000011011000 z_mux_ss = 1111111111011000 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110110 y_sgn_s = 1111111111110110 +z_sgn_u = 1111111111110110 z_sgn_s = 1111111111110110 +y_add_uu = 0000000011100001 y_add_us = 0000000011100001 y_add_su = 0000000011100001 y_add_ss = 1111111111100001 +z_add_uu = 0000000011100001 z_add_us = 0000000011100001 z_add_su = 0000000011100001 z_add_ss = 1111111111100001 +y_sub_uu = 0000000011001111 y_sub_us = 0000000011001111 y_sub_su = 0000000011001111 y_sub_ss = 1111111111001111 +z_sub_uu = 0000000011001111 z_sub_us = 0000000011001111 z_sub_su = 0000000011001111 z_sub_ss = 1111111111001111 +y_mul_uu = 0000011110011000 y_mul_us = 0000011110011000 y_mul_su = 0000011110011000 y_mul_ss = 1111111010011000 +z_mul_uu = 0000011110011000 z_mul_us = 0000011110011000 z_mul_su = 0000011110011000 z_mul_ss = 1111111010011000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 10110110 +b = 11000110 +c = 101110 +y_mux_uu = 0000000010110110 y_mux_us = 0000000010110110 y_mux_su = 0000000010110110 y_mux_ss = 1111111110110110 +z_mux_uu = 0000000010110110 z_mux_us = 0000000010110110 z_mux_su = 0000000010110110 z_mux_ss = 1111111110110110 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111010001 y_sgn_s = 0000000000010001 +z_sgn_u = 1111111111010001 z_sgn_s = 0000000000010001 +y_add_uu = 0000000011100100 y_add_us = 0000000011100100 y_add_su = 0000000011100100 y_add_ss = 1111111110100100 +z_add_uu = 0000000011100100 z_add_us = 0000000011100100 z_add_su = 0000000011100100 z_add_ss = 1111111110100100 +y_sub_uu = 0000000010001000 y_sub_us = 0000000010001000 y_sub_su = 0000000010001000 y_sub_ss = 1111111111001000 +z_sub_uu = 0000000010001000 z_sub_us = 0000000010001000 z_sub_su = 0000000010001000 z_sub_ss = 1111111111001000 +y_mul_uu = 0010000010110100 y_mul_us = 0010000010110100 y_mul_su = 0010000010110100 y_mul_ss = 0000010100110100 +z_mul_uu = 0010000010110100 z_mul_us = 0010000010110100 z_mul_su = 0010000010110100 z_mul_ss = 0000010100110100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 00101010 +b = 00001011 +c = 110001 +y_mux_uu = 0000000000001011 y_mux_us = 0000000000001011 y_mux_su = 0000000000001011 y_mux_ss = 0000000000001011 +z_mux_uu = 0000000000001011 z_mux_us = 0000000000001011 z_mux_su = 0000000000001011 z_mux_ss = 0000000000001011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111001110 y_sgn_s = 0000000000001110 +z_sgn_u = 1111111111001110 z_sgn_s = 0000000000001110 +y_add_uu = 0000000001011011 y_add_us = 0000000001011011 y_add_su = 0000000001011011 y_add_ss = 0000000000011011 +z_add_uu = 0000000001011011 z_add_us = 0000000001011011 z_add_su = 0000000001011011 z_add_ss = 0000000000011011 +y_sub_uu = 1111111111111001 y_sub_us = 1111111111111001 y_sub_su = 1111111111111001 y_sub_ss = 0000000000111001 +z_sub_uu = 1111111111111001 z_sub_us = 1111111111111001 z_sub_su = 1111111111111001 z_sub_ss = 0000000000111001 +y_mul_uu = 0000100000001010 y_mul_us = 0000100000001010 y_mul_su = 0000100000001010 y_mul_ss = 1111110110001010 +z_mul_uu = 0000100000001010 z_mul_us = 0000100000001010 z_mul_su = 0000100000001010 z_mul_ss = 1111110110001010 +y_ltn_uu = 1 y_ltn_us = 1 y_ltn_su = 1 y_ltn_ss = 0 +z_ltn_uu = 1 z_ltn_us = 1 z_ltn_su = 1 z_ltn_ss = 0 +y_leq_uu = 1 y_leq_us = 1 y_leq_su = 1 y_leq_ss = 0 +z_leq_uu = 1 z_leq_us = 1 z_leq_su = 1 z_leq_ss = 0 +sel = 1 +a = 01001111 +b = 00111011 +c = 111010 +y_mux_uu = 0000000001001111 y_mux_us = 0000000001001111 y_mux_su = 0000000001001111 y_mux_ss = 0000000001001111 +z_mux_uu = 0000000001001111 z_mux_us = 0000000001001111 z_mux_su = 0000000001001111 z_mux_ss = 0000000001001111 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000101 y_sgn_s = 0000000000000101 +z_sgn_u = 1111111111000101 z_sgn_s = 0000000000000101 +y_add_uu = 0000000010001001 y_add_us = 0000000010001001 y_add_su = 0000000010001001 y_add_ss = 0000000001001001 +z_add_uu = 0000000010001001 z_add_us = 0000000010001001 z_add_su = 0000000010001001 z_add_ss = 0000000001001001 +y_sub_uu = 0000000000010101 y_sub_us = 0000000000010101 y_sub_su = 0000000000010101 y_sub_ss = 0000000001010101 +z_sub_uu = 0000000000010101 z_sub_us = 0000000000010101 z_sub_su = 0000000000010101 z_sub_ss = 0000000001010101 +y_mul_uu = 0001000111100110 y_mul_us = 0001000111100110 y_mul_su = 0001000111100110 y_mul_ss = 1111111000100110 +z_mul_uu = 0001000111100110 z_mul_us = 0001000111100110 z_mul_su = 0001000111100110 z_mul_ss = 1111111000100110 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 00010101 +b = 11110001 +c = 011001 +y_mux_uu = 0000000011110001 y_mux_us = 0000000011110001 y_mux_su = 0000000011110001 y_mux_ss = 1111111111110001 +z_mux_uu = 0000000011110001 z_mux_us = 0000000011110001 z_mux_su = 0000000011110001 z_mux_ss = 1111111111110001 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111100110 y_sgn_s = 1111111111100110 +z_sgn_u = 1111111111100110 z_sgn_s = 1111111111100110 +y_add_uu = 0000000000101110 y_add_us = 0000000000101110 y_add_su = 0000000000101110 y_add_ss = 0000000000101110 +z_add_uu = 0000000000101110 z_add_us = 0000000000101110 z_add_su = 0000000000101110 z_add_ss = 0000000000101110 +y_sub_uu = 1111111111111100 y_sub_us = 1111111111111100 y_sub_su = 1111111111111100 y_sub_ss = 1111111111111100 +z_sub_uu = 1111111111111100 z_sub_us = 1111111111111100 z_sub_su = 1111111111111100 z_sub_ss = 1111111111111100 +y_mul_uu = 0000001000001101 y_mul_us = 0000001000001101 y_mul_su = 0000001000001101 y_mul_ss = 0000001000001101 +z_mul_uu = 0000001000001101 z_mul_us = 0000001000001101 z_mul_su = 0000001000001101 z_mul_ss = 0000001000001101 +y_ltn_uu = 1 y_ltn_us = 1 y_ltn_su = 1 y_ltn_ss = 1 +z_ltn_uu = 1 z_ltn_us = 1 z_ltn_su = 1 z_ltn_ss = 1 +y_leq_uu = 1 y_leq_us = 1 y_leq_su = 1 y_leq_ss = 1 +z_leq_uu = 1 z_leq_us = 1 z_leq_su = 1 z_leq_ss = 1 +sel = 0 +a = 01001100 +b = 10011111 +c = 001111 +y_mux_uu = 0000000010011111 y_mux_us = 0000000010011111 y_mux_su = 0000000010011111 y_mux_ss = 1111111110011111 +z_mux_uu = 0000000010011111 z_mux_us = 0000000010011111 z_mux_su = 0000000010011111 z_mux_ss = 1111111110011111 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110000 y_sgn_s = 1111111111110000 +z_sgn_u = 1111111111110000 z_sgn_s = 1111111111110000 +y_add_uu = 0000000001011011 y_add_us = 0000000001011011 y_add_su = 0000000001011011 y_add_ss = 0000000001011011 +z_add_uu = 0000000001011011 z_add_us = 0000000001011011 z_add_su = 0000000001011011 z_add_ss = 0000000001011011 +y_sub_uu = 0000000000111101 y_sub_us = 0000000000111101 y_sub_su = 0000000000111101 y_sub_ss = 0000000000111101 +z_sub_uu = 0000000000111101 z_sub_us = 0000000000111101 z_sub_su = 0000000000111101 z_sub_ss = 0000000000111101 +y_mul_uu = 0000010001110100 y_mul_us = 0000010001110100 y_mul_su = 0000010001110100 y_mul_ss = 0000010001110100 +z_mul_uu = 0000010001110100 z_mul_us = 0000010001110100 z_mul_su = 0000010001110100 z_mul_ss = 0000010001110100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 10110111 +b = 10011111 +c = 011100 +y_mux_uu = 0000000010011111 y_mux_us = 0000000010011111 y_mux_su = 0000000010011111 y_mux_ss = 1111111110011111 +z_mux_uu = 0000000010011111 z_mux_us = 0000000010011111 z_mux_su = 0000000010011111 z_mux_ss = 1111111110011111 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111100011 y_sgn_s = 1111111111100011 +z_sgn_u = 1111111111100011 z_sgn_s = 1111111111100011 +y_add_uu = 0000000011010011 y_add_us = 0000000011010011 y_add_su = 0000000011010011 y_add_ss = 1111111111010011 +z_add_uu = 0000000011010011 z_add_us = 0000000011010011 z_add_su = 0000000011010011 z_add_ss = 1111111111010011 +y_sub_uu = 0000000010011011 y_sub_us = 0000000010011011 y_sub_su = 0000000010011011 y_sub_ss = 1111111110011011 +z_sub_uu = 0000000010011011 z_sub_us = 0000000010011011 z_sub_su = 0000000010011011 z_sub_ss = 1111111110011011 +y_mul_uu = 0001010000000100 y_mul_us = 0001010000000100 y_mul_su = 0001010000000100 y_mul_ss = 1111100000000100 +z_mul_uu = 0001010000000100 z_mul_us = 0001010000000100 z_mul_su = 0001010000000100 z_mul_ss = 1111100000000100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 10001001 +b = 01001001 +c = 010000 +y_mux_uu = 0000000010001001 y_mux_us = 0000000010001001 y_mux_su = 0000000010001001 y_mux_ss = 1111111110001001 +z_mux_uu = 0000000010001001 z_mux_us = 0000000010001001 z_mux_su = 0000000010001001 z_mux_ss = 1111111110001001 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111101111 y_sgn_s = 1111111111101111 +z_sgn_u = 1111111111101111 z_sgn_s = 1111111111101111 +y_add_uu = 0000000010011001 y_add_us = 0000000010011001 y_add_su = 0000000010011001 y_add_ss = 1111111110011001 +z_add_uu = 0000000010011001 z_add_us = 0000000010011001 z_add_su = 0000000010011001 z_add_ss = 1111111110011001 +y_sub_uu = 0000000001111001 y_sub_us = 0000000001111001 y_sub_su = 0000000001111001 y_sub_ss = 1111111101111001 +z_sub_uu = 0000000001111001 z_sub_us = 0000000001111001 z_sub_su = 0000000001111001 z_sub_ss = 1111111101111001 +y_mul_uu = 0000100010010000 y_mul_us = 0000100010010000 y_mul_su = 0000100010010000 y_mul_ss = 1111100010010000 +z_mul_uu = 0000100010010000 z_mul_us = 0000100010010000 z_mul_su = 0000100010010000 z_mul_ss = 1111100010010000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 01010001 +b = 10010110 +c = 001100 +y_mux_uu = 0000000001010001 y_mux_us = 0000000001010001 y_mux_su = 0000000001010001 y_mux_ss = 0000000001010001 +z_mux_uu = 0000000001010001 z_mux_us = 0000000001010001 z_mux_su = 0000000001010001 z_mux_ss = 0000000001010001 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110011 y_sgn_s = 1111111111110011 +z_sgn_u = 1111111111110011 z_sgn_s = 1111111111110011 +y_add_uu = 0000000001011101 y_add_us = 0000000001011101 y_add_su = 0000000001011101 y_add_ss = 0000000001011101 +z_add_uu = 0000000001011101 z_add_us = 0000000001011101 z_add_su = 0000000001011101 z_add_ss = 0000000001011101 +y_sub_uu = 0000000001000101 y_sub_us = 0000000001000101 y_sub_su = 0000000001000101 y_sub_ss = 0000000001000101 +z_sub_uu = 0000000001000101 z_sub_us = 0000000001000101 z_sub_su = 0000000001000101 z_sub_ss = 0000000001000101 +y_mul_uu = 0000001111001100 y_mul_us = 0000001111001100 y_mul_su = 0000001111001100 y_mul_ss = 0000001111001100 +z_mul_uu = 0000001111001100 z_mul_us = 0000001111001100 z_mul_su = 0000001111001100 z_mul_ss = 0000001111001100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 11001000 +b = 01110111 +c = 111101 +y_mux_uu = 0000000001110111 y_mux_us = 0000000001110111 y_mux_su = 0000000001110111 y_mux_ss = 0000000001110111 +z_mux_uu = 0000000001110111 z_mux_us = 0000000001110111 z_mux_su = 0000000001110111 z_mux_ss = 0000000001110111 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000010 y_sgn_s = 0000000000000010 +z_sgn_u = 1111111111000010 z_sgn_s = 0000000000000010 +y_add_uu = 0000000100000101 y_add_us = 0000000100000101 y_add_su = 0000000100000101 y_add_ss = 1111111111000101 +z_add_uu = 0000000100000101 z_add_us = 0000000100000101 z_add_su = 0000000100000101 z_add_ss = 1111111111000101 +y_sub_uu = 0000000010001011 y_sub_us = 0000000010001011 y_sub_su = 0000000010001011 y_sub_ss = 1111111111001011 +z_sub_uu = 0000000010001011 z_sub_us = 0000000010001011 z_sub_su = 0000000010001011 z_sub_ss = 1111111111001011 +y_mul_uu = 0010111110101000 y_mul_us = 0010111110101000 y_mul_su = 0010111110101000 y_mul_ss = 0000000010101000 +z_mul_uu = 0010111110101000 z_mul_us = 0010111110101000 z_mul_su = 0010111110101000 z_mul_ss = 0000000010101000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 01111110 +b = 01101101 +c = 111001 +y_mux_uu = 0000000001101101 y_mux_us = 0000000001101101 y_mux_su = 0000000001101101 y_mux_ss = 0000000001101101 +z_mux_uu = 0000000001101101 z_mux_us = 0000000001101101 z_mux_su = 0000000001101101 z_mux_ss = 0000000001101101 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000110 y_sgn_s = 0000000000000110 +z_sgn_u = 1111111111000110 z_sgn_s = 0000000000000110 +y_add_uu = 0000000010110111 y_add_us = 0000000010110111 y_add_su = 0000000010110111 y_add_ss = 0000000001110111 +z_add_uu = 0000000010110111 z_add_us = 0000000010110111 z_add_su = 0000000010110111 z_add_ss = 0000000001110111 +y_sub_uu = 0000000001000101 y_sub_us = 0000000001000101 y_sub_su = 0000000001000101 y_sub_ss = 0000000010000101 +z_sub_uu = 0000000001000101 z_sub_us = 0000000001000101 z_sub_su = 0000000001000101 z_sub_ss = 0000000010000101 +y_mul_uu = 0001110000001110 y_mul_us = 0001110000001110 y_mul_su = 0001110000001110 y_mul_ss = 1111110010001110 +z_mul_uu = 0001110000001110 z_mul_us = 0001110000001110 z_mul_su = 0001110000001110 z_mul_ss = 1111110010001110 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 1 +a = 11010011 +b = 10000101 +c = 111000 +y_mux_uu = 0000000011010011 y_mux_us = 0000000011010011 y_mux_su = 0000000011010011 y_mux_ss = 1111111111010011 +z_mux_uu = 0000000011010011 z_mux_us = 0000000011010011 z_mux_su = 0000000011010011 z_mux_ss = 1111111111010011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000111 y_sgn_s = 0000000000000111 +z_sgn_u = 1111111111000111 z_sgn_s = 0000000000000111 +y_add_uu = 0000000100001011 y_add_us = 0000000100001011 y_add_su = 0000000100001011 y_add_ss = 1111111111001011 +z_add_uu = 0000000100001011 z_add_us = 0000000100001011 z_add_su = 0000000100001011 z_add_ss = 1111111111001011 +y_sub_uu = 0000000010011011 y_sub_us = 0000000010011011 y_sub_su = 0000000010011011 y_sub_ss = 1111111111011011 +z_sub_uu = 0000000010011011 z_sub_us = 0000000010011011 z_sub_su = 0000000010011011 z_sub_ss = 1111111111011011 +y_mul_uu = 0010111000101000 y_mul_us = 0010111000101000 y_mul_su = 0010111000101000 y_mul_ss = 0000000101101000 +z_mul_uu = 0010111000101000 z_mul_us = 0010111000101000 z_mul_su = 0010111000101000 z_mul_ss = 0000000101101000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 01001001 +b = 00111111 +c = 101010 +y_mux_uu = 0000000001001001 y_mux_us = 0000000001001001 y_mux_su = 0000000001001001 y_mux_ss = 0000000001001001 +z_mux_uu = 0000000001001001 z_mux_us = 0000000001001001 z_mux_su = 0000000001001001 z_mux_ss = 0000000001001001 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111010101 y_sgn_s = 0000000000010101 +z_sgn_u = 1111111111010101 z_sgn_s = 0000000000010101 +y_add_uu = 0000000001110011 y_add_us = 0000000001110011 y_add_su = 0000000001110011 y_add_ss = 0000000000110011 +z_add_uu = 0000000001110011 z_add_us = 0000000001110011 z_add_su = 0000000001110011 z_add_ss = 0000000000110011 +y_sub_uu = 0000000000011111 y_sub_us = 0000000000011111 y_sub_su = 0000000000011111 y_sub_ss = 0000000001011111 +z_sub_uu = 0000000000011111 z_sub_us = 0000000000011111 z_sub_su = 0000000000011111 z_sub_ss = 0000000001011111 +y_mul_uu = 0000101111111010 y_mul_us = 0000101111111010 y_mul_su = 0000101111111010 y_mul_ss = 1111100110111010 +z_mul_uu = 0000101111111010 z_mul_us = 0000101111111010 z_mul_su = 0000101111111010 z_mul_ss = 1111100110111010 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 10000110 +b = 10001110 +c = 011100 +y_mux_uu = 0000000010001110 y_mux_us = 0000000010001110 y_mux_su = 0000000010001110 y_mux_ss = 1111111110001110 +z_mux_uu = 0000000010001110 z_mux_us = 0000000010001110 z_mux_su = 0000000010001110 z_mux_ss = 1111111110001110 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111100011 y_sgn_s = 1111111111100011 +z_sgn_u = 1111111111100011 z_sgn_s = 1111111111100011 +y_add_uu = 0000000010100010 y_add_us = 0000000010100010 y_add_su = 0000000010100010 y_add_ss = 1111111110100010 +z_add_uu = 0000000010100010 z_add_us = 0000000010100010 z_add_su = 0000000010100010 z_add_ss = 1111111110100010 +y_sub_uu = 0000000001101010 y_sub_us = 0000000001101010 y_sub_su = 0000000001101010 y_sub_ss = 1111111101101010 +z_sub_uu = 0000000001101010 z_sub_us = 0000000001101010 z_sub_su = 0000000001101010 z_sub_ss = 1111111101101010 +y_mul_uu = 0000111010101000 y_mul_us = 0000111010101000 y_mul_su = 0000111010101000 y_mul_ss = 1111001010101000 +z_mul_uu = 0000111010101000 z_mul_us = 0000111010101000 z_mul_su = 0000111010101000 z_mul_ss = 1111001010101000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 00100110 +b = 01110011 +c = 100011 +y_mux_uu = 0000000001110011 y_mux_us = 0000000001110011 y_mux_su = 0000000001110011 y_mux_ss = 0000000001110011 +z_mux_uu = 0000000001110011 z_mux_us = 0000000001110011 z_mux_su = 0000000001110011 z_mux_ss = 0000000001110011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111011100 y_sgn_s = 0000000000011100 +z_sgn_u = 1111111111011100 z_sgn_s = 0000000000011100 +y_add_uu = 0000000001001001 y_add_us = 0000000001001001 y_add_su = 0000000001001001 y_add_ss = 0000000000001001 +z_add_uu = 0000000001001001 z_add_us = 0000000001001001 z_add_su = 0000000001001001 z_add_ss = 0000000000001001 +y_sub_uu = 0000000000000011 y_sub_us = 0000000000000011 y_sub_su = 0000000000000011 y_sub_ss = 0000000001000011 +z_sub_uu = 0000000000000011 z_sub_us = 0000000000000011 z_sub_su = 0000000000000011 z_sub_ss = 0000000001000011 +y_mul_uu = 0000010100110010 y_mul_us = 0000010100110010 y_mul_su = 0000010100110010 y_mul_ss = 1111101110110010 +z_mul_uu = 0000010100110010 z_mul_us = 0000010100110010 z_mul_su = 0000010100110010 z_mul_ss = 1111101110110010 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 1 +a = 10110011 +b = 01011111 +c = 000100 +y_mux_uu = 0000000010110011 y_mux_us = 0000000010110011 y_mux_su = 0000000010110011 y_mux_ss = 1111111110110011 +z_mux_uu = 0000000010110011 z_mux_us = 0000000010110011 z_mux_su = 0000000010110011 z_mux_ss = 1111111110110011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111111011 y_sgn_s = 1111111111111011 +z_sgn_u = 1111111111111011 z_sgn_s = 1111111111111011 +y_add_uu = 0000000010110111 y_add_us = 0000000010110111 y_add_su = 0000000010110111 y_add_ss = 1111111110110111 +z_add_uu = 0000000010110111 z_add_us = 0000000010110111 z_add_su = 0000000010110111 z_add_ss = 1111111110110111 +y_sub_uu = 0000000010101111 y_sub_us = 0000000010101111 y_sub_su = 0000000010101111 y_sub_ss = 1111111110101111 +z_sub_uu = 0000000010101111 z_sub_us = 0000000010101111 z_sub_su = 0000000010101111 z_sub_ss = 1111111110101111 +y_mul_uu = 0000001011001100 y_mul_us = 0000001011001100 y_mul_su = 0000001011001100 y_mul_ss = 1111111011001100 +z_mul_uu = 0000001011001100 z_mul_us = 0000001011001100 z_mul_su = 0000001011001100 z_mul_ss = 1111111011001100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 11001011 +b = 11100110 +c = 011010 +y_mux_uu = 0000000011001011 y_mux_us = 0000000011001011 y_mux_su = 0000000011001011 y_mux_ss = 1111111111001011 +z_mux_uu = 0000000011001011 z_mux_us = 0000000011001011 z_mux_su = 0000000011001011 z_mux_ss = 1111111111001011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111100101 y_sgn_s = 1111111111100101 +z_sgn_u = 1111111111100101 z_sgn_s = 1111111111100101 +y_add_uu = 0000000011100101 y_add_us = 0000000011100101 y_add_su = 0000000011100101 y_add_ss = 1111111111100101 +z_add_uu = 0000000011100101 z_add_us = 0000000011100101 z_add_su = 0000000011100101 z_add_ss = 1111111111100101 +y_sub_uu = 0000000010110001 y_sub_us = 0000000010110001 y_sub_su = 0000000010110001 y_sub_ss = 1111111110110001 +z_sub_uu = 0000000010110001 z_sub_us = 0000000010110001 z_sub_su = 0000000010110001 z_sub_ss = 1111111110110001 +y_mul_uu = 0001010010011110 y_mul_us = 0001010010011110 y_mul_su = 0001010010011110 y_mul_ss = 1111101010011110 +z_mul_uu = 0001010010011110 z_mul_us = 0001010010011110 z_mul_su = 0001010010011110 z_mul_ss = 1111101010011110 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 11101101 +b = 11011010 +c = 100101 +y_mux_uu = 0000000011101101 y_mux_us = 0000000011101101 y_mux_su = 0000000011101101 y_mux_ss = 1111111111101101 +z_mux_uu = 0000000011101101 z_mux_us = 0000000011101101 z_mux_su = 0000000011101101 z_mux_ss = 1111111111101101 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111011010 y_sgn_s = 0000000000011010 +z_sgn_u = 1111111111011010 z_sgn_s = 0000000000011010 +y_add_uu = 0000000100010010 y_add_us = 0000000100010010 y_add_su = 0000000100010010 y_add_ss = 1111111111010010 +z_add_uu = 0000000100010010 z_add_us = 0000000100010010 z_add_su = 0000000100010010 z_add_ss = 1111111111010010 +y_sub_uu = 0000000011001000 y_sub_us = 0000000011001000 y_sub_su = 0000000011001000 y_sub_ss = 0000000000001000 +z_sub_uu = 0000000011001000 z_sub_us = 0000000011001000 z_sub_su = 0000000011001000 z_sub_ss = 0000000000001000 +y_mul_uu = 0010001001000001 y_mul_us = 0010001001000001 y_mul_su = 0010001001000001 y_mul_ss = 0000001000000001 +z_mul_uu = 0010001001000001 z_mul_us = 0010001001000001 z_mul_su = 0010001001000001 z_mul_ss = 0000001000000001 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 1 +a = 11011111 +b = 01111001 +c = 000100 +y_mux_uu = 0000000011011111 y_mux_us = 0000000011011111 y_mux_su = 0000000011011111 y_mux_ss = 1111111111011111 +z_mux_uu = 0000000011011111 z_mux_us = 0000000011011111 z_mux_su = 0000000011011111 z_mux_ss = 1111111111011111 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111111011 y_sgn_s = 1111111111111011 +z_sgn_u = 1111111111111011 z_sgn_s = 1111111111111011 +y_add_uu = 0000000011100011 y_add_us = 0000000011100011 y_add_su = 0000000011100011 y_add_ss = 1111111111100011 +z_add_uu = 0000000011100011 z_add_us = 0000000011100011 z_add_su = 0000000011100011 z_add_ss = 1111111111100011 +y_sub_uu = 0000000011011011 y_sub_us = 0000000011011011 y_sub_su = 0000000011011011 y_sub_ss = 1111111111011011 +z_sub_uu = 0000000011011011 z_sub_us = 0000000011011011 z_sub_su = 0000000011011011 z_sub_ss = 1111111111011011 +y_mul_uu = 0000001101111100 y_mul_us = 0000001101111100 y_mul_su = 0000001101111100 y_mul_ss = 1111111101111100 +z_mul_uu = 0000001101111100 z_mul_us = 0000001101111100 z_mul_su = 0000001101111100 z_mul_ss = 1111111101111100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 00101010 +b = 10101011 +c = 001110 +y_mux_uu = 0000000010101011 y_mux_us = 0000000010101011 y_mux_su = 0000000010101011 y_mux_ss = 1111111110101011 +z_mux_uu = 0000000010101011 z_mux_us = 0000000010101011 z_mux_su = 0000000010101011 z_mux_ss = 1111111110101011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110001 y_sgn_s = 1111111111110001 +z_sgn_u = 1111111111110001 z_sgn_s = 1111111111110001 +y_add_uu = 0000000000111000 y_add_us = 0000000000111000 y_add_su = 0000000000111000 y_add_ss = 0000000000111000 +z_add_uu = 0000000000111000 z_add_us = 0000000000111000 z_add_su = 0000000000111000 z_add_ss = 0000000000111000 +y_sub_uu = 0000000000011100 y_sub_us = 0000000000011100 y_sub_su = 0000000000011100 y_sub_ss = 0000000000011100 +z_sub_uu = 0000000000011100 z_sub_us = 0000000000011100 z_sub_su = 0000000000011100 z_sub_ss = 0000000000011100 +y_mul_uu = 0000001001001100 y_mul_us = 0000001001001100 y_mul_su = 0000001001001100 y_mul_ss = 0000001001001100 +z_mul_uu = 0000001001001100 z_mul_us = 0000001001001100 z_mul_su = 0000001001001100 z_mul_ss = 0000001001001100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 10011010 +b = 11111101 +c = 000011 +y_mux_uu = 0000000011111101 y_mux_us = 0000000011111101 y_mux_su = 0000000011111101 y_mux_ss = 1111111111111101 +z_mux_uu = 0000000011111101 z_mux_us = 0000000011111101 z_mux_su = 0000000011111101 z_mux_ss = 1111111111111101 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111111100 y_sgn_s = 1111111111111100 +z_sgn_u = 1111111111111100 z_sgn_s = 1111111111111100 +y_add_uu = 0000000010011101 y_add_us = 0000000010011101 y_add_su = 0000000010011101 y_add_ss = 1111111110011101 +z_add_uu = 0000000010011101 z_add_us = 0000000010011101 z_add_su = 0000000010011101 z_add_ss = 1111111110011101 +y_sub_uu = 0000000010010111 y_sub_us = 0000000010010111 y_sub_su = 0000000010010111 y_sub_ss = 1111111110010111 +z_sub_uu = 0000000010010111 z_sub_us = 0000000010010111 z_sub_su = 0000000010010111 z_sub_ss = 1111111110010111 +y_mul_uu = 0000000111001110 y_mul_us = 0000000111001110 y_mul_su = 0000000111001110 y_mul_ss = 1111111011001110 +z_mul_uu = 0000000111001110 z_mul_us = 0000000111001110 z_mul_su = 0000000111001110 z_mul_ss = 1111111011001110 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 01001110 +b = 01100111 +c = 001010 +y_mux_uu = 0000000001100111 y_mux_us = 0000000001100111 y_mux_su = 0000000001100111 y_mux_ss = 0000000001100111 +z_mux_uu = 0000000001100111 z_mux_us = 0000000001100111 z_mux_su = 0000000001100111 z_mux_ss = 0000000001100111 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110101 y_sgn_s = 1111111111110101 +z_sgn_u = 1111111111110101 z_sgn_s = 1111111111110101 +y_add_uu = 0000000001011000 y_add_us = 0000000001011000 y_add_su = 0000000001011000 y_add_ss = 0000000001011000 +z_add_uu = 0000000001011000 z_add_us = 0000000001011000 z_add_su = 0000000001011000 z_add_ss = 0000000001011000 +y_sub_uu = 0000000001000100 y_sub_us = 0000000001000100 y_sub_su = 0000000001000100 y_sub_ss = 0000000001000100 +z_sub_uu = 0000000001000100 z_sub_us = 0000000001000100 z_sub_su = 0000000001000100 z_sub_ss = 0000000001000100 +y_mul_uu = 0000001100001100 y_mul_us = 0000001100001100 y_mul_su = 0000001100001100 y_mul_ss = 0000001100001100 +z_mul_uu = 0000001100001100 z_mul_us = 0000001100001100 z_mul_su = 0000001100001100 z_mul_ss = 0000001100001100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 00111000 +b = 01111001 +c = 111000 +y_mux_uu = 0000000001111001 y_mux_us = 0000000001111001 y_mux_su = 0000000001111001 y_mux_ss = 0000000001111001 +z_mux_uu = 0000000001111001 z_mux_us = 0000000001111001 z_mux_su = 0000000001111001 z_mux_ss = 0000000001111001 +y_eql_uu = 1 y_eql_us = 1 y_eql_su = 1 y_eql_ss = 0 +z_eql_uu = 1 z_eql_us = 1 z_eql_su = 1 z_eql_ss = 0 +y_neq_uu = 0 y_neq_us = 0 y_neq_su = 0 y_neq_ss = 1 +z_neq_uu = 0 z_neq_us = 0 z_neq_su = 0 z_neq_ss = 1 +y_sgn_u = 1111111111000111 y_sgn_s = 0000000000000111 +z_sgn_u = 1111111111000111 z_sgn_s = 0000000000000111 +y_add_uu = 0000000001110000 y_add_us = 0000000001110000 y_add_su = 0000000001110000 y_add_ss = 0000000000110000 +z_add_uu = 0000000001110000 z_add_us = 0000000001110000 z_add_su = 0000000001110000 z_add_ss = 0000000000110000 +y_sub_uu = 0000000000000000 y_sub_us = 0000000000000000 y_sub_su = 0000000000000000 y_sub_ss = 0000000001000000 +z_sub_uu = 0000000000000000 z_sub_us = 0000000000000000 z_sub_su = 0000000000000000 z_sub_ss = 0000000001000000 +y_mul_uu = 0000110001000000 y_mul_us = 0000110001000000 y_mul_su = 0000110001000000 y_mul_ss = 1111111001000000 +z_mul_uu = 0000110001000000 z_mul_us = 0000110001000000 z_mul_su = 0000110001000000 z_mul_ss = 1111111001000000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 1 y_leq_us = 1 y_leq_su = 1 y_leq_ss = 0 +z_leq_uu = 1 z_leq_us = 1 z_leq_su = 1 z_leq_ss = 0 +sel = 0 +a = 10010011 +b = 00000100 +c = 011001 +y_mux_uu = 0000000000000100 y_mux_us = 0000000000000100 y_mux_su = 0000000000000100 y_mux_ss = 0000000000000100 +z_mux_uu = 0000000000000100 z_mux_us = 0000000000000100 z_mux_su = 0000000000000100 z_mux_ss = 0000000000000100 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111100110 y_sgn_s = 1111111111100110 +z_sgn_u = 1111111111100110 z_sgn_s = 1111111111100110 +y_add_uu = 0000000010101100 y_add_us = 0000000010101100 y_add_su = 0000000010101100 y_add_ss = 1111111110101100 +z_add_uu = 0000000010101100 z_add_us = 0000000010101100 z_add_su = 0000000010101100 z_add_ss = 1111111110101100 +y_sub_uu = 0000000001111010 y_sub_us = 0000000001111010 y_sub_su = 0000000001111010 y_sub_ss = 1111111101111010 +z_sub_uu = 0000000001111010 z_sub_us = 0000000001111010 z_sub_su = 0000000001111010 z_sub_ss = 1111111101111010 +y_mul_uu = 0000111001011011 y_mul_us = 0000111001011011 y_mul_su = 0000111001011011 y_mul_ss = 1111010101011011 +z_mul_uu = 0000111001011011 z_mul_us = 0000111001011011 z_mul_su = 0000111001011011 z_mul_ss = 1111010101011011 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 01001101 +b = 11011001 +c = 101101 +y_mux_uu = 0000000001001101 y_mux_us = 0000000001001101 y_mux_su = 0000000001001101 y_mux_ss = 0000000001001101 +z_mux_uu = 0000000001001101 z_mux_us = 0000000001001101 z_mux_su = 0000000001001101 z_mux_ss = 0000000001001101 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111010010 y_sgn_s = 0000000000010010 +z_sgn_u = 1111111111010010 z_sgn_s = 0000000000010010 +y_add_uu = 0000000001111010 y_add_us = 0000000001111010 y_add_su = 0000000001111010 y_add_ss = 0000000000111010 +z_add_uu = 0000000001111010 z_add_us = 0000000001111010 z_add_su = 0000000001111010 z_add_ss = 0000000000111010 +y_sub_uu = 0000000000100000 y_sub_us = 0000000000100000 y_sub_su = 0000000000100000 y_sub_ss = 0000000001100000 +z_sub_uu = 0000000000100000 z_sub_us = 0000000000100000 z_sub_su = 0000000000100000 z_sub_ss = 0000000001100000 +y_mul_uu = 0000110110001001 y_mul_us = 0000110110001001 y_mul_su = 0000110110001001 y_mul_ss = 1111101001001001 +z_mul_uu = 0000110110001001 z_mul_us = 0000110110001001 z_mul_su = 0000110110001001 z_mul_ss = 1111101001001001 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 11001010 +b = 10110110 +c = 010101 +y_mux_uu = 0000000010110110 y_mux_us = 0000000010110110 y_mux_su = 0000000010110110 y_mux_ss = 1111111110110110 +z_mux_uu = 0000000010110110 z_mux_us = 0000000010110110 z_mux_su = 0000000010110110 z_mux_ss = 1111111110110110 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111101010 y_sgn_s = 1111111111101010 +z_sgn_u = 1111111111101010 z_sgn_s = 1111111111101010 +y_add_uu = 0000000011011111 y_add_us = 0000000011011111 y_add_su = 0000000011011111 y_add_ss = 1111111111011111 +z_add_uu = 0000000011011111 z_add_us = 0000000011011111 z_add_su = 0000000011011111 z_add_ss = 1111111111011111 +y_sub_uu = 0000000010110101 y_sub_us = 0000000010110101 y_sub_su = 0000000010110101 y_sub_ss = 1111111110110101 +z_sub_uu = 0000000010110101 z_sub_us = 0000000010110101 z_sub_su = 0000000010110101 z_sub_ss = 1111111110110101 +y_mul_uu = 0001000010010010 y_mul_us = 0001000010010010 y_mul_su = 0001000010010010 y_mul_ss = 1111101110010010 +z_mul_uu = 0001000010010010 z_mul_us = 0001000010010010 z_mul_su = 0001000010010010 z_mul_ss = 1111101110010010 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 00000100 +b = 11110111 +c = 101001 +y_mux_uu = 0000000011110111 y_mux_us = 0000000011110111 y_mux_su = 0000000011110111 y_mux_ss = 1111111111110111 +z_mux_uu = 0000000011110111 z_mux_us = 0000000011110111 z_mux_su = 0000000011110111 z_mux_ss = 1111111111110111 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111010110 y_sgn_s = 0000000000010110 +z_sgn_u = 1111111111010110 z_sgn_s = 0000000000010110 +y_add_uu = 0000000000101101 y_add_us = 0000000000101101 y_add_su = 0000000000101101 y_add_ss = 1111111111101101 +z_add_uu = 0000000000101101 z_add_us = 0000000000101101 z_add_su = 0000000000101101 z_add_ss = 1111111111101101 +y_sub_uu = 1111111111011011 y_sub_us = 1111111111011011 y_sub_su = 1111111111011011 y_sub_ss = 0000000000011011 +z_sub_uu = 1111111111011011 z_sub_us = 1111111111011011 z_sub_su = 1111111111011011 z_sub_ss = 0000000000011011 +y_mul_uu = 0000000010100100 y_mul_us = 0000000010100100 y_mul_su = 0000000010100100 y_mul_ss = 1111111110100100 +z_mul_uu = 0000000010100100 z_mul_us = 0000000010100100 z_mul_su = 0000000010100100 z_mul_ss = 1111111110100100 +y_ltn_uu = 1 y_ltn_us = 1 y_ltn_su = 1 y_ltn_ss = 0 +z_ltn_uu = 1 z_ltn_us = 1 z_ltn_su = 1 z_ltn_ss = 0 +y_leq_uu = 1 y_leq_us = 1 y_leq_su = 1 y_leq_ss = 0 +z_leq_uu = 1 z_leq_us = 1 z_leq_su = 1 z_leq_ss = 0 +sel = 0 +a = 10001000 +b = 00101000 +c = 101101 +y_mux_uu = 0000000000101000 y_mux_us = 0000000000101000 y_mux_su = 0000000000101000 y_mux_ss = 0000000000101000 +z_mux_uu = 0000000000101000 z_mux_us = 0000000000101000 z_mux_su = 0000000000101000 z_mux_ss = 0000000000101000 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111010010 y_sgn_s = 0000000000010010 +z_sgn_u = 1111111111010010 z_sgn_s = 0000000000010010 +y_add_uu = 0000000010110101 y_add_us = 0000000010110101 y_add_su = 0000000010110101 y_add_ss = 1111111101110101 +z_add_uu = 0000000010110101 z_add_us = 0000000010110101 z_add_su = 0000000010110101 z_add_ss = 1111111101110101 +y_sub_uu = 0000000001011011 y_sub_us = 0000000001011011 y_sub_su = 0000000001011011 y_sub_ss = 1111111110011011 +z_sub_uu = 0000000001011011 z_sub_us = 0000000001011011 z_sub_su = 0000000001011011 z_sub_ss = 1111111110011011 +y_mul_uu = 0001011111101000 y_mul_us = 0001011111101000 y_mul_su = 0001011111101000 y_mul_ss = 0000100011101000 +z_mul_uu = 0001011111101000 z_mul_us = 0001011111101000 z_mul_su = 0001011111101000 z_mul_ss = 0000100011101000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 00101110 +b = 00001000 +c = 011100 +y_mux_uu = 0000000000101110 y_mux_us = 0000000000101110 y_mux_su = 0000000000101110 y_mux_ss = 0000000000101110 +z_mux_uu = 0000000000101110 z_mux_us = 0000000000101110 z_mux_su = 0000000000101110 z_mux_ss = 0000000000101110 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111100011 y_sgn_s = 1111111111100011 +z_sgn_u = 1111111111100011 z_sgn_s = 1111111111100011 +y_add_uu = 0000000001001010 y_add_us = 0000000001001010 y_add_su = 0000000001001010 y_add_ss = 0000000001001010 +z_add_uu = 0000000001001010 z_add_us = 0000000001001010 z_add_su = 0000000001001010 z_add_ss = 0000000001001010 +y_sub_uu = 0000000000010010 y_sub_us = 0000000000010010 y_sub_su = 0000000000010010 y_sub_ss = 0000000000010010 +z_sub_uu = 0000000000010010 z_sub_us = 0000000000010010 z_sub_su = 0000000000010010 z_sub_ss = 0000000000010010 +y_mul_uu = 0000010100001000 y_mul_us = 0000010100001000 y_mul_su = 0000010100001000 y_mul_ss = 0000010100001000 +z_mul_uu = 0000010100001000 z_mul_us = 0000010100001000 z_mul_su = 0000010100001000 z_mul_ss = 0000010100001000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 1 +a = 00101001 +b = 00011100 +c = 000110 +y_mux_uu = 0000000000101001 y_mux_us = 0000000000101001 y_mux_su = 0000000000101001 y_mux_ss = 0000000000101001 +z_mux_uu = 0000000000101001 z_mux_us = 0000000000101001 z_mux_su = 0000000000101001 z_mux_ss = 0000000000101001 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111111001 y_sgn_s = 1111111111111001 +z_sgn_u = 1111111111111001 z_sgn_s = 1111111111111001 +y_add_uu = 0000000000101111 y_add_us = 0000000000101111 y_add_su = 0000000000101111 y_add_ss = 0000000000101111 +z_add_uu = 0000000000101111 z_add_us = 0000000000101111 z_add_su = 0000000000101111 z_add_ss = 0000000000101111 +y_sub_uu = 0000000000100011 y_sub_us = 0000000000100011 y_sub_su = 0000000000100011 y_sub_ss = 0000000000100011 +z_sub_uu = 0000000000100011 z_sub_us = 0000000000100011 z_sub_su = 0000000000100011 z_sub_ss = 0000000000100011 +y_mul_uu = 0000000011110110 y_mul_us = 0000000011110110 y_mul_su = 0000000011110110 y_mul_ss = 0000000011110110 +z_mul_uu = 0000000011110110 z_mul_us = 0000000011110110 z_mul_su = 0000000011110110 z_mul_ss = 0000000011110110 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 00111101 +b = 01100110 +c = 110000 +y_mux_uu = 0000000001100110 y_mux_us = 0000000001100110 y_mux_su = 0000000001100110 y_mux_ss = 0000000001100110 +z_mux_uu = 0000000001100110 z_mux_us = 0000000001100110 z_mux_su = 0000000001100110 z_mux_ss = 0000000001100110 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111001111 y_sgn_s = 0000000000001111 +z_sgn_u = 1111111111001111 z_sgn_s = 0000000000001111 +y_add_uu = 0000000001101101 y_add_us = 0000000001101101 y_add_su = 0000000001101101 y_add_ss = 0000000000101101 +z_add_uu = 0000000001101101 z_add_us = 0000000001101101 z_add_su = 0000000001101101 z_add_ss = 0000000000101101 +y_sub_uu = 0000000000001101 y_sub_us = 0000000000001101 y_sub_su = 0000000000001101 y_sub_ss = 0000000001001101 +z_sub_uu = 0000000000001101 z_sub_us = 0000000000001101 z_sub_su = 0000000000001101 z_sub_ss = 0000000001001101 +y_mul_uu = 0000101101110000 y_mul_us = 0000101101110000 y_mul_su = 0000101101110000 y_mul_ss = 1111110000110000 +z_mul_uu = 0000101101110000 z_mul_us = 0000101101110000 z_mul_su = 0000101101110000 z_mul_ss = 1111110000110000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 1 +a = 10111010 +b = 01011110 +c = 111010 +y_mux_uu = 0000000010111010 y_mux_us = 0000000010111010 y_mux_su = 0000000010111010 y_mux_ss = 1111111110111010 +z_mux_uu = 0000000010111010 z_mux_us = 0000000010111010 z_mux_su = 0000000010111010 z_mux_ss = 1111111110111010 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000101 y_sgn_s = 0000000000000101 +z_sgn_u = 1111111111000101 z_sgn_s = 0000000000000101 +y_add_uu = 0000000011110100 y_add_us = 0000000011110100 y_add_su = 0000000011110100 y_add_ss = 1111111110110100 +z_add_uu = 0000000011110100 z_add_us = 0000000011110100 z_add_su = 0000000011110100 z_add_ss = 1111111110110100 +y_sub_uu = 0000000010000000 y_sub_us = 0000000010000000 y_sub_su = 0000000010000000 y_sub_ss = 1111111111000000 +z_sub_uu = 0000000010000000 z_sub_us = 0000000010000000 z_sub_su = 0000000010000000 z_sub_ss = 1111111111000000 +y_mul_uu = 0010101000100100 y_mul_us = 0010101000100100 y_mul_su = 0010101000100100 y_mul_ss = 0000000110100100 +z_mul_uu = 0010101000100100 z_mul_us = 0010101000100100 z_mul_su = 0010101000100100 z_mul_ss = 0000000110100100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 00011010 +b = 10111001 +c = 110111 +y_mux_uu = 0000000000011010 y_mux_us = 0000000000011010 y_mux_su = 0000000000011010 y_mux_ss = 0000000000011010 +z_mux_uu = 0000000000011010 z_mux_us = 0000000000011010 z_mux_su = 0000000000011010 z_mux_ss = 0000000000011010 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111001000 y_sgn_s = 0000000000001000 +z_sgn_u = 1111111111001000 z_sgn_s = 0000000000001000 +y_add_uu = 0000000001010001 y_add_us = 0000000001010001 y_add_su = 0000000001010001 y_add_ss = 0000000000010001 +z_add_uu = 0000000001010001 z_add_us = 0000000001010001 z_add_su = 0000000001010001 z_add_ss = 0000000000010001 +y_sub_uu = 1111111111100011 y_sub_us = 1111111111100011 y_sub_su = 1111111111100011 y_sub_ss = 0000000000100011 +z_sub_uu = 1111111111100011 z_sub_us = 1111111111100011 z_sub_su = 1111111111100011 z_sub_ss = 0000000000100011 +y_mul_uu = 0000010110010110 y_mul_us = 0000010110010110 y_mul_su = 0000010110010110 y_mul_ss = 1111111100010110 +z_mul_uu = 0000010110010110 z_mul_us = 0000010110010110 z_mul_su = 0000010110010110 z_mul_ss = 1111111100010110 +y_ltn_uu = 1 y_ltn_us = 1 y_ltn_su = 1 y_ltn_ss = 0 +z_ltn_uu = 1 z_ltn_us = 1 z_ltn_su = 1 z_ltn_ss = 0 +y_leq_uu = 1 y_leq_us = 1 y_leq_su = 1 y_leq_ss = 0 +z_leq_uu = 1 z_leq_us = 1 z_leq_su = 1 z_leq_ss = 0 +sel = 0 +a = 11000000 +b = 00100110 +c = 110110 +y_mux_uu = 0000000000100110 y_mux_us = 0000000000100110 y_mux_su = 0000000000100110 y_mux_ss = 0000000000100110 +z_mux_uu = 0000000000100110 z_mux_us = 0000000000100110 z_mux_su = 0000000000100110 z_mux_ss = 0000000000100110 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111001001 y_sgn_s = 0000000000001001 +z_sgn_u = 1111111111001001 z_sgn_s = 0000000000001001 +y_add_uu = 0000000011110110 y_add_us = 0000000011110110 y_add_su = 0000000011110110 y_add_ss = 1111111110110110 +z_add_uu = 0000000011110110 z_add_us = 0000000011110110 z_add_su = 0000000011110110 z_add_ss = 1111111110110110 +y_sub_uu = 0000000010001010 y_sub_us = 0000000010001010 y_sub_su = 0000000010001010 y_sub_ss = 1111111111001010 +z_sub_uu = 0000000010001010 z_sub_us = 0000000010001010 z_sub_su = 0000000010001010 z_sub_ss = 1111111111001010 +y_mul_uu = 0010100010000000 y_mul_us = 0010100010000000 y_mul_su = 0010100010000000 y_mul_ss = 0000001010000000 +z_mul_uu = 0010100010000000 z_mul_us = 0010100010000000 z_mul_su = 0010100010000000 z_mul_ss = 0000001010000000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 11011100 +b = 10000110 +c = 111000 +y_mux_uu = 0000000011011100 y_mux_us = 0000000011011100 y_mux_su = 0000000011011100 y_mux_ss = 1111111111011100 +z_mux_uu = 0000000011011100 z_mux_us = 0000000011011100 z_mux_su = 0000000011011100 z_mux_ss = 1111111111011100 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000111 y_sgn_s = 0000000000000111 +z_sgn_u = 1111111111000111 z_sgn_s = 0000000000000111 +y_add_uu = 0000000100010100 y_add_us = 0000000100010100 y_add_su = 0000000100010100 y_add_ss = 1111111111010100 +z_add_uu = 0000000100010100 z_add_us = 0000000100010100 z_add_su = 0000000100010100 z_add_ss = 1111111111010100 +y_sub_uu = 0000000010100100 y_sub_us = 0000000010100100 y_sub_su = 0000000010100100 y_sub_ss = 1111111111100100 +z_sub_uu = 0000000010100100 z_sub_us = 0000000010100100 z_sub_su = 0000000010100100 z_sub_ss = 1111111111100100 +y_mul_uu = 0011000000100000 y_mul_us = 0011000000100000 y_mul_su = 0011000000100000 y_mul_ss = 0000000100100000 +z_mul_uu = 0011000000100000 z_mul_us = 0011000000100000 z_mul_su = 0011000000100000 z_mul_ss = 0000000100100000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 11011011 +b = 11001111 +c = 111001 +y_mux_uu = 0000000011001111 y_mux_us = 0000000011001111 y_mux_su = 0000000011001111 y_mux_ss = 1111111111001111 +z_mux_uu = 0000000011001111 z_mux_us = 0000000011001111 z_mux_su = 0000000011001111 z_mux_ss = 1111111111001111 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000110 y_sgn_s = 0000000000000110 +z_sgn_u = 1111111111000110 z_sgn_s = 0000000000000110 +y_add_uu = 0000000100010100 y_add_us = 0000000100010100 y_add_su = 0000000100010100 y_add_ss = 1111111111010100 +z_add_uu = 0000000100010100 z_add_us = 0000000100010100 z_add_su = 0000000100010100 z_add_ss = 1111111111010100 +y_sub_uu = 0000000010100010 y_sub_us = 0000000010100010 y_sub_su = 0000000010100010 y_sub_ss = 1111111111100010 +z_sub_uu = 0000000010100010 z_sub_us = 0000000010100010 z_sub_su = 0000000010100010 z_sub_ss = 1111111111100010 +y_mul_uu = 0011000011000011 y_mul_us = 0011000011000011 y_mul_su = 0011000011000011 y_mul_ss = 0000000100000011 +z_mul_uu = 0011000011000011 z_mul_us = 0011000011000011 z_mul_su = 0011000011000011 z_mul_ss = 0000000100000011 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 01100001 +b = 00010111 +c = 100001 +y_mux_uu = 0000000000010111 y_mux_us = 0000000000010111 y_mux_su = 0000000000010111 y_mux_ss = 0000000000010111 +z_mux_uu = 0000000000010111 z_mux_us = 0000000000010111 z_mux_su = 0000000000010111 z_mux_ss = 0000000000010111 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111011110 y_sgn_s = 0000000000011110 +z_sgn_u = 1111111111011110 z_sgn_s = 0000000000011110 +y_add_uu = 0000000010000010 y_add_us = 0000000010000010 y_add_su = 0000000010000010 y_add_ss = 0000000001000010 +z_add_uu = 0000000010000010 z_add_us = 0000000010000010 z_add_su = 0000000010000010 z_add_ss = 0000000001000010 +y_sub_uu = 0000000001000000 y_sub_us = 0000000001000000 y_sub_su = 0000000001000000 y_sub_ss = 0000000010000000 +z_sub_uu = 0000000001000000 z_sub_us = 0000000001000000 z_sub_su = 0000000001000000 z_sub_ss = 0000000010000000 +y_mul_uu = 0000110010000001 y_mul_us = 0000110010000001 y_mul_su = 0000110010000001 y_mul_ss = 1111010001000001 +z_mul_uu = 0000110010000001 z_mul_us = 0000110010000001 z_mul_su = 0000110010000001 z_mul_ss = 1111010001000001 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 01010000 +b = 11110101 +c = 110101 +y_mux_uu = 0000000011110101 y_mux_us = 0000000011110101 y_mux_su = 0000000011110101 y_mux_ss = 1111111111110101 +z_mux_uu = 0000000011110101 z_mux_us = 0000000011110101 z_mux_su = 0000000011110101 z_mux_ss = 1111111111110101 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111001010 y_sgn_s = 0000000000001010 +z_sgn_u = 1111111111001010 z_sgn_s = 0000000000001010 +y_add_uu = 0000000010000101 y_add_us = 0000000010000101 y_add_su = 0000000010000101 y_add_ss = 0000000001000101 +z_add_uu = 0000000010000101 z_add_us = 0000000010000101 z_add_su = 0000000010000101 z_add_ss = 0000000001000101 +y_sub_uu = 0000000000011011 y_sub_us = 0000000000011011 y_sub_su = 0000000000011011 y_sub_ss = 0000000001011011 +z_sub_uu = 0000000000011011 z_sub_us = 0000000000011011 z_sub_su = 0000000000011011 z_sub_ss = 0000000001011011 +y_mul_uu = 0001000010010000 y_mul_us = 0001000010010000 y_mul_su = 0001000010010000 y_mul_ss = 1111110010010000 +z_mul_uu = 0001000010010000 z_mul_us = 0001000010010000 z_mul_su = 0001000010010000 z_mul_ss = 1111110010010000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 1 +a = 11000001 +b = 11000101 +c = 011000 +y_mux_uu = 0000000011000001 y_mux_us = 0000000011000001 y_mux_su = 0000000011000001 y_mux_ss = 1111111111000001 +z_mux_uu = 0000000011000001 z_mux_us = 0000000011000001 z_mux_su = 0000000011000001 z_mux_ss = 1111111111000001 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111100111 y_sgn_s = 1111111111100111 +z_sgn_u = 1111111111100111 z_sgn_s = 1111111111100111 +y_add_uu = 0000000011011001 y_add_us = 0000000011011001 y_add_su = 0000000011011001 y_add_ss = 1111111111011001 +z_add_uu = 0000000011011001 z_add_us = 0000000011011001 z_add_su = 0000000011011001 z_add_ss = 1111111111011001 +y_sub_uu = 0000000010101001 y_sub_us = 0000000010101001 y_sub_su = 0000000010101001 y_sub_ss = 1111111110101001 +z_sub_uu = 0000000010101001 z_sub_us = 0000000010101001 z_sub_su = 0000000010101001 z_sub_ss = 1111111110101001 +y_mul_uu = 0001001000011000 y_mul_us = 0001001000011000 y_mul_su = 0001001000011000 y_mul_ss = 1111101000011000 +z_mul_uu = 0001001000011000 z_mul_us = 0001001000011000 z_mul_su = 0001001000011000 z_mul_ss = 1111101000011000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 01110011 +b = 11101100 +c = 001010 +y_mux_uu = 0000000001110011 y_mux_us = 0000000001110011 y_mux_su = 0000000001110011 y_mux_ss = 0000000001110011 +z_mux_uu = 0000000001110011 z_mux_us = 0000000001110011 z_mux_su = 0000000001110011 z_mux_ss = 0000000001110011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110101 y_sgn_s = 1111111111110101 +z_sgn_u = 1111111111110101 z_sgn_s = 1111111111110101 +y_add_uu = 0000000001111101 y_add_us = 0000000001111101 y_add_su = 0000000001111101 y_add_ss = 0000000001111101 +z_add_uu = 0000000001111101 z_add_us = 0000000001111101 z_add_su = 0000000001111101 z_add_ss = 0000000001111101 +y_sub_uu = 0000000001101001 y_sub_us = 0000000001101001 y_sub_su = 0000000001101001 y_sub_ss = 0000000001101001 +z_sub_uu = 0000000001101001 z_sub_us = 0000000001101001 z_sub_su = 0000000001101001 z_sub_ss = 0000000001101001 +y_mul_uu = 0000010001111110 y_mul_us = 0000010001111110 y_mul_su = 0000010001111110 y_mul_ss = 0000010001111110 +z_mul_uu = 0000010001111110 z_mul_us = 0000010001111110 z_mul_su = 0000010001111110 z_mul_ss = 0000010001111110 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 10101000 +b = 10101001 +c = 100001 +y_mux_uu = 0000000010101001 y_mux_us = 0000000010101001 y_mux_su = 0000000010101001 y_mux_ss = 1111111110101001 +z_mux_uu = 0000000010101001 z_mux_us = 0000000010101001 z_mux_su = 0000000010101001 z_mux_ss = 1111111110101001 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111011110 y_sgn_s = 0000000000011110 +z_sgn_u = 1111111111011110 z_sgn_s = 0000000000011110 +y_add_uu = 0000000011001001 y_add_us = 0000000011001001 y_add_su = 0000000011001001 y_add_ss = 1111111110001001 +z_add_uu = 0000000011001001 z_add_us = 0000000011001001 z_add_su = 0000000011001001 z_add_ss = 1111111110001001 +y_sub_uu = 0000000010000111 y_sub_us = 0000000010000111 y_sub_su = 0000000010000111 y_sub_ss = 1111111111000111 +z_sub_uu = 0000000010000111 z_sub_us = 0000000010000111 z_sub_su = 0000000010000111 z_sub_ss = 1111111111000111 +y_mul_uu = 0001010110101000 y_mul_us = 0001010110101000 y_mul_su = 0001010110101000 y_mul_ss = 0000101010101000 +z_mul_uu = 0001010110101000 z_mul_us = 0001010110101000 z_mul_su = 0001010110101000 z_mul_ss = 0000101010101000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 11100110 +b = 10011111 +c = 101010 +y_mux_uu = 0000000010011111 y_mux_us = 0000000010011111 y_mux_su = 0000000010011111 y_mux_ss = 1111111110011111 +z_mux_uu = 0000000010011111 z_mux_us = 0000000010011111 z_mux_su = 0000000010011111 z_mux_ss = 1111111110011111 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111010101 y_sgn_s = 0000000000010101 +z_sgn_u = 1111111111010101 z_sgn_s = 0000000000010101 +y_add_uu = 0000000100010000 y_add_us = 0000000100010000 y_add_su = 0000000100010000 y_add_ss = 1111111111010000 +z_add_uu = 0000000100010000 z_add_us = 0000000100010000 z_add_su = 0000000100010000 z_add_ss = 1111111111010000 +y_sub_uu = 0000000010111100 y_sub_us = 0000000010111100 y_sub_su = 0000000010111100 y_sub_ss = 1111111111111100 +z_sub_uu = 0000000010111100 z_sub_us = 0000000010111100 z_sub_su = 0000000010111100 z_sub_ss = 1111111111111100 +y_mul_uu = 0010010110111100 y_mul_us = 0010010110111100 y_mul_su = 0010010110111100 y_mul_ss = 0000001000111100 +z_mul_uu = 0010010110111100 z_mul_us = 0010010110111100 z_mul_su = 0010010110111100 z_mul_ss = 0000001000111100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 10001101 +b = 10011110 +c = 111000 +y_mux_uu = 0000000010011110 y_mux_us = 0000000010011110 y_mux_su = 0000000010011110 y_mux_ss = 1111111110011110 +z_mux_uu = 0000000010011110 z_mux_us = 0000000010011110 z_mux_su = 0000000010011110 z_mux_ss = 1111111110011110 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000111 y_sgn_s = 0000000000000111 +z_sgn_u = 1111111111000111 z_sgn_s = 0000000000000111 +y_add_uu = 0000000011000101 y_add_us = 0000000011000101 y_add_su = 0000000011000101 y_add_ss = 1111111110000101 +z_add_uu = 0000000011000101 z_add_us = 0000000011000101 z_add_su = 0000000011000101 z_add_ss = 1111111110000101 +y_sub_uu = 0000000001010101 y_sub_us = 0000000001010101 y_sub_su = 0000000001010101 y_sub_ss = 1111111110010101 +z_sub_uu = 0000000001010101 z_sub_us = 0000000001010101 z_sub_su = 0000000001010101 z_sub_ss = 1111111110010101 +y_mul_uu = 0001111011011000 y_mul_us = 0001111011011000 y_mul_su = 0001111011011000 y_mul_ss = 0000001110011000 +z_mul_uu = 0001111011011000 z_mul_us = 0001111011011000 z_mul_su = 0001111011011000 z_mul_ss = 0000001110011000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 11001000 +b = 11001010 +c = 010011 +y_mux_uu = 0000000011001000 y_mux_us = 0000000011001000 y_mux_su = 0000000011001000 y_mux_ss = 1111111111001000 +z_mux_uu = 0000000011001000 z_mux_us = 0000000011001000 z_mux_su = 0000000011001000 z_mux_ss = 1111111111001000 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111101100 y_sgn_s = 1111111111101100 +z_sgn_u = 1111111111101100 z_sgn_s = 1111111111101100 +y_add_uu = 0000000011011011 y_add_us = 0000000011011011 y_add_su = 0000000011011011 y_add_ss = 1111111111011011 +z_add_uu = 0000000011011011 z_add_us = 0000000011011011 z_add_su = 0000000011011011 z_add_ss = 1111111111011011 +y_sub_uu = 0000000010110101 y_sub_us = 0000000010110101 y_sub_su = 0000000010110101 y_sub_ss = 1111111110110101 +z_sub_uu = 0000000010110101 z_sub_us = 0000000010110101 z_sub_su = 0000000010110101 z_sub_ss = 1111111110110101 +y_mul_uu = 0000111011011000 y_mul_us = 0000111011011000 y_mul_su = 0000111011011000 y_mul_ss = 1111101111011000 +z_mul_uu = 0000111011011000 z_mul_us = 0000111011011000 z_mul_su = 0000111011011000 z_mul_ss = 1111101111011000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 11000111 +b = 10110110 +c = 111010 +y_mux_uu = 0000000011000111 y_mux_us = 0000000011000111 y_mux_su = 0000000011000111 y_mux_ss = 1111111111000111 +z_mux_uu = 0000000011000111 z_mux_us = 0000000011000111 z_mux_su = 0000000011000111 z_mux_ss = 1111111111000111 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000101 y_sgn_s = 0000000000000101 +z_sgn_u = 1111111111000101 z_sgn_s = 0000000000000101 +y_add_uu = 0000000100000001 y_add_us = 0000000100000001 y_add_su = 0000000100000001 y_add_ss = 1111111111000001 +z_add_uu = 0000000100000001 z_add_us = 0000000100000001 z_add_su = 0000000100000001 z_add_ss = 1111111111000001 +y_sub_uu = 0000000010001101 y_sub_us = 0000000010001101 y_sub_su = 0000000010001101 y_sub_ss = 1111111111001101 +z_sub_uu = 0000000010001101 z_sub_us = 0000000010001101 z_sub_su = 0000000010001101 z_sub_ss = 1111111111001101 +y_mul_uu = 0010110100010110 y_mul_us = 0010110100010110 y_mul_su = 0010110100010110 y_mul_ss = 0000000101010110 +z_mul_uu = 0010110100010110 z_mul_us = 0010110100010110 z_mul_su = 0010110100010110 z_mul_ss = 0000000101010110 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 10111001 +b = 10010010 +c = 110100 +y_mux_uu = 0000000010010010 y_mux_us = 0000000010010010 y_mux_su = 0000000010010010 y_mux_ss = 1111111110010010 +z_mux_uu = 0000000010010010 z_mux_us = 0000000010010010 z_mux_su = 0000000010010010 z_mux_ss = 1111111110010010 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111001011 y_sgn_s = 0000000000001011 +z_sgn_u = 1111111111001011 z_sgn_s = 0000000000001011 +y_add_uu = 0000000011101101 y_add_us = 0000000011101101 y_add_su = 0000000011101101 y_add_ss = 1111111110101101 +z_add_uu = 0000000011101101 z_add_us = 0000000011101101 z_add_su = 0000000011101101 z_add_ss = 1111111110101101 +y_sub_uu = 0000000010000101 y_sub_us = 0000000010000101 y_sub_su = 0000000010000101 y_sub_ss = 1111111111000101 +z_sub_uu = 0000000010000101 z_sub_us = 0000000010000101 z_sub_su = 0000000010000101 z_sub_ss = 1111111111000101 +y_mul_uu = 0010010110010100 y_mul_us = 0010010110010100 y_mul_su = 0010010110010100 y_mul_ss = 0000001101010100 +z_mul_uu = 0010010110010100 z_mul_us = 0010010110010100 z_mul_su = 0010010110010100 z_mul_ss = 0000001101010100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 10000110 +b = 11111010 +c = 110010 +y_mux_uu = 0000000010000110 y_mux_us = 0000000010000110 y_mux_su = 0000000010000110 y_mux_ss = 1111111110000110 +z_mux_uu = 0000000010000110 z_mux_us = 0000000010000110 z_mux_su = 0000000010000110 z_mux_ss = 1111111110000110 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111001101 y_sgn_s = 0000000000001101 +z_sgn_u = 1111111111001101 z_sgn_s = 0000000000001101 +y_add_uu = 0000000010111000 y_add_us = 0000000010111000 y_add_su = 0000000010111000 y_add_ss = 1111111101111000 +z_add_uu = 0000000010111000 z_add_us = 0000000010111000 z_add_su = 0000000010111000 z_add_ss = 1111111101111000 +y_sub_uu = 0000000001010100 y_sub_us = 0000000001010100 y_sub_su = 0000000001010100 y_sub_ss = 1111111110010100 +z_sub_uu = 0000000001010100 z_sub_us = 0000000001010100 z_sub_su = 0000000001010100 z_sub_ss = 1111111110010100 +y_mul_uu = 0001101000101100 y_mul_us = 0001101000101100 y_mul_su = 0001101000101100 y_mul_ss = 0000011010101100 +z_mul_uu = 0001101000101100 z_mul_us = 0001101000101100 z_mul_su = 0001101000101100 z_mul_ss = 0000011010101100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 10111101 +b = 10000100 +c = 100100 +y_mux_uu = 0000000010000100 y_mux_us = 0000000010000100 y_mux_su = 0000000010000100 y_mux_ss = 1111111110000100 +z_mux_uu = 0000000010000100 z_mux_us = 0000000010000100 z_mux_su = 0000000010000100 z_mux_ss = 1111111110000100 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111011011 y_sgn_s = 0000000000011011 +z_sgn_u = 1111111111011011 z_sgn_s = 0000000000011011 +y_add_uu = 0000000011100001 y_add_us = 0000000011100001 y_add_su = 0000000011100001 y_add_ss = 1111111110100001 +z_add_uu = 0000000011100001 z_add_us = 0000000011100001 z_add_su = 0000000011100001 z_add_ss = 1111111110100001 +y_sub_uu = 0000000010011001 y_sub_us = 0000000010011001 y_sub_su = 0000000010011001 y_sub_ss = 1111111111011001 +z_sub_uu = 0000000010011001 z_sub_us = 0000000010011001 z_sub_su = 0000000010011001 z_sub_ss = 1111111111011001 +y_mul_uu = 0001101010010100 y_mul_us = 0001101010010100 y_mul_su = 0001101010010100 y_mul_ss = 0000011101010100 +z_mul_uu = 0001101010010100 z_mul_us = 0001101010010100 z_mul_su = 0001101010010100 z_mul_ss = 0000011101010100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 10101001 +b = 10100001 +c = 001110 +y_mux_uu = 0000000010100001 y_mux_us = 0000000010100001 y_mux_su = 0000000010100001 y_mux_ss = 1111111110100001 +z_mux_uu = 0000000010100001 z_mux_us = 0000000010100001 z_mux_su = 0000000010100001 z_mux_ss = 1111111110100001 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110001 y_sgn_s = 1111111111110001 +z_sgn_u = 1111111111110001 z_sgn_s = 1111111111110001 +y_add_uu = 0000000010110111 y_add_us = 0000000010110111 y_add_su = 0000000010110111 y_add_ss = 1111111110110111 +z_add_uu = 0000000010110111 z_add_us = 0000000010110111 z_add_su = 0000000010110111 z_add_ss = 1111111110110111 +y_sub_uu = 0000000010011011 y_sub_us = 0000000010011011 y_sub_su = 0000000010011011 y_sub_ss = 1111111110011011 +z_sub_uu = 0000000010011011 z_sub_us = 0000000010011011 z_sub_su = 0000000010011011 z_sub_ss = 1111111110011011 +y_mul_uu = 0000100100111110 y_mul_us = 0000100100111110 y_mul_su = 0000100100111110 y_mul_ss = 1111101100111110 +z_mul_uu = 0000100100111110 z_mul_us = 0000100100111110 z_mul_su = 0000100100111110 z_mul_ss = 1111101100111110 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 00001011 +b = 11101111 +c = 001001 +y_mux_uu = 0000000000001011 y_mux_us = 0000000000001011 y_mux_su = 0000000000001011 y_mux_ss = 0000000000001011 +z_mux_uu = 0000000000001011 z_mux_us = 0000000000001011 z_mux_su = 0000000000001011 z_mux_ss = 0000000000001011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110110 y_sgn_s = 1111111111110110 +z_sgn_u = 1111111111110110 z_sgn_s = 1111111111110110 +y_add_uu = 0000000000010100 y_add_us = 0000000000010100 y_add_su = 0000000000010100 y_add_ss = 0000000000010100 +z_add_uu = 0000000000010100 z_add_us = 0000000000010100 z_add_su = 0000000000010100 z_add_ss = 0000000000010100 +y_sub_uu = 0000000000000010 y_sub_us = 0000000000000010 y_sub_su = 0000000000000010 y_sub_ss = 0000000000000010 +z_sub_uu = 0000000000000010 z_sub_us = 0000000000000010 z_sub_su = 0000000000000010 z_sub_ss = 0000000000000010 +y_mul_uu = 0000000001100011 y_mul_us = 0000000001100011 y_mul_su = 0000000001100011 y_mul_ss = 0000000001100011 +z_mul_uu = 0000000001100011 z_mul_us = 0000000001100011 z_mul_su = 0000000001100011 z_mul_ss = 0000000001100011 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 01110101 +b = 10001111 +c = 101011 +y_mux_uu = 0000000010001111 y_mux_us = 0000000010001111 y_mux_su = 0000000010001111 y_mux_ss = 1111111110001111 +z_mux_uu = 0000000010001111 z_mux_us = 0000000010001111 z_mux_su = 0000000010001111 z_mux_ss = 1111111110001111 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111010100 y_sgn_s = 0000000000010100 +z_sgn_u = 1111111111010100 z_sgn_s = 0000000000010100 +y_add_uu = 0000000010100000 y_add_us = 0000000010100000 y_add_su = 0000000010100000 y_add_ss = 0000000001100000 +z_add_uu = 0000000010100000 z_add_us = 0000000010100000 z_add_su = 0000000010100000 z_add_ss = 0000000001100000 +y_sub_uu = 0000000001001010 y_sub_us = 0000000001001010 y_sub_su = 0000000001001010 y_sub_ss = 0000000010001010 +z_sub_uu = 0000000001001010 z_sub_us = 0000000001001010 z_sub_su = 0000000001001010 z_sub_ss = 0000000010001010 +y_mul_uu = 0001001110100111 y_mul_us = 0001001110100111 y_mul_su = 0001001110100111 y_mul_ss = 1111011001100111 +z_mul_uu = 0001001110100111 z_mul_us = 0001001110100111 z_mul_su = 0001001110100111 z_mul_ss = 1111011001100111 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 10101110 +b = 10011011 +c = 010010 +y_mux_uu = 0000000010011011 y_mux_us = 0000000010011011 y_mux_su = 0000000010011011 y_mux_ss = 1111111110011011 +z_mux_uu = 0000000010011011 z_mux_us = 0000000010011011 z_mux_su = 0000000010011011 z_mux_ss = 1111111110011011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111101101 y_sgn_s = 1111111111101101 +z_sgn_u = 1111111111101101 z_sgn_s = 1111111111101101 +y_add_uu = 0000000011000000 y_add_us = 0000000011000000 y_add_su = 0000000011000000 y_add_ss = 1111111111000000 +z_add_uu = 0000000011000000 z_add_us = 0000000011000000 z_add_su = 0000000011000000 z_add_ss = 1111111111000000 +y_sub_uu = 0000000010011100 y_sub_us = 0000000010011100 y_sub_su = 0000000010011100 y_sub_ss = 1111111110011100 +z_sub_uu = 0000000010011100 z_sub_us = 0000000010011100 z_sub_su = 0000000010011100 z_sub_ss = 1111111110011100 +y_mul_uu = 0000110000111100 y_mul_us = 0000110000111100 y_mul_su = 0000110000111100 y_mul_ss = 1111101000111100 +z_mul_uu = 0000110000111100 z_mul_us = 0000110000111100 z_mul_su = 0000110000111100 z_mul_ss = 1111101000111100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 00101101 +b = 01001011 +c = 000010 +y_mux_uu = 0000000001001011 y_mux_us = 0000000001001011 y_mux_su = 0000000001001011 y_mux_ss = 0000000001001011 +z_mux_uu = 0000000001001011 z_mux_us = 0000000001001011 z_mux_su = 0000000001001011 z_mux_ss = 0000000001001011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111111101 y_sgn_s = 1111111111111101 +z_sgn_u = 1111111111111101 z_sgn_s = 1111111111111101 +y_add_uu = 0000000000101111 y_add_us = 0000000000101111 y_add_su = 0000000000101111 y_add_ss = 0000000000101111 +z_add_uu = 0000000000101111 z_add_us = 0000000000101111 z_add_su = 0000000000101111 z_add_ss = 0000000000101111 +y_sub_uu = 0000000000101011 y_sub_us = 0000000000101011 y_sub_su = 0000000000101011 y_sub_ss = 0000000000101011 +z_sub_uu = 0000000000101011 z_sub_us = 0000000000101011 z_sub_su = 0000000000101011 z_sub_ss = 0000000000101011 +y_mul_uu = 0000000001011010 y_mul_us = 0000000001011010 y_mul_su = 0000000001011010 y_mul_ss = 0000000001011010 +z_mul_uu = 0000000001011010 z_mul_us = 0000000001011010 z_mul_su = 0000000001011010 z_mul_ss = 0000000001011010 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 00001101 +b = 11101100 +c = 011000 +y_mux_uu = 0000000011101100 y_mux_us = 0000000011101100 y_mux_su = 0000000011101100 y_mux_ss = 1111111111101100 +z_mux_uu = 0000000011101100 z_mux_us = 0000000011101100 z_mux_su = 0000000011101100 z_mux_ss = 1111111111101100 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111100111 y_sgn_s = 1111111111100111 +z_sgn_u = 1111111111100111 z_sgn_s = 1111111111100111 +y_add_uu = 0000000000100101 y_add_us = 0000000000100101 y_add_su = 0000000000100101 y_add_ss = 0000000000100101 +z_add_uu = 0000000000100101 z_add_us = 0000000000100101 z_add_su = 0000000000100101 z_add_ss = 0000000000100101 +y_sub_uu = 1111111111110101 y_sub_us = 1111111111110101 y_sub_su = 1111111111110101 y_sub_ss = 1111111111110101 +z_sub_uu = 1111111111110101 z_sub_us = 1111111111110101 z_sub_su = 1111111111110101 z_sub_ss = 1111111111110101 +y_mul_uu = 0000000100111000 y_mul_us = 0000000100111000 y_mul_su = 0000000100111000 y_mul_ss = 0000000100111000 +z_mul_uu = 0000000100111000 z_mul_us = 0000000100111000 z_mul_su = 0000000100111000 z_mul_ss = 0000000100111000 +y_ltn_uu = 1 y_ltn_us = 1 y_ltn_su = 1 y_ltn_ss = 1 +z_ltn_uu = 1 z_ltn_us = 1 z_ltn_su = 1 z_ltn_ss = 1 +y_leq_uu = 1 y_leq_us = 1 y_leq_su = 1 y_leq_ss = 1 +z_leq_uu = 1 z_leq_us = 1 z_leq_su = 1 z_leq_ss = 1 +sel = 1 +a = 10000110 +b = 01000001 +c = 111011 +y_mux_uu = 0000000010000110 y_mux_us = 0000000010000110 y_mux_su = 0000000010000110 y_mux_ss = 1111111110000110 +z_mux_uu = 0000000010000110 z_mux_us = 0000000010000110 z_mux_su = 0000000010000110 z_mux_ss = 1111111110000110 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000100 y_sgn_s = 0000000000000100 +z_sgn_u = 1111111111000100 z_sgn_s = 0000000000000100 +y_add_uu = 0000000011000001 y_add_us = 0000000011000001 y_add_su = 0000000011000001 y_add_ss = 1111111110000001 +z_add_uu = 0000000011000001 z_add_us = 0000000011000001 z_add_su = 0000000011000001 z_add_ss = 1111111110000001 +y_sub_uu = 0000000001001011 y_sub_us = 0000000001001011 y_sub_su = 0000000001001011 y_sub_ss = 1111111110001011 +z_sub_uu = 0000000001001011 z_sub_us = 0000000001001011 z_sub_su = 0000000001001011 z_sub_ss = 1111111110001011 +y_mul_uu = 0001111011100010 y_mul_us = 0001111011100010 y_mul_su = 0001111011100010 y_mul_ss = 0000001001100010 +z_mul_uu = 0001111011100010 z_mul_us = 0001111011100010 z_mul_su = 0001111011100010 z_mul_ss = 0000001001100010 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 01010011 +b = 01010110 +c = 011011 +y_mux_uu = 0000000001010110 y_mux_us = 0000000001010110 y_mux_su = 0000000001010110 y_mux_ss = 0000000001010110 +z_mux_uu = 0000000001010110 z_mux_us = 0000000001010110 z_mux_su = 0000000001010110 z_mux_ss = 0000000001010110 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111100100 y_sgn_s = 1111111111100100 +z_sgn_u = 1111111111100100 z_sgn_s = 1111111111100100 +y_add_uu = 0000000001101110 y_add_us = 0000000001101110 y_add_su = 0000000001101110 y_add_ss = 0000000001101110 +z_add_uu = 0000000001101110 z_add_us = 0000000001101110 z_add_su = 0000000001101110 z_add_ss = 0000000001101110 +y_sub_uu = 0000000000111000 y_sub_us = 0000000000111000 y_sub_su = 0000000000111000 y_sub_ss = 0000000000111000 +z_sub_uu = 0000000000111000 z_sub_us = 0000000000111000 z_sub_su = 0000000000111000 z_sub_ss = 0000000000111000 +y_mul_uu = 0000100011000001 y_mul_us = 0000100011000001 y_mul_su = 0000100011000001 y_mul_ss = 0000100011000001 +z_mul_uu = 0000100011000001 z_mul_us = 0000100011000001 z_mul_su = 0000100011000001 z_mul_ss = 0000100011000001 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 00000100 +b = 01110011 +c = 011000 +y_mux_uu = 0000000001110011 y_mux_us = 0000000001110011 y_mux_su = 0000000001110011 y_mux_ss = 0000000001110011 +z_mux_uu = 0000000001110011 z_mux_us = 0000000001110011 z_mux_su = 0000000001110011 z_mux_ss = 0000000001110011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111100111 y_sgn_s = 1111111111100111 +z_sgn_u = 1111111111100111 z_sgn_s = 1111111111100111 +y_add_uu = 0000000000011100 y_add_us = 0000000000011100 y_add_su = 0000000000011100 y_add_ss = 0000000000011100 +z_add_uu = 0000000000011100 z_add_us = 0000000000011100 z_add_su = 0000000000011100 z_add_ss = 0000000000011100 +y_sub_uu = 1111111111101100 y_sub_us = 1111111111101100 y_sub_su = 1111111111101100 y_sub_ss = 1111111111101100 +z_sub_uu = 1111111111101100 z_sub_us = 1111111111101100 z_sub_su = 1111111111101100 z_sub_ss = 1111111111101100 +y_mul_uu = 0000000001100000 y_mul_us = 0000000001100000 y_mul_su = 0000000001100000 y_mul_ss = 0000000001100000 +z_mul_uu = 0000000001100000 z_mul_us = 0000000001100000 z_mul_su = 0000000001100000 z_mul_ss = 0000000001100000 +y_ltn_uu = 1 y_ltn_us = 1 y_ltn_su = 1 y_ltn_ss = 1 +z_ltn_uu = 1 z_ltn_us = 1 z_ltn_su = 1 z_ltn_ss = 1 +y_leq_uu = 1 y_leq_us = 1 y_leq_su = 1 y_leq_ss = 1 +z_leq_uu = 1 z_leq_us = 1 z_leq_su = 1 z_leq_ss = 1 +sel = 0 +a = 10111000 +b = 00111001 +c = 100101 +y_mux_uu = 0000000000111001 y_mux_us = 0000000000111001 y_mux_su = 0000000000111001 y_mux_ss = 0000000000111001 +z_mux_uu = 0000000000111001 z_mux_us = 0000000000111001 z_mux_su = 0000000000111001 z_mux_ss = 0000000000111001 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111011010 y_sgn_s = 0000000000011010 +z_sgn_u = 1111111111011010 z_sgn_s = 0000000000011010 +y_add_uu = 0000000011011101 y_add_us = 0000000011011101 y_add_su = 0000000011011101 y_add_ss = 1111111110011101 +z_add_uu = 0000000011011101 z_add_us = 0000000011011101 z_add_su = 0000000011011101 z_add_ss = 1111111110011101 +y_sub_uu = 0000000010010011 y_sub_us = 0000000010010011 y_sub_su = 0000000010010011 y_sub_ss = 1111111111010011 +z_sub_uu = 0000000010010011 z_sub_us = 0000000010010011 z_sub_su = 0000000010010011 z_sub_ss = 1111111111010011 +y_mul_uu = 0001101010011000 y_mul_us = 0001101010011000 y_mul_su = 0001101010011000 y_mul_ss = 0000011110011000 +z_mul_uu = 0001101010011000 z_mul_us = 0001101010011000 z_mul_su = 0001101010011000 z_mul_ss = 0000011110011000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 00101011 +b = 10000001 +c = 001000 +y_mux_uu = 0000000000101011 y_mux_us = 0000000000101011 y_mux_su = 0000000000101011 y_mux_ss = 0000000000101011 +z_mux_uu = 0000000000101011 z_mux_us = 0000000000101011 z_mux_su = 0000000000101011 z_mux_ss = 0000000000101011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110111 y_sgn_s = 1111111111110111 +z_sgn_u = 1111111111110111 z_sgn_s = 1111111111110111 +y_add_uu = 0000000000110011 y_add_us = 0000000000110011 y_add_su = 0000000000110011 y_add_ss = 0000000000110011 +z_add_uu = 0000000000110011 z_add_us = 0000000000110011 z_add_su = 0000000000110011 z_add_ss = 0000000000110011 +y_sub_uu = 0000000000100011 y_sub_us = 0000000000100011 y_sub_su = 0000000000100011 y_sub_ss = 0000000000100011 +z_sub_uu = 0000000000100011 z_sub_us = 0000000000100011 z_sub_su = 0000000000100011 z_sub_ss = 0000000000100011 +y_mul_uu = 0000000101011000 y_mul_us = 0000000101011000 y_mul_su = 0000000101011000 y_mul_ss = 0000000101011000 +z_mul_uu = 0000000101011000 z_mul_us = 0000000101011000 z_mul_su = 0000000101011000 z_mul_ss = 0000000101011000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 1 +a = 10100001 +b = 00011111 +c = 000100 +y_mux_uu = 0000000010100001 y_mux_us = 0000000010100001 y_mux_su = 0000000010100001 y_mux_ss = 1111111110100001 +z_mux_uu = 0000000010100001 z_mux_us = 0000000010100001 z_mux_su = 0000000010100001 z_mux_ss = 1111111110100001 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111111011 y_sgn_s = 1111111111111011 +z_sgn_u = 1111111111111011 z_sgn_s = 1111111111111011 +y_add_uu = 0000000010100101 y_add_us = 0000000010100101 y_add_su = 0000000010100101 y_add_ss = 1111111110100101 +z_add_uu = 0000000010100101 z_add_us = 0000000010100101 z_add_su = 0000000010100101 z_add_ss = 1111111110100101 +y_sub_uu = 0000000010011101 y_sub_us = 0000000010011101 y_sub_su = 0000000010011101 y_sub_ss = 1111111110011101 +z_sub_uu = 0000000010011101 z_sub_us = 0000000010011101 z_sub_su = 0000000010011101 z_sub_ss = 1111111110011101 +y_mul_uu = 0000001010000100 y_mul_us = 0000001010000100 y_mul_su = 0000001010000100 y_mul_ss = 1111111010000100 +z_mul_uu = 0000001010000100 z_mul_us = 0000001010000100 z_mul_su = 0000001010000100 z_mul_ss = 1111111010000100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 10010110 +b = 00010100 +c = 010010 +y_mux_uu = 0000000000010100 y_mux_us = 0000000000010100 y_mux_su = 0000000000010100 y_mux_ss = 0000000000010100 +z_mux_uu = 0000000000010100 z_mux_us = 0000000000010100 z_mux_su = 0000000000010100 z_mux_ss = 0000000000010100 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111101101 y_sgn_s = 1111111111101101 +z_sgn_u = 1111111111101101 z_sgn_s = 1111111111101101 +y_add_uu = 0000000010101000 y_add_us = 0000000010101000 y_add_su = 0000000010101000 y_add_ss = 1111111110101000 +z_add_uu = 0000000010101000 z_add_us = 0000000010101000 z_add_su = 0000000010101000 z_add_ss = 1111111110101000 +y_sub_uu = 0000000010000100 y_sub_us = 0000000010000100 y_sub_su = 0000000010000100 y_sub_ss = 1111111110000100 +z_sub_uu = 0000000010000100 z_sub_us = 0000000010000100 z_sub_su = 0000000010000100 z_sub_ss = 1111111110000100 +y_mul_uu = 0000101010001100 y_mul_us = 0000101010001100 y_mul_su = 0000101010001100 y_mul_ss = 1111100010001100 +z_mul_uu = 0000101010001100 z_mul_us = 0000101010001100 z_mul_su = 0000101010001100 z_mul_ss = 1111100010001100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 10110001 +b = 01010101 +c = 101101 +y_mux_uu = 0000000001010101 y_mux_us = 0000000001010101 y_mux_su = 0000000001010101 y_mux_ss = 0000000001010101 +z_mux_uu = 0000000001010101 z_mux_us = 0000000001010101 z_mux_su = 0000000001010101 z_mux_ss = 0000000001010101 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111010010 y_sgn_s = 0000000000010010 +z_sgn_u = 1111111111010010 z_sgn_s = 0000000000010010 +y_add_uu = 0000000011011110 y_add_us = 0000000011011110 y_add_su = 0000000011011110 y_add_ss = 1111111110011110 +z_add_uu = 0000000011011110 z_add_us = 0000000011011110 z_add_su = 0000000011011110 z_add_ss = 1111111110011110 +y_sub_uu = 0000000010000100 y_sub_us = 0000000010000100 y_sub_su = 0000000010000100 y_sub_ss = 1111111111000100 +z_sub_uu = 0000000010000100 z_sub_us = 0000000010000100 z_sub_su = 0000000010000100 z_sub_ss = 1111111111000100 +y_mul_uu = 0001111100011101 y_mul_us = 0001111100011101 y_mul_su = 0001111100011101 y_mul_ss = 0000010111011101 +z_mul_uu = 0001111100011101 z_mul_us = 0001111100011101 z_mul_su = 0001111100011101 z_mul_ss = 0000010111011101 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 11110101 +b = 10101101 +c = 100111 +y_mux_uu = 0000000011110101 y_mux_us = 0000000011110101 y_mux_su = 0000000011110101 y_mux_ss = 1111111111110101 +z_mux_uu = 0000000011110101 z_mux_us = 0000000011110101 z_mux_su = 0000000011110101 z_mux_ss = 1111111111110101 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111011000 y_sgn_s = 0000000000011000 +z_sgn_u = 1111111111011000 z_sgn_s = 0000000000011000 +y_add_uu = 0000000100011100 y_add_us = 0000000100011100 y_add_su = 0000000100011100 y_add_ss = 1111111111011100 +z_add_uu = 0000000100011100 z_add_us = 0000000100011100 z_add_su = 0000000100011100 z_add_ss = 1111111111011100 +y_sub_uu = 0000000011001110 y_sub_us = 0000000011001110 y_sub_su = 0000000011001110 y_sub_ss = 0000000000001110 +z_sub_uu = 0000000011001110 z_sub_us = 0000000011001110 z_sub_su = 0000000011001110 z_sub_ss = 0000000000001110 +y_mul_uu = 0010010101010011 y_mul_us = 0010010101010011 y_mul_su = 0010010101010011 y_mul_ss = 0000000100010011 +z_mul_uu = 0010010101010011 z_mul_us = 0010010101010011 z_mul_su = 0010010101010011 z_mul_ss = 0000000100010011 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 10100111 +b = 11100111 +c = 111001 +y_mux_uu = 0000000011100111 y_mux_us = 0000000011100111 y_mux_su = 0000000011100111 y_mux_ss = 1111111111100111 +z_mux_uu = 0000000011100111 z_mux_us = 0000000011100111 z_mux_su = 0000000011100111 z_mux_ss = 1111111111100111 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000110 y_sgn_s = 0000000000000110 +z_sgn_u = 1111111111000110 z_sgn_s = 0000000000000110 +y_add_uu = 0000000011100000 y_add_us = 0000000011100000 y_add_su = 0000000011100000 y_add_ss = 1111111110100000 +z_add_uu = 0000000011100000 z_add_us = 0000000011100000 z_add_su = 0000000011100000 z_add_ss = 1111111110100000 +y_sub_uu = 0000000001101110 y_sub_us = 0000000001101110 y_sub_su = 0000000001101110 y_sub_ss = 1111111110101110 +z_sub_uu = 0000000001101110 z_sub_us = 0000000001101110 z_sub_su = 0000000001101110 z_sub_ss = 1111111110101110 +y_mul_uu = 0010010100101111 y_mul_us = 0010010100101111 y_mul_su = 0010010100101111 y_mul_ss = 0000001001101111 +z_mul_uu = 0010010100101111 z_mul_us = 0010010100101111 z_mul_su = 0010010100101111 z_mul_ss = 0000001001101111 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 11011011 +b = 11001001 +c = 010001 +y_mux_uu = 0000000011011011 y_mux_us = 0000000011011011 y_mux_su = 0000000011011011 y_mux_ss = 1111111111011011 +z_mux_uu = 0000000011011011 z_mux_us = 0000000011011011 z_mux_su = 0000000011011011 z_mux_ss = 1111111111011011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111101110 y_sgn_s = 1111111111101110 +z_sgn_u = 1111111111101110 z_sgn_s = 1111111111101110 +y_add_uu = 0000000011101100 y_add_us = 0000000011101100 y_add_su = 0000000011101100 y_add_ss = 1111111111101100 +z_add_uu = 0000000011101100 z_add_us = 0000000011101100 z_add_su = 0000000011101100 z_add_ss = 1111111111101100 +y_sub_uu = 0000000011001010 y_sub_us = 0000000011001010 y_sub_su = 0000000011001010 y_sub_ss = 1111111111001010 +z_sub_uu = 0000000011001010 z_sub_us = 0000000011001010 z_sub_su = 0000000011001010 z_sub_ss = 1111111111001010 +y_mul_uu = 0000111010001011 y_mul_us = 0000111010001011 y_mul_su = 0000111010001011 y_mul_ss = 1111110110001011 +z_mul_uu = 0000111010001011 z_mul_us = 0000111010001011 z_mul_su = 0000111010001011 z_mul_ss = 1111110110001011 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 00101010 +b = 11111010 +c = 000101 +y_mux_uu = 0000000000101010 y_mux_us = 0000000000101010 y_mux_su = 0000000000101010 y_mux_ss = 0000000000101010 +z_mux_uu = 0000000000101010 z_mux_us = 0000000000101010 z_mux_su = 0000000000101010 z_mux_ss = 0000000000101010 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111111010 y_sgn_s = 1111111111111010 +z_sgn_u = 1111111111111010 z_sgn_s = 1111111111111010 +y_add_uu = 0000000000101111 y_add_us = 0000000000101111 y_add_su = 0000000000101111 y_add_ss = 0000000000101111 +z_add_uu = 0000000000101111 z_add_us = 0000000000101111 z_add_su = 0000000000101111 z_add_ss = 0000000000101111 +y_sub_uu = 0000000000100101 y_sub_us = 0000000000100101 y_sub_su = 0000000000100101 y_sub_ss = 0000000000100101 +z_sub_uu = 0000000000100101 z_sub_us = 0000000000100101 z_sub_su = 0000000000100101 z_sub_ss = 0000000000100101 +y_mul_uu = 0000000011010010 y_mul_us = 0000000011010010 y_mul_su = 0000000011010010 y_mul_ss = 0000000011010010 +z_mul_uu = 0000000011010010 z_mul_us = 0000000011010010 z_mul_su = 0000000011010010 z_mul_ss = 0000000011010010 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 1 +a = 01111100 +b = 01110010 +c = 111110 +y_mux_uu = 0000000001111100 y_mux_us = 0000000001111100 y_mux_su = 0000000001111100 y_mux_ss = 0000000001111100 +z_mux_uu = 0000000001111100 z_mux_us = 0000000001111100 z_mux_su = 0000000001111100 z_mux_ss = 0000000001111100 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000001 y_sgn_s = 0000000000000001 +z_sgn_u = 1111111111000001 z_sgn_s = 0000000000000001 +y_add_uu = 0000000010111010 y_add_us = 0000000010111010 y_add_su = 0000000010111010 y_add_ss = 0000000001111010 +z_add_uu = 0000000010111010 z_add_us = 0000000010111010 z_add_su = 0000000010111010 z_add_ss = 0000000001111010 +y_sub_uu = 0000000000111110 y_sub_us = 0000000000111110 y_sub_su = 0000000000111110 y_sub_ss = 0000000001111110 +z_sub_uu = 0000000000111110 z_sub_us = 0000000000111110 z_sub_su = 0000000000111110 z_sub_ss = 0000000001111110 +y_mul_uu = 0001111000001000 y_mul_us = 0001111000001000 y_mul_su = 0001111000001000 y_mul_ss = 1111111100001000 +z_mul_uu = 0001111000001000 z_mul_us = 0001111000001000 z_mul_su = 0001111000001000 z_mul_ss = 1111111100001000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 01101111 +b = 10000110 +c = 110000 +y_mux_uu = 0000000010000110 y_mux_us = 0000000010000110 y_mux_su = 0000000010000110 y_mux_ss = 1111111110000110 +z_mux_uu = 0000000010000110 z_mux_us = 0000000010000110 z_mux_su = 0000000010000110 z_mux_ss = 1111111110000110 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111001111 y_sgn_s = 0000000000001111 +z_sgn_u = 1111111111001111 z_sgn_s = 0000000000001111 +y_add_uu = 0000000010011111 y_add_us = 0000000010011111 y_add_su = 0000000010011111 y_add_ss = 0000000001011111 +z_add_uu = 0000000010011111 z_add_us = 0000000010011111 z_add_su = 0000000010011111 z_add_ss = 0000000001011111 +y_sub_uu = 0000000000111111 y_sub_us = 0000000000111111 y_sub_su = 0000000000111111 y_sub_ss = 0000000001111111 +z_sub_uu = 0000000000111111 z_sub_us = 0000000000111111 z_sub_su = 0000000000111111 z_sub_ss = 0000000001111111 +y_mul_uu = 0001010011010000 y_mul_us = 0001010011010000 y_mul_su = 0001010011010000 y_mul_ss = 1111100100010000 +z_mul_uu = 0001010011010000 z_mul_us = 0001010011010000 z_mul_su = 0001010011010000 z_mul_ss = 1111100100010000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 01000000 +b = 00101000 +c = 110110 +y_mux_uu = 0000000000101000 y_mux_us = 0000000000101000 y_mux_su = 0000000000101000 y_mux_ss = 0000000000101000 +z_mux_uu = 0000000000101000 z_mux_us = 0000000000101000 z_mux_su = 0000000000101000 z_mux_ss = 0000000000101000 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111001001 y_sgn_s = 0000000000001001 +z_sgn_u = 1111111111001001 z_sgn_s = 0000000000001001 +y_add_uu = 0000000001110110 y_add_us = 0000000001110110 y_add_su = 0000000001110110 y_add_ss = 0000000000110110 +z_add_uu = 0000000001110110 z_add_us = 0000000001110110 z_add_su = 0000000001110110 z_add_ss = 0000000000110110 +y_sub_uu = 0000000000001010 y_sub_us = 0000000000001010 y_sub_su = 0000000000001010 y_sub_ss = 0000000001001010 +z_sub_uu = 0000000000001010 z_sub_us = 0000000000001010 z_sub_su = 0000000000001010 z_sub_ss = 0000000001001010 +y_mul_uu = 0000110110000000 y_mul_us = 0000110110000000 y_mul_su = 0000110110000000 y_mul_ss = 1111110110000000 +z_mul_uu = 0000110110000000 z_mul_us = 0000110110000000 z_mul_su = 0000110110000000 z_mul_ss = 1111110110000000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 1 +a = 11000000 +b = 01110100 +c = 111001 +y_mux_uu = 0000000011000000 y_mux_us = 0000000011000000 y_mux_su = 0000000011000000 y_mux_ss = 1111111111000000 +z_mux_uu = 0000000011000000 z_mux_us = 0000000011000000 z_mux_su = 0000000011000000 z_mux_ss = 1111111111000000 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000110 y_sgn_s = 0000000000000110 +z_sgn_u = 1111111111000110 z_sgn_s = 0000000000000110 +y_add_uu = 0000000011111001 y_add_us = 0000000011111001 y_add_su = 0000000011111001 y_add_ss = 1111111110111001 +z_add_uu = 0000000011111001 z_add_us = 0000000011111001 z_add_su = 0000000011111001 z_add_ss = 1111111110111001 +y_sub_uu = 0000000010000111 y_sub_us = 0000000010000111 y_sub_su = 0000000010000111 y_sub_ss = 1111111111000111 +z_sub_uu = 0000000010000111 z_sub_us = 0000000010000111 z_sub_su = 0000000010000111 z_sub_ss = 1111111111000111 +y_mul_uu = 0010101011000000 y_mul_us = 0010101011000000 y_mul_su = 0010101011000000 y_mul_ss = 0000000111000000 +z_mul_uu = 0010101011000000 z_mul_us = 0010101011000000 z_mul_su = 0010101011000000 z_mul_ss = 0000000111000000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 00111100 +b = 00101010 +c = 100010 +y_mux_uu = 0000000000101010 y_mux_us = 0000000000101010 y_mux_su = 0000000000101010 y_mux_ss = 0000000000101010 +z_mux_uu = 0000000000101010 z_mux_us = 0000000000101010 z_mux_su = 0000000000101010 z_mux_ss = 0000000000101010 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111011101 y_sgn_s = 0000000000011101 +z_sgn_u = 1111111111011101 z_sgn_s = 0000000000011101 +y_add_uu = 0000000001011110 y_add_us = 0000000001011110 y_add_su = 0000000001011110 y_add_ss = 0000000000011110 +z_add_uu = 0000000001011110 z_add_us = 0000000001011110 z_add_su = 0000000001011110 z_add_ss = 0000000000011110 +y_sub_uu = 0000000000011010 y_sub_us = 0000000000011010 y_sub_su = 0000000000011010 y_sub_ss = 0000000001011010 +z_sub_uu = 0000000000011010 z_sub_us = 0000000000011010 z_sub_su = 0000000000011010 z_sub_ss = 0000000001011010 +y_mul_uu = 0000011111111000 y_mul_us = 0000011111111000 y_mul_su = 0000011111111000 y_mul_ss = 1111100011111000 +z_mul_uu = 0000011111111000 z_mul_us = 0000011111111000 z_mul_su = 0000011111111000 z_mul_ss = 1111100011111000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 1 +a = 11100001 +b = 00010111 +c = 000011 +y_mux_uu = 0000000011100001 y_mux_us = 0000000011100001 y_mux_su = 0000000011100001 y_mux_ss = 1111111111100001 +z_mux_uu = 0000000011100001 z_mux_us = 0000000011100001 z_mux_su = 0000000011100001 z_mux_ss = 1111111111100001 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111111100 y_sgn_s = 1111111111111100 +z_sgn_u = 1111111111111100 z_sgn_s = 1111111111111100 +y_add_uu = 0000000011100100 y_add_us = 0000000011100100 y_add_su = 0000000011100100 y_add_ss = 1111111111100100 +z_add_uu = 0000000011100100 z_add_us = 0000000011100100 z_add_su = 0000000011100100 z_add_ss = 1111111111100100 +y_sub_uu = 0000000011011110 y_sub_us = 0000000011011110 y_sub_su = 0000000011011110 y_sub_ss = 1111111111011110 +z_sub_uu = 0000000011011110 z_sub_us = 0000000011011110 z_sub_su = 0000000011011110 z_sub_ss = 1111111111011110 +y_mul_uu = 0000001010100011 y_mul_us = 0000001010100011 y_mul_su = 0000001010100011 y_mul_ss = 1111111110100011 +z_mul_uu = 0000001010100011 z_mul_us = 0000001010100011 z_mul_su = 0000001010100011 z_mul_ss = 1111111110100011 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 10000110 +b = 00100101 +c = 000001 +y_mux_uu = 0000000010000110 y_mux_us = 0000000010000110 y_mux_su = 0000000010000110 y_mux_ss = 1111111110000110 +z_mux_uu = 0000000010000110 z_mux_us = 0000000010000110 z_mux_su = 0000000010000110 z_mux_ss = 1111111110000110 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111111110 y_sgn_s = 1111111111111110 +z_sgn_u = 1111111111111110 z_sgn_s = 1111111111111110 +y_add_uu = 0000000010000111 y_add_us = 0000000010000111 y_add_su = 0000000010000111 y_add_ss = 1111111110000111 +z_add_uu = 0000000010000111 z_add_us = 0000000010000111 z_add_su = 0000000010000111 z_add_ss = 1111111110000111 +y_sub_uu = 0000000010000101 y_sub_us = 0000000010000101 y_sub_su = 0000000010000101 y_sub_ss = 1111111110000101 +z_sub_uu = 0000000010000101 z_sub_us = 0000000010000101 z_sub_su = 0000000010000101 z_sub_ss = 1111111110000101 +y_mul_uu = 0000000010000110 y_mul_us = 0000000010000110 y_mul_su = 0000000010000110 y_mul_ss = 1111111110000110 +z_mul_uu = 0000000010000110 z_mul_us = 0000000010000110 z_mul_su = 0000000010000110 z_mul_ss = 1111111110000110 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 01011010 +b = 00000111 +c = 101100 +y_mux_uu = 0000000001011010 y_mux_us = 0000000001011010 y_mux_su = 0000000001011010 y_mux_ss = 0000000001011010 +z_mux_uu = 0000000001011010 z_mux_us = 0000000001011010 z_mux_su = 0000000001011010 z_mux_ss = 0000000001011010 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111010011 y_sgn_s = 0000000000010011 +z_sgn_u = 1111111111010011 z_sgn_s = 0000000000010011 +y_add_uu = 0000000010000110 y_add_us = 0000000010000110 y_add_su = 0000000010000110 y_add_ss = 0000000001000110 +z_add_uu = 0000000010000110 z_add_us = 0000000010000110 z_add_su = 0000000010000110 z_add_ss = 0000000001000110 +y_sub_uu = 0000000000101110 y_sub_us = 0000000000101110 y_sub_su = 0000000000101110 y_sub_ss = 0000000001101110 +z_sub_uu = 0000000000101110 z_sub_us = 0000000000101110 z_sub_su = 0000000000101110 z_sub_ss = 0000000001101110 +y_mul_uu = 0000111101111000 y_mul_us = 0000111101111000 y_mul_su = 0000111101111000 y_mul_ss = 1111100011111000 +z_mul_uu = 0000111101111000 z_mul_us = 0000111101111000 z_mul_su = 0000111101111000 z_mul_ss = 1111100011111000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 01110001 +b = 00111011 +c = 110110 +y_mux_uu = 0000000000111011 y_mux_us = 0000000000111011 y_mux_su = 0000000000111011 y_mux_ss = 0000000000111011 +z_mux_uu = 0000000000111011 z_mux_us = 0000000000111011 z_mux_su = 0000000000111011 z_mux_ss = 0000000000111011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111001001 y_sgn_s = 0000000000001001 +z_sgn_u = 1111111111001001 z_sgn_s = 0000000000001001 +y_add_uu = 0000000010100111 y_add_us = 0000000010100111 y_add_su = 0000000010100111 y_add_ss = 0000000001100111 +z_add_uu = 0000000010100111 z_add_us = 0000000010100111 z_add_su = 0000000010100111 z_add_ss = 0000000001100111 +y_sub_uu = 0000000000111011 y_sub_us = 0000000000111011 y_sub_su = 0000000000111011 y_sub_ss = 0000000001111011 +z_sub_uu = 0000000000111011 z_sub_us = 0000000000111011 z_sub_su = 0000000000111011 z_sub_ss = 0000000001111011 +y_mul_uu = 0001011111010110 y_mul_us = 0001011111010110 y_mul_su = 0001011111010110 y_mul_ss = 1111101110010110 +z_mul_uu = 0001011111010110 z_mul_us = 0001011111010110 z_mul_su = 0001011111010110 z_mul_ss = 1111101110010110 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 1 +a = 10011110 +b = 01011100 +c = 010101 +y_mux_uu = 0000000010011110 y_mux_us = 0000000010011110 y_mux_su = 0000000010011110 y_mux_ss = 1111111110011110 +z_mux_uu = 0000000010011110 z_mux_us = 0000000010011110 z_mux_su = 0000000010011110 z_mux_ss = 1111111110011110 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111101010 y_sgn_s = 1111111111101010 +z_sgn_u = 1111111111101010 z_sgn_s = 1111111111101010 +y_add_uu = 0000000010110011 y_add_us = 0000000010110011 y_add_su = 0000000010110011 y_add_ss = 1111111110110011 +z_add_uu = 0000000010110011 z_add_us = 0000000010110011 z_add_su = 0000000010110011 z_add_ss = 1111111110110011 +y_sub_uu = 0000000010001001 y_sub_us = 0000000010001001 y_sub_su = 0000000010001001 y_sub_ss = 1111111110001001 +z_sub_uu = 0000000010001001 z_sub_us = 0000000010001001 z_sub_su = 0000000010001001 z_sub_ss = 1111111110001001 +y_mul_uu = 0000110011110110 y_mul_us = 0000110011110110 y_mul_su = 0000110011110110 y_mul_ss = 1111011111110110 +z_mul_uu = 0000110011110110 z_mul_us = 0000110011110110 z_mul_su = 0000110011110110 z_mul_ss = 1111011111110110 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 10100000 +b = 01110010 +c = 110100 +y_mux_uu = 0000000001110010 y_mux_us = 0000000001110010 y_mux_su = 0000000001110010 y_mux_ss = 0000000001110010 +z_mux_uu = 0000000001110010 z_mux_us = 0000000001110010 z_mux_su = 0000000001110010 z_mux_ss = 0000000001110010 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111001011 y_sgn_s = 0000000000001011 +z_sgn_u = 1111111111001011 z_sgn_s = 0000000000001011 +y_add_uu = 0000000011010100 y_add_us = 0000000011010100 y_add_su = 0000000011010100 y_add_ss = 1111111110010100 +z_add_uu = 0000000011010100 z_add_us = 0000000011010100 z_add_su = 0000000011010100 z_add_ss = 1111111110010100 +y_sub_uu = 0000000001101100 y_sub_us = 0000000001101100 y_sub_su = 0000000001101100 y_sub_ss = 1111111110101100 +z_sub_uu = 0000000001101100 z_sub_us = 0000000001101100 z_sub_su = 0000000001101100 z_sub_ss = 1111111110101100 +y_mul_uu = 0010000010000000 y_mul_us = 0010000010000000 y_mul_su = 0010000010000000 y_mul_ss = 0000010010000000 +z_mul_uu = 0010000010000000 z_mul_us = 0010000010000000 z_mul_su = 0010000010000000 z_mul_ss = 0000010010000000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 00001101 +b = 01001011 +c = 111001 +y_mux_uu = 0000000000001101 y_mux_us = 0000000000001101 y_mux_su = 0000000000001101 y_mux_ss = 0000000000001101 +z_mux_uu = 0000000000001101 z_mux_us = 0000000000001101 z_mux_su = 0000000000001101 z_mux_ss = 0000000000001101 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111000110 y_sgn_s = 0000000000000110 +z_sgn_u = 1111111111000110 z_sgn_s = 0000000000000110 +y_add_uu = 0000000001000110 y_add_us = 0000000001000110 y_add_su = 0000000001000110 y_add_ss = 0000000000000110 +z_add_uu = 0000000001000110 z_add_us = 0000000001000110 z_add_su = 0000000001000110 z_add_ss = 0000000000000110 +y_sub_uu = 1111111111010100 y_sub_us = 1111111111010100 y_sub_su = 1111111111010100 y_sub_ss = 0000000000010100 +z_sub_uu = 1111111111010100 z_sub_us = 1111111111010100 z_sub_su = 1111111111010100 z_sub_ss = 0000000000010100 +y_mul_uu = 0000001011100101 y_mul_us = 0000001011100101 y_mul_su = 0000001011100101 y_mul_ss = 1111111110100101 +z_mul_uu = 0000001011100101 z_mul_us = 0000001011100101 z_mul_su = 0000001011100101 z_mul_ss = 1111111110100101 +y_ltn_uu = 1 y_ltn_us = 1 y_ltn_su = 1 y_ltn_ss = 0 +z_ltn_uu = 1 z_ltn_us = 1 z_ltn_su = 1 z_ltn_ss = 0 +y_leq_uu = 1 y_leq_us = 1 y_leq_su = 1 y_leq_ss = 0 +z_leq_uu = 1 z_leq_us = 1 z_leq_su = 1 z_leq_ss = 0 +sel = 0 +a = 11111101 +b = 01111011 +c = 001111 +y_mux_uu = 0000000001111011 y_mux_us = 0000000001111011 y_mux_su = 0000000001111011 y_mux_ss = 0000000001111011 +z_mux_uu = 0000000001111011 z_mux_us = 0000000001111011 z_mux_su = 0000000001111011 z_mux_ss = 0000000001111011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110000 y_sgn_s = 1111111111110000 +z_sgn_u = 1111111111110000 z_sgn_s = 1111111111110000 +y_add_uu = 0000000100001100 y_add_us = 0000000100001100 y_add_su = 0000000100001100 y_add_ss = 0000000000001100 +z_add_uu = 0000000100001100 z_add_us = 0000000100001100 z_add_su = 0000000100001100 z_add_ss = 0000000000001100 +y_sub_uu = 0000000011101110 y_sub_us = 0000000011101110 y_sub_su = 0000000011101110 y_sub_ss = 1111111111101110 +z_sub_uu = 0000000011101110 z_sub_us = 0000000011101110 z_sub_su = 0000000011101110 z_sub_ss = 1111111111101110 +y_mul_uu = 0000111011010011 y_mul_us = 0000111011010011 y_mul_su = 0000111011010011 y_mul_ss = 1111111111010011 +z_mul_uu = 0000111011010011 z_mul_us = 0000111011010011 z_mul_su = 0000111011010011 z_mul_ss = 1111111111010011 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 1 +a = 11100011 +b = 00011101 +c = 110001 +y_mux_uu = 0000000011100011 y_mux_us = 0000000011100011 y_mux_su = 0000000011100011 y_mux_ss = 1111111111100011 +z_mux_uu = 0000000011100011 z_mux_us = 0000000011100011 z_mux_su = 0000000011100011 z_mux_ss = 1111111111100011 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111001110 y_sgn_s = 0000000000001110 +z_sgn_u = 1111111111001110 z_sgn_s = 0000000000001110 +y_add_uu = 0000000100010100 y_add_us = 0000000100010100 y_add_su = 0000000100010100 y_add_ss = 1111111111010100 +z_add_uu = 0000000100010100 z_add_us = 0000000100010100 z_add_su = 0000000100010100 z_add_ss = 1111111111010100 +y_sub_uu = 0000000010110010 y_sub_us = 0000000010110010 y_sub_su = 0000000010110010 y_sub_ss = 1111111111110010 +z_sub_uu = 0000000010110010 z_sub_us = 0000000010110010 z_sub_su = 0000000010110010 z_sub_ss = 1111111111110010 +y_mul_uu = 0010101101110011 y_mul_us = 0010101101110011 y_mul_su = 0010101101110011 y_mul_ss = 0000000110110011 +z_mul_uu = 0010101101110011 z_mul_us = 0010101101110011 z_mul_su = 0010101101110011 z_mul_ss = 0000000110110011 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 10010101 +b = 11100000 +c = 101101 +y_mux_uu = 0000000011100000 y_mux_us = 0000000011100000 y_mux_su = 0000000011100000 y_mux_ss = 1111111111100000 +z_mux_uu = 0000000011100000 z_mux_us = 0000000011100000 z_mux_su = 0000000011100000 z_mux_ss = 1111111111100000 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111010010 y_sgn_s = 0000000000010010 +z_sgn_u = 1111111111010010 z_sgn_s = 0000000000010010 +y_add_uu = 0000000011000010 y_add_us = 0000000011000010 y_add_su = 0000000011000010 y_add_ss = 1111111110000010 +z_add_uu = 0000000011000010 z_add_us = 0000000011000010 z_add_su = 0000000011000010 z_add_ss = 1111111110000010 +y_sub_uu = 0000000001101000 y_sub_us = 0000000001101000 y_sub_su = 0000000001101000 y_sub_ss = 1111111110101000 +z_sub_uu = 0000000001101000 z_sub_us = 0000000001101000 z_sub_su = 0000000001101000 z_sub_ss = 1111111110101000 +y_mul_uu = 0001101000110001 y_mul_us = 0001101000110001 y_mul_su = 0001101000110001 y_mul_ss = 0000011111110001 +z_mul_uu = 0001101000110001 z_mul_us = 0001101000110001 z_mul_su = 0001101000110001 z_mul_ss = 0000011111110001 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 11111000 +b = 10001101 +c = 010010 +y_mux_uu = 0000000010001101 y_mux_us = 0000000010001101 y_mux_su = 0000000010001101 y_mux_ss = 1111111110001101 +z_mux_uu = 0000000010001101 z_mux_us = 0000000010001101 z_mux_su = 0000000010001101 z_mux_ss = 1111111110001101 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111101101 y_sgn_s = 1111111111101101 +z_sgn_u = 1111111111101101 z_sgn_s = 1111111111101101 +y_add_uu = 0000000100001010 y_add_us = 0000000100001010 y_add_su = 0000000100001010 y_add_ss = 0000000000001010 +z_add_uu = 0000000100001010 z_add_us = 0000000100001010 z_add_su = 0000000100001010 z_add_ss = 0000000000001010 +y_sub_uu = 0000000011100110 y_sub_us = 0000000011100110 y_sub_su = 0000000011100110 y_sub_ss = 1111111111100110 +z_sub_uu = 0000000011100110 z_sub_us = 0000000011100110 z_sub_su = 0000000011100110 z_sub_ss = 1111111111100110 +y_mul_uu = 0001000101110000 y_mul_us = 0001000101110000 y_mul_su = 0001000101110000 y_mul_ss = 1111111101110000 +z_mul_uu = 0001000101110000 z_mul_us = 0001000101110000 z_mul_su = 0001000101110000 z_mul_ss = 1111111101110000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 1 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 1 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 1 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 1 +sel = 0 +a = 01000110 +b = 10001100 +c = 010000 +y_mux_uu = 0000000010001100 y_mux_us = 0000000010001100 y_mux_su = 0000000010001100 y_mux_ss = 1111111110001100 +z_mux_uu = 0000000010001100 z_mux_us = 0000000010001100 z_mux_su = 0000000010001100 z_mux_ss = 1111111110001100 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111101111 y_sgn_s = 1111111111101111 +z_sgn_u = 1111111111101111 z_sgn_s = 1111111111101111 +y_add_uu = 0000000001010110 y_add_us = 0000000001010110 y_add_su = 0000000001010110 y_add_ss = 0000000001010110 +z_add_uu = 0000000001010110 z_add_us = 0000000001010110 z_add_su = 0000000001010110 z_add_ss = 0000000001010110 +y_sub_uu = 0000000000110110 y_sub_us = 0000000000110110 y_sub_su = 0000000000110110 y_sub_ss = 0000000000110110 +z_sub_uu = 0000000000110110 z_sub_us = 0000000000110110 z_sub_su = 0000000000110110 z_sub_ss = 0000000000110110 +y_mul_uu = 0000010001100000 y_mul_us = 0000010001100000 y_mul_su = 0000010001100000 y_mul_ss = 0000010001100000 +z_mul_uu = 0000010001100000 z_mul_us = 0000010001100000 z_mul_su = 0000010001100000 z_mul_ss = 0000010001100000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 1 +a = 01101010 +b = 10000100 +c = 101010 +y_mux_uu = 0000000001101010 y_mux_us = 0000000001101010 y_mux_su = 0000000001101010 y_mux_ss = 0000000001101010 +z_mux_uu = 0000000001101010 z_mux_us = 0000000001101010 z_mux_su = 0000000001101010 z_mux_ss = 0000000001101010 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111010101 y_sgn_s = 0000000000010101 +z_sgn_u = 1111111111010101 z_sgn_s = 0000000000010101 +y_add_uu = 0000000010010100 y_add_us = 0000000010010100 y_add_su = 0000000010010100 y_add_ss = 0000000001010100 +z_add_uu = 0000000010010100 z_add_us = 0000000010010100 z_add_su = 0000000010010100 z_add_ss = 0000000001010100 +y_sub_uu = 0000000001000000 y_sub_us = 0000000001000000 y_sub_su = 0000000001000000 y_sub_ss = 0000000010000000 +z_sub_uu = 0000000001000000 z_sub_us = 0000000001000000 z_sub_su = 0000000001000000 z_sub_ss = 0000000010000000 +y_mul_uu = 0001000101100100 y_mul_us = 0001000101100100 y_mul_su = 0001000101100100 y_mul_ss = 1111011011100100 +z_mul_uu = 0001000101100100 z_mul_us = 0001000101100100 z_mul_su = 0001000101100100 z_mul_ss = 1111011011100100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 01100000 +b = 10111010 +c = 001011 +y_mux_uu = 0000000010111010 y_mux_us = 0000000010111010 y_mux_su = 0000000010111010 y_mux_ss = 1111111110111010 +z_mux_uu = 0000000010111010 z_mux_us = 0000000010111010 z_mux_su = 0000000010111010 z_mux_ss = 1111111110111010 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110100 y_sgn_s = 1111111111110100 +z_sgn_u = 1111111111110100 z_sgn_s = 1111111111110100 +y_add_uu = 0000000001101011 y_add_us = 0000000001101011 y_add_su = 0000000001101011 y_add_ss = 0000000001101011 +z_add_uu = 0000000001101011 z_add_us = 0000000001101011 z_add_su = 0000000001101011 z_add_ss = 0000000001101011 +y_sub_uu = 0000000001010101 y_sub_us = 0000000001010101 y_sub_su = 0000000001010101 y_sub_ss = 0000000001010101 +z_sub_uu = 0000000001010101 z_sub_us = 0000000001010101 z_sub_su = 0000000001010101 z_sub_ss = 0000000001010101 +y_mul_uu = 0000010000100000 y_mul_us = 0000010000100000 y_mul_su = 0000010000100000 y_mul_ss = 0000010000100000 +z_mul_uu = 0000010000100000 z_mul_us = 0000010000100000 z_mul_su = 0000010000100000 z_mul_ss = 0000010000100000 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 0 +a = 00100101 +b = 00110010 +c = 100010 +y_mux_uu = 0000000000110010 y_mux_us = 0000000000110010 y_mux_su = 0000000000110010 y_mux_ss = 0000000000110010 +z_mux_uu = 0000000000110010 z_mux_us = 0000000000110010 z_mux_su = 0000000000110010 z_mux_ss = 0000000000110010 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111011101 y_sgn_s = 0000000000011101 +z_sgn_u = 1111111111011101 z_sgn_s = 0000000000011101 +y_add_uu = 0000000001000111 y_add_us = 0000000001000111 y_add_su = 0000000001000111 y_add_ss = 0000000000000111 +z_add_uu = 0000000001000111 z_add_us = 0000000001000111 z_add_su = 0000000001000111 z_add_ss = 0000000000000111 +y_sub_uu = 0000000000000011 y_sub_us = 0000000000000011 y_sub_su = 0000000000000011 y_sub_ss = 0000000001000011 +z_sub_uu = 0000000000000011 z_sub_us = 0000000000000011 z_sub_su = 0000000000000011 z_sub_ss = 0000000001000011 +y_mul_uu = 0000010011101010 y_mul_us = 0000010011101010 y_mul_su = 0000010011101010 y_mul_ss = 1111101110101010 +z_mul_uu = 0000010011101010 z_mul_us = 0000010011101010 z_mul_su = 0000010011101010 z_mul_ss = 1111101110101010 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 +sel = 1 +a = 00010100 +b = 00111101 +c = 001011 +y_mux_uu = 0000000000010100 y_mux_us = 0000000000010100 y_mux_su = 0000000000010100 y_mux_ss = 0000000000010100 +z_mux_uu = 0000000000010100 z_mux_us = 0000000000010100 z_mux_su = 0000000000010100 z_mux_ss = 0000000000010100 +y_eql_uu = 0 y_eql_us = 0 y_eql_su = 0 y_eql_ss = 0 +z_eql_uu = 0 z_eql_us = 0 z_eql_su = 0 z_eql_ss = 0 +y_neq_uu = 1 y_neq_us = 1 y_neq_su = 1 y_neq_ss = 1 +z_neq_uu = 1 z_neq_us = 1 z_neq_su = 1 z_neq_ss = 1 +y_sgn_u = 1111111111110100 y_sgn_s = 1111111111110100 +z_sgn_u = 1111111111110100 z_sgn_s = 1111111111110100 +y_add_uu = 0000000000011111 y_add_us = 0000000000011111 y_add_su = 0000000000011111 y_add_ss = 0000000000011111 +z_add_uu = 0000000000011111 z_add_us = 0000000000011111 z_add_su = 0000000000011111 z_add_ss = 0000000000011111 +y_sub_uu = 0000000000001001 y_sub_us = 0000000000001001 y_sub_su = 0000000000001001 y_sub_ss = 0000000000001001 +z_sub_uu = 0000000000001001 z_sub_us = 0000000000001001 z_sub_su = 0000000000001001 z_sub_ss = 0000000000001001 +y_mul_uu = 0000000011011100 y_mul_us = 0000000011011100 y_mul_su = 0000000011011100 y_mul_ss = 0000000011011100 +z_mul_uu = 0000000011011100 z_mul_us = 0000000011011100 z_mul_su = 0000000011011100 z_mul_ss = 0000000011011100 +y_ltn_uu = 0 y_ltn_us = 0 y_ltn_su = 0 y_ltn_ss = 0 +z_ltn_uu = 0 z_ltn_us = 0 z_ltn_su = 0 z_ltn_ss = 0 +y_leq_uu = 0 y_leq_us = 0 y_leq_su = 0 y_leq_ss = 0 +z_leq_uu = 0 z_leq_us = 0 z_leq_su = 0 z_leq_ss = 0 diff --git a/ivtest/gold/pr2146620.gold b/ivtest/gold/pr2146620.gold new file mode 100644 index 000000000..1c8373fec --- /dev/null +++ b/ivtest/gold/pr2146620.gold @@ -0,0 +1,4 @@ + 0 +128 + 0 +128 diff --git a/ivtest/gold/pr2146620b.gold b/ivtest/gold/pr2146620b.gold new file mode 100644 index 000000000..4a9dac24b --- /dev/null +++ b/ivtest/gold/pr2146620b.gold @@ -0,0 +1,6 @@ +5 +4 +3 +2 +1 +0 diff --git a/ivtest/gold/pr2146824.gold b/ivtest/gold/pr2146824.gold new file mode 100644 index 000000000..ee6a30817 --- /dev/null +++ b/ivtest/gold/pr2146824.gold @@ -0,0 +1 @@ +'hfe diff --git a/ivtest/gold/pr2152011.gold b/ivtest/gold/pr2152011.gold new file mode 100644 index 000000000..a2a1af763 --- /dev/null +++ b/ivtest/gold/pr2152011.gold @@ -0,0 +1,20 @@ + 0 + 144857 + 199758 + 130608 + -19650 +-157705 +-197825 +-115095 + 39109 + 169027 + 193978 + 98468 + -58190 +-178713 +-188254 + -80889 + 76709 + 186670 + 180708 + 62527 diff --git a/ivtest/gold/pr2159630.gold b/ivtest/gold/pr2159630.gold new file mode 100644 index 000000000..bd8247c79 --- /dev/null +++ b/ivtest/gold/pr2159630.gold @@ -0,0 +1 @@ +Var -4 vs signed(concat) -4 diff --git a/ivtest/gold/pr2169870.gold b/ivtest/gold/pr2169870.gold new file mode 100644 index 000000000..eda4c04d6 --- /dev/null +++ b/ivtest/gold/pr2169870.gold @@ -0,0 +1,20 @@ +0 +0 +1 +1 +2 +2 +3 +3 +4 +4 +5 +5 +6 +6 +7 +7 +8 +8 +9 +9 diff --git a/ivtest/gold/pr2248925.gold b/ivtest/gold/pr2248925.gold new file mode 100644 index 000000000..3d86ec649 --- /dev/null +++ b/ivtest/gold/pr2248925.gold @@ -0,0 +1 @@ +1500 diff --git a/ivtest/gold/pr2251119.gold b/ivtest/gold/pr2251119.gold new file mode 100644 index 000000000..511d42f3c --- /dev/null +++ b/ivtest/gold/pr2251119.gold @@ -0,0 +1 @@ +PASSED: 1100 < 1000 false branch taken diff --git a/ivtest/gold/pr2251119_std.gold b/ivtest/gold/pr2251119_std.gold new file mode 100644 index 000000000..82a2900d2 --- /dev/null +++ b/ivtest/gold/pr2251119_std.gold @@ -0,0 +1 @@ +PASSED: 1100 < 1000 false branch taken diff --git a/ivtest/gold/pr2272468.gold b/ivtest/gold/pr2272468.gold new file mode 100644 index 000000000..8551d860e --- /dev/null +++ b/ivtest/gold/pr2272468.gold @@ -0,0 +1,256 @@ + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 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5060ns:1fa + 5070ns:1fb + 5080ns:1fc + 5090ns:1fd + 5100ns:1fe + 5110ns:1ff + 5120ns:200 diff --git a/ivtest/gold/pr2486350.gold b/ivtest/gold/pr2486350.gold new file mode 100644 index 000000000..150ea84f5 --- /dev/null +++ b/ivtest/gold/pr2486350.gold @@ -0,0 +1 @@ +simtime= 10000000000000000 (2386f26fc10000) diff --git a/ivtest/gold/pr2509349a-msys2.gold b/ivtest/gold/pr2509349a-msys2.gold new file mode 100755 index 000000000..8fd001964 --- /dev/null +++ b/ivtest/gold/pr2509349a-msys2.gold @@ -0,0 +1,5 @@ +WARNING: ./ivltests/pr2509349a.v:10: $readmempath could not find directory "/tmp"! +WARNING: ./ivltests/pr2509349a.v:10: $readmempath could not find directory "/no_dir"! +WARNING: ./ivltests/pr2509349a.v:10: $readmempath could not find directory "no_dir2"! +WARNING: ./ivltests/pr2509349a.v:10: $readmempath's path element "vsim" is not a directory! +PASSED diff --git a/ivtest/gold/pr2509349a-vlog95.gold b/ivtest/gold/pr2509349a-vlog95.gold new file mode 100644 index 000000000..a35abdbd0 --- /dev/null +++ b/ivtest/gold/pr2509349a-vlog95.gold @@ -0,0 +1,4 @@ +WARNING: vlog95.v:17: $readmempath could not find directory "/no_dir"! +WARNING: vlog95.v:17: $readmempath could not find directory "no_dir2"! +WARNING: vlog95.v:17: $readmempath's path element "vsim" is not a directory! +PASSED diff --git a/ivtest/gold/pr2509349a.gold b/ivtest/gold/pr2509349a.gold new file mode 100644 index 000000000..decc2f1a1 --- /dev/null +++ b/ivtest/gold/pr2509349a.gold @@ -0,0 +1,4 @@ +WARNING: ./ivltests/pr2509349a.v:10: $readmempath could not find directory "/no_dir"! +WARNING: ./ivltests/pr2509349a.v:10: $readmempath could not find directory "no_dir2"! +WARNING: ./ivltests/pr2509349a.v:10: $readmempath's path element "vsim" is not a directory! +PASSED diff --git a/ivtest/gold/pr2509349b-vlog95.gold b/ivtest/gold/pr2509349b-vlog95.gold new file mode 100644 index 000000000..5b8b4c063 --- /dev/null +++ b/ivtest/gold/pr2509349b-vlog95.gold @@ -0,0 +1,3 @@ +WARNING: vlog95.v:14: $readmempath's argument (vpiReg) is not a valid string. +WARNING: vlog95.v:17: $readmempath's argument contains non-printable characters. + "tes\002" diff --git a/ivtest/gold/pr2509349b.gold b/ivtest/gold/pr2509349b.gold new file mode 100644 index 000000000..bb994b320 --- /dev/null +++ b/ivtest/gold/pr2509349b.gold @@ -0,0 +1,3 @@ +WARNING: ./ivltests/pr2509349b.v:5: $readmempath's argument (vpiReg) is not a valid string. +WARNING: ./ivltests/pr2509349b.v:8: $readmempath's argument contains non-printable characters. + "tes\002" diff --git a/ivtest/gold/pr2580730.gold b/ivtest/gold/pr2580730.gold new file mode 100644 index 000000000..093632df7 --- /dev/null +++ b/ivtest/gold/pr2580730.gold @@ -0,0 +1,10 @@ +dl:ls32b- 1 ps +rl:ls32b- 2 ps +rg:ls32b- 3 ps +ar:ls32b- 4 ps +ps:ls32b- 5 ps +dl:gt32b- 1000000000000 ps +rl:gt32b- 2000000000000 ps +rg:gt32b- 3000000000000 ps +ar:gt32b- 4000000000000 ps +ps:gt32b- 5000000000000 ps diff --git a/ivtest/gold/pr2590274.gold b/ivtest/gold/pr2590274.gold new file mode 100644 index 000000000..498b75909 --- /dev/null +++ b/ivtest/gold/pr2590274.gold @@ -0,0 +1,4 @@ +warning: Found both default and `timescale based delays. Use + : -Wtimescale to find the module(s) with no `timescale. +The time in w_time is: 1.000000e-09 +The time in wo_time is: 1.000000e+00 diff --git a/ivtest/gold/pr2715558.gold b/ivtest/gold/pr2715558.gold new file mode 100644 index 000000000..0e042c765 --- /dev/null +++ b/ivtest/gold/pr2715558.gold @@ -0,0 +1,16 @@ +sup1_sup0 resulted in: x +sup1_str0 resulted in: x +sup1_pl0 resulted in: x +sup1_we0 resulted in: x +str1_sup0 resulted in: x +str1_str0 resulted in: x +str1_pl0 resulted in: x +str1_we0 resulted in: x +pl1_sup0 resulted in: x +pl1_str0 resulted in: x +pl1_pl0 resulted in: x +pl1_we0 resulted in: x +we1_sup0 resulted in: x +we1_str0 resulted in: x +we1_pl0 resulted in: x +we1_we0 resulted in: x diff --git a/ivtest/gold/pr2715558b.gold b/ivtest/gold/pr2715558b.gold new file mode 100644 index 000000000..2539efe08 --- /dev/null +++ b/ivtest/gold/pr2715558b.gold @@ -0,0 +1,16 @@ +sup1_sup0 resulted in: x +sup1_str0 resulted in: 1 +sup1_pl0 resulted in: 1 +sup1_we0 resulted in: 1 +str1_sup0 resulted in: 0 +str1_str0 resulted in: x +str1_pl0 resulted in: 1 +str1_we0 resulted in: 1 +pl1_sup0 resulted in: 0 +pl1_str0 resulted in: 0 +pl1_pl0 resulted in: x +pl1_we0 resulted in: 1 +we1_sup0 resulted in: 0 +we1_str0 resulted in: 0 +we1_pl0 resulted in: 0 +we1_we0 resulted in: x diff --git a/ivtest/gold/pr2715748.gold b/ivtest/gold/pr2715748.gold new file mode 100644 index 000000000..f12cfe01f --- /dev/null +++ b/ivtest/gold/pr2715748.gold @@ -0,0 +1,6 @@ +Real -1, Realtime 1 +Real as int -1, Realtime as int 1 +Real net 2 +Real net as int 2 +Passed %f put +Passed %d put diff --git a/ivtest/gold/pr2785294.gold b/ivtest/gold/pr2785294.gold new file mode 100644 index 000000000..4601f288f --- /dev/null +++ b/ivtest/gold/pr2785294.gold @@ -0,0 +1,5 @@ + 0 BS = 0, PS = 0, AR = 0 + 2 BS = 1, PS = 0, AR = 0 + 10 BS = 1, PS = 1, AR = 0 + 11 BS = 1, PS = 3, AR = 0 + 18 BS = 1, PS = 3, AR = 1 diff --git a/ivtest/gold/pr2794144.gold b/ivtest/gold/pr2794144.gold new file mode 100644 index 000000000..4497f3bec --- /dev/null +++ b/ivtest/gold/pr2794144.gold @@ -0,0 +1,3 @@ +./ivltests/pr2794144.v:8: error: '~' '|' is not a valid expression. Please use operator '~|' instead. +./ivltests/pr2794144.v:9: error: '~' '&' is not a valid expression. Please use operator '~&' instead. +./ivltests/pr2794144.v:10: error: '~' '^' is not a valid expression. Please use operator '~^' instead. diff --git a/ivtest/gold/pr2800985b-vlog95.gold b/ivtest/gold/pr2800985b-vlog95.gold new file mode 100644 index 000000000..4a161da36 --- /dev/null +++ b/ivtest/gold/pr2800985b-vlog95.gold @@ -0,0 +1,6 @@ +ERROR: vlog95.v:18: $ferror's fd (first) argument must be numeric. +ERROR: vlog95.v:19: $ferror requires a second (register) argument. +ERROR: vlog95.v:20: $ferror's second argument must be a reg (>=640 bits). +ERROR: vlog95.v:21: $ferror's second argument must have 640 bit or more. +ERROR: vlog95.v:22: $ferror takes two arguments. + Found 1 extra argument. diff --git a/ivtest/gold/pr2800985b.gold b/ivtest/gold/pr2800985b.gold new file mode 100644 index 000000000..9f626a7f9 --- /dev/null +++ b/ivtest/gold/pr2800985b.gold @@ -0,0 +1,6 @@ +ERROR: ./ivltests/pr2800985b.v:11: $ferror's fd (first) argument must be numeric. +ERROR: ./ivltests/pr2800985b.v:12: $ferror requires a second (register) argument. +ERROR: ./ivltests/pr2800985b.v:13: $ferror's second argument must be a reg (>=640 bits). +ERROR: ./ivltests/pr2800985b.v:14: $ferror's second argument must have 640 bit or more. +ERROR: ./ivltests/pr2800985b.v:15: $ferror takes two arguments. + Found 1 extra argument. diff --git a/ivtest/gold/pr2809288.gold b/ivtest/gold/pr2809288.gold new file mode 100644 index 000000000..b6f5131c7 --- /dev/null +++ b/ivtest/gold/pr2809288.gold @@ -0,0 +1,2 @@ +./ivltests/pr2809288.v:5: error: genvar is missing for generate "loop" variable 'i'. +1 error(s) during elaboration. diff --git a/ivtest/gold/pr2815398a.gold b/ivtest/gold/pr2815398a.gold new file mode 100644 index 000000000..0aa7d9bef --- /dev/null +++ b/ivtest/gold/pr2815398a.gold @@ -0,0 +1,2 @@ +./ivltests/pr2815398a.v:65: warning: returning 'bx for out of bounds array access dummy[7]. +PASSED diff --git a/ivtest/gold/pr2815398b.gold b/ivtest/gold/pr2815398b.gold new file mode 100644 index 000000000..0fd78465a --- /dev/null +++ b/ivtest/gold/pr2815398b.gold @@ -0,0 +1,11 @@ +./ivltests/pr2815398b.v:39: warning: ignoring out of bounds l-value array access arr[8]. +./ivltests/pr2815398b.v:39: warning: ignoring out of bounds l-value array access arr[9]. +./ivltests/pr2815398b.v:39: warning: ignoring out of bounds l-value array access arr[10]. +./ivltests/pr2815398b.v:39: warning: ignoring out of bounds l-value array access arr[11]. +./ivltests/pr2815398b.v:39: warning: ignoring out of bounds l-value array access arr[12]. +./ivltests/pr2815398b.v:39: warning: ignoring out of bounds l-value array access arr[13]. +./ivltests/pr2815398b.v:39: warning: ignoring out of bounds l-value array access arr[14]. +./ivltests/pr2815398b.v:39: warning: ignoring out of bounds l-value array access arr[15]. +./ivltests/pr2815398b.v:26: warning: ignoring out of bounds l-value array access arr[20]. +./ivltests/pr2815398b.v:27: warning: ignoring out of bounds l-value array access arr[-1]. +PASSED diff --git a/ivtest/gold/pr2823414.gold b/ivtest/gold/pr2823414.gold new file mode 100644 index 000000000..45da891c0 --- /dev/null +++ b/ivtest/gold/pr2823414.gold @@ -0,0 +1,2 @@ +./ivltests/pr2823414.v:10: error: Enable of unknown task ``fail_at_line_10''. +Elaboration failed diff --git a/ivtest/gold/pr2842621.gold b/ivtest/gold/pr2842621.gold new file mode 100644 index 000000000..e39b988c2 --- /dev/null +++ b/ivtest/gold/pr2842621.gold @@ -0,0 +1,8 @@ + 1 + 2 +The result for $fdisplay( 1, ...) is 3 +The result for $fwrite( 1, ...) is 4 +The $fstrobe( 1, ...) ran. + 3 + 4 +PASSED diff --git a/ivtest/gold/pr2848986.gold b/ivtest/gold/pr2848986.gold new file mode 100644 index 000000000..772ed4e9b --- /dev/null +++ b/ivtest/gold/pr2848986.gold @@ -0,0 +1,5 @@ +./ivltests/pr2848986.v:6: error: An event 'evt' can not be a user function argument. +./ivltests/pr2848986.v:6: internal error: Failed to synthesize expression: top.func() +./ivltests/pr2848986.v:25: error: An event 'evt' can not be a user function argument. +./ivltests/pr2848986.v:26: error: An event 'evt' can not be a user task argument. +4 error(s) during elaboration. diff --git a/ivtest/gold/pr2859628.vcd.gold b/ivtest/gold/pr2859628.vcd.gold new file mode 100644 index 000000000..36c6406bb --- /dev/null +++ b/ivtest/gold/pr2859628.vcd.gold @@ -0,0 +1,24 @@ +$date + Tue Sep 15 16:56:35 2009 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module top $end +$upscope $end +$scope module top $end +$var reg 4 ! \array[0] [3:0] $end +$upscope $end +$scope module top $end +$var reg 4 " \array[1] [3:0] $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +bx " +bx ! +$end +#1 diff --git a/ivtest/gold/pr2877564.gold b/ivtest/gold/pr2877564.gold new file mode 100644 index 000000000..da04a1cf6 --- /dev/null +++ b/ivtest/gold/pr2877564.gold @@ -0,0 +1,2 @@ +./ivltests/pr2877564.v:2: error: Unable to bind parameter `ASDF' in `testbench' +1 error(s) during elaboration. diff --git a/ivtest/gold/pr2924354.gold b/ivtest/gold/pr2924354.gold new file mode 100644 index 000000000..f85f92bff --- /dev/null +++ b/ivtest/gold/pr2924354.gold @@ -0,0 +1,4 @@ +foo=1, bar=1 +foo=1, bar=1 +foo=1, bar=1 +foo=1, bar=1 diff --git a/ivtest/gold/pr2972866.gold b/ivtest/gold/pr2972866.gold new file mode 100644 index 000000000..2d049d960 --- /dev/null +++ b/ivtest/gold/pr2972866.gold @@ -0,0 +1,7 @@ +0.000000 x 0 +0.690000 0 0 +10.000000 0 1 +10.730000 1 1 +20.000000 1 0 +20.690000 0 0 +Simulation ran correctly. diff --git a/ivtest/gold/pr2976242c.gold b/ivtest/gold/pr2976242c.gold new file mode 100644 index 000000000..45baf1d45 --- /dev/null +++ b/ivtest/gold/pr2976242c.gold @@ -0,0 +1,8 @@ +./ivltests/pr2976242c.v:43: error: Port out of module io_real_to_vec is declared as a real inout port. +./ivltests/pr2976242c.v:11: error: Cannot connect an arrayed instance of module vec_to_real to real signal r_vec. +./ivltests/pr2976242c.v:14: error: When automatically converting a real port of an arrayed instance to a bit signal +./ivltests/pr2976242c.v:14: : the signal width (5) must be an integer multiple of the instance count (2). +./ivltests/pr2976242c.v:15: error: An arrayed instance of arr_real cannot have a real port (port 1 : out) connected to a real signal (r_arr). +./ivltests/pr2976242c.v:18: error: Cannot automatically connect bit based inout port 1 (out) of module io_vec_to_real to real signal r_io. +./ivltests/pr2976242c.v:21: error: No support for connecting real inout ports (port 1 (out) of module io_real_to_vec). +6 error(s) during elaboration. diff --git a/ivtest/gold/pr298.gold b/ivtest/gold/pr298.gold new file mode 100644 index 000000000..06ddb6bcf --- /dev/null +++ b/ivtest/gold/pr298.gold @@ -0,0 +1,3 @@ +00 +00 +11 diff --git a/ivtest/gold/pr3015421-fsv.gold b/ivtest/gold/pr3015421-fsv.gold new file mode 100644 index 000000000..f544d178f --- /dev/null +++ b/ivtest/gold/pr3015421-fsv.gold @@ -0,0 +1,2 @@ +./ivltests/pr3015421.v:12: syntax error +I give up. diff --git a/ivtest/gold/pr3015421.gold b/ivtest/gold/pr3015421.gold new file mode 100644 index 000000000..60e72868a --- /dev/null +++ b/ivtest/gold/pr3015421.gold @@ -0,0 +1,3 @@ +./ivltests/pr3015421.v:7: syntax error +./ivltests/pr3015421.v:7: error: Syntax error defining function. +./ivltests/pr3015421.v:16: syntax error diff --git a/ivtest/gold/pr3039548.gold b/ivtest/gold/pr3039548.gold new file mode 100644 index 000000000..f06354b16 --- /dev/null +++ b/ivtest/gold/pr3039548.gold @@ -0,0 +1,2 @@ +00000001100000000010000000 +00000001100000000010000000 diff --git a/ivtest/gold/pr3054101a.gold b/ivtest/gold/pr3054101a.gold new file mode 100644 index 000000000..f9adfc7e7 --- /dev/null +++ b/ivtest/gold/pr3054101a.gold @@ -0,0 +1,31 @@ +a[s0]: x +b[s0]: x +a[s1]: x +b[s1]: x +a[s2]: x +b[s2]: x +c[s3]: 1 +d[s3]: 0 +c[s4]: 1 +d[s4]: 0 +ap[s0]: x +bp[s0]: x +ap[s1]: x +bp[s1]: x +ap[s2]: x +bp[s2]: x +cp[s3]: 1 +dp[s3]: 0 +cp[s4]: 1 +dp[s4]: 0 +ar[s0]: x +br[s0]: x +ar[s1]: x +br[s1]: x +ar[s2]: x +br[s2]: x +cr[s3]: 1 +dr[s3]: 0 +cr[s4]: 1 +dr[s4]: 0 +Compare tests passed diff --git a/ivtest/gold/pr3054101c.gold b/ivtest/gold/pr3054101c.gold new file mode 100644 index 000000000..a3bc062ca --- /dev/null +++ b/ivtest/gold/pr3054101c.gold @@ -0,0 +1,31 @@ +a[s0+:2]: 0x +b[s0+:2]: 1x +a[s1+:2]: 0x +b[s1+:2]: 1x +a[s2+:2]: 0x +b[s2+:2]: 1x +c[s3+:2]: x1 +d[s3+:2]: x0 +c[s4+:2]: x1 +d[s4+:2]: x0 +ap[s0+:2]: 0x +bp[s0+:2]: 1x +ap[s1+:2]: 0x +bp[s1+:2]: 1x +ap[s2+:2]: 0x +bp[s2+:2]: 1x +cp[s3+:2]: x1 +dp[s3+:2]: x0 +cp[s4+:2]: x1 +dp[s4+:2]: x0 +ar[s0+:2]: 0x +br[s0+:2]: 1x +ar[s1+:2]: 0x +br[s1+:2]: 1x +ar[s2+:2]: 0x +br[s2+:2]: 1x +cr[s3+:2]: x1 +dr[s3+:2]: x0 +cr[s4+:2]: x1 +dr[s4+:2]: x0 +Compare tests passed diff --git a/ivtest/gold/pr3054101e.gold b/ivtest/gold/pr3054101e.gold new file mode 100644 index 000000000..50b33ce49 --- /dev/null +++ b/ivtest/gold/pr3054101e.gold @@ -0,0 +1,31 @@ +a[s0-:2]: 0x +b[s0-:2]: 1x +a[s1-:2]: 0x +b[s1-:2]: 1x +a[s2-:2]: 0x +b[s2-:2]: 1x +c[s3-:2]: x1 +d[s3-:2]: x0 +c[s4-:2]: x1 +d[s4-:2]: x0 +ap[s0-:2]: 0x +bp[s0-:2]: 1x +ap[s1-:2]: 0x +bp[s1-:2]: 1x +ap[s2-:2]: 0x +bp[s2-:2]: 1x +cp[s3-:2]: x1 +dp[s3-:2]: x0 +cp[s4-:2]: x1 +dp[s4-:2]: x0 +ar[s0-:2]: 0x +br[s0-:2]: 1x +ar[s1-:2]: 0x +br[s1-:2]: 1x +ar[s2-:2]: 0x +br[s2-:2]: 1x +cr[s3-:2]: x1 +dr[s3-:2]: x0 +cr[s4-:2]: x1 +dr[s4-:2]: x0 +Compare tests passed diff --git a/ivtest/gold/pr3054101g.gold b/ivtest/gold/pr3054101g.gold new file mode 100644 index 000000000..56ba9593d --- /dev/null +++ b/ivtest/gold/pr3054101g.gold @@ -0,0 +1,11 @@ +a[s0]: xx +a[s1]: xx +a[s2]: xx +c[s3]: 11 +c[s4]: 11 +ar[s0]: xx +ar[s1]: xx +ar[s2]: xx +cr[s3]: 11 +cr[s4]: 11 +Compare tests passed diff --git a/ivtest/gold/pr3064375.gold b/ivtest/gold/pr3064375.gold new file mode 100644 index 000000000..a37886f07 --- /dev/null +++ b/ivtest/gold/pr3064375.gold @@ -0,0 +1,25 @@ +CLK 0 RST 1 Reg1 x Reg2 x +CLK 1 RST 1 Reg1 0 Reg2 x +CLK 0 RST 1 Reg1 0 Reg2 0 +CLK 1 RST 1 Reg1 0 Reg2 0 +CLK 0 RST 0 Reg1 0 Reg2 0 +CLK 1 RST 0 Reg1 1 Reg2 0 +CLK 0 RST 0 Reg1 1 Reg2 1 +CLK 1 RST 0 Reg1 0 Reg2 1 +CLK 0 RST 0 Reg1 0 Reg2 0 +CLK 1 RST 0 Reg1 1 Reg2 0 +CLK 0 RST 0 Reg1 1 Reg2 1 +CLK 1 RST 0 Reg1 0 Reg2 1 +CLK 0 RST 0 Reg1 0 Reg2 0 +CLK 1 RST 0 Reg1 1 Reg2 0 +CLK 0 RST 0 Reg1 1 Reg2 1 +CLK 1 RST 0 Reg1 0 Reg2 1 +CLK 0 RST 0 Reg1 0 Reg2 0 +CLK 1 RST 0 Reg1 1 Reg2 0 +CLK 0 RST 0 Reg1 1 Reg2 1 +CLK 1 RST 0 Reg1 0 Reg2 1 +CLK 0 RST 0 Reg1 0 Reg2 0 +CLK 1 RST 0 Reg1 1 Reg2 0 +CLK 0 RST 0 Reg1 1 Reg2 1 +CLK 1 RST 0 Reg1 0 Reg2 1 +CLK 0 RST 0 Reg1 0 Reg2 0 diff --git a/ivtest/gold/pr3149494.gold b/ivtest/gold/pr3149494.gold new file mode 100644 index 000000000..38b3b8fa0 --- /dev/null +++ b/ivtest/gold/pr3149494.gold @@ -0,0 +1,2 @@ +x = 1 +y = 111111111 diff --git a/ivtest/gold/pr3190941.gold b/ivtest/gold/pr3190941.gold new file mode 100644 index 000000000..0b63b4ffd --- /dev/null +++ b/ivtest/gold/pr3190941.gold @@ -0,0 +1,4 @@ +./ivltests/pr3190941.v:9: error: expression not valid in assign l-value: 4'bxxxx +./ivltests/pr3190941.v:9: error: Output port expression must support continuous assignment. +./ivltests/pr3190941.v:9: : Port 1 (x) of m1 is connected to {4'bxxxx, y} +2 error(s) during elaboration. diff --git a/ivtest/gold/pr3194155.gold b/ivtest/gold/pr3194155.gold new file mode 100644 index 000000000..3c448dca5 --- /dev/null +++ b/ivtest/gold/pr3194155.gold @@ -0,0 +1,9 @@ +./ivltests/pr3194155.v:13: warning: input port x is coerced to inout. +./ivltests/pr3194155.v:14: warning: input port x is coerced to inout. +x(1) : 0 +x(2) : 1 +x(3) : 0 +x(4) : 0 +x(5) : 0 +y : 0 +z : 0 diff --git a/ivtest/gold/pr3194155_std.gold b/ivtest/gold/pr3194155_std.gold new file mode 100644 index 000000000..64de784b0 --- /dev/null +++ b/ivtest/gold/pr3194155_std.gold @@ -0,0 +1,7 @@ +x(1) : 0 +x(2) : 1 +x(3) : 0 +x(4) : 0 +x(5) : 0 +y : 0 +z : 0 diff --git a/ivtest/gold/pr3366217a.gold b/ivtest/gold/pr3366217a.gold new file mode 100644 index 000000000..ccb991e1d --- /dev/null +++ b/ivtest/gold/pr3366217a.gold @@ -0,0 +1,2 @@ +./ivltests/pr3366217a.v:3: error: Enumeration name some0 has a value that is too large 32'sd100. +2 error(s) during elaboration. diff --git a/ivtest/gold/pr3366217b.gold b/ivtest/gold/pr3366217b.gold new file mode 100644 index 000000000..628cca2d6 --- /dev/null +++ b/ivtest/gold/pr3366217b.gold @@ -0,0 +1,4 @@ +./ivltests/pr3366217b.v:3: error: Enumeration name nega has a negative value. +./ivltests/pr3366217b.v:3: error: Enumeration name b has an inferred value that overflowed. +./ivltests/pr3366217b.v:3: error: Enumeration name c has an inferred value that overflowed. +4 error(s) during elaboration. diff --git a/ivtest/gold/pr3366217c.gold b/ivtest/gold/pr3366217c.gold new file mode 100644 index 000000000..fc8eb3353 --- /dev/null +++ b/ivtest/gold/pr3366217c.gold @@ -0,0 +1,3 @@ +./ivltests/pr3366217c.v:3: error: Enumeration name b has an inferred value that overflowed. +./ivltests/pr3366217c.v:3: error: Enumeration name c has an inferred value that overflowed. +3 error(s) during elaboration. diff --git a/ivtest/gold/pr3366217d.gold b/ivtest/gold/pr3366217d.gold new file mode 100644 index 000000000..2c8f41971 --- /dev/null +++ b/ivtest/gold/pr3366217d.gold @@ -0,0 +1,22 @@ +./ivltests/pr3366217d.v:3: error: undefined value used in enum name sequence. +./ivltests/pr3366217d.v:4: error: undefined value used in enum name sequence. +./ivltests/pr3366217d.v:5: error: undefined value used in enum name sequence. +./ivltests/pr3366217d.v:6: error: undefined value used in enum name sequence. +./ivltests/pr3366217d.v:6: error: undefined value used in enum name sequence. +./ivltests/pr3366217d.v:7: error: undefined value used in enum name sequence. +./ivltests/pr3366217d.v:8: error: undefined value used in enum name sequence. +./ivltests/pr3366217d.v:9: error: undefined value used in enum name sequence. +./ivltests/pr3366217d.v:10: error: undefined value used in enum name sequence. +./ivltests/pr3366217d.v:10: error: undefined value used in enum name sequence. +./ivltests/pr3366217d.v:13: error: zero count used in enum name sequence. +./ivltests/pr3366217d.v:14: error: zero count used in enum name sequence. +./ivltests/pr3366217d.v:17: error: negative value used in enum name sequence. +./ivltests/pr3366217d.v:18: error: negative value used in enum name sequence. +./ivltests/pr3366217d.v:19: error: negative value used in enum name sequence. +./ivltests/pr3366217d.v:20: error: negative value used in enum name sequence. +./ivltests/pr3366217d.v:20: error: negative value used in enum name sequence. +./ivltests/pr3366217d.v:21: error: negative value used in enum name sequence. +./ivltests/pr3366217d.v:22: error: negative value used in enum name sequence. +./ivltests/pr3366217d.v:23: error: negative value used in enum name sequence. +./ivltests/pr3366217d.v:24: error: negative value used in enum name sequence. +./ivltests/pr3366217d.v:24: error: negative value used in enum name sequence. diff --git a/ivtest/gold/pr3366217f.gold b/ivtest/gold/pr3366217f.gold new file mode 100644 index 000000000..d341484e7 --- /dev/null +++ b/ivtest/gold/pr3366217f.gold @@ -0,0 +1,7 @@ +First: -1 +Second: -2 +Third: -3 +Wrapped: -1 +Wrapped: -3 +As integer: -3 +Compile: -1 diff --git a/ivtest/gold/pr3366217g.gold b/ivtest/gold/pr3366217g.gold new file mode 100644 index 000000000..b662e8d25 --- /dev/null +++ b/ivtest/gold/pr3366217g.gold @@ -0,0 +1,3 @@ +./ivltests/pr3366217g.v:3: error: Enumeration name blue and green have the same value: 32'sd2 +./ivltests/pr3366217g.v:4: error: Enumeration name third and first have the same value: 32'sd2 +3 error(s) during elaboration. diff --git a/ivtest/gold/pr3441576.gold b/ivtest/gold/pr3441576.gold new file mode 100644 index 000000000..9159dd110 --- /dev/null +++ b/ivtest/gold/pr3441576.gold @@ -0,0 +1,2 @@ +./ivltests/pr3441576.v:3: warning: @* found no sensitivities so it will never trigger. +foo is x diff --git a/ivtest/gold/pr3499807.gold b/ivtest/gold/pr3499807.gold new file mode 100644 index 000000000..d8a0992bc --- /dev/null +++ b/ivtest/gold/pr3499807.gold @@ -0,0 +1,3 @@ + 0 0 x x + 100 0 0 x + 200 0 0 0 diff --git a/ivtest/gold/pr3515542.gold b/ivtest/gold/pr3515542.gold new file mode 100644 index 000000000..061d4d7d1 --- /dev/null +++ b/ivtest/gold/pr3515542.gold @@ -0,0 +1,6 @@ +./ivltests/pr3515542.v:5: error: Unbased SystemVerilog literal cannot have a size. +./ivltests/pr3515542.v:6: error: Unbased SystemVerilog literal cannot have a size. +./ivltests/pr3515542.v:7: error: Unbased SystemVerilog literal cannot have a size. +./ivltests/pr3515542.v:8: error: Unbased SystemVerilog literal cannot have a size. +./ivltests/pr3515542.v:9: error: Unbased SystemVerilog literal cannot have a size. +./ivltests/pr3515542.v:10: error: Unbased SystemVerilog literal cannot have a size. diff --git a/ivtest/gold/pr3522653.gold b/ivtest/gold/pr3522653.gold new file mode 100644 index 000000000..e9f6c9345 --- /dev/null +++ b/ivtest/gold/pr3522653.gold @@ -0,0 +1,8 @@ +00000000000000000000000000000001 + 1 +11111111111111111111111111111111 +4294967295 +00000000000000000000000000000001 + 1 +11111111111111111111111111111111 + -1 diff --git a/ivtest/gold/pr3527694.gold b/ivtest/gold/pr3527694.gold new file mode 100644 index 000000000..2755d7574 --- /dev/null +++ b/ivtest/gold/pr3527694.gold @@ -0,0 +1,9 @@ +top.test1.not1.test2_0 big_width: 00000012 +top.test1.not1.test2_1 big_width: 00000012 +top.test2_top big_width: 00000012 +top.test1.not1.test2_0.test3_0 wide: 00000012, width1:00000012, width2:00000012 +top.test1.not1.test2_0.test3_1 wide: 00000012, width1:00000012, width2:00000012 +top.test1.not1.test2_1.test3_0 wide: 00000012, width1:00000012, width2:00000012 +top.test1.not1.test2_1.test3_1 wide: 00000012, width1:00000012, width2:00000012 +top.test2_top.test3_0 wide: 00000012, width1:00000012, width2:00000012 +top.test2_top.test3_1 wide: 00000012, width1:00000012, width2:00000012 diff --git a/ivtest/gold/pr3571573.gold b/ivtest/gold/pr3571573.gold new file mode 100644 index 000000000..69ccb9f4a --- /dev/null +++ b/ivtest/gold/pr3571573.gold @@ -0,0 +1 @@ +zzz01z diff --git a/ivtest/gold/pr377.gold b/ivtest/gold/pr377.gold new file mode 100644 index 000000000..d4dc73eff --- /dev/null +++ b/ivtest/gold/pr377.gold @@ -0,0 +1,8 @@ +0 +1 +2 +3 +0 +1 +2 +3 diff --git a/ivtest/gold/pr434.gold b/ivtest/gold/pr434.gold new file mode 100644 index 000000000..c01dfc7d3 --- /dev/null +++ b/ivtest/gold/pr434.gold @@ -0,0 +1,10 @@ + 0 reset0=x, reset1=x, reset2=x, reset3=x + 10 reset0=0, reset1=0, reset2=0, reset3=0 + 75 reset0=1, reset1=0, reset2=0, reset3=0 + 105 reset0=0, reset1=0, reset2=0, reset3=0 + 165 reset0=0, reset1=1, reset2=0, reset3=0 + 195 reset0=0, reset1=0, reset2=0, reset3=0 + 225 reset0=0, reset1=0, reset2=1, reset3=0 + 255 reset0=0, reset1=0, reset2=0, reset3=0 + 285 reset0=0, reset1=0, reset2=0, reset3=1 + 315 reset0=0, reset1=0, reset2=0, reset3=0 diff --git a/ivtest/gold/pr487.gold b/ivtest/gold/pr487.gold new file mode 100644 index 000000000..6493422d3 --- /dev/null +++ b/ivtest/gold/pr487.gold @@ -0,0 +1,4 @@ +async_wrport[ 1] --> 1 +async_wrport[ 2] --> 1 +async_wrport[ 3] --> 0 +async_wrport[ 4] --> 0 diff --git a/ivtest/gold/pr492.gold b/ivtest/gold/pr492.gold new file mode 100644 index 000000000..2546bcb03 --- /dev/null +++ b/ivtest/gold/pr492.gold @@ -0,0 +1,23 @@ +000 000 +001 fff +002 ffe +003 ffd +004 ffc +005 ffb +006 ffa +007 ff9 +008 ff8 +009 ff7 +00a ff6 +00b ff5 +00c ff4 +00d ff3 +00e ff2 +00f ff1 +010 ff0 +011 fef +012 fee +013 fed +014 fec +015 feb +016 fea diff --git a/ivtest/gold/pr522.gold b/ivtest/gold/pr522.gold new file mode 100644 index 000000000..fc558581f --- /dev/null +++ b/ivtest/gold/pr522.gold @@ -0,0 +1,4 @@ + +***** simple block disable PASSED ***** +***** complex block & loop disable PASSED ***** + diff --git a/ivtest/gold/pr524.gold b/ivtest/gold/pr524.gold new file mode 100644 index 000000000..14a3b76c7 --- /dev/null +++ b/ivtest/gold/pr524.gold @@ -0,0 +1,2 @@ + 0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + 0 diff --git a/ivtest/gold/pr527.gold b/ivtest/gold/pr527.gold new file mode 100644 index 000000000..f85b02d51 --- /dev/null +++ b/ivtest/gold/pr527.gold @@ -0,0 +1,34 @@ + +expecting junk,junkbus to be 1 at T=1 +then changing to 0 at T=2 +then junk is 0 from T=3 to T=11, while +junkbus changes to 2 at T=5 and remains 2 through to T=16 +junk changes to 2 at T=12 +then 2 from T=13 to T=14 +then changing to 3 at T=15 +then 3 from T=16 on +junkbus changes to 3 at T=17 and remains 3 from then on + +time: 0, a: 01, junk: 01, junkbus: 01 +time: 1, a: 01, junk: 01, junkbus: 01 +time: 2, a: 01, junk: 00, junkbus: 00 +time: 3, a: 01, junk: 00, junkbus: 00 +time: 4, a: 01, junk: 00, junkbus: 00 +time: 5, a: 10, junk: 00, junkbus: 10 +time: 6, a: 10, junk: 00, junkbus: 10 +time: 7, a: 10, junk: 00, junkbus: 10 +time: 8, a: 10, junk: 00, junkbus: 10 +time: 9, a: 10, junk: 00, junkbus: 10 +time: 10, a: 10, junk: 00, junkbus: 10 +time: 11, a: 10, junk: 00, junkbus: 10 +time: 12, a: 10, junk: 10, junkbus: 10 +time: 13, a: 10, junk: 10, junkbus: 10 +time: 14, a: 10, junk: 10, junkbus: 10 +time: 15, a: 11, junk: 11, junkbus: 10 +time: 16, a: 11, junk: 11, junkbus: 10 +time: 17, a: 11, junk: 11, junkbus: 11 +time: 18, a: 11, junk: 11, junkbus: 11 +time: 19, a: 11, junk: 11, junkbus: 11 + + --------- force test passed --------- + diff --git a/ivtest/gold/pr528.gold b/ivtest/gold/pr528.gold new file mode 100644 index 000000000..74b3cc1e7 --- /dev/null +++ b/ivtest/gold/pr528.gold @@ -0,0 +1,21 @@ + 0 0 x x + 50 0 0 0 + 5000 1 0 0 + 5050 1 1 1 + 10000 0 1 1 + 10050 0 0 0 + 15000 1 0 0 + 15050 1 1 1 + 20000 0 1 1 + 20050 0 0 0 + 25000 1 0 0 + 25050 1 1 1 + 30000 0 1 1 + 30050 0 0 0 + 35000 1 0 0 + 35050 1 1 1 + 40000 0 1 1 + 40050 0 0 0 + 45000 1 0 0 + 45050 1 1 1 + 50000 0 1 1 diff --git a/ivtest/gold/pr528b.gold b/ivtest/gold/pr528b.gold new file mode 100644 index 000000000..74b3cc1e7 --- /dev/null +++ b/ivtest/gold/pr528b.gold @@ -0,0 +1,21 @@ + 0 0 x x + 50 0 0 0 + 5000 1 0 0 + 5050 1 1 1 + 10000 0 1 1 + 10050 0 0 0 + 15000 1 0 0 + 15050 1 1 1 + 20000 0 1 1 + 20050 0 0 0 + 25000 1 0 0 + 25050 1 1 1 + 30000 0 1 1 + 30050 0 0 0 + 35000 1 0 0 + 35050 1 1 1 + 40000 0 1 1 + 40050 0 0 0 + 45000 1 0 0 + 45050 1 1 1 + 50000 0 1 1 diff --git a/ivtest/gold/pr530.gold b/ivtest/gold/pr530.gold new file mode 100644 index 000000000..e39037a06 --- /dev/null +++ b/ivtest/gold/pr530.gold @@ -0,0 +1,2 @@ +here +in top, time: 0.000000ns diff --git a/ivtest/gold/pr531a.gold b/ivtest/gold/pr531a.gold new file mode 100644 index 000000000..789a901b7 --- /dev/null +++ b/ivtest/gold/pr531a.gold @@ -0,0 +1,26 @@ + time addr maddr m0 m1 m2 m3 m4 m5 m6 m7 + ---- ---- ----- ---- ---- ---- ---- ---- ---- ---- ---- + 0 0000 1000 1000 0001 0010 0011 0100 0101 0110 0111 + 100 0001 0001 1000 0001 0010 0011 0100 0101 0110 0111 + 200 0010 0010 1000 0001 0010 0011 0100 0101 0110 0111 + 300 0011 0011 1000 0001 0010 0011 0100 0101 0110 0111 + 400 0100 0100 1000 0001 0010 0011 0100 0101 0110 0111 + 500 0101 0101 1000 0001 0010 0011 0100 0101 0110 0111 + 600 0110 0110 1000 0001 0010 0011 0100 0101 0110 0111 + 700 0111 0111 1000 0001 0010 0011 0100 0101 0110 0111 + 800 1000 xxxx 1000 0001 0010 0011 0100 0101 0110 0111 + 900 001x xxxx 1000 0001 0010 0011 0100 0101 0110 0111 + 1000 01x0 xxxx 1000 0001 0010 0011 0100 0101 0110 0111 + 1100 0x01 xxxx 1000 0001 0010 0011 0100 0101 0110 0111 + 1200 0000 1000 1000 0001 0010 0011 0100 0101 0110 0111 + 1300 0000 1001 1001 0001 0010 0011 0100 0101 0110 0111 + 1400 0011 0011 1001 0001 0010 0011 0100 0101 0110 0111 + 1500 0011 1010 1001 0001 0010 1010 0100 0101 0110 0111 + 1600 0110 0110 1001 0001 0010 1010 0100 0101 0110 0111 + 1700 0110 1011 1001 0001 0010 1010 0100 0101 1011 0111 + 1800 1000 xxxx 1001 0001 0010 1010 0100 0101 1011 0111 + 2000 010x xxxx 1001 0001 0010 1010 0100 0101 1011 0111 + 2200 00x1 xxxx 1001 0001 0010 1010 0100 0101 1011 0111 + 2400 0x10 xxxx 1001 0001 0010 1010 0100 0101 1011 0111 + 2600 xxxx xxxx 1001 0001 0010 1010 0100 0101 1011 0111 +Finish at time 2800 diff --git a/ivtest/gold/pr532.gold b/ivtest/gold/pr532.gold new file mode 100644 index 000000000..19ddfefa0 --- /dev/null +++ b/ivtest/gold/pr532.gold @@ -0,0 +1,29 @@ + time ix vix vec + ---- ---- --- -------- + 0 0000 0 00000000 + 100 0001 0 00000000 + 200 0010 0 00000000 + 300 0011 0 00000000 + 400 0100 0 00000000 + 500 0101 0 00000000 + 600 0110 0 00000000 + 700 0111 0 00000000 + 800 1000 x 00000000 + 900 001x x 00000000 + 1000 01x0 x 00000000 + 1100 0x01 x 00000000 + 1200 0000 0 00000000 + 1300 0000 1 00000001 + 1400 0000 0 00000000 + 1500 0011 0 00000000 + 1600 0011 1 00001000 + 1700 0011 0 00000000 + 1800 0110 0 00000000 + 1900 0110 1 01000000 + 2000 0110 0 00000000 + 2100 1000 x 00000000 + 2400 010x x 00000000 + 2700 00x1 x 00000000 + 3000 0x10 x 00000000 + 3300 xxxx x 00000000 +Finish at time 3600 diff --git a/ivtest/gold/pr533.gold b/ivtest/gold/pr533.gold new file mode 100644 index 000000000..6c384c816 --- /dev/null +++ b/ivtest/gold/pr533.gold @@ -0,0 +1,4 @@ +x,x,x = ( x | ( xxxxx == xxxxx ) ) ? 0 : 1 +0,0,0 = ( 1 | ( xxxxx == xxxxx ) ) ? 0 : 1 +0,0,0 = ( 1 | ( 00000 == 00000 ) ) ? 0 : 1 +0,0,0 = ( 0 | ( 00000 == 00000 ) ) ? 0 : 1 diff --git a/ivtest/gold/pr534.gold b/ivtest/gold/pr534.gold new file mode 100644 index 000000000..b7267be6b --- /dev/null +++ b/ivtest/gold/pr534.gold @@ -0,0 +1,12 @@ + + ==> CHECK THIS DISPLAY ==> + +pci_clk_period: 15 +pci_clk_period: 1500 +after setting timeformat: +pci_clk_period: 15 +pci_clk_period: 15.00ns + ********************************************** + ****** time representation test OK ******* + ********************************************** + diff --git a/ivtest/gold/pr538.gold b/ivtest/gold/pr538.gold new file mode 100644 index 000000000..5e2a76fa7 --- /dev/null +++ b/ivtest/gold/pr538.gold @@ -0,0 +1,5 @@ + + ********************************************** + ********** timescale test PASSED ************* + ********************************************** + diff --git a/ivtest/gold/pr540.gold b/ivtest/gold/pr540.gold new file mode 100644 index 000000000..333c09f9c --- /dev/null +++ b/ivtest/gold/pr540.gold @@ -0,0 +1,7 @@ + +***** simple block disable PASSED ***** +***** block with loop disable PASSED ***** +***** forked block disable PASSED ***** +***** task with loop disable PASSED ***** +***** task with forked block disable PASSED **** + diff --git a/ivtest/gold/pr540b.gold b/ivtest/gold/pr540b.gold new file mode 100644 index 000000000..2f22a06db --- /dev/null +++ b/ivtest/gold/pr540b.gold @@ -0,0 +1,9 @@ +Check disable: +***** simple block PASSED ***** +***** block with loop PASSED ***** +***** forked block PASSED ***** +***** task with loop PASSED ***** +***** task with forked block PASSED ***** +***** one forked block PASSED ***** +***** the other forked block PASSED ***** + diff --git a/ivtest/gold/pr540c.gold b/ivtest/gold/pr540c.gold new file mode 100644 index 000000000..de9217725 --- /dev/null +++ b/ivtest/gold/pr540c.gold @@ -0,0 +1 @@ +***** disable test PASSED ***** diff --git a/ivtest/gold/pr541.gold b/ivtest/gold/pr541.gold new file mode 100644 index 000000000..86cb60557 --- /dev/null +++ b/ivtest/gold/pr541.gold @@ -0,0 +1,8 @@ +000000[5:0] = - 000[2:0] +111111[5:0] = - 001[2:0] +111110[5:0] = - 010[2:0] +111101[5:0] = - 011[2:0] +111100[5:0] = - 100[2:0] +111011[5:0] = - 101[2:0] +111010[5:0] = - 110[2:0] +111001[5:0] = - 111[2:0] diff --git a/ivtest/gold/pr542.gold b/ivtest/gold/pr542.gold new file mode 100644 index 000000000..9a7d146e7 --- /dev/null +++ b/ivtest/gold/pr542.gold @@ -0,0 +1,2 @@ +d_pm_in_dac_st = 1 +d_pm_in_dac_st = 1 diff --git a/ivtest/gold/pr544.gold b/ivtest/gold/pr544.gold new file mode 100644 index 000000000..6f18a1c1c --- /dev/null +++ b/ivtest/gold/pr544.gold @@ -0,0 +1,15 @@ + 0 Pu:0/0 St:0/0 Y:z,HiZ + 100 Pu:0/x St:0/0 Y:x,PuL + 200 Pu:0/0 St:0/x Y:x,StL + 300 Pu:1/x St:0/0 Y:x,PuH + 400 Pu:0/0 St:1/x Y:x,StH + 500 Pu:0/1 St:0/0 Y:0,Pu0 + 600 Pu:0/0 St:0/1 Y:0,St0 + 700 Pu:1/1 St:0/0 Y:1,Pu1 + 800 Pu:0/0 St:1/1 Y:1,St1 + 900 Pu:x/1 St:0/0 Y:x,PuX + 1000 Pu:0/0 St:x/1 Y:x,StX + 1100 Pu:0/1 St:0/x Y:0,650 + 1200 Pu:x/1 St:0/x Y:x,65X + 1300 Pu:1/1 St:1/x Y:1,651 + 1400 Pu:x/1 St:1/x Y:x,56X diff --git a/ivtest/gold/pr547.gold b/ivtest/gold/pr547.gold new file mode 100644 index 000000000..5c281962a --- /dev/null +++ b/ivtest/gold/pr547.gold @@ -0,0 +1 @@ +A = 3ff, b = x diff --git a/ivtest/gold/pr556.gold b/ivtest/gold/pr556.gold new file mode 100644 index 000000000..ac307a454 --- /dev/null +++ b/ivtest/gold/pr556.gold @@ -0,0 +1,256 @@ +The random number is 36 +The random number is -127 +The random number is -247 +The random number is -157 +The random number is 13 +The random number is 141 +The random number is -155 +The random number is -238 +The random number is 1 +The random number is 13 +The random number is 118 +The random number is 61 +The random number is 237 +The random number is 140 +The random number is 249 +The random number is -58 +The random number is -59 +The random number is -86 +The random number is 229 +The random number is -137 +The random number is -238 +The random number is 143 +The random number is 242 +The random number is -50 +The random number is -24 +The random number is -59 +The random number is 92 +The random number is -67 +The random number is -211 +The random number is -155 +The random number is -157 +The random number is 10 +The random number is -128 +The random number is 32 +The random number is 170 +The random number is -99 +The random number is -106 +The random number is -237 +The random number is -243 +The random number is -173 +The random number is 107 +The random number is -43 +The random number is -254 +The random number is -82 +The random number is 29 +The random number is -49 +The random number is 35 +The random number is 10 +The random number is -54 +The random number is -196 +The random number is 242 +The random number is 138 +The random number is 65 +The random number is -40 +The random number is 120 +The random number is -119 +The random number is 235 +The random number is 182 +The random number is 198 +The random number is 174 +The random number is -68 +The random number is 42 +The random number is -245 +The random number is -143 +The random number is 133 +The random number is 79 +The random number is -197 +The random number is 58 +The random number is -130 +The random number is 21 +The random number is 241 +The random number is 217 +The random number is 98 +The random number is 76 +The random number is 159 +The random number is 143 +The random number is 248 +The random number is -73 +The random number is -97 +The random number is -164 +The random number is -165 +The random number is 137 +The random number is -183 +The random number is -48 +The random number is -41 +The random number is -175 +The random number is 150 +The random number is 12 +The random number is -62 +The random number is 200 +The random number is -137 +The random number is 61 +The random number is 18 +The random number is -130 +The random number is 109 +The random number is 57 +The random number is 31 +The random number is -45 +The random number is 133 +The random number is -136 +The random number is 91 +The random number is 73 +The random number is -193 +The random number is 42 +The random number is 88 +The random number is -122 +The random number is -114 +The random number is -100 +The random number is 250 +The random number is -218 +The random number is 115 +The random number is -93 +The random number is -209 +The random number is -77 +The random number is -161 +The random number is 68 +The random number is 247 +The random number is -53 +The random number is -26 +The random number is 90 +The random number is 41 +The random number is -19 +The random number is -38 +The random number is -155 +The random number is -75 +The random number is -33 +The random number is 121 +The random number is 68 +The random number is -48 +The random number is 42 +The random number is 171 +The random number is 14 +The random number is 220 +The random number is -102 +The random number is -3 +The random number is -61 +The random number is 86 +The random number is 78 +The random number is -153 +The random number is -246 +The random number is 182 +The random number is -200 +The random number is 121 +The random number is -72 +The random number is 148 +The random number is 147 +The random number is -252 +The random number is -167 +The random number is 219 +The random number is -179 +The random number is 217 +The random number is -147 +The random number is -138 +The random number is 202 +The random number is 182 +The random number is 149 +The random number is -186 +The random number is 4 +The random number is 247 +The random number is 105 +The random number is -76 +The random number is 136 +The random number is 40 +The random number is -211 +The random number is -57 +The random number is -210 +The random number is -248 +The random number is 28 +The random number is -3 +The random number is 41 +The random number is -228 +The random number is 134 +The random number is -38 +The random number is -195 +The random number is 102 +The random number is -144 +The random number is -141 +The random number is 186 +The random number is 94 +The random number is 250 +The random number is 213 +The random number is -230 +The random number is -71 +The random number is 55 +The random number is 150 +The random number is 192 +The random number is 38 +The random number is -74 +The random number is 125 +The random number is 220 +The random number is 134 +The random number is 120 +The random number is 126 +The random number is -37 +The random number is -49 +The random number is 121 +The random number is -6 +The random number is -159 +The random number is 23 +The random number is -95 +The random number is 134 +The random number is -176 +The random number is 245 +The random number is -203 +The random number is -215 +The random number is 193 +The random number is -59 +The random number is -104 +The random number is 75 +The random number is -141 +The random number is -20 +The random number is -118 +The random number is 78 +The random number is -88 +The random number is 169 +The random number is -95 +The random number is 14 +The random number is -26 +The random number is -97 +The random number is 42 +The random number is 42 +The random number is -115 +The random number is 158 +The random number is -200 +The random number is -135 +The random number is 200 +The random number is 202 +The random number is 19 +The random number is 107 +The random number is -57 +The random number is 182 +The random number is 186 +The random number is 196 +The random number is 185 +The random number is 146 +The random number is -76 +The random number is 127 +The random number is -122 +The random number is 250 +The random number is -14 +The random number is 50 +The random number is -67 +The random number is 132 +The random number is -28 +The random number is 202 +The random number is 169 +The random number is -95 +The random number is 142 +The random number is -5 +The random number is -245 +The random number is -17 +The random number is 201 +The random number is 54 +The random number is -139 +The random number is -113 +The random number is 107 diff --git a/ivtest/gold/pr569.gold b/ivtest/gold/pr569.gold new file mode 100644 index 000000000..09595fb06 --- /dev/null +++ b/ivtest/gold/pr569.gold @@ -0,0 +1 @@ +010101010101010101010101 diff --git a/ivtest/gold/pr572.gold b/ivtest/gold/pr572.gold new file mode 100644 index 000000000..25a514171 --- /dev/null +++ b/ivtest/gold/pr572.gold @@ -0,0 +1,2 @@ +at 10: toplevel event triggered +at 25: local event triggered diff --git a/ivtest/gold/pr584.gold b/ivtest/gold/pr584.gold new file mode 100644 index 000000000..0bb816b39 --- /dev/null +++ b/ivtest/gold/pr584.gold @@ -0,0 +1,5 @@ +20 +20 +20 +20 +20 diff --git a/ivtest/gold/pr584_std.gold b/ivtest/gold/pr584_std.gold new file mode 100644 index 000000000..890dd4cdb --- /dev/null +++ b/ivtest/gold/pr584_std.gold @@ -0,0 +1,5 @@ + 20 + 20 + 20 + 20 + 20 diff --git a/ivtest/gold/pr590.gold b/ivtest/gold/pr590.gold new file mode 100644 index 000000000..ad05c0390 --- /dev/null +++ b/ivtest/gold/pr590.gold @@ -0,0 +1,9 @@ + + starting the testbench + +out: 0000, in: 0000 + 10..................clock tickling +out: 0011, in: 0010 + 30..................clock tickling + 50..................clock tickling + 70..................clock tickling diff --git a/ivtest/gold/pr594.gold b/ivtest/gold/pr594.gold new file mode 100644 index 000000000..5dac24c9b --- /dev/null +++ b/ivtest/gold/pr594.gold @@ -0,0 +1,21 @@ +RSData=30 +RSData=48 +RSData=31 +RSData=64 +RSData=32 +RSData=6a +RSData=33 +RSData=69 +RSData=34 +RSData=6b +RSData=20 +RSData=35 +RSData=52 +RSData=36 +RSData=69 +RSData=37 +RSData=6b +RSData=38 +RSData=64 +RSData=39 +RSData=5b diff --git a/ivtest/gold/pr596.gold b/ivtest/gold/pr596.gold new file mode 100644 index 000000000..39620e29f --- /dev/null +++ b/ivtest/gold/pr596.gold @@ -0,0 +1,49 @@ +out=0000 +out=0100 +out=0101 +out=0111 +out=0011 +out=0111 +out=0010 +out=0101 +out=0110 +out=0001 +out=0011 +out=0110 +out=0000 +out=0001 +out=0010 +out=0100 +out=0000 +out=0100 +out=0101 +out=0111 +out=0011 +out=0111 +out=0010 +out=0101 +out=0110 +out=0001 +out=0011 +out=0110 +out=0000 +out=0001 +out=0010 +out=0100 +out=0000 +out=0100 +out=0101 +out=0111 +out=0011 +out=0111 +out=0010 +out=0101 +out=0110 +out=0001 +out=0011 +out=0110 +out=0000 +out=0001 +out=0010 +out=0100 +out=0000 diff --git a/ivtest/gold/pr622.gold b/ivtest/gold/pr622.gold new file mode 100644 index 000000000..cd8bb5614 --- /dev/null +++ b/ivtest/gold/pr622.gold @@ -0,0 +1 @@ +macro FOO = bar diff --git a/ivtest/gold/pr632.gold b/ivtest/gold/pr632.gold new file mode 100644 index 000000000..f3a716e33 --- /dev/null +++ b/ivtest/gold/pr632.gold @@ -0,0 +1,31 @@ +a1[0]=1 +a1[0]=0 +a1[0]=1 +a1[0]=0 +a1[0]=1 +a1[0]=0 +a1[0]=1 +a1[0]=0 +a1[0]=1 +a1[0]=0 +a1[0]=1 +a1[0]=0 +a1[0]=1 +a1[0]=0 +a1[0]=1 +a1[0]=0 +a1[0]=1 +a1[0]=0 +a1[0]=1 +a1[0]=0 +a1[0]=1 +a1[0]=0 +a1[0]=1 +a1[0]=0 +a1[0]=1 +a1[0]=0 +a1[0]=1 +a1[0]=0 +a1[0]=1 +a1[0]=0 +a1[0]=1 diff --git a/ivtest/gold/pr639.gold b/ivtest/gold/pr639.gold new file mode 100644 index 000000000..5b5a2c336 --- /dev/null +++ b/ivtest/gold/pr639.gold @@ -0,0 +1,13 @@ +integer & real periods: 'd15 'd15 +integer & real periods (15.00, 15.20): 't15.00ns 't15.20ns +......... 15.2 should be displayed as 15.20 in its timeformat. +integer & real periods: 'b1111 'b1111 +integer & real periods: 'hf 'hf + $time is in ns + time (1, 1h): 'd1, 't1.00ns, 'h1 + $simtime is in 10 ps + simtime (100, 64h): 'd100, 't100.00ns, 'h64 + ********************************************** + ****** time precision test PASSED ******* + ********************************************** + diff --git a/ivtest/gold/pr673.gold b/ivtest/gold/pr673.gold new file mode 100644 index 000000000..b920adf73 --- /dev/null +++ b/ivtest/gold/pr673.gold @@ -0,0 +1,3 @@ +init right +right 10 10 +bye. diff --git a/ivtest/gold/pr693.gold b/ivtest/gold/pr693.gold new file mode 100644 index 000000000..f928980f4 --- /dev/null +++ b/ivtest/gold/pr693.gold @@ -0,0 +1,8 @@ +in=0000; co/sum = 0/0 +in=0001; co/sum = 0/1 +in=0010; co/sum = 0/1 +in=0011; co/sum = 1/0 +in=0100; co/sum = 0/1 +in=0101; co/sum = 1/0 +in=0110; co/sum = 1/0 +in=0111; co/sum = 1/1 diff --git a/ivtest/gold/pr729.gold b/ivtest/gold/pr729.gold new file mode 100644 index 000000000..68aacab21 --- /dev/null +++ b/ivtest/gold/pr729.gold @@ -0,0 +1 @@ +p_real=1.234500, v_real=1.234500, v_real_x2=2.469000 diff --git a/ivtest/gold/pr751.gold b/ivtest/gold/pr751.gold new file mode 100644 index 000000000..253a95640 --- /dev/null +++ b/ivtest/gold/pr751.gold @@ -0,0 +1,5 @@ +./ivltests/pr751.v:10: warning: @* is sensitive to all bits in 'in[0:3]'. + 0 xxxx[xx]: x + 10 0100[xx]: x + 20 0100[00]: 0 + 30 0100[01]: 1 diff --git a/ivtest/gold/pr751_std.gold b/ivtest/gold/pr751_std.gold new file mode 100644 index 000000000..c7f5fb9d3 --- /dev/null +++ b/ivtest/gold/pr751_std.gold @@ -0,0 +1,4 @@ + 0 xxxx[xx]: x + 10 0100[xx]: x + 20 0100[00]: 0 + 30 0100[01]: 1 diff --git a/ivtest/gold/pr812.gold b/ivtest/gold/pr812.gold new file mode 100644 index 000000000..c733a5977 --- /dev/null +++ b/ivtest/gold/pr812.gold @@ -0,0 +1,4 @@ +tp = 10.000000, tp2 = 10.000000 +tp == 10, (expected) +tp = 1 in top +tp = 10.000000, tp2 = 10.000000 diff --git a/ivtest/gold/pr820.gold b/ivtest/gold/pr820.gold new file mode 100644 index 000000000..d872e2932 --- /dev/null +++ b/ivtest/gold/pr820.gold @@ -0,0 +1,300 @@ + 10 waddr wdata 0 0 raddr rdata 14 x + 20 waddr wdata 1 3 raddr rdata 15 x + 30 waddr wdata 2 6 raddr rdata 0 x + 40 waddr wdata 3 9 raddr rdata 1 0 + 50 waddr wdata 4 12 raddr rdata 2 3 + 60 waddr wdata 5 15 raddr rdata 3 6 + 70 waddr wdata 6 18 raddr rdata 4 9 + 80 waddr wdata 7 21 raddr rdata 5 12 + 90 waddr wdata 8 24 raddr rdata 6 15 + 100 waddr wdata 9 27 raddr rdata 7 18 + 110 waddr wdata 10 30 raddr rdata 8 21 + 120 waddr wdata 11 33 raddr rdata 9 24 + 130 waddr wdata 12 36 raddr rdata 10 27 + 140 waddr wdata 13 39 raddr rdata 11 30 + 150 waddr wdata 14 42 raddr rdata 12 33 + 160 waddr wdata 15 45 raddr rdata 13 36 + 170 waddr wdata 0 48 raddr rdata 14 39 + 180 waddr wdata 1 51 raddr rdata 15 42 + 190 waddr wdata 2 54 raddr rdata 0 45 + 200 waddr wdata 3 57 raddr rdata 1 48 + 210 waddr wdata 4 60 raddr rdata 2 51 + 220 waddr wdata 5 63 raddr rdata 3 54 + 230 waddr wdata 6 66 raddr rdata 4 57 + 240 waddr wdata 7 69 raddr rdata 5 60 + 250 waddr wdata 8 72 raddr rdata 6 63 + 260 waddr wdata 9 75 raddr rdata 7 66 + 270 waddr wdata 10 78 raddr rdata 8 69 + 280 waddr wdata 11 81 raddr rdata 9 72 + 290 waddr wdata 12 84 raddr rdata 10 75 + 300 waddr wdata 13 87 raddr rdata 11 78 + 310 waddr wdata 14 90 raddr rdata 12 81 + 320 waddr wdata 15 93 raddr rdata 13 84 + 330 waddr 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113 + 1280 waddr wdata 15 125 raddr rdata 13 116 + 1290 waddr wdata 0 128 raddr rdata 14 119 + 1300 waddr wdata 1 131 raddr rdata 15 122 + 1310 waddr wdata 2 134 raddr rdata 0 125 + 1320 waddr wdata 3 137 raddr rdata 1 128 + 1330 waddr wdata 4 140 raddr rdata 2 131 + 1340 waddr wdata 5 143 raddr rdata 3 134 + 1350 waddr wdata 6 146 raddr rdata 4 137 + 1360 waddr wdata 7 149 raddr rdata 5 140 + 1370 waddr wdata 8 152 raddr rdata 6 143 + 1380 waddr wdata 9 155 raddr rdata 7 146 + 1390 waddr wdata 10 158 raddr rdata 8 149 + 1400 waddr wdata 11 161 raddr rdata 9 152 + 1410 waddr wdata 12 164 raddr rdata 10 155 + 1420 waddr wdata 13 167 raddr rdata 11 158 + 1430 waddr wdata 14 170 raddr rdata 12 161 + 1440 waddr wdata 15 173 raddr rdata 13 164 + 1450 waddr wdata 0 176 raddr rdata 14 167 + 1460 waddr wdata 1 179 raddr rdata 15 170 + 1470 waddr wdata 2 182 raddr rdata 0 173 + 1480 waddr wdata 3 185 raddr rdata 1 176 + 1490 waddr wdata 4 188 raddr rdata 2 179 + 1500 waddr wdata 5 191 raddr rdata 3 182 + 1510 waddr wdata 6 194 raddr rdata 4 185 + 1520 waddr wdata 7 197 raddr rdata 5 188 + 1530 waddr wdata 8 200 raddr rdata 6 191 + 1540 waddr wdata 9 203 raddr rdata 7 194 + 1550 waddr wdata 10 206 raddr rdata 8 197 + 1560 waddr wdata 11 209 raddr rdata 9 200 + 1570 waddr wdata 12 212 raddr rdata 10 203 + 1580 waddr wdata 13 215 raddr rdata 11 206 + 1590 waddr wdata 14 218 raddr rdata 12 209 + 1600 waddr wdata 15 221 raddr rdata 13 212 + 1610 waddr wdata 0 224 raddr rdata 14 215 + 1620 waddr wdata 1 227 raddr rdata 15 218 + 1630 waddr wdata 2 230 raddr rdata 0 221 + 1640 waddr wdata 3 233 raddr rdata 1 224 + 1650 waddr wdata 4 236 raddr rdata 2 227 + 1660 waddr wdata 5 239 raddr rdata 3 230 + 1670 waddr wdata 6 242 raddr rdata 4 233 + 1680 waddr wdata 7 245 raddr rdata 5 236 + 1690 waddr wdata 8 248 raddr rdata 6 239 + 1700 waddr wdata 9 251 raddr rdata 7 242 + 1710 waddr wdata 10 254 raddr rdata 8 245 + 1720 waddr wdata 11 1 raddr rdata 9 248 + 1730 waddr wdata 12 4 raddr rdata 10 251 + 1740 waddr wdata 13 7 raddr rdata 11 254 + 1750 waddr wdata 14 10 raddr rdata 12 1 + 1760 waddr wdata 15 13 raddr rdata 13 4 + 1770 waddr wdata 0 16 raddr rdata 14 7 + 1780 waddr wdata 1 19 raddr rdata 15 10 + 1790 waddr wdata 2 22 raddr rdata 0 13 + 1800 waddr wdata 3 25 raddr rdata 1 16 + 1810 waddr wdata 4 28 raddr rdata 2 19 + 1820 waddr wdata 5 31 raddr rdata 3 22 + 1830 waddr wdata 6 34 raddr rdata 4 25 + 1840 waddr wdata 7 37 raddr rdata 5 28 + 1850 waddr wdata 8 40 raddr rdata 6 31 + 1860 waddr wdata 9 43 raddr rdata 7 34 + 1870 waddr wdata 10 46 raddr rdata 8 37 + 1880 waddr wdata 11 49 raddr rdata 9 40 + 1890 waddr wdata 12 52 raddr rdata 10 43 + 1900 waddr wdata 13 55 raddr rdata 11 46 + 1910 waddr wdata 14 58 raddr rdata 12 49 + 1920 waddr wdata 15 61 raddr rdata 13 52 + 1930 waddr wdata 0 64 raddr rdata 14 55 + 1940 waddr wdata 1 67 raddr rdata 15 58 + 1950 waddr wdata 2 70 raddr rdata 0 61 + 1960 waddr wdata 3 73 raddr rdata 1 64 + 1970 waddr wdata 4 76 raddr rdata 2 67 + 1980 waddr wdata 5 79 raddr rdata 3 70 + 1990 waddr wdata 6 82 raddr rdata 4 73 + 2000 waddr wdata 7 85 raddr rdata 5 76 + 2010 waddr wdata 8 88 raddr rdata 6 79 + 2020 waddr wdata 9 91 raddr rdata 7 82 + 2030 waddr wdata 10 94 raddr rdata 8 85 + 2040 waddr wdata 11 97 raddr rdata 9 88 + 2050 waddr wdata 12 100 raddr rdata 10 91 + 2060 waddr wdata 13 103 raddr rdata 11 94 + 2070 waddr wdata 14 106 raddr rdata 12 97 + 2080 waddr wdata 15 109 raddr rdata 13 100 + 2090 waddr wdata 0 112 raddr rdata 14 103 + 2100 waddr wdata 1 115 raddr rdata 15 106 + 2110 waddr wdata 2 118 raddr rdata 0 109 + 2120 waddr wdata 3 121 raddr rdata 1 112 + 2130 waddr wdata 4 124 raddr rdata 2 115 + 2140 waddr wdata 5 127 raddr rdata 3 118 + 2150 waddr wdata 6 130 raddr rdata 4 121 + 2160 waddr wdata 7 133 raddr rdata 5 124 + 2170 waddr wdata 8 136 raddr rdata 6 127 + 2180 waddr wdata 9 139 raddr rdata 7 130 + 2190 waddr wdata 10 142 raddr rdata 8 133 + 2200 waddr wdata 11 145 raddr rdata 9 136 + 2210 waddr wdata 12 148 raddr rdata 10 139 + 2220 waddr wdata 13 151 raddr rdata 11 142 + 2230 waddr wdata 14 154 raddr rdata 12 145 + 2240 waddr wdata 15 157 raddr rdata 13 148 + 2250 waddr wdata 0 160 raddr rdata 14 151 + 2260 waddr wdata 1 163 raddr rdata 15 154 + 2270 waddr wdata 2 166 raddr rdata 0 157 + 2280 waddr wdata 3 169 raddr rdata 1 160 + 2290 waddr wdata 4 172 raddr rdata 2 163 + 2300 waddr wdata 5 175 raddr rdata 3 166 + 2310 waddr wdata 6 178 raddr rdata 4 169 + 2320 waddr wdata 7 181 raddr rdata 5 172 + 2330 waddr wdata 8 184 raddr rdata 6 175 + 2340 waddr wdata 9 187 raddr rdata 7 178 + 2350 waddr wdata 10 190 raddr rdata 8 181 + 2360 waddr wdata 11 193 raddr rdata 9 184 + 2370 waddr wdata 12 196 raddr rdata 10 187 + 2380 waddr wdata 13 199 raddr rdata 11 190 + 2390 waddr wdata 14 202 raddr rdata 12 193 + 2400 waddr wdata 15 205 raddr rdata 13 196 + 2410 waddr wdata 0 208 raddr rdata 14 199 + 2420 waddr wdata 1 211 raddr rdata 15 202 + 2430 waddr wdata 2 214 raddr rdata 0 205 + 2440 waddr wdata 3 217 raddr rdata 1 208 + 2450 waddr wdata 4 220 raddr rdata 2 211 + 2460 waddr wdata 5 223 raddr rdata 3 214 + 2470 waddr wdata 6 226 raddr rdata 4 217 + 2480 waddr wdata 7 229 raddr rdata 5 220 + 2490 waddr wdata 8 232 raddr rdata 6 223 + 2500 waddr wdata 9 235 raddr rdata 7 226 + 2510 waddr wdata 10 238 raddr rdata 8 229 + 2520 waddr wdata 11 241 raddr rdata 9 232 + 2530 waddr wdata 12 244 raddr rdata 10 235 + 2540 waddr wdata 13 247 raddr rdata 11 238 + 2550 waddr wdata 14 250 raddr rdata 12 241 + 2560 waddr wdata 15 253 raddr rdata 13 244 + 2570 waddr wdata 0 0 raddr rdata 14 247 + 2580 waddr wdata 1 3 raddr rdata 15 250 + 2590 waddr wdata 2 6 raddr rdata 0 253 + 2600 waddr wdata 3 9 raddr rdata 1 0 + 2610 waddr wdata 4 12 raddr rdata 2 3 + 2620 waddr wdata 5 15 raddr rdata 3 6 + 2630 waddr wdata 6 18 raddr rdata 4 9 + 2640 waddr wdata 7 21 raddr rdata 5 12 + 2650 waddr wdata 8 24 raddr rdata 6 15 + 2660 waddr wdata 9 27 raddr rdata 7 18 + 2670 waddr wdata 10 30 raddr rdata 8 21 + 2680 waddr wdata 11 33 raddr rdata 9 24 + 2690 waddr wdata 12 36 raddr rdata 10 27 + 2700 waddr wdata 13 39 raddr rdata 11 30 + 2710 waddr wdata 14 42 raddr rdata 12 33 + 2720 waddr wdata 15 45 raddr rdata 13 36 + 2730 waddr wdata 0 48 raddr rdata 14 39 + 2740 waddr wdata 1 51 raddr rdata 15 42 + 2750 waddr wdata 2 54 raddr rdata 0 45 + 2760 waddr wdata 3 57 raddr rdata 1 48 + 2770 waddr wdata 4 60 raddr rdata 2 51 + 2780 waddr wdata 5 63 raddr rdata 3 54 + 2790 waddr wdata 6 66 raddr rdata 4 57 + 2800 waddr wdata 7 69 raddr rdata 5 60 + 2810 waddr wdata 8 72 raddr rdata 6 63 + 2820 waddr wdata 9 75 raddr rdata 7 66 + 2830 waddr wdata 10 78 raddr rdata 8 69 + 2840 waddr wdata 11 81 raddr rdata 9 72 + 2850 waddr wdata 12 84 raddr rdata 10 75 + 2860 waddr wdata 13 87 raddr rdata 11 78 + 2870 waddr wdata 14 90 raddr rdata 12 81 + 2880 waddr wdata 15 93 raddr rdata 13 84 + 2890 waddr wdata 0 96 raddr rdata 14 87 + 2900 waddr wdata 1 99 raddr rdata 15 90 + 2910 waddr wdata 2 102 raddr rdata 0 93 + 2920 waddr wdata 3 105 raddr rdata 1 96 + 2930 waddr wdata 4 108 raddr rdata 2 99 + 2940 waddr wdata 5 111 raddr rdata 3 102 + 2950 waddr wdata 6 114 raddr rdata 4 105 + 2960 waddr wdata 7 117 raddr rdata 5 108 + 2970 waddr wdata 8 120 raddr rdata 6 111 + 2980 waddr wdata 9 123 raddr rdata 7 114 + 2990 waddr wdata 10 126 raddr rdata 8 117 + 3000 waddr wdata 11 129 raddr rdata 9 120 diff --git a/ivtest/gold/pr902.gold b/ivtest/gold/pr902.gold new file mode 100644 index 000000000..47e17628a --- /dev/null +++ b/ivtest/gold/pr902.gold @@ -0,0 +1 @@ + 0 0 0 0 diff --git a/ivtest/gold/pr905.gold b/ivtest/gold/pr905.gold new file mode 100644 index 000000000..320a0dbba --- /dev/null +++ b/ivtest/gold/pr905.gold @@ -0,0 +1,3 @@ +00000063 +00000000143 +00000000000000000000000001100011 diff --git a/ivtest/gold/pr910-vlog95.gold b/ivtest/gold/pr910-vlog95.gold new file mode 100644 index 000000000..c018dbb0d --- /dev/null +++ b/ivtest/gold/pr910-vlog95.gold @@ -0,0 +1,7 @@ +./ivltests/pr910.v:27: vlog95 warning: Duplicate name (cin) found for nexus (b) +./ivltests/pr910.v:27: vlog95 warning: Duplicate name (cin) found for nexus (b) +0000 00 +1000 00 +0000 00 +1000 00 +0000 00 diff --git a/ivtest/gold/pr910.gold b/ivtest/gold/pr910.gold new file mode 100644 index 000000000..3d76615a2 --- /dev/null +++ b/ivtest/gold/pr910.gold @@ -0,0 +1,5 @@ +0000 00 +1000 00 +0000 00 +1000 00 +0000 00 diff --git a/ivtest/gold/pr923.gold b/ivtest/gold/pr923.gold new file mode 100644 index 000000000..6eabb9b67 --- /dev/null +++ b/ivtest/gold/pr923.gold @@ -0,0 +1,21 @@ + 0 p1=x p2=StX + 5 p1=1 p2=StX + 10 p1=0 p2=St0 + 15 p1=1 p2=St0 + 20 p1=0 p2=St0 + 25 p1=1 p2=St0 + 30 p1=0 p2=St0 + 35 p1=1 p2=St0 + 40 p1=0 p2=St0 + 45 p1=1 p2=St0 + 50 p1=0 p2=St0 + 55 p1=1 p2=St0 + 60 p1=0 p2=St0 + 65 p1=1 p2=St0 + 70 p1=0 p2=St0 + 75 p1=1 p2=St0 + 80 p1=0 p2=St0 + 85 p1=1 p2=St0 + 90 p1=0 p2=St0 + 95 p1=1 p2=St0 + 100 p1=0 p2=St0 diff --git a/ivtest/gold/pr938.gold b/ivtest/gold/pr938.gold new file mode 100644 index 000000000..e66564084 --- /dev/null +++ b/ivtest/gold/pr938.gold @@ -0,0 +1,9 @@ +A B S out +0 0 0 --> 0 +1 0 0 --> 1 +0 1 0 --> 0 +1 1 0 --> 1 +0 0 1 --> 0 +1 0 1 --> 0 +0 1 1 --> 1 +1 1 1 --> 1 diff --git a/ivtest/gold/pr979.gold b/ivtest/gold/pr979.gold new file mode 100644 index 000000000..226c4cbbc --- /dev/null +++ b/ivtest/gold/pr979.gold @@ -0,0 +1,5 @@ +0.250000 0011111111010000000000000000000000000000000000000000000000000000 0.250000 +0.500000 0011111111100000000000000000000000000000000000000000000000000000 0.500000 +neg reals don't work +-0.250000 1011111111010000000000000000000000000000000000000000000000000000 -0.250000 +-0.500000 1011111111100000000000000000000000000000000000000000000000000000 -0.500000 diff --git a/ivtest/gold/pr985.gold b/ivtest/gold/pr985.gold new file mode 100644 index 000000000..c1fa97beb --- /dev/null +++ b/ivtest/gold/pr985.gold @@ -0,0 +1,2 @@ +GRANDCHILD parameters are: 00000008 10 1f +CHILD parameters are: 00000008 10 1f diff --git a/ivtest/gold/pr987.gold b/ivtest/gold/pr987.gold new file mode 100644 index 000000000..ce4c3d1e7 --- /dev/null +++ b/ivtest/gold/pr987.gold @@ -0,0 +1,4 @@ +./ivltests/pr987.v:12: warning: wait expression is constant false. +./ivltests/pr987.v:12: : The statement will block permanently. +Test thread runs. +Test thread runs. diff --git a/ivtest/gold/pr987_std.gold b/ivtest/gold/pr987_std.gold new file mode 100644 index 000000000..d5c154e04 --- /dev/null +++ b/ivtest/gold/pr987_std.gold @@ -0,0 +1,2 @@ +Test thread runs. +Test thread runs. diff --git a/ivtest/gold/pr991.gold b/ivtest/gold/pr991.gold new file mode 100644 index 000000000..f30d2e346 --- /dev/null +++ b/ivtest/gold/pr991.gold @@ -0,0 +1,5 @@ +0 +0 +1 +0 +1 diff --git a/ivtest/gold/pr993.gold b/ivtest/gold/pr993.gold new file mode 100644 index 000000000..b84dd60fe --- /dev/null +++ b/ivtest/gold/pr993.gold @@ -0,0 +1,55 @@ +length= 1, length_bits= 1 ( 1) +length= 2, length_bits= 2 ( 2) +length= 3, length_bits= 3 ( 3) +length= 4, length_bits= 3 ( 3) +length= 5, length_bits= 4 ( 4) +length= 6, length_bits= 5 ( 5) +length= 7, length_bits= 6 ( 6) +length= 8, length_bits= 6 ( 6) +length= 9, length_bits= 7 ( 7) +length= 10, length_bits= 8 ( 8) +length= 11, length_bits= 8 ( 8) +length= 12, length_bits= 9 ( 9) +length= 13, length_bits= 10 ( 10) +length= 14, length_bits= 11 ( 11) +length= 15, length_bits= 11 ( 11) +length= 16, length_bits= 12 ( 12) +length= 17, length_bits= 13 ( 13) +length= 18, length_bits= 14 ( 14) +length= 19, length_bits= 14 ( 14) +length= 20, length_bits= 15 ( 15) +length= 21, length_bits= 16 ( 16) +length= 22, length_bits= 16 ( 16) +length= 23, length_bits= 17 ( 17) +length= 24, length_bits= 18 ( 18) +length= 25, length_bits= 19 ( 19) +length= 26, length_bits= 19 ( 19) +length= 27, length_bits= 20 ( 20) +length= 28, length_bits= 21 ( 21) +length= 29, length_bits= 22 ( 22) +length= 30, length_bits= 22 ( 22) +length= 31, length_bits= 23 ( 23) +length= 32, length_bits= 24 ( 24) +length= 33, length_bits= 24 ( 24) +length= 34, length_bits= 25 ( 25) +length= 35, length_bits= 26 ( 26) +length= 36, length_bits= 27 ( 27) +length= 37, length_bits= 27 ( 27) +length= 38, length_bits= 28 ( 28) +length= 39, length_bits= 29 ( 29) +length= 40, length_bits= 30 ( 30) +length= 41, length_bits= 30 ( 30) +length= 42, length_bits= 31 ( 31) +length= 43, length_bits= 32 ( 32) +length= 44, length_bits= 32 ( 32) +length= 45, length_bits= 33 ( 33) +length= 46, length_bits= 34 ( 34) +length= 47, length_bits= 35 ( 35) +length= 48, length_bits= 35 ( 35) +length= 49, length_bits= 36 ( 36) +length= 50, length_bits= 37 ( 37) +length= 51, length_bits= 38 ( 38) +length= 52, length_bits= 38 ( 38) +length= 53, length_bits= 39 ( 39) +length= 54, length_bits= 40 ( 40) +length= 55, length_bits= 40 ( 40) diff --git a/ivtest/gold/pr995.gold b/ivtest/gold/pr995.gold new file mode 100644 index 000000000..e701d523a --- /dev/null +++ b/ivtest/gold/pr995.gold @@ -0,0 +1,96 @@ +Start sequence: seed=00000001 +seed=00010dce result=80010e00 +seed=1c5983f7 result=9c598438 +seed=c35937cc result=43593986 +seed=2e130a5d result=ae130c5c +seed=e723057a result=672307ce +seed=e3cc94b3 result=63cc97c7 +seed=63132a58 result=e3132cc6 +seed=79d76079 result=f9d762f3 +seed=e1d765e6 result=61d767c3 +seed=2f8f472f result=af8f485f +seed=a38863a4 result=23886547 +seed=44eb1e55 result=c4eb2089 +seed=3f269b12 result=bf269c7e +seed=22dc176b result=a2dc1845 +seed=2eda2fb0 result=aeda305d +seed=c8d41ff1 result=48d42191 +seed=b76dd0fe result=376dd36e +seed=478b4167 result=c78b428f +seed=9e3c9a7c result=1e3c9d3c +seed=64dc014d result=e4dc02c9 +seed=f18af3aa result=718af5e3 +seed=6e4ec123 result=ee4ec2dc +seed=16027008 result=9602722c +seed=2fac1e69 result=afac205f +seed=08c8af16 result=88c8b011 +seed=e8ae529f result=68ae55d1 +seed=80693c54 result=00693f00 +seed=68a99345 result=e8a994d1 +seed=ff8a6f42 result=7f8a71ff +seed=18c371db result=98c37231 +seed=33254b60 result=b3254c66 +Start sequence: seed=00000002 +seed=00021b9b result=80021c00 +seed=38b1fa20 result=b8b1fc71 +seed=6a58eba1 result=ea58ecd4 +seed=98ccdcee result=18ccdf31 +seed=a0330097 result=20330340 +seed=e07623ec result=607625c0 +seed=e259bffd result=6259c1c4 +seed=909b969a result=109b9921 +seed=49d76b53 result=c9d76c93 +seed=7d472878 result=fd472afa +seed=17818019 result=9781822f +seed=e64dd906 result=664ddbcc +seed=396217cf result=b9621872 +seed=069193c4 result=8691940d +seed=3ad847f5 result=bad84875 +seed=62ce1032 result=e2ce12c5 +seed=a607820b result=2607854c +seed=d7a8b1d0 result=57a8b3af +seed=f4edf391 result=74edf5e9 +seed=2b7b681e result=ab7b6a56 +seed=7e39e607 result=fe39e8fc +seed=eb128e9c result=6b1291d6 +seed=bdb61eed result=3db6217b +seed=4955ccca result=c955ce92 +seed=e1e53fc3 result=61e541c3 +seed=c893f628 result=4893f991 +seed=18242609 result=98242830 +seed=50e9ea36 result=d0e9eca1 +seed=966b4b3f result=166b4d2c +seed=31fc7474 result=b1fc7663 +seed=4d8724e5 result=cd87269b +Start sequence: seed=00000001 +seed=00010dce result=80010e00 +seed=1c5983f7 result=9c598438 +seed=c35937cc result=43593986 +seed=2e130a5d result=ae130c5c +seed=e723057a result=672307ce +seed=e3cc94b3 result=63cc97c7 +seed=63132a58 result=e3132cc6 +seed=79d76079 result=f9d762f3 +seed=e1d765e6 result=61d767c3 +seed=2f8f472f result=af8f485f +seed=a38863a4 result=23886547 +seed=44eb1e55 result=c4eb2089 +seed=3f269b12 result=bf269c7e +seed=22dc176b result=a2dc1845 +seed=2eda2fb0 result=aeda305d +seed=c8d41ff1 result=48d42191 +seed=b76dd0fe result=376dd36e +seed=478b4167 result=c78b428f +seed=9e3c9a7c result=1e3c9d3c +seed=64dc014d result=e4dc02c9 +seed=f18af3aa result=718af5e3 +seed=6e4ec123 result=ee4ec2dc +seed=16027008 result=9602722c +seed=2fac1e69 result=afac205f +seed=08c8af16 result=88c8b011 +seed=e8ae529f result=68ae55d1 +seed=80693c54 result=00693f00 +seed=68a99345 result=e8a994d1 +seed=ff8a6f42 result=7f8a71ff +seed=18c371db result=98c37231 +seed=33254b60 result=b3254c66 diff --git a/ivtest/gold/queue_fail-vlog95.gold b/ivtest/gold/queue_fail-vlog95.gold new file mode 100644 index 000000000..357bfd586 --- /dev/null +++ b/ivtest/gold/queue_fail-vlog95.gold @@ -0,0 +1,70 @@ +ERROR: vlog95.v:24: $q_initialize requires four arguments. +ERROR: vlog95.v:25: $q_initialize requires a second (<= 32 bit numeric) argument. +ERROR: vlog95.v:26: $q_initialize requires a second (<= 32 bit numeric) argument. +ERROR: vlog95.v:27: $q_initialize's first argument must be numeric (<= 32 bits). +ERROR: vlog95.v:27: $q_initialize requires a second (<= 32 bit numeric) argument. +ERROR: vlog95.v:28: $q_initialize requires a third (<= 32 bit numeric) argument. +ERROR: vlog95.v:29: $q_initialize requires a third (<= 32 bit numeric) argument. +ERROR: vlog95.v:30: $q_initialize's second argument must be numeric (<= 32 bits). +ERROR: vlog95.v:30: $q_initialize requires a third (<= 32 bit numeric) argument. +ERROR: vlog95.v:31: $q_initialize requires a fourth (variable) argument. +ERROR: vlog95.v:32: $q_initialize's third argument must be numeric (<= 32 bits). +ERROR: vlog95.v:32: $q_initialize requires a fourth (variable) argument. +ERROR: vlog95.v:33: $q_initialize's fourth argument must be a 32 bit variable. +ERROR: vlog95.v:34: $q_initialize's fourth (variable) argument must be 32 bits. +ERROR: vlog95.v:35: $q_initialize takes four arguments. + Found 1 extra argument. +ERROR: vlog95.v:36: $q_add requires four arguments. +ERROR: vlog95.v:37: $q_add requires a second (<= 32 bit numeric) argument. +ERROR: vlog95.v:38: $q_add requires a second (<= 32 bit numeric) argument. +ERROR: vlog95.v:39: $q_add's first argument must be numeric (<= 32 bits). +ERROR: vlog95.v:39: $q_add requires a second (<= 32 bit numeric) argument. +ERROR: vlog95.v:40: $q_add requires a third (<= 32 bit numeric) argument. +ERROR: vlog95.v:41: $q_add's second argument must be numeric (<= 32 bits). +ERROR: vlog95.v:41: $q_add requires a third (<= 32 bit numeric) argument. +ERROR: vlog95.v:42: $q_add requires a fourth (variable) argument. +ERROR: vlog95.v:43: $q_add's third argument must be numeric (<= 32 bits). +ERROR: vlog95.v:43: $q_add requires a fourth (variable) argument. +ERROR: vlog95.v:44: $q_add's fourth (variable) argument must be 32 bits. +ERROR: vlog95.v:45: $q_add takes four arguments. + Found 1 extra argument. +ERROR: vlog95.v:46: $q_remove requires four arguments. +ERROR: vlog95.v:47: $q_remove requires a second (variable) argument. +ERROR: vlog95.v:48: $q_remove requires a second (variable) argument. +ERROR: vlog95.v:49: $q_remove's first argument must be numeric (<= 32 bits). +ERROR: vlog95.v:49: $q_remove requires a second (variable) argument. +ERROR: vlog95.v:50: $q_remove requires a third (variable) argument. +ERROR: vlog95.v:51: $q_remove's second argument must be a 32 bit variable. +ERROR: vlog95.v:51: $q_remove requires a third (variable) argument. +ERROR: vlog95.v:52: $q_remove requires a fourth (variable) argument. +ERROR: vlog95.v:53: $q_remove's third argument must be a 32 bit variable. +ERROR: vlog95.v:53: $q_remove requires a fourth (variable) argument. +ERROR: vlog95.v:54: $q_remove's fourth (variable) argument must be 32 bits. +ERROR: vlog95.v:55: $q_remove's second (variable) argument must be 32 bits. +ERROR: vlog95.v:55: $q_remove's third (variable) argument must be 32 bits. +ERROR: vlog95.v:56: $q_remove takes four arguments. + Found 1 extra argument. +ERROR: vlog95.v:57: $q_full requires a second (variable) argument. +ERROR: vlog95.v:58: $q_full requires a second (variable) argument. +ERROR: vlog95.v:59: $q_full's first argument must be numeric (<= 32 bits). +ERROR: vlog95.v:59: $q_full requires a second (variable) argument. +ERROR: vlog95.v:60: $q_full's second (variable) argument must be 32 bits. +ERROR: vlog95.v:61: $q_full takes two arguments. + Found 1 extra argument. +ERROR: vlog95.v:62: $q_exam requires four arguments. +ERROR: vlog95.v:63: $q_exam requires a second (<= 32 bit numeric) argument. +ERROR: vlog95.v:64: $q_exam requires a second (<= 32 bit numeric) argument. +ERROR: vlog95.v:65: $q_exam's first argument must be numeric (<= 32 bits). +ERROR: vlog95.v:65: $q_exam requires a second (<= 32 bit numeric) argument. +ERROR: vlog95.v:66: $q_exam requires a third (variable) argument. +ERROR: vlog95.v:67: $q_exam requires a third (variable) argument. +ERROR: vlog95.v:68: $q_exam's second argument must be numeric (<= 32 bits). +ERROR: vlog95.v:68: $q_exam requires a third (variable) argument. +ERROR: vlog95.v:69: $q_exam requires a fourth (variable) argument. +ERROR: vlog95.v:70: $q_exam's third (variable) argument must have at least 32 bits. +ERROR: vlog95.v:70: $q_exam requires a fourth (variable) argument. +ERROR: vlog95.v:71: $q_exam's third argument must be a variable. +ERROR: vlog95.v:71: $q_exam requires a fourth (variable) argument. +ERROR: vlog95.v:72: $q_exam's fourth (variable) argument must be 32 bits. +ERROR: vlog95.v:73: $q_exam takes two arguments. + Found 1 extra argument. diff --git a/ivtest/gold/queue_fail.gold b/ivtest/gold/queue_fail.gold new file mode 100644 index 000000000..e9b4ff158 --- /dev/null +++ b/ivtest/gold/queue_fail.gold @@ -0,0 +1,70 @@ +ERROR: ./ivltests/queue_fail.v:7: $q_initialize requires four arguments. +ERROR: ./ivltests/queue_fail.v:8: $q_initialize requires a second (<= 32 bit numeric) argument. +ERROR: ./ivltests/queue_fail.v:9: $q_initialize requires a second (<= 32 bit numeric) argument. +ERROR: ./ivltests/queue_fail.v:10: $q_initialize's first argument must be numeric (<= 32 bits). +ERROR: ./ivltests/queue_fail.v:10: $q_initialize requires a second (<= 32 bit numeric) argument. +ERROR: ./ivltests/queue_fail.v:11: $q_initialize requires a third (<= 32 bit numeric) argument. +ERROR: ./ivltests/queue_fail.v:12: $q_initialize requires a third (<= 32 bit numeric) argument. +ERROR: ./ivltests/queue_fail.v:13: $q_initialize's second argument must be numeric (<= 32 bits). +ERROR: ./ivltests/queue_fail.v:13: $q_initialize requires a third (<= 32 bit numeric) argument. +ERROR: ./ivltests/queue_fail.v:14: $q_initialize requires a fourth (variable) argument. +ERROR: ./ivltests/queue_fail.v:15: $q_initialize's third argument must be numeric (<= 32 bits). +ERROR: ./ivltests/queue_fail.v:15: $q_initialize requires a fourth (variable) argument. +ERROR: ./ivltests/queue_fail.v:16: $q_initialize's fourth argument must be a 32 bit variable. +ERROR: ./ivltests/queue_fail.v:17: $q_initialize's fourth (variable) argument must be 32 bits. +ERROR: ./ivltests/queue_fail.v:18: $q_initialize takes four arguments. + Found 1 extra argument. +ERROR: ./ivltests/queue_fail.v:20: $q_add requires four arguments. +ERROR: ./ivltests/queue_fail.v:21: $q_add requires a second (<= 32 bit numeric) argument. +ERROR: ./ivltests/queue_fail.v:22: $q_add requires a second (<= 32 bit numeric) argument. +ERROR: ./ivltests/queue_fail.v:23: $q_add's first argument must be numeric (<= 32 bits). +ERROR: ./ivltests/queue_fail.v:23: $q_add requires a second (<= 32 bit numeric) argument. +ERROR: ./ivltests/queue_fail.v:24: $q_add requires a third (<= 32 bit numeric) argument. +ERROR: ./ivltests/queue_fail.v:25: $q_add's second argument must be numeric (<= 32 bits). +ERROR: ./ivltests/queue_fail.v:25: $q_add requires a third (<= 32 bit numeric) argument. +ERROR: ./ivltests/queue_fail.v:26: $q_add requires a fourth (variable) argument. +ERROR: ./ivltests/queue_fail.v:27: $q_add's third argument must be numeric (<= 32 bits). +ERROR: ./ivltests/queue_fail.v:27: $q_add requires a fourth (variable) argument. +ERROR: ./ivltests/queue_fail.v:28: $q_add's fourth (variable) argument must be 32 bits. +ERROR: ./ivltests/queue_fail.v:29: $q_add takes four arguments. + Found 1 extra argument. +ERROR: ./ivltests/queue_fail.v:31: $q_remove requires four arguments. +ERROR: ./ivltests/queue_fail.v:32: $q_remove requires a second (variable) argument. +ERROR: ./ivltests/queue_fail.v:33: $q_remove requires a second (variable) argument. +ERROR: ./ivltests/queue_fail.v:34: $q_remove's first argument must be numeric (<= 32 bits). +ERROR: ./ivltests/queue_fail.v:34: $q_remove requires a second (variable) argument. +ERROR: ./ivltests/queue_fail.v:35: $q_remove requires a third (variable) argument. +ERROR: ./ivltests/queue_fail.v:36: $q_remove's second argument must be a 32 bit variable. +ERROR: ./ivltests/queue_fail.v:36: $q_remove requires a third (variable) argument. +ERROR: ./ivltests/queue_fail.v:37: $q_remove requires a fourth (variable) argument. +ERROR: ./ivltests/queue_fail.v:38: $q_remove's third argument must be a 32 bit variable. +ERROR: ./ivltests/queue_fail.v:38: $q_remove requires a fourth (variable) argument. +ERROR: ./ivltests/queue_fail.v:39: $q_remove's fourth (variable) argument must be 32 bits. +ERROR: ./ivltests/queue_fail.v:40: $q_remove's second (variable) argument must be 32 bits. +ERROR: ./ivltests/queue_fail.v:40: $q_remove's third (variable) argument must be 32 bits. +ERROR: ./ivltests/queue_fail.v:41: $q_remove takes four arguments. + Found 1 extra argument. +ERROR: ./ivltests/queue_fail.v:43: $q_full requires a second (variable) argument. +ERROR: ./ivltests/queue_fail.v:44: $q_full requires a second (variable) argument. +ERROR: ./ivltests/queue_fail.v:45: $q_full's first argument must be numeric (<= 32 bits). +ERROR: ./ivltests/queue_fail.v:45: $q_full requires a second (variable) argument. +ERROR: ./ivltests/queue_fail.v:46: $q_full's second (variable) argument must be 32 bits. +ERROR: ./ivltests/queue_fail.v:47: $q_full takes two arguments. + Found 1 extra argument. +ERROR: ./ivltests/queue_fail.v:49: $q_exam requires four arguments. +ERROR: ./ivltests/queue_fail.v:50: $q_exam requires a second (<= 32 bit numeric) argument. +ERROR: ./ivltests/queue_fail.v:51: $q_exam requires a second (<= 32 bit numeric) argument. +ERROR: ./ivltests/queue_fail.v:52: $q_exam's first argument must be numeric (<= 32 bits). +ERROR: ./ivltests/queue_fail.v:52: $q_exam requires a second (<= 32 bit numeric) argument. +ERROR: ./ivltests/queue_fail.v:53: $q_exam requires a third (variable) argument. +ERROR: ./ivltests/queue_fail.v:54: $q_exam requires a third (variable) argument. +ERROR: ./ivltests/queue_fail.v:55: $q_exam's second argument must be numeric (<= 32 bits). +ERROR: ./ivltests/queue_fail.v:55: $q_exam requires a third (variable) argument. +ERROR: ./ivltests/queue_fail.v:56: $q_exam requires a fourth (variable) argument. +ERROR: ./ivltests/queue_fail.v:57: $q_exam's third (variable) argument must have at least 32 bits. +ERROR: ./ivltests/queue_fail.v:57: $q_exam requires a fourth (variable) argument. +ERROR: ./ivltests/queue_fail.v:58: $q_exam's third argument must be a variable. +ERROR: ./ivltests/queue_fail.v:58: $q_exam requires a fourth (variable) argument. +ERROR: ./ivltests/queue_fail.v:59: $q_exam's fourth (variable) argument must be 32 bits. +ERROR: ./ivltests/queue_fail.v:60: $q_exam takes two arguments. + Found 1 extra argument. diff --git a/ivtest/gold/queue_stat.gold b/ivtest/gold/queue_stat.gold new file mode 100644 index 000000000..0f198b917 --- /dev/null +++ b/ivtest/gold/queue_stat.gold @@ -0,0 +1,42 @@ +----- INIT ----- +Queue statistics at time 0 + 0, x, 0, x, x, x +----- ADD ----- +Queue statistics at time 0 + 1, x, 1, x, 0, 0 +----- ADD ----- +Queue statistics at time 1 + 2, 1, 2, x, 1, 0 +----- ADD ----- +Queue statistics at time 2 + 3, 1, 3, x, 2, 1 +----- REMOVE ----- +Queue statistics at time 3 + 2, 1, 3, 3, 2, 2 +Queue statistics at time 4 + 2, 1, 3, 3, 3, 2 +----- ADD ----- +Queue statistics at time 5 + 3, 1, 3, 3, 4, 2 +----- REMOVE TWO ----- +Queue statistics at time 6 + 1, 1, 3, 3, 1, 3 +----- REMOVE ----- +Queue statistics at time 7 + 0, 1, 3, 2, x, 3 +----- ADD ----- +Queue statistics at time 8 + 1, 2, 3, 2, 0, 2 +----- REMOVE ----- +Queue statistics at time 9 + 0, 2, 3, 1, x, 3 +----- ADD ----- +Queue statistics at time 16 + 1, 3, 3, 1, 0, 2 +----- ADD ----- +Queue statistics at time 17 + 2, 2, 3, 1, 1, 2 +----- ADD ----- +Queue statistics at time 18 + 3, 2, 3, 1, 2, 2 +PASSED diff --git a/ivtest/gold/readmem-error-vlog95.gold b/ivtest/gold/readmem-error-vlog95.gold new file mode 100644 index 000000000..5a18318c7 --- /dev/null +++ b/ivtest/gold/readmem-error-vlog95.gold @@ -0,0 +1,26 @@ +WARNING: vlog95.v:20: $readmemb's file name argument (vpiReg) is not a valid string. +WARNING: vlog95.v:21: $readmemb's file name argument (vpiIntegerVar) is not a valid string. +WARNING: vlog95.v:26: $readmemb's file name argument contains non-printable characters. + "ivltests/readmemb.tx\002" +WARNING: vlog95.v:29: $readmemb's third argument (start address) is a real value. +WARNING: vlog95.v:33: $readmemb's fourth argument (finish address) is a real value. +ERROR: vlog95.v:36: $readmemb: Start address -1 is out of bounds for memory 'top.array[0:7]'! +ERROR: vlog95.v:38: $readmemb: Start address 7 is out of bounds for memory 'top.array2[8:15]'! +ERROR: vlog95.v:40: $readmemb: Finish address 8 is out of bounds for memory 'top.array[0:7]'! +ERROR: vlog95.v:42: $readmemb: Finish address 16 is out of bounds for memory 'top.array2[8:15]'! +WARNING: vlog95.v:45: $readmemb(ivltests/readmemb.txt): Too many words in the file for the requested range [0:6]. +WARNING: vlog95.v:48: $readmemb(ivltests/readmemb.txt): Not enough words in the file for the requested range [-1:7]. +ERROR: vlog95.v:51: $readmemb(ivltests/readmem-error.txt): Invalid input character: u +WARNING: vlog95.v:53: $readmemh's file name argument (vpiReg) is not a valid string. +WARNING: vlog95.v:54: $readmemh's file name argument (vpiIntegerVar) is not a valid string. +WARNING: vlog95.v:59: $readmemh's file name argument contains non-printable characters. + "ivltests/readmemh.tx\002" +WARNING: vlog95.v:62: $readmemh's third argument (start address) is a real value. +WARNING: vlog95.v:66: $readmemh's fourth argument (finish address) is a real value. +ERROR: vlog95.v:69: $readmemh: Start address -1 is out of bounds for memory 'top.array[0:7]'! +ERROR: vlog95.v:71: $readmemh: Start address 7 is out of bounds for memory 'top.array2[8:15]'! +ERROR: vlog95.v:73: $readmemh: Finish address 8 is out of bounds for memory 'top.array[0:7]'! +ERROR: vlog95.v:75: $readmemh: Finish address 16 is out of bounds for memory 'top.array2[8:15]'! +WARNING: vlog95.v:78: $readmemh(ivltests/readmemh.txt): Too many words in the file for the requested range [0:6]. +WARNING: vlog95.v:81: $readmemh(ivltests/readmemh.txt): Not enough words in the file for the requested range [-1:7]. +ERROR: vlog95.v:84: $readmemh(ivltests/readmem-error.txt): Invalid input character: u diff --git a/ivtest/gold/readmem-error.gold b/ivtest/gold/readmem-error.gold new file mode 100644 index 000000000..449804bbf --- /dev/null +++ b/ivtest/gold/readmem-error.gold @@ -0,0 +1,26 @@ +WARNING: ./ivltests/readmem-error.v:18: $readmemb's file name argument (vpiReg) is not a valid string. +WARNING: ./ivltests/readmem-error.v:19: $readmemb's file name argument (vpiIntegerVar) is not a valid string. +WARNING: ./ivltests/readmem-error.v:33: $readmemb's file name argument contains non-printable characters. + "ivltests/readmemb.tx\002" +WARNING: ./ivltests/readmem-error.v:38: $readmemb's third argument (start address) is a real value. +WARNING: ./ivltests/readmem-error.v:49: $readmemb's fourth argument (finish address) is a real value. +ERROR: ./ivltests/readmem-error.v:59: $readmemb: Start address -1 is out of bounds for memory 'top.array[0:7]'! +ERROR: ./ivltests/readmem-error.v:67: $readmemb: Start address 7 is out of bounds for memory 'top.array2[8:15]'! +ERROR: ./ivltests/readmem-error.v:75: $readmemb: Finish address 8 is out of bounds for memory 'top.array[0:7]'! +ERROR: ./ivltests/readmem-error.v:83: $readmemb: Finish address 16 is out of bounds for memory 'top.array2[8:15]'! +WARNING: ./ivltests/readmem-error.v:93: $readmemb(ivltests/readmemb.txt): Too many words in the file for the requested range [0:6]. +WARNING: ./ivltests/readmem-error.v:105: $readmemb(ivltests/readmemb.txt): Not enough words in the file for the requested range [-1:7]. +ERROR: ./ivltests/readmem-error.v:118: $readmemb(ivltests/readmem-error.txt): Invalid input character: u +WARNING: ./ivltests/readmem-error.v:123: $readmemh's file name argument (vpiReg) is not a valid string. +WARNING: ./ivltests/readmem-error.v:124: $readmemh's file name argument (vpiIntegerVar) is not a valid string. +WARNING: ./ivltests/readmem-error.v:138: $readmemh's file name argument contains non-printable characters. + "ivltests/readmemh.tx\002" +WARNING: ./ivltests/readmem-error.v:143: $readmemh's third argument (start address) is a real value. +WARNING: ./ivltests/readmem-error.v:154: $readmemh's fourth argument (finish address) is a real value. +ERROR: ./ivltests/readmem-error.v:164: $readmemh: Start address -1 is out of bounds for memory 'top.array[0:7]'! +ERROR: ./ivltests/readmem-error.v:172: $readmemh: Start address 7 is out of bounds for memory 'top.array2[8:15]'! +ERROR: ./ivltests/readmem-error.v:180: $readmemh: Finish address 8 is out of bounds for memory 'top.array[0:7]'! +ERROR: ./ivltests/readmem-error.v:188: $readmemh: Finish address 16 is out of bounds for memory 'top.array2[8:15]'! +WARNING: ./ivltests/readmem-error.v:198: $readmemh(ivltests/readmemh.txt): Too many words in the file for the requested range [0:6]. +WARNING: ./ivltests/readmem-error.v:210: $readmemh(ivltests/readmemh.txt): Not enough words in the file for the requested range [-1:7]. +ERROR: ./ivltests/readmem-error.v:223: $readmemh(ivltests/readmem-error.txt): Invalid input character: u diff --git a/ivtest/gold/readmem-invalid-vlog95.gold b/ivtest/gold/readmem-invalid-vlog95.gold new file mode 100644 index 000000000..47a847642 --- /dev/null +++ b/ivtest/gold/readmem-invalid-vlog95.gold @@ -0,0 +1,18 @@ +ERROR: vlog95.v:14: $readmemb requires two arguments. +ERROR: vlog95.v:15: $readmemb's first argument must be a file name (string). +ERROR: vlog95.v:15: $readmemb requires a second (memory) argument. +ERROR: vlog95.v:16: $readmemb requires a second (memory) argument. +ERROR: vlog95.v:17: $readmemb's second argument must be a memory. +ERROR: vlog95.v:18: $readmemb's third argument must be a start address (numeric). +ERROR: vlog95.v:19: $readmemb's fourth argument must be a finish address (numeric). +ERROR: vlog95.v:20: $readmemb takes at most four arguments. + Found 1 extra argument. +ERROR: vlog95.v:21: $readmemh requires two arguments. +ERROR: vlog95.v:22: $readmemh's first argument must be a file name (string). +ERROR: vlog95.v:22: $readmemh requires a second (memory) argument. +ERROR: vlog95.v:23: $readmemh requires a second (memory) argument. +ERROR: vlog95.v:24: $readmemh's second argument must be a memory. +ERROR: vlog95.v:25: $readmemh's third argument must be a start address (numeric). +ERROR: vlog95.v:26: $readmemh's fourth argument must be a finish address (numeric). +ERROR: vlog95.v:27: $readmemh takes at most four arguments. + Found 1 extra argument. diff --git a/ivtest/gold/readmem-invalid.gold b/ivtest/gold/readmem-invalid.gold new file mode 100644 index 000000000..95c8cf7b6 --- /dev/null +++ b/ivtest/gold/readmem-invalid.gold @@ -0,0 +1,18 @@ +ERROR: ./ivltests/readmem-invalid.v:5: $readmemb requires two arguments. +ERROR: ./ivltests/readmem-invalid.v:6: $readmemb's first argument must be a file name (string). +ERROR: ./ivltests/readmem-invalid.v:6: $readmemb requires a second (memory) argument. +ERROR: ./ivltests/readmem-invalid.v:7: $readmemb requires a second (memory) argument. +ERROR: ./ivltests/readmem-invalid.v:8: $readmemb's second argument must be a memory. +ERROR: ./ivltests/readmem-invalid.v:9: $readmemb's third argument must be a start address (numeric). +ERROR: ./ivltests/readmem-invalid.v:10: $readmemb's fourth argument must be a finish address (numeric). +ERROR: ./ivltests/readmem-invalid.v:11: $readmemb takes at most four arguments. + Found 1 extra argument. +ERROR: ./ivltests/readmem-invalid.v:13: $readmemh requires two arguments. +ERROR: ./ivltests/readmem-invalid.v:14: $readmemh's first argument must be a file name (string). +ERROR: ./ivltests/readmem-invalid.v:14: $readmemh requires a second (memory) argument. +ERROR: ./ivltests/readmem-invalid.v:15: $readmemh requires a second (memory) argument. +ERROR: ./ivltests/readmem-invalid.v:16: $readmemh's second argument must be a memory. +ERROR: ./ivltests/readmem-invalid.v:17: $readmemh's third argument must be a start address (numeric). +ERROR: ./ivltests/readmem-invalid.v:18: $readmemh's fourth argument must be a finish address (numeric). +ERROR: ./ivltests/readmem-invalid.v:19: $readmemh takes at most four arguments. + Found 1 extra argument. diff --git a/ivtest/gold/real5.gold b/ivtest/gold/real5.gold new file mode 100644 index 000000000..048b98aba --- /dev/null +++ b/ivtest/gold/real5.gold @@ -0,0 +1 @@ +max foo period( posedge FOOCLK:0.050ns, 40000 : 0.000ns ); diff --git a/ivtest/gold/real_concat_invalid1.gold b/ivtest/gold/real_concat_invalid1.gold new file mode 100644 index 000000000..008b4b7fc --- /dev/null +++ b/ivtest/gold/real_concat_invalid1.gold @@ -0,0 +1,27 @@ +ivltests/real_concat_invalid1.v:5: error: concatenation operand can not be real: 2.00000 +ivltests/real_concat_invalid1.v:5: error: concatenation operand can not be real: 1.00000 +ivltests/real_concat_invalid1.v:5: error: Concatenation may not have zero width in this context. +ivltests/real_concat_invalid1.v:5: error: Unable to elaborate r-value: {2.00000, 1.00000} +ivltests/real_concat_invalid1.v:6: error: concatenation operand can not be real: rvar1 +ivltests/real_concat_invalid1.v:6: error: concatenation operand can not be real: rvar2 +ivltests/real_concat_invalid1.v:6: error: Concatenation may not have zero width in this context. +ivltests/real_concat_invalid1.v:6: error: Unable to elaborate r-value: {rvar1, rvar2} +ivltests/real_concat_invalid1.v:8: error: concatenation operand can not be real: 2.00000 +ivltests/real_concat_invalid1.v:8: error: concatenation operand can not be real: 1.00000 +ivltests/real_concat_invalid1.v:8: error: Concatenation may not have zero width in this context. +ivltests/real_concat_invalid1.v:8: error: Unable to elaborate r-value: {2.00000, 1.00000} +ivltests/real_concat_invalid1.v:9: error: concatenation operand can not be real: rvar1 +ivltests/real_concat_invalid1.v:9: error: concatenation operand can not be real: rvar2 +ivltests/real_concat_invalid1.v:9: error: Concatenation may not have zero width in this context. +ivltests/real_concat_invalid1.v:9: error: Unable to elaborate r-value: {rvar1, rvar2} +ivltests/real_concat_invalid1.v:11: error: concatenation operand can no be real: wrcon5 +ivltests/real_concat_invalid1.v:11: error: concatenation operand can no be real: wrcon6 +ivltests/real_concat_invalid1.v:14: error: concatenation operand can not be real: 2.00000 +ivltests/real_concat_invalid1.v:14: error: concatenation operand can not be real: 1.00000 +ivltests/real_concat_invalid1.v:14: error: Concatenation may not have zero width in this context. +ivltests/real_concat_invalid1.v:15: error: concatenation operand can not be real: rvar1 +ivltests/real_concat_invalid1.v:15: error: concatenation operand can not be real: rvar2 +ivltests/real_concat_invalid1.v:15: error: Concatenation may not have zero width in this context. +ivltests/real_concat_invalid1.v:17: error: concatenation operand can not be real: rvar1 +ivltests/real_concat_invalid1.v:17: error: concatenation operand can not be real: rvar2 +26 error(s) during elaboration. diff --git a/ivtest/gold/real_concat_invalid2.gold b/ivtest/gold/real_concat_invalid2.gold new file mode 100644 index 000000000..41f4d9322 --- /dev/null +++ b/ivtest/gold/real_concat_invalid2.gold @@ -0,0 +1,5 @@ +ivltests/real_concat_invalid2.v:5: error: concatenation operand can not be real: 2.00000 +ivltests/real_concat_invalid2.v:5: error: concatenation operand can not be real: 1.00000 +ivltests/real_concat_invalid2.v:4: error: concatenation operand can not be real: +ivltests/real_concat_invalid2.v:4: error: concatenation operand can not be real: +5 error(s) during elaboration. diff --git a/ivtest/gold/real_delay.gold b/ivtest/gold/real_delay.gold new file mode 100644 index 000000000..f8fa72629 --- /dev/null +++ b/ivtest/gold/real_delay.gold @@ -0,0 +1,4 @@ +0.000 00000000 000 00000000 00000000 +1.200 00000000 000 00000000 11111111 +1.230 00000000 000 11111111 11111111 +1.234 11111111 111 11111111 11111111 diff --git a/ivtest/gold/real_events.gold b/ivtest/gold/real_events.gold new file mode 100644 index 000000000..4bbdbe958 --- /dev/null +++ b/ivtest/gold/real_events.gold @@ -0,0 +1,10 @@ +val = 1.000000 +val = 2.000000 +val1 = 1.100000 +val2 = 1.200000 +val1 = 2.100000 +val2 = 2.200000 +val1 = 2.100000 +val2 = 2.200000 +val1 = 3.100000 +val2 = 3.200000 diff --git a/ivtest/gold/real_invalid_ops.gold b/ivtest/gold/real_invalid_ops.gold new file mode 100644 index 000000000..c36b8d014 --- /dev/null +++ b/ivtest/gold/real_invalid_ops.gold @@ -0,0 +1,69 @@ +./ivltests/real_invalid_ops.v:6: error: & operator may not have a REAL operand. +./ivltests/real_invalid_ops.v:6: error: Unable to elaborate r-value: &(var1) +./ivltests/real_invalid_ops.v:7: error: | operator may not have a REAL operand. +./ivltests/real_invalid_ops.v:7: error: Unable to elaborate r-value: |(var1) +./ivltests/real_invalid_ops.v:8: error: ^ operator may not have a REAL operand. +./ivltests/real_invalid_ops.v:8: error: Unable to elaborate r-value: ^(var1) +./ivltests/real_invalid_ops.v:9: error: ~& operator may not have a REAL operand. +./ivltests/real_invalid_ops.v:9: error: Unable to elaborate r-value: A(var1) +./ivltests/real_invalid_ops.v:10: error: ~| operator may not have a REAL operand. +./ivltests/real_invalid_ops.v:10: error: Unable to elaborate r-value: N(var1) +./ivltests/real_invalid_ops.v:11: error: ~^ operator may not have a REAL operand. +./ivltests/real_invalid_ops.v:11: error: Unable to elaborate r-value: X(var1) +./ivltests/real_invalid_ops.v:12: error: ~^ operator may not have a REAL operand. +./ivltests/real_invalid_ops.v:12: error: Unable to elaborate r-value: X(var1) +./ivltests/real_invalid_ops.v:14: error: & operator may not have REAL operands. +./ivltests/real_invalid_ops.v:14: error: Unable to elaborate r-value: (var1)&(var2) +./ivltests/real_invalid_ops.v:15: error: | operator may not have REAL operands. +./ivltests/real_invalid_ops.v:15: error: Unable to elaborate r-value: (var1)|(var2) +./ivltests/real_invalid_ops.v:16: error: ^ operator may not have REAL operands. +./ivltests/real_invalid_ops.v:16: error: Unable to elaborate r-value: (var1)^(var2) +./ivltests/real_invalid_ops.v:17: error: ~& operator may not have REAL operands. +./ivltests/real_invalid_ops.v:17: error: Unable to elaborate r-value: (var1)A(var2) +./ivltests/real_invalid_ops.v:18: error: ~| operator may not have REAL operands. +./ivltests/real_invalid_ops.v:18: error: Unable to elaborate r-value: (var1)O(var2) +./ivltests/real_invalid_ops.v:19: error: ~^ operator may not have REAL operands. +./ivltests/real_invalid_ops.v:19: error: Unable to elaborate r-value: (var1)X(var2) +./ivltests/real_invalid_ops.v:20: error: ~^ operator may not have REAL operands. +./ivltests/real_invalid_ops.v:20: error: Unable to elaborate r-value: (var1)X(var2) +./ivltests/real_invalid_ops.v:22: error: === operator may not have REAL or STRING operands. +./ivltests/real_invalid_ops.v:22: error: Unable to elaborate r-value: (var1)===(var2) +./ivltests/real_invalid_ops.v:23: error: !== operator may not have REAL or STRING operands. +./ivltests/real_invalid_ops.v:23: error: Unable to elaborate r-value: (var1)!==(var2) +./ivltests/real_invalid_ops.v:25: error: <<(<) operator may not have REAL operands. +./ivltests/real_invalid_ops.v:25: error: Unable to elaborate r-value: (var1)<<(var2) +./ivltests/real_invalid_ops.v:26: error: <<(<) operator may not have REAL operands. +./ivltests/real_invalid_ops.v:26: error: Unable to elaborate r-value: (var1)<<(var2) +./ivltests/real_invalid_ops.v:27: error: >> operator may not have REAL operands. +./ivltests/real_invalid_ops.v:27: error: Unable to elaborate r-value: (var1)>>(var2) +./ivltests/real_invalid_ops.v:28: error: >>> operator may not have REAL operands. +./ivltests/real_invalid_ops.v:28: error: Unable to elaborate r-value: (var1)>>>(var2) +./ivltests/real_invalid_ops.v:30: error: Concatenation operand can not be real: var1 +./ivltests/real_invalid_ops.v:30: error: Unable to elaborate r-value: {var1} +./ivltests/real_invalid_ops.v:31: error: Concatenation repeat expression can not be REAL. +./ivltests/real_invalid_ops.v:31: error: Concatenation operand can not be real: var1 +./ivltests/real_invalid_ops.v:31: error: Unable to elaborate r-value: {2.00000{var1}} +./ivltests/real_invalid_ops.v:40: error: & operator may not have a REAL operand. +./ivltests/real_invalid_ops.v:41: error: | operator may not have a REAL operand. +./ivltests/real_invalid_ops.v:42: error: ^ operator may not have a REAL operand. +./ivltests/real_invalid_ops.v:43: error: ~& operator may not have a REAL operand. +./ivltests/real_invalid_ops.v:44: error: ~| operator may not have a REAL operand. +./ivltests/real_invalid_ops.v:45: error: ~^ operator may not have a REAL operand. +./ivltests/real_invalid_ops.v:46: error: ~^ operator may not have a REAL operand. +./ivltests/real_invalid_ops.v:48: error: & operator may not have REAL operands. +./ivltests/real_invalid_ops.v:49: error: | operator may not have REAL operands. +./ivltests/real_invalid_ops.v:50: error: ^ operator may not have REAL operands. +./ivltests/real_invalid_ops.v:51: error: ~& operator may not have REAL operands. +./ivltests/real_invalid_ops.v:52: error: ~| operator may not have REAL operands. +./ivltests/real_invalid_ops.v:53: error: ~^ operator may not have REAL operands. +./ivltests/real_invalid_ops.v:54: error: ~^ operator may not have REAL operands. +./ivltests/real_invalid_ops.v:56: error: === operator may not have REAL or STRING operands. +./ivltests/real_invalid_ops.v:57: error: !== operator may not have REAL or STRING operands. +./ivltests/real_invalid_ops.v:59: error: <<(<) operator may not have REAL operands. +./ivltests/real_invalid_ops.v:60: error: <<(<) operator may not have REAL operands. +./ivltests/real_invalid_ops.v:61: error: >> operator may not have REAL operands. +./ivltests/real_invalid_ops.v:62: error: >>> operator may not have REAL operands. +./ivltests/real_invalid_ops.v:64: error: Concatenation operand can not be real: var1 +./ivltests/real_invalid_ops.v:65: error: Concatenation repeat expression can not be REAL. +./ivltests/real_invalid_ops.v:65: error: Concatenation operand can not be real: var1 +68 error(s) during elaboration. diff --git a/ivtest/gold/real_select_invalid.gold b/ivtest/gold/real_select_invalid.gold new file mode 100644 index 000000000..d98c495fe --- /dev/null +++ b/ivtest/gold/real_select_invalid.gold @@ -0,0 +1,89 @@ +ivltests/real_select_invalid.v:10: error: can not select part of real parameter: rpar +ivltests/real_select_invalid.v:10: error: Unable to elaborate r-value: rpar['sd0] +ivltests/real_select_invalid.v:11: error: can not select part of real parameter: rpar +ivltests/real_select_invalid.v:11: error: Unable to elaborate r-value: rpar['sd0:'sd0] +ivltests/real_select_invalid.v:12: error: can not select part of real parameter: rpar +ivltests/real_select_invalid.v:12: error: Unable to elaborate r-value: rpar['sd0+:'sd1] +ivltests/real_select_invalid.v:13: error: can not select part of real parameter: rpar +ivltests/real_select_invalid.v:13: error: Unable to elaborate r-value: rpar['sd0-:'sd1] +ivltests/real_select_invalid.v:15: error: can not select part of real: rvar +ivltests/real_select_invalid.v:15: error: Unable to elaborate r-value: rvar['sd0] +ivltests/real_select_invalid.v:16: error: can not select part of real: rvar +ivltests/real_select_invalid.v:16: error: Unable to elaborate r-value: rvar['sd0:'sd0] +ivltests/real_select_invalid.v:17: error: can not select part of real: rvar +ivltests/real_select_invalid.v:17: error: Unable to elaborate r-value: rvar['sd0+:'sd1] +ivltests/real_select_invalid.v:18: error: can not select part of real: rvar +ivltests/real_select_invalid.v:18: error: Unable to elaborate r-value: rvar['sd0-:'sd1] +ivltests/real_select_invalid.v:20: error: can not select part of real array word: rarr['sd0] +ivltests/real_select_invalid.v:20: error: Unable to elaborate r-value: rarr['sd0]['sd0] +ivltests/real_select_invalid.v:21: error: can not select part of real array word: rarr['sd0] +ivltests/real_select_invalid.v:21: error: Unable to elaborate r-value: rarr['sd0]['sd0:'sd0] +ivltests/real_select_invalid.v:22: error: can not select part of real array word: rarr['sd0] +ivltests/real_select_invalid.v:22: error: Unable to elaborate r-value: rarr['sd0]['sd0+:'sd1] +ivltests/real_select_invalid.v:23: error: can not select part of real array word: rarr['sd0] +ivltests/real_select_invalid.v:23: error: Unable to elaborate r-value: rarr['sd0]['sd0-:'sd1] +ivltests/real_select_invalid.v:25: error: can not select part of real: wrbslv +ivltests/real_select_invalid.v:26: error: can not select part of real: wrpslv +ivltests/real_select_invalid.v:27: error: can not select part of real: wruplv +ivltests/real_select_invalid.v:28: error: can not select part of real: wrdolv +ivltests/real_select_invalid.v:30: error: can not select part of real array word: wrarr[0] +ivltests/real_select_invalid.v:31: error: can not select part of real array word: wrarr[0] +ivltests/real_select_invalid.v:32: error: can not select part of real array word: wrarr[0] +ivltests/real_select_invalid.v:33: error: can not select part of real array word: wrarr[0] +ivltests/real_select_invalid.v:35: error: can not select part of real: wrbstr +ivltests/real_select_invalid.v:36: error: can not select part of real: wrpstr +ivltests/real_select_invalid.v:37: error: can not select part of real: wruptr +ivltests/real_select_invalid.v:38: error: can not select part of real: wrdotr +ivltests/real_select_invalid.v:40: error: can not select part of real: wrbstr +ivltests/real_select_invalid.v:40: internal error: Port expression too complicated for elaboration. +ivltests/real_select_invalid.v:40: error: can not select part of real: wrpstr +ivltests/real_select_invalid.v:40: internal error: Port expression too complicated for elaboration. +ivltests/real_select_invalid.v:40: error: can not select part of real: wruptr +ivltests/real_select_invalid.v:40: internal error: Port expression too complicated for elaboration. +ivltests/real_select_invalid.v:40: error: can not select part of real: wrdotr +ivltests/real_select_invalid.v:40: internal error: Port expression too complicated for elaboration. +ivltests/real_select_invalid.v:41: error: can not select part of real: wrbstr +ivltests/real_select_invalid.v:41: error: Output port expression must support continuous assignment. +ivltests/real_select_invalid.v:41: : Port of submod2 is arg1 +ivltests/real_select_invalid.v:41: error: can not select part of real: wrpstr +ivltests/real_select_invalid.v:41: error: Output port expression must support continuous assignment. +ivltests/real_select_invalid.v:41: : Port of submod2 is arg2 +ivltests/real_select_invalid.v:41: error: can not select part of real: wruptr +ivltests/real_select_invalid.v:41: error: Output port expression must support continuous assignment. +ivltests/real_select_invalid.v:41: : Port of submod2 is arg3 +ivltests/real_select_invalid.v:41: error: can not select part of real: wrdotr +ivltests/real_select_invalid.v:41: error: Output port expression must support continuous assignment. +ivltests/real_select_invalid.v:41: : Port of submod2 is arg4 +ivltests/real_select_invalid.v:42: error: can not select part of real: wrbstr +ivltests/real_select_invalid.v:42: error: Inout port expression must support continuous assignment. +ivltests/real_select_invalid.v:42: : Port of submod3 is arg1 +ivltests/real_select_invalid.v:42: error: can not select part of real: wrpstr +ivltests/real_select_invalid.v:42: error: Inout port expression must support continuous assignment. +ivltests/real_select_invalid.v:42: : Port of submod3 is arg2 +ivltests/real_select_invalid.v:42: error: can not select part of real: wruptr +ivltests/real_select_invalid.v:42: error: Inout port expression must support continuous assignment. +ivltests/real_select_invalid.v:42: : Port of submod3 is arg3 +ivltests/real_select_invalid.v:42: error: can not select part of real: wrdotr +ivltests/real_select_invalid.v:42: error: Inout port expression must support continuous assignment. +ivltests/real_select_invalid.v:42: : Port of submod3 is arg4 +ivltests/real_select_invalid.v:45: error: can not select part of real parameter: rpar +ivltests/real_select_invalid.v:46: error: can not select part of real parameter: rpar +ivltests/real_select_invalid.v:47: error: can not select part of real parameter: rpar +ivltests/real_select_invalid.v:48: error: can not select part of real parameter: rpar +ivltests/real_select_invalid.v:50: error: can not select part of real: rvar +ivltests/real_select_invalid.v:51: error: can not select part of real: rvar +ivltests/real_select_invalid.v:52: error: can not select part of real: rvar +ivltests/real_select_invalid.v:53: error: can not select part of real: rvar +ivltests/real_select_invalid.v:55: error: can not select part of real array word: rarr['sd0] +ivltests/real_select_invalid.v:56: error: can not select part of real array word: rarr['sd0] +ivltests/real_select_invalid.v:57: error: can not select part of real array word: rarr['sd0] +ivltests/real_select_invalid.v:58: error: can not select part of real array word: rarr['sd0] +ivltests/real_select_invalid.v:60: error: can not select part of real: rout +ivltests/real_select_invalid.v:61: error: can not select part of real: rout +ivltests/real_select_invalid.v:62: error: can not select part of real: rout +ivltests/real_select_invalid.v:63: error: can not select part of real: rout +ivltests/real_select_invalid.v:65: error: can not select part of real array word: rarr['sd0] +ivltests/real_select_invalid.v:66: error: can not select part of real array word: rarr['sd0] +ivltests/real_select_invalid.v:67: error: can not select part of real array word: rarr['sd0] +ivltests/real_select_invalid.v:68: error: can not select part of real array word: rarr['sd0] +76 error(s) during elaboration. diff --git a/ivtest/gold/recursive_func.gold b/ivtest/gold/recursive_func.gold new file mode 100644 index 000000000..7116adc3c --- /dev/null +++ b/ivtest/gold/recursive_func.gold @@ -0,0 +1,6 @@ +factorial 3 = 6 +factorial 4 = 24 +factorial 5 = 120 +factorial 6 = 720 +factorial 7 = 5040 +factorial 8 = 40320 diff --git a/ivtest/gold/recursive_task.gold b/ivtest/gold/recursive_task.gold new file mode 100644 index 000000000..49c48d6b2 --- /dev/null +++ b/ivtest/gold/recursive_task.gold @@ -0,0 +1,15 @@ +intermediate value = 1 +intermediate value = 1 +intermediate value = 1 +intermediate value = 2 +intermediate value = 2 +intermediate value = 2 +intermediate value = 6 +intermediate value = 6 +intermediate value = 6 +intermediate value = 24 +intermediate value = 24 +intermediate value = 120 +factorial 3 = 6 +factorial 4 = 24 +factorial 5 = 120 diff --git a/ivtest/gold/resetall-fsv.gold b/ivtest/gold/resetall-fsv.gold new file mode 100644 index 000000000..853d8b90e --- /dev/null +++ b/ivtest/gold/resetall-fsv.gold @@ -0,0 +1,10 @@ +warning: Some design elements have no explicit time unit and/or + : time precision. This may cause confusing timing results. + : Affected design elements are: + : -- module top_default declared here: ./ivltests/resetall.v:1 + : -- module top_resetall declared here: ./ivltests/resetall.v:20 +Time scale of (top_default) is 1s / 1s +Time scale of (top_timescale) is 1ns / 1ns +Time scale of (top_resetall) is 1s / 1s +Time scale of (top_timescale2) is 1ms / 1ms +Time scale of (top_timescale3) is 1us / 1us diff --git a/ivtest/gold/resetall-v10.gold b/ivtest/gold/resetall-v10.gold new file mode 100644 index 000000000..2140e3ab5 --- /dev/null +++ b/ivtest/gold/resetall-v10.gold @@ -0,0 +1,11 @@ +./ivltests/resetall.v:12: warning: Some modules have no timescale. This may cause +./ivltests/resetall.v:12: : confusing timing results. Affected modules are: +./ivltests/resetall.v:12: : -- module top_default declared here: ./ivltests/resetall.v:1 +./ivltests/resetall.v:26: warning: Some modules have no timescale. This may cause +./ivltests/resetall.v:26: : confusing timing results. Affected modules are: +./ivltests/resetall.v:26: : -- module top_resetall declared here: ./ivltests/resetall.v:20 +Time scale of (top_default) is 1s / 1s +Time scale of (top_timescale) is 1ns / 1ns +Time scale of (top_resetall) is 1s / 1s +Time scale of (top_timescale2) is 1ms / 1ms +Time scale of (top_timescale3) is 1us / 1us diff --git a/ivtest/gold/resetall.gold b/ivtest/gold/resetall.gold new file mode 100644 index 000000000..904b9a20e --- /dev/null +++ b/ivtest/gold/resetall.gold @@ -0,0 +1,9 @@ +warning: Some modules have no timescale. This may cause + : confusing timing results. Affected modules are: + : -- module top_default declared here: ./ivltests/resetall.v:1 + : -- module top_resetall declared here: ./ivltests/resetall.v:20 +Time scale of (top_default) is 1s / 1s +Time scale of (top_timescale) is 1ns / 1ns +Time scale of (top_resetall) is 1s / 1s +Time scale of (top_timescale2) is 1ms / 1ms +Time scale of (top_timescale3) is 1us / 1us diff --git a/ivtest/gold/resetall2.gold b/ivtest/gold/resetall2.gold new file mode 100644 index 000000000..81977f381 --- /dev/null +++ b/ivtest/gold/resetall2.gold @@ -0,0 +1,2 @@ +Time scale of (top_timescale) is 1us / 1us +Time scale of (top_timescale2) is 1ns / 1ns diff --git a/ivtest/gold/resetall2_std.gold b/ivtest/gold/resetall2_std.gold new file mode 100644 index 000000000..59c69a623 --- /dev/null +++ b/ivtest/gold/resetall2_std.gold @@ -0,0 +1,2 @@ +Time scale of (top_timescale) is 1us / 1us +Time scale of (top_timescale2) is 1ns / 1ns diff --git a/ivtest/gold/rtran.gold b/ivtest/gold/rtran.gold new file mode 100644 index 000000000..99fec707a --- /dev/null +++ b/ivtest/gold/rtran.gold @@ -0,0 +1,112 @@ +a = z b = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = x b = z +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX PuX) t12(67X PuX) t13(57X 35X) t14(37X 25X) t15(SuH PuH) +t21(76X PuX) t22(StX PuX) t23(56X 35X) t24(36X 25X) t25(StH PuH) +t31(75X 53X) t32(65X 53X) t33(PuX WeX) t34(35X 23X) t35(PuH WeH) +t41(73X 52X) t42(63X 52X) t43(53X 32X) t44(WeX MeX) t45(WeH MeH) +t51(SuL PuL) t52(StL PuL) t53(PuL WeL) t54(WeL MeL) t55(HiZ HiZ) +a = 0 b = z +a1(Su0) a2(Pu0) a3(We0) a4(Me0) a5(Sm0) a6(Sm0) a7(Sm0) +t11(Su0 Pu0) t12(St0 Pu0) t13(Pu0 We0) t14(We0 Me0) t15(HiZ HiZ) +t21(Su0 Pu0) t22(St0 Pu0) t23(Pu0 We0) t24(We0 Me0) t25(HiZ HiZ) +t31(Su0 Pu0) t32(St0 Pu0) t33(Pu0 We0) t34(We0 Me0) t35(HiZ HiZ) +t41(Su0 Pu0) t42(St0 Pu0) t43(Pu0 We0) t44(We0 Me0) t45(HiZ HiZ) +t51(Su0 Pu0) t52(St0 Pu0) t53(Pu0 We0) t54(We0 Me0) t55(HiZ HiZ) +a = 1 b = z +a1(Su1) a2(Pu1) a3(We1) a4(Me1) a5(Sm1) a6(Sm1) a7(Sm1) +t11(Su1 Pu1) t12(Su1 Pu1) t13(Su1 Pu1) t14(Su1 Pu1) t15(Su1 Pu1) +t21(St1 Pu1) t22(St1 Pu1) t23(St1 Pu1) t24(St1 Pu1) t25(St1 Pu1) +t31(Pu1 We1) t32(Pu1 We1) t33(Pu1 We1) t34(Pu1 We1) t35(Pu1 We1) +t41(We1 Me1) t42(We1 Me1) t43(We1 Me1) t44(We1 Me1) t45(We1 Me1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(PuX SuX) t12(PuX 67X) t13(35X 57X) t14(25X 37X) t15(PuH SuH) +t21(PuX 76X) t22(PuX StX) t23(35X 56X) t24(25X 36X) t25(PuH StH) +t31(53X 75X) t32(53X 65X) t33(WeX PuX) t34(23X 35X) t35(WeH PuH) +t41(52X 73X) t42(52X 63X) t43(32X 53X) t44(MeX WeX) t45(MeH WeH) +t51(PuL SuL) t52(PuL StL) t53(WeL PuL) t54(MeL WeL) t55(HiZ HiZ) +a = x b = x +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = 0 b = x +a1(Su0) a2(Pu0) a3(We0) a4(Me0) a5(Sm0) a6(Sm0) a7(Sm0) +t11(Su0 SuX) t12(St0 67X) t13(PuX 57X) t14(35X 37X) t15(PuH SuH) +t21(Su0 76X) t22(St0 StX) t23(PuX 56X) t24(35X 36X) t25(PuH StH) +t31(Su0 75X) t32(St0 65X) t33(Pu0 PuX) t34(WeX 35X) t35(WeH PuH) +t41(Su0 750) t42(St0 650) t43(Pu0 53X) t44(We0 WeX) t45(MeH WeH) +t51(Su0 750) t52(St0 650) t53(Pu0 530) t54(We0 320) t55(HiZ HiZ) +a = 1 b = x +a1(Su1) a2(Pu1) a3(We1) a4(Me1) a5(Sm1) a6(Sm1) a7(Sm1) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 57X) t14(Su1 751) t15(Su1 751) +t21(St1 76X) t22(St1 StX) t23(St1 56X) t24(St1 651) t25(St1 651) +t31(PuX 75X) t32(PuX 65X) t33(Pu1 PuX) t34(Pu1 35X) t35(Pu1 531) +t41(53X 73X) t42(53X 63X) t43(WeX 53X) t44(We1 WeX) t45(We1 321) +t51(PuL SuL) t52(PuL StL) t53(WeL PuL) t54(MeL WeL) t55(HiZ HiZ) +a = z b = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Pu0 Su0) t12(Pu0 St0) t13(We0 Pu0) t14(Me0 We0) t15(HiZ HiZ) +t21(Pu0 Su0) t22(Pu0 St0) t23(We0 Pu0) t24(Me0 We0) t25(HiZ HiZ) +t31(Pu0 Su0) t32(Pu0 St0) t33(We0 Pu0) t34(Me0 We0) t35(HiZ HiZ) +t41(Pu0 Su0) t42(Pu0 St0) t43(We0 Pu0) t44(Me0 We0) t45(HiZ HiZ) +t51(Pu0 Su0) t52(Pu0 St0) t53(We0 Pu0) t54(Me0 We0) t55(HiZ HiZ) +a = x b = 0 +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX Su0) t12(67X St0) t13(57X PuX) t14(37X 35X) t15(SuH PuH) +t21(76X Su0) t22(StX St0) t23(56X PuX) t24(36X 35X) t25(StH PuH) +t31(75X Su0) t32(65X St0) t33(PuX Pu0) t34(35X WeX) t35(PuH WeH) +t41(750 Su0) t42(650 St0) t43(53X Pu0) t44(WeX We0) t45(WeH MeH) +t51(750 Su0) t52(650 St0) t53(530 Pu0) t54(320 We0) t55(HiZ HiZ) +a = 0 b = 0 +a1(Su0) a2(Pu0) a3(We0) a4(Me0) a5(Sm0) a6(Sm0) a7(Sm0) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 1 b = 0 +a1(Su1) a2(Pu1) a3(We1) a4(Me1) a5(Sm1) a6(Sm1) a7(Sm1) +t11(Su1 Su0) t12(Su1 St0) t13(Su1 PuX) t14(Su1 Pu1) t15(Su1 Pu1) +t21(St1 Su0) t22(St1 St0) t23(St1 PuX) t24(St1 Pu1) t25(St1 Pu1) +t31(PuX Su0) t32(PuX St0) t33(Pu1 Pu0) t34(Pu1 WeX) t35(Pu1 We1) +t41(Pu0 Su0) t42(Pu0 St0) t43(WeX Pu0) t44(We1 We0) t45(We1 Me1) +t51(Pu0 Su0) t52(Pu0 St0) t53(We0 Pu0) t54(Me0 We0) t55(HiZ HiZ) +a = z b = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Pu1 Su1) t12(Pu1 Su1) t13(Pu1 Su1) t14(Pu1 Su1) t15(Pu1 Su1) +t21(Pu1 St1) t22(Pu1 St1) t23(Pu1 St1) t24(Pu1 St1) t25(Pu1 St1) +t31(We1 Pu1) t32(We1 Pu1) t33(We1 Pu1) t34(We1 Pu1) t35(We1 Pu1) +t41(Me1 We1) t42(Me1 We1) t43(Me1 We1) t44(Me1 We1) t45(Me1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = x b = 1 +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX Su1) t12(67X Su1) t13(57X Su1) t14(751 Su1) t15(751 Su1) +t21(76X St1) t22(StX St1) t23(56X St1) t24(651 St1) t25(651 St1) +t31(75X PuX) t32(65X PuX) t33(PuX Pu1) t34(35X Pu1) t35(531 Pu1) +t41(73X 53X) t42(63X 53X) t43(53X WeX) t44(WeX We1) t45(321 We1) +t51(SuL PuL) t52(StL PuL) t53(PuL WeL) t54(WeL MeL) t55(HiZ HiZ) +a = 0 b = 1 +a1(Su0) a2(Pu0) a3(We0) a4(Me0) a5(Sm0) a6(Sm0) a7(Sm0) +t11(Su0 Su1) t12(St0 Su1) t13(PuX Su1) t14(Pu1 Su1) t15(Pu1 Su1) +t21(Su0 St1) t22(St0 St1) t23(PuX St1) t24(Pu1 St1) t25(Pu1 St1) +t31(Su0 PuX) t32(St0 PuX) t33(Pu0 Pu1) t34(WeX Pu1) t35(We1 Pu1) +t41(Su0 Pu0) t42(St0 Pu0) t43(Pu0 WeX) t44(We0 We1) t45(Me1 We1) +t51(Su0 Pu0) t52(St0 Pu0) t53(Pu0 We0) t54(We0 Me0) t55(HiZ HiZ) +a = 1 b = 1 +a1(Su1) a2(Pu1) a3(We1) a4(Me1) a5(Sm1) a6(Sm1) a7(Sm1) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) diff --git a/ivtest/gold/rtranif0.gold b/ivtest/gold/rtranif0.gold new file mode 100644 index 000000000..eb6a3669a --- /dev/null +++ b/ivtest/gold/rtranif0.gold @@ -0,0 +1,448 @@ +a = z b = z en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = z en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = z en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = z en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = x b = z en = z +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX PuX) t12(67X PuX) t13(57X 35X) t14(37X 25X) t15(SuH PuH) +t21(76X PuX) t22(StX PuX) t23(56X 35X) t24(36X 25X) t25(StH PuH) +t31(75X 53X) t32(65X 53X) t33(PuX WeX) t34(35X 23X) t35(PuH WeH) +t41(73X 52X) t42(63X 52X) t43(53X 32X) t44(WeX MeX) t45(WeH MeH) +t51(SuL PuL) t52(StL PuL) t53(PuL WeL) t54(WeL MeL) t55(HiZ HiZ) +a = x b = z en = x +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX PuX) t12(67X PuX) t13(57X 35X) t14(37X 25X) t15(SuH PuH) +t21(76X PuX) t22(StX PuX) t23(56X 35X) t24(36X 25X) t25(StH PuH) +t31(75X 53X) t32(65X 53X) t33(PuX WeX) t34(35X 23X) t35(PuH WeH) +t41(73X 52X) t42(63X 52X) t43(53X 32X) t44(WeX MeX) t45(WeH MeH) +t51(SuL PuL) t52(StL PuL) t53(PuL WeL) t54(WeL MeL) t55(HiZ HiZ) +a = x b = z en = 0 +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX PuX) t12(67X PuX) t13(57X 35X) t14(37X 25X) t15(SuH PuH) +t21(76X PuX) t22(StX PuX) t23(56X 35X) t24(36X 25X) t25(StH PuH) +t31(75X 53X) t32(65X 53X) t33(PuX WeX) t34(35X 23X) t35(PuH WeH) +t41(73X 52X) t42(63X 52X) t43(53X 32X) t44(WeX MeX) t45(WeH MeH) +t51(SuL PuL) t52(StL PuL) t53(PuL WeL) t54(WeL MeL) t55(HiZ HiZ) +a = x b = z en = 1 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX HiZ) t12(67X HiZ) t13(57X HiZ) t14(37X HiZ) t15(SuH HiZ) +t21(76X HiZ) t22(StX HiZ) t23(56X HiZ) t24(36X HiZ) t25(StH HiZ) +t31(75X HiZ) t32(65X HiZ) t33(PuX HiZ) t34(35X HiZ) t35(PuH HiZ) +t41(73X HiZ) t42(63X HiZ) t43(53X HiZ) t44(WeX HiZ) t45(WeH HiZ) +t51(SuL HiZ) t52(StL HiZ) t53(PuL HiZ) t54(WeL HiZ) t55(HiZ HiZ) +a = 0 b = z en = z +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 PuL) t12(St0 PuL) t13(Pu0 WeL) t14(We0 MeL) t15(HiZ HiZ) +t21(Su0 PuL) t22(St0 PuL) t23(Pu0 WeL) t24(We0 MeL) t25(HiZ HiZ) +t31(Su0 PuL) t32(St0 PuL) t33(Pu0 WeL) t34(We0 MeL) t35(HiZ HiZ) +t41(Su0 PuL) t42(St0 PuL) t43(Pu0 WeL) t44(We0 MeL) t45(HiZ HiZ) +t51(Su0 PuL) t52(St0 PuL) t53(Pu0 WeL) t54(We0 MeL) t55(HiZ HiZ) +a = 0 b = z en = x +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 PuL) t12(St0 PuL) t13(Pu0 WeL) t14(We0 MeL) t15(HiZ HiZ) +t21(Su0 PuL) t22(St0 PuL) t23(Pu0 WeL) t24(We0 MeL) t25(HiZ HiZ) +t31(Su0 PuL) t32(St0 PuL) t33(Pu0 WeL) t34(We0 MeL) t35(HiZ HiZ) +t41(Su0 PuL) t42(St0 PuL) t43(Pu0 WeL) t44(We0 MeL) t45(HiZ HiZ) +t51(Su0 PuL) t52(St0 PuL) t53(Pu0 WeL) t54(We0 MeL) t55(HiZ HiZ) +a = 0 b = z en = 0 +a1(Su0) a2(Pu0) a3(We0) a4(Me0) a5(Sm0) a6(Sm0) a7(Sm0) +t11(Su0 Pu0) t12(St0 Pu0) t13(Pu0 We0) t14(We0 Me0) t15(HiZ HiZ) +t21(Su0 Pu0) t22(St0 Pu0) t23(Pu0 We0) t24(We0 Me0) t25(HiZ HiZ) +t31(Su0 Pu0) t32(St0 Pu0) t33(Pu0 We0) t34(We0 Me0) t35(HiZ HiZ) +t41(Su0 Pu0) t42(St0 Pu0) t43(Pu0 We0) t44(We0 Me0) t45(HiZ HiZ) +t51(Su0 Pu0) t52(St0 Pu0) t53(Pu0 We0) t54(We0 Me0) t55(HiZ HiZ) +a = 0 b = z en = 1 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 HiZ) t12(St0 HiZ) t13(Pu0 HiZ) t14(We0 HiZ) t15(HiZ HiZ) +t21(Su0 HiZ) t22(St0 HiZ) t23(Pu0 HiZ) t24(We0 HiZ) t25(HiZ HiZ) +t31(Su0 HiZ) t32(St0 HiZ) t33(Pu0 HiZ) t34(We0 HiZ) t35(HiZ HiZ) +t41(Su0 HiZ) t42(St0 HiZ) t43(Pu0 HiZ) t44(We0 HiZ) t45(HiZ HiZ) +t51(Su0 HiZ) t52(St0 HiZ) t53(Pu0 HiZ) t54(We0 HiZ) t55(HiZ HiZ) +a = 1 b = z en = z +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 PuH) t12(Su1 PuH) t13(Su1 PuH) t14(Su1 PuH) t15(Su1 PuH) +t21(St1 PuH) t22(St1 PuH) t23(St1 PuH) t24(St1 PuH) t25(St1 PuH) +t31(Pu1 WeH) t32(Pu1 WeH) t33(Pu1 WeH) t34(Pu1 WeH) t35(Pu1 WeH) +t41(We1 MeH) t42(We1 MeH) t43(We1 MeH) t44(We1 MeH) t45(We1 MeH) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = z en = x +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 PuH) t12(Su1 PuH) t13(Su1 PuH) t14(Su1 PuH) t15(Su1 PuH) +t21(St1 PuH) t22(St1 PuH) t23(St1 PuH) t24(St1 PuH) t25(St1 PuH) +t31(Pu1 WeH) t32(Pu1 WeH) t33(Pu1 WeH) t34(Pu1 WeH) t35(Pu1 WeH) +t41(We1 MeH) t42(We1 MeH) t43(We1 MeH) t44(We1 MeH) t45(We1 MeH) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = z en = 0 +a1(Su1) a2(Pu1) a3(We1) a4(Me1) a5(Sm1) a6(Sm1) a7(Sm1) +t11(Su1 Pu1) t12(Su1 Pu1) t13(Su1 Pu1) t14(Su1 Pu1) t15(Su1 Pu1) +t21(St1 Pu1) t22(St1 Pu1) t23(St1 Pu1) t24(St1 Pu1) t25(St1 Pu1) +t31(Pu1 We1) t32(Pu1 We1) t33(Pu1 We1) t34(Pu1 We1) t35(Pu1 We1) +t41(We1 Me1) t42(We1 Me1) t43(We1 Me1) t44(We1 Me1) t45(We1 Me1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = z en = 1 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 HiZ) t12(Su1 HiZ) t13(Su1 HiZ) t14(Su1 HiZ) t15(Su1 HiZ) +t21(St1 HiZ) t22(St1 HiZ) t23(St1 HiZ) t24(St1 HiZ) t25(St1 HiZ) +t31(Pu1 HiZ) t32(Pu1 HiZ) t33(Pu1 HiZ) t34(Pu1 HiZ) t35(Pu1 HiZ) +t41(We1 HiZ) t42(We1 HiZ) t43(We1 HiZ) t44(We1 HiZ) t45(We1 HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = x en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(PuX SuX) t12(PuX 67X) t13(35X 57X) t14(25X 37X) t15(PuH SuH) +t21(PuX 76X) t22(PuX StX) t23(35X 56X) t24(25X 36X) t25(PuH StH) +t31(53X 75X) t32(53X 65X) t33(WeX PuX) t34(23X 35X) t35(WeH PuH) +t41(52X 73X) t42(52X 63X) t43(32X 53X) t44(MeX WeX) t45(MeH WeH) +t51(PuL SuL) t52(PuL StL) t53(WeL PuL) t54(MeL WeL) t55(HiZ HiZ) +a = z b = x en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(PuX SuX) t12(PuX 67X) t13(35X 57X) t14(25X 37X) t15(PuH SuH) +t21(PuX 76X) t22(PuX StX) t23(35X 56X) t24(25X 36X) t25(PuH StH) +t31(53X 75X) t32(53X 65X) t33(WeX PuX) t34(23X 35X) t35(WeH PuH) +t41(52X 73X) t42(52X 63X) t43(32X 53X) t44(MeX WeX) t45(MeH WeH) +t51(PuL SuL) t52(PuL StL) t53(WeL PuL) t54(MeL WeL) t55(HiZ HiZ) +a = z b = x en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(PuX SuX) t12(PuX 67X) t13(35X 57X) t14(25X 37X) t15(PuH SuH) +t21(PuX 76X) t22(PuX StX) t23(35X 56X) t24(25X 36X) t25(PuH StH) +t31(53X 75X) t32(53X 65X) t33(WeX PuX) t34(23X 35X) t35(WeH PuH) +t41(52X 73X) t42(52X 63X) t43(32X 53X) t44(MeX WeX) t45(MeH WeH) +t51(PuL SuL) t52(PuL StL) t53(WeL PuL) t54(MeL WeL) t55(HiZ HiZ) +a = z b = x en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ SuX) t12(HiZ 67X) t13(HiZ 57X) t14(HiZ 37X) t15(HiZ SuH) +t21(HiZ 76X) t22(HiZ StX) t23(HiZ 56X) t24(HiZ 36X) t25(HiZ StH) +t31(HiZ 75X) t32(HiZ 65X) t33(HiZ PuX) t34(HiZ 35X) t35(HiZ PuH) +t41(HiZ 73X) t42(HiZ 63X) t43(HiZ 53X) t44(HiZ WeX) t45(HiZ WeH) +t51(HiZ SuL) t52(HiZ StL) t53(HiZ PuL) t54(HiZ WeL) t55(HiZ HiZ) +a = x b = x en = z +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = x en = x +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = x en = 0 +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = x en = 1 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = 0 b = x en = z +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 SuX) t12(St0 67X) t13(PuX 57X) t14(35X 37X) t15(PuH SuH) +t21(Su0 76X) t22(St0 StX) t23(PuX 56X) t24(35X 36X) t25(PuH StH) +t31(Su0 75X) t32(St0 65X) t33(Pu0 PuX) t34(WeX 35X) t35(WeH PuH) +t41(Su0 73X) t42(St0 63X) t43(Pu0 53X) t44(We0 WeX) t45(MeH WeH) +t51(Su0 SuL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = x en = x +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 SuX) t12(St0 67X) t13(PuX 57X) t14(35X 37X) t15(PuH SuH) +t21(Su0 76X) t22(St0 StX) t23(PuX 56X) t24(35X 36X) t25(PuH StH) +t31(Su0 75X) t32(St0 65X) t33(Pu0 PuX) t34(WeX 35X) t35(WeH PuH) +t41(Su0 73X) t42(St0 63X) t43(Pu0 53X) t44(We0 WeX) t45(MeH WeH) +t51(Su0 SuL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = x en = 0 +a1(Su0) a2(Pu0) a3(We0) a4(Me0) a5(Sm0) a6(Sm0) a7(Sm0) +t11(Su0 SuX) t12(St0 67X) t13(PuX 57X) t14(35X 37X) t15(PuH SuH) +t21(Su0 76X) t22(St0 StX) t23(PuX 56X) t24(35X 36X) t25(PuH StH) +t31(Su0 75X) t32(St0 65X) t33(Pu0 PuX) t34(WeX 35X) t35(WeH PuH) +t41(Su0 750) t42(St0 650) t43(Pu0 53X) t44(We0 WeX) t45(MeH WeH) +t51(Su0 750) t52(St0 650) t53(Pu0 530) t54(We0 320) t55(HiZ HiZ) +a = 0 b = x en = 1 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 SuX) t12(St0 67X) t13(Pu0 57X) t14(We0 37X) t15(HiZ SuH) +t21(Su0 76X) t22(St0 StX) t23(Pu0 56X) t24(We0 36X) t25(HiZ StH) +t31(Su0 75X) t32(St0 65X) t33(Pu0 PuX) t34(We0 35X) t35(HiZ PuH) +t41(Su0 73X) t42(St0 63X) t43(Pu0 53X) t44(We0 WeX) t45(HiZ WeH) +t51(Su0 SuL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 1 b = x en = z +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 57X) t14(Su1 37X) t15(Su1 SuH) +t21(St1 76X) t22(St1 StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(PuX 75X) t32(PuX 65X) t33(Pu1 PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(53X 73X) t42(53X 63X) t43(WeX 53X) t44(We1 WeX) t45(We1 WeH) +t51(PuL SuL) t52(PuL StL) t53(WeL PuL) t54(MeL WeL) t55(HiZ HiZ) +a = 1 b = x en = x +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 57X) t14(Su1 37X) t15(Su1 SuH) +t21(St1 76X) t22(St1 StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(PuX 75X) t32(PuX 65X) t33(Pu1 PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(53X 73X) t42(53X 63X) t43(WeX 53X) t44(We1 WeX) t45(We1 WeH) +t51(PuL SuL) t52(PuL StL) t53(WeL PuL) t54(MeL WeL) t55(HiZ HiZ) +a = 1 b = x en = 0 +a1(Su1) a2(Pu1) a3(We1) a4(Me1) a5(Sm1) a6(Sm1) a7(Sm1) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 57X) t14(Su1 751) t15(Su1 751) +t21(St1 76X) t22(St1 StX) t23(St1 56X) t24(St1 651) t25(St1 651) +t31(PuX 75X) t32(PuX 65X) t33(Pu1 PuX) t34(Pu1 35X) t35(Pu1 531) +t41(53X 73X) t42(53X 63X) t43(WeX 53X) t44(We1 WeX) t45(We1 321) +t51(PuL SuL) t52(PuL StL) t53(WeL PuL) t54(MeL WeL) t55(HiZ HiZ) +a = 1 b = x en = 1 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 57X) t14(Su1 37X) t15(Su1 SuH) +t21(St1 76X) t22(St1 StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(Pu1 75X) t32(Pu1 65X) t33(Pu1 PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(We1 73X) t42(We1 63X) t43(We1 53X) t44(We1 WeX) t45(We1 WeH) +t51(HiZ SuL) t52(HiZ StL) t53(HiZ PuL) t54(HiZ WeL) t55(HiZ HiZ) +a = z b = 0 en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(PuL Su0) t12(PuL St0) t13(WeL Pu0) t14(MeL We0) t15(HiZ HiZ) +t21(PuL Su0) t22(PuL St0) t23(WeL Pu0) t24(MeL We0) t25(HiZ HiZ) +t31(PuL Su0) t32(PuL St0) t33(WeL Pu0) t34(MeL We0) t35(HiZ HiZ) +t41(PuL Su0) t42(PuL St0) t43(WeL Pu0) t44(MeL We0) t45(HiZ HiZ) +t51(PuL Su0) t52(PuL St0) t53(WeL Pu0) t54(MeL We0) t55(HiZ HiZ) +a = z b = 0 en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(PuL Su0) t12(PuL St0) t13(WeL Pu0) t14(MeL We0) t15(HiZ HiZ) +t21(PuL Su0) t22(PuL St0) t23(WeL Pu0) t24(MeL We0) t25(HiZ HiZ) +t31(PuL Su0) t32(PuL St0) t33(WeL Pu0) t34(MeL We0) t35(HiZ HiZ) +t41(PuL Su0) t42(PuL St0) t43(WeL Pu0) t44(MeL We0) t45(HiZ HiZ) +t51(PuL Su0) t52(PuL St0) t53(WeL Pu0) t54(MeL We0) t55(HiZ HiZ) +a = z b = 0 en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Pu0 Su0) t12(Pu0 St0) t13(We0 Pu0) t14(Me0 We0) t15(HiZ HiZ) +t21(Pu0 Su0) t22(Pu0 St0) t23(We0 Pu0) t24(Me0 We0) t25(HiZ HiZ) +t31(Pu0 Su0) t32(Pu0 St0) t33(We0 Pu0) t34(Me0 We0) t35(HiZ HiZ) +t41(Pu0 Su0) t42(Pu0 St0) t43(We0 Pu0) t44(Me0 We0) t45(HiZ HiZ) +t51(Pu0 Su0) t52(Pu0 St0) t53(We0 Pu0) t54(Me0 We0) t55(HiZ HiZ) +a = z b = 0 en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ Su0) t12(HiZ St0) t13(HiZ Pu0) t14(HiZ We0) t15(HiZ HiZ) +t21(HiZ Su0) t22(HiZ St0) t23(HiZ Pu0) t24(HiZ We0) t25(HiZ HiZ) +t31(HiZ Su0) t32(HiZ St0) t33(HiZ Pu0) t34(HiZ We0) t35(HiZ HiZ) +t41(HiZ Su0) t42(HiZ St0) t43(HiZ Pu0) t44(HiZ We0) t45(HiZ HiZ) +t51(HiZ Su0) t52(HiZ St0) t53(HiZ Pu0) t54(HiZ We0) t55(HiZ HiZ) +a = x b = 0 en = z +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX Su0) t12(67X St0) t13(57X PuX) t14(37X 35X) t15(SuH PuH) +t21(76X Su0) t22(StX St0) t23(56X PuX) t24(36X 35X) t25(StH PuH) +t31(75X Su0) t32(65X St0) t33(PuX Pu0) t34(35X WeX) t35(PuH WeH) +t41(73X Su0) t42(63X St0) t43(53X Pu0) t44(WeX We0) t45(WeH MeH) +t51(SuL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = x b = 0 en = x +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX Su0) t12(67X St0) t13(57X PuX) t14(37X 35X) t15(SuH PuH) +t21(76X Su0) t22(StX St0) t23(56X PuX) t24(36X 35X) t25(StH PuH) +t31(75X Su0) t32(65X St0) t33(PuX Pu0) t34(35X WeX) t35(PuH WeH) +t41(73X Su0) t42(63X St0) t43(53X Pu0) t44(WeX We0) t45(WeH MeH) +t51(SuL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = x b = 0 en = 0 +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX Su0) t12(67X St0) t13(57X PuX) t14(37X 35X) t15(SuH PuH) +t21(76X Su0) t22(StX St0) t23(56X PuX) t24(36X 35X) t25(StH PuH) +t31(75X Su0) t32(65X St0) t33(PuX Pu0) t34(35X WeX) t35(PuH WeH) +t41(750 Su0) t42(650 St0) t43(53X Pu0) t44(WeX We0) t45(WeH MeH) +t51(750 Su0) t52(650 St0) t53(530 Pu0) t54(320 We0) t55(HiZ HiZ) +a = x b = 0 en = 1 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX Su0) t12(67X St0) t13(57X Pu0) t14(37X We0) t15(SuH HiZ) +t21(76X Su0) t22(StX St0) t23(56X Pu0) t24(36X We0) t25(StH HiZ) +t31(75X Su0) t32(65X St0) t33(PuX Pu0) t34(35X We0) t35(PuH HiZ) +t41(73X Su0) t42(63X St0) t43(53X Pu0) t44(WeX We0) t45(WeH HiZ) +t51(SuL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = 0 b = 0 en = z +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = 0 en = x +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = 0 en = 0 +a1(Su0) a2(Pu0) a3(We0) a4(Me0) a5(Sm0) a6(Sm0) a7(Sm0) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = 0 en = 1 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 1 b = 0 en = z +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 Su0) t12(Su1 St0) t13(Su1 PuX) t14(Su1 35X) t15(Su1 PuH) +t21(St1 Su0) t22(St1 St0) t23(St1 PuX) t24(St1 35X) t25(St1 PuH) +t31(PuX Su0) t32(PuX St0) t33(Pu1 Pu0) t34(Pu1 WeX) t35(Pu1 WeH) +t41(53X Su0) t42(53X St0) t43(WeX Pu0) t44(We1 We0) t45(We1 MeH) +t51(PuL Su0) t52(PuL St0) t53(WeL Pu0) t54(MeL We0) t55(HiZ HiZ) +a = 1 b = 0 en = x +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 Su0) t12(Su1 St0) t13(Su1 PuX) t14(Su1 35X) t15(Su1 PuH) +t21(St1 Su0) t22(St1 St0) t23(St1 PuX) t24(St1 35X) t25(St1 PuH) +t31(PuX Su0) t32(PuX St0) t33(Pu1 Pu0) t34(Pu1 WeX) t35(Pu1 WeH) +t41(53X Su0) t42(53X St0) t43(WeX Pu0) t44(We1 We0) t45(We1 MeH) +t51(PuL Su0) t52(PuL St0) t53(WeL Pu0) t54(MeL We0) t55(HiZ HiZ) +a = 1 b = 0 en = 0 +a1(Su1) a2(Pu1) a3(We1) a4(Me1) a5(Sm1) a6(Sm1) a7(Sm1) +t11(Su1 Su0) t12(Su1 St0) t13(Su1 PuX) t14(Su1 Pu1) t15(Su1 Pu1) +t21(St1 Su0) t22(St1 St0) t23(St1 PuX) t24(St1 Pu1) t25(St1 Pu1) +t31(PuX Su0) t32(PuX St0) t33(Pu1 Pu0) t34(Pu1 WeX) t35(Pu1 We1) +t41(Pu0 Su0) t42(Pu0 St0) t43(WeX Pu0) t44(We1 We0) t45(We1 Me1) +t51(Pu0 Su0) t52(Pu0 St0) t53(We0 Pu0) t54(Me0 We0) t55(HiZ HiZ) +a = 1 b = 0 en = 1 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 Su0) t12(Su1 St0) t13(Su1 Pu0) t14(Su1 We0) t15(Su1 HiZ) +t21(St1 Su0) t22(St1 St0) t23(St1 Pu0) t24(St1 We0) t25(St1 HiZ) +t31(Pu1 Su0) t32(Pu1 St0) t33(Pu1 Pu0) t34(Pu1 We0) t35(Pu1 HiZ) +t41(We1 Su0) t42(We1 St0) t43(We1 Pu0) t44(We1 We0) t45(We1 HiZ) +t51(HiZ Su0) t52(HiZ St0) t53(HiZ Pu0) t54(HiZ We0) t55(HiZ HiZ) +a = z b = 1 en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(PuH Su1) t12(PuH Su1) t13(PuH Su1) t14(PuH Su1) t15(PuH Su1) +t21(PuH St1) t22(PuH St1) t23(PuH St1) t24(PuH St1) t25(PuH St1) +t31(WeH Pu1) t32(WeH Pu1) t33(WeH Pu1) t34(WeH Pu1) t35(WeH Pu1) +t41(MeH We1) t42(MeH We1) t43(MeH We1) t44(MeH We1) t45(MeH We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = 1 en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(PuH Su1) t12(PuH Su1) t13(PuH Su1) t14(PuH Su1) t15(PuH Su1) +t21(PuH St1) t22(PuH St1) t23(PuH St1) t24(PuH St1) t25(PuH St1) +t31(WeH Pu1) t32(WeH Pu1) t33(WeH Pu1) t34(WeH Pu1) t35(WeH Pu1) +t41(MeH We1) t42(MeH We1) t43(MeH We1) t44(MeH We1) t45(MeH We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = 1 en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Pu1 Su1) t12(Pu1 Su1) t13(Pu1 Su1) t14(Pu1 Su1) t15(Pu1 Su1) +t21(Pu1 St1) t22(Pu1 St1) t23(Pu1 St1) t24(Pu1 St1) t25(Pu1 St1) +t31(We1 Pu1) t32(We1 Pu1) t33(We1 Pu1) t34(We1 Pu1) t35(We1 Pu1) +t41(Me1 We1) t42(Me1 We1) t43(Me1 We1) t44(Me1 We1) t45(Me1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = 1 en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ Su1) t12(HiZ Su1) t13(HiZ Su1) t14(HiZ Su1) t15(HiZ Su1) +t21(HiZ St1) t22(HiZ St1) t23(HiZ St1) t24(HiZ St1) t25(HiZ St1) +t31(HiZ Pu1) t32(HiZ Pu1) t33(HiZ Pu1) t34(HiZ Pu1) t35(HiZ Pu1) +t41(HiZ We1) t42(HiZ We1) t43(HiZ We1) t44(HiZ We1) t45(HiZ We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = x b = 1 en = z +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX Su1) t12(67X Su1) t13(57X Su1) t14(37X Su1) t15(SuH Su1) +t21(76X St1) t22(StX St1) t23(56X St1) t24(36X St1) t25(StH St1) +t31(75X PuX) t32(65X PuX) t33(PuX Pu1) t34(35X Pu1) t35(PuH Pu1) +t41(73X 53X) t42(63X 53X) t43(53X WeX) t44(WeX We1) t45(WeH We1) +t51(SuL PuL) t52(StL PuL) t53(PuL WeL) t54(WeL MeL) t55(HiZ HiZ) +a = x b = 1 en = x +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX Su1) t12(67X Su1) t13(57X Su1) t14(37X Su1) t15(SuH Su1) +t21(76X St1) t22(StX St1) t23(56X St1) t24(36X St1) t25(StH St1) +t31(75X PuX) t32(65X PuX) t33(PuX Pu1) t34(35X Pu1) t35(PuH Pu1) +t41(73X 53X) t42(63X 53X) t43(53X WeX) t44(WeX We1) t45(WeH We1) +t51(SuL PuL) t52(StL PuL) t53(PuL WeL) t54(WeL MeL) t55(HiZ HiZ) +a = x b = 1 en = 0 +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX Su1) t12(67X Su1) t13(57X Su1) t14(751 Su1) t15(751 Su1) +t21(76X St1) t22(StX St1) t23(56X St1) t24(651 St1) t25(651 St1) +t31(75X PuX) t32(65X PuX) t33(PuX Pu1) t34(35X Pu1) t35(531 Pu1) +t41(73X 53X) t42(63X 53X) t43(53X WeX) t44(WeX We1) t45(321 We1) +t51(SuL PuL) t52(StL PuL) t53(PuL WeL) t54(WeL MeL) t55(HiZ HiZ) +a = x b = 1 en = 1 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX Su1) t12(67X Su1) t13(57X Su1) t14(37X Su1) t15(SuH Su1) +t21(76X St1) t22(StX St1) t23(56X St1) t24(36X St1) t25(StH St1) +t31(75X Pu1) t32(65X Pu1) t33(PuX Pu1) t34(35X Pu1) t35(PuH Pu1) +t41(73X We1) t42(63X We1) t43(53X We1) t44(WeX We1) t45(WeH We1) +t51(SuL HiZ) t52(StL HiZ) t53(PuL HiZ) t54(WeL HiZ) t55(HiZ HiZ) +a = 0 b = 1 en = z +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 Su1) t12(St0 Su1) t13(PuX Su1) t14(35X Su1) t15(PuH Su1) +t21(Su0 St1) t22(St0 St1) t23(PuX St1) t24(35X St1) t25(PuH St1) +t31(Su0 PuX) t32(St0 PuX) t33(Pu0 Pu1) t34(WeX Pu1) t35(WeH Pu1) +t41(Su0 53X) t42(St0 53X) t43(Pu0 WeX) t44(We0 We1) t45(MeH We1) +t51(Su0 PuL) t52(St0 PuL) t53(Pu0 WeL) t54(We0 MeL) t55(HiZ HiZ) +a = 0 b = 1 en = x +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 Su1) t12(St0 Su1) t13(PuX Su1) t14(35X Su1) t15(PuH Su1) +t21(Su0 St1) t22(St0 St1) t23(PuX St1) t24(35X St1) t25(PuH St1) +t31(Su0 PuX) t32(St0 PuX) t33(Pu0 Pu1) t34(WeX Pu1) t35(WeH Pu1) +t41(Su0 53X) t42(St0 53X) t43(Pu0 WeX) t44(We0 We1) t45(MeH We1) +t51(Su0 PuL) t52(St0 PuL) t53(Pu0 WeL) t54(We0 MeL) t55(HiZ HiZ) +a = 0 b = 1 en = 0 +a1(Su0) a2(Pu0) a3(We0) a4(Me0) a5(Sm0) a6(Sm0) a7(Sm0) +t11(Su0 Su1) t12(St0 Su1) t13(PuX Su1) t14(Pu1 Su1) t15(Pu1 Su1) +t21(Su0 St1) t22(St0 St1) t23(PuX St1) t24(Pu1 St1) t25(Pu1 St1) +t31(Su0 PuX) t32(St0 PuX) t33(Pu0 Pu1) t34(WeX Pu1) t35(We1 Pu1) +t41(Su0 Pu0) t42(St0 Pu0) t43(Pu0 WeX) t44(We0 We1) t45(Me1 We1) +t51(Su0 Pu0) t52(St0 Pu0) t53(Pu0 We0) t54(We0 Me0) t55(HiZ HiZ) +a = 0 b = 1 en = 1 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 Su1) t12(St0 Su1) t13(Pu0 Su1) t14(We0 Su1) t15(HiZ Su1) +t21(Su0 St1) t22(St0 St1) t23(Pu0 St1) t24(We0 St1) t25(HiZ St1) +t31(Su0 Pu1) t32(St0 Pu1) t33(Pu0 Pu1) t34(We0 Pu1) t35(HiZ Pu1) +t41(Su0 We1) t42(St0 We1) t43(Pu0 We1) t44(We0 We1) t45(HiZ We1) +t51(Su0 HiZ) t52(St0 HiZ) t53(Pu0 HiZ) t54(We0 HiZ) t55(HiZ HiZ) +a = 1 b = 1 en = z +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = 1 en = x +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = 1 en = 0 +a1(Su1) a2(Pu1) a3(We1) a4(Me1) a5(Sm1) a6(Sm1) a7(Sm1) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = 1 en = 1 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) diff --git a/ivtest/gold/rtranif1.gold b/ivtest/gold/rtranif1.gold new file mode 100644 index 000000000..7ead1e414 --- /dev/null +++ b/ivtest/gold/rtranif1.gold @@ -0,0 +1,448 @@ +a = z b = z en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = z en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = z en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = z en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = x b = z en = z +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX PuX) t12(67X PuX) t13(57X 35X) t14(37X 25X) t15(SuH PuH) +t21(76X PuX) t22(StX PuX) t23(56X 35X) t24(36X 25X) t25(StH PuH) +t31(75X 53X) t32(65X 53X) t33(PuX WeX) t34(35X 23X) t35(PuH WeH) +t41(73X 52X) t42(63X 52X) t43(53X 32X) t44(WeX MeX) t45(WeH MeH) +t51(SuL PuL) t52(StL PuL) t53(PuL WeL) t54(WeL MeL) t55(HiZ HiZ) +a = x b = z en = x +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX PuX) t12(67X PuX) t13(57X 35X) t14(37X 25X) t15(SuH PuH) +t21(76X PuX) t22(StX PuX) t23(56X 35X) t24(36X 25X) t25(StH PuH) +t31(75X 53X) t32(65X 53X) t33(PuX WeX) t34(35X 23X) t35(PuH WeH) +t41(73X 52X) t42(63X 52X) t43(53X 32X) t44(WeX MeX) t45(WeH MeH) +t51(SuL PuL) t52(StL PuL) t53(PuL WeL) t54(WeL MeL) t55(HiZ HiZ) +a = x b = z en = 0 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX HiZ) t12(67X HiZ) t13(57X HiZ) t14(37X HiZ) t15(SuH HiZ) +t21(76X HiZ) t22(StX HiZ) t23(56X HiZ) t24(36X HiZ) t25(StH HiZ) +t31(75X HiZ) t32(65X HiZ) t33(PuX HiZ) t34(35X HiZ) t35(PuH HiZ) +t41(73X HiZ) t42(63X HiZ) t43(53X HiZ) t44(WeX HiZ) t45(WeH HiZ) +t51(SuL HiZ) t52(StL HiZ) t53(PuL HiZ) t54(WeL HiZ) t55(HiZ HiZ) +a = x b = z en = 1 +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX PuX) t12(67X PuX) t13(57X 35X) t14(37X 25X) t15(SuH PuH) +t21(76X PuX) t22(StX PuX) t23(56X 35X) t24(36X 25X) t25(StH PuH) +t31(75X 53X) t32(65X 53X) t33(PuX WeX) t34(35X 23X) t35(PuH WeH) +t41(73X 52X) t42(63X 52X) t43(53X 32X) t44(WeX MeX) t45(WeH MeH) +t51(SuL PuL) t52(StL PuL) t53(PuL WeL) t54(WeL MeL) t55(HiZ HiZ) +a = 0 b = z en = z +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 PuL) t12(St0 PuL) t13(Pu0 WeL) t14(We0 MeL) t15(HiZ HiZ) +t21(Su0 PuL) t22(St0 PuL) t23(Pu0 WeL) t24(We0 MeL) t25(HiZ HiZ) +t31(Su0 PuL) t32(St0 PuL) t33(Pu0 WeL) t34(We0 MeL) t35(HiZ HiZ) +t41(Su0 PuL) t42(St0 PuL) t43(Pu0 WeL) t44(We0 MeL) t45(HiZ HiZ) +t51(Su0 PuL) t52(St0 PuL) t53(Pu0 WeL) t54(We0 MeL) t55(HiZ HiZ) +a = 0 b = z en = x +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 PuL) t12(St0 PuL) t13(Pu0 WeL) t14(We0 MeL) t15(HiZ HiZ) +t21(Su0 PuL) t22(St0 PuL) t23(Pu0 WeL) t24(We0 MeL) t25(HiZ HiZ) +t31(Su0 PuL) t32(St0 PuL) t33(Pu0 WeL) t34(We0 MeL) t35(HiZ HiZ) +t41(Su0 PuL) t42(St0 PuL) t43(Pu0 WeL) t44(We0 MeL) t45(HiZ HiZ) +t51(Su0 PuL) t52(St0 PuL) t53(Pu0 WeL) t54(We0 MeL) t55(HiZ HiZ) +a = 0 b = z en = 0 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 HiZ) t12(St0 HiZ) t13(Pu0 HiZ) t14(We0 HiZ) t15(HiZ HiZ) +t21(Su0 HiZ) t22(St0 HiZ) t23(Pu0 HiZ) t24(We0 HiZ) t25(HiZ HiZ) +t31(Su0 HiZ) t32(St0 HiZ) t33(Pu0 HiZ) t34(We0 HiZ) t35(HiZ HiZ) +t41(Su0 HiZ) t42(St0 HiZ) t43(Pu0 HiZ) t44(We0 HiZ) t45(HiZ HiZ) +t51(Su0 HiZ) t52(St0 HiZ) t53(Pu0 HiZ) t54(We0 HiZ) t55(HiZ HiZ) +a = 0 b = z en = 1 +a1(Su0) a2(Pu0) a3(We0) a4(Me0) a5(Sm0) a6(Sm0) a7(Sm0) +t11(Su0 Pu0) t12(St0 Pu0) t13(Pu0 We0) t14(We0 Me0) t15(HiZ HiZ) +t21(Su0 Pu0) t22(St0 Pu0) t23(Pu0 We0) t24(We0 Me0) t25(HiZ HiZ) +t31(Su0 Pu0) t32(St0 Pu0) t33(Pu0 We0) t34(We0 Me0) t35(HiZ HiZ) +t41(Su0 Pu0) t42(St0 Pu0) t43(Pu0 We0) t44(We0 Me0) t45(HiZ HiZ) +t51(Su0 Pu0) t52(St0 Pu0) t53(Pu0 We0) t54(We0 Me0) t55(HiZ HiZ) +a = 1 b = z en = z +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 PuH) t12(Su1 PuH) t13(Su1 PuH) t14(Su1 PuH) t15(Su1 PuH) +t21(St1 PuH) t22(St1 PuH) t23(St1 PuH) t24(St1 PuH) t25(St1 PuH) +t31(Pu1 WeH) t32(Pu1 WeH) t33(Pu1 WeH) t34(Pu1 WeH) t35(Pu1 WeH) +t41(We1 MeH) t42(We1 MeH) t43(We1 MeH) t44(We1 MeH) t45(We1 MeH) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = z en = x +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 PuH) t12(Su1 PuH) t13(Su1 PuH) t14(Su1 PuH) t15(Su1 PuH) +t21(St1 PuH) t22(St1 PuH) t23(St1 PuH) t24(St1 PuH) t25(St1 PuH) +t31(Pu1 WeH) t32(Pu1 WeH) t33(Pu1 WeH) t34(Pu1 WeH) t35(Pu1 WeH) +t41(We1 MeH) t42(We1 MeH) t43(We1 MeH) t44(We1 MeH) t45(We1 MeH) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = z en = 0 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 HiZ) t12(Su1 HiZ) t13(Su1 HiZ) t14(Su1 HiZ) t15(Su1 HiZ) +t21(St1 HiZ) t22(St1 HiZ) t23(St1 HiZ) t24(St1 HiZ) t25(St1 HiZ) +t31(Pu1 HiZ) t32(Pu1 HiZ) t33(Pu1 HiZ) t34(Pu1 HiZ) t35(Pu1 HiZ) +t41(We1 HiZ) t42(We1 HiZ) t43(We1 HiZ) t44(We1 HiZ) t45(We1 HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = z en = 1 +a1(Su1) a2(Pu1) a3(We1) a4(Me1) a5(Sm1) a6(Sm1) a7(Sm1) +t11(Su1 Pu1) t12(Su1 Pu1) t13(Su1 Pu1) t14(Su1 Pu1) t15(Su1 Pu1) +t21(St1 Pu1) t22(St1 Pu1) t23(St1 Pu1) t24(St1 Pu1) t25(St1 Pu1) +t31(Pu1 We1) t32(Pu1 We1) t33(Pu1 We1) t34(Pu1 We1) t35(Pu1 We1) +t41(We1 Me1) t42(We1 Me1) t43(We1 Me1) t44(We1 Me1) t45(We1 Me1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = x en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(PuX SuX) t12(PuX 67X) t13(35X 57X) t14(25X 37X) t15(PuH SuH) +t21(PuX 76X) t22(PuX StX) t23(35X 56X) t24(25X 36X) t25(PuH StH) +t31(53X 75X) t32(53X 65X) t33(WeX PuX) t34(23X 35X) t35(WeH PuH) +t41(52X 73X) t42(52X 63X) t43(32X 53X) t44(MeX WeX) t45(MeH WeH) +t51(PuL SuL) t52(PuL StL) t53(WeL PuL) t54(MeL WeL) t55(HiZ HiZ) +a = z b = x en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(PuX SuX) t12(PuX 67X) t13(35X 57X) t14(25X 37X) t15(PuH SuH) +t21(PuX 76X) t22(PuX StX) t23(35X 56X) t24(25X 36X) t25(PuH StH) +t31(53X 75X) t32(53X 65X) t33(WeX PuX) t34(23X 35X) t35(WeH PuH) +t41(52X 73X) t42(52X 63X) t43(32X 53X) t44(MeX WeX) t45(MeH WeH) +t51(PuL SuL) t52(PuL StL) t53(WeL PuL) t54(MeL WeL) t55(HiZ HiZ) +a = z b = x en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ SuX) t12(HiZ 67X) t13(HiZ 57X) t14(HiZ 37X) t15(HiZ SuH) +t21(HiZ 76X) t22(HiZ StX) t23(HiZ 56X) t24(HiZ 36X) t25(HiZ StH) +t31(HiZ 75X) t32(HiZ 65X) t33(HiZ PuX) t34(HiZ 35X) t35(HiZ PuH) +t41(HiZ 73X) t42(HiZ 63X) t43(HiZ 53X) t44(HiZ WeX) t45(HiZ WeH) +t51(HiZ SuL) t52(HiZ StL) t53(HiZ PuL) t54(HiZ WeL) t55(HiZ HiZ) +a = z b = x en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(PuX SuX) t12(PuX 67X) t13(35X 57X) t14(25X 37X) t15(PuH SuH) +t21(PuX 76X) t22(PuX StX) t23(35X 56X) t24(25X 36X) t25(PuH StH) +t31(53X 75X) t32(53X 65X) t33(WeX PuX) t34(23X 35X) t35(WeH PuH) +t41(52X 73X) t42(52X 63X) t43(32X 53X) t44(MeX WeX) t45(MeH WeH) +t51(PuL SuL) t52(PuL StL) t53(WeL PuL) t54(MeL WeL) t55(HiZ HiZ) +a = x b = x en = z +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = x en = x +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = x en = 0 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = x en = 1 +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = 0 b = x en = z +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 SuX) t12(St0 67X) t13(PuX 57X) t14(35X 37X) t15(PuH SuH) +t21(Su0 76X) t22(St0 StX) t23(PuX 56X) t24(35X 36X) t25(PuH StH) +t31(Su0 75X) t32(St0 65X) t33(Pu0 PuX) t34(WeX 35X) t35(WeH PuH) +t41(Su0 73X) t42(St0 63X) t43(Pu0 53X) t44(We0 WeX) t45(MeH WeH) +t51(Su0 SuL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = x en = x +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 SuX) t12(St0 67X) t13(PuX 57X) t14(35X 37X) t15(PuH SuH) +t21(Su0 76X) t22(St0 StX) t23(PuX 56X) t24(35X 36X) t25(PuH StH) +t31(Su0 75X) t32(St0 65X) t33(Pu0 PuX) t34(WeX 35X) t35(WeH PuH) +t41(Su0 73X) t42(St0 63X) t43(Pu0 53X) t44(We0 WeX) t45(MeH WeH) +t51(Su0 SuL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = x en = 0 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 SuX) t12(St0 67X) t13(Pu0 57X) t14(We0 37X) t15(HiZ SuH) +t21(Su0 76X) t22(St0 StX) t23(Pu0 56X) t24(We0 36X) t25(HiZ StH) +t31(Su0 75X) t32(St0 65X) t33(Pu0 PuX) t34(We0 35X) t35(HiZ PuH) +t41(Su0 73X) t42(St0 63X) t43(Pu0 53X) t44(We0 WeX) t45(HiZ WeH) +t51(Su0 SuL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = x en = 1 +a1(Su0) a2(Pu0) a3(We0) a4(Me0) a5(Sm0) a6(Sm0) a7(Sm0) +t11(Su0 SuX) t12(St0 67X) t13(PuX 57X) t14(35X 37X) t15(PuH SuH) +t21(Su0 76X) t22(St0 StX) t23(PuX 56X) t24(35X 36X) t25(PuH StH) +t31(Su0 75X) t32(St0 65X) t33(Pu0 PuX) t34(WeX 35X) t35(WeH PuH) +t41(Su0 750) t42(St0 650) t43(Pu0 53X) t44(We0 WeX) t45(MeH WeH) +t51(Su0 750) t52(St0 650) t53(Pu0 530) t54(We0 320) t55(HiZ HiZ) +a = 1 b = x en = z +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 57X) t14(Su1 37X) t15(Su1 SuH) +t21(St1 76X) t22(St1 StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(PuX 75X) t32(PuX 65X) t33(Pu1 PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(53X 73X) t42(53X 63X) t43(WeX 53X) t44(We1 WeX) t45(We1 WeH) +t51(PuL SuL) t52(PuL StL) t53(WeL PuL) t54(MeL WeL) t55(HiZ HiZ) +a = 1 b = x en = x +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 57X) t14(Su1 37X) t15(Su1 SuH) +t21(St1 76X) t22(St1 StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(PuX 75X) t32(PuX 65X) t33(Pu1 PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(53X 73X) t42(53X 63X) t43(WeX 53X) t44(We1 WeX) t45(We1 WeH) +t51(PuL SuL) t52(PuL StL) t53(WeL PuL) t54(MeL WeL) t55(HiZ HiZ) +a = 1 b = x en = 0 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 57X) t14(Su1 37X) t15(Su1 SuH) +t21(St1 76X) t22(St1 StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(Pu1 75X) t32(Pu1 65X) t33(Pu1 PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(We1 73X) t42(We1 63X) t43(We1 53X) t44(We1 WeX) t45(We1 WeH) +t51(HiZ SuL) t52(HiZ StL) t53(HiZ PuL) t54(HiZ WeL) t55(HiZ HiZ) +a = 1 b = x en = 1 +a1(Su1) a2(Pu1) a3(We1) a4(Me1) a5(Sm1) a6(Sm1) a7(Sm1) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 57X) t14(Su1 751) t15(Su1 751) +t21(St1 76X) t22(St1 StX) t23(St1 56X) t24(St1 651) t25(St1 651) +t31(PuX 75X) t32(PuX 65X) t33(Pu1 PuX) t34(Pu1 35X) t35(Pu1 531) +t41(53X 73X) t42(53X 63X) t43(WeX 53X) t44(We1 WeX) t45(We1 321) +t51(PuL SuL) t52(PuL StL) t53(WeL PuL) t54(MeL WeL) t55(HiZ HiZ) +a = z b = 0 en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(PuL Su0) t12(PuL St0) t13(WeL Pu0) t14(MeL We0) t15(HiZ HiZ) +t21(PuL Su0) t22(PuL St0) t23(WeL Pu0) t24(MeL We0) t25(HiZ HiZ) +t31(PuL Su0) t32(PuL St0) t33(WeL Pu0) t34(MeL We0) t35(HiZ HiZ) +t41(PuL Su0) t42(PuL St0) t43(WeL Pu0) t44(MeL We0) t45(HiZ HiZ) +t51(PuL Su0) t52(PuL St0) t53(WeL Pu0) t54(MeL We0) t55(HiZ HiZ) +a = z b = 0 en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(PuL Su0) t12(PuL St0) t13(WeL Pu0) t14(MeL We0) t15(HiZ HiZ) +t21(PuL Su0) t22(PuL St0) t23(WeL Pu0) t24(MeL We0) t25(HiZ HiZ) +t31(PuL Su0) t32(PuL St0) t33(WeL Pu0) t34(MeL We0) t35(HiZ HiZ) +t41(PuL Su0) t42(PuL St0) t43(WeL Pu0) t44(MeL We0) t45(HiZ HiZ) +t51(PuL Su0) t52(PuL St0) t53(WeL Pu0) t54(MeL We0) t55(HiZ HiZ) +a = z b = 0 en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ Su0) t12(HiZ St0) t13(HiZ Pu0) t14(HiZ We0) t15(HiZ HiZ) +t21(HiZ Su0) t22(HiZ St0) t23(HiZ Pu0) t24(HiZ We0) t25(HiZ HiZ) +t31(HiZ Su0) t32(HiZ St0) t33(HiZ Pu0) t34(HiZ We0) t35(HiZ HiZ) +t41(HiZ Su0) t42(HiZ St0) t43(HiZ Pu0) t44(HiZ We0) t45(HiZ HiZ) +t51(HiZ Su0) t52(HiZ St0) t53(HiZ Pu0) t54(HiZ We0) t55(HiZ HiZ) +a = z b = 0 en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Pu0 Su0) t12(Pu0 St0) t13(We0 Pu0) t14(Me0 We0) t15(HiZ HiZ) +t21(Pu0 Su0) t22(Pu0 St0) t23(We0 Pu0) t24(Me0 We0) t25(HiZ HiZ) +t31(Pu0 Su0) t32(Pu0 St0) t33(We0 Pu0) t34(Me0 We0) t35(HiZ HiZ) +t41(Pu0 Su0) t42(Pu0 St0) t43(We0 Pu0) t44(Me0 We0) t45(HiZ HiZ) +t51(Pu0 Su0) t52(Pu0 St0) t53(We0 Pu0) t54(Me0 We0) t55(HiZ HiZ) +a = x b = 0 en = z +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX Su0) t12(67X St0) t13(57X PuX) t14(37X 35X) t15(SuH PuH) +t21(76X Su0) t22(StX St0) t23(56X PuX) t24(36X 35X) t25(StH PuH) +t31(75X Su0) t32(65X St0) t33(PuX Pu0) t34(35X WeX) t35(PuH WeH) +t41(73X Su0) t42(63X St0) t43(53X Pu0) t44(WeX We0) t45(WeH MeH) +t51(SuL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = x b = 0 en = x +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX Su0) t12(67X St0) t13(57X PuX) t14(37X 35X) t15(SuH PuH) +t21(76X Su0) t22(StX St0) t23(56X PuX) t24(36X 35X) t25(StH PuH) +t31(75X Su0) t32(65X St0) t33(PuX Pu0) t34(35X WeX) t35(PuH WeH) +t41(73X Su0) t42(63X St0) t43(53X Pu0) t44(WeX We0) t45(WeH MeH) +t51(SuL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = x b = 0 en = 0 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX Su0) t12(67X St0) t13(57X Pu0) t14(37X We0) t15(SuH HiZ) +t21(76X Su0) t22(StX St0) t23(56X Pu0) t24(36X We0) t25(StH HiZ) +t31(75X Su0) t32(65X St0) t33(PuX Pu0) t34(35X We0) t35(PuH HiZ) +t41(73X Su0) t42(63X St0) t43(53X Pu0) t44(WeX We0) t45(WeH HiZ) +t51(SuL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = x b = 0 en = 1 +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX Su0) t12(67X St0) t13(57X PuX) t14(37X 35X) t15(SuH PuH) +t21(76X Su0) t22(StX St0) t23(56X PuX) t24(36X 35X) t25(StH PuH) +t31(75X Su0) t32(65X St0) t33(PuX Pu0) t34(35X WeX) t35(PuH WeH) +t41(750 Su0) t42(650 St0) t43(53X Pu0) t44(WeX We0) t45(WeH MeH) +t51(750 Su0) t52(650 St0) t53(530 Pu0) t54(320 We0) t55(HiZ HiZ) +a = 0 b = 0 en = z +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = 0 en = x +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = 0 en = 0 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = 0 en = 1 +a1(Su0) a2(Pu0) a3(We0) a4(Me0) a5(Sm0) a6(Sm0) a7(Sm0) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 1 b = 0 en = z +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 Su0) t12(Su1 St0) t13(Su1 PuX) t14(Su1 35X) t15(Su1 PuH) +t21(St1 Su0) t22(St1 St0) t23(St1 PuX) t24(St1 35X) t25(St1 PuH) +t31(PuX Su0) t32(PuX St0) t33(Pu1 Pu0) t34(Pu1 WeX) t35(Pu1 WeH) +t41(53X Su0) t42(53X St0) t43(WeX Pu0) t44(We1 We0) t45(We1 MeH) +t51(PuL Su0) t52(PuL St0) t53(WeL Pu0) t54(MeL We0) t55(HiZ HiZ) +a = 1 b = 0 en = x +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 Su0) t12(Su1 St0) t13(Su1 PuX) t14(Su1 35X) t15(Su1 PuH) +t21(St1 Su0) t22(St1 St0) t23(St1 PuX) t24(St1 35X) t25(St1 PuH) +t31(PuX Su0) t32(PuX St0) t33(Pu1 Pu0) t34(Pu1 WeX) t35(Pu1 WeH) +t41(53X Su0) t42(53X St0) t43(WeX Pu0) t44(We1 We0) t45(We1 MeH) +t51(PuL Su0) t52(PuL St0) t53(WeL Pu0) t54(MeL We0) t55(HiZ HiZ) +a = 1 b = 0 en = 0 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 Su0) t12(Su1 St0) t13(Su1 Pu0) t14(Su1 We0) t15(Su1 HiZ) +t21(St1 Su0) t22(St1 St0) t23(St1 Pu0) t24(St1 We0) t25(St1 HiZ) +t31(Pu1 Su0) t32(Pu1 St0) t33(Pu1 Pu0) t34(Pu1 We0) t35(Pu1 HiZ) +t41(We1 Su0) t42(We1 St0) t43(We1 Pu0) t44(We1 We0) t45(We1 HiZ) +t51(HiZ Su0) t52(HiZ St0) t53(HiZ Pu0) t54(HiZ We0) t55(HiZ HiZ) +a = 1 b = 0 en = 1 +a1(Su1) a2(Pu1) a3(We1) a4(Me1) a5(Sm1) a6(Sm1) a7(Sm1) +t11(Su1 Su0) t12(Su1 St0) t13(Su1 PuX) t14(Su1 Pu1) t15(Su1 Pu1) +t21(St1 Su0) t22(St1 St0) t23(St1 PuX) t24(St1 Pu1) t25(St1 Pu1) +t31(PuX Su0) t32(PuX St0) t33(Pu1 Pu0) t34(Pu1 WeX) t35(Pu1 We1) +t41(Pu0 Su0) t42(Pu0 St0) t43(WeX Pu0) t44(We1 We0) t45(We1 Me1) +t51(Pu0 Su0) t52(Pu0 St0) t53(We0 Pu0) t54(Me0 We0) t55(HiZ HiZ) +a = z b = 1 en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(PuH Su1) t12(PuH Su1) t13(PuH Su1) t14(PuH Su1) t15(PuH Su1) +t21(PuH St1) t22(PuH St1) t23(PuH St1) t24(PuH St1) t25(PuH St1) +t31(WeH Pu1) t32(WeH Pu1) t33(WeH Pu1) t34(WeH Pu1) t35(WeH Pu1) +t41(MeH We1) t42(MeH We1) t43(MeH We1) t44(MeH We1) t45(MeH We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = 1 en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(PuH Su1) t12(PuH Su1) t13(PuH Su1) t14(PuH Su1) t15(PuH Su1) +t21(PuH St1) t22(PuH St1) t23(PuH St1) t24(PuH St1) t25(PuH St1) +t31(WeH Pu1) t32(WeH Pu1) t33(WeH Pu1) t34(WeH Pu1) t35(WeH Pu1) +t41(MeH We1) t42(MeH We1) t43(MeH We1) t44(MeH We1) t45(MeH We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = 1 en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ Su1) t12(HiZ Su1) t13(HiZ Su1) t14(HiZ Su1) t15(HiZ Su1) +t21(HiZ St1) t22(HiZ St1) t23(HiZ St1) t24(HiZ St1) t25(HiZ St1) +t31(HiZ Pu1) t32(HiZ Pu1) t33(HiZ Pu1) t34(HiZ Pu1) t35(HiZ Pu1) +t41(HiZ We1) t42(HiZ We1) t43(HiZ We1) t44(HiZ We1) t45(HiZ We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = 1 en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Pu1 Su1) t12(Pu1 Su1) t13(Pu1 Su1) t14(Pu1 Su1) t15(Pu1 Su1) +t21(Pu1 St1) t22(Pu1 St1) t23(Pu1 St1) t24(Pu1 St1) t25(Pu1 St1) +t31(We1 Pu1) t32(We1 Pu1) t33(We1 Pu1) t34(We1 Pu1) t35(We1 Pu1) +t41(Me1 We1) t42(Me1 We1) t43(Me1 We1) t44(Me1 We1) t45(Me1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = x b = 1 en = z +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX Su1) t12(67X Su1) t13(57X Su1) t14(37X Su1) t15(SuH Su1) +t21(76X St1) t22(StX St1) t23(56X St1) t24(36X St1) t25(StH St1) +t31(75X PuX) t32(65X PuX) t33(PuX Pu1) t34(35X Pu1) t35(PuH Pu1) +t41(73X 53X) t42(63X 53X) t43(53X WeX) t44(WeX We1) t45(WeH We1) +t51(SuL PuL) t52(StL PuL) t53(PuL WeL) t54(WeL MeL) t55(HiZ HiZ) +a = x b = 1 en = x +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX Su1) t12(67X Su1) t13(57X Su1) t14(37X Su1) t15(SuH Su1) +t21(76X St1) t22(StX St1) t23(56X St1) t24(36X St1) t25(StH St1) +t31(75X PuX) t32(65X PuX) t33(PuX Pu1) t34(35X Pu1) t35(PuH Pu1) +t41(73X 53X) t42(63X 53X) t43(53X WeX) t44(WeX We1) t45(WeH We1) +t51(SuL PuL) t52(StL PuL) t53(PuL WeL) t54(WeL MeL) t55(HiZ HiZ) +a = x b = 1 en = 0 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX Su1) t12(67X Su1) t13(57X Su1) t14(37X Su1) t15(SuH Su1) +t21(76X St1) t22(StX St1) t23(56X St1) t24(36X St1) t25(StH St1) +t31(75X Pu1) t32(65X Pu1) t33(PuX Pu1) t34(35X Pu1) t35(PuH Pu1) +t41(73X We1) t42(63X We1) t43(53X We1) t44(WeX We1) t45(WeH We1) +t51(SuL HiZ) t52(StL HiZ) t53(PuL HiZ) t54(WeL HiZ) t55(HiZ HiZ) +a = x b = 1 en = 1 +a1(SuX) a2(PuX) a3(WeX) a4(MeX) a5(SmX) a6(SmX) a7(SmX) +t11(SuX Su1) t12(67X Su1) t13(57X Su1) t14(751 Su1) t15(751 Su1) +t21(76X St1) t22(StX St1) t23(56X St1) t24(651 St1) t25(651 St1) +t31(75X PuX) t32(65X PuX) t33(PuX Pu1) t34(35X Pu1) t35(531 Pu1) +t41(73X 53X) t42(63X 53X) t43(53X WeX) t44(WeX We1) t45(321 We1) +t51(SuL PuL) t52(StL PuL) t53(PuL WeL) t54(WeL MeL) t55(HiZ HiZ) +a = 0 b = 1 en = z +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 Su1) t12(St0 Su1) t13(PuX Su1) t14(35X Su1) t15(PuH Su1) +t21(Su0 St1) t22(St0 St1) t23(PuX St1) t24(35X St1) t25(PuH St1) +t31(Su0 PuX) t32(St0 PuX) t33(Pu0 Pu1) t34(WeX Pu1) t35(WeH Pu1) +t41(Su0 53X) t42(St0 53X) t43(Pu0 WeX) t44(We0 We1) t45(MeH We1) +t51(Su0 PuL) t52(St0 PuL) t53(Pu0 WeL) t54(We0 MeL) t55(HiZ HiZ) +a = 0 b = 1 en = x +a1(Su0) a2(PuL) a3(WeL) a4(MeL) a5(SmL) a6(SmL) a7(SmL) +t11(Su0 Su1) t12(St0 Su1) t13(PuX Su1) t14(35X Su1) t15(PuH Su1) +t21(Su0 St1) t22(St0 St1) t23(PuX St1) t24(35X St1) t25(PuH St1) +t31(Su0 PuX) t32(St0 PuX) t33(Pu0 Pu1) t34(WeX Pu1) t35(WeH Pu1) +t41(Su0 53X) t42(St0 53X) t43(Pu0 WeX) t44(We0 We1) t45(MeH We1) +t51(Su0 PuL) t52(St0 PuL) t53(Pu0 WeL) t54(We0 MeL) t55(HiZ HiZ) +a = 0 b = 1 en = 0 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 Su1) t12(St0 Su1) t13(Pu0 Su1) t14(We0 Su1) t15(HiZ Su1) +t21(Su0 St1) t22(St0 St1) t23(Pu0 St1) t24(We0 St1) t25(HiZ St1) +t31(Su0 Pu1) t32(St0 Pu1) t33(Pu0 Pu1) t34(We0 Pu1) t35(HiZ Pu1) +t41(Su0 We1) t42(St0 We1) t43(Pu0 We1) t44(We0 We1) t45(HiZ We1) +t51(Su0 HiZ) t52(St0 HiZ) t53(Pu0 HiZ) t54(We0 HiZ) t55(HiZ HiZ) +a = 0 b = 1 en = 1 +a1(Su0) a2(Pu0) a3(We0) a4(Me0) a5(Sm0) a6(Sm0) a7(Sm0) +t11(Su0 Su1) t12(St0 Su1) t13(PuX Su1) t14(Pu1 Su1) t15(Pu1 Su1) +t21(Su0 St1) t22(St0 St1) t23(PuX St1) t24(Pu1 St1) t25(Pu1 St1) +t31(Su0 PuX) t32(St0 PuX) t33(Pu0 Pu1) t34(WeX Pu1) t35(We1 Pu1) +t41(Su0 Pu0) t42(St0 Pu0) t43(Pu0 WeX) t44(We0 We1) t45(Me1 We1) +t51(Su0 Pu0) t52(St0 Pu0) t53(Pu0 We0) t54(We0 Me0) t55(HiZ HiZ) +a = 1 b = 1 en = z +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = 1 en = x +a1(Su1) a2(PuH) a3(WeH) a4(MeH) a5(SmH) a6(SmH) a7(SmH) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = 1 en = 0 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = 1 en = 1 +a1(Su1) a2(Pu1) a3(We1) a4(Me1) a5(Sm1) a6(Sm1) a7(Sm1) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) diff --git a/ivtest/gold/scan-invalid.gold b/ivtest/gold/scan-invalid.gold new file mode 100644 index 000000000..e5b88a652 --- /dev/null +++ b/ivtest/gold/scan-invalid.gold @@ -0,0 +1,12 @@ +ERROR: ./ivltests/scan-invalid.v:10: $sscanf requires at least three argument. +ERROR: ./ivltests/scan-invalid.v:11: $sscanf's first argument must be a register or a string. +ERROR: ./ivltests/scan-invalid.v:12: $sscanf requires at least three argument. +ERROR: ./ivltests/scan-invalid.v:13: $sscanf argument 3 (a vpiModule) is not assignable. +ERROR: ./ivltests/scan-invalid.v:14: $sscanf argument 3 (a vpiNet) is not assignable. +ERROR: ./ivltests/scan-invalid.v:15: $sscanf argument 4 (a vpiNet) is not assignable. +ERROR: ./ivltests/scan-invalid.v:20: $fscanf requires at least three argument. +ERROR: ./ivltests/scan-invalid.v:21: $fscanf's first argument (fd) must be numeric. +ERROR: ./ivltests/scan-invalid.v:22: $fscanf requires at least three argument. +ERROR: ./ivltests/scan-invalid.v:23: $fscanf argument 3 (a vpiModule) is not assignable. +ERROR: ./ivltests/scan-invalid.v:24: $fscanf argument 3 (a vpiNet) is not assignable. +ERROR: ./ivltests/scan-invalid.v:25: $fscanf argument 4 (a vpiNet) is not assignable. diff --git a/ivtest/gold/scoped_events.gold b/ivtest/gold/scoped_events.gold new file mode 100644 index 000000000..eaa5fd73b --- /dev/null +++ b/ivtest/gold/scoped_events.gold @@ -0,0 +1,6 @@ +generate block 1 triggered +generate block 2 triggered +generate block 3 triggered +generate block 4 triggered +block 5 triggered +task 6 triggered diff --git a/ivtest/gold/sdf1.gold b/ivtest/gold/sdf1.gold new file mode 100644 index 000000000..79f1cb1b0 --- /dev/null +++ b/ivtest/gold/sdf1.gold @@ -0,0 +1,5 @@ + 0 A=x, B=x, Q=x + 10 A=1, B=1, Q=x + 13 A=1, B=1, Q=0 + 20 A=1, B=0, Q=0 + 23 A=1, B=0, Q=1 diff --git a/ivtest/gold/sdf5.gold b/ivtest/gold/sdf5.gold new file mode 100644 index 000000000..d540f880e --- /dev/null +++ b/ivtest/gold/sdf5.gold @@ -0,0 +1,7 @@ + 0 D=0, Q=x, clk=0 + 10 D=0, Q=x, clk=1 + 13 D=0, Q=0, clk=1 + 20 D=1, Q=0, clk=0 + 30 D=1, Q=0, clk=1 + 33 D=1, Q=1, clk=1 + 40 D=1, Q=1, clk=0 diff --git a/ivtest/gold/sdf6.gold b/ivtest/gold/sdf6.gold new file mode 100644 index 000000000..0ba0a1027 --- /dev/null +++ b/ivtest/gold/sdf6.gold @@ -0,0 +1,11 @@ + 0 d=0, clk=0, set=0, clr=0, q=x + 10 d=1, clk=0, set=0, clr=0, q=x + 20 d=1, clk=0, set=1, clr=0, q=x + 24 d=1, clk=0, set=1, clr=0, q=1 + 30 d=1, clk=0, set=0, clr=0, q=1 + 40 d=1, clk=0, set=0, clr=1, q=1 + 43 d=1, clk=0, set=0, clr=1, q=0 + 50 d=1, clk=0, set=0, clr=0, q=0 + 60 d=1, clk=1, set=0, clr=0, q=0 + 66 d=1, clk=1, set=0, clr=0, q=1 + 70 d=0, clk=1, set=0, clr=0, q=1 diff --git a/ivtest/gold/sdf7.gold b/ivtest/gold/sdf7.gold new file mode 100644 index 000000000..8d3d2b4d5 --- /dev/null +++ b/ivtest/gold/sdf7.gold @@ -0,0 +1,9 @@ + 0 A=x, B=x, Q=x + 10 A=1, B=1, Q=x + 13 A=1, B=1, Q=0 + 20 A=1, B=0, Q=0 + 21 A=1, B=0, Q=1 + 30 A=1, B=1, Q=1 + 33 A=1, B=1, Q=0 + 40 A=0, B=1, Q=0 + 41 A=0, B=1, Q=1 diff --git a/ivtest/gold/sdf8.gold b/ivtest/gold/sdf8.gold new file mode 100644 index 000000000..84f79059a --- /dev/null +++ b/ivtest/gold/sdf8.gold @@ -0,0 +1,5 @@ + 0 A=x, B=1, Q=x + 10 A=1, B=1, Q=x + 13 A=1, B=1, Q=0 + 20 A=0, B=1, Q=0 + 22 A=0, B=1, Q=1 diff --git a/ivtest/gold/sel_rval_bit_ob.gold b/ivtest/gold/sel_rval_bit_ob.gold new file mode 100644 index 000000000..e628af45f --- /dev/null +++ b/ivtest/gold/sel_rval_bit_ob.gold @@ -0,0 +1,113 @@ +./ivltests/sel_rval_bit_ob.v:60: warning: Constant bit select [32] is after pvar0[31:0]. +./ivltests/sel_rval_bit_ob.v:60: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:65: warning: Constant bit select [-1] is before pvar0[31:0]. +./ivltests/sel_rval_bit_ob.v:65: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:70: warning: Constant undefined bit select [1'bx] for parameter 'pvar0'. +./ivltests/sel_rval_bit_ob.v:70: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:75: warning: Constant undefined bit select [1'bz] for parameter 'pvar0'. +./ivltests/sel_rval_bit_ob.v:75: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:89: warning: Constant bit select [32] is after pvar1[31:0]. +./ivltests/sel_rval_bit_ob.v:89: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:94: warning: Constant bit select [-1] is before pvar1[31:0]. +./ivltests/sel_rval_bit_ob.v:94: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:99: warning: Constant undefined bit select [1'bx] for parameter 'pvar1'. +./ivltests/sel_rval_bit_ob.v:99: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:104: warning: Constant undefined bit select [1'bz] for parameter 'pvar1'. +./ivltests/sel_rval_bit_ob.v:104: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:118: warning: Constant bit select [32] is after pvar2[31:0]. +./ivltests/sel_rval_bit_ob.v:118: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:123: warning: Constant bit select [-1] is before pvar2[31:0]. +./ivltests/sel_rval_bit_ob.v:123: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:128: warning: Constant undefined bit select [1'bx] for parameter 'pvar2'. +./ivltests/sel_rval_bit_ob.v:128: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:133: warning: Constant undefined bit select [1'bz] for parameter 'pvar2'. +./ivltests/sel_rval_bit_ob.v:133: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:142: warning: Constant bit select [4] is after pvar3[3:0]. +./ivltests/sel_rval_bit_ob.v:142: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:147: warning: Constant bit select [-1] is before pvar3[3:0]. +./ivltests/sel_rval_bit_ob.v:147: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:152: warning: Constant undefined bit select [1'bx] for parameter 'pvar3'. +./ivltests/sel_rval_bit_ob.v:152: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:157: warning: Constant undefined bit select [1'bz] for parameter 'pvar3'. +./ivltests/sel_rval_bit_ob.v:157: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:166: warning: Constant bit select [5] is after pvar4[4:1]. +./ivltests/sel_rval_bit_ob.v:166: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:171: warning: Constant bit select [0] is before pvar4[4:1]. +./ivltests/sel_rval_bit_ob.v:171: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:176: warning: Constant undefined bit select [1'bx] for parameter 'pvar4'. +./ivltests/sel_rval_bit_ob.v:176: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:181: warning: Constant undefined bit select [1'bz] for parameter 'pvar4'. +./ivltests/sel_rval_bit_ob.v:181: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:190: warning: Constant bit select [0] is after pvar5[1:4]. +./ivltests/sel_rval_bit_ob.v:190: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:195: warning: Constant bit select [5] is before pvar5[1:4]. +./ivltests/sel_rval_bit_ob.v:195: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:200: warning: Constant undefined bit select [1'bx] for parameter 'pvar5'. +./ivltests/sel_rval_bit_ob.v:200: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:205: warning: Constant undefined bit select [1'bz] for parameter 'pvar5'. +./ivltests/sel_rval_bit_ob.v:205: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:215: warning: Constant bit select [5] is after vector rvar[4:1]. +./ivltests/sel_rval_bit_ob.v:215: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:220: warning: Constant bit select [0] is before vector rvar[4:1]. +./ivltests/sel_rval_bit_ob.v:220: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:225: warning: Constant bit select [1'bx] is undefined for vector 'rvar'. +./ivltests/sel_rval_bit_ob.v:225: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:230: warning: Constant bit select [1'bz] is undefined for vector 'rvar'. +./ivltests/sel_rval_bit_ob.v:230: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:239: warning: Constant bit select [0] is after vector rvar2[1:4]. +./ivltests/sel_rval_bit_ob.v:239: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:244: warning: Constant bit select [5] is before vector rvar2[1:4]. +./ivltests/sel_rval_bit_ob.v:244: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:249: warning: Constant bit select [1'bx] is undefined for vector 'rvar2'. +./ivltests/sel_rval_bit_ob.v:249: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:254: warning: Constant bit select [1'bz] is undefined for vector 'rvar2'. +./ivltests/sel_rval_bit_ob.v:254: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:264: warning: Constant bit select [5] is after array word ravar[][4:1]. +./ivltests/sel_rval_bit_ob.v:264: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:269: warning: Constant bit select [0] is before array word ravar[][4:1]. +./ivltests/sel_rval_bit_ob.v:269: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:274: warning: Constant bit select [1'bx] is undefined for array word 'ravar[]'. +./ivltests/sel_rval_bit_ob.v:274: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:279: warning: Constant bit select [1'bz] is undefined for array word 'ravar[]'. +./ivltests/sel_rval_bit_ob.v:279: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:288: warning: Constant bit select [0] is after array word ravar2[][1:4]. +./ivltests/sel_rval_bit_ob.v:288: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:293: warning: Constant bit select [5] is before array word ravar2[][1:4]. +./ivltests/sel_rval_bit_ob.v:293: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:298: warning: Constant bit select [1'bx] is undefined for array word 'ravar2[]'. +./ivltests/sel_rval_bit_ob.v:298: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:303: warning: Constant bit select [1'bz] is undefined for array word 'ravar2[]'. +./ivltests/sel_rval_bit_ob.v:303: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:313: warning: Constant bit select [5] is after vector wvar[4:1]. +./ivltests/sel_rval_bit_ob.v:313: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:318: warning: Constant bit select [0] is before vector wvar[4:1]. +./ivltests/sel_rval_bit_ob.v:318: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:323: warning: Constant bit select [1'bx] is undefined for vector 'wvar'. +./ivltests/sel_rval_bit_ob.v:323: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:328: warning: Constant bit select [1'bz] is undefined for vector 'wvar'. +./ivltests/sel_rval_bit_ob.v:328: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:337: warning: Constant bit select [0] is after vector wvar2[1:4]. +./ivltests/sel_rval_bit_ob.v:337: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:342: warning: Constant bit select [5] is before vector wvar2[1:4]. +./ivltests/sel_rval_bit_ob.v:342: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:347: warning: Constant bit select [1'bx] is undefined for vector 'wvar2'. +./ivltests/sel_rval_bit_ob.v:347: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:352: warning: Constant bit select [1'bz] is undefined for vector 'wvar2'. +./ivltests/sel_rval_bit_ob.v:352: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:362: warning: Constant bit select [5] is after array word wavar[][4:1]. +./ivltests/sel_rval_bit_ob.v:362: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:367: warning: Constant bit select [0] is before array word wavar[][4:1]. +./ivltests/sel_rval_bit_ob.v:367: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:372: warning: Constant bit select [1'bx] is undefined for array word 'wavar[]'. +./ivltests/sel_rval_bit_ob.v:372: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:377: warning: Constant bit select [1'bz] is undefined for array word 'wavar[]'. +./ivltests/sel_rval_bit_ob.v:377: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:386: warning: Constant bit select [0] is after array word wavar2[][1:4]. +./ivltests/sel_rval_bit_ob.v:386: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:391: warning: Constant bit select [5] is before array word wavar2[][1:4]. +./ivltests/sel_rval_bit_ob.v:391: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:397: warning: Constant bit select [1'bx] is undefined for array word 'wavar2[]'. +./ivltests/sel_rval_bit_ob.v:397: : Replacing select with a constant 1'bx. +./ivltests/sel_rval_bit_ob.v:403: warning: Constant bit select [1'bz] is undefined for array word 'wavar2[]'. +./ivltests/sel_rval_bit_ob.v:403: : Replacing select with a constant 1'bx. +PASSED diff --git a/ivtest/gold/sel_rval_part_ob.gold b/ivtest/gold/sel_rval_part_ob.gold new file mode 100644 index 000000000..0d4dcafba --- /dev/null +++ b/ivtest/gold/sel_rval_part_ob.gold @@ -0,0 +1,225 @@ +./ivltests/sel_rval_part_ob.v:57: warning: Part select pvar0[33:32] is selecting after the parameter pvar0[31:0]. +./ivltests/sel_rval_part_ob.v:57: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:62: warning: Part select pvar0[32:31] is selecting after the parameter pvar0[31:0]. +./ivltests/sel_rval_part_ob.v:62: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:68: warning: Part select [-1:-2] is selecting before the parameter pvar0[31:0]. +./ivltests/sel_rval_part_ob.v:68: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:73: warning: Part select [0:-1] is selecting before the parameter pvar0[31:0]. +./ivltests/sel_rval_part_ob.v:73: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:79: warning: Undefined part select [1'bx:'sd1] for parameter 'pvar0'. +./ivltests/sel_rval_part_ob.v:79: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:85: warning: Undefined part select ['sd1:1'bx] for parameter 'pvar0'. +./ivltests/sel_rval_part_ob.v:85: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:91: warning: Undefined part select [1'bz:'sd1] for parameter 'pvar0'. +./ivltests/sel_rval_part_ob.v:91: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:97: warning: Undefined part select ['sd1:1'bz] for parameter 'pvar0'. +./ivltests/sel_rval_part_ob.v:97: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:112: warning: Part select pvar1[33:32] is selecting after the parameter pvar1[31:0]. +./ivltests/sel_rval_part_ob.v:112: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:117: warning: Part select pvar1[32:31] is selecting after the parameter pvar1[31:0]. +./ivltests/sel_rval_part_ob.v:117: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:123: warning: Part select [-1:-2] is selecting before the parameter pvar1[31:0]. +./ivltests/sel_rval_part_ob.v:123: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:128: warning: Part select [0:-1] is selecting before the parameter pvar1[31:0]. +./ivltests/sel_rval_part_ob.v:128: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:134: warning: Undefined part select [1'bx:'sd1] for parameter 'pvar1'. +./ivltests/sel_rval_part_ob.v:134: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:140: warning: Undefined part select ['sd1:1'bx] for parameter 'pvar1'. +./ivltests/sel_rval_part_ob.v:140: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:146: warning: Undefined part select [1'bz:'sd1] for parameter 'pvar1'. +./ivltests/sel_rval_part_ob.v:146: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:152: warning: Undefined part select ['sd1:1'bz] for parameter 'pvar1'. +./ivltests/sel_rval_part_ob.v:152: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:167: warning: Part select pvar2[33:32] is selecting after the parameter pvar2[31:0]. +./ivltests/sel_rval_part_ob.v:167: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:172: warning: Part select pvar2[32:31] is selecting after the parameter pvar2[31:0]. +./ivltests/sel_rval_part_ob.v:172: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:178: warning: Part select [-1:-2] is selecting before the parameter pvar2[31:0]. +./ivltests/sel_rval_part_ob.v:178: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:183: warning: Part select [0:-1] is selecting before the parameter pvar2[31:0]. +./ivltests/sel_rval_part_ob.v:183: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:189: warning: Undefined part select [1'bx:'sd1] for parameter 'pvar2'. +./ivltests/sel_rval_part_ob.v:189: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:195: warning: Undefined part select ['sd1:1'bx] for parameter 'pvar2'. +./ivltests/sel_rval_part_ob.v:195: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:201: warning: Undefined part select [1'bz:'sd1] for parameter 'pvar2'. +./ivltests/sel_rval_part_ob.v:201: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:207: warning: Undefined part select ['sd1:1'bz] for parameter 'pvar2'. +./ivltests/sel_rval_part_ob.v:207: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:217: warning: Part select pvar3[5:4] is selecting after the parameter pvar3[3:0]. +./ivltests/sel_rval_part_ob.v:217: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:222: warning: Part select pvar3[4:3] is selecting after the parameter pvar3[3:0]. +./ivltests/sel_rval_part_ob.v:222: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:228: warning: Part select [-1:-2] is selecting before the parameter pvar3[3:0]. +./ivltests/sel_rval_part_ob.v:228: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:233: warning: Part select [0:-1] is selecting before the parameter pvar3[3:0]. +./ivltests/sel_rval_part_ob.v:233: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:239: warning: Undefined part select [1'bx:'sd1] for parameter 'pvar3'. +./ivltests/sel_rval_part_ob.v:239: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:245: warning: Undefined part select ['sd1:1'bx] for parameter 'pvar3'. +./ivltests/sel_rval_part_ob.v:245: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:251: warning: Undefined part select [1'bz:'sd1] for parameter 'pvar3'. +./ivltests/sel_rval_part_ob.v:251: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:257: warning: Undefined part select ['sd1:1'bz] for parameter 'pvar3'. +./ivltests/sel_rval_part_ob.v:257: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:267: warning: Part select pvar4[6:5] is selecting after the parameter pvar4[4:1]. +./ivltests/sel_rval_part_ob.v:267: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:272: warning: Part select pvar4[5:4] is selecting after the parameter pvar4[4:1]. +./ivltests/sel_rval_part_ob.v:272: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:278: warning: Part select [0:-1] is selecting before the parameter pvar4[4:1]. +./ivltests/sel_rval_part_ob.v:278: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:283: warning: Part select [1:0] is selecting before the parameter pvar4[4:1]. +./ivltests/sel_rval_part_ob.v:283: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:289: warning: Undefined part select [1'bx:'sd1] for parameter 'pvar4'. +./ivltests/sel_rval_part_ob.v:289: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:295: warning: Undefined part select ['sd1:1'bx] for parameter 'pvar4'. +./ivltests/sel_rval_part_ob.v:295: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:301: warning: Undefined part select [1'bz:'sd1] for parameter 'pvar4'. +./ivltests/sel_rval_part_ob.v:301: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:307: warning: Undefined part select ['sd1:1'bz] for parameter 'pvar4'. +./ivltests/sel_rval_part_ob.v:307: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:317: warning: Part select pvar5[-1:0] is selecting after the parameter pvar5[1:4]. +./ivltests/sel_rval_part_ob.v:317: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:322: warning: Part select pvar5[0:1] is selecting after the parameter pvar5[1:4]. +./ivltests/sel_rval_part_ob.v:322: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:328: warning: Part select [5:6] is selecting before the parameter pvar5[1:4]. +./ivltests/sel_rval_part_ob.v:328: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:333: warning: Part select [4:5] is selecting before the parameter pvar5[1:4]. +./ivltests/sel_rval_part_ob.v:333: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:339: warning: Undefined part select [1'bx:'sd1] for parameter 'pvar5'. +./ivltests/sel_rval_part_ob.v:339: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:345: warning: Undefined part select ['sd1:1'bx] for parameter 'pvar5'. +./ivltests/sel_rval_part_ob.v:345: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:351: warning: Undefined part select [1'bz:'sd1] for parameter 'pvar5'. +./ivltests/sel_rval_part_ob.v:351: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:357: warning: Undefined part select ['sd1:1'bz] for parameter 'pvar5'. +./ivltests/sel_rval_part_ob.v:357: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:368: warning: Part select [6:5] is selecting after the vector rvar[4:1]. +./ivltests/sel_rval_part_ob.v:368: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:373: warning: Part select [5:4] is selecting after the vector rvar[4:1]. +./ivltests/sel_rval_part_ob.v:373: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:378: warning: Part select [0:-1] is selecting before the vector rvar[4:1]. +./ivltests/sel_rval_part_ob.v:378: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:383: warning: Part select [1:0] is selecting before the vector rvar[4:1]. +./ivltests/sel_rval_part_ob.v:383: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:388: warning: Undefined part select [1'bx:'sd1] for vector 'rvar'. +./ivltests/sel_rval_part_ob.v:388: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:393: warning: Undefined part select ['sd1:1'bx] for vector 'rvar'. +./ivltests/sel_rval_part_ob.v:393: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:398: warning: Undefined part select [1'bz:'sd1] for vector 'rvar'. +./ivltests/sel_rval_part_ob.v:398: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:403: warning: Undefined part select ['sd1:1'bz] for vector 'rvar'. +./ivltests/sel_rval_part_ob.v:403: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:412: warning: Part select [-1:0] is selecting after the vector rvar2[1:4]. +./ivltests/sel_rval_part_ob.v:412: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:417: warning: Part select [0:1] is selecting after the vector rvar2[1:4]. +./ivltests/sel_rval_part_ob.v:417: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:423: warning: Part select [5:6] is selecting before the vector rvar2[1:4]. +./ivltests/sel_rval_part_ob.v:423: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:428: warning: Part select [4:5] is selecting before the vector rvar2[1:4]. +./ivltests/sel_rval_part_ob.v:428: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:434: warning: Undefined part select [1'bx:'sd1] for vector 'rvar2'. +./ivltests/sel_rval_part_ob.v:434: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:440: warning: Undefined part select ['sd1:1'bx] for vector 'rvar2'. +./ivltests/sel_rval_part_ob.v:440: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:446: warning: Undefined part select [1'bz:'sd1] for vector 'rvar2'. +./ivltests/sel_rval_part_ob.v:446: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:451: warning: Undefined part select ['sd1:1'bz] for vector 'rvar2'. +./ivltests/sel_rval_part_ob.v:451: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:461: warning: Part select [6:5] is selecting after the array word ravar[][4:1]. +./ivltests/sel_rval_part_ob.v:461: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:466: warning: Part select [5:4] is selecting after the array word ravar[][4:1]. +./ivltests/sel_rval_part_ob.v:466: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:472: warning: Part select [0:-1] is selecting before the array word ravar[][4:1]. +./ivltests/sel_rval_part_ob.v:472: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:477: warning: Part select [1:0] is selecting before the array word ravar[][4:1]. +./ivltests/sel_rval_part_ob.v:477: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:483: warning: Undefined part select [1'bx:'sd1] for array word 'ravar[]'. +./ivltests/sel_rval_part_ob.v:483: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:489: warning: Undefined part select ['sd1:1'bx] for array word 'ravar[]'. +./ivltests/sel_rval_part_ob.v:489: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:495: warning: Undefined part select [1'bz:'sd1] for array word 'ravar[]'. +./ivltests/sel_rval_part_ob.v:495: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:500: warning: Undefined part select ['sd1:1'bz] for array word 'ravar[]'. +./ivltests/sel_rval_part_ob.v:500: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:509: warning: Part select [-1:0] is selecting after the array word ravar2[][1:4]. +./ivltests/sel_rval_part_ob.v:509: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:514: warning: Part select [0:1] is selecting after the array word ravar2[][1:4]. +./ivltests/sel_rval_part_ob.v:514: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:520: warning: Part select [5:6] is selecting before the array word ravar2[][1:4]. +./ivltests/sel_rval_part_ob.v:520: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:525: warning: Part select [4:5] is selecting before the array word ravar2[][1:4]. +./ivltests/sel_rval_part_ob.v:525: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:531: warning: Undefined part select [1'bx:'sd1] for array word 'ravar2[]'. +./ivltests/sel_rval_part_ob.v:531: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:537: warning: Undefined part select ['sd1:1'bx] for array word 'ravar2[]'. +./ivltests/sel_rval_part_ob.v:537: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:543: warning: Undefined part select [1'bz:'sd1] for array word 'ravar2[]'. +./ivltests/sel_rval_part_ob.v:543: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:549: warning: Undefined part select ['sd1:1'bz] for array word 'ravar2[]'. +./ivltests/sel_rval_part_ob.v:549: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:560: warning: Part select [6:5] is selecting after the vector wvar[4:1]. +./ivltests/sel_rval_part_ob.v:560: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:565: warning: Part select [5:4] is selecting after the vector wvar[4:1]. +./ivltests/sel_rval_part_ob.v:565: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:570: warning: Part select [0:-1] is selecting before the vector wvar[4:1]. +./ivltests/sel_rval_part_ob.v:570: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:575: warning: Part select [1:0] is selecting before the vector wvar[4:1]. +./ivltests/sel_rval_part_ob.v:575: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:580: warning: Undefined part select [1'bx:'sd1] for vector 'wvar'. +./ivltests/sel_rval_part_ob.v:580: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:585: warning: Undefined part select ['sd1:1'bx] for vector 'wvar'. +./ivltests/sel_rval_part_ob.v:585: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:590: warning: Undefined part select [1'bz:'sd1] for vector 'wvar'. +./ivltests/sel_rval_part_ob.v:590: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:595: warning: Undefined part select ['sd1:1'bz] for vector 'wvar'. +./ivltests/sel_rval_part_ob.v:595: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:604: warning: Part select [-1:0] is selecting after the vector wvar2[1:4]. +./ivltests/sel_rval_part_ob.v:604: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:609: warning: Part select [0:1] is selecting after the vector wvar2[1:4]. +./ivltests/sel_rval_part_ob.v:609: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:614: warning: Part select [5:6] is selecting before the vector wvar2[1:4]. +./ivltests/sel_rval_part_ob.v:614: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:619: warning: Part select [4:5] is selecting before the vector wvar2[1:4]. +./ivltests/sel_rval_part_ob.v:619: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:624: warning: Undefined part select [1'bx:'sd1] for vector 'wvar2'. +./ivltests/sel_rval_part_ob.v:624: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:629: warning: Undefined part select ['sd1:1'bx] for vector 'wvar2'. +./ivltests/sel_rval_part_ob.v:629: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:634: warning: Undefined part select [1'bz:'sd1] for vector 'wvar2'. +./ivltests/sel_rval_part_ob.v:634: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:639: warning: Undefined part select ['sd1:1'bz] for vector 'wvar2'. +./ivltests/sel_rval_part_ob.v:639: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:649: warning: Part select [6:5] is selecting after the array word wavar[][4:1]. +./ivltests/sel_rval_part_ob.v:649: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:654: warning: Part select [5:4] is selecting after the array word wavar[][4:1]. +./ivltests/sel_rval_part_ob.v:654: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:660: warning: Part select [0:-1] is selecting before the array word wavar[][4:1]. +./ivltests/sel_rval_part_ob.v:660: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:665: warning: Part select [1:0] is selecting before the array word wavar[][4:1]. +./ivltests/sel_rval_part_ob.v:665: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:671: warning: Undefined part select [1'bx:'sd1] for array word 'wavar[]'. +./ivltests/sel_rval_part_ob.v:671: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:677: warning: Undefined part select ['sd1:1'bx] for array word 'wavar[]'. +./ivltests/sel_rval_part_ob.v:677: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:683: warning: Undefined part select [1'bz:'sd1] for array word 'wavar[]'. +./ivltests/sel_rval_part_ob.v:683: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:689: warning: Undefined part select ['sd1:1'bz] for array word 'wavar[]'. +./ivltests/sel_rval_part_ob.v:689: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:699: warning: Part select [-1:0] is selecting after the array word wavar2[][1:4]. +./ivltests/sel_rval_part_ob.v:699: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:705: warning: Part select [0:1] is selecting after the array word wavar2[][1:4]. +./ivltests/sel_rval_part_ob.v:705: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:711: warning: Part select [5:6] is selecting before the array word wavar2[][1:4]. +./ivltests/sel_rval_part_ob.v:711: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:717: warning: Part select [4:5] is selecting before the array word wavar2[][1:4]. +./ivltests/sel_rval_part_ob.v:717: : Replacing the out of bound bits with 'bx. +./ivltests/sel_rval_part_ob.v:723: warning: Undefined part select [1'bx:'sd1] for array word 'wavar2[]'. +./ivltests/sel_rval_part_ob.v:723: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:729: warning: Undefined part select ['sd1:1'bx] for array word 'wavar2[]'. +./ivltests/sel_rval_part_ob.v:729: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:735: warning: Undefined part select [1'bz:'sd1] for array word 'wavar2[]'. +./ivltests/sel_rval_part_ob.v:735: : Replacing select with a constant 'bx. +./ivltests/sel_rval_part_ob.v:741: warning: Undefined part select ['sd1:1'bz] for array word 'wavar2[]'. +./ivltests/sel_rval_part_ob.v:741: : Replacing select with a constant 'bx. +PASSED diff --git a/ivtest/gold/select3.gold b/ivtest/gold/select3.gold new file mode 100644 index 000000000..eece5fbd2 --- /dev/null +++ b/ivtest/gold/select3.gold @@ -0,0 +1,16 @@ +dut[00] = 0 +dut[01] = 1 +dut[02] = 0 +dut[03] = 1 +dut[04] = 0 +dut[05] = 1 +dut[06] = 0 +dut[07] = 1 +dut[08] = 1 +dut[09] = 0 +dut[0a] = 1 +dut[0b] = 0 +dut[0c] = 1 +dut[0d] = 0 +dut[0e] = 1 +dut[0f] = 0 diff --git a/ivtest/gold/sf_countbits_fail.gold b/ivtest/gold/sf_countbits_fail.gold new file mode 100644 index 000000000..a16b5732f --- /dev/null +++ b/ivtest/gold/sf_countbits_fail.gold @@ -0,0 +1,14 @@ +./ivltests/sf_countbits_fail.v:6: error: constant function $countbits() does not support a single argument. +./ivltests/sf_countbits_fail.v:7: error: constant function $countbits() does not support a single argument. +./ivltests/sf_countbits_fail.v:8: error: constant function $countbits() does not support a single argument. +./ivltests/sf_countbits_fail.v:9: error: constant function $countbits() does not support a string argument (1). +./ivltests/sf_countbits_fail.v:10: error: constant function $countbits() does not support a string argument (2). +./ivltests/sf_countbits_fail.v:11: error: constant function $countbits() does not support a string argument (3). +ERROR: ./ivltests/sf_countbits_fail.v:6: The first argument to $countbits() must be numeric. +ERROR: ./ivltests/sf_countbits_fail.v:6: $countbits() requires at least one control bit argument. +ERROR: ./ivltests/sf_countbits_fail.v:7: The first argument to $countbits() must be numeric. +ERROR: ./ivltests/sf_countbits_fail.v:7: $countbits() requires at least one control bit argument. +ERROR: ./ivltests/sf_countbits_fail.v:8: $countbits() requires at least one control bit argument. +ERROR: ./ivltests/sf_countbits_fail.v:9: The first argument to $countbits() must be numeric. +ERROR: ./ivltests/sf_countbits_fail.v:10: Control bit argument 1 to $countbits() must be numeric. +ERROR: ./ivltests/sf_countbits_fail.v:11: Control bit argument 2 to $countbits() must be numeric. diff --git a/ivtest/gold/sf_countones_fail.gold b/ivtest/gold/sf_countones_fail.gold new file mode 100644 index 000000000..db251060c --- /dev/null +++ b/ivtest/gold/sf_countones_fail.gold @@ -0,0 +1,6 @@ +./ivltests/sf_countones_fail.v:7: error: constant function $countones() does not support a string argument (1). +./ivltests/sf_countones_fail.v:8: error: constant function $countones() does not support two arguments. +ERROR: ./ivltests/sf_countones_fail.v:6: $countones's argument must be numeric. +ERROR: ./ivltests/sf_countones_fail.v:7: $countones's argument must be numeric. +ERROR: ./ivltests/sf_countones_fail.v:8: $countones takes a single numeric argument. + Found 1 extra argument. diff --git a/ivtest/gold/sf_isunknown_fail.gold b/ivtest/gold/sf_isunknown_fail.gold new file mode 100644 index 000000000..619c05ca7 --- /dev/null +++ b/ivtest/gold/sf_isunknown_fail.gold @@ -0,0 +1,6 @@ +./ivltests/sf_isunknown_fail.v:7: error: constant function $isunknown() does not support a string argument (1). +./ivltests/sf_isunknown_fail.v:8: error: constant function $isunknown() does not support two arguments. +ERROR: ./ivltests/sf_isunknown_fail.v:6: $isunknown's argument must be numeric. +ERROR: ./ivltests/sf_isunknown_fail.v:7: $isunknown's argument must be numeric. +ERROR: ./ivltests/sf_isunknown_fail.v:8: $isunknown takes a single numeric argument. + Found 1 extra argument. diff --git a/ivtest/gold/sf_onehot0_fail.gold b/ivtest/gold/sf_onehot0_fail.gold new file mode 100644 index 000000000..3d314c1fa --- /dev/null +++ b/ivtest/gold/sf_onehot0_fail.gold @@ -0,0 +1,6 @@ +./ivltests/sf_onehot0_fail.v:7: error: constant function $onehot0() does not support a string argument (1). +./ivltests/sf_onehot0_fail.v:8: error: constant function $onehot0() does not support two arguments. +ERROR: ./ivltests/sf_onehot0_fail.v:6: $onehot0's argument must be numeric. +ERROR: ./ivltests/sf_onehot0_fail.v:7: $onehot0's argument must be numeric. +ERROR: ./ivltests/sf_onehot0_fail.v:8: $onehot0 takes a single numeric argument. + Found 1 extra argument. diff --git a/ivtest/gold/sf_onehot_fail.gold b/ivtest/gold/sf_onehot_fail.gold new file mode 100644 index 000000000..843580b8c --- /dev/null +++ b/ivtest/gold/sf_onehot_fail.gold @@ -0,0 +1,6 @@ +./ivltests/sf_onehot_fail.v:7: error: constant function $onehot() does not support a string argument (1). +./ivltests/sf_onehot_fail.v:8: error: constant function $onehot() does not support two arguments. +ERROR: ./ivltests/sf_onehot_fail.v:6: $onehot's argument must be numeric. +ERROR: ./ivltests/sf_onehot_fail.v:7: $onehot's argument must be numeric. +ERROR: ./ivltests/sf_onehot_fail.v:8: $onehot takes a single numeric argument. + Found 1 extra argument. diff --git a/ivtest/gold/shellho1.gold b/ivtest/gold/shellho1.gold new file mode 100644 index 000000000..8f1650158 --- /dev/null +++ b/ivtest/gold/shellho1.gold @@ -0,0 +1,10 @@ +Running first test. + +PASS! top.memory.memory[0] set correctly. +top.memory.memory[0] = f + +Running second test. + +top.memory.memory[1] = f +PASS! top.memory.memory[1] set correctly. +top.memory.memory[1] = f diff --git a/ivtest/gold/shift1.gold b/ivtest/gold/shift1.gold new file mode 100644 index 000000000..6dd34a9c8 --- /dev/null +++ b/ivtest/gold/shift1.gold @@ -0,0 +1,3 @@ +02 55 55 +80 00 00 +02 55 55 diff --git a/ivtest/gold/shift5.gold b/ivtest/gold/shift5.gold new file mode 100644 index 000000000..5783917b0 --- /dev/null +++ b/ivtest/gold/shift5.gold @@ -0,0 +1 @@ +PASS: 32'sh80000000 >>> 6'd32 = 0xffffffff diff --git a/ivtest/gold/signed10.gold b/ivtest/gold/signed10.gold new file mode 100644 index 000000000..92b49eca5 --- /dev/null +++ b/ivtest/gold/signed10.gold @@ -0,0 +1 @@ +foo=-2 bar=254 $signed(bar)=-2 diff --git a/ivtest/gold/signed12.gold b/ivtest/gold/signed12.gold new file mode 100644 index 000000000..ca028fbba --- /dev/null +++ b/ivtest/gold/signed12.gold @@ -0,0 +1 @@ +11111111 diff --git a/ivtest/gold/signed4.gold b/ivtest/gold/signed4.gold new file mode 100644 index 000000000..9cca410c1 --- /dev/null +++ b/ivtest/gold/signed4.gold @@ -0,0 +1,3 @@ +x = 3 (should be 3) +y = -3 (should be -3) +x = 253 (should be 253) diff --git a/ivtest/gold/sp2.inv b/ivtest/gold/sp2.inv new file mode 100644 index 000000000..f6fa2c813 --- /dev/null +++ b/ivtest/gold/sp2.inv @@ -0,0 +1,2 @@ +# captured from: fo + diff --git a/ivtest/gold/specify3.gold b/ivtest/gold/specify3.gold new file mode 100644 index 000000000..9c9d0e6b6 --- /dev/null +++ b/ivtest/gold/specify3.gold @@ -0,0 +1,20 @@ + 10 a=0, b=0, fast=0, q=0 + 20 a=1, b=0, fast=0, q=0 + 24 a=1, b=0, fast=0, q=1 + 30 a=0, b=0, fast=0, q=1 + 34 a=0, b=0, fast=0, q=0 + 40 a=0, b=1, fast=0, q=0 + 44 a=0, b=1, fast=0, q=1 + 50 a=0, b=0, fast=0, q=1 + 54 a=0, b=0, fast=0, q=0 + 60 a=1, b=0, fast=0, q=0 + 64 a=1, b=0, fast=0, q=1 + 70 a=1, b=0, fast=1, q=1 + 80 a=1, b=1, fast=1, q=1 + 81 a=1, b=1, fast=1, q=0 + 90 a=1, b=0, fast=1, q=0 + 91 a=1, b=0, fast=1, q=1 + 100 a=0, b=0, fast=1, q=1 + 101 a=0, b=0, fast=1, q=0 + 110 a=1, b=0, fast=1, q=0 + 111 a=1, b=0, fast=1, q=1 diff --git a/ivtest/gold/specify4.gold b/ivtest/gold/specify4.gold new file mode 100644 index 000000000..885c94e51 --- /dev/null +++ b/ivtest/gold/specify4.gold @@ -0,0 +1,9 @@ + 10 q=0, d=0, c=1 + 15 q=0, d=0, c=0 + 20 q=0, d=0, c=1 + 25 q=0, d=1, c=0 + 30 q=0, d=1, c=1 + 33 q=1, d=1, c=1 + 35 q=1, d=0, c=0 + 40 q=1, d=0, c=1 + 42 q=0, d=0, c=1 diff --git a/ivtest/gold/specify5.gold b/ivtest/gold/specify5.gold new file mode 100644 index 000000000..9b5e64823 --- /dev/null +++ b/ivtest/gold/specify5.gold @@ -0,0 +1,12 @@ + 0.00 ns - cdn=x, cp=0, d=1, qr=x, qp=x + 10.00 ns - cdn=0, cp=0, d=1, qr=x, qp=x + 10.30 ns - cdn=0, cp=0, d=1, qr=0, qp=0 + 20.00 ns - cdn=1, cp=0, d=1, qr=0, qp=0 + 30.00 ns - cdn=1, cp=1, d=1, qr=0, qp=0 + 30.60 ns - cdn=1, cp=1, d=1, qr=1, qp=1 + 40.00 ns - cdn=1, cp=0, d=0, qr=1, qp=1 + 50.00 ns - cdn=1, cp=1, d=0, qr=1, qp=1 + 50.70 ns - cdn=1, cp=1, d=0, qr=0, qp=0 + 60.00 ns - cdn=1, cp=0, d=1, qr=0, qp=0 + 70.00 ns - cdn=1, cp=1, d=1, qr=0, qp=0 + 70.60 ns - cdn=1, cp=1, d=1, qr=1, qp=1 diff --git a/ivtest/gold/stask_parm2.gold b/ivtest/gold/stask_parm2.gold new file mode 100644 index 000000000..299619e38 --- /dev/null +++ b/ivtest/gold/stask_parm2.gold @@ -0,0 +1,225 @@ +{a, b} == 00000000 +{a, b} == 00000001 +{a, b} == 00000010 +{a, b} == 00000011 +{a, b} == 00000100 +{a, b} == 00000101 +{a, b} == 00000110 +{a, b} == 00000111 +{a, b} == 00001000 +{a, b} == 00001001 +{a, b} == 00001010 +{a, b} == 00001011 +{a, b} == 00001100 +{a, b} == 00001101 +{a, b} == 00001110 +{a, b} == 00010000 +{a, b} == 00010001 +{a, b} == 00010010 +{a, b} == 00010011 +{a, b} == 00010100 +{a, b} == 00010101 +{a, b} == 00010110 +{a, b} == 00010111 +{a, b} == 00011000 +{a, b} == 00011001 +{a, b} == 00011010 +{a, b} == 00011011 +{a, b} == 00011100 +{a, b} == 00011101 +{a, b} == 00011110 +{a, b} == 00100000 +{a, b} == 00100001 +{a, b} == 00100010 +{a, b} == 00100011 +{a, b} == 00100100 +{a, b} == 00100101 +{a, b} == 00100110 +{a, b} == 00100111 +{a, b} == 00101000 +{a, b} == 00101001 +{a, b} == 00101010 +{a, b} == 00101011 +{a, b} == 00101100 +{a, b} == 00101101 +{a, b} == 00101110 +{a, b} == 00110000 +{a, b} == 00110001 +{a, b} == 00110010 +{a, b} == 00110011 +{a, b} == 00110100 +{a, b} == 00110101 +{a, b} == 00110110 +{a, b} == 00110111 +{a, b} == 00111000 +{a, b} == 00111001 +{a, b} == 00111010 +{a, b} == 00111011 +{a, b} == 00111100 +{a, b} == 00111101 +{a, b} == 00111110 +{a, b} == 01000000 +{a, b} == 01000001 +{a, b} == 01000010 +{a, b} == 01000011 +{a, b} == 01000100 +{a, b} == 01000101 +{a, b} == 01000110 +{a, b} == 01000111 +{a, b} == 01001000 +{a, b} == 01001001 +{a, b} == 01001010 +{a, b} == 01001011 +{a, b} == 01001100 +{a, b} == 01001101 +{a, b} == 01001110 +{a, b} == 01010000 +{a, b} == 01010001 +{a, b} == 01010010 +{a, b} == 01010011 +{a, b} == 01010100 +{a, b} == 01010101 +{a, b} == 01010110 +{a, b} == 01010111 +{a, b} == 01011000 +{a, b} == 01011001 +{a, b} == 01011010 +{a, b} == 01011011 +{a, b} == 01011100 +{a, b} == 01011101 +{a, b} == 01011110 +{a, b} == 01100000 +{a, b} == 01100001 +{a, b} == 01100010 +{a, b} == 01100011 +{a, b} == 01100100 +{a, b} == 01100101 +{a, b} == 01100110 +{a, b} == 01100111 +{a, b} == 01101000 +{a, b} == 01101001 +{a, b} == 01101010 +{a, b} == 01101011 +{a, b} == 01101100 +{a, b} == 01101101 +{a, b} == 01101110 +{a, b} == 01110000 +{a, b} == 01110001 +{a, b} == 01110010 +{a, b} == 01110011 +{a, b} == 01110100 +{a, b} == 01110101 +{a, b} == 01110110 +{a, b} == 01110111 +{a, b} == 01111000 +{a, b} == 01111001 +{a, b} == 01111010 +{a, b} == 01111011 +{a, b} == 01111100 +{a, b} == 01111101 +{a, b} == 01111110 +{a, b} == 10000000 +{a, b} == 10000001 +{a, b} == 10000010 +{a, b} == 10000011 +{a, b} == 10000100 +{a, b} == 10000101 +{a, b} == 10000110 +{a, b} == 10000111 +{a, b} == 10001000 +{a, b} == 10001001 +{a, b} == 10001010 +{a, b} == 10001011 +{a, b} == 10001100 +{a, b} == 10001101 +{a, b} == 10001110 +{a, b} == 10010000 +{a, b} == 10010001 +{a, b} == 10010010 +{a, b} == 10010011 +{a, b} == 10010100 +{a, b} == 10010101 +{a, b} == 10010110 +{a, b} == 10010111 +{a, b} == 10011000 +{a, b} == 10011001 +{a, b} == 10011010 +{a, b} == 10011011 +{a, b} == 10011100 +{a, b} == 10011101 +{a, b} == 10011110 +{a, b} == 10100000 +{a, b} == 10100001 +{a, b} == 10100010 +{a, b} == 10100011 +{a, b} == 10100100 +{a, b} == 10100101 +{a, b} == 10100110 +{a, b} == 10100111 +{a, b} == 10101000 +{a, b} == 10101001 +{a, b} == 10101010 +{a, b} == 10101011 +{a, b} == 10101100 +{a, b} == 10101101 +{a, b} == 10101110 +{a, b} == 10110000 +{a, b} == 10110001 +{a, b} == 10110010 +{a, b} == 10110011 +{a, b} == 10110100 +{a, b} == 10110101 +{a, b} == 10110110 +{a, b} == 10110111 +{a, b} == 10111000 +{a, b} == 10111001 +{a, b} == 10111010 +{a, b} == 10111011 +{a, b} == 10111100 +{a, b} == 10111101 +{a, b} == 10111110 +{a, b} == 11000000 +{a, b} == 11000001 +{a, b} == 11000010 +{a, b} == 11000011 +{a, b} == 11000100 +{a, b} == 11000101 +{a, b} == 11000110 +{a, b} == 11000111 +{a, b} == 11001000 +{a, b} == 11001001 +{a, b} == 11001010 +{a, b} == 11001011 +{a, b} == 11001100 +{a, b} == 11001101 +{a, b} == 11001110 +{a, b} == 11010000 +{a, b} == 11010001 +{a, b} == 11010010 +{a, b} == 11010011 +{a, b} == 11010100 +{a, b} == 11010101 +{a, b} == 11010110 +{a, b} == 11010111 +{a, b} == 11011000 +{a, b} == 11011001 +{a, b} == 11011010 +{a, b} == 11011011 +{a, b} == 11011100 +{a, b} == 11011101 +{a, b} == 11011110 +{a, b} == 11100000 +{a, b} == 11100001 +{a, b} == 11100010 +{a, b} == 11100011 +{a, b} == 11100100 +{a, b} == 11100101 +{a, b} == 11100110 +{a, b} == 11100111 +{a, b} == 11101000 +{a, b} == 11101001 +{a, b} == 11101010 +{a, b} == 11101011 +{a, b} == 11101100 +{a, b} == 11101101 +{a, b} == 11101110 diff --git a/ivtest/gold/stime.gold b/ivtest/gold/stime.gold new file mode 100644 index 000000000..fcf43700a --- /dev/null +++ b/ivtest/gold/stime.gold @@ -0,0 +1,3 @@ +$simtime: 4026531840, $time: 4026531840, $stime: 4026531840 +$simtime: 4294967296, $time: 4294967296, $stime: 0 +$simtime: 8321499136, $time: 8321499136, $stime: 4026531840 diff --git a/ivtest/gold/string10.gold b/ivtest/gold/string10.gold new file mode 100644 index 000000000..3c62d8c24 --- /dev/null +++ b/ivtest/gold/string10.gold @@ -0,0 +1,24 @@ +============================ +>|This is a test| +*|This is a test| +*|This is a test| +>| 65| +*| 65| +>|16706| +*|16706| +>| 4276803| +*| 4276803| +>|1094861636| +*|1094861636| +>|01000001| +*|01000001| +>|01000001010000100100001101000100| +*|01000001010000100100001101000100| +>|01000001010000100100001101000100010010000100100101001010010010110100110001001101010011100100111101010000010100010101001001010011| +*|01000001010000100100001101000100010010000100100101001010010010110100110001001101010011100100111101010000010100010101001001010011| +>|41| +*|41| +>|41424344| +*|41424344| +>|4142434448494a4b4c4d4e4f50515253| +*|4142434448494a4b4c4d4e4f50515253| diff --git a/ivtest/gold/string11.gold b/ivtest/gold/string11.gold new file mode 100644 index 000000000..5ac690f7c --- /dev/null +++ b/ivtest/gold/string11.gold @@ -0,0 +1 @@ +bytes=4142430a diff --git a/ivtest/gold/string4.gold b/ivtest/gold/string4.gold new file mode 100644 index 000000000..330457d6d --- /dev/null +++ b/ivtest/gold/string4.gold @@ -0,0 +1,2 @@ + hi +Mes1 diff --git a/ivtest/gold/string5.gold b/ivtest/gold/string5.gold new file mode 100644 index 000000000..4153cf6b4 --- /dev/null +++ b/ivtest/gold/string5.gold @@ -0,0 +1 @@ + Hello world of Verilog diff --git a/ivtest/gold/string7.gold b/ivtest/gold/string7.gold new file mode 100644 index 000000000..ab21ee629 --- /dev/null +++ b/ivtest/gold/string7.gold @@ -0,0 +1,27 @@ +============================ myReg8 = 65 +>|A| +*|A| +============================ myReg40 = "12345" +>|12345| +*|12345| +>|5| +*|5| +============================ myReg40r = "12345" +>|12345| +*|12345| +>|1| +*|1| +============================ myReg39r = "12345" +>|12345| +*|12345| +>|b| +*|b| +============================ myReg14 = 65 +>| A| +*| A| +============================ myReg14 = 33*356+65 +>|!A| +*|!A| +============================ myInt = 65 +>| A| +*| A| diff --git a/ivtest/gold/string8.gold b/ivtest/gold/string8.gold new file mode 100644 index 000000000..619236e71 --- /dev/null +++ b/ivtest/gold/string8.gold @@ -0,0 +1,8 @@ +============================ myReg14 = 33*256+65 +>|!A| +*|!A| +>|!| +*|!| +============================ myReg16 = 33*512+65*2 +>|!A| +*|!A| diff --git a/ivtest/gold/string9.gold b/ivtest/gold/string9.gold new file mode 100644 index 000000000..7766a086b --- /dev/null +++ b/ivtest/gold/string9.gold @@ -0,0 +1,26 @@ +============================ myReg8 = 65 +>|A| +*|A| +============================ myReg40 = "12345" +>|5| +*|5| +>|5| +*|5| +============================ myReg40r = "12345" +>|5| +*|5| +>|1| +*|1| +============================ myReg39r = "12345" +>|5| +*|5| +>|b| +*|b| +============================ myReg14 = 33*256+65 +>|A| +*|A| +>|!| +*|!| +============================ myInt = 66*256 + 65 +>|A| +*|A| diff --git a/ivtest/gold/string_events.gold b/ivtest/gold/string_events.gold new file mode 100644 index 000000000..1a2f4b8ff --- /dev/null +++ b/ivtest/gold/string_events.gold @@ -0,0 +1,10 @@ +str = hello +str = world +str1 = hello1 +str2 = hello2 +str1 = world1 +str2 = world2 +str1 = world1 +str2 = world2 +str1 = hello1 +str2 = hello2 diff --git a/ivtest/gold/sv_default_port_value3.gold b/ivtest/gold/sv_default_port_value3.gold new file mode 100644 index 000000000..94a31424e --- /dev/null +++ b/ivtest/gold/sv_default_port_value3.gold @@ -0,0 +1,3 @@ +./ivltests/sv_default_port_value3.v:3: error: A reference to a wire or reg (`v') is not allowed in a constant expression. +./ivltests/sv_default_port_value3.v:3: error: Failed to elaborate port default value. +2 error(s) during elaboration. diff --git a/ivtest/gold/sv_deferred_assert1.gold b/ivtest/gold/sv_deferred_assert1.gold new file mode 100644 index 000000000..d91d56079 --- /dev/null +++ b/ivtest/gold/sv_deferred_assert1.gold @@ -0,0 +1,8 @@ +./ivltests/sv_deferred_assert1.v:8: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assert1.v:9: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assert1.v:10: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assert1.v:11: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assert1.v:12: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assert1.v:13: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assert1.v:14: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assert1.v:16: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. diff --git a/ivtest/gold/sv_deferred_assert2.gold b/ivtest/gold/sv_deferred_assert2.gold new file mode 100644 index 000000000..bbee0b8df --- /dev/null +++ b/ivtest/gold/sv_deferred_assert2.gold @@ -0,0 +1,8 @@ +./ivltests/sv_deferred_assert2.v:8: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assert2.v:9: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assert2.v:10: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assert2.v:11: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assert2.v:12: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assert2.v:13: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assert2.v:14: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assert2.v:16: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. diff --git a/ivtest/gold/sv_deferred_assume1.gold b/ivtest/gold/sv_deferred_assume1.gold new file mode 100644 index 000000000..785d730a1 --- /dev/null +++ b/ivtest/gold/sv_deferred_assume1.gold @@ -0,0 +1,8 @@ +./ivltests/sv_deferred_assume1.v:8: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assume1.v:9: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assume1.v:10: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assume1.v:11: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assume1.v:12: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assume1.v:13: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assume1.v:14: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assume1.v:16: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. diff --git a/ivtest/gold/sv_deferred_assume2.gold b/ivtest/gold/sv_deferred_assume2.gold new file mode 100644 index 000000000..cba99fd82 --- /dev/null +++ b/ivtest/gold/sv_deferred_assume2.gold @@ -0,0 +1,8 @@ +./ivltests/sv_deferred_assume2.v:8: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assume2.v:9: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assume2.v:10: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assume2.v:11: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assume2.v:12: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assume2.v:13: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assume2.v:14: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. +./ivltests/sv_deferred_assume2.v:16: sorry: Deferred assertions are not supported. Try -gno-assertions or -gsupported-assertions to turn this message off. diff --git a/ivtest/gold/sv_end_label_fail.gold b/ivtest/gold/sv_end_label_fail.gold new file mode 100644 index 000000000..6c1b2492b --- /dev/null +++ b/ivtest/gold/sv_end_label_fail.gold @@ -0,0 +1,15 @@ +./ivltests/sv_end_label_fail.v:4: error: End label doesn't match begin name +./ivltests/sv_end_label_fail.v:7: error: End label doesn't match fork name +./ivltests/sv_end_label_fail.v:10: error: End label doesn't match fork name +./ivltests/sv_end_label_fail.v:13: error: End label doesn't match fork name +./ivltests/sv_end_label_fail.v:16: error: End label doesn't match task name +./ivltests/sv_end_label_fail.v:19: error: End label doesn't match task name +./ivltests/sv_end_label_fail.v:23: error: End label doesn't match function name +./ivltests/sv_end_label_fail.v:26: error: End label doesn't match function name +./ivltests/sv_end_label_fail.v:28: error: End label doesn't match module name. +./ivltests/sv_end_label_fail.v:38: error: End label doesn't match begin name +./ivltests/sv_end_label_fail.v:40: error: End label doesn't match module name. +./ivltests/sv_end_label_fail.v:43: error: End label doesn't match package name +./ivltests/sv_end_label_fail.v:47: error: Class end label doesn't match class name. +./ivltests/sv_end_label_fail.v:48: error: End label doesn't match program name. +./ivltests/sv_end_label_fail.v:64: error: End label doesn't match primitive name diff --git a/ivtest/gold/sv_end_labels_bad.gold b/ivtest/gold/sv_end_labels_bad.gold new file mode 100644 index 000000000..4e98a1ce8 --- /dev/null +++ b/ivtest/gold/sv_end_labels_bad.gold @@ -0,0 +1,2 @@ +./ivltests/sv_end_labels_bad.v:14: error: End label doesn't match begin name +./ivltests/sv_end_labels_bad.v:16: error: End label doesn't match module name. diff --git a/ivtest/gold/sv_immediate_assert-vlog95.gold b/ivtest/gold/sv_immediate_assert-vlog95.gold new file mode 100644 index 000000000..2d548ff30 --- /dev/null +++ b/ivtest/gold/sv_immediate_assert-vlog95.gold @@ -0,0 +1,8 @@ +ERROR: vlog95.v:24: + Time: 0 Scope: test +Check 4 : this should be displayed +Check 5 : this should be displayed +ERROR: vlog95.v:32: + Time: 0 Scope: test +Check 7 : this should be displayed +Check 8 : this should be displayed diff --git a/ivtest/gold/sv_immediate_assert.gold b/ivtest/gold/sv_immediate_assert.gold new file mode 100644 index 000000000..3eed78c91 --- /dev/null +++ b/ivtest/gold/sv_immediate_assert.gold @@ -0,0 +1,8 @@ +ERROR: ./ivltests/sv_immediate_assert.v:7: + Time: 0 Scope: test +Check 4 : this should be displayed +Check 5 : this should be displayed +ERROR: ./ivltests/sv_immediate_assert.v:11: + Time: 0 Scope: test +Check 7 : this should be displayed +Check 8 : this should be displayed diff --git a/ivtest/gold/sv_immediate_assume-vlog95.gold b/ivtest/gold/sv_immediate_assume-vlog95.gold new file mode 100644 index 000000000..2d548ff30 --- /dev/null +++ b/ivtest/gold/sv_immediate_assume-vlog95.gold @@ -0,0 +1,8 @@ +ERROR: vlog95.v:24: + Time: 0 Scope: test +Check 4 : this should be displayed +Check 5 : this should be displayed +ERROR: vlog95.v:32: + Time: 0 Scope: test +Check 7 : this should be displayed +Check 8 : this should be displayed diff --git a/ivtest/gold/sv_immediate_assume.gold b/ivtest/gold/sv_immediate_assume.gold new file mode 100644 index 000000000..bd642991a --- /dev/null +++ b/ivtest/gold/sv_immediate_assume.gold @@ -0,0 +1,8 @@ +ERROR: ./ivltests/sv_immediate_assume.v:7: + Time: 0 Scope: test +Check 4 : this should be displayed +Check 5 : this should be displayed +ERROR: ./ivltests/sv_immediate_assume.v:11: + Time: 0 Scope: test +Check 7 : this should be displayed +Check 8 : this should be displayed diff --git a/ivtest/gold/sv_macro2.gold b/ivtest/gold/sv_macro2.gold new file mode 100644 index 000000000..9a22636dc --- /dev/null +++ b/ivtest/gold/sv_macro2.gold @@ -0,0 +1 @@ +left side: "right side" diff --git a/ivtest/gold/sv_macro3.gold b/ivtest/gold/sv_macro3.gold new file mode 100644 index 000000000..035a99af1 --- /dev/null +++ b/ivtest/gold/sv_macro3.gold @@ -0,0 +1,3 @@ +` +my_prefix_my_suffix +my_prefix_my_suffix diff --git a/ivtest/gold/sv_new_array_error.gold b/ivtest/gold/sv_new_array_error.gold new file mode 100644 index 000000000..395a6f039 --- /dev/null +++ b/ivtest/gold/sv_new_array_error.gold @@ -0,0 +1,2 @@ +./ivltests/sv_new_array_error.v:3: error: The new array constructor may only be used in an assignment to a dynamic array. +Elaboration failed diff --git a/ivtest/gold/sv_pkg_class.gold b/ivtest/gold/sv_pkg_class.gold new file mode 100644 index 000000000..dfee0c599 --- /dev/null +++ b/ivtest/gold/sv_pkg_class.gold @@ -0,0 +1,2 @@ +This is class 2. +This is class 1. diff --git a/ivtest/gold/sv_queue_real.gold b/ivtest/gold/sv_queue_real.gold new file mode 100644 index 000000000..035f8f17c --- /dev/null +++ b/ivtest/gold/sv_queue_real.gold @@ -0,0 +1,16 @@ +./ivltests/sv_queue_real.v:32: Warning: skipping delete(0) on empty queue. +./ivltests/sv_queue_real.v:36: Warning: pop_front() on empty queue. +./ivltests/sv_queue_real.v:42: Warning: pop_back() on empty queue. +./ivltests/sv_queue_real.v:53: Warning: skipping out of range delete(3) on queue of size 3. +./ivltests/sv_queue_real.v:54: Warning: skipping queue delete() with negative index. +./ivltests/sv_queue_real.v:55: Warning: skipping queue delete() with undefined index. +./ivltests/sv_queue_real.v:129: Warning: cannot assign to a negative queue index (-1). 10 was not added. +./ivltests/sv_queue_real.v:130: Warning: cannot assign to an undefined queue index. 10 was not added. +./ivltests/sv_queue_real.v:131: Warning: assigning to queue[4] is outside of size (3). 10 was not added. +./ivltests/sv_queue_real.v:134: Warning: cannot assign to a negative queue index (-1). 10 was not added. +./ivltests/sv_queue_real.v:136: Warning: cannot assign to an undefined queue index. 10 was not added. +./ivltests/sv_queue_real.v:138: Warning: assigning to queue[4] is outside of size (3). 10 was not added. +./ivltests/sv_queue_real.v:150: Warning: cannot insert at a negative queue index (-1). 10 was not added. +./ivltests/sv_queue_real.v:151: Warning: cannot insert at an undefined queue index. 10 was not added. +./ivltests/sv_queue_real.v:152: Warning: inserting to queue[5] is outside of size (4). 10 was not added. +PASSED diff --git a/ivtest/gold/sv_queue_real_bounded.gold b/ivtest/gold/sv_queue_real_bounded.gold new file mode 100644 index 000000000..fa9927bda --- /dev/null +++ b/ivtest/gold/sv_queue_real_bounded.gold @@ -0,0 +1,9 @@ +./ivltests/sv_queue_real_bounded.v:58: Warning: Array pattern assignment has more elements (4) than bounded queue 'q_tst' supports (3). + Only using first 3 elements. +./ivltests/sv_queue_real_bounded.v:35: Warning: push_back(100) skipped for already full bounded queue [3]. +./ivltests/sv_queue_real_bounded.v:42: Warning: push_front(0.5) removed 3 from already full bounded queue [3]. +./ivltests/sv_queue_real_bounded.v:43: Warning: assigning to queue[3] is outside bound (3). 3 was not added. +./ivltests/sv_queue_real_bounded.v:50: Warning: inserting to queue[3] is outside bound (3). 10 was not added. +./ivltests/sv_queue_real_bounded.v:51: Warning: insert(1, 2) removed 2 from already full bounded queue [3]. +./ivltests/sv_queue_real_bounded.v:66: Warning: queue is bounded to have at most 3 elements, source has 4 elements. +PASSED diff --git a/ivtest/gold/sv_queue_real_fail.gold b/ivtest/gold/sv_queue_real_fail.gold new file mode 100644 index 000000000..dd358f2b6 --- /dev/null +++ b/ivtest/gold/sv_queue_real_fail.gold @@ -0,0 +1,10 @@ +./ivltests/sv_queue_real_fail.v:4: error: queue 'q_real1' bound must be positive (-1)! +./ivltests/sv_queue_real_fail.v:5: error: queue 'q_real2' bound is undefined! +./ivltests/sv_queue_real_fail.v:6: error: A reference to a wire or reg (`bound') is not allowed in a constant expression. +./ivltests/sv_queue_real_fail.v:6: error: queue 'q_real3' bound must be a constant! +./ivltests/sv_queue_real_fail.v:9: error: size() method takes no arguments +./ivltests/sv_queue_real_fail.v:10: error: pop_front() method takes no arguments +./ivltests/sv_queue_real_fail.v:11: error: pop_back() method takes no arguments +./ivltests/sv_queue_real_fail.v:12: error: push_front() method requires a single argument. +./ivltests/sv_queue_real_fail.v:13: error: push_back() method requires a single argument. +9 error(s) during elaboration. diff --git a/ivtest/gold/sv_queue_string.gold b/ivtest/gold/sv_queue_string.gold new file mode 100644 index 000000000..66135e4fa --- /dev/null +++ b/ivtest/gold/sv_queue_string.gold @@ -0,0 +1,16 @@ +./ivltests/sv_queue_string.v:32: Warning: skipping delete(0) on empty queue. +./ivltests/sv_queue_string.v:36: Warning: pop_front() on empty queue. +./ivltests/sv_queue_string.v:42: Warning: pop_back() on empty queue. +./ivltests/sv_queue_string.v:53: Warning: skipping out of range delete(3) on queue of size 3. +./ivltests/sv_queue_string.v:54: Warning: skipping queue delete() with negative index. +./ivltests/sv_queue_string.v:55: Warning: skipping queue delete() with undefined index. +./ivltests/sv_queue_string.v:129: Warning: cannot assign to a negative queue index (-1). "Will not write" was not added. +./ivltests/sv_queue_string.v:130: Warning: cannot assign to an undefined queue index. "Will not write" was not added. +./ivltests/sv_queue_string.v:131: Warning: assigning to queue[4] is outside of size (3). "Will not write" was not added. +./ivltests/sv_queue_string.v:134: Warning: cannot assign to a negative queue index (-1). "Will not write" was not added. +./ivltests/sv_queue_string.v:136: Warning: cannot assign to an undefined queue index. "Will not write" was not added. +./ivltests/sv_queue_string.v:138: Warning: assigning to queue[4] is outside of size (3). "Will not write" was not added. +./ivltests/sv_queue_string.v:150: Warning: cannot insert at a negative queue index (-1). "Will not be added" was not added. +./ivltests/sv_queue_string.v:151: Warning: cannot insert at an undefined queue index. "Will not be added" was not added. +./ivltests/sv_queue_string.v:152: Warning: inserting to queue[5] is outside of size (4). "Will not be added" was not added. +PASSED diff --git a/ivtest/gold/sv_queue_string_bounded.gold b/ivtest/gold/sv_queue_string_bounded.gold new file mode 100644 index 000000000..9d6e93990 --- /dev/null +++ b/ivtest/gold/sv_queue_string_bounded.gold @@ -0,0 +1,9 @@ +./ivltests/sv_queue_string_bounded.v:58: Warning: Array pattern assignment has more elements (4) than bounded queue 'q_tst' supports (3). + Only using first 3 elements. +./ivltests/sv_queue_string_bounded.v:35: Warning: push_back("This will not be added") skipped for already full bounded queue [3]. +./ivltests/sv_queue_string_bounded.v:42: Warning: push_front("I say,") removed "!" from already full bounded queue [3]. +./ivltests/sv_queue_string_bounded.v:43: Warning: assigning to queue[3] is outside bound (3). "Will not be added" was not added. +./ivltests/sv_queue_string_bounded.v:50: Warning: inserting to queue[3] is outside bound (3). "Will not be added" was not added. +./ivltests/sv_queue_string_bounded.v:51: Warning: insert(1, "to you") removed "World" from already full bounded queue [3]. +./ivltests/sv_queue_string_bounded.v:67: Warning: queue is bounded to have at most 3 elements, source has 4 elements. +PASSED diff --git a/ivtest/gold/sv_queue_string_fail.gold b/ivtest/gold/sv_queue_string_fail.gold new file mode 100644 index 000000000..ed1cd7169 --- /dev/null +++ b/ivtest/gold/sv_queue_string_fail.gold @@ -0,0 +1,10 @@ +./ivltests/sv_queue_string_fail.v:4: error: queue 'q_str1' bound must be positive (-1)! +./ivltests/sv_queue_string_fail.v:5: error: queue 'q_str2' bound is undefined! +./ivltests/sv_queue_string_fail.v:6: error: A reference to a wire or reg (`bound') is not allowed in a constant expression. +./ivltests/sv_queue_string_fail.v:6: error: queue 'q_str3' bound must be a constant! +./ivltests/sv_queue_string_fail.v:9: error: size() method takes no arguments +./ivltests/sv_queue_string_fail.v:10: error: pop_front() method takes no arguments +./ivltests/sv_queue_string_fail.v:11: error: pop_back() method takes no arguments +./ivltests/sv_queue_string_fail.v:12: error: push_front() method requires a single argument. +./ivltests/sv_queue_string_fail.v:13: error: push_back() method requires a single argument. +9 error(s) during elaboration. diff --git a/ivtest/gold/sv_queue_vec.gold b/ivtest/gold/sv_queue_vec.gold new file mode 100644 index 000000000..50c32afb2 --- /dev/null +++ b/ivtest/gold/sv_queue_vec.gold @@ -0,0 +1,16 @@ +./ivltests/sv_queue_vec.v:32: Warning: skipping delete(0) on empty queue. +./ivltests/sv_queue_vec.v:36: Warning: pop_front() on empty queue. +./ivltests/sv_queue_vec.v:42: Warning: pop_back() on empty queue. +./ivltests/sv_queue_vec.v:53: Warning: skipping out of range delete(3) on queue of size 3. +./ivltests/sv_queue_vec.v:54: Warning: skipping queue delete() with negative index. +./ivltests/sv_queue_vec.v:55: Warning: skipping queue delete() with undefined index. +./ivltests/sv_queue_vec.v:129: Warning: cannot assign to a negative queue index (-1). 32'b00000000000000000000000000001010 was not added. +./ivltests/sv_queue_vec.v:130: Warning: cannot assign to an undefined queue index. 32'b00000000000000000000000000001010 was not added. +./ivltests/sv_queue_vec.v:131: Warning: assigning to queue[4] is outside of size (3). 32'b00000000000000000000000000001010 was not added. +./ivltests/sv_queue_vec.v:134: Warning: cannot assign to a negative queue index (-1). 32'b00000000000000000000000000001010 was not added. +./ivltests/sv_queue_vec.v:136: Warning: cannot assign to an undefined queue index. 32'b00000000000000000000000000001010 was not added. +./ivltests/sv_queue_vec.v:138: Warning: assigning to queue[4] is outside of size (3). 32'b00000000000000000000000000001010 was not added. +./ivltests/sv_queue_vec.v:150: Warning: cannot insert at a negative queue index (-1). 32'b00000000000000000000000000001010 was not added. +./ivltests/sv_queue_vec.v:151: Warning: cannot insert at an undefined queue index. 32'b00000000000000000000000000001010 was not added. +./ivltests/sv_queue_vec.v:152: Warning: inserting to queue[5] is outside of size (4). 32'b00000000000000000000000000001010 was not added. +PASSED diff --git a/ivtest/gold/sv_queue_vec_bounded.gold b/ivtest/gold/sv_queue_vec_bounded.gold new file mode 100644 index 000000000..2490d2b93 --- /dev/null +++ b/ivtest/gold/sv_queue_vec_bounded.gold @@ -0,0 +1,9 @@ +./ivltests/sv_queue_vec_bounded.v:58: Warning: Array pattern assignment has more elements (4) than bounded queue 'q_tst' supports (3). + Only using first 3 elements. +./ivltests/sv_queue_vec_bounded.v:35: Warning: push_back(32'b00000000000000000000000001100100) skipped for already full bounded queue [3]. +./ivltests/sv_queue_vec_bounded.v:42: Warning: push_front(32'b00000000000000000000000000000101) removed 32'b00000000000000000000000000000011 from already full bounded queue [3]. +./ivltests/sv_queue_vec_bounded.v:43: Warning: assigning to queue[3] is outside bound (3). 32'b00000000000000000000000000000011 was not added. +./ivltests/sv_queue_vec_bounded.v:50: Warning: inserting to queue[3] is outside bound (3). 32'b00000000000000000000000000001010 was not added. +./ivltests/sv_queue_vec_bounded.v:51: Warning: insert(1, 32'b00000000000000000000000000000010) removed 32'b00000000000000000000000000000010 from already full bounded queue [3]. +./ivltests/sv_queue_vec_bounded.v:66: Warning: queue is bounded to have at most 3 elements, source has 4 elements. +PASSED diff --git a/ivtest/gold/sv_queue_vec_fail.gold b/ivtest/gold/sv_queue_vec_fail.gold new file mode 100644 index 000000000..21080cf7a --- /dev/null +++ b/ivtest/gold/sv_queue_vec_fail.gold @@ -0,0 +1,10 @@ +./ivltests/sv_queue_vec_fail.v:4: error: queue 'q_vec1' bound must be positive (-1)! +./ivltests/sv_queue_vec_fail.v:5: error: queue 'q_vec2' bound is undefined! +./ivltests/sv_queue_vec_fail.v:6: error: A reference to a wire or reg (`bound') is not allowed in a constant expression. +./ivltests/sv_queue_vec_fail.v:6: error: queue 'q_vec3' bound must be a constant! +./ivltests/sv_queue_vec_fail.v:9: error: size() method takes no arguments +./ivltests/sv_queue_vec_fail.v:10: error: pop_front() method takes no arguments +./ivltests/sv_queue_vec_fail.v:11: error: pop_back() method takes no arguments +./ivltests/sv_queue_vec_fail.v:12: error: push_front() method requires a single argument. +./ivltests/sv_queue_vec_fail.v:13: error: push_back() method requires a single argument. +9 error(s) during elaboration. diff --git a/ivtest/gold/sv_root_class.gold b/ivtest/gold/sv_root_class.gold new file mode 100644 index 000000000..dfee0c599 --- /dev/null +++ b/ivtest/gold/sv_root_class.gold @@ -0,0 +1,2 @@ +This is class 2. +This is class 1. diff --git a/ivtest/gold/sv_root_func.gold b/ivtest/gold/sv_root_func.gold new file mode 100644 index 000000000..eabb387a5 --- /dev/null +++ b/ivtest/gold/sv_root_func.gold @@ -0,0 +1,2 @@ +this is func 2. +this is func 1. diff --git a/ivtest/gold/sv_root_task.gold b/ivtest/gold/sv_root_task.gold new file mode 100644 index 000000000..930d540e5 --- /dev/null +++ b/ivtest/gold/sv_root_task.gold @@ -0,0 +1,2 @@ +This is task 2. +This is task 1. diff --git a/ivtest/gold/sv_timeunit_prec3a.gold b/ivtest/gold/sv_timeunit_prec3a.gold new file mode 100644 index 000000000..8d7ffba6d --- /dev/null +++ b/ivtest/gold/sv_timeunit_prec3a.gold @@ -0,0 +1,28 @@ +Time scale of (check_100s) is 100s / 100s +Time scale of (check_10s) is 10s / 10s +Time scale of (check_1s) is 1s / 1s +Time scale of (check_100ms) is 100ms / 100ms +Time scale of (check_10ms) is 10ms / 10ms +Time scale of (check_1ms) is 1ms / 1ms +Time scale of (check_100us) is 100us / 100us +Time scale of (check_10us) is 10us / 10us +Time scale of (check_1us) is 1us / 1us +Time scale of (check_100ns) is 100ns / 100ns +Time scale of (check_10ns) is 10ns / 10ns +Time scale of (check_1ns) is 1ns / 1ns +Time scale of (check_100ps) is 100ps / 100ps +Time scale of (check_10ps) is 10ps / 10ps +Time scale of (check_1ps) is 1ps / 1ps +Time scale of (check_100fs) is 100fs / 100fs +Time scale of (check_10fs) is 10fs / 10fs +Time scale of (check_1fs) is 1fs / 1fs + +Time scale of (check_tu) is 10us / 1us +Time scale of (check_tp) is 100us / 10us +Time scale of (check_tup) is 10us / 10us +Time scale of (check_tpu) is 10us / 10us + +Time scale of (check_tu_d) is 10us / 1us +Time scale of (check_tp_d) is 100us / 10us +Time scale of (check_tup_d) is 10us / 10us +Time scale of (check_tpu_d) is 10us / 10us diff --git a/ivtest/gold/sv_timeunit_prec3b.gold b/ivtest/gold/sv_timeunit_prec3b.gold new file mode 100644 index 000000000..69e8fe6d3 --- /dev/null +++ b/ivtest/gold/sv_timeunit_prec3b.gold @@ -0,0 +1,9 @@ +Time scale of (check_tu_nest) is 10us / 1us +Time scale of (check_tp_nest) is 100us / 10us +Time scale of (check_tup_nest) is 10us / 10us +Time scale of (check_tpu_nest) is 10us / 10us + +Time scale of (check_tu_nest.nested) is 100us / 1us +Time scale of (check_tp_nest.nested) is 100us / 1us +Time scale of (check_tup_nest.nested) is 100us / 1us +Time scale of (check_tpu_nest.nested) is 100us / 1us diff --git a/ivtest/gold/sv_timeunit_prec3c.gold b/ivtest/gold/sv_timeunit_prec3c.gold new file mode 100644 index 000000000..66bff8298 --- /dev/null +++ b/ivtest/gold/sv_timeunit_prec3c.gold @@ -0,0 +1,2 @@ +Time scale of (gtp_ltu1) is 1ns / 10ps +Time scale of (gtp_ltu2) is 1us / 10ps diff --git a/ivtest/gold/sv_timeunit_prec3d.gold b/ivtest/gold/sv_timeunit_prec3d.gold new file mode 100644 index 000000000..986a130ef --- /dev/null +++ b/ivtest/gold/sv_timeunit_prec3d.gold @@ -0,0 +1,2 @@ +Time scale of (gtu_ltp1) is 10s / 10ps +Time scale of (gtu_ltp2) is 10s / 1ns diff --git a/ivtest/gold/sv_timeunit_prec4a.gold b/ivtest/gold/sv_timeunit_prec4a.gold new file mode 100644 index 000000000..3d286b221 --- /dev/null +++ b/ivtest/gold/sv_timeunit_prec4a.gold @@ -0,0 +1,21 @@ +Time scale of (check_100s) is 100s / 100s +Time scale of (check_10s) is 10s / 10s +Time scale of (check_1s) is 1s / 1s +Time scale of (check_100ms) is 100ms / 100ms +Time scale of (check_10ms) is 10ms / 10ms +Time scale of (check_1ms) is 1ms / 1ms +Time scale of (check_100us) is 100us / 100us +Time scale of (check_10us) is 10us / 10us +Time scale of (check_1us) is 1us / 1us +Time scale of (check_100ns) is 100ns / 100ns +Time scale of (check_10ns) is 10ns / 10ns +Time scale of (check_1ns) is 1ns / 1ns +Time scale of (check_100ps) is 100ps / 100ps +Time scale of (check_10ps) is 10ps / 10ps +Time scale of (check_1ps) is 1ps / 1ps +Time scale of (check_100fs) is 100fs / 100fs +Time scale of (check_10fs) is 10fs / 10fs +Time scale of (check_1fs) is 1fs / 1fs + +Time scale of (check_tup) is 10us / 10us +Time scale of (check_tup_d) is 10us / 10us diff --git a/ivtest/gold/sv_timeunit_prec4b.gold b/ivtest/gold/sv_timeunit_prec4b.gold new file mode 100644 index 000000000..fcb7e1194 --- /dev/null +++ b/ivtest/gold/sv_timeunit_prec4b.gold @@ -0,0 +1,2 @@ +Time scale of (check_tup_nest) is 10us / 10us +Time scale of (check_tup_nest.nested) is 100us / 1us diff --git a/ivtest/gold/sv_timeunit_prec_fail1-v10.gold b/ivtest/gold/sv_timeunit_prec_fail1-v10.gold new file mode 100644 index 000000000..56d0a3a9f --- /dev/null +++ b/ivtest/gold/sv_timeunit_prec_fail1-v10.gold @@ -0,0 +1,18 @@ +./ivltests/sv_timeunit_prec_fail1a.v:15: error: repeat timeunit does not match the initial module timeunit declaration. +./ivltests/sv_timeunit_prec_fail1a.v:21: error: repeat timeprecision does not match the initial module timeprecision declaration. +./ivltests/sv_timeunit_prec_fail1a.v:27: error: repeat timeunit found and the initial module timeunit is missing. +./ivltests/sv_timeunit_prec_fail1a.v:33: error: repeat timeprecision found and the initial module timeprecision is missing. +./ivltests/sv_timeunit_prec_fail1a.v:40: error: repeat timeprecision found and the initial module timeprecision is missing. +./ivltests/sv_timeunit_prec_fail1a.v:47: error: repeat timeunit found and the initial module timeunit is missing. +./ivltests/sv_timeunit_prec_fail1a.v:53: Invalid timeunit constant (1st digit). +./ivltests/sv_timeunit_prec_fail1a.v:54: Invalid timeprecision constant (1st digit). +./ivltests/sv_timeunit_prec_fail1a.v:56: Invalid timeunit constant (number of zeros). +./ivltests/sv_timeunit_prec_fail1a.v:57: Invalid timeprecision constant (number of zeros). +./ivltests/sv_timeunit_prec_fail1a.v:59: Invalid timeunit scale '2s'. +./ivltests/sv_timeunit_prec_fail1a.v:60: Invalid timeprecision scale '2s'. +./ivltests/sv_timeunit_prec_fail1a.v:63: Invalid timeunit constant ('_' is not supported). +./ivltests/sv_timeunit_prec_fail1a.v:64: Invalid timeprecision constant ('_' is not supported). +./ivltests/sv_timeunit_prec_fail1b.v:5: error: a timeprecision is missing or is too large! +./ivltests/sv_timeunit_prec_fail1c.v:6: error: a timeprecision is missing or is too large! +./ivltests/sv_timeunit_prec_fail1d.v:5: error: a timeprecision is missing or is too large! +./ivltests/sv_timeunit_prec_fail1e.v:5: error: a timeprecision is missing or is too large! diff --git a/ivtest/gold/sv_timeunit_prec_fail1.gold b/ivtest/gold/sv_timeunit_prec_fail1.gold new file mode 100644 index 000000000..398fd2552 --- /dev/null +++ b/ivtest/gold/sv_timeunit_prec_fail1.gold @@ -0,0 +1,20 @@ +./ivltests/sv_timeunit_prec_fail1a.v:9: error: repeat timeunit does not match the initial timeunit for this scope. +./ivltests/sv_timeunit_prec_fail1a.v:10: error: repeat timeprecision does not match the initial timeprecision for this scope. +./ivltests/sv_timeunit_prec_fail1a.v:15: error: repeat timeunit does not match the initial timeunit for this scope. +./ivltests/sv_timeunit_prec_fail1a.v:21: error: repeat timeprecision does not match the initial timeprecision for this scope. +./ivltests/sv_timeunit_prec_fail1a.v:27: error: repeat timeunit found and the initial timeunit for this scope is missing. +./ivltests/sv_timeunit_prec_fail1a.v:33: error: repeat timeprecision found and the initial timeprecision for this scope is missing. +./ivltests/sv_timeunit_prec_fail1a.v:40: error: repeat timeprecision found and the initial timeprecision for this scope is missing. +./ivltests/sv_timeunit_prec_fail1a.v:47: error: repeat timeunit found and the initial timeunit for this scope is missing. +./ivltests/sv_timeunit_prec_fail1a.v:53: Invalid timeunit constant (1st digit). +./ivltests/sv_timeunit_prec_fail1a.v:54: Invalid timeprecision constant (1st digit). +./ivltests/sv_timeunit_prec_fail1a.v:56: Invalid timeunit constant (number of zeros). +./ivltests/sv_timeunit_prec_fail1a.v:57: Invalid timeprecision constant (number of zeros). +./ivltests/sv_timeunit_prec_fail1a.v:59: Invalid timeunit scale '2s'. +./ivltests/sv_timeunit_prec_fail1a.v:60: Invalid timeprecision scale '2s'. +./ivltests/sv_timeunit_prec_fail1a.v:63: Invalid timeunit constant ('_' is not supported). +./ivltests/sv_timeunit_prec_fail1a.v:64: Invalid timeprecision constant ('_' is not supported). +./ivltests/sv_timeunit_prec_fail1b.v:4: error: a timeprecision is missing or is too large! +./ivltests/sv_timeunit_prec_fail1c.v:4: error: a timeprecision is missing or is too large! +./ivltests/sv_timeunit_prec_fail1d.v:5: error: a timeprecision is missing or is too large! +./ivltests/sv_timeunit_prec_fail1e.v:5: error: a timeprecision is missing or is too large! diff --git a/ivtest/gold/sv_timeunit_prec_fail2-v10.gold b/ivtest/gold/sv_timeunit_prec_fail2-v10.gold new file mode 100644 index 000000000..5a1d00390 --- /dev/null +++ b/ivtest/gold/sv_timeunit_prec_fail2-v10.gold @@ -0,0 +1,18 @@ +./ivltests/sv_timeunit_prec_fail2a.v:13: error: repeat timeunit does not match the initial module timeunit declaration. +./ivltests/sv_timeunit_prec_fail2a.v:13: error: repeat timeprecision does not match the initial module timeprecision declaration. +./ivltests/sv_timeunit_prec_fail2a.v:14: error: repeat timeunit does not match the initial module timeunit declaration. +./ivltests/sv_timeunit_prec_fail2a.v:15: error: repeat timeprecision does not match the initial module timeprecision declaration. +./ivltests/sv_timeunit_prec_fail2a.v:21: error: repeat timeunit found and the initial module timeunit is missing. +./ivltests/sv_timeunit_prec_fail2a.v:21: error: repeat timeprecision found and the initial module timeprecision is missing. +./ivltests/sv_timeunit_prec_fail2a.v:27: error: repeat timeprecision found and the initial module timeprecision is missing. +./ivltests/sv_timeunit_prec_fail2a.v:33: error: repeat timeunit found and the initial module timeunit is missing. +./ivltests/sv_timeunit_prec_fail2a.v:39: Invalid timeunit constant (1st digit). +./ivltests/sv_timeunit_prec_fail2a.v:39: Invalid timeprecision constant (1st digit). +./ivltests/sv_timeunit_prec_fail2a.v:41: Invalid timeunit constant (number of zeros). +./ivltests/sv_timeunit_prec_fail2a.v:41: Invalid timeprecision constant (number of zeros). +./ivltests/sv_timeunit_prec_fail2a.v:43: Invalid timeunit scale '2s'. +./ivltests/sv_timeunit_prec_fail2a.v:43: Invalid timeprecision scale '2s'. +./ivltests/sv_timeunit_prec_fail2a.v:46: Invalid timeunit constant ('_' is not supported). +./ivltests/sv_timeunit_prec_fail2a.v:46: Invalid timeprecision constant ('_' is not supported). +./ivltests/sv_timeunit_prec_fail2b.v:5: error: a timeprecision is missing or is too large! +./ivltests/sv_timeunit_prec_fail2c.v:4: error: a timeprecision is missing or is too large! diff --git a/ivtest/gold/sv_timeunit_prec_fail2.gold b/ivtest/gold/sv_timeunit_prec_fail2.gold new file mode 100644 index 000000000..7ccd2b8aa --- /dev/null +++ b/ivtest/gold/sv_timeunit_prec_fail2.gold @@ -0,0 +1,20 @@ +./ivltests/sv_timeunit_prec_fail2a.v:8: error: repeat timeunit does not match the initial timeunit for this scope. +./ivltests/sv_timeunit_prec_fail2a.v:8: error: repeat timeprecision does not match the initial timeprecision for this scope. +./ivltests/sv_timeunit_prec_fail2a.v:13: error: repeat timeunit does not match the initial timeunit for this scope. +./ivltests/sv_timeunit_prec_fail2a.v:13: error: repeat timeprecision does not match the initial timeprecision for this scope. +./ivltests/sv_timeunit_prec_fail2a.v:14: error: repeat timeunit does not match the initial timeunit for this scope. +./ivltests/sv_timeunit_prec_fail2a.v:15: error: repeat timeprecision does not match the initial timeprecision for this scope. +./ivltests/sv_timeunit_prec_fail2a.v:21: error: repeat timeunit found and the initial timeunit for this scope is missing. +./ivltests/sv_timeunit_prec_fail2a.v:21: error: repeat timeprecision found and the initial timeprecision for this scope is missing. +./ivltests/sv_timeunit_prec_fail2a.v:27: error: repeat timeprecision found and the initial timeprecision for this scope is missing. +./ivltests/sv_timeunit_prec_fail2a.v:33: error: repeat timeunit found and the initial timeunit for this scope is missing. +./ivltests/sv_timeunit_prec_fail2a.v:39: Invalid timeunit constant (1st digit). +./ivltests/sv_timeunit_prec_fail2a.v:39: Invalid timeprecision constant (1st digit). +./ivltests/sv_timeunit_prec_fail2a.v:41: Invalid timeunit constant (number of zeros). +./ivltests/sv_timeunit_prec_fail2a.v:41: Invalid timeprecision constant (number of zeros). +./ivltests/sv_timeunit_prec_fail2a.v:43: Invalid timeunit scale '2s'. +./ivltests/sv_timeunit_prec_fail2a.v:43: Invalid timeprecision scale '2s'. +./ivltests/sv_timeunit_prec_fail2a.v:46: Invalid timeunit constant ('_' is not supported). +./ivltests/sv_timeunit_prec_fail2a.v:46: Invalid timeprecision constant ('_' is not supported). +./ivltests/sv_timeunit_prec_fail2b.v:4: error: a timeprecision is missing or is too large! +./ivltests/sv_timeunit_prec_fail2c.v:5: error: a timeprecision is missing or is too large! diff --git a/ivtest/gold/sv_unit1b.gold b/ivtest/gold/sv_unit1b.gold new file mode 100644 index 000000000..a4549d81e --- /dev/null +++ b/ivtest/gold/sv_unit1b.gold @@ -0,0 +1,8 @@ +test1 macro1 = 1 +test1 macro2 = 12 +test1 macro3 = 13 +test1 wire = 1 +test2 macro1 = 21 +test2 macro2 = 12 +test2 macro3 = 13 +test2 wire = 1 diff --git a/ivtest/gold/sv_unit1c.gold b/ivtest/gold/sv_unit1c.gold new file mode 100644 index 000000000..23b48d714 --- /dev/null +++ b/ivtest/gold/sv_unit1c.gold @@ -0,0 +1,8 @@ +test1 macro1 = 1 +test1 macro2 = 12 +test1 macro3 = 13 +test1 wire = 1 +test2 macro1 = 1 +test2 macro2 = 2 +test2 macro3 = 23 +test2 wire = z diff --git a/ivtest/gold/sv_unit2b.gold b/ivtest/gold/sv_unit2b.gold new file mode 100644 index 000000000..e474866c5 --- /dev/null +++ b/ivtest/gold/sv_unit2b.gold @@ -0,0 +1,13 @@ +hello from unit 1 +hello1 from unit 1 +hello2 from c1 +hello1 from unit 1 +hello2 from m1 +hello3 from unit 1 +hello4 from m2 +hello1 from unit 1 +hello2 from c1 +hello1 from unit 2 +hello2 from m3 +hello3 from unit 2 +hello4 from m4 diff --git a/ivtest/gold/sv_unit3b.gold b/ivtest/gold/sv_unit3b.gold new file mode 100644 index 000000000..7da7b8b46 --- /dev/null +++ b/ivtest/gold/sv_unit3b.gold @@ -0,0 +1,12 @@ + 101 from unit1 + 100 from c1 + 101 from unit1 + 112 from m1 + 103 from unit1 + 124 from m2 + 101 from unit1 + 100 from c1 + 201 from unit2 + 232 from m3 + 203 from unit2 + 244 from m4 diff --git a/ivtest/gold/sv_wildcard_import4.gold b/ivtest/gold/sv_wildcard_import4.gold new file mode 100644 index 000000000..28497a305 --- /dev/null +++ b/ivtest/gold/sv_wildcard_import4.gold @@ -0,0 +1,5 @@ +./ivltests/sv_wildcard_import4.v:24: error: 'p1' has already been imported into this scope from package 'my_package'. +./ivltests/sv_wildcard_import4.v:25: error: 'p2' has already been imported into this scope from package 'my_package'. +./ivltests/sv_wildcard_import4.v:27: error: 'word' has already been imported into this scope from package 'my_package'. +./ivltests/sv_wildcard_import4.v:29: error: 'v' has already been imported into this scope from package 'my_package'. +./ivltests/sv_wildcard_import4.v:31: error: 'e' has already been imported into this scope from package 'my_package'. diff --git a/ivtest/gold/sv_wildcard_import5.gold b/ivtest/gold/sv_wildcard_import5.gold new file mode 100644 index 000000000..d5290ab19 --- /dev/null +++ b/ivtest/gold/sv_wildcard_import5.gold @@ -0,0 +1,7 @@ +./ivltests/sv_wildcard_import5.v:50: error: Ambiguous use of 'word'. It is exported by both 'my_package1' and by 'my_package2'. +./ivltests/sv_wildcard_import5.v:53: error: Ambiguous use of 'e'. It is exported by both 'my_package1' and by 'my_package2'. +./ivltests/sv_wildcard_import5.v:53: error: Ambiguous use of 'v'. It is exported by both 'my_package1' and by 'my_package2'. +./ivltests/sv_wildcard_import5.v:53: error: Ambiguous use of 'p1'. It is exported by both 'my_package1' and by 'my_package2'. +./ivltests/sv_wildcard_import5.v:53: error: Ambiguous use of 'p2'. It is exported by both 'my_package1' and by 'my_package2'. +./ivltests/sv_wildcard_import5.v:54: error: Ambiguous use of 'f'. It is exported by both 'my_package1' and by 'my_package2'. +./ivltests/sv_wildcard_import5.v:54: error: Ambiguous use of 'h'. It is exported by both 'my_package1' and by 'my_package2'. diff --git a/ivtest/gold/switch_primitives.gold b/ivtest/gold/switch_primitives.gold new file mode 100644 index 000000000..4274c9d97 --- /dev/null +++ b/ivtest/gold/switch_primitives.gold @@ -0,0 +1,21 @@ +x x x x x x x x StX StX StX StX StX StX +------------------ +0 0 0 z 0 z 0 z St0 HiZ St0 HiZ St0 HiZ +0 1 1 z 1 z 1 z St1 HiZ St1 HiZ St1 HiZ +0 x x z x z x z StX HiZ StX HiZ StX HiZ +0 z x z z z z z StX HiZ HiZ HiZ HiZ HiZ +------------------ +1 0 z 0 z 0 z 0 HiZ St0 HiZ St0 HiZ St0 +1 1 z 1 z 1 z 1 HiZ St1 HiZ St1 HiZ St1 +1 x z x z x z x HiZ StX HiZ StX HiZ StX +1 z z x z z z z HiZ StX HiZ HiZ HiZ HiZ +------------------ +x 0 x x x x x x StL StL StL StL StL StL +x 1 x x x x x x StH StH StH StH StH StH +x x x x x x x x StX StX StX StX StX StX +x z x x z z z z StX StX HiZ HiZ HiZ HiZ +------------------ +z 0 x x x x x x StL StL StL StL StL StL +z 1 x x x x x x StH StH StH StH StH StH +z x x x x x x x StX StX StX StX StX StX +z z x x z z z z StX StX HiZ HiZ HiZ HiZ diff --git a/ivtest/gold/swrite-vlog95.gold b/ivtest/gold/swrite-vlog95.gold new file mode 100644 index 000000000..b7bfd4445 --- /dev/null +++ b/ivtest/gold/swrite-vlog95.gold @@ -0,0 +1,10 @@ +WARNING: vlog95.v:171: %l currently unsupported $swrite<%l>. +WARNING: vlog95.v:173: %L currently unsupported $swrite<%L>. +WARNING: vlog95.v:223: $swrite returned a value with an embedded NULL (see %u/%z). +WARNING: vlog95.v:225: $swrite returned a value with an embedded NULL (see %u/%z). +WARNING: vlog95.v:241: $swrite returned a value with an embedded NULL (see %u/%z). +WARNING: vlog95.v:243: $swrite returned a value with an embedded NULL (see %u/%z). +WARNING: vlog95.v:245: $swrite returned a value with an embedded NULL (see %u/%z). +WARNING: vlog95.v:255: missing argument for $sformat<%s>. +WARNING: vlog95.v:257: $sformat has 1 extra argument(s). +All tests passed. diff --git a/ivtest/gold/swrite.gold b/ivtest/gold/swrite.gold new file mode 100644 index 000000000..2eb540340 --- /dev/null +++ b/ivtest/gold/swrite.gold @@ -0,0 +1,10 @@ +WARNING: ./ivltests/swrite.v:210: %l currently unsupported $swrite<%l>. +WARNING: ./ivltests/swrite.v:212: %L currently unsupported $swrite<%L>. +WARNING: ./ivltests/swrite.v:275: $swrite returned a value with an embedded NULL (see %u/%z). +WARNING: ./ivltests/swrite.v:277: $swrite returned a value with an embedded NULL (see %u/%z). +WARNING: ./ivltests/swrite.v:299: $swrite returned a value with an embedded NULL (see %u/%z). +WARNING: ./ivltests/swrite.v:301: $swrite returned a value with an embedded NULL (see %u/%z). +WARNING: ./ivltests/swrite.v:304: $swrite returned a value with an embedded NULL (see %u/%z). +WARNING: ./ivltests/swrite.v:318: missing argument for $sformat<%s>. +WARNING: ./ivltests/swrite.v:320: $sformat has 1 extra argument(s). +All tests passed. diff --git a/ivtest/gold/sys_func_as_task.gold b/ivtest/gold/sys_func_as_task.gold new file mode 100644 index 000000000..bfa5301ba --- /dev/null +++ b/ivtest/gold/sys_func_as_task.gold @@ -0,0 +1,3 @@ +./ivltests/sys_func_as_task.v:7: Warning: Calling system function $sscanf() as a task. +./ivltests/sys_func_as_task.v:7: The functions return value will be ignored. +PASSED diff --git a/ivtest/gold/sys_func_task_error-fsv.gold b/ivtest/gold/sys_func_task_error-fsv.gold new file mode 100644 index 000000000..6541682ac --- /dev/null +++ b/ivtest/gold/sys_func_task_error-fsv.gold @@ -0,0 +1,5 @@ +./ivltests/sys_func_task_error.v:7: Error: System task/function $this_icarus_call_should_not_exist() is not defined by any module. +./ivltests/sys_func_task_error.v:10: Warning: Calling system function $sscanf() as a task. +./ivltests/sys_func_task_error.v:10: The functions return value will be ignored. +./ivltests/sys_func_task_error.v:12: Error: $display() is a system task, it cannot be called as a function. +vsim: Program not runnable, 2 errors. diff --git a/ivtest/gold/sys_func_task_error-vlog95.gold b/ivtest/gold/sys_func_task_error-vlog95.gold new file mode 100644 index 000000000..f4e5ace44 --- /dev/null +++ b/ivtest/gold/sys_func_task_error-vlog95.gold @@ -0,0 +1,4 @@ +vlog95.v:14: Error: System task/function $this_icarus_call_should_not_exist() is not defined by any module. +vlog95.v:16: Error: $sscanf() is a system function, it cannot be called as a task. +vlog95.v:17: Error: $display() is a system task, it cannot be called as a function. +vsim: Program not runnable, 3 errors. diff --git a/ivtest/gold/sys_func_task_error.gold b/ivtest/gold/sys_func_task_error.gold new file mode 100644 index 000000000..fa7c78287 --- /dev/null +++ b/ivtest/gold/sys_func_task_error.gold @@ -0,0 +1,4 @@ +./ivltests/sys_func_task_error.v:7: Error: System task/function $this_icarus_call_should_not_exist() is not defined by any module. +./ivltests/sys_func_task_error.v:10: Error: $sscanf() is a system function, it cannot be called as a task. +./ivltests/sys_func_task_error.v:12: Error: $display() is a system task, it cannot be called as a function. +vsim: Program not runnable, 3 errors. diff --git a/ivtest/gold/tern3.gold b/ivtest/gold/tern3.gold new file mode 100644 index 000000000..0d2b6f279 --- /dev/null +++ b/ivtest/gold/tern3.gold @@ -0,0 +1,4 @@ +(Start) +(Start) +$bits == 40 +$bits == 40 diff --git a/ivtest/gold/tern5.gold b/ivtest/gold/tern5.gold new file mode 100644 index 000000000..b386b4e9a --- /dev/null +++ b/ivtest/gold/tern5.gold @@ -0,0 +1,10 @@ +00: foo = 01x01x01x +01: foo = 000111xxx +0x: foo = 0xxx1xxxx +11: foo = 000111xxx +1x: foo = 000111xxx +00: foo = 01x01x01x +01: foo = 000111xxx +0x: foo = 0xxx1xxxx +11: foo = 000111xxx +1x: foo = 000111xxx diff --git a/ivtest/gold/test_disphob.gold b/ivtest/gold/test_disphob.gold new file mode 100644 index 000000000..45a569980 --- /dev/null +++ b/ivtest/gold/test_disphob.gold @@ -0,0 +1,40 @@ +============================ myReg14 = 65 +>| 65| +*| 65| +*| 65| +>|0041| +*|0041| +*|0041| +>|00101| +*|00101| +*|00101| +>|00000001000001| +*|00000001000001| +*|00000001000001| +============================ myInt = -10 +>| -10| +*| -10| +>|fffffff6| +*|fffffff6| +>|37777777766| +*|37777777766| +>|11111111111111111111111111110110| +*|11111111111111111111111111110110| +============================ myReg32 = -10 +>|4294967286| +*|4294967286| +>|fffffff6| +*|fffffff6| +>|37777777766| +*|37777777766| +>|11111111111111111111111111110110| +*|11111111111111111111111111110110| +============================ myInt = 65 +>| 65| +*| 65| +>|00000041| +*|00000041| +>|00000000101| +*|00000000101| +>|00000000000000000000000001000001| +*|00000000000000000000000001000001| diff --git a/ivtest/gold/test_dispwided.gold b/ivtest/gold/test_dispwided.gold new file mode 100644 index 000000000..e51b63fb7 --- /dev/null +++ b/ivtest/gold/test_dispwided.gold @@ -0,0 +1,256 @@ +value= 1 +value= 2 +value= 4 +value= 8 +value= 16 +value= 32 +value= 64 +value= 128 +value= 256 +value= 512 +value= 1024 +value= 2048 +value= 4096 +value= 8192 +value= 16384 +value= 32768 +value= 65536 +value= 131072 +value= 262144 +value= 524288 +value= 1048576 +value= 2097152 +value= 4194304 +value= 8388608 +value= 16777216 +value= 33554432 +value= 67108864 +value= 134217728 +value= 268435456 +value= 536870912 +value= 1073741824 +value= 2147483648 +value= 4294967296 +value= 8589934592 +value= 17179869184 +value= 34359738368 +value= 68719476736 +value= 137438953472 +value= 274877906944 +value= 549755813888 +value= 1099511627776 +value= 2199023255552 +value= 4398046511104 +value= 8796093022208 +value= 17592186044416 +value= 35184372088832 +value= 70368744177664 +value= 140737488355328 +value= 281474976710656 +value= 562949953421312 +value= 1125899906842624 +value= 2251799813685248 +value= 4503599627370496 +value= 9007199254740992 +value= 18014398509481984 +value= 36028797018963968 +value= 72057594037927936 +value= 144115188075855872 +value= 288230376151711744 +value= 576460752303423488 +value= 1152921504606846976 +value= 2305843009213693952 +value= 4611686018427387904 +value= 9223372036854775808 +value= 18446744073709551616 +value= 36893488147419103232 +value= 73786976294838206464 +value= 147573952589676412928 +value= 295147905179352825856 +value= 590295810358705651712 +value= 1180591620717411303424 +value= 2361183241434822606848 +value= 4722366482869645213696 +value= 9444732965739290427392 +value= 18889465931478580854784 +value= 37778931862957161709568 +value= 75557863725914323419136 +value= 151115727451828646838272 +value= 302231454903657293676544 +value= 604462909807314587353088 +value= 1208925819614629174706176 +value= 2417851639229258349412352 +value= 4835703278458516698824704 +value= 9671406556917033397649408 +value= 19342813113834066795298816 +value= 38685626227668133590597632 +value= 77371252455336267181195264 +value= 154742504910672534362390528 +value= 309485009821345068724781056 +value= 618970019642690137449562112 +value= 1237940039285380274899124224 +value= 2475880078570760549798248448 +value= 4951760157141521099596496896 +value= 9903520314283042199192993792 +value= 19807040628566084398385987584 +value= 39614081257132168796771975168 +value= 79228162514264337593543950336 +value= 158456325028528675187087900672 +value= 316912650057057350374175801344 +value= 633825300114114700748351602688 +value= 1267650600228229401496703205376 +value= 2535301200456458802993406410752 +value= 5070602400912917605986812821504 +value= 10141204801825835211973625643008 +value= 20282409603651670423947251286016 +value= 40564819207303340847894502572032 +value= 81129638414606681695789005144064 +value= 162259276829213363391578010288128 +value= 324518553658426726783156020576256 +value= 649037107316853453566312041152512 +value= 1298074214633706907132624082305024 +value= 2596148429267413814265248164610048 +value= 5192296858534827628530496329220096 +value= 10384593717069655257060992658440192 +value= 20769187434139310514121985316880384 +value= 41538374868278621028243970633760768 +value= 83076749736557242056487941267521536 +value= 166153499473114484112975882535043072 +value= 332306998946228968225951765070086144 +value= 664613997892457936451903530140172288 +value= 1329227995784915872903807060280344576 +value= 2658455991569831745807614120560689152 +value= 5316911983139663491615228241121378304 +value= 10633823966279326983230456482242756608 +value= 21267647932558653966460912964485513216 +value= 42535295865117307932921825928971026432 +value= 85070591730234615865843651857942052864 +value=-170141183460469231731687303715884105728 +value= -1 +value= -2 +value= -4 +value= -8 +value= -16 +value= -32 +value= -64 +value= -128 +value= -256 +value= -512 +value= -1024 +value= -2048 +value= -4096 +value= -8192 +value= -16384 +value= -32768 +value= -65536 +value= -131072 +value= -262144 +value= -524288 +value= -1048576 +value= -2097152 +value= -4194304 +value= -8388608 +value= -16777216 +value= -33554432 +value= -67108864 +value= -134217728 +value= -268435456 +value= -536870912 +value= -1073741824 +value= -2147483648 +value= -4294967296 +value= -8589934592 +value= -17179869184 +value= -34359738368 +value= -68719476736 +value= -137438953472 +value= -274877906944 +value= -549755813888 +value= -1099511627776 +value= -2199023255552 +value= -4398046511104 +value= -8796093022208 +value= -17592186044416 +value= -35184372088832 +value= -70368744177664 +value= -140737488355328 +value= -281474976710656 +value= -562949953421312 +value= -1125899906842624 +value= -2251799813685248 +value= -4503599627370496 +value= -9007199254740992 +value= -18014398509481984 +value= -36028797018963968 +value= -72057594037927936 +value= -144115188075855872 +value= -288230376151711744 +value= -576460752303423488 +value= -1152921504606846976 +value= -2305843009213693952 +value= -4611686018427387904 +value= -9223372036854775808 +value= -18446744073709551616 +value= -36893488147419103232 +value= -73786976294838206464 +value= -147573952589676412928 +value= -295147905179352825856 +value= -590295810358705651712 +value= -1180591620717411303424 +value= -2361183241434822606848 +value= -4722366482869645213696 +value= -9444732965739290427392 +value= -18889465931478580854784 +value= -37778931862957161709568 +value= -75557863725914323419136 +value= -151115727451828646838272 +value= -302231454903657293676544 +value= -604462909807314587353088 +value= -1208925819614629174706176 +value= -2417851639229258349412352 +value= -4835703278458516698824704 +value= -9671406556917033397649408 +value= -19342813113834066795298816 +value= -38685626227668133590597632 +value= -77371252455336267181195264 +value= -154742504910672534362390528 +value= -309485009821345068724781056 +value= -618970019642690137449562112 +value= -1237940039285380274899124224 +value= -2475880078570760549798248448 +value= -4951760157141521099596496896 +value= -9903520314283042199192993792 +value= -19807040628566084398385987584 +value= -39614081257132168796771975168 +value= -79228162514264337593543950336 +value= -158456325028528675187087900672 +value= -316912650057057350374175801344 +value= -633825300114114700748351602688 +value= -1267650600228229401496703205376 +value= -2535301200456458802993406410752 +value= -5070602400912917605986812821504 +value= -10141204801825835211973625643008 +value= -20282409603651670423947251286016 +value= -40564819207303340847894502572032 +value= -81129638414606681695789005144064 +value= -162259276829213363391578010288128 +value= -324518553658426726783156020576256 +value= -649037107316853453566312041152512 +value= -1298074214633706907132624082305024 +value= -2596148429267413814265248164610048 +value= -5192296858534827628530496329220096 +value= -10384593717069655257060992658440192 +value= -20769187434139310514121985316880384 +value= -41538374868278621028243970633760768 +value= -83076749736557242056487941267521536 +value= -166153499473114484112975882535043072 +value= -332306998946228968225951765070086144 +value= -664613997892457936451903530140172288 +value= -1329227995784915872903807060280344576 +value= -2658455991569831745807614120560689152 +value= -5316911983139663491615228241121378304 +value= -10633823966279326983230456482242756608 +value= -21267647932558653966460912964485513216 +value= -42535295865117307932921825928971026432 +value= -85070591730234615865843651857942052864 +value=-170141183460469231731687303715884105728 diff --git a/ivtest/gold/test_extended.gold b/ivtest/gold/test_extended.gold new file mode 100644 index 000000000..31d4d5f3b --- /dev/null +++ b/ivtest/gold/test_extended.gold @@ -0,0 +1,24 @@ +============================ myReg8 = 65 +>| 65| +*| 65| +*| 65| +============================ myReg14 = -10 +>|16374| +*|16374| +*|16374| +============================ myReg14 = 65 +>1| 65| +*1| 65| +>2|65| +*2|65| +>3| 65| +*3| 65| +>4| 65| +*4|00000065| +*4| 65| +>5| 65| +*5|065| +*5| 65| +============================ myReg14 = 1000 +>|1000| +*|1000| diff --git a/ivtest/gold/test_va_math.gold b/ivtest/gold/test_va_math.gold new file mode 100644 index 000000000..a269057f6 --- /dev/null +++ b/ivtest/gold/test_va_math.gold @@ -0,0 +1,328 @@ +Using +0 = 0.000000, -0 = -0.000000, nan = nan, inf = inf and -inf = -inf. + +NaN != comparison works correctly. +NaN == comparison works correctly. + +--- Checking the $sqrt function --- +The square root of 2.0 is 1.414214. +The square root of 1.0 is 1.000000. +The square root of 0.0 is 0.000000. +The square root of -0.0 is -0.000000. +The square root of -1.0 is nan. +The square root of inf is inf. +The square root of -inf is nan. +The square root of nan is nan. + +--- Checking the $ln function --- +The natural log of 10.0 is 2.302585. +The natural log of 1.0 is 0.000000. +The natural log of 0.5 is -0.693147. +The natural log of 0.0 is -inf. +The natural log of -0.0 is -inf. +The natural log of -1.0 is nan. +The natural log of inf is inf. +The natural log of -inf is nan. +The natural log of nan is nan. + +--- Checking the $log10 function --- +The log base 10 of 10.0 is 1.000000. +The log base 10 of 1.0 is 0.000000. +The log base 10 of 0.5 is -0.301030. +The log base 10 of 0.0 is -inf. +The log base 10 of -0.0 is -inf. +The log base 10 of -1.0 is nan. +The log base 10 of inf is inf. +The log base 10 of -inf is nan. +The log base 10 of nan is nan. + +--- Checking the $exp function --- +The exponential of 1.0 is 2.718282. +The exponential of 0.0 is 1.000000. +The exponential of -0.0 is 1.000000. +The exponential of -1.0 is 0.367879. +The exponential of inf is inf. +The exponential of -inf is 0.000000. +The exponential of nan is nan. + +--- Checking the $abs function --- +The absolute value of 1.0 is 1.000000. +The absolute value of 0.0 is 0.000000. +The absolute value of -0.0 is 0.000000. +The absolute value of -1.0 is 1.000000. +The absolute value of inf is inf. +The absolute value of -inf is inf. +The absolute value of nan is nan. + +--- Checking the $ceil function --- +The ceiling of 2.1 is 3.000000. +The ceiling of 0.5 is 1.000000. +The ceiling of -0.5 is 0.000000. +The ceiling of -1.1 is -1.000000. +The ceiling of inf is inf. +The ceiling of -inf is -inf. +The ceiling of nan is nan. + +--- Checking the $floor function --- +The floor of 2.1 is 2.000000. +The floor of 0.5 is 0.000000. +The floor of -0.5 is -1.000000. +The floor of -1.1 is -2.000000. +The floor of inf is inf. +The floor of -inf is -inf. +The floor of nan is nan. + +--- Checking the $sin function --- +The sin of 4.0 is -0.756802. +The sin of 1.0 is 0.841471. +The sin of 0.0 is 0.000000. +The sin of -0.0 is -0.000000. +The sin of -1.0 is -0.841471. +The sin of -4.0 is 0.756802. +The sin of inf is nan. +The sin of -inf is nan. +The sin of nan is nan. + +--- Checking the $cos function --- +The cos of 4.0 is -0.653644. +The cos of 1.0 is 0.540302. +The cos of 0.0 is 1.000000. +The cos of -0.0 is 1.000000. +The cos of -1.0 is 0.540302. +The cos of -4.0 is -0.653644. +The cos of inf is nan. +The cos of -inf is nan. +The cos of nan is nan. + +--- Checking the $tan function --- +The tan of 4.0 is 1.157821. +The tan of 1.0 is 1.557408. +The tan of 0.0 is 0.000000. +The tan of -0.0 is -0.000000. +The tan of -1.0 is -1.557408. +The tan of -4.0 is -1.157821. +The tan of pi/2 is 1.633e+16. +The tan of -pi/2 is -1.633e+16. +The tan of inf is nan. +The tan of -inf is nan. +The tan of nan is nan. + +--- Checking the $asin function --- +The asin of 1.1 is nan. +The asin of 1.0 is 1.570796. +The asin of 0.5 is 0.523599. +The asin of 0.0 is 0.000000. +The asin of -0.0 is -0.000000. +The asin of -0.5 is -0.523599. +The asin of -1.0 is -1.570796. +The asin of -1.1 is nan. +The asin of inf is nan. +The asin of -inf is nan. +The asin of nan is nan. + +--- Checking the $acos function --- +The acos of 1.1 is nan. +The acos of 1.0 is 0.000000. +The acos of 0.5 is 1.047198. +The acos of 0.0 is 1.570796. +The acos of -0.0 is 1.570796. +The acos of -0.5 is 2.094395. +The acos of -1.0 is 3.141593. +The acos of -1.1 is nan. +The acos of inf is nan. +The acos of -inf is nan. +The acos of nan is nan. + +--- Checking the $atan function --- +The atan of 2.0 is 1.107149. +The atan of 0.5 is 0.463648. +The atan of 0.0 is 0.000000. +The atan of -0.0 is -0.000000. +The atan of -0.5 is -0.463648. +The atan of -2.0 is -1.107149. +The atan of inf is 1.570796. +The atan of -inf is -1.570796. +The atan of nan is nan. + +--- Checking the $sinh function --- +The sinh of 2.0 is 3.626860. +The sinh of 1.0 is 1.175201. +The sinh of 0.5 is 0.521095. +The sinh of 0.0 is 0.000000. +The sinh of -0.0 is -0.000000. +The sinh of -0.5 is -0.521095. +The sinh of -1.0 is -1.175201. +The sinh of -2.0 is -3.626860. +The sinh of inf is inf. +The sinh of -inf is -inf. +The sinh of nan is nan. + +--- Checking the $cosh function --- +The cosh of 2.0 is 3.762196. +The cosh of 1.0 is 1.543081. +The cosh of 0.5 is 1.127626. +The cosh of 0.0 is 1.000000. +The cosh of -0.0 is 1.000000. +The cosh of -0.5 is 1.127626. +The cosh of -1.0 is 1.543081. +The cosh of -2.0 is 3.762196. +The cosh of inf is inf. +The cosh of -inf is inf. +The cosh of nan is nan. + +--- Checking the $tanh function --- +The tanh of 2.0 is 0.964028. +The tanh of 1.0 is 0.761594. +The tanh of 0.5 is 0.462117. +The tanh of 0.0 is 0.000000. +The tanh of -0.0 is -0.000000. +The tanh of -0.5 is -0.462117. +The tanh of -1.0 is -0.761594. +The tanh of -2.0 is -0.964028. +The tanh of inf is 1.000000. +The tanh of -inf is -1.000000. +The tanh of nan is nan. + +--- Checking the $asinh function --- +The asinh of 2.0 is 1.443635. +The asinh of 1.0 is 0.881374. +The asinh of 0.5 is 0.481212. +The asinh of 0.0 is 0.000000. +The asinh of -0.0 is -0.000000. +The asinh of -0.5 is -0.481212. +The asinh of -1.0 is -0.881374. +The asinh of -2.0 is -1.443635. +The asinh of inf is inf. +The asinh of -inf is -inf. +The asinh of nan is nan. + +--- Checking the $acosh function --- +The acosh of 2.0 is 1.316958. +The acosh of 1.0 is 0.000000. +The acosh of 0.5 is nan. +The acosh of 0 is nan. +The acosh of -0 is nan. +The acosh of -0.5 is nan. +The acosh of -1.0 is nan. +The acosh of -2.0 is nan. +The acosh of inf is inf. +The acosh of -inf is nan. +The acosh of nan is nan. + +--- Checking the $atanh function --- +The atanh of 2.0 is nan. +The atanh of 1.0 is inf. +The atanh of 0.5 is 0.549306. +The atanh of 0.0 is 0.000000. +The atanh of -0.0 is -0.000000. +The atanh of -0.5 is -0.549306. +The atanh of -1.0 is -inf. +The atanh of -2.0 is nan. +The atanh of inf is nan. +The atanh of -inf is nan. +The atanh of nan is nan. + +--- Checking the $min function --- +The minimum of 1.0 and 2.0 is 1.000000. +The minimum of 2.0 and 1.0 is 1.000000. +The minimum of 1.0 and -1.0 is -1.000000. +The minimum of -1.0 and -2.0 is -2.000000. +The minimum of 2.0 and inf is 2.000000. +The minimum of inf and 2.0 is 2.000000. +The minimum of 2.0 and -inf is -inf. +The minimum of -inf and 2.0 is -inf. +The minimum of 2.0 and nan is 2.000000. +The minimum of nan and 2.0 is 2.000000. + +--- Checking the $max function --- +The maximum of 1.0 and 2.0 is 2.000000. +The maximum of 2.0 and 1.0 is 2.000000. +The maximum of 1.0 and -1.0 is 1.000000. +The maximum of -1.0 and -2.0 is -1.000000. +The maximum of 2.0 and inf is inf. +The maximum of inf and 2.0 is inf. +The maximum of 2.0 and -inf is 2.000000. +The maximum of -inf and 2.0 is 2.000000. +The maximum of 2.0 and nan is 2.000000. +The maximum of nan and 2.0 is 2.000000. + +--- Checking the $pow function --- + 0.0 to the power of 0.0 is 1.000000. + 1.0 to the power of 0.0 is 1.000000. +-1.0 to the power of 0.0 is 1.000000. + 0.0 to the power of 1.0 is 0.000000. + 1.0 to the power of 1.0 is 1.000000. +-1.0 to the power of 1.0 is -1.000000. + 8.0 to the power of 1/3 is 2.000000. + 8.0 to the power of -1/3 is 0.500000. + 2.0 to the power of 3.0 is 8.000000. + 2.0 to the power of 5000 is inf. +-2.0 to the power of 5001 is -inf. + 2.0 to the power of -5000 is 0.000000. + inf to the power of 0.0 is 1.000000. +-inf to the power of 0.0 is 1.000000. + inf to the power of 1.0 is inf. +-inf to the power of 1.0 is -inf. + inf to the power of 2.0 is inf. +-inf to the power of 2.0 is inf. + 1.0 to the power of inf is 1.000000. +-1.0 to the power of inf is 1.000000. + 0.5 to the power of inf is 0.000000. + 2.0 to the power of inf is inf. + 1.0 to the power of -inf is 1.000000. +-1.0 to the power of -inf is 1.000000. + 0.5 to the power of -inf is inf. + 2.0 to the power of -inf is 0.000000. +-1.0 to the power of -1/3 is nan. + 1.0 to the power of nan is 1.000000. + nan to the power of 1.0 is nan. + nan to the power of 0.0 is 1.000000. + nan to the power of nan is nan. + +--- Checking the $atan2 function --- +The atan of 0.0/ 0.0 is 0.000000. +The atan of -0.0/ 0.0 is -0.000000. +The atan of 0.0/-0.0 is 3.141593. +The atan of -0.0/-0.0 is -3.141593. +The atan of 0.0/ 1.0 is 0.000000. +The atan of 1.0/ 0.0 is 1.570796. +The atan of 1.0/ 1.0 is 0.785398. +The atan of 0.0/-1.0 is 3.141593. +The atan of -1.0/ 0.0 is -1.570796. +The atan of -1.0/-1.0 is -2.356194. +The atan of inf/ 0.0 is 1.570796. +The atan of 0.0/ inf is 0.000000. +The atan of inf/ inf is 0.785398. +The atan of -inf/ 0.0 is -1.570796. +The atan of 0.0/-inf is 3.141593. +The atan of -inf/-inf is -2.356194. +The atan of nan/ 0.0 is nan. +The atan of nan/ 1.0 is nan. +The atan of 1.0/ nan is nan. + +--- Checking the $hypot function --- +The distance to ( 0.0, 0.0) is 0.000000. +The distance to ( 2.0, 0.0) is 2.000000. +The distance to ( -2.0, 0.0) is 2.000000. +The distance to ( 0.0, 2.0) is 2.000000. +The distance to ( 0.0, -2.0) is 2.000000. +The distance to ( inf, 0.0) is inf. +The distance to ( 0.0, inf) is inf. +The distance to ( -inf, 0.0) is inf. +The distance to ( nan, 0.0) is nan. +The distance to ( 0.0, nan) is nan. + +--- Checking the mathematical constants --- + Pi is 3.1415926535897931. + 2*Pi is 6.2831853071795862. + Pi/2 is 1.5707963267948966. + Pi/4 is 0.7853981633974483. + 1/Pi is 0.3183098861837907. + 2/Pi is 0.6366197723675814. +2/sqrt(Pi) is 1.1283791670955126. + e is 2.7182818284590451. + log2(e) is 1.4426950408889634. + log10(e) is 0.4342944819032518. + loge(2) is 0.6931471805599453. + loge(10) is 2.3025850929940459. + sqrt(2) is 1.4142135623730951. + 1/sqrt(2) is 0.7071067811865476. diff --git a/ivtest/gold/test_vams_math.gold b/ivtest/gold/test_vams_math.gold new file mode 100644 index 000000000..7ae8821ca --- /dev/null +++ b/ivtest/gold/test_vams_math.gold @@ -0,0 +1,328 @@ +Using +0 = 0.000000, -0 = -0.000000, nan = nan, inf = inf and -inf = -inf. + +NaN != comparison works correctly. +NaN == comparison works correctly. + +--- Checking the sqrt function --- +The square root of 2.0 is 1.414214. +The square root of 1.0 is 1.000000. +The square root of 0.0 is 0.000000. +The square root of -0.0 is -0.000000. +The square root of -1.0 is nan. +The square root of inf is inf. +The square root of -inf is nan. +The square root of nan is nan. + +--- Checking the ln function --- +The natural log of 10.0 is 2.302585. +The natural log of 1.0 is 0.000000. +The natural log of 0.5 is -0.693147. +The natural log of 0.0 is -inf. +The natural log of -0.0 is -inf. +The natural log of -1.0 is nan. +The natural log of inf is inf. +The natural log of -inf is nan. +The natural log of nan is nan. + +--- Checking the log function --- +The log base 10 of 10.0 is 1.000000. +The log base 10 of 1.0 is 0.000000. +The log base 10 of 0.5 is -0.301030. +The log base 10 of 0.0 is -inf. +The log base 10 of -0.0 is -inf. +The log base 10 of -1.0 is nan. +The log base 10 of inf is inf. +The log base 10 of -inf is nan. +The log base 10 of nan is nan. + +--- Checking the exp function --- +The exponential of 1.0 is 2.718282. +The exponential of 0.0 is 1.000000. +The exponential of -0.0 is 1.000000. +The exponential of -1.0 is 0.367879. +The exponential of inf is inf. +The exponential of -inf is 0.000000. +The exponential of nan is nan. + +--- Checking the abs function --- +The absolute value of 1.0 is 1.000000. +The absolute value of 0.0 is 0.000000. +The absolute value of -0.0 is 0.000000. +The absolute value of -1.0 is 1.000000. +The absolute value of inf is inf. +The absolute value of -inf is inf. +The absolute value of nan is nan. + +--- Checking the ceil function --- +The ceiling of 2.1 is 3.000000. +The ceiling of 0.5 is 1.000000. +The ceiling of -0.5 is 0.000000. +The ceiling of -1.1 is -1.000000. +The ceiling of inf is inf. +The ceiling of -inf is -inf. +The ceiling of nan is nan. + +--- Checking the floor function --- +The floor of 2.1 is 2.000000. +The floor of 0.5 is 0.000000. +The floor of -0.5 is -1.000000. +The floor of -1.1 is -2.000000. +The floor of inf is inf. +The floor of -inf is -inf. +The floor of nan is nan. + +--- Checking the sin function --- +The sin of 4.0 is -0.756802. +The sin of 1.0 is 0.841471. +The sin of 0.0 is 0.000000. +The sin of -0.0 is -0.000000. +The sin of -1.0 is -0.841471. +The sin of -4.0 is 0.756802. +The sin of inf is nan. +The sin of -inf is nan. +The sin of nan is nan. + +--- Checking the cos function --- +The cos of 4.0 is -0.653644. +The cos of 1.0 is 0.540302. +The cos of 0.0 is 1.000000. +The cos of -0.0 is 1.000000. +The cos of -1.0 is 0.540302. +The cos of -4.0 is -0.653644. +The cos of inf is nan. +The cos of -inf is nan. +The cos of nan is nan. + +--- Checking the tan function --- +The tan of 4.0 is 1.157821. +The tan of 1.0 is 1.557408. +The tan of 0.0 is 0.000000. +The tan of -0.0 is -0.000000. +The tan of -1.0 is -1.557408. +The tan of -4.0 is -1.157821. +The tan of pi/2 is 1.633e+16. +The tan of -pi/2 is -1.633e+16. +The tan of inf is nan. +The tan of -inf is nan. +The tan of nan is nan. + +--- Checking the asin function --- +The asin of 1.1 is nan. +The asin of 1.0 is 1.570796. +The asin of 0.5 is 0.523599. +The asin of 0.0 is 0.000000. +The asin of -0.0 is -0.000000. +The asin of -0.5 is -0.523599. +The asin of -1.0 is -1.570796. +The asin of -1.1 is nan. +The asin of inf is nan. +The asin of -inf is nan. +The asin of nan is nan. + +--- Checking the acos function --- +The acos of 1.1 is nan. +The acos of 1.0 is 0.000000. +The acos of 0.5 is 1.047198. +The acos of 0.0 is 1.570796. +The acos of -0.0 is 1.570796. +The acos of -0.5 is 2.094395. +The acos of -1.0 is 3.141593. +The acos of -1.1 is nan. +The acos of inf is nan. +The acos of -inf is nan. +The acos of nan is nan. + +--- Checking the atan function --- +The atan of 2.0 is 1.107149. +The atan of 0.5 is 0.463648. +The atan of 0.0 is 0.000000. +The atan of -0.0 is -0.000000. +The atan of -0.5 is -0.463648. +The atan of -2.0 is -1.107149. +The atan of inf is 1.570796. +The atan of -inf is -1.570796. +The atan of nan is nan. + +--- Checking the sinh function --- +The sinh of 2.0 is 3.626860. +The sinh of 1.0 is 1.175201. +The sinh of 0.5 is 0.521095. +The sinh of 0.0 is 0.000000. +The sinh of -0.0 is -0.000000. +The sinh of -0.5 is -0.521095. +The sinh of -1.0 is -1.175201. +The sinh of -2.0 is -3.626860. +The sinh of inf is inf. +The sinh of -inf is -inf. +The sinh of nan is nan. + +--- Checking the cosh function --- +The cosh of 2.0 is 3.762196. +The cosh of 1.0 is 1.543081. +The cosh of 0.5 is 1.127626. +The cosh of 0.0 is 1.000000. +The cosh of -0.0 is 1.000000. +The cosh of -0.5 is 1.127626. +The cosh of -1.0 is 1.543081. +The cosh of -2.0 is 3.762196. +The cosh of inf is inf. +The cosh of -inf is inf. +The cosh of nan is nan. + +--- Checking the tanh function --- +The tanh of 2.0 is 0.964028. +The tanh of 1.0 is 0.761594. +The tanh of 0.5 is 0.462117. +The tanh of 0.0 is 0.000000. +The tanh of -0.0 is -0.000000. +The tanh of -0.5 is -0.462117. +The tanh of -1.0 is -0.761594. +The tanh of -2.0 is -0.964028. +The tanh of inf is 1.000000. +The tanh of -inf is -1.000000. +The tanh of nan is nan. + +--- Checking the asinh function --- +The asinh of 2.0 is 1.443635. +The asinh of 1.0 is 0.881374. +The asinh of 0.5 is 0.481212. +The asinh of 0.0 is 0.000000. +The asinh of -0.0 is -0.000000. +The asinh of -0.5 is -0.481212. +The asinh of -1.0 is -0.881374. +The asinh of -2.0 is -1.443635. +The asinh of inf is inf. +The asinh of -inf is -inf. +The asinh of nan is nan. + +--- Checking the acosh function --- +The acosh of 2.0 is 1.316958. +The acosh of 1.0 is 0.000000. +The acosh of 0.5 is nan. +The acosh of 0 is nan. +The acosh of -0 is nan. +The acosh of -0.5 is nan. +The acosh of -1.0 is nan. +The acosh of -2.0 is nan. +The acosh of inf is inf. +The acosh of -inf is nan. +The acosh of nan is nan. + +--- Checking the atanh function --- +The atanh of 2.0 is nan. +The atanh of 1.0 is inf. +The atanh of 0.5 is 0.549306. +The atanh of 0.0 is 0.000000. +The atanh of -0.0 is -0.000000. +The atanh of -0.5 is -0.549306. +The atanh of -1.0 is -inf. +The atanh of -2.0 is nan. +The atanh of inf is nan. +The atanh of -inf is nan. +The atanh of nan is nan. + +--- Checking the min function --- +The minimum of 1.0 and 2.0 is 1.000000. +The minimum of 2.0 and 1.0 is 1.000000. +The minimum of 1.0 and -1.0 is -1.000000. +The minimum of -1.0 and -2.0 is -2.000000. +The minimum of 2.0 and inf is 2.000000. +The minimum of inf and 2.0 is 2.000000. +The minimum of 2.0 and -inf is -inf. +The minimum of -inf and 2.0 is -inf. +The minimum of 2.0 and nan is 2.000000. +The minimum of nan and 2.0 is 2.000000. + +--- Checking the max function --- +The maximum of 1.0 and 2.0 is 2.000000. +The maximum of 2.0 and 1.0 is 2.000000. +The maximum of 1.0 and -1.0 is 1.000000. +The maximum of -1.0 and -2.0 is -1.000000. +The maximum of 2.0 and inf is inf. +The maximum of inf and 2.0 is inf. +The maximum of 2.0 and -inf is 2.000000. +The maximum of -inf and 2.0 is 2.000000. +The maximum of 2.0 and nan is 2.000000. +The maximum of nan and 2.0 is 2.000000. + +--- Checking the pow function --- + 0.0 to the power of 0.0 is 1.000000. + 1.0 to the power of 0.0 is 1.000000. +-1.0 to the power of 0.0 is 1.000000. + 0.0 to the power of 1.0 is 0.000000. + 1.0 to the power of 1.0 is 1.000000. +-1.0 to the power of 1.0 is -1.000000. + 8.0 to the power of 1/3 is 2.000000. + 8.0 to the power of -1/3 is 0.500000. + 2.0 to the power of 3.0 is 8.000000. + 2.0 to the power of 5000 is inf. +-2.0 to the power of 5001 is -inf. + 2.0 to the power of -5000 is 0.000000. + inf to the power of 0.0 is 1.000000. +-inf to the power of 0.0 is 1.000000. + inf to the power of 1.0 is inf. +-inf to the power of 1.0 is -inf. + inf to the power of 2.0 is inf. +-inf to the power of 2.0 is inf. + 1.0 to the power of inf is 1.000000. +-1.0 to the power of inf is 1.000000. + 0.5 to the power of inf is 0.000000. + 2.0 to the power of inf is inf. + 1.0 to the power of -inf is 1.000000. +-1.0 to the power of -inf is 1.000000. + 0.5 to the power of -inf is inf. + 2.0 to the power of -inf is 0.000000. +-1.0 to the power of -1/3 is nan. + 1.0 to the power of nan is 1.000000. + nan to the power of 1.0 is nan. + nan to the power of 0.0 is 1.000000. + nan to the power of nan is nan. + +--- Checking the atan2 function --- +The atan of 0.0/ 0.0 is 0.000000. +The atan of -0.0/ 0.0 is -0.000000. +The atan of 0.0/-0.0 is 3.141593. +The atan of -0.0/-0.0 is -3.141593. +The atan of 0.0/ 1.0 is 0.000000. +The atan of 1.0/ 0.0 is 1.570796. +The atan of 1.0/ 1.0 is 0.785398. +The atan of 0.0/-1.0 is 3.141593. +The atan of -1.0/ 0.0 is -1.570796. +The atan of -1.0/-1.0 is -2.356194. +The atan of inf/ 0.0 is 1.570796. +The atan of 0.0/ inf is 0.000000. +The atan of inf/ inf is 0.785398. +The atan of -inf/ 0.0 is -1.570796. +The atan of 0.0/-inf is 3.141593. +The atan of -inf/-inf is -2.356194. +The atan of nan/ 0.0 is nan. +The atan of nan/ 1.0 is nan. +The atan of 1.0/ nan is nan. + +--- Checking the hypot function --- +The distance to ( 0.0, 0.0) is 0.000000. +The distance to ( 2.0, 0.0) is 2.000000. +The distance to ( -2.0, 0.0) is 2.000000. +The distance to ( 0.0, 2.0) is 2.000000. +The distance to ( 0.0, -2.0) is 2.000000. +The distance to ( inf, 0.0) is inf. +The distance to ( 0.0, inf) is inf. +The distance to ( -inf, 0.0) is inf. +The distance to ( nan, 0.0) is nan. +The distance to ( 0.0, nan) is nan. + +--- Checking the mathematical constants --- + Pi is 3.1415926535897931. + 2*Pi is 6.2831853071795862. + Pi/2 is 1.5707963267948966. + Pi/4 is 0.7853981633974483. + 1/Pi is 0.3183098861837907. + 2/Pi is 0.6366197723675814. +2/sqrt(Pi) is 1.1283791670955126. + e is 2.7182818284590451. + log2(e) is 1.4426950408889634. + log10(e) is 0.4342944819032518. + loge(2) is 0.6931471805599453. + loge(10) is 2.3025850929940459. + sqrt(2) is 1.4142135623730951. + 1/sqrt(2) is 0.7071067811865476. diff --git a/ivtest/gold/test_width.gold b/ivtest/gold/test_width.gold new file mode 100644 index 000000000..25a9d8207 --- /dev/null +++ b/ivtest/gold/test_width.gold @@ -0,0 +1,84 @@ +============================ myReg14 = -10 +>|16374| +*|16374| +*|16374| +*|16374| +============================ myReg14 = 65 +>| 65| +*| 65| +*| 65| +>|65| +*|65| +>|0041| +*|0041| +>|41| +*|41| +>|00101| +*|00101| +>|101| +*|101| +>|00000001000001| +*|00000001000001| +>|1000001| +*|1000001| +>| A| +*| A| +>|A| +*|A| +============================ myInt = -10 +>| -10| +*| -10| +*| -10| +>|-10| +*|-10| +>|fffffff6| +*|fffffff6| +*|fffffff6| +>|37777777766| +*|37777777766| +*|37777777766| +>|11111111111111111111111111110110| +*|11111111111111111111111111110110| +*|11111111111111111111111111110110| +============================ myReg32 = -10 +>|4294967286| +*|4294967286| +*|4294967286| +*|4294967286| +>|fffffff6| +*|fffffff6| +*|fffffff6| +>|37777777766| +*|37777777766| +*|37777777766| +============================ myInt = 65 +>| 65| +*| 65| +*| 65| +>|65| +*|65| +>|00000041| +*|00000041| +>|41| +*|41| +>|00000000101| +*|00000000101| +>|101| +*|101| +>|00000000000000000000000001000001| +*|00000000000000000000000001000001| +>|1000001| +*|1000001| +*| A| +>| A| +*|A| +>|A| +============================ Print " A" +*| A| +>| A| +>| A| +============================ Print $time +*| 0| +>| 0| +*|0| +>|0| diff --git a/ivtest/gold/time6c.gold b/ivtest/gold/time6c.gold new file mode 100644 index 000000000..e4faaa04e --- /dev/null +++ b/ivtest/gold/time6c.gold @@ -0,0 +1,2 @@ + 3 3.4 set out1 == 1 + 4 3.6 set out2 == 1 diff --git a/ivtest/gold/time7.gold b/ivtest/gold/time7.gold new file mode 100644 index 000000000..ca9343c45 --- /dev/null +++ b/ivtest/gold/time7.gold @@ -0,0 +1,51 @@ + +<< BEGIN >> +@ 0 - no count +@ 0 - no count +@ 1 - no count +@ 2 - no count +@ 3 - no count +@ 4 - no count +@ 5 - no count +@ 6 - no count +@ 7 - no count +@ 8 - no count +@ 9 - no count +@ 10 - no count +@ 11 - no count +@ 12 - no count +@ 13 - no count +@ 14 - no count +@ 15 - no count +@ 16 - no count +@ 17 - no count +@ 18 - no count +@ 19 - no count +@ 20 - no count +@ 21 - no count +@ 22 - no count +@ 23 - no count +@ 24 - Got ONE +@ 25 - no count +@ 26 - no count +@ 27 - no count +@ 28 - Got ONE +@ 29 - no count +@ 30 - no count +@ 31 - no count +@ 32 - no count +@ 33 - no count +@ 34 - no count +@ 35 - no count +@ 36 - no count +@ 37 - no count +@ 38 - no count +@ 39 - no count +@ 40 - no count +@ 41 - no count +@ 42 - no count +@ 43 - no count +@ 44 - no count + +<< END >> +OK diff --git a/ivtest/gold/timeform1.gold b/ivtest/gold/timeform1.gold new file mode 100644 index 000000000..69d9fc726 --- /dev/null +++ b/ivtest/gold/timeform1.gold @@ -0,0 +1,3 @@ +$time = 3 (unformatted) +$time = 0.003000ns (-6,6) +$time = 0.0ns (-6,1) diff --git a/ivtest/gold/timeform2.gold b/ivtest/gold/timeform2.gold new file mode 100644 index 000000000..5b76cd992 --- /dev/null +++ b/ivtest/gold/timeform2.gold @@ -0,0 +1,2 @@ +time within module: 1.000ns +time within task: 1.000ns diff --git a/ivtest/gold/tran.gold b/ivtest/gold/tran.gold new file mode 100644 index 000000000..bb6a6c730 --- /dev/null +++ b/ivtest/gold/tran.gold @@ -0,0 +1,112 @@ +a = z b = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = x b = z +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX StX) t12(67X StX) t13(57X 56X) t14(37X 36X) t15(SuH StH) +t21(76X StX) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 65X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 63X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL StL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = 0 b = z +a1(Su0) a2(St0) a3(St0) a4(St0) a5(St0) a6(St0) a7(St0) +t11(Su0 St0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 St0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 St0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 St0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 St0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 1 b = z +a1(Su1) a2(St1) a3(St1) a4(St1) a5(St1) a6(St1) a7(St1) +t11(Su1 St1) t12(Su1 St1) t13(Su1 St1) t14(Su1 St1) t15(Su1 St1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(StX SuX) t12(StX 67X) t13(56X 57X) t14(36X 37X) t15(StH SuH) +t21(StX 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(65X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(63X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(StL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = x +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = 0 b = x +a1(Su0) a2(St0) a3(St0) a4(St0) a5(St0) a6(St0) a7(St0) +t11(Su0 SuX) t12(StX 67X) t13(56X 57X) t14(36X 37X) t15(StH SuH) +t21(Su0 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(Su0 760) t32(St0 St0) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(Su0 760) t42(St0 St0) t43(Pu0 Pu0) t44(WeX WeX) t45(WeH WeH) +t51(Su0 760) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 1 b = x +a1(Su1) a2(St1) a3(St1) a4(St1) a5(St1) a6(St1) a7(St1) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 761) t14(Su1 761) t15(Su1 761) +t21(StX 76X) t22(StX StX) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(65X 75X) t32(65X 65X) t33(PuX PuX) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(63X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(We1 We1) +t51(StL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = z b = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(St0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(St0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(St0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(St0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(St0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = x b = 0 +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX Su0) t12(67X StX) t13(57X 56X) t14(37X 36X) t15(SuH StH) +t21(76X Su0) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(760 Su0) t32(St0 St0) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(760 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(WeX WeX) t45(WeH WeH) +t51(760 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = 0 +a1(Su0) a2(St0) a3(St0) a4(St0) a5(St0) a6(St0) a7(St0) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 1 b = 0 +a1(Su1) a2(St1) a3(St1) a4(St1) a5(St1) a6(St1) a7(St1) +t11(Su1 Su0) t12(Su1 StX) t13(Su1 St1) t14(Su1 St1) t15(Su1 St1) +t21(StX Su0) t22(StX StX) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(St0 Su0) t32(St0 St0) t33(PuX PuX) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(St0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(WeX WeX) t45(We1 We1) +t51(St0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = z b = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(St1 Su1) t12(St1 Su1) t13(St1 Su1) t14(St1 Su1) t15(St1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = x b = 1 +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX Su1) t12(67X Su1) t13(761 Su1) t14(761 Su1) t15(761 Su1) +t21(76X StX) t22(StX StX) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(75X 65X) t32(65X 65X) t33(PuX PuX) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(73X 63X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(We1 We1) +t51(SuL StL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = 0 b = 1 +a1(Su0) a2(St0) a3(St0) a4(St0) a5(St0) a6(St0) a7(St0) +t11(Su0 Su1) t12(StX Su1) t13(St1 Su1) t14(St1 Su1) t15(St1 Su1) +t21(Su0 StX) t22(StX StX) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Su0 St0) t32(St0 St0) t33(PuX PuX) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(Su0 St0) t42(St0 St0) t43(Pu0 Pu0) t44(WeX WeX) t45(We1 We1) +t51(Su0 St0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 1 b = 1 +a1(Su1) a2(St1) a3(St1) a4(St1) a5(St1) a6(St1) a7(St1) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) diff --git a/ivtest/gold/tranif0.gold b/ivtest/gold/tranif0.gold new file mode 100644 index 000000000..ca0703187 --- /dev/null +++ b/ivtest/gold/tranif0.gold @@ -0,0 +1,448 @@ +a = z b = z en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = z en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = z en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = z en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = x b = z en = z +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX StX) t12(67X StX) t13(57X 56X) t14(37X 36X) t15(SuH StH) +t21(76X StX) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 65X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 63X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL StL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = z en = x +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX StX) t12(67X StX) t13(57X 56X) t14(37X 36X) t15(SuH StH) +t21(76X StX) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 65X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 63X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL StL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = z en = 0 +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX StX) t12(67X StX) t13(57X 56X) t14(37X 36X) t15(SuH StH) +t21(76X StX) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 65X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 63X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL StL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = z en = 1 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX HiZ) t12(67X HiZ) t13(57X HiZ) t14(37X HiZ) t15(SuH HiZ) +t21(76X HiZ) t22(StX HiZ) t23(56X HiZ) t24(36X HiZ) t25(StH HiZ) +t31(75X HiZ) t32(65X HiZ) t33(PuX HiZ) t34(35X HiZ) t35(PuH HiZ) +t41(73X HiZ) t42(63X HiZ) t43(53X HiZ) t44(WeX HiZ) t45(WeH HiZ) +t51(SuL HiZ) t52(StL HiZ) t53(PuL HiZ) t54(WeL HiZ) t55(HiZ HiZ) +a = 0 b = z en = z +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 StL) t12(St0 StL) t13(Pu0 PuL) t14(We0 WeL) t15(HiZ HiZ) +t21(Su0 StL) t22(St0 StL) t23(Pu0 PuL) t24(We0 WeL) t25(HiZ HiZ) +t31(Su0 StL) t32(St0 StL) t33(Pu0 PuL) t34(We0 WeL) t35(HiZ HiZ) +t41(Su0 StL) t42(St0 StL) t43(Pu0 PuL) t44(We0 WeL) t45(HiZ HiZ) +t51(Su0 StL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = z en = x +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 StL) t12(St0 StL) t13(Pu0 PuL) t14(We0 WeL) t15(HiZ HiZ) +t21(Su0 StL) t22(St0 StL) t23(Pu0 PuL) t24(We0 WeL) t25(HiZ HiZ) +t31(Su0 StL) t32(St0 StL) t33(Pu0 PuL) t34(We0 WeL) t35(HiZ HiZ) +t41(Su0 StL) t42(St0 StL) t43(Pu0 PuL) t44(We0 WeL) t45(HiZ HiZ) +t51(Su0 StL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = z en = 0 +a1(Su0) a2(St0) a3(St0) a4(St0) a5(St0) a6(St0) a7(St0) +t11(Su0 St0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 St0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 St0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 St0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 St0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = z en = 1 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 HiZ) t12(St0 HiZ) t13(Pu0 HiZ) t14(We0 HiZ) t15(HiZ HiZ) +t21(Su0 HiZ) t22(St0 HiZ) t23(Pu0 HiZ) t24(We0 HiZ) t25(HiZ HiZ) +t31(Su0 HiZ) t32(St0 HiZ) t33(Pu0 HiZ) t34(We0 HiZ) t35(HiZ HiZ) +t41(Su0 HiZ) t42(St0 HiZ) t43(Pu0 HiZ) t44(We0 HiZ) t45(HiZ HiZ) +t51(Su0 HiZ) t52(St0 HiZ) t53(Pu0 HiZ) t54(We0 HiZ) t55(HiZ HiZ) +a = 1 b = z en = z +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 StH) t12(Su1 StH) t13(Su1 StH) t14(Su1 StH) t15(Su1 StH) +t21(St1 StH) t22(St1 StH) t23(St1 StH) t24(St1 StH) t25(St1 StH) +t31(Pu1 PuH) t32(Pu1 PuH) t33(Pu1 PuH) t34(Pu1 PuH) t35(Pu1 PuH) +t41(We1 WeH) t42(We1 WeH) t43(We1 WeH) t44(We1 WeH) t45(We1 WeH) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = z en = x +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 StH) t12(Su1 StH) t13(Su1 StH) t14(Su1 StH) t15(Su1 StH) +t21(St1 StH) t22(St1 StH) t23(St1 StH) t24(St1 StH) t25(St1 StH) +t31(Pu1 PuH) t32(Pu1 PuH) t33(Pu1 PuH) t34(Pu1 PuH) t35(Pu1 PuH) +t41(We1 WeH) t42(We1 WeH) t43(We1 WeH) t44(We1 WeH) t45(We1 WeH) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = z en = 0 +a1(Su1) a2(St1) a3(St1) a4(St1) a5(St1) a6(St1) a7(St1) +t11(Su1 St1) t12(Su1 St1) t13(Su1 St1) t14(Su1 St1) t15(Su1 St1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = z en = 1 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 HiZ) t12(Su1 HiZ) t13(Su1 HiZ) t14(Su1 HiZ) t15(Su1 HiZ) +t21(St1 HiZ) t22(St1 HiZ) t23(St1 HiZ) t24(St1 HiZ) t25(St1 HiZ) +t31(Pu1 HiZ) t32(Pu1 HiZ) t33(Pu1 HiZ) t34(Pu1 HiZ) t35(Pu1 HiZ) +t41(We1 HiZ) t42(We1 HiZ) t43(We1 HiZ) t44(We1 HiZ) t45(We1 HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = x en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(StX SuX) t12(StX 67X) t13(56X 57X) t14(36X 37X) t15(StH SuH) +t21(StX 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(65X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(63X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(StL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = z b = x en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(StX SuX) t12(StX 67X) t13(56X 57X) t14(36X 37X) t15(StH SuH) +t21(StX 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(65X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(63X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(StL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = z b = x en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(StX SuX) t12(StX 67X) t13(56X 57X) t14(36X 37X) t15(StH SuH) +t21(StX 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(65X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(63X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(StL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = z b = x en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ SuX) t12(HiZ 67X) t13(HiZ 57X) t14(HiZ 37X) t15(HiZ SuH) +t21(HiZ 76X) t22(HiZ StX) t23(HiZ 56X) t24(HiZ 36X) t25(HiZ StH) +t31(HiZ 75X) t32(HiZ 65X) t33(HiZ PuX) t34(HiZ 35X) t35(HiZ PuH) +t41(HiZ 73X) t42(HiZ 63X) t43(HiZ 53X) t44(HiZ WeX) t45(HiZ WeH) +t51(HiZ SuL) t52(HiZ StL) t53(HiZ PuL) t54(HiZ WeL) t55(HiZ HiZ) +a = x b = x en = z +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = x en = x +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = x en = 0 +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = x en = 1 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = 0 b = x en = z +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 SuX) t12(StX 67X) t13(56X 57X) t14(36X 37X) t15(StH SuH) +t21(Su0 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(Su0 75X) t32(St0 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(Su0 73X) t42(St0 63X) t43(Pu0 53X) t44(WeX WeX) t45(WeH WeH) +t51(Su0 SuL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = x en = x +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 SuX) t12(StX 67X) t13(56X 57X) t14(36X 37X) t15(StH SuH) +t21(Su0 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(Su0 75X) t32(St0 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(Su0 73X) t42(St0 63X) t43(Pu0 53X) t44(WeX WeX) t45(WeH WeH) +t51(Su0 SuL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = x en = 0 +a1(Su0) a2(St0) a3(St0) a4(St0) a5(St0) a6(St0) a7(St0) +t11(Su0 SuX) t12(StX 67X) t13(56X 57X) t14(36X 37X) t15(StH SuH) +t21(Su0 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(Su0 760) t32(St0 St0) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(Su0 760) t42(St0 St0) t43(Pu0 Pu0) t44(WeX WeX) t45(WeH WeH) +t51(Su0 760) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = x en = 1 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 SuX) t12(St0 67X) t13(Pu0 57X) t14(We0 37X) t15(HiZ SuH) +t21(Su0 76X) t22(St0 StX) t23(Pu0 56X) t24(We0 36X) t25(HiZ StH) +t31(Su0 75X) t32(St0 65X) t33(Pu0 PuX) t34(We0 35X) t35(HiZ PuH) +t41(Su0 73X) t42(St0 63X) t43(Pu0 53X) t44(We0 WeX) t45(HiZ WeH) +t51(Su0 SuL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 1 b = x en = z +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 57X) t14(Su1 37X) t15(Su1 SuH) +t21(StX 76X) t22(StX StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(65X 75X) t32(65X 65X) t33(PuX PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(63X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(We1 WeH) +t51(StL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = 1 b = x en = x +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 57X) t14(Su1 37X) t15(Su1 SuH) +t21(StX 76X) t22(StX StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(65X 75X) t32(65X 65X) t33(PuX PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(63X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(We1 WeH) +t51(StL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = 1 b = x en = 0 +a1(Su1) a2(St1) a3(St1) a4(St1) a5(St1) a6(St1) a7(St1) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 761) t14(Su1 761) t15(Su1 761) +t21(StX 76X) t22(StX StX) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(65X 75X) t32(65X 65X) t33(PuX PuX) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(63X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(We1 We1) +t51(StL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = 1 b = x en = 1 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 57X) t14(Su1 37X) t15(Su1 SuH) +t21(St1 76X) t22(St1 StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(Pu1 75X) t32(Pu1 65X) t33(Pu1 PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(We1 73X) t42(We1 63X) t43(We1 53X) t44(We1 WeX) t45(We1 WeH) +t51(HiZ SuL) t52(HiZ StL) t53(HiZ PuL) t54(HiZ WeL) t55(HiZ HiZ) +a = z b = 0 en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(StL Su0) t12(StL St0) t13(PuL Pu0) t14(WeL We0) t15(HiZ HiZ) +t21(StL Su0) t22(StL St0) t23(PuL Pu0) t24(WeL We0) t25(HiZ HiZ) +t31(StL Su0) t32(StL St0) t33(PuL Pu0) t34(WeL We0) t35(HiZ HiZ) +t41(StL Su0) t42(StL St0) t43(PuL Pu0) t44(WeL We0) t45(HiZ HiZ) +t51(StL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = z b = 0 en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(StL Su0) t12(StL St0) t13(PuL Pu0) t14(WeL We0) t15(HiZ HiZ) +t21(StL Su0) t22(StL St0) t23(PuL Pu0) t24(WeL We0) t25(HiZ HiZ) +t31(StL Su0) t32(StL St0) t33(PuL Pu0) t34(WeL We0) t35(HiZ HiZ) +t41(StL Su0) t42(StL St0) t43(PuL Pu0) t44(WeL We0) t45(HiZ HiZ) +t51(StL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = z b = 0 en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(St0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(St0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(St0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(St0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(St0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = z b = 0 en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ Su0) t12(HiZ St0) t13(HiZ Pu0) t14(HiZ We0) t15(HiZ HiZ) +t21(HiZ Su0) t22(HiZ St0) t23(HiZ Pu0) t24(HiZ We0) t25(HiZ HiZ) +t31(HiZ Su0) t32(HiZ St0) t33(HiZ Pu0) t34(HiZ We0) t35(HiZ HiZ) +t41(HiZ Su0) t42(HiZ St0) t43(HiZ Pu0) t44(HiZ We0) t45(HiZ HiZ) +t51(HiZ Su0) t52(HiZ St0) t53(HiZ Pu0) t54(HiZ We0) t55(HiZ HiZ) +a = x b = 0 en = z +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX Su0) t12(67X StX) t13(57X 56X) t14(37X 36X) t15(SuH StH) +t21(76X Su0) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X Su0) t32(65X St0) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X Su0) t42(63X St0) t43(53X Pu0) t44(WeX WeX) t45(WeH WeH) +t51(SuL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = x b = 0 en = x +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX Su0) t12(67X StX) t13(57X 56X) t14(37X 36X) t15(SuH StH) +t21(76X Su0) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X Su0) t32(65X St0) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X Su0) t42(63X St0) t43(53X Pu0) t44(WeX WeX) t45(WeH WeH) +t51(SuL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = x b = 0 en = 0 +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX Su0) t12(67X StX) t13(57X 56X) t14(37X 36X) t15(SuH StH) +t21(76X Su0) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(760 Su0) t32(St0 St0) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(760 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(WeX WeX) t45(WeH WeH) +t51(760 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = x b = 0 en = 1 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX Su0) t12(67X St0) t13(57X Pu0) t14(37X We0) t15(SuH HiZ) +t21(76X Su0) t22(StX St0) t23(56X Pu0) t24(36X We0) t25(StH HiZ) +t31(75X Su0) t32(65X St0) t33(PuX Pu0) t34(35X We0) t35(PuH HiZ) +t41(73X Su0) t42(63X St0) t43(53X Pu0) t44(WeX We0) t45(WeH HiZ) +t51(SuL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = 0 b = 0 en = z +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = 0 en = x +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = 0 en = 0 +a1(Su0) a2(St0) a3(St0) a4(St0) a5(St0) a6(St0) a7(St0) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = 0 en = 1 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 1 b = 0 en = z +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 Su0) t12(Su1 StX) t13(Su1 56X) t14(Su1 36X) t15(Su1 StH) +t21(StX Su0) t22(StX StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(65X Su0) t32(65X St0) t33(PuX PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(63X Su0) t42(63X St0) t43(53X Pu0) t44(WeX WeX) t45(We1 WeH) +t51(StL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = 1 b = 0 en = x +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 Su0) t12(Su1 StX) t13(Su1 56X) t14(Su1 36X) t15(Su1 StH) +t21(StX Su0) t22(StX StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(65X Su0) t32(65X St0) t33(PuX PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(63X Su0) t42(63X St0) t43(53X Pu0) t44(WeX WeX) t45(We1 WeH) +t51(StL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = 1 b = 0 en = 0 +a1(Su1) a2(St1) a3(St1) a4(St1) a5(St1) a6(St1) a7(St1) +t11(Su1 Su0) t12(Su1 StX) t13(Su1 St1) t14(Su1 St1) t15(Su1 St1) +t21(StX Su0) t22(StX StX) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(St0 Su0) t32(St0 St0) t33(PuX PuX) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(St0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(WeX WeX) t45(We1 We1) +t51(St0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 1 b = 0 en = 1 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 Su0) t12(Su1 St0) t13(Su1 Pu0) t14(Su1 We0) t15(Su1 HiZ) +t21(St1 Su0) t22(St1 St0) t23(St1 Pu0) t24(St1 We0) t25(St1 HiZ) +t31(Pu1 Su0) t32(Pu1 St0) t33(Pu1 Pu0) t34(Pu1 We0) t35(Pu1 HiZ) +t41(We1 Su0) t42(We1 St0) t43(We1 Pu0) t44(We1 We0) t45(We1 HiZ) +t51(HiZ Su0) t52(HiZ St0) t53(HiZ Pu0) t54(HiZ We0) t55(HiZ HiZ) +a = z b = 1 en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(StH Su1) t12(StH Su1) t13(StH Su1) t14(StH Su1) t15(StH Su1) +t21(StH St1) t22(StH St1) t23(StH St1) t24(StH St1) t25(StH St1) +t31(PuH Pu1) t32(PuH Pu1) t33(PuH Pu1) t34(PuH Pu1) t35(PuH Pu1) +t41(WeH We1) t42(WeH We1) t43(WeH We1) t44(WeH We1) t45(WeH We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = 1 en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(StH Su1) t12(StH Su1) t13(StH Su1) t14(StH Su1) t15(StH Su1) +t21(StH St1) t22(StH St1) t23(StH St1) t24(StH St1) t25(StH St1) +t31(PuH Pu1) t32(PuH Pu1) t33(PuH Pu1) t34(PuH Pu1) t35(PuH Pu1) +t41(WeH We1) t42(WeH We1) t43(WeH We1) t44(WeH We1) t45(WeH We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = 1 en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(St1 Su1) t12(St1 Su1) t13(St1 Su1) t14(St1 Su1) t15(St1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = 1 en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ Su1) t12(HiZ Su1) t13(HiZ Su1) t14(HiZ Su1) t15(HiZ Su1) +t21(HiZ St1) t22(HiZ St1) t23(HiZ St1) t24(HiZ St1) t25(HiZ St1) +t31(HiZ Pu1) t32(HiZ Pu1) t33(HiZ Pu1) t34(HiZ Pu1) t35(HiZ Pu1) +t41(HiZ We1) t42(HiZ We1) t43(HiZ We1) t44(HiZ We1) t45(HiZ We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = x b = 1 en = z +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX Su1) t12(67X Su1) t13(57X Su1) t14(37X Su1) t15(SuH Su1) +t21(76X StX) t22(StX StX) t23(56X St1) t24(36X St1) t25(StH St1) +t31(75X 65X) t32(65X 65X) t33(PuX PuX) t34(35X Pu1) t35(PuH Pu1) +t41(73X 63X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH We1) +t51(SuL StL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = 1 en = x +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX Su1) t12(67X Su1) t13(57X Su1) t14(37X Su1) t15(SuH Su1) +t21(76X StX) t22(StX StX) t23(56X St1) t24(36X St1) t25(StH St1) +t31(75X 65X) t32(65X 65X) t33(PuX PuX) t34(35X Pu1) t35(PuH Pu1) +t41(73X 63X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH We1) +t51(SuL StL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = 1 en = 0 +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX Su1) t12(67X Su1) t13(761 Su1) t14(761 Su1) t15(761 Su1) +t21(76X StX) t22(StX StX) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(75X 65X) t32(65X 65X) t33(PuX PuX) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(73X 63X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(We1 We1) +t51(SuL StL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = 1 en = 1 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX Su1) t12(67X Su1) t13(57X Su1) t14(37X Su1) t15(SuH Su1) +t21(76X St1) t22(StX St1) t23(56X St1) t24(36X St1) t25(StH St1) +t31(75X Pu1) t32(65X Pu1) t33(PuX Pu1) t34(35X Pu1) t35(PuH Pu1) +t41(73X We1) t42(63X We1) t43(53X We1) t44(WeX We1) t45(WeH We1) +t51(SuL HiZ) t52(StL HiZ) t53(PuL HiZ) t54(WeL HiZ) t55(HiZ HiZ) +a = 0 b = 1 en = z +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 Su1) t12(StX Su1) t13(56X Su1) t14(36X Su1) t15(StH Su1) +t21(Su0 StX) t22(StX StX) t23(56X St1) t24(36X St1) t25(StH St1) +t31(Su0 65X) t32(St0 65X) t33(PuX PuX) t34(35X Pu1) t35(PuH Pu1) +t41(Su0 63X) t42(St0 63X) t43(Pu0 53X) t44(WeX WeX) t45(WeH We1) +t51(Su0 StL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = 1 en = x +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 Su1) t12(StX Su1) t13(56X Su1) t14(36X Su1) t15(StH Su1) +t21(Su0 StX) t22(StX StX) t23(56X St1) t24(36X St1) t25(StH St1) +t31(Su0 65X) t32(St0 65X) t33(PuX PuX) t34(35X Pu1) t35(PuH Pu1) +t41(Su0 63X) t42(St0 63X) t43(Pu0 53X) t44(WeX WeX) t45(WeH We1) +t51(Su0 StL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = 1 en = 0 +a1(Su0) a2(St0) a3(St0) a4(St0) a5(St0) a6(St0) a7(St0) +t11(Su0 Su1) t12(StX Su1) t13(St1 Su1) t14(St1 Su1) t15(St1 Su1) +t21(Su0 StX) t22(StX StX) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Su0 St0) t32(St0 St0) t33(PuX PuX) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(Su0 St0) t42(St0 St0) t43(Pu0 Pu0) t44(WeX WeX) t45(We1 We1) +t51(Su0 St0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = 1 en = 1 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 Su1) t12(St0 Su1) t13(Pu0 Su1) t14(We0 Su1) t15(HiZ Su1) +t21(Su0 St1) t22(St0 St1) t23(Pu0 St1) t24(We0 St1) t25(HiZ St1) +t31(Su0 Pu1) t32(St0 Pu1) t33(Pu0 Pu1) t34(We0 Pu1) t35(HiZ Pu1) +t41(Su0 We1) t42(St0 We1) t43(Pu0 We1) t44(We0 We1) t45(HiZ We1) +t51(Su0 HiZ) t52(St0 HiZ) t53(Pu0 HiZ) t54(We0 HiZ) t55(HiZ HiZ) +a = 1 b = 1 en = z +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = 1 en = x +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = 1 en = 0 +a1(Su1) a2(St1) a3(St1) a4(St1) a5(St1) a6(St1) a7(St1) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = 1 en = 1 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) diff --git a/ivtest/gold/tranif1.gold b/ivtest/gold/tranif1.gold new file mode 100644 index 000000000..9720bc4c1 --- /dev/null +++ b/ivtest/gold/tranif1.gold @@ -0,0 +1,448 @@ +a = z b = z en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = z en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = z en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = z en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ HiZ) t12(HiZ HiZ) t13(HiZ HiZ) t14(HiZ HiZ) t15(HiZ HiZ) +t21(HiZ HiZ) t22(HiZ HiZ) t23(HiZ HiZ) t24(HiZ HiZ) t25(HiZ HiZ) +t31(HiZ HiZ) t32(HiZ HiZ) t33(HiZ HiZ) t34(HiZ HiZ) t35(HiZ HiZ) +t41(HiZ HiZ) t42(HiZ HiZ) t43(HiZ HiZ) t44(HiZ HiZ) t45(HiZ HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = x b = z en = z +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX StX) t12(67X StX) t13(57X 56X) t14(37X 36X) t15(SuH StH) +t21(76X StX) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 65X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 63X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL StL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = z en = x +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX StX) t12(67X StX) t13(57X 56X) t14(37X 36X) t15(SuH StH) +t21(76X StX) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 65X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 63X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL StL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = z en = 0 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX HiZ) t12(67X HiZ) t13(57X HiZ) t14(37X HiZ) t15(SuH HiZ) +t21(76X HiZ) t22(StX HiZ) t23(56X HiZ) t24(36X HiZ) t25(StH HiZ) +t31(75X HiZ) t32(65X HiZ) t33(PuX HiZ) t34(35X HiZ) t35(PuH HiZ) +t41(73X HiZ) t42(63X HiZ) t43(53X HiZ) t44(WeX HiZ) t45(WeH HiZ) +t51(SuL HiZ) t52(StL HiZ) t53(PuL HiZ) t54(WeL HiZ) t55(HiZ HiZ) +a = x b = z en = 1 +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX StX) t12(67X StX) t13(57X 56X) t14(37X 36X) t15(SuH StH) +t21(76X StX) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 65X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 63X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL StL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = 0 b = z en = z +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 StL) t12(St0 StL) t13(Pu0 PuL) t14(We0 WeL) t15(HiZ HiZ) +t21(Su0 StL) t22(St0 StL) t23(Pu0 PuL) t24(We0 WeL) t25(HiZ HiZ) +t31(Su0 StL) t32(St0 StL) t33(Pu0 PuL) t34(We0 WeL) t35(HiZ HiZ) +t41(Su0 StL) t42(St0 StL) t43(Pu0 PuL) t44(We0 WeL) t45(HiZ HiZ) +t51(Su0 StL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = z en = x +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 StL) t12(St0 StL) t13(Pu0 PuL) t14(We0 WeL) t15(HiZ HiZ) +t21(Su0 StL) t22(St0 StL) t23(Pu0 PuL) t24(We0 WeL) t25(HiZ HiZ) +t31(Su0 StL) t32(St0 StL) t33(Pu0 PuL) t34(We0 WeL) t35(HiZ HiZ) +t41(Su0 StL) t42(St0 StL) t43(Pu0 PuL) t44(We0 WeL) t45(HiZ HiZ) +t51(Su0 StL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = z en = 0 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 HiZ) t12(St0 HiZ) t13(Pu0 HiZ) t14(We0 HiZ) t15(HiZ HiZ) +t21(Su0 HiZ) t22(St0 HiZ) t23(Pu0 HiZ) t24(We0 HiZ) t25(HiZ HiZ) +t31(Su0 HiZ) t32(St0 HiZ) t33(Pu0 HiZ) t34(We0 HiZ) t35(HiZ HiZ) +t41(Su0 HiZ) t42(St0 HiZ) t43(Pu0 HiZ) t44(We0 HiZ) t45(HiZ HiZ) +t51(Su0 HiZ) t52(St0 HiZ) t53(Pu0 HiZ) t54(We0 HiZ) t55(HiZ HiZ) +a = 0 b = z en = 1 +a1(Su0) a2(St0) a3(St0) a4(St0) a5(St0) a6(St0) a7(St0) +t11(Su0 St0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 St0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 St0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 St0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 St0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 1 b = z en = z +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 StH) t12(Su1 StH) t13(Su1 StH) t14(Su1 StH) t15(Su1 StH) +t21(St1 StH) t22(St1 StH) t23(St1 StH) t24(St1 StH) t25(St1 StH) +t31(Pu1 PuH) t32(Pu1 PuH) t33(Pu1 PuH) t34(Pu1 PuH) t35(Pu1 PuH) +t41(We1 WeH) t42(We1 WeH) t43(We1 WeH) t44(We1 WeH) t45(We1 WeH) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = z en = x +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 StH) t12(Su1 StH) t13(Su1 StH) t14(Su1 StH) t15(Su1 StH) +t21(St1 StH) t22(St1 StH) t23(St1 StH) t24(St1 StH) t25(St1 StH) +t31(Pu1 PuH) t32(Pu1 PuH) t33(Pu1 PuH) t34(Pu1 PuH) t35(Pu1 PuH) +t41(We1 WeH) t42(We1 WeH) t43(We1 WeH) t44(We1 WeH) t45(We1 WeH) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = z en = 0 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 HiZ) t12(Su1 HiZ) t13(Su1 HiZ) t14(Su1 HiZ) t15(Su1 HiZ) +t21(St1 HiZ) t22(St1 HiZ) t23(St1 HiZ) t24(St1 HiZ) t25(St1 HiZ) +t31(Pu1 HiZ) t32(Pu1 HiZ) t33(Pu1 HiZ) t34(Pu1 HiZ) t35(Pu1 HiZ) +t41(We1 HiZ) t42(We1 HiZ) t43(We1 HiZ) t44(We1 HiZ) t45(We1 HiZ) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = z en = 1 +a1(Su1) a2(St1) a3(St1) a4(St1) a5(St1) a6(St1) a7(St1) +t11(Su1 St1) t12(Su1 St1) t13(Su1 St1) t14(Su1 St1) t15(Su1 St1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = x en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(StX SuX) t12(StX 67X) t13(56X 57X) t14(36X 37X) t15(StH SuH) +t21(StX 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(65X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(63X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(StL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = z b = x en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(StX SuX) t12(StX 67X) t13(56X 57X) t14(36X 37X) t15(StH SuH) +t21(StX 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(65X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(63X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(StL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = z b = x en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ SuX) t12(HiZ 67X) t13(HiZ 57X) t14(HiZ 37X) t15(HiZ SuH) +t21(HiZ 76X) t22(HiZ StX) t23(HiZ 56X) t24(HiZ 36X) t25(HiZ StH) +t31(HiZ 75X) t32(HiZ 65X) t33(HiZ PuX) t34(HiZ 35X) t35(HiZ PuH) +t41(HiZ 73X) t42(HiZ 63X) t43(HiZ 53X) t44(HiZ WeX) t45(HiZ WeH) +t51(HiZ SuL) t52(HiZ StL) t53(HiZ PuL) t54(HiZ WeL) t55(HiZ HiZ) +a = z b = x en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(StX SuX) t12(StX 67X) t13(56X 57X) t14(36X 37X) t15(StH SuH) +t21(StX 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(65X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(63X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(StL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = x en = z +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = x en = x +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = x en = 0 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = x en = 1 +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX SuX) t12(67X 67X) t13(57X 57X) t14(37X 37X) t15(SuH SuH) +t21(76X 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X 75X) t32(65X 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH WeH) +t51(SuL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = 0 b = x en = z +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 SuX) t12(StX 67X) t13(56X 57X) t14(36X 37X) t15(StH SuH) +t21(Su0 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(Su0 75X) t32(St0 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(Su0 73X) t42(St0 63X) t43(Pu0 53X) t44(WeX WeX) t45(WeH WeH) +t51(Su0 SuL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = x en = x +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 SuX) t12(StX 67X) t13(56X 57X) t14(36X 37X) t15(StH SuH) +t21(Su0 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(Su0 75X) t32(St0 65X) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(Su0 73X) t42(St0 63X) t43(Pu0 53X) t44(WeX WeX) t45(WeH WeH) +t51(Su0 SuL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = x en = 0 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 SuX) t12(St0 67X) t13(Pu0 57X) t14(We0 37X) t15(HiZ SuH) +t21(Su0 76X) t22(St0 StX) t23(Pu0 56X) t24(We0 36X) t25(HiZ StH) +t31(Su0 75X) t32(St0 65X) t33(Pu0 PuX) t34(We0 35X) t35(HiZ PuH) +t41(Su0 73X) t42(St0 63X) t43(Pu0 53X) t44(We0 WeX) t45(HiZ WeH) +t51(Su0 SuL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = x en = 1 +a1(Su0) a2(St0) a3(St0) a4(St0) a5(St0) a6(St0) a7(St0) +t11(Su0 SuX) t12(StX 67X) t13(56X 57X) t14(36X 37X) t15(StH SuH) +t21(Su0 76X) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(Su0 760) t32(St0 St0) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(Su0 760) t42(St0 St0) t43(Pu0 Pu0) t44(WeX WeX) t45(WeH WeH) +t51(Su0 760) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 1 b = x en = z +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 57X) t14(Su1 37X) t15(Su1 SuH) +t21(StX 76X) t22(StX StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(65X 75X) t32(65X 65X) t33(PuX PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(63X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(We1 WeH) +t51(StL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = 1 b = x en = x +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 57X) t14(Su1 37X) t15(Su1 SuH) +t21(StX 76X) t22(StX StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(65X 75X) t32(65X 65X) t33(PuX PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(63X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(We1 WeH) +t51(StL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = 1 b = x en = 0 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 57X) t14(Su1 37X) t15(Su1 SuH) +t21(St1 76X) t22(St1 StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(Pu1 75X) t32(Pu1 65X) t33(Pu1 PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(We1 73X) t42(We1 63X) t43(We1 53X) t44(We1 WeX) t45(We1 WeH) +t51(HiZ SuL) t52(HiZ StL) t53(HiZ PuL) t54(HiZ WeL) t55(HiZ HiZ) +a = 1 b = x en = 1 +a1(Su1) a2(St1) a3(St1) a4(St1) a5(St1) a6(St1) a7(St1) +t11(Su1 SuX) t12(Su1 67X) t13(Su1 761) t14(Su1 761) t15(Su1 761) +t21(StX 76X) t22(StX StX) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(65X 75X) t32(65X 65X) t33(PuX PuX) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(63X 73X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(We1 We1) +t51(StL SuL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = z b = 0 en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(StL Su0) t12(StL St0) t13(PuL Pu0) t14(WeL We0) t15(HiZ HiZ) +t21(StL Su0) t22(StL St0) t23(PuL Pu0) t24(WeL We0) t25(HiZ HiZ) +t31(StL Su0) t32(StL St0) t33(PuL Pu0) t34(WeL We0) t35(HiZ HiZ) +t41(StL Su0) t42(StL St0) t43(PuL Pu0) t44(WeL We0) t45(HiZ HiZ) +t51(StL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = z b = 0 en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(StL Su0) t12(StL St0) t13(PuL Pu0) t14(WeL We0) t15(HiZ HiZ) +t21(StL Su0) t22(StL St0) t23(PuL Pu0) t24(WeL We0) t25(HiZ HiZ) +t31(StL Su0) t32(StL St0) t33(PuL Pu0) t34(WeL We0) t35(HiZ HiZ) +t41(StL Su0) t42(StL St0) t43(PuL Pu0) t44(WeL We0) t45(HiZ HiZ) +t51(StL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = z b = 0 en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ Su0) t12(HiZ St0) t13(HiZ Pu0) t14(HiZ We0) t15(HiZ HiZ) +t21(HiZ Su0) t22(HiZ St0) t23(HiZ Pu0) t24(HiZ We0) t25(HiZ HiZ) +t31(HiZ Su0) t32(HiZ St0) t33(HiZ Pu0) t34(HiZ We0) t35(HiZ HiZ) +t41(HiZ Su0) t42(HiZ St0) t43(HiZ Pu0) t44(HiZ We0) t45(HiZ HiZ) +t51(HiZ Su0) t52(HiZ St0) t53(HiZ Pu0) t54(HiZ We0) t55(HiZ HiZ) +a = z b = 0 en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(St0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(St0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(St0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(St0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(St0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = x b = 0 en = z +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX Su0) t12(67X StX) t13(57X 56X) t14(37X 36X) t15(SuH StH) +t21(76X Su0) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X Su0) t32(65X St0) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X Su0) t42(63X St0) t43(53X Pu0) t44(WeX WeX) t45(WeH WeH) +t51(SuL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = x b = 0 en = x +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX Su0) t12(67X StX) t13(57X 56X) t14(37X 36X) t15(SuH StH) +t21(76X Su0) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(75X Su0) t32(65X St0) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(73X Su0) t42(63X St0) t43(53X Pu0) t44(WeX WeX) t45(WeH WeH) +t51(SuL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = x b = 0 en = 0 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX Su0) t12(67X St0) t13(57X Pu0) t14(37X We0) t15(SuH HiZ) +t21(76X Su0) t22(StX St0) t23(56X Pu0) t24(36X We0) t25(StH HiZ) +t31(75X Su0) t32(65X St0) t33(PuX Pu0) t34(35X We0) t35(PuH HiZ) +t41(73X Su0) t42(63X St0) t43(53X Pu0) t44(WeX We0) t45(WeH HiZ) +t51(SuL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = x b = 0 en = 1 +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX Su0) t12(67X StX) t13(57X 56X) t14(37X 36X) t15(SuH StH) +t21(76X Su0) t22(StX StX) t23(56X 56X) t24(36X 36X) t25(StH StH) +t31(760 Su0) t32(St0 St0) t33(PuX PuX) t34(35X 35X) t35(PuH PuH) +t41(760 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(WeX WeX) t45(WeH WeH) +t51(760 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = 0 en = z +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = 0 en = x +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = 0 en = 0 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 0 b = 0 en = 1 +a1(Su0) a2(St0) a3(St0) a4(St0) a5(St0) a6(St0) a7(St0) +t11(Su0 Su0) t12(St0 St0) t13(Pu0 Pu0) t14(We0 We0) t15(HiZ HiZ) +t21(Su0 Su0) t22(St0 St0) t23(Pu0 Pu0) t24(We0 We0) t25(HiZ HiZ) +t31(Su0 Su0) t32(St0 St0) t33(Pu0 Pu0) t34(We0 We0) t35(HiZ HiZ) +t41(Su0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(We0 We0) t45(HiZ HiZ) +t51(Su0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 1 b = 0 en = z +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 Su0) t12(Su1 StX) t13(Su1 56X) t14(Su1 36X) t15(Su1 StH) +t21(StX Su0) t22(StX StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(65X Su0) t32(65X St0) t33(PuX PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(63X Su0) t42(63X St0) t43(53X Pu0) t44(WeX WeX) t45(We1 WeH) +t51(StL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = 1 b = 0 en = x +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 Su0) t12(Su1 StX) t13(Su1 56X) t14(Su1 36X) t15(Su1 StH) +t21(StX Su0) t22(StX StX) t23(St1 56X) t24(St1 36X) t25(St1 StH) +t31(65X Su0) t32(65X St0) t33(PuX PuX) t34(Pu1 35X) t35(Pu1 PuH) +t41(63X Su0) t42(63X St0) t43(53X Pu0) t44(WeX WeX) t45(We1 WeH) +t51(StL Su0) t52(StL St0) t53(PuL Pu0) t54(WeL We0) t55(HiZ HiZ) +a = 1 b = 0 en = 0 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 Su0) t12(Su1 St0) t13(Su1 Pu0) t14(Su1 We0) t15(Su1 HiZ) +t21(St1 Su0) t22(St1 St0) t23(St1 Pu0) t24(St1 We0) t25(St1 HiZ) +t31(Pu1 Su0) t32(Pu1 St0) t33(Pu1 Pu0) t34(Pu1 We0) t35(Pu1 HiZ) +t41(We1 Su0) t42(We1 St0) t43(We1 Pu0) t44(We1 We0) t45(We1 HiZ) +t51(HiZ Su0) t52(HiZ St0) t53(HiZ Pu0) t54(HiZ We0) t55(HiZ HiZ) +a = 1 b = 0 en = 1 +a1(Su1) a2(St1) a3(St1) a4(St1) a5(St1) a6(St1) a7(St1) +t11(Su1 Su0) t12(Su1 StX) t13(Su1 St1) t14(Su1 St1) t15(Su1 St1) +t21(StX Su0) t22(StX StX) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(St0 Su0) t32(St0 St0) t33(PuX PuX) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(St0 Su0) t42(St0 St0) t43(Pu0 Pu0) t44(WeX WeX) t45(We1 We1) +t51(St0 Su0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = z b = 1 en = z +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(StH Su1) t12(StH Su1) t13(StH Su1) t14(StH Su1) t15(StH Su1) +t21(StH St1) t22(StH St1) t23(StH St1) t24(StH St1) t25(StH St1) +t31(PuH Pu1) t32(PuH Pu1) t33(PuH Pu1) t34(PuH Pu1) t35(PuH Pu1) +t41(WeH We1) t42(WeH We1) t43(WeH We1) t44(WeH We1) t45(WeH We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = 1 en = x +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(StH Su1) t12(StH Su1) t13(StH Su1) t14(StH Su1) t15(StH Su1) +t21(StH St1) t22(StH St1) t23(StH St1) t24(StH St1) t25(StH St1) +t31(PuH Pu1) t32(PuH Pu1) t33(PuH Pu1) t34(PuH Pu1) t35(PuH Pu1) +t41(WeH We1) t42(WeH We1) t43(WeH We1) t44(WeH We1) t45(WeH We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = 1 en = 0 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(HiZ Su1) t12(HiZ Su1) t13(HiZ Su1) t14(HiZ Su1) t15(HiZ Su1) +t21(HiZ St1) t22(HiZ St1) t23(HiZ St1) t24(HiZ St1) t25(HiZ St1) +t31(HiZ Pu1) t32(HiZ Pu1) t33(HiZ Pu1) t34(HiZ Pu1) t35(HiZ Pu1) +t41(HiZ We1) t42(HiZ We1) t43(HiZ We1) t44(HiZ We1) t45(HiZ We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = z b = 1 en = 1 +a1(HiZ) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(St1 Su1) t12(St1 Su1) t13(St1 Su1) t14(St1 Su1) t15(St1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = x b = 1 en = z +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX Su1) t12(67X Su1) t13(57X Su1) t14(37X Su1) t15(SuH Su1) +t21(76X StX) t22(StX StX) t23(56X St1) t24(36X St1) t25(StH St1) +t31(75X 65X) t32(65X 65X) t33(PuX PuX) t34(35X Pu1) t35(PuH Pu1) +t41(73X 63X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH We1) +t51(SuL StL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = 1 en = x +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX Su1) t12(67X Su1) t13(57X Su1) t14(37X Su1) t15(SuH Su1) +t21(76X StX) t22(StX StX) t23(56X St1) t24(36X St1) t25(StH St1) +t31(75X 65X) t32(65X 65X) t33(PuX PuX) t34(35X Pu1) t35(PuH Pu1) +t41(73X 63X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(WeH We1) +t51(SuL StL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = x b = 1 en = 0 +a1(SuX) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(SuX Su1) t12(67X Su1) t13(57X Su1) t14(37X Su1) t15(SuH Su1) +t21(76X St1) t22(StX St1) t23(56X St1) t24(36X St1) t25(StH St1) +t31(75X Pu1) t32(65X Pu1) t33(PuX Pu1) t34(35X Pu1) t35(PuH Pu1) +t41(73X We1) t42(63X We1) t43(53X We1) t44(WeX We1) t45(WeH We1) +t51(SuL HiZ) t52(StL HiZ) t53(PuL HiZ) t54(WeL HiZ) t55(HiZ HiZ) +a = x b = 1 en = 1 +a1(SuX) a2(StX) a3(StX) a4(StX) a5(StX) a6(StX) a7(StX) +t11(SuX Su1) t12(67X Su1) t13(761 Su1) t14(761 Su1) t15(761 Su1) +t21(76X StX) t22(StX StX) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(75X 65X) t32(65X 65X) t33(PuX PuX) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(73X 63X) t42(63X 63X) t43(53X 53X) t44(WeX WeX) t45(We1 We1) +t51(SuL StL) t52(StL StL) t53(PuL PuL) t54(WeL WeL) t55(HiZ HiZ) +a = 0 b = 1 en = z +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 Su1) t12(StX Su1) t13(56X Su1) t14(36X Su1) t15(StH Su1) +t21(Su0 StX) t22(StX StX) t23(56X St1) t24(36X St1) t25(StH St1) +t31(Su0 65X) t32(St0 65X) t33(PuX PuX) t34(35X Pu1) t35(PuH Pu1) +t41(Su0 63X) t42(St0 63X) t43(Pu0 53X) t44(WeX WeX) t45(WeH We1) +t51(Su0 StL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = 1 en = x +a1(Su0) a2(StL) a3(StL) a4(StL) a5(StL) a6(StL) a7(StL) +t11(Su0 Su1) t12(StX Su1) t13(56X Su1) t14(36X Su1) t15(StH Su1) +t21(Su0 StX) t22(StX StX) t23(56X St1) t24(36X St1) t25(StH St1) +t31(Su0 65X) t32(St0 65X) t33(PuX PuX) t34(35X Pu1) t35(PuH Pu1) +t41(Su0 63X) t42(St0 63X) t43(Pu0 53X) t44(WeX WeX) t45(WeH We1) +t51(Su0 StL) t52(St0 StL) t53(Pu0 PuL) t54(We0 WeL) t55(HiZ HiZ) +a = 0 b = 1 en = 0 +a1(Su0) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su0 Su1) t12(St0 Su1) t13(Pu0 Su1) t14(We0 Su1) t15(HiZ Su1) +t21(Su0 St1) t22(St0 St1) t23(Pu0 St1) t24(We0 St1) t25(HiZ St1) +t31(Su0 Pu1) t32(St0 Pu1) t33(Pu0 Pu1) t34(We0 Pu1) t35(HiZ Pu1) +t41(Su0 We1) t42(St0 We1) t43(Pu0 We1) t44(We0 We1) t45(HiZ We1) +t51(Su0 HiZ) t52(St0 HiZ) t53(Pu0 HiZ) t54(We0 HiZ) t55(HiZ HiZ) +a = 0 b = 1 en = 1 +a1(Su0) a2(St0) a3(St0) a4(St0) a5(St0) a6(St0) a7(St0) +t11(Su0 Su1) t12(StX Su1) t13(St1 Su1) t14(St1 Su1) t15(St1 Su1) +t21(Su0 StX) t22(StX StX) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Su0 St0) t32(St0 St0) t33(PuX PuX) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(Su0 St0) t42(St0 St0) t43(Pu0 Pu0) t44(WeX WeX) t45(We1 We1) +t51(Su0 St0) t52(St0 St0) t53(Pu0 Pu0) t54(We0 We0) t55(HiZ HiZ) +a = 1 b = 1 en = z +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = 1 en = x +a1(Su1) a2(StH) a3(StH) a4(StH) a5(StH) a6(StH) a7(StH) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = 1 en = 0 +a1(Su1) a2(HiZ) a3(HiZ) a4(HiZ) a5(HiZ) a6(HiZ) a7(HiZ) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) +a = 1 b = 1 en = 1 +a1(Su1) a2(St1) a3(St1) a4(St1) a5(St1) a6(St1) a7(St1) +t11(Su1 Su1) t12(Su1 Su1) t13(Su1 Su1) t14(Su1 Su1) t15(Su1 Su1) +t21(St1 St1) t22(St1 St1) t23(St1 St1) t24(St1 St1) t25(St1 St1) +t31(Pu1 Pu1) t32(Pu1 Pu1) t33(Pu1 Pu1) t34(Pu1 Pu1) t35(Pu1 Pu1) +t41(We1 We1) t42(We1 We1) t43(We1 We1) t44(We1 We1) t45(We1 We1) +t51(HiZ HiZ) t52(HiZ HiZ) t53(HiZ HiZ) t54(HiZ HiZ) t55(HiZ HiZ) diff --git a/ivtest/gold/two_state_display.gold b/ivtest/gold/two_state_display.gold new file mode 100644 index 000000000..55f41556a --- /dev/null +++ b/ivtest/gold/two_state_display.gold @@ -0,0 +1,43 @@ +Vec: 9 +Bit: 0 +Byte: 0 +Short: 0 +Int: 0 +Long: 0 +Monitor results: +Time: 0 + Bit: 0 + Byte: 0 + Short: 0 + Int: 0 + Long: 0 +Time: 1 + Bit: 1 + Byte: 0 + Short: 0 + Int: 0 + Long: 0 +Time: 2 + Bit: 1 + Byte: 1 + Short: 0 + Int: 0 + Long: 0 +Time: 3 + Bit: 1 + Byte: 1 + Short: 1 + Int: 0 + Long: 0 +Time: 4 + Bit: 1 + Byte: 1 + Short: 1 + Int: 1 + Long: 0 +Time: 5 + Bit: 1 + Byte: 1 + Short: 1 + Int: 1 + Long: 1 diff --git a/ivtest/gold/udp_bx.gold b/ivtest/gold/udp_bx.gold new file mode 100644 index 000000000..1d9b90ff3 --- /dev/null +++ b/ivtest/gold/udp_bx.gold @@ -0,0 +1,6 @@ + 0 CL = 0, D = 1, Q = 0 + 10 CL = x, D = 1, Q = x + 20 CL = 0, D = 1, Q = 0 + 30 CL = x, D = 1, Q = x + 40 CL = 1, D = 1, Q = x + 50 CL = 1, D = 1, Q = 1 diff --git a/ivtest/gold/undef.gold b/ivtest/gold/undef.gold new file mode 100644 index 000000000..2d04a1f00 --- /dev/null +++ b/ivtest/gold/undef.gold @@ -0,0 +1,2 @@ +./ivltests/undef.v:23: warning: macro a undefined (and assumed null) at this point. +PASSED diff --git a/ivtest/gold/unnamed_generate_block.gold b/ivtest/gold/unnamed_generate_block.gold new file mode 100644 index 000000000..bc856dafa --- /dev/null +++ b/ivtest/gold/unnamed_generate_block.gold @@ -0,0 +1,4 @@ +0 +1 +2 +3 diff --git a/ivtest/gold/urand.gold b/ivtest/gold/urand.gold new file mode 100644 index 000000000..b42d3dabf --- /dev/null +++ b/ivtest/gold/urand.gold @@ -0,0 +1,61 @@ + 0 0 +2450863396 2450863396 +1082744449 1082744449 + 75814409 75814409 + 837834339 837834339 +2260302605 2260302605 +3336542605 3336542605 + 851608677 851608677 + 154620434 154620434 +2163467009 2163467009 +2262289677 2262289677 +3139694966 3139694966 +2660093245 2660093245 +4141111277 4141111277 +3324901260 3324901260 +4244498937 4244498937 +1664558278 1664558278 +1660388549 1660388549 +1427362474 1427362474 +4071618533 4071618533 +1003647607 1003647607 + 154326546 154326546 +3354188687 3354188687 +4180699634 4180699634 +1735825102 1735825102 +1946188520 1946188520 +1657425605 1657425605 +2925021532 2925021532 +1586374845 1586374845 + 380327981 380327981 + 849815141 849815141 + 837771875 837771875 +2238940938 2238940938 +1077617280 1077617280 +2422481184 2422481184 +3581429162 3581429162 +1322044573 1322044573 +1260404374 1260404374 + 159627283 159627283 + 112998413 112998413 + 698865235 698865235 +3047153003 3047153003 +1789274837 1789274837 + 18303490 18303490 +1465269934 1465269934 +2399136029 2399136029 +1740993231 1740993231 +2441365795 2441365795 +2231985418 2231985418 +1702038218 1702038218 + 506547260 506547260 +4184391154 4184391154 +3308151178 3308151178 +2697245505 2697245505 +1816868056 1816868056 +3156276088 3156276088 +1149899401 1149899401 +4123332075 4123332075 +3674367414 3674367414 +3813407174 3813407174 +3608482734 3608482734 diff --git a/ivtest/gold/urand_r.gold b/ivtest/gold/urand_r.gold new file mode 100644 index 000000000..09cf9ed0f --- /dev/null +++ b/ivtest/gold/urand_r.gold @@ -0,0 +1,57 @@ + 0 + 9 + 4 + 0 + 3 + 8 + 13 + 3 + 0 + 8 + 12 + 10 + 16 + 13 + 16 + 6 + 5 + 16 + 3 + 0 + 13 + 16 + 6 + 7 + 6 + 11 + 6 + 1 + 3 + 8 + 4 + 9 + 14 + 5 + 4 + 0 + 2 + 12 + 7 + 0 + 5 + 9 + 6 + 9 + 8 + 6 + 2 + 16 + 13 + 10 + 7 + 12 + 4 + 16 + 14 + 15 + 14 diff --git a/ivtest/gold/uwire_fail.gold b/ivtest/gold/uwire_fail.gold new file mode 100644 index 000000000..3d0474a9f --- /dev/null +++ b/ivtest/gold/uwire_fail.gold @@ -0,0 +1,2 @@ +./ivltests/uwire_fail.v:5: error: Unresolved net/uwire two cannot have multiple drivers. +1 error(s) during elaboration. diff --git a/ivtest/gold/vcd-dup.log.gold b/ivtest/gold/vcd-dup.log.gold new file mode 100644 index 000000000..755fff3de --- /dev/null +++ b/ivtest/gold/vcd-dup.log.gold @@ -0,0 +1,4 @@ +VCD info: dumpfile work/vcd-dup.vcd opened for output. +VCD warning: skipping signal test.m2.c1, it was previously included. +VCD warning: ignoring signals in previously scanned scope test.m1. +VCD warning: $dumpvars ignored, previously called at simtime 0 diff --git a/ivtest/gold/vcd-dup.vcd.gold b/ivtest/gold/vcd-dup.vcd.gold new file mode 100644 index 000000000..2439e1a37 --- /dev/null +++ b/ivtest/gold/vcd-dup.vcd.gold @@ -0,0 +1,195 @@ +$date + Fri Oct 16 08:46:35 2009 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module test $end +$var wire 1 ! c2 $end +$var wire 1 " c1 $end +$var reg 1 # a $end +$var reg 1 $ b1 $end +$var reg 1 % b2 $end +$scope module m1 $end +$var wire 1 # a $end +$var wire 1 $ b $end +$var wire 1 " c $end +$var wire 1 & c2 $end +$var wire 1 ' c1 $end +$upscope $end +$scope module m2 $end +$var wire 1 # a $end +$var wire 1 % b $end +$var wire 1 ! c $end +$var wire 1 ( c2 $end +$var wire 1 ) c1 $end +$upscope $end +$scope task set $end +$var reg 3 * bits [2:0] $end +$var reg 1 + t1 $end +$upscope $end +$upscope $end +$scope module test $end +$scope module m1 $end +$scope module mm1 $end +$var wire 1 , c1 $end +$upscope $end +$upscope $end +$upscope $end +$scope module test $end +$scope module m1 $end +$scope module mm1 $end +$var wire 1 - a $end +$var wire 1 ' c $end +$upscope $end +$scope module mm2 $end +$var wire 1 . a $end +$var wire 1 & c $end +$var wire 1 / c1 $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +x/ +x. +0- +1, +x+ +bx * +1) +x( +1' +x& +x% +x$ +0# +x" +x! +$end +#1 +0+ +b0 * +#2 +0" +0! +1& +1/ +1( +0. +0$ +0% +#4 +b1 * +#5 +1! +0( +1% +#7 +b10 * +#8 +1" +0! +0& +0/ +1( +1. +1$ +0% +#9 +$dumpoff +x/ +x. +x- +x, +x+ +bx * +x) +x( +x' +x& +x% +x$ +x# +x" +x! +$end +#15 +$dumpon +0/ +1. +0- +1, +0+ +b100 * +1) +0( +1' +0& +0% +0$ +1# +1" +1! +$end +#16 +1+ +b101 * +#17 +0! +0) +1% +#19 +b110 * +#20 +0" +1! +0' +0, +1) +1- +1$ +0% +#22 +b111 * +#23 +0! +0) +1% +#25 +b0 * +#26 +1' +1, +1& +1/ +1) +1( +0- +0. +0# +0$ +0% +#27 +$dumpall +1/ +0. +0- +1, +1+ +b0 * +1) +1( +1' +1& +0% +0$ +0# +0" +0! +$end +#28 diff --git a/ivtest/gold/vector.gold b/ivtest/gold/vector.gold new file mode 100644 index 000000000..f48fbbac7 --- /dev/null +++ b/ivtest/gold/vector.gold @@ -0,0 +1,44 @@ +foo40= 0 + foo04= 0 + foo51= 0 + foo15= 0 +foo40= 1 + foo04= 1 + foo51= 1 + foo15= 1 +foo40= 2 + foo04= 2 + foo51= 2 + foo15= 2 +foo40= 3 + foo04= 3 + foo51= 3 + foo15= 3 +foo40= 4 + foo04= 4 + foo51= 4 + foo15= 4 +foo40= 5 + foo04= 5 + foo51= 5 + foo15= 5 +foo40= 6 + foo04= 6 + foo51= 6 + foo15= 6 +foo40= 7 + foo04= 7 + foo51= 7 + foo15= 7 +foo40= 8 + foo04= 8 + foo51= 8 + foo15= 8 +foo40= 9 + foo04= 9 + foo51= 9 + foo15= 9 +foo40= 10 + foo04= 10 + foo51= 10 + foo15= 10 diff --git a/ivtest/gold/vhdl_concurrent_assert.gold b/ivtest/gold/vhdl_concurrent_assert.gold new file mode 100644 index 000000000..3cf76203c --- /dev/null +++ b/ivtest/gold/vhdl_concurrent_assert.gold @@ -0,0 +1 @@ +** Note: this assert should be fired (ivltests/vhdl_concurrent_assert.vhd:32) diff --git a/ivtest/gold/vhdl_image_attr.gold b/ivtest/gold/vhdl_image_attr.gold new file mode 100644 index 000000000..a53fb9f3b --- /dev/null +++ b/ivtest/gold/vhdl_image_attr.gold @@ -0,0 +1,4 @@ +** Note: integer'image test: 10 (ivltests/vhdl_image_attr.vhd:38) +** Note: real'image test: 12.340000 (ivltests/vhdl_image_attr.vhd:39) +** Note: character'image test: 'o' (ivltests/vhdl_image_attr.vhd:40) +** Note: time'image test: 10 ns (ivltests/vhdl_image_attr.vhd:41) diff --git a/ivtest/gold/vhdl_lfcr.gold b/ivtest/gold/vhdl_lfcr.gold new file mode 100644 index 000000000..1dce57476 --- /dev/null +++ b/ivtest/gold/vhdl_lfcr.gold @@ -0,0 +1,2 @@ +** Note: first line +after LFrafter CR (ivltests/vhdl_lfcr.vhd:32) diff --git a/ivtest/gold/vhdl_mux2.gold b/ivtest/gold/vhdl_mux2.gold new file mode 100644 index 000000000..16db301bb --- /dev/null +++ b/ivtest/gold/vhdl_mux2.gold @@ -0,0 +1,3 @@ +1 +0 +1 diff --git a/ivtest/gold/vhdl_now.gold b/ivtest/gold/vhdl_now.gold new file mode 100644 index 000000000..6984ec34f --- /dev/null +++ b/ivtest/gold/vhdl_now.gold @@ -0,0 +1,3 @@ +** Note: reporting sim time: 5 (ivltests/vhdl_now.vhd:34) +** Note: reporting sim time: 15 (ivltests/vhdl_now.vhd:34) +** Note: reporting sim time: 25 (ivltests/vhdl_now.vhd:34) diff --git a/ivtest/gold/vhdl_procedure.gold b/ivtest/gold/vhdl_procedure.gold new file mode 100644 index 000000000..d9243253b --- /dev/null +++ b/ivtest/gold/vhdl_procedure.gold @@ -0,0 +1,7 @@ +** Note: before rising_edge (ivltests/vhdl_procedure.vhd:38) +** Note: after rising_edge (ivltests/vhdl_procedure.vhd:44) +** Note: before rising_edge (ivltests/vhdl_procedure.vhd:38) +** Note: after rising_edge (ivltests/vhdl_procedure.vhd:44) +** Note: before rising_edge (ivltests/vhdl_procedure.vhd:38) +** Note: Procedure executed (ivltests/vhdl_procedure.vhd:33) +** Note: after rising_edge (ivltests/vhdl_procedure.vhd:44) diff --git a/ivtest/gold/vhdl_report.gold b/ivtest/gold/vhdl_report.gold new file mode 100644 index 000000000..296317087 --- /dev/null +++ b/ivtest/gold/vhdl_report.gold @@ -0,0 +1,11 @@ +** Error: procedure 1 (ivltests/vhdl_report_pkg.vhd:35) +** Error: Assertion violation. (ivltests/vhdl_report_pkg.vhd:38) +** Note: procedure 2 (ivltests/vhdl_report_pkg.vhd:40) +** Note: Assertion violation. (ivltests/vhdl_report_pkg.vhd:43) +** Warning: procedure 3 (ivltests/vhdl_report_pkg.vhd:46) +** Note: normal report (ivltests/vhdl_report.vhd:36) +** Error: report with severity (ivltests/vhdl_report.vhd:40) +** Error: Assertion violation. (ivltests/vhdl_report.vhd:44) +** Note: assert with report (ivltests/vhdl_report.vhd:47) +** Note: Assertion violation. (ivltests/vhdl_report.vhd:52) +** Failure: assert with report & severity (ivltests/vhdl_report.vhd:56) diff --git a/ivtest/gold/vhdl_string.gold b/ivtest/gold/vhdl_string.gold new file mode 100644 index 000000000..d860555d9 --- /dev/null +++ b/ivtest/gold/vhdl_string.gold @@ -0,0 +1,7 @@ +** Note: (ivltests/vhdl_string.vhd:34) +** Note: " (ivltests/vhdl_string.vhd:35) +** Note: test (ivltests/vhdl_string.vhd:36) +** Note: VHDL (ivltests/vhdl_string.vhd:37) +** Note: brackets test (ivltests/vhdl_string.vhd:39) +** Note: multiple brackets test (ivltests/vhdl_string.vhd:40) +** Note: "quotation " marks " test" (ivltests/vhdl_string.vhd:41) diff --git a/ivtest/gold/vhdl_test3.gold b/ivtest/gold/vhdl_test3.gold new file mode 100644 index 000000000..9767a2615 --- /dev/null +++ b/ivtest/gold/vhdl_test3.gold @@ -0,0 +1,17 @@ +input = 0000, output=0000000000000001 +input = 0001, output=0000000000000010 +input = 0010, output=0000000000000011 +input = 0011, output=0000000000000100 +input = 0100, output=0000000000000101 +input = 0101, output=0000000000000110 +input = 0110, output=0000000000000111 +input = 0111, output=0000000000001000 +input = 1000, output=0000000000001001 +input = 1001, output=0000000000001010 +input = 1010, output=0000000000001011 +input = 1011, output=0000000000001100 +input = 1100, output=0000000000001101 +input = 1101, output=0000000000001110 +input = 1110, output=0000000000001111 +input = 1111, output=0000000000010000 +input = 0000, output=0000000000000001 diff --git a/ivtest/gold/vhdl_time.gold b/ivtest/gold/vhdl_time.gold new file mode 100644 index 000000000..8554c758d --- /dev/null +++ b/ivtest/gold/vhdl_time.gold @@ -0,0 +1,10 @@ + 140 +a changed at 0 +a changed at 50 +a changed at 550 +a changed at 750 +a changed at 850 +a changed at 1650 +a changed at 1660 +a changed at 1680 +a changed at 1780 diff --git a/ivtest/gold/vhdl_wait.gold b/ivtest/gold/vhdl_wait.gold new file mode 100644 index 000000000..6818b0957 --- /dev/null +++ b/ivtest/gold/vhdl_wait.gold @@ -0,0 +1,3 @@ +** Note: final wait test (ivltests/vhdl_wait.vhd:33) +** Note: wait 1 completed (ivltests/vhdl_wait.vhd:39) +wait 1 acknowledged diff --git a/ivtest/gold/wait3.gold b/ivtest/gold/wait3.gold new file mode 100644 index 000000000..595ae4f78 --- /dev/null +++ b/ivtest/gold/wait3.gold @@ -0,0 +1,8 @@ +starting + 0 x0 + 100 00 + 200 10 + 201 11 + 301 01 + 302 00 +timeout diff --git a/ivtest/gold/warn_opt_sys_tf-vlog95.gold b/ivtest/gold/warn_opt_sys_tf-vlog95.gold new file mode 100644 index 000000000..ec2040f03 --- /dev/null +++ b/ivtest/gold/warn_opt_sys_tf-vlog95.gold @@ -0,0 +1,16 @@ +SORRY: vlog95.v:14: $getpattern() is not available in Icarus Verilog. +SORRY: vlog95.v:15: $input() is not available in Icarus Verilog. +SORRY: vlog95.v:16: $key() is not available in Icarus Verilog. +SORRY: vlog95.v:17: $nokey() is not available in Icarus Verilog. +SORRY: vlog95.v:18: $list() is not available in Icarus Verilog. +SORRY: vlog95.v:19: $log() is not available in Icarus Verilog. +SORRY: vlog95.v:20: $nolog() is not available in Icarus Verilog. +SORRY: vlog95.v:21: $save() is not available in Icarus Verilog. +SORRY: vlog95.v:22: $restart() is not available in Icarus Verilog. +SORRY: vlog95.v:23: $incsave() is not available in Icarus Verilog. +SORRY: vlog95.v:24: $scale() is not available in Icarus Verilog. +SORRY: vlog95.v:25: $scope() is not available in Icarus Verilog. +SORRY: vlog95.v:26: $showscopes() is not available in Icarus Verilog. +SORRY: vlog95.v:27: $showvars() is not available in Icarus Verilog. +SORRY: vlog95.v:28: $sreadmemb() is not available in Icarus Verilog. +SORRY: vlog95.v:29: $sreadmemh() is not available in Icarus Verilog. diff --git a/ivtest/gold/warn_opt_sys_tf.gold b/ivtest/gold/warn_opt_sys_tf.gold new file mode 100644 index 000000000..f76afe9c7 --- /dev/null +++ b/ivtest/gold/warn_opt_sys_tf.gold @@ -0,0 +1,16 @@ +SORRY: ./ivltests/warn_opt_sys_tf.v:7: $getpattern() is not available in Icarus Verilog. +SORRY: ./ivltests/warn_opt_sys_tf.v:8: $input() is not available in Icarus Verilog. +SORRY: ./ivltests/warn_opt_sys_tf.v:9: $key() is not available in Icarus Verilog. +SORRY: ./ivltests/warn_opt_sys_tf.v:10: $nokey() is not available in Icarus Verilog. +SORRY: ./ivltests/warn_opt_sys_tf.v:11: $list() is not available in Icarus Verilog. +SORRY: ./ivltests/warn_opt_sys_tf.v:12: $log() is not available in Icarus Verilog. +SORRY: ./ivltests/warn_opt_sys_tf.v:13: $nolog() is not available in Icarus Verilog. +SORRY: ./ivltests/warn_opt_sys_tf.v:14: $save() is not available in Icarus Verilog. +SORRY: ./ivltests/warn_opt_sys_tf.v:15: $restart() is not available in Icarus Verilog. +SORRY: ./ivltests/warn_opt_sys_tf.v:16: $incsave() is not available in Icarus Verilog. +SORRY: ./ivltests/warn_opt_sys_tf.v:17: $scale() is not available in Icarus Verilog. +SORRY: ./ivltests/warn_opt_sys_tf.v:18: $scope() is not available in Icarus Verilog. +SORRY: ./ivltests/warn_opt_sys_tf.v:19: $showscopes() is not available in Icarus Verilog. +SORRY: ./ivltests/warn_opt_sys_tf.v:20: $showvars() is not available in Icarus Verilog. +SORRY: ./ivltests/warn_opt_sys_tf.v:21: $sreadmemb() is not available in Icarus Verilog. +SORRY: ./ivltests/warn_opt_sys_tf.v:22: $sreadmemh() is not available in Icarus Verilog. diff --git a/ivtest/gold/wild_cmp_err.gold b/ivtest/gold/wild_cmp_err.gold new file mode 100644 index 000000000..1c308e695 --- /dev/null +++ b/ivtest/gold/wild_cmp_err.gold @@ -0,0 +1,5 @@ +./ivltests/wild_cmp_err.v:2: error: ==? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err.v:3: error: ==? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err.v:4: error: !=? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err.v:5: error: !=? operator may only have INTEGRAL operands. +4 error(s) during elaboration. diff --git a/ivtest/gold/wild_cmp_err2.gold b/ivtest/gold/wild_cmp_err2.gold new file mode 100644 index 000000000..600d31dbb --- /dev/null +++ b/ivtest/gold/wild_cmp_err2.gold @@ -0,0 +1,25 @@ +./ivltests/wild_cmp_err2.v:9: error: ==? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err2.v:9: error: Unable to elaborate r-value: (rl)w(rv) +./ivltests/wild_cmp_err2.v:10: error: ==? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err2.v:10: error: Unable to elaborate r-value: (lv)w(rl) +./ivltests/wild_cmp_err2.v:11: error: !=? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err2.v:11: error: Unable to elaborate r-value: (rl)W(rv) +./ivltests/wild_cmp_err2.v:12: error: !=? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err2.v:12: error: Unable to elaborate r-value: (lv)W(rl) +./ivltests/wild_cmp_err2.v:13: error: ==? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err2.v:13: error: Unable to elaborate r-value: (st)w(rv) +./ivltests/wild_cmp_err2.v:14: error: ==? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err2.v:14: error: Unable to elaborate r-value: (lv)w(st) +./ivltests/wild_cmp_err2.v:15: error: !=? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err2.v:15: error: Unable to elaborate r-value: (st)W(rv) +./ivltests/wild_cmp_err2.v:16: error: !=? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err2.v:16: error: Unable to elaborate r-value: (lv)W(st) +./ivltests/wild_cmp_err2.v:19: error: ==? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err2.v:20: error: ==? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err2.v:21: error: !=? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err2.v:22: error: !=? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err2.v:23: error: ==? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err2.v:24: error: ==? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err2.v:25: error: !=? operator may only have INTEGRAL operands. +./ivltests/wild_cmp_err2.v:26: error: !=? operator may only have INTEGRAL operands. +24 error(s) during elaboration. diff --git a/ivtest/gold/wiresl2.gold b/ivtest/gold/wiresl2.gold new file mode 100644 index 000000000..0823a50d3 --- /dev/null +++ b/ivtest/gold/wiresl2.gold @@ -0,0 +1,8 @@ +out=01 +out=02 +out=04 +out=08 +out=10 +out=20 +out=40 +out=80 diff --git a/ivtest/gold/writemem-error-vlog95.gold b/ivtest/gold/writemem-error-vlog95.gold new file mode 100644 index 000000000..880a10eb5 --- /dev/null +++ b/ivtest/gold/writemem-error-vlog95.gold @@ -0,0 +1,20 @@ +WARNING: vlog95.v:22: $writememb's file name argument (vpiReg) is not a valid string. +WARNING: vlog95.v:23: $writememb's file name argument (vpiIntegerVar) is not a valid string. +WARNING: vlog95.v:30: $writememb's file name argument contains non-printable characters. + "work/writemem.tx\002" +WARNING: vlog95.v:33: $writememb's third argument (start address) is a real value. +WARNING: vlog95.v:38: $writememb's fourth argument (finish address) is a real value. +ERROR: vlog95.v:42: $writememb: Start address -1 is out of bounds for memory 'top.check[0:7]'! +ERROR: vlog95.v:46: $writememb: Start address 7 is out of bounds for memory 'top.array2[8:15]'! +ERROR: vlog95.v:50: $writememb: Finish address 8 is out of bounds for memory 'top.check[0:7]'! +ERROR: vlog95.v:54: $writememb: Finish address 16 is out of bounds for memory 'top.array2[8:15]'! +WARNING: vlog95.v:63: $writememh's file name argument (vpiReg) is not a valid string. +WARNING: vlog95.v:64: $writememh's file name argument (vpiIntegerVar) is not a valid string. +WARNING: vlog95.v:71: $writememh's file name argument contains non-printable characters. + "work/writemem.tx\002" +WARNING: vlog95.v:74: $writememh's third argument (start address) is a real value. +WARNING: vlog95.v:79: $writememh's fourth argument (finish address) is a real value. +ERROR: vlog95.v:83: $writememh: Start address -1 is out of bounds for memory 'top.check[0:7]'! +ERROR: vlog95.v:87: $writememh: Start address 7 is out of bounds for memory 'top.array2[8:15]'! +ERROR: vlog95.v:91: $writememh: Finish address 8 is out of bounds for memory 'top.check[0:7]'! +ERROR: vlog95.v:95: $writememh: Finish address 16 is out of bounds for memory 'top.array2[8:15]'! diff --git a/ivtest/gold/writemem-error.gold b/ivtest/gold/writemem-error.gold new file mode 100644 index 000000000..f4d10a7cc --- /dev/null +++ b/ivtest/gold/writemem-error.gold @@ -0,0 +1,20 @@ +WARNING: ./ivltests/writemem-error.v:15: $writememb's file name argument (vpiReg) is not a valid string. +WARNING: ./ivltests/writemem-error.v:16: $writememb's file name argument (vpiIntegerVar) is not a valid string. +WARNING: ./ivltests/writemem-error.v:32: $writememb's file name argument contains non-printable characters. + "work/writemem.tx\002" +WARNING: ./ivltests/writemem-error.v:37: $writememb's third argument (start address) is a real value. +WARNING: ./ivltests/writemem-error.v:49: $writememb's fourth argument (finish address) is a real value. +ERROR: ./ivltests/writemem-error.v:60: $writememb: Start address -1 is out of bounds for memory 'top.check[0:7]'! +ERROR: ./ivltests/writemem-error.v:70: $writememb: Start address 7 is out of bounds for memory 'top.array2[8:15]'! +ERROR: ./ivltests/writemem-error.v:80: $writememb: Finish address 8 is out of bounds for memory 'top.check[0:7]'! +ERROR: ./ivltests/writemem-error.v:90: $writememb: Finish address 16 is out of bounds for memory 'top.array2[8:15]'! +WARNING: ./ivltests/writemem-error.v:117: $writememh's file name argument (vpiReg) is not a valid string. +WARNING: ./ivltests/writemem-error.v:118: $writememh's file name argument (vpiIntegerVar) is not a valid string. +WARNING: ./ivltests/writemem-error.v:134: $writememh's file name argument contains non-printable characters. + "work/writemem.tx\002" +WARNING: ./ivltests/writemem-error.v:139: $writememh's third argument (start address) is a real value. +WARNING: ./ivltests/writemem-error.v:151: $writememh's fourth argument (finish address) is a real value. +ERROR: ./ivltests/writemem-error.v:162: $writememh: Start address -1 is out of bounds for memory 'top.check[0:7]'! +ERROR: ./ivltests/writemem-error.v:172: $writememh: Start address 7 is out of bounds for memory 'top.array2[8:15]'! +ERROR: ./ivltests/writemem-error.v:182: $writememh: Finish address 8 is out of bounds for memory 'top.check[0:7]'! +ERROR: ./ivltests/writemem-error.v:192: $writememh: Finish address 16 is out of bounds for memory 'top.array2[8:15]'! diff --git a/ivtest/gold/writemem-invalid-vlog95.gold b/ivtest/gold/writemem-invalid-vlog95.gold new file mode 100644 index 000000000..880336f59 --- /dev/null +++ b/ivtest/gold/writemem-invalid-vlog95.gold @@ -0,0 +1,18 @@ +ERROR: vlog95.v:14: $writememb requires two arguments. +ERROR: vlog95.v:15: $writememb's first argument must be a file name (string). +ERROR: vlog95.v:15: $writememb requires a second (memory) argument. +ERROR: vlog95.v:16: $writememb requires a second (memory) argument. +ERROR: vlog95.v:17: $writememb's second argument must be a memory. +ERROR: vlog95.v:18: $writememb's third argument must be a start address (numeric). +ERROR: vlog95.v:19: $writememb's fourth argument must be a finish address (numeric). +ERROR: vlog95.v:20: $writememb takes at most four arguments. + Found 1 extra argument. +ERROR: vlog95.v:21: $writememh requires two arguments. +ERROR: vlog95.v:22: $writememh's first argument must be a file name (string). +ERROR: vlog95.v:22: $writememh requires a second (memory) argument. +ERROR: vlog95.v:23: $writememh requires a second (memory) argument. +ERROR: vlog95.v:24: $writememh's second argument must be a memory. +ERROR: vlog95.v:25: $writememh's third argument must be a start address (numeric). +ERROR: vlog95.v:26: $writememh's fourth argument must be a finish address (numeric). +ERROR: vlog95.v:27: $writememh takes at most four arguments. + Found 1 extra argument. diff --git a/ivtest/gold/writemem-invalid.gold b/ivtest/gold/writemem-invalid.gold new file mode 100644 index 000000000..5c8179d78 --- /dev/null +++ b/ivtest/gold/writemem-invalid.gold @@ -0,0 +1,18 @@ +ERROR: ./ivltests/writemem-invalid.v:5: $writememb requires two arguments. +ERROR: ./ivltests/writemem-invalid.v:6: $writememb's first argument must be a file name (string). +ERROR: ./ivltests/writemem-invalid.v:6: $writememb requires a second (memory) argument. +ERROR: ./ivltests/writemem-invalid.v:7: $writememb requires a second (memory) argument. +ERROR: ./ivltests/writemem-invalid.v:8: $writememb's second argument must be a memory. +ERROR: ./ivltests/writemem-invalid.v:9: $writememb's third argument must be a start address (numeric). +ERROR: ./ivltests/writemem-invalid.v:10: $writememb's fourth argument must be a finish address (numeric). +ERROR: ./ivltests/writemem-invalid.v:11: $writememb takes at most four arguments. + Found 1 extra argument. +ERROR: ./ivltests/writemem-invalid.v:13: $writememh requires two arguments. +ERROR: ./ivltests/writemem-invalid.v:14: $writememh's first argument must be a file name (string). +ERROR: ./ivltests/writemem-invalid.v:14: $writememh requires a second (memory) argument. +ERROR: ./ivltests/writemem-invalid.v:15: $writememh requires a second (memory) argument. +ERROR: ./ivltests/writemem-invalid.v:16: $writememh's second argument must be a memory. +ERROR: ./ivltests/writemem-invalid.v:17: $writememh's third argument must be a start address (numeric). +ERROR: ./ivltests/writemem-invalid.v:18: $writememh's fourth argument must be a finish address (numeric). +ERROR: ./ivltests/writemem-invalid.v:19: $writememh takes at most four arguments. + Found 1 extra argument. diff --git a/ivtest/ivltests/abstime.v b/ivtest/ivltests/abstime.v new file mode 100644 index 000000000..76dd42fc4 --- /dev/null +++ b/ivtest/ivltests/abstime.v @@ -0,0 +1,43 @@ +`timescale 1ns/10ps + +module top; + reg pass; + real result; + + initial begin + pass = 1'b1; + + result = $abstime; + if (result != 0.0) begin + $display("FAILED at time 0, expected 0.0, got %g", result); + pass = 1'b0; + end + + #10; + result = $abstime; + if ($abs(result-10e-9) > result*1e-9) begin + $display("FAILED at time 10ns, expected 1e-8, got %g", result); + pass = 1'b0; + end + + #999990; + result = $abstime; + if ($abs(result-0.001) > result*1e-9) begin + $display("FAILED at time 1ms, expected 0.001, got %g", result); + pass = 1'b0; + end + +`ifdef __ICARUS_UNSIZED__ + #9999000000; +`else + #9999000000.0; +`endif + result = $abstime; + if ($abs(result-10.0) > result*1e-9) begin + $display("FAILED at time 10s, expected 10.0, got %g", result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/addsr.v b/ivtest/ivltests/addsr.v new file mode 100644 index 000000000..f6fc96433 --- /dev/null +++ b/ivtest/ivltests/addsr.v @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test caught a problem with the addition with different size + * operands was an operand of the shift. + */ +module main; + + reg [3:0] a; + reg [4:0] result, b; + + initial begin + a = 5; + b = 6; + result = (a + b) >> 1; + if (result !== 5) begin + $display("FAILED: result === %b", result); + $finish; + end + + $display("PASSED"); + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/addwide.v b/ivtest/ivltests/addwide.v new file mode 100644 index 000000000..524b0bcc0 --- /dev/null +++ b/ivtest/ivltests/addwide.v @@ -0,0 +1,53 @@ +// (c) Alex.Perry@qm.com - 2002, Quantum Magnetics Inc, San Diego CA +// This source file is licensed under the GNU public license version 2.0 +// All other rights reserved. + +// NOTE: This test catches addition of wide (>16 bits) constants +// to wide vectors. -- Steve Williams +module source ( C, h ); +output [ 0:0] C; +output [11:0] h; +reg [ 0:0] C; +reg [11:0] h; +reg [21:0] l; + +parameter kh = 3; +parameter kl = 21'd364066; +parameter wl = 21'h100000; + +initial #5 + begin + C <= 0; + l <= 0; + h <= 0; + end +always #10 C = ~C; +always @(posedge C) +begin if ( l >= wl ) + begin l <= l + kl - wl; + h <= h + kh + 1; + end else + begin l <= l + kl; + h <= h + kh; + end +end + +endmodule + + +module bench; +wire [ 0:0] clock; +wire [11:0] h; +source dut ( .C(clock), .h(h) ); +initial #85 + begin + if ( h == 13 ) begin + $display ( "%7d", h ); + $display ("PASSED"); + end else begin + $display ( "%7d = FAIL", h ); + end + $finish; + end + +endmodule diff --git a/ivtest/ivltests/always3.1.10A.v b/ivtest/ivltests/always3.1.10A.v new file mode 100644 index 000000000..44b17db61 --- /dev/null +++ b/ivtest/ivltests/always3.1.10A.v @@ -0,0 +1,43 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always event_trigger ; + + +module main ; + + +event one_event ; + +always @(one_event) + begin + # 1; + $display("saw event"); + end + +initial + begin + #1 ; + #1 ; + #1 ; + $finish ; + end + +always -> one_event ; + +endmodule diff --git a/ivtest/ivltests/always3.1.11A.v b/ivtest/ivltests/always3.1.11A.v new file mode 100644 index 000000000..b029ea5d9 --- /dev/null +++ b/ivtest/ivltests/always3.1.11A.v @@ -0,0 +1,52 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always begin some_statements ; end + + + +module main ; + +reg [3:0] value1,value2,value3; + +always begin + #5 ; + value1 = 1; + end + +initial + begin + value1 = 0; + value2 = 0; + if(value1 != 0) + begin + $display("FAILED - 3.1.11A always begin statement end"); + value2 = 1; + end + #6; + if(value1 != 1) + begin + $display("FAILED - 3.1.11A always begin statement end"); + value2 = 1; + end + if(value2 == 0) + $display("PASSED"); + $finish ; + end + +endmodule diff --git a/ivtest/ivltests/always3.1.11B.v b/ivtest/ivltests/always3.1.11B.v new file mode 100644 index 000000000..d5f894d4e --- /dev/null +++ b/ivtest/ivltests/always3.1.11B.v @@ -0,0 +1,54 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always begin : id block_defines some_statements ; end + + + +module main ; + +reg [3:0] value1,value2,value3; + +always begin : block_id + reg [3:0] value4 ; + value4 = 1; + #5 ; + value1 = value4; + end + +initial + begin + value1 = 0; + value2 = 0; + if(value1 != 0) + begin + $display("FAILED - 3.1.11B always begin : id defines statement end"); + value2 = 1; + end + #6; + if(value1 != 1) + begin + $display("FAILED - 3.1.11B always begin : id defines statement end"); + value2 = 1; + end + if(value2 == 0) + $display("PASSED"); + $finish ; + end + +endmodule diff --git a/ivtest/ivltests/always3.1.12A.v b/ivtest/ivltests/always3.1.12A.v new file mode 100644 index 000000000..ee6dbec42 --- /dev/null +++ b/ivtest/ivltests/always3.1.12A.v @@ -0,0 +1,63 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always fork parallel_statements join + + + +module main ; + +reg [3:0] value1,value2,value3; + +always fork + #5 value1 = 1 ; + #8 value1 = 2; + join + +initial + begin + value1 = 0; + value2 = 0; + #4 ; + if(value1 != 0) + begin + $display("FAILED - 3.1.12A always fork statements join (0)"); + value2 = 1; + end + #2 ; + if(value1 != 1) + begin + $display("FAILED - 3.1.12A always fork statements join (1)"); + value2 = 1; + end + #3 ; + if(value1 != 2) + begin + $display("FAILED - 3.1.12A always fork statements join (2)"); + value2 = 1; + end + #5 ; + if(value1 != 1) + begin + $display("FAILED - 3.1.12A always fork statements join (3)"); + value2 = 1; + end + if(value2 == 0) $display("PASSED"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/always3.1.12B.v b/ivtest/ivltests/always3.1.12B.v new file mode 100644 index 000000000..811bd7cfa --- /dev/null +++ b/ivtest/ivltests/always3.1.12B.v @@ -0,0 +1,63 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always fork : id parallel_statements join + + + +module main ; + +reg [3:0] value1,value2,value3; + +always fork : fork_id + #5 value1 = 1 ; + #10 value1 = 2; + join + +initial + begin + value1 = 0; + value2 = 0; + #4 ; + if(value1 != 0) + begin + $display("FAILED - 3.1.12B always fork : id statements join (0)"); + value2 = 1; + end + #2 ; + if(value1 != 1) + begin + $display("FAILED - 3.1.12B always fork : id statements join (1)"); + value2 = 1; + end + #5 ; + if(value1 != 2) + begin + $display("FAILED - 3.1.12B always fork : id statements join (2)"); + value2 = 1; + end + #5 ; + if(value1 != 1) + begin + $display("FAILED - 3.1.12B always fork : id statements join (3)"); + value2 = 1; + end + if(value2 == 0) $display("PASSED"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/always3.1.12C.v b/ivtest/ivltests/always3.1.12C.v new file mode 100644 index 000000000..cf632a438 --- /dev/null +++ b/ivtest/ivltests/always3.1.12C.v @@ -0,0 +1,67 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always fork : id block_decl parallel_statements join + + + +module main ; + +reg [3:0] value1,value2,value3; + +always fork : fork_id + reg [3:0] value4 ; + #5 begin + value4 = 0; + value1 = value4 + 1 ; + end + #10 value1 = value4 + 2; + join + +initial + begin + value1 = 0; + value2 = 0; + #4 ; + if(value1 != 0) + begin + $display("FAILED - 3.1.12C always fork : id block_decl statements join (0)"); + value2 = 1; + end + #2 ; + if(value1 != 1) + begin + $display("FAILED - 3.1.12C always fork : id block_decl statements join (1)"); + value2 = 1; + end + #5 ; + if(value1 != 2) + begin + $display("FAILED - 3.1.12C always fork : id block_decl statements join (2)"); + value2 = 1; + end + #5 ; + if(value1 != 1) + begin + $display("FAILED - 3.1.12C always fork : id block_decl statements join (3)"); + value2 = 1; + end + if(value2 == 0) $display("PASSED"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/always3.1.1A.v b/ivtest/ivltests/always3.1.1A.v new file mode 100644 index 000000000..0123776e8 --- /dev/null +++ b/ivtest/ivltests/always3.1.1A.v @@ -0,0 +1,42 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always 3.1.1A always reg_lvalue = constant ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +always begin + #0; #0; #0; + end + +always value1 = 4'h5 ; + +initial + if(value1 != 4'h5) + $display("FAILED - 3.1.1A always reg_lvalue = constant\n"); + else + begin + $display("PASSED\n"); + $finish; + end + + +endmodule diff --git a/ivtest/ivltests/always3.1.1B.v b/ivtest/ivltests/always3.1.1B.v new file mode 100644 index 000000000..985be481e --- /dev/null +++ b/ivtest/ivltests/always3.1.1B.v @@ -0,0 +1,37 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always 3.1.1B always reg_lvalue = boolean_expression ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + if(value1 != 4'b1) + $display("FAILED - 3.1.1B always reg_lvalue = boolean_expression\n"); + else + begin + $display("PASSED\n"); + $finish; + end + +always value1 = 1'b1 && 1'b1 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.1C.v b/ivtest/ivltests/always3.1.1C.v new file mode 100644 index 000000000..a7efa3c6c --- /dev/null +++ b/ivtest/ivltests/always3.1.1C.v @@ -0,0 +1,42 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate 3.1.1C always reg_lvalue = # delay_value constant ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + begin + if(value1 !== 4'hx) + $display("FAILED - always reg_lvalue = # delay_value constant"); + #15 ; + if(value1 !== 4'h5) + $display("FAILED - always reg_lvalue = # delay_value constant"); + else + begin + $display("PASSED\n"); + $finish ; + end + end + +always value1 = # 10 4'h5 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.1D.v b/ivtest/ivltests/always3.1.1D.v new file mode 100644 index 000000000..a3bdf4e9a --- /dev/null +++ b/ivtest/ivltests/always3.1.1D.v @@ -0,0 +1,42 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue = # delay_value boolean_expression +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + begin + if(value1 !== 4'hx) + $display("FAILED - always reg_lvalue = # delay_value boolean_expression\n"); + #15 ; + if(value1 != 4'h5) + $display("FAILED - always reg_lvalue = # delay_value boolean_expression\n"); + else + begin + $display("PASSED\n"); + $finish ; + end + end + +always value1 = # 10 4'h5 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.1E.v b/ivtest/ivltests/always3.1.1E.v new file mode 100644 index 000000000..4feff6f07 --- /dev/null +++ b/ivtest/ivltests/always3.1.1E.v @@ -0,0 +1,43 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue = # (mintypmax_expression) constant ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + begin + # 3; /* Wait till here to verify didn't see 2ns delay! */ + if(value1 !== 4'hx) + $display("FAILED - always reg_lvalue = # (mintypmax_expression) constant \n"); + #12 ; + if(value1 != 4'h5) + $display("FAILED - always reg_lvalue = # (mintypmax_expression) constant \n"); + else + begin + $display("PASSED\n"); + $finish ; + end + end + +always value1 = # (2:10:17) 4'h5 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.1F.v b/ivtest/ivltests/always3.1.1F.v new file mode 100644 index 000000000..159040c19 --- /dev/null +++ b/ivtest/ivltests/always3.1.1F.v @@ -0,0 +1,43 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue = # (mintypmax_expression) boolean_exp ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + begin + # 3; /* Wait till here to verify didn't see 2ns delay! */ + if(value1 !== 4'hx) + $display("FAILED - always reg_lvalue = # (mintypmax_expression) boolean_exp \n"); + #12 ; + if(value1 != 4'b1) + $display("FAILED - always reg_lvalue = # (mintypmax_expression) boolean_exp \n"); + else + begin + $display("PASSED\n"); + $finish ; + end + end + +always value1 = # (2:10:17) 1'b1 && 1'b1 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.1G.v b/ivtest/ivltests/always3.1.1G.v new file mode 100644 index 000000000..6c47ece23 --- /dev/null +++ b/ivtest/ivltests/always3.1.1G.v @@ -0,0 +1,49 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue = @ event_identifier constant +// D: There is a dependency here between this and event keyword and -> + +module main ; + +reg [3:0] value1 ; +event event_ident ; + +initial +begin + # 5 -> event_ident ; +end + +initial + begin + if(value1 !== 4'bxxxx) + $display("FAILED - always reg_lvalue = @ event_identifier constant\n"); + #10 ; + if(value1 != 4'h5) + $display("FAILED - always reg_lvalue = @ event_identifier constant\n"); + else + begin + $display("PASSED\n"); + $finish ; + end + end + +always value1 = @ event_ident 4'h5; + + +endmodule diff --git a/ivtest/ivltests/always3.1.1H.v b/ivtest/ivltests/always3.1.1H.v new file mode 100644 index 000000000..627438d29 --- /dev/null +++ b/ivtest/ivltests/always3.1.1H.v @@ -0,0 +1,49 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue = @ event_identifier boolean_expression +// D: There is a dependency here between this and event keyword and -> + +module main ; + +reg [3:0] value1 ; +event event_ident ; + +initial +begin + # 5 -> event_ident ; +end + +initial + begin + if(value1 !== 4'bxxxx) + $display("FAILED - always reg_lvalue = @ event_identifier boolean_expression\n"); + #10 ; + if(value1 != 4'b1) + $display("FAILED - always reg_lvalue = @ event_identifier boolean_expression\n"); + else + begin + $display("PASSED\n"); + $finish ; + end + end + +always value1 = @ event_ident 1'b1 && 1'b1 ; + + +endmodule diff --git a/ivtest/ivltests/always3.1.1I.v b/ivtest/ivltests/always3.1.1I.v new file mode 100644 index 000000000..cf15f0d2c --- /dev/null +++ b/ivtest/ivltests/always3.1.1I.v @@ -0,0 +1,59 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue = @ (event_expression) constant +// + +module main ; + +reg [3:0] value1 ; +reg event_var ; + +initial +begin + # 2 ; + value1 = 5'h 0 ; + # 3 ; + event_var = 1'b0 ; + # 2 ; + value1 = 5'h 0 ; + # 3 ; + event_var = 1'b1 ; + #5 ; +end + +initial + begin // Should be xxxx at initial time + if(value1 !== 4'bxxxx) + $display("FAILED - always reg_lvalue = @ (event_expression) constant \n"); + # 6 ; + if(value1 != 4'h5) // Time 5 should see a change of 0 to 1 + $display("FAILED - always reg_lvalue = @ event_identifier boolean_expression\n"); + # 5 ; + if(value1 != 4'h5) // Time 5 should see a change of 0 to 1 + $display("FAILED - always reg_lvalue = @ event_identifier boolean_expression\n"); + begin + $display("PASSED\n"); + $finish ; + end + end + +always value1 = @ (event_var) 4'h5 ; + + +endmodule diff --git a/ivtest/ivltests/always3.1.1J.v b/ivtest/ivltests/always3.1.1J.v new file mode 100644 index 000000000..d15f16b7d --- /dev/null +++ b/ivtest/ivltests/always3.1.1J.v @@ -0,0 +1,59 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue = @ (event_expression) boolean_expr +// + +module main ; + +reg [3:0] value1 ; +reg event_var ; + +initial +begin + # 2 ; + value1 = 5'h 0 ; + # 3 ; + event_var = 1'b0 ; + # 2 ; + value1 = 5'h 0 ; + # 3 ; + event_var = 1'b1 ; + #5 ; +end + +initial + begin // Should be xxxx at initial time + if(value1 !== 4'bxxxx) + $display("FAILED - always reg_lvalue = @ (event_expression) boolean_expr\n"); + # 6 ; + if(value1 != 4'h1) // Time 5 should see a change of 0 to 1 + $display("FAILED - always reg_lvalue = @ (event_expression) boolean_expr\n"); + # 5 ; + if(value1 != 4'h1) // Time 5 should see a change of 0 to 1 + $display("FAILED - always reg_lvalue = @ (event_expression) boolean_expr\n"); + begin + $display("PASSED\n"); + $finish ; + end + end + +always value1 = @ (event_var) 1'b1 && 1'b1 ; + + +endmodule diff --git a/ivtest/ivltests/always3.1.1K.v b/ivtest/ivltests/always3.1.1K.v new file mode 100644 index 000000000..4f4f48144 --- /dev/null +++ b/ivtest/ivltests/always3.1.1K.v @@ -0,0 +1,49 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue = @ event_identifier constant +// D: There is a dependency here between this and event keyword and -> + +module main ; + +reg [3:0] value1 ; +event event_ident ; + +initial +begin + # 5 -> event_ident ; +end + +initial + begin + if(value1 !== 4'bxxxx) + $display("FAILED - always reg_lvalue = @ event_identifier constant\n"); + #10 ; + if(value1 != 4'h5) + $display("FAILED - always reg_lvalue = @ event_identifier constant\n"); + else + begin + $display("PASSED\n"); + $finish ; + end + end + +always value1 = repeat ( 5 ) @ event_ident 4'h5 ; + + +endmodule diff --git a/ivtest/ivltests/always3.1.2A.v b/ivtest/ivltests/always3.1.2A.v new file mode 100644 index 000000000..474e1371d --- /dev/null +++ b/ivtest/ivltests/always3.1.2A.v @@ -0,0 +1,37 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always 3.1.2A always reg_lvalue <= constant ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + if(value1 != 4'h5) + $display("FAILED - 3.1.2A always reg_lvalue = constant\n"); + else + begin + $display("PASSED\n"); + $finish; + end + +always value1 <= 4'h5 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.2B.v b/ivtest/ivltests/always3.1.2B.v new file mode 100644 index 000000000..2fbf60f3a --- /dev/null +++ b/ivtest/ivltests/always3.1.2B.v @@ -0,0 +1,37 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always 3.1.2B always reg_lvalue <= boolean_expression ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + if(value1 != 4'b1) + $display("FAILED - 3.1.2B always reg_lvalue = boolean_expression\n"); + else + begin + $display("PASSED\n"); + $finish; + end + +always value1 <= 1'b1 && 1'b1 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.2C.v b/ivtest/ivltests/always3.1.2C.v new file mode 100644 index 000000000..bde9837a9 --- /dev/null +++ b/ivtest/ivltests/always3.1.2C.v @@ -0,0 +1,44 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate 3.1.2C always reg_lvalue = # delay_value constant ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + begin + # 1; + if(value1 !== 4'hx) + $display("FAILED - always reg_lvalue = # delay_value constant"); + #15 ; + if(value1 != 4'h5) + $display("FAILED - always reg_lvalue = # delay_value constant"); + else + begin + $display("PASSED\n"); + $finish ; + end + end + +always + value1 <= # 10 4'h5 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.2D.v b/ivtest/ivltests/always3.1.2D.v new file mode 100644 index 000000000..420ab1f8b --- /dev/null +++ b/ivtest/ivltests/always3.1.2D.v @@ -0,0 +1,43 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate 3.1.2D always reg_lvalue = # delay_value boolean_expr ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + begin + if(value1 !== 4'hx) + $display("FAILED - always reg_lvalue = # delay_value boolean_expr"); + #15 ; + if(value1 != 4'b1) + $display("FAILED - always reg_lvalue = # delay_value boolean_expr"); + else + begin + $display("PASSED\n"); + $finish ; + end + end + +always + value1 <= # 10 1'b1 && 1'b1 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.2E.v b/ivtest/ivltests/always3.1.2E.v new file mode 100644 index 000000000..1abda685c --- /dev/null +++ b/ivtest/ivltests/always3.1.2E.v @@ -0,0 +1,43 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate 3.1.2E always reg_lvalue <= # (mintypmax_expression) constant ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + begin + # 3; /* Wait till here to verify didn't see 2ns delay! */ + if(value1 !== 4'hx) + $display("FAILED - always reg_lvalue <= # (mintypmax_expression) constant \n"); + #12 ; + if(value1 != 4'h5) + $display("FAILED - always reg_lvalue <= # (mintypmax_expression) constant \n"); + else + begin + $display("PASSED\n"); + $finish ; + end + end + +always value1 <= # (2:10:17) 4'h5 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.2F.v b/ivtest/ivltests/always3.1.2F.v new file mode 100644 index 000000000..3c35cb380 --- /dev/null +++ b/ivtest/ivltests/always3.1.2F.v @@ -0,0 +1,43 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue <= # (mintypmax_expression) boolean_expr ; +// D: This guy doesn't stop.. + +module main ; + +reg [3:0] value1 ; + +initial + begin + # 3; /* Wait till here to verify didn't see 2ns delay! */ + if(value1 !== 4'hx) + $display("FAILED - always reg_lvalue <= # (mintypmax_expression) boolean_expr \n"); + #12 ; + if(value1 != 4'h5) + $display("FAILED - always reg_lvalue <= # (mintypmax_expression) boolean_expr \n"); + else + begin + $display("PASSED\n"); + $finish ; + end + end + +always value1 <= # (2:10:17) 1'b1 && 1'b1 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.2G.v b/ivtest/ivltests/always3.1.2G.v new file mode 100644 index 000000000..e68b4bdb1 --- /dev/null +++ b/ivtest/ivltests/always3.1.2G.v @@ -0,0 +1,49 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue <= @ event_identifier constant +// D: There is a dependency here between this and event keyword and -> + +module main ; + +reg [3:0] value1 ; +event event_ident ; + +initial +begin + # 5 -> event_ident ; +end + +initial + begin + if(value1 !== 4'bxxxx) + $display("FAILED - always reg_lvalue <= @ event_identifier constant\n"); + #10 ; + if(value1 != 4'h5) + $display("FAILED - always reg_lvalue <= @ event_identifier constant\n"); + else + begin + $display("PASSED\n"); + $finish ; + end + end + +always value1 <= @ event_ident 4'h5; + + +endmodule diff --git a/ivtest/ivltests/always3.1.2H.v b/ivtest/ivltests/always3.1.2H.v new file mode 100644 index 000000000..e597bcd8c --- /dev/null +++ b/ivtest/ivltests/always3.1.2H.v @@ -0,0 +1,49 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue <= @ event_identifier boolean_expression +// D: There is a dependency here between this and event keyword and -> + +module main ; + +reg [3:0] value1 ; +event event_ident ; + +initial +begin + # 5 -> event_ident ; +end + +initial + begin + if(value1 !== 4'bxxxx) + $display("FAILED - always reg_lvalue <= @ event_identifier boolean_expression\n"); + #10 ; + if(value1 != 4'b1) + $display("FAILED - always reg_lvalue <= @ event_identifier boolean_expression\n"); + else + begin + $display("PASSED\n"); + $finish ; + end + end + +always value1 <= @ event_ident 1'b1 && 1'b1 ; + + +endmodule diff --git a/ivtest/ivltests/always3.1.2I.v b/ivtest/ivltests/always3.1.2I.v new file mode 100644 index 000000000..daae41a4a --- /dev/null +++ b/ivtest/ivltests/always3.1.2I.v @@ -0,0 +1,59 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always reg_lvalue <= @ (event_expression) constant +// + +module main ; + +reg [3:0] value1 ; +reg event_var ; + +initial +begin + # 2 ; + value1 = 5'h 0 ; + # 3 ; + event_var = 1'b0 ; + # 2 ; + value1 = 5'h 0 ; + # 3 ; + event_var = 1'b1 ; + #5 ; +end + +initial + begin // Should be xxxx at initial time + if(value1 !== 4'bxxxx) + $display("FAILED - always reg_lvalue <= @ (event_expression) constant \n"); + # 6 ; + if(value1 != 4'h5) // Time 5 should see a change of 0 to 1 + $display("FAILED - always reg_lvalue <= @ event_identifier boolean_expression\n"); + # 5 ; + if(value1 != 4'h5) // Time 5 should see a change of 0 to 1 + $display("FAILED - always reg_lvalue <= @ event_identifier boolean_expression\n"); + begin + $display("PASSED\n"); + $finish ; + end + end + +always value1 <= @ (event_var) 4'h5 ; + + +endmodule diff --git a/ivtest/ivltests/always3.1.3A.v b/ivtest/ivltests/always3.1.3A.v new file mode 100644 index 000000000..22d2daec0 --- /dev/null +++ b/ivtest/ivltests/always3.1.3A.v @@ -0,0 +1,37 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always assign reg_lvalue = constant ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + if(value1 != 4'h5) + $display("FAILED - 3.1.3A always assign reg_lvalue = constant\n"); + else + begin + $display("PASSED\n"); + $finish; + end + +always assign value1 = 4'h5 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.3B.v b/ivtest/ivltests/always3.1.3B.v new file mode 100644 index 000000000..e61f6d72c --- /dev/null +++ b/ivtest/ivltests/always3.1.3B.v @@ -0,0 +1,37 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always assign reg_lvalue = boolean_expression ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + if(value1 != 4'h1) + $display("FAILED - 3.1.3B always assign reg_lvalue = boolean_expr\n"); + else + begin + $display("PASSED\n"); + $finish; + end + +always assign value1 = 1'b1 && 1'b1 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.3B2.v b/ivtest/ivltests/always3.1.3B2.v new file mode 100644 index 000000000..6b9f39ee3 --- /dev/null +++ b/ivtest/ivltests/always3.1.3B2.v @@ -0,0 +1,40 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always assign reg_lvalue = boolean_expression ; +// D: Note that initial has to be before always to execute! +// SJW - This is a fixed version of always3.1.3B that actually runs. +// Save the original always3.1.3B as a compile-only test as +// there are syntax differences that the compiler might as well +// have tested + +module main ; + +reg [3:0] value1 ; + +initial begin + #3 if(value1 != 4'h1) + $display("FAILED - 3.1.3B always assign reg_lvalue = boolean_expr"); + else + $display("PASSED"); + $finish; +end + +always #2 assign value1 = 1'b1 && 1'b1 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.3C.v b/ivtest/ivltests/always3.1.3C.v new file mode 100644 index 000000000..e61f6d72c --- /dev/null +++ b/ivtest/ivltests/always3.1.3C.v @@ -0,0 +1,37 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always assign reg_lvalue = boolean_expression ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + if(value1 != 4'h1) + $display("FAILED - 3.1.3B always assign reg_lvalue = boolean_expr\n"); + else + begin + $display("PASSED\n"); + $finish; + end + +always assign value1 = 1'b1 && 1'b1 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.3D.v b/ivtest/ivltests/always3.1.3D.v new file mode 100644 index 000000000..00b538ff4 --- /dev/null +++ b/ivtest/ivltests/always3.1.3D.v @@ -0,0 +1,40 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - always force reg_lvalue = constant ; +// D: No dependancy + +module main ; + +reg [3:0] value1 ; + +initial + begin + #15; + if(value1 != 4'h5) + $display("FAILED - 3.1.3D always force reg_lvalue = constant;\n"); + else + begin + $display("PASSED\n"); + $finish; + end + end + +always force value1 = 4'h5; + +endmodule diff --git a/ivtest/ivltests/always3.1.3D2.v b/ivtest/ivltests/always3.1.3D2.v new file mode 100644 index 000000000..73ab59a90 --- /dev/null +++ b/ivtest/ivltests/always3.1.3D2.v @@ -0,0 +1,40 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - always force reg_lvalue = constant ; +// D: No dependancy +// SJW - Fix to actually run. Save the existing always3.1.3D.v, as it +// has slightly different syntax that may as well be tested. + +module main ; + +reg [3:0] value1 ; + +initial + begin + #15; + if(value1 !== 4'h5) + $display("FAILED - 3.1.3D always force reg_lvalue = constant;"); + else + $display("PASSED"); + $finish; + end + +always #10 force value1 = 4'h5; + +endmodule diff --git a/ivtest/ivltests/always3.1.3E.v b/ivtest/ivltests/always3.1.3E.v new file mode 100644 index 000000000..e8bd9c8e0 --- /dev/null +++ b/ivtest/ivltests/always3.1.3E.v @@ -0,0 +1,40 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - always force reg_lvalue = boolean_expr ; +// D: This is an infinite loop - thus compile only + +module main ; + +reg [3:0] value1 ; + +initial + begin + #15; + if(value1 != 4'b1) + $display("FAILED - 3.1.3E always force reg_lvalue = boolean_expr;\n"); + else + begin + $display("PASSED\n"); + $finish; + end + end + +always force value1 = 1'b1 & 1'b1 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.3E2.v b/ivtest/ivltests/always3.1.3E2.v new file mode 100644 index 000000000..e821cb6bd --- /dev/null +++ b/ivtest/ivltests/always3.1.3E2.v @@ -0,0 +1,39 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - always force reg_lvalue = boolean_expr ; +// D: This is an infinite loop - thus compile only +// SJW - rework from akways3.1.3E to make it runnable. + +module main ; + +reg [3:0] value1 ; + +initial + begin + #15; + if(value1 !== 4'b1) + $display("FAILED - 3.1.3E always force reg_lvalue = boolean_expr;"); + else + $display("PASSED"); + $finish; + end + +always #10 force value1 = 1'b1 & 1'b1 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.3F.v b/ivtest/ivltests/always3.1.3F.v new file mode 100644 index 000000000..37fbad008 --- /dev/null +++ b/ivtest/ivltests/always3.1.3F.v @@ -0,0 +1,40 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - always force reg_lvalue = constant ; +// D: No dependancy + +module main ; + +wire [3:0] value1 ; + +initial + begin + #15; + if(value1 != 4'h5) + $display("FAILED - 3.1.3F always force net_lvalue = constant;\n"); + else + begin + $display("PASSED\n"); + $finish; + end + end + +always force value1 = 4'h5; + +endmodule diff --git a/ivtest/ivltests/always3.1.3F2.v b/ivtest/ivltests/always3.1.3F2.v new file mode 100644 index 000000000..69467c0eb --- /dev/null +++ b/ivtest/ivltests/always3.1.3F2.v @@ -0,0 +1,42 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - always force reg_lvalue = constant ; +// D: No dependancy +// +// SJW - This is adjusted from always3.1.3F to be actually runnable. +// Without a delay in the always statement, there would be an +// infinite loop that blocks execution. + +module main ; + +wire [3:0] value1 ; + +initial + begin + #15; + if(value1 !== 4'h5) + $display("FAILED - 3.1.3F always force net_lvalue = constant;"); + else + $display("PASSED"); + $finish; + end + +always #10 force value1 = 4'h5; + +endmodule diff --git a/ivtest/ivltests/always3.1.3G.v b/ivtest/ivltests/always3.1.3G.v new file mode 100644 index 000000000..744237d8f --- /dev/null +++ b/ivtest/ivltests/always3.1.3G.v @@ -0,0 +1,40 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - always force net_lvalue = boolean_expr ; +// D: No dependancy + +module main ; + +wire [3:0] value1 ; + +initial + begin + #15; + if(value1 != 4'h5) + $display("FAILED - 3.1.3G always force net_lvalue = boolean_expr;\n"); + else + begin + $display("PASSED\n"); + $finish; + end + end + +always force value1 = 1'b1 && 1'b1; + +endmodule diff --git a/ivtest/ivltests/always3.1.3H.v b/ivtest/ivltests/always3.1.3H.v new file mode 100644 index 000000000..83c8eaddb --- /dev/null +++ b/ivtest/ivltests/always3.1.3H.v @@ -0,0 +1,40 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - always release reg_lvalue ; +// D: No dependancy + +module main ; + +reg [3:0] value1 ; + +initial + begin + #15; + if(value1 != 4'h5) + $display("FAILED - 3.1.3H always release rev_lvalue;\n"); + else + begin + $display("PASSED\n"); + $finish; + end + end + +always release value1 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.3J.v b/ivtest/ivltests/always3.1.3J.v new file mode 100644 index 000000000..06742fc40 --- /dev/null +++ b/ivtest/ivltests/always3.1.3J.v @@ -0,0 +1,40 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - always release net_lvalue ; +// D: No dependancy + +module main ; + +wire [3:0] value1 ; + +initial + begin + #15; + if(value1 != 4'h5) + $display("FAILED - 3.1.3H always release net_lvalue;\n"); + else + begin + $display("PASSED\n"); + $finish; + end + end + +always release value1 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.4A.v b/ivtest/ivltests/always3.1.4A.v new file mode 100644 index 000000000..881f4f9ac --- /dev/null +++ b/ivtest/ivltests/always3.1.4A.v @@ -0,0 +1,35 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always # delay_value ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + begin + # 20 ; + $display("PASSED\n"); + $finish; + end + +always # 10 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.4B.v b/ivtest/ivltests/always3.1.4B.v new file mode 100644 index 000000000..8649377ba --- /dev/null +++ b/ivtest/ivltests/always3.1.4B.v @@ -0,0 +1,43 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always # delay_value reg_lvalue = constant ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + begin + # 1; + if(value1 != 4'bxxxx) + $display("FAILED - 3.1.4B - initial value not xxxx;\n"); + #15 ; + if(value1 != 4'h5) + $display("FAILED - 3.1.4B - always # delay_value reg_lvalue = constant\n"); + else + begin + $display("PASSED\n"); + $finish; + end + end + +always # 10 value1 = 4'h5; + +endmodule diff --git a/ivtest/ivltests/always3.1.4C.v b/ivtest/ivltests/always3.1.4C.v new file mode 100644 index 000000000..19774b279 --- /dev/null +++ b/ivtest/ivltests/always3.1.4C.v @@ -0,0 +1,58 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always # delay_value reg_lvalue = boolean_expr ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; +reg err ; + +initial + begin + err = 0; + # 1; + if(value1 !== 4'bxxxx) + begin + $display("FAILED - 3.1.4C - initial value not xxxx;\n"); + err = 1; + end + #10 ; + if(value1 != 4'h5) + begin + $display("FAILED - 3.1.4C - always # delay_value reg_lvalue = boolean_expr\n"); + err = 1; + end + #10 ; + if(value1 != 4'hA) + begin + $display("FAILED - 3.1.4C - always # delay_value reg_lvalue = boolean_expr\n"); + err = 1; + end + + if (err == 0) + $display("PASSED\n"); + + $finish; + + end + +always # 10 value1 = ~value1; + +endmodule diff --git a/ivtest/ivltests/always3.1.4D.v b/ivtest/ivltests/always3.1.4D.v new file mode 100644 index 000000000..33939e738 --- /dev/null +++ b/ivtest/ivltests/always3.1.4D.v @@ -0,0 +1,35 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always # (mintypmax_dly) reg_lvalue ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + begin + #30; + $display("PASSED\n"); + $finish; + end + +always # (3:10:15) ; + +endmodule diff --git a/ivtest/ivltests/always3.1.4E.v b/ivtest/ivltests/always3.1.4E.v new file mode 100644 index 000000000..31cec81d1 --- /dev/null +++ b/ivtest/ivltests/always3.1.4E.v @@ -0,0 +1,50 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always # (mintypmax_dly) reg_lvalue = constant ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; +reg err ; + +initial + begin + err = 0; + # 1; + if(value1 !== 4'bxxxx) + begin + $display("FAILED - 3.1.4E - initial value not xxxx;\n"); + err = 1; + end + #15 ; + if(value1 != 4'h5) + begin + $display("FAILED - 3.1.4E - always # mintypmax_dly reg_lvalue = constant\n"); + err = 1; + end + + if (err == 0) + $display("PASSED\n"); + $finish; + end + +always # (3:10:15) value1 = 4'h5; + +endmodule diff --git a/ivtest/ivltests/always3.1.4F.v b/ivtest/ivltests/always3.1.4F.v new file mode 100644 index 000000000..edb3964f0 --- /dev/null +++ b/ivtest/ivltests/always3.1.4F.v @@ -0,0 +1,47 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always # (mintypmax_dly) reg_lvalue = boolean_expr ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + begin + # 1; + if(value1 != 4'bxxxx) + $display("FAILED - 3.1.4F - initial value not xxxx;\n"); + #10 ; + if(value1 != 4'h5) + $display("FAILED - 3.1.4F - always # (mintypmax_dly) reg_lvalue = boolean_expr\n"); + #10 ; + if(value1 != 4'hA) + $display("FAILED - 3.1.4F - always # (mintypmax_dly) reg_lvalue = boolean_expr\n"); + else + begin + $display("PASSED\n"); + end + $finish; + + end + +always # 10 value1 = ~value1; + +endmodule diff --git a/ivtest/ivltests/always3.1.4G.v b/ivtest/ivltests/always3.1.4G.v new file mode 100644 index 000000000..72ac989a1 --- /dev/null +++ b/ivtest/ivltests/always3.1.4G.v @@ -0,0 +1,37 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always @ (event_expression) ; +// D: + +module main ; + +reg [3:0] value1 ; + +initial + begin + # 10 ; + value1 = 4'h5; + # 10 ; + $display("PASSED\n"); + $finish; + end + +always @ (value1) ; + +endmodule diff --git a/ivtest/ivltests/always3.1.4H.v b/ivtest/ivltests/always3.1.4H.v new file mode 100644 index 000000000..ab7c85582 --- /dev/null +++ b/ivtest/ivltests/always3.1.4H.v @@ -0,0 +1,44 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always @ (event_expr) reg_lvalue = constant ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1,value2 ; + +initial + begin + # 1; + if(value1 != 4'bxxxx) + $display("FAILED - 3.1.4H - initial value not xxxx;\n"); + value2 = 4'h1; // Cause @ to execute. + #15 ; + if(value1 != 4'h5) + $display("FAILED - 3.1.4H - always @ (event_expression) reg_lvalue = constant ;\n"); + else + begin + $display("PASSED\n"); + $finish; + end + end + +always @ (value2) value1 = ~value1; + +endmodule diff --git a/ivtest/ivltests/always3.1.4I.v b/ivtest/ivltests/always3.1.4I.v new file mode 100644 index 000000000..290a0a905 --- /dev/null +++ b/ivtest/ivltests/always3.1.4I.v @@ -0,0 +1,49 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always @ (event_expression) reg_lvalue = boolean_expr ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1,value2; + +initial + begin + # 1; + if(value1 != 4'bxxxx) + $display("FAILED - 3.1.4I - initial value not xxxx;\n"); + value2 = 4'b1; + #10 ; + if(value1 != 4'h5) + $display("FAILED - 3.1.4I - always @ (event_expression) reg_lvalue = boolean_expr;\n"); + value2 = 4'b0; + #10 ; + if(value1 != 4'hA) + $display("FAILED - 3.1.4I - always @ (event_expression) reg_lvalue = boolean_expr;\n"); + else + begin + $display("PASSED\n"); + end + $finish; + + end + +always # 10 value1 = ~value1; + +endmodule diff --git a/ivtest/ivltests/always3.1.5A.v b/ivtest/ivltests/always3.1.5A.v new file mode 100644 index 000000000..9eccf4a73 --- /dev/null +++ b/ivtest/ivltests/always3.1.5A.v @@ -0,0 +1,42 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always if ( constant) statement ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + begin + value1 = 0; + # 5 ; + if(value1 != 4'd4) + $display("FAILED - always 3.1.5A always if ( constant) statement \n"); + else + $display("PASSED"); + $finish; + end + +always if( 1'b1) begin + # 1; + value1 = value1 + 1; + end + +endmodule diff --git a/ivtest/ivltests/always3.1.5B.v b/ivtest/ivltests/always3.1.5B.v new file mode 100644 index 000000000..13dcb140a --- /dev/null +++ b/ivtest/ivltests/always3.1.5B.v @@ -0,0 +1,42 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always if ( constant) statement else ; + +module main ; + +reg [3:0] value1 ; + +initial + begin + value1 = 0; + # 5 ; + if(value1 != 4'd4) + $display("FAILED - always 3.1.5B always if ( constant) statementelse ;"); + else + $display("PASSED"); + $finish; + end + +always if( 1'b1) begin + # 1; + value1 = value1 + 1; + end + else ; + +endmodule diff --git a/ivtest/ivltests/always3.1.5C.v b/ivtest/ivltests/always3.1.5C.v new file mode 100644 index 000000000..71d6b6105 --- /dev/null +++ b/ivtest/ivltests/always3.1.5C.v @@ -0,0 +1,42 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always if ( constant) statement_1 else statement_2 ; + +module main ; + +reg [3:0] value1 ; + +initial + begin + value1 = 0; + # 5 ; + if(value1 != 4'd4) + $display("FAILED - always 3.1.5C always if ( constant) statementelse ;"); + else + $display("PASSED"); + $finish; + end + +always if( 1'b1) begin + # 1; + value1 = value1 + 1; + end + else value1 = 0 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.5D.v b/ivtest/ivltests/always3.1.5D.v new file mode 100644 index 000000000..1e66852b0 --- /dev/null +++ b/ivtest/ivltests/always3.1.5D.v @@ -0,0 +1,42 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always if ( boolean_expr ) statement ; +// D: Note that initial has to be before always to execute! + +module main ; + +reg [3:0] value1 ; + +initial + begin + value1 = 0; + # 5 ; + if(value1 != 4'd4) + $display("FAILED - always 3.1.5D always if ( bool_expr) statement \n"); + else + $display("PASSED"); + $finish; + end + +always if( 1'b1 && 1'b1 ) begin + # 1; + value1 = value1 + 1; + end + +endmodule diff --git a/ivtest/ivltests/always3.1.5E.v b/ivtest/ivltests/always3.1.5E.v new file mode 100644 index 000000000..667edccda --- /dev/null +++ b/ivtest/ivltests/always3.1.5E.v @@ -0,0 +1,42 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always if ( bool_expr) statement else ; + +module main ; + +reg [3:0] value1 ; + +initial + begin + value1 = 0; + # 5 ; + if(value1 != 4'd4) + $display("FAILED - always 3.1.5E always if ( bool_expr) statementelse ;"); + else + $display("PASSED"); + $finish; + end + +always if( 1'b1 & 1'b1) begin + # 1; + value1 = value1 + 1; + end + else ; + +endmodule diff --git a/ivtest/ivltests/always3.1.5F.v b/ivtest/ivltests/always3.1.5F.v new file mode 100644 index 000000000..f8d11da7a --- /dev/null +++ b/ivtest/ivltests/always3.1.5F.v @@ -0,0 +1,42 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always if ( bool_expr) statement_1 else statement_2 ; + +module main ; + +reg [3:0] value1 ; + +initial + begin + value1 = 0; + # 5 ; + if(value1 != 4'd4) + $display("FAILED - always 3.1.5F always if ( bool_expr) statementelse ;"); + else + $display("PASSED"); + $finish; + end + +always if( 1'b1 | 1'b1) begin + # 1; + value1 = value1 + 1; + end + else value1 = 0 ; + +endmodule diff --git a/ivtest/ivltests/always3.1.6A.v b/ivtest/ivltests/always3.1.6A.v new file mode 100644 index 000000000..0dc20b807 --- /dev/null +++ b/ivtest/ivltests/always3.1.6A.v @@ -0,0 +1,83 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always case ( reg_value) case_item1; case_item2; case_item3; endcase +// D: + +module main ; + +reg [3:0] value1,value2,value3; + +initial + begin + #0; + value3 = 0; + #3 ; // t=3 + value1 = 4'b0000 ; // Picked up at time 4 + #5 ; // check at time 8 + if(value2 != 4'b0) + begin + $display("FAILED - always3.1.6A - case 0 at %t",$time); + value3 = 1; + end + #1 ; // Picked up at time 10 + value1 = 4'b0001 ; // Set at time 9. + + #5 ; // Check at time 14 + if(value2 != 4'b0001) + begin + $display("FAILED - always3.1.6A - case 1 at %t",$time); + value3 = 1; + end + #1; // Picked up at time 16 + value1 = 4'b0010; // Changed at time 15. + + #5; // Check at time 20... + if(value2 != 4'b0010) + begin + $display("FAILED - always3.1.6A - case 2 at %t",$time); + value3 = 1; + end + + #10; + if(value3 == 0) + $display("PASSED"); + $finish; + end + +always case (value1) + 4'b0000: begin + #3 ; + value2 = 4'b0000 ; + #3 ; + end + 4'b0001: begin + #3 ; + value2 = 4'b0001 ; + #3 ; + end + 4'b0010: begin + #3 ; + value2 = 4'b0010 ; + #3 ; + end + default: #2 ; + endcase + + +endmodule diff --git a/ivtest/ivltests/always3.1.6B.v b/ivtest/ivltests/always3.1.6B.v new file mode 100644 index 000000000..e0d52ada3 --- /dev/null +++ b/ivtest/ivltests/always3.1.6B.v @@ -0,0 +1,82 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always casex ( reg_value) case_item1; case_item2; case_item3; endcase +// D: + +module main ; + +reg [3:0] value1,value2,value3; + +initial + begin + #0; + value3 = 0; + #1 ; // t=3 + value1 = 4'b0000 ; // Picked up at time 6 + #9 ; // check at time 10 + if(value2 != 4'b0) + begin + $display("FAILED - always3.1.6B - casex 0 at %t",$time); + value3 = 1; + end + #1 ; // Picked up at time 12 + value1 = 4'b0011 ; // Set at time 11. + + #5 ; // Check at time 16 + if(value2 != 4'b0001) + begin + $display("FAILED - always3.1.6B - casex 1 at %t",$time); + value3 = 1; + end + #1; // Picked up at time 16 + value1 = 4'b0100; // Changed at time 15. + + #5; // Check at time 20... + if(value2 != 4'b0010) + begin + $display("FAILED - always3.1.6B - casex 2 at %t",$time); + value3 = 1; + end + + #10; + if(value3 == 0) + $display("PASSED"); + $finish; + end + +always casex (value1) + 4'b0000: begin + #3 ; + value2 = 4'b0000 ; + #3 ; + end + 4'b00x1: begin + #3 ; + value2 = 4'b0001 ; + #3 ; + end + 4'b0100: begin + #3 ; + value2 = 4'b0010 ; + #3 ; + end + endcase + + +endmodule diff --git a/ivtest/ivltests/always3.1.6C.v b/ivtest/ivltests/always3.1.6C.v new file mode 100644 index 000000000..083aa05cc --- /dev/null +++ b/ivtest/ivltests/always3.1.6C.v @@ -0,0 +1,99 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always casez ( reg_value) case_item1; case_item2; case_item3; endcase +// D: + +module main ; + +reg [3:0] value1,value2,value3; + +initial + begin + #0; +// $dumpfile("test.vcd"); +// $dumpvars(0,main); + value3 = 0; + #3 ; // t=3 + value1 = 4'b0000 ; // Picked up at time 4 + #5 ; // check at time 8 + $display("check == 0000:at time=%t value2=%h",$time,value2); + if(value2 != 4'b0) + begin + $display("FAILED - always3.1.6C - casez 0 at %t",$time); + value3 = 1; + end + #1 ; // Picked up at time 10 + value1 = 4'b00z1 ; // Set at time 9. + + #5 ; // Check at time 14 + $display("check == 0001:at time=%t value2=%h",$time,value2); + if(value2 != 4'b0001) + begin + $display("FAILED - always3.1.6C - casez z1 at %t",$time); + value3 = 1; + end + #1; // Picked up at time 16 + value1 = 4'b0100; // Changed at time 15. + + #5; // Check at time 20... + $display("check == 0010:at time=%t value2=%h",$time,value2); + if(value2 != 4'b0010) + begin + $display("FAILED - always3.1.6C - casez 4 at %t",$time); + value3 = 1; + end + + #10; + if(value3 == 0) + $display("PASSED"); + $finish; + end + +always + begin + $display("Entering case at time=%t value1=%b",$time,value1); + casez (value1) + 4'b0000: begin + #3 ; + value2 = 4'b0000 ; + $display("case0000: at time=%t",$time); + #3 ; + end + 4'b00z1: begin + #3 ; + value2 = 4'b0001 ; + $display("case00z1: at time=%t",$time); + #3 ; + end + 4'b0100: begin + #3 ; + value2 = 4'b0010 ; + $display("case100: at time=%t",$time); + #3 ; + end + default: + begin + #2 ; + $display("default: %t",$time); + end + endcase + $display("Leaving case at time=%t",$time); + end + +endmodule diff --git a/ivtest/ivltests/always3.1.6D.v b/ivtest/ivltests/always3.1.6D.v new file mode 100644 index 000000000..d06dd7f37 --- /dev/null +++ b/ivtest/ivltests/always3.1.6D.v @@ -0,0 +1,83 @@ +// + // Copyright (c) 1999 Stephen Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always case ( reg_value) case_item1; case_item2; case_item3; endcase +// D: + + + // time value1 value2 + // xxxx xxxx + // 1 0000 + // 2 0000 + // 3 0001 + // 4 0001 + // 5 0010 + // 6 0010 + +module main ; + +reg [3:0] value1,value2,value3; + +initial begin + #1 ; + #2 if (value2 != 0) begin + $display("FAILED == at time 3, %b != 0", value2); + $finish; + end + #2 if (value2 != 1) begin + $display("FAILED == at time 5, %b != 1", value2); + $finish; + end + #2 if (value2 != 2) begin + $display("FAILED == at time 7, %b != 2", value2); + $finish; + end + $display("PASSED"); + $finish; +end + +initial begin + #1 value1 = 4'b0000; + #2 value1 = 4'b0001; + #2 value1 = 4'b0010; +end + +always case (value1) + 4'b0000 : begin + value2 = 4'b0000 ; + #2 ; + end + 4'b0001 : begin + value2 = 4'b0001 ; + #2 ; + end + 4'b0010 : begin + value2 = 4'b0010 ; + #2 ; + end + 4'bxxxx : #2 ; + + default : begin + $display("FAILED -- unexpected value1===%b", value1); + $finish; + end + + endcase + + +endmodule diff --git a/ivtest/ivltests/always3.1.7A.v b/ivtest/ivltests/always3.1.7A.v new file mode 100644 index 000000000..7aa83b887 --- /dev/null +++ b/ivtest/ivltests/always3.1.7A.v @@ -0,0 +1,58 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always forever statement ; + +module main ; + +reg [3:0] value1,value2,value3; + +initial + begin + value1 = 0; // Time 0 assignemnt + value2 = 0; + #6 ; + if(value1 != 4'h1) + begin + $display("FAILED - 3.1.7A always forever (1) "); + value2 = 1; + end + #5 ; + if(value1 != 4'h2) + begin + $display("FAILED - 3.1.7A always forever (2) "); + value2 = 1; + end + #5 ; + if(value1 != 4'h3) + begin + $display("FAILED - 3.1.7A always forever (3) "); + value2 = 1; + end + if(value2 == 0) + $display("PASSED"); + $finish; + end + +always forever begin + #5 ; + value1 = value1 + 1; + end + + +endmodule diff --git a/ivtest/ivltests/always3.1.7B.v b/ivtest/ivltests/always3.1.7B.v new file mode 100644 index 000000000..528afba7b --- /dev/null +++ b/ivtest/ivltests/always3.1.7B.v @@ -0,0 +1,58 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always repeat (expression) statement ; + +module main ; + +reg [3:0] value1,value2,value3; + +initial + begin + value1 = 0; // Time 0 assignemnt + value2 = 0; + #6 ; + if(value1 != 4'h1) + begin + $display("FAILED - 3.1.7B always forever (1) "); + value2 = 1; + end + #5 ; + if(value1 != 4'h2) + begin + $display("FAILED - 3.1.7B always forever (2) "); + value2 = 1; + end + #5 ; + if(value1 != 4'h3) + begin + $display("FAILED - 3.1.7B always forever (3) "); + value2 = 1; + end + if(value2 == 0) + $display("PASSED"); + $finish; + end + +always repeat(3) begin + #5 ; + value1 = value1 + 1; + end + + +endmodule diff --git a/ivtest/ivltests/always3.1.7C.v b/ivtest/ivltests/always3.1.7C.v new file mode 100644 index 000000000..cd4f055a0 --- /dev/null +++ b/ivtest/ivltests/always3.1.7C.v @@ -0,0 +1,59 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always while (boolean_expression ) statement ; + + +module main ; + +reg [3:0] value1,value2,value3; + +initial + begin + value1 = 0; // Time 0 assignemnt + value2 = 0; + #6 ; + if(value1 != 4'h1) + begin + $display("FAILED - 3.1.7C always while (1'b1 )") ; + value2 = 1; + end + #5 ; + if(value1 != 4'h2) + begin + $display("FAILED - 3.1.7C always while (1'b1) "); + value2 = 1; + end + #5 ; + if(value1 != 4'h3) + begin + $display("FAILED - 3.1.7C always while (1'b1) "); + value2 = 1; + end + if(value2 == 0) + $display("PASSED"); + $finish; + end + +always while (1'b1 && 1'b1) begin + #5 ; + value1 = value1 + 1; + end + + +endmodule diff --git a/ivtest/ivltests/always3.1.7D.v b/ivtest/ivltests/always3.1.7D.v new file mode 100644 index 000000000..ba0e03e20 --- /dev/null +++ b/ivtest/ivltests/always3.1.7D.v @@ -0,0 +1,56 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always for (expr1;boolean_expr;expr2) statement ; + + +module main ; + +reg [3:0] value1,value2,value3; + +initial + begin + value1 = 0; // Time 0 assignemnt + value2 = 0; + #6 ; + if(value1 != 4'h1) + begin + $display("FAILED - 3.1.7D always for (1)") ; + value2 = 1; + end + #5 ; + if(value1 != 4'h2) + begin + $display("FAILED - 3.1.7D always for (2) "); + value2 = 1; + end + #5 ; + if(value1 != 4'h3) + begin + $display("FAILED - 3.1.7D always for (3) "); + value2 = 1; + end + if(value2 == 0) + $display("PASSED"); + $finish; + end + +always for(value1 = 0; value1 <= 5; value1 = value1 + 1) #5 ; + + +endmodule diff --git a/ivtest/ivltests/always3.1.8A.v b/ivtest/ivltests/always3.1.8A.v new file mode 100644 index 000000000..1f0486712 --- /dev/null +++ b/ivtest/ivltests/always3.1.8A.v @@ -0,0 +1,69 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always wait (expression ) reg_lvalue = constant ; + + +module main ; + +reg [3:0] value1,value2,value3; + +always wait (value1 == 4'h3) begin + value2 = 3 ; + #1 ; + end + +initial + begin + value1 = 0; + value2 = 0; + value3 = 0; + #2 ; + if(value2 != 0) + begin + $display("FAILED - 3.1.8A always wait (expr) reg_lval = const (1);"); + value3 = 1; + end + value1 = 1; + #2 ; + if(value2 != 0) + begin + $display("FAILED - 3.1.8A always wait (expr) reg_lval = const (2);"); + value3 = 1; + end + value1 = 2; + #2 ; + if(value2 != 0) + begin + $display("FAILED - 3.1.8A always wait (expr) reg_lval = const (3);"); + value3 = 1; + end + value1 = 4'h3; + #2; + if(value2 != 3) + begin + $display("FAILED - 3.1.8A always wait (expr) reg_lval = const (4);"); + value3 = 1; + end + #10; + if(value3 == 0) + $display("PASSED"); + $finish ; + end + +endmodule diff --git a/ivtest/ivltests/always3.1.9A.v b/ivtest/ivltests/always3.1.9A.v new file mode 100644 index 000000000..a579d025f --- /dev/null +++ b/ivtest/ivltests/always3.1.9A.v @@ -0,0 +1,42 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always disable task_identifier ; + + +module main ; + + +reg [3:0] value1 ; + +task foo ; + value1 = #1 1; +endtask + +initial + begin + value1 = 0; + #2 ; + $display("value = %d",value1); + #1 ; + $finish ; + end + +always disable foo ; + +endmodule diff --git a/ivtest/ivltests/always3.1.9B.v b/ivtest/ivltests/always3.1.9B.v new file mode 100644 index 000000000..44cb088d2 --- /dev/null +++ b/ivtest/ivltests/always3.1.9B.v @@ -0,0 +1,35 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always disable block_identifier ; + + +module main ; + + +reg [3:0] value1 ; + +always begin : block_id + #1 ; + $display("Hi there"); + $finish ; + end + +always disable block_id ; + +endmodule diff --git a/ivtest/ivltests/always3.1.9C.v b/ivtest/ivltests/always3.1.9C.v new file mode 100644 index 000000000..8be1ae0f8 --- /dev/null +++ b/ivtest/ivltests/always3.1.9C.v @@ -0,0 +1,45 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always #1 disable task_identifier ; + +module main ; + + +reg [3:0] value1 ; + +task foo ; + value1 = #2 1; +endtask + +initial + begin + value1 = 1'b0; + #5; + foo ; + #4 ; + if(value1 === 1'b0) + $display("PASSED"); + else + $display("FAILED - always3.1.9C always #2 disable foo"); + $finish ; + end + +always #6 disable foo ; + +endmodule diff --git a/ivtest/ivltests/always3.1.9D.v b/ivtest/ivltests/always3.1.9D.v new file mode 100644 index 000000000..38765f6d1 --- /dev/null +++ b/ivtest/ivltests/always3.1.9D.v @@ -0,0 +1,47 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always disable block_identifier ; + + +module main ; + + +reg [3:0] value1 ; + +always begin : block_id + #4 ; + value1 = 1; + $finish ; + end + +initial + begin + value1 = 0; + #5; + if(value1 === 1'b0) + $display("PASSED"); + else + $display("FAILED - always3.1.9D always #1 disable block_id"); + #1; + $finish ; + end + +always #3 disable block_id ; + +endmodule diff --git a/ivtest/ivltests/always4A.v b/ivtest/ivltests/always4A.v new file mode 100644 index 000000000..030d5b32b --- /dev/null +++ b/ivtest/ivltests/always4A.v @@ -0,0 +1,15 @@ +module top; + + // A join_any will always take the shortest path + always fork + #0; + #1; + join_any + + initial begin + $display("FAILED"); + #1; + $finish; + end + +endmodule diff --git a/ivtest/ivltests/always4B.v b/ivtest/ivltests/always4B.v new file mode 100644 index 000000000..a1a5bad26 --- /dev/null +++ b/ivtest/ivltests/always4B.v @@ -0,0 +1,15 @@ +module top; + + // A join_any will always take the shortest path + always fork + #2; + #1; + join_none + + initial begin + $display("FAILED"); + #1; + $finish; + end + +endmodule diff --git a/ivtest/ivltests/always_comb.v b/ivtest/ivltests/always_comb.v new file mode 100644 index 000000000..501644cdf --- /dev/null +++ b/ivtest/ivltests/always_comb.v @@ -0,0 +1,76 @@ +module top; + reg y, a, b, flip, hidden; + reg pass; + + function f_and (input i1, i2); + reg partial; + begin + partial = i1 & i2; + f_and = partial | hidden; + end + endfunction + + reg intr; + always_comb begin + intr = flip; + y = f_and(a, b) ^ intr; + end + + initial begin + pass = 1'b1; + + flip = 1'b0; + hidden = 1'b0; + a = 1'b0; + b = 1'b0; + #1; + if (y !== 1'b0) begin + $display("FAILED: a=1'b0, b=1'b0, hidden=1'b0, expected 1'b0, got %b", y); + pass = 1'b0; + end + + a = 1'b0; + b = 1'b1; + #1; + if (y !== 1'b0) begin + $display("FAILED: a=1'b0, b=1'b1, hidden=1'b0, expected 1'b0, got %b", y); + pass = 1'b0; + end + + a = 1'b1; + b = 1'b0; + #1; + if (y !== 1'b0) begin + $display("FAILED: a=1'b1, b=1'b0, hidden=1'b0, expected 1'b0, got %b", y); + pass = 1'b0; + end + + a = 1'b1; + b = 1'b1; + #1; + if (y !== 1'b1) begin + $display("FAILED: a=1'b1, b=1'b1, hidden=1'b0, expected 1'b1, got %b", y); + pass = 1'b0; + end + + hidden = 1'b0; + a = 1'b0; + b = 1'b0; + #1; + if (y !== 1'b0) begin + $display("FAILED: a=1'b0, b=1'b0, hidden=1'b0, expected 1'b0, got %b", y); + pass = 1'b0; + end + + hidden = 1'b1; + a = 1'b0; + b = 1'b0; + #1; + if (y !== 1'b1) begin + $display("FAILED: a=1'b0, b=1'b0, hidden=1'b1, expected 1'b1, got %b", y); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/always_comb_fail.v b/ivtest/ivltests/always_comb_fail.v new file mode 100644 index 000000000..8d1808dba --- /dev/null +++ b/ivtest/ivltests/always_comb_fail.v @@ -0,0 +1,10 @@ +module top; + reg q, d; + + always_comb begin + #0 q = d; + end + + initial $display("Expected compile failure!"); + +endmodule diff --git a/ivtest/ivltests/always_comb_fail3.v b/ivtest/ivltests/always_comb_fail3.v new file mode 100644 index 000000000..62475ed79 --- /dev/null +++ b/ivtest/ivltests/always_comb_fail3.v @@ -0,0 +1,11 @@ +module top; + reg q, d; + event foo; + + always_comb begin + @foo q = d; + end + + initial $display("Expected compile failure!"); + +endmodule diff --git a/ivtest/ivltests/always_comb_fail4.v b/ivtest/ivltests/always_comb_fail4.v new file mode 100644 index 000000000..155aff296 --- /dev/null +++ b/ivtest/ivltests/always_comb_fail4.v @@ -0,0 +1,24 @@ +module top; + reg a, b; + reg q, d; + event foo; + + always_comb begin + q = d; + fork + $display("fork/join 1"); + join + fork + $display("fork/join_any 1"); + join_any + fork + $display("fork/join_none 1"); + join_none + a <= @foo 1'b1; + @(b) a <= repeat(2) @foo 1'b0; + wait (!a) $display("wait"); + end + + initial #1 $display("Expect compile errors!"); + +endmodule diff --git a/ivtest/ivltests/always_comb_no_sens.v b/ivtest/ivltests/always_comb_no_sens.v new file mode 100644 index 000000000..a249eedaf --- /dev/null +++ b/ivtest/ivltests/always_comb_no_sens.v @@ -0,0 +1,22 @@ +module test; + reg passed; + logic y; + + always_comb begin + y = 1'b0; + end + + initial begin + passed = 1'b1; + if (y !== 1'bx) begin + $display("FAILED: expected 1'bx, got %b", y); + passed = 1'b0; + end + #1; + if (y !== 1'b0) begin + $display("FAILED: expected 1'b0, got %b", y); + passed = 1'b0; + end + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/always_comb_rfunc.v b/ivtest/ivltests/always_comb_rfunc.v new file mode 100644 index 000000000..e6586c785 --- /dev/null +++ b/ivtest/ivltests/always_comb_rfunc.v @@ -0,0 +1,44 @@ +module top; + logic passed; + logic [7:0] value; + integer ones; + + function automatic integer count_by_one(input integer start); + if (start) count_by_one = (value[start] ? 1 : 0) + count_ones(start-1); + else count_by_one = value[start] ? 1 : 0; + endfunction + + function automatic integer count_ones(input integer start); + if (start) count_ones = (value[start] ? 1 : 0) + count_by_one(start-1); + else count_ones = value[start] ? 1 : 0; + endfunction + + always_comb ones = count_ones(7); + + initial begin + passed = 1'b1; + + value = 8'b0000_0000; + #1; + if (ones !== 0) begin + $display("Expected 0, got %d", ones); + passed = 1'b0; + end + + value = 8'b0011_1100; + #1; + if (ones !== 4) begin + $display("Expected 4, got %d", ones); + passed = 1'b0; + end + + value = 8'b1011_1101; + #1; + if (ones !== 6) begin + $display("Expected 6, got %d", ones); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/always_comb_trig.v b/ivtest/ivltests/always_comb_trig.v new file mode 100644 index 000000000..81e809e97 --- /dev/null +++ b/ivtest/ivltests/always_comb_trig.v @@ -0,0 +1,60 @@ +module top; + reg a, q, qb; + reg pass; + + always_comb q = a !== 1'bx; + + always_comb qb = a === 1'bx; + + initial begin + pass = 1'b1; + #0; + // This second delay is needed for vlog95 since it uses #0 to create + // the T0 trigger. vvp also needs it since it puts the event in the + // inactive queue just like a #0 delay. + #0; + if (q !== 1'b0) begin + $display("Expected q = 1'b0 with the default 1'bx input, got %b", q); + pass = 1'b0; + end + if (qb !== 1'b1) begin + $display("Expected qb = 1'b1 with the default 1'bx input, got %b", qb); + pass = 1'b0; + end + + #1; + a = 1'b0; + #0; + if (q !== 1'b1) begin + $display("Expected q = 1'b1 with an explicit 1'b0 input, got %b", q); + pass = 1'b0; + end + + #1; + a = 1'b1; + #0; + if (q !== 1'b1) begin + $display("Expected q = 1'b1 with an explicit 1'b1 input, got %b", q); + pass = 1'b0; + end + + #1; + a = 1'bz; + #0; + if (q !== 1'b1) begin + $display("Expected q = 1'b1 with an explicit 1'bz input, got %b", q); + pass = 1'b0; + end + + #1; + a = 1'bx; + #0; + if (q !== 1'b0) begin + $display("Expected q = 1'b0 with an explicit 1'bx input, got %b", q); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/always_comb_warn.v b/ivtest/ivltests/always_comb_warn.v new file mode 100644 index 000000000..0dcd1fa36 --- /dev/null +++ b/ivtest/ivltests/always_comb_warn.v @@ -0,0 +1,61 @@ +module top; + reg a; + reg q, d; + event foo; + real rl; + int ar []; + int start = 0; + int stop = 1; + int step = 1; + int done = 0; + + task a_task; + real trl; + event tevt; + reg tvr; + $display("user task"); + endtask + + always_comb begin: blk_name + event int1, int2; + real intrl; + q <= d; + -> foo; + rl = 0.0; + rl <= 1.0; + ar = new [2]; + for (int idx = start; idx < stop; idx += step) $display("For: %0d", idx); + for (int idx = 0; done; idx = done + 1) $display("Should never run!"); + for (int idx = 0; idx; done = done + 1) $display("Should never run!"); + for (int idx = 0; idx; {done, idx} = done + 1) $display("Should never run!"); + for (int idx = 0; idx; idx <<= 1) $display("Should never run!"); + for (int idx = 0; idx; idx = idx << 1) $display("Should never run!"); + $display("array size: %0d", ar.size()); + ar.delete(); + $display("array size: %0d", ar.size()); + a_task; + assign a = 1'b0; + deassign a; + do $display("do/while"); + while (a); + force a = 1'b1; + release a; + while(a) begin + $display("while"); + a = 1'b0; + end + repeat(2) $display("repeat"); + disable out_name; + forever begin + $display("forever"); + disable blk_name; // This one should not generate a warning + end + end + + initial #1 $display("Expect compile warnings!\nPASSED"); + + initial begin: out_name + #2 $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/always_ff.v b/ivtest/ivltests/always_ff.v new file mode 100644 index 000000000..38f64b7f8 --- /dev/null +++ b/ivtest/ivltests/always_ff.v @@ -0,0 +1,43 @@ +module top; + reg q, clk, d; + reg pass; + + always_ff @(posedge clk) begin + q <= d; + end + + initial begin + pass = 1'b1; + + #1; + if (q !== 1'bx) begin + $display("FAILED: initally expected 1'bx, got %b", q); + pass = 1'b0; + end + + d = 1'b0; + clk = 1'b1; + #1; + if (q !== 1'b0) begin + $display("FAILED: clock in a 0 expected 1'b0, got %b", q); + pass = 1'b0; + end + + d = 1'b1; + clk = 1'b0; + #1; + if (q !== 1'b0) begin + $display("FAILED: no clock change expected 1'b0, got %b", q); + pass = 1'b0; + end + + clk = 1'b1; + #1; + if (q !== 1'b1) begin + $display("FAILED: clock in a 1 expected 1'b1, got %b", q); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/always_ff_fail.v b/ivtest/ivltests/always_ff_fail.v new file mode 100644 index 000000000..ddafb0adf --- /dev/null +++ b/ivtest/ivltests/always_ff_fail.v @@ -0,0 +1,10 @@ +module top; + reg q, clk, d; + + always_ff @(posedge clk) begin + #0 q <= d; + end + + initial $display("Expected compile failure!"); + +endmodule diff --git a/ivtest/ivltests/always_ff_fail2.v b/ivtest/ivltests/always_ff_fail2.v new file mode 100644 index 000000000..22a0103f7 --- /dev/null +++ b/ivtest/ivltests/always_ff_fail2.v @@ -0,0 +1,11 @@ +module top; + reg q, clk, d; + + always_ff begin + q <= d; + @(posedge clk); + end + + initial $display("Expected compile failure!"); + +endmodule diff --git a/ivtest/ivltests/always_ff_fail3.v b/ivtest/ivltests/always_ff_fail3.v new file mode 100644 index 000000000..27744da14 --- /dev/null +++ b/ivtest/ivltests/always_ff_fail3.v @@ -0,0 +1,11 @@ +module top; + reg q, clk, d; + event foo; + + always_ff @(posedge clk) begin + @foo q <= d; + end + + initial $display("Expected compile failure!"); + +endmodule diff --git a/ivtest/ivltests/always_ff_fail4.v b/ivtest/ivltests/always_ff_fail4.v new file mode 100644 index 000000000..1e0b3faea --- /dev/null +++ b/ivtest/ivltests/always_ff_fail4.v @@ -0,0 +1,25 @@ +module top; + reg a, b; + reg q, d; + reg clk; + event foo; + + always_ff @(posedge clk) begin + q <= d; + fork + $display("fork/join 1"); + join + fork + $display("fork/join_any 1"); + join_any + fork + $display("fork/join_none 1"); + join_none + a <= @foo 1'b1; + @(b) a <= repeat(2) @foo 1'b0; + wait (!a) $display("wait"); + end + + initial #1 $display("Expect compile errors!"); + +endmodule diff --git a/ivtest/ivltests/always_ff_no_sens.v b/ivtest/ivltests/always_ff_no_sens.v new file mode 100644 index 000000000..3531ca522 --- /dev/null +++ b/ivtest/ivltests/always_ff_no_sens.v @@ -0,0 +1,9 @@ +module test; + logic y; + + always_ff begin + y = 1'b0; + end + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/always_ff_warn.v b/ivtest/ivltests/always_ff_warn.v new file mode 100644 index 000000000..b4185a69e --- /dev/null +++ b/ivtest/ivltests/always_ff_warn.v @@ -0,0 +1,65 @@ +module top; + reg a; + reg q, d; + reg clk; + event foo; + real rl; + int ar []; + int start = 0; + int stop = 1; + int step = 1; + int done = 0; + + task a_task; + real trl; + event tevt; + reg tvr; + $display("user task"); + endtask + + always_ff @(posedge clk) begin: blk_name + event int1, int2; + real intrl; + q = d; + -> foo; + rl = 0.0; + rl <= 1.0; + ar = new [2]; + for (int idx = start; idx < stop; idx += step) $display("For: %0d", idx); + for (int idx = 0; done; idx = done + 1) $display("Should never run!"); + for (int idx = 0; idx; done = done + 1) $display("Should never run!"); + for (int idx = 0; idx; {done, idx} = done + 1) $display("Should never run!"); + for (int idx = 0; idx; idx <<= 1) $display("Should never run!"); + for (int idx = 0; idx; idx = idx << 1) $display("Should never run!"); + $display("array size: %0d", ar.size()); + ar.delete(); + $display("array size: %0d", ar.size()); + a_task; + assign a = 1'b0; + deassign a; + do $display("do/while"); + while (a); + force a = 1'b1; + release a; + while(a) begin + $display("while"); + a = 1'b0; + end + repeat(2) $display("repeat"); + disable out_name; + forever begin + $display("forever"); + disable blk_name; // This one should not generate a warning + end + end + + initial begin + #1 clk = 1'b1; + #0 $display("Expect compile warnings!\nPASSED"); + end + + initial begin: out_name + #2 $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/always_ff_warn_sens.v b/ivtest/ivltests/always_ff_warn_sens.v new file mode 100644 index 000000000..a74cdeac3 --- /dev/null +++ b/ivtest/ivltests/always_ff_warn_sens.v @@ -0,0 +1,64 @@ +module top; + reg q1, q2, q3, q4, q5, q6, q7, d; + reg clk; + reg [5:4] rst; + integer i; + + // The compiler should warn that clk is missing an edge keyword. + always_ff @(clk) begin + q1 <= d; + end + + // The compiler should warn that rst is missing an edge keyword. + always_ff @(posedge clk or rst[4]) begin + if (rst[4]) + q2 <= 1'b0; + else + q2 <= d; + end + + // The compiler should warn that rst is missing an edge keyword. + always_ff @(posedge clk or rst[i]) begin + if (rst[i]) + q3 <= 1'b0; + else + q3 <= d; + end + + // The compiler should warn that rst is missing an edge keyword. + always_ff @(posedge clk or !rst) begin + if (!rst) + q4 <= 1'b0; + else + q4 <= d; + end + + // The compiler should warn that rst is missing an edge keyword. + always_ff @(posedge clk or ~rst[4]) begin + if (~rst[4]) + q5 <= 1'b0; + else + q5 <= d; + end + + // The compiler should warn that rst is missing an edge keyword. + always_ff @(posedge clk or &rst) begin + if (&rst) + q6 <= 1'b0; + else + q6 <= d; + end + + // The compiler should warn that rst is not a single bit. + always_ff @(posedge clk or posedge rst) begin + if (rst) + q7 <= 1'b0; + else + q7 <= d; + end + + initial begin + $display("Expect compile warnings!\nPASSED"); + end + +endmodule diff --git a/ivtest/ivltests/always_latch.v b/ivtest/ivltests/always_latch.v new file mode 100644 index 000000000..f18dc3e39 --- /dev/null +++ b/ivtest/ivltests/always_latch.v @@ -0,0 +1,87 @@ +module top; + reg y, a, b, flip, hidden, en; + reg pass; + + function f_and (input i1, i2); + reg partial; + begin + partial = i1 & i2; + f_and = partial | hidden; + end + endfunction + + reg intr; + always_latch begin + if (en) begin + intr = flip; + y <= f_and(a, b) ^ intr; + end + end + + initial begin + pass = 1'b1; + + en = 1'b1; + flip = 1'b0; + hidden = 1'b0; + a = 1'b0; + b = 1'b0; + #1; + if (y !== 1'b0) begin + $display("FAILED: a=1'b0, b=1'b0, hidden=1'b0, expected 1'b0, got %b", y); + pass = 1'b0; + end + + a = 1'b0; + b = 1'b1; + #1; + if (y !== 1'b0) begin + $display("FAILED: a=1'b0, b=1'b1, hidden=1'b0, expected 1'b0, got %b", y); + pass = 1'b0; + end + + a = 1'b1; + b = 1'b0; + #1; + if (y !== 1'b0) begin + $display("FAILED: a=1'b1, b=1'b0, hidden=1'b0, expected 1'b0, got %b", y); + pass = 1'b0; + end + + a = 1'b1; + b = 1'b1; + #1; + if (y !== 1'b1) begin + $display("FAILED: a=1'b1, b=1'b1, hidden=1'b0, expected 1'b1, got %b", y); + pass = 1'b0; + end + + hidden = 1'b0; + a = 1'b0; + b = 1'b0; + #1; + if (y !== 1'b0) begin + $display("FAILED: a=1'b0, b=1'b0, hidden=1'b0, expected 1'b0, got %b", y); + pass = 1'b0; + end + + hidden = 1'b1; + a = 1'b0; + b = 1'b0; + #1; + if (y !== 1'b1) begin + $display("FAILED: a=1'b0, b=1'b0, hidden=1'b1, expected 1'b1, got %b", y); + pass = 1'b0; + end + + en = 1'b0; + hidden = 1'b0; + #1; + if (y !== 1'b1) begin + $display("FAILED: en=1'b0, expected 1'b1, got %b", y); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/always_latch_fail.v b/ivtest/ivltests/always_latch_fail.v new file mode 100644 index 000000000..82e00d6c0 --- /dev/null +++ b/ivtest/ivltests/always_latch_fail.v @@ -0,0 +1,10 @@ +module top; + reg q, en, d; + + always_latch begin + if (en) #0 q <= d; + end + + initial $display("Expected compile failure!"); + +endmodule diff --git a/ivtest/ivltests/always_latch_fail3.v b/ivtest/ivltests/always_latch_fail3.v new file mode 100644 index 000000000..ddb9d53c2 --- /dev/null +++ b/ivtest/ivltests/always_latch_fail3.v @@ -0,0 +1,11 @@ +module top; + reg q, en, d; + event foo; + + always_latch begin + if (en) @foo q <= d; + end + + initial $display("Expected compile failure!"); + +endmodule diff --git a/ivtest/ivltests/always_latch_fail4.v b/ivtest/ivltests/always_latch_fail4.v new file mode 100644 index 000000000..7bae7070a --- /dev/null +++ b/ivtest/ivltests/always_latch_fail4.v @@ -0,0 +1,24 @@ +module top; + reg a, b; + reg q, d; + event foo; + + always_latch begin + q <= d; + fork + $display("fork/join 1"); + join + fork + $display("fork/join_any 1"); + join_any + fork + $display("fork/join_none 1"); + join_none + a <= @foo 1'b1; + @(b) a <= repeat(2) @foo 1'b0; + wait (!a) $display("wait"); + end + + initial #1 $display("Expect compile errors!"); + +endmodule diff --git a/ivtest/ivltests/always_latch_no_sens.v b/ivtest/ivltests/always_latch_no_sens.v new file mode 100644 index 000000000..2d3185635 --- /dev/null +++ b/ivtest/ivltests/always_latch_no_sens.v @@ -0,0 +1,9 @@ +module test; + logic y; + + always_latch begin + y = 1'b0; + end + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/always_latch_trig.v b/ivtest/ivltests/always_latch_trig.v new file mode 100644 index 000000000..cbebebd0d --- /dev/null +++ b/ivtest/ivltests/always_latch_trig.v @@ -0,0 +1,55 @@ +module top; + reg a, enb, q; + reg pass; + + always_latch if (enb !== 1'b1) q <= a !== 1'bx; + + + initial begin + pass = 1'b1; + #1; + if (q !== 1'b0) begin + $display("Expected q = 1'b0 with the default 1'bx input, got %b", q); + pass = 1'b0; + end + + a = 1'b0; + #1; + if (q !== 1'b1) begin + $display("Expected q = 1'b1 with an explicit 1'b0 input, got %b", q); + pass = 1'b0; + end + + a = 1'b1; + #1; + if (q !== 1'b1) begin + $display("Expected q = 1'b1 with an explicit 1'b1 input, got %b", q); + pass = 1'b0; + end + + a = 1'bz; + #1; + if (q !== 1'b1) begin + $display("Expected q = 1'b1 with an explicit 1'bz input, got %b", q); + pass = 1'b0; + end + + a = 1'bx; + #1; + if (q !== 1'b0) begin + $display("Expected q = 1'b0 with an explicit 1'bx input, got %b", q); + pass = 1'b0; + end + + enb = 1'b1; + a = 1'bz; + #1; + if (q !== 1'b0) begin + $display("Expected q = 1'b0 with an enb = 1'b1, got %b", q); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/always_latch_warn.v b/ivtest/ivltests/always_latch_warn.v new file mode 100644 index 000000000..047e3eb34 --- /dev/null +++ b/ivtest/ivltests/always_latch_warn.v @@ -0,0 +1,61 @@ +module top; + reg a; + reg q, d; + event foo; + real rl; + int ar []; + int start = 0; + int stop = 1; + int step = 1; + int done = 0; + + task a_task; + real trl; + event tevt; + reg tvr; + $display("user task"); + endtask + + always_latch begin: blk_name + event int1, int2; + real intrl; + q = d; + -> foo; + rl = 0.0; + rl <= 1.0; + ar = new [2]; + for (int idx = start; idx < stop; idx += step) $display("For: %0d", idx); + for (int idx = 0; done; idx = done + 1) $display("Should never run!"); + for (int idx = 0; idx; done = done + 1) $display("Should never run!"); + for (int idx = 0; idx; {done, idx} = done + 1) $display("Should never run!"); + for (int idx = 0; idx; idx <<= 1) $display("Should never run!"); + for (int idx = 0; idx; idx = idx << 1) $display("Should never run!"); + $display("array size: %0d", ar.size()); + ar.delete(); + $display("array size: %0d", ar.size()); + a_task; + assign a = 1'b0; + deassign a; + do $display("do/while"); + while (a); + force a = 1'b1; + release a; + while(a) begin + $display("while"); + a = 1'b0; + end + repeat(2) $display("repeat"); + disable out_name; + forever begin + $display("forever"); + disable blk_name; // This one should not generate a warning + end + end + + initial #1 $display("Expect compile warnings!\nPASSED"); + + initial begin: out_name + #2 $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/always_star_array_lval.v b/ivtest/ivltests/always_star_array_lval.v new file mode 100644 index 000000000..69833a09d --- /dev/null +++ b/ivtest/ivltests/always_star_array_lval.v @@ -0,0 +1,32 @@ +// This test was written to catch spurious "internal error" messages generated +// by the compiler, so uses a gold file for checking. +module test(); + +reg [7:0] Reg[0:3]; + +reg [7:0] Val0 = 255; +reg [7:0] Val1 = 1; +reg [7:0] Val2 = 2; +reg [7:0] Val3 = 3; + +always @* begin + Reg[0] = Val0; + Reg[1] = Val1; + Reg[2] = Val2; + Reg[3] = Val3; +end + +initial begin + Val0 <= 0; // To make sure this triggers at T0 for SystemVerilog + #1 $display("%0d %0d %0d %0d", Reg[0], Reg[1], Reg[2], Reg[3]); + Val0 = 4; + #1 $display("%0d %0d %0d %0d", Reg[0], Reg[1], Reg[2], Reg[3]); + Val1 = 5; + #1 $display("%0d %0d %0d %0d", Reg[0], Reg[1], Reg[2], Reg[3]); + Val2 = 6; + #1 $display("%0d %0d %0d %0d", Reg[0], Reg[1], Reg[2], Reg[3]); + Val3 = 7; + #1 $display("%0d %0d %0d %0d", Reg[0], Reg[1], Reg[2], Reg[3]); +end + +endmodule diff --git a/ivtest/ivltests/analog1.v b/ivtest/ivltests/analog1.v new file mode 100644 index 000000000..6ee598622 --- /dev/null +++ b/ivtest/ivltests/analog1.v @@ -0,0 +1,42 @@ +nature Voltage; + units = "V"; + access = V; + idt_nature = Flux; + abstol = 1e-6; +endnature + +nature Flux; + units = "Wb"; + access = Phi; + ddt_nature = Voltage; + abstol = 1e-9; +endnature + +discipline voltage; + potential Voltage; +enddiscipline + + +module main; + + real value; + voltage out; + analog V(out) <+ abs(value); + + initial begin + value = 1.0; + #1 if (V(out) != abs(value)) begin + $display("FAILED -- value=%g, res=%g", value, V(out)); + $finish; + end + + value = -1.0; + #1 if (V(out) != abs(value)) begin + $display("FAILED -- value=%g, res=%f", value, V(out)); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/analog2.v b/ivtest/ivltests/analog2.v new file mode 100644 index 000000000..83d25481b --- /dev/null +++ b/ivtest/ivltests/analog2.v @@ -0,0 +1,52 @@ +nature Voltage; + units = "V"; + access = V; + idt_nature = Flux; + abstol = 1e-6; +endnature + +discipline voltage; + potential Voltage; +enddiscipline + +nature Flux; + units = "Wb"; + access = Phi; + ddt_nature = Voltage; + abstol = 1e-9; +endnature + +`timescale 1s/1s +module main; + + real value; + voltage in, out; + analog V(out) <+ transition(value, 0, 4); + + initial begin + value = 0.0; + #10 if (V(out) != value) begin + $display("FAILED -- value=%g, res=%g", value, V(out)); + $finish; + end + + // Halfway through the rise time, the output should have + // half the input. + value = 2.0; + //#2 if (V(out) != value/2) begin + #2 if (abs(V(out) - value/2) > 1e-6) begin + $display("FAILED -- value=%g, value/2=%g, res=%f", value, value/2, V(out)); + $finish; + end + + // After the full transition time, the output should match + // the input. + #2 if (V(out) != value) begin + $display("FAILED -- value=%g, res=%f", value, V(out)); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/andnot1.v b/ivtest/ivltests/andnot1.v new file mode 100644 index 000000000..6594d56b0 --- /dev/null +++ b/ivtest/ivltests/andnot1.v @@ -0,0 +1,48 @@ +`begin_keywords "1364-2005" +/* + * Copyright (c) 2005 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* andnot1.v + * This tests types. + */ +module main; + + reg a, b, c; + + wire d = a & !b; // change from !b to ~b and everything is fine + reg [2:0] tmp; + reg ref; + initial begin + // Do an exaustive scan of the possible values. + for (tmp = 0 ; tmp < 4 ; tmp = tmp + 1) begin + a = tmp[0]; + b = tmp[1]; + c = a & ~b; + #1 if (c != d) begin + $display("FAILED -- a=%b, b=%b, c=%b, d=%b", + a, b, c, d); + $finish; + end + end // for (tmp = 0 ; tmp < 4 ; tmp = tmp + 1) + + $display("PASSED"); + end + +endmodule // main +`end_keywords diff --git a/ivtest/ivltests/arith-unknown.v b/ivtest/ivltests/arith-unknown.v new file mode 100644 index 000000000..dae28f27e --- /dev/null +++ b/ivtest/ivltests/arith-unknown.v @@ -0,0 +1,32 @@ +// Ensure the compiler doesn't perform some invalid optimisations. + +module test(); + +reg [3:0] unknown; +reg [3:0] result; + +reg failed; + +initial begin + failed = 0; + unknown = 4'bx101; + result = unknown + 0; + $display("%b", result); + if (result !== 4'bxxxx) failed = 1; + result = (unknown >> 1) + 0; + $display("%b", result); + if (result !== 4'bxxxx) failed = 1; + result = unknown - 0; + $display("%b", result); + if (result !== 4'bxxxx) failed = 1; + result = unknown * 0; + $display("%b", result); + if (result !== 4'bxxxx) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/array4.v b/ivtest/ivltests/array4.v new file mode 100644 index 000000000..111bf73ff --- /dev/null +++ b/ivtest/ivltests/array4.v @@ -0,0 +1,31 @@ +module test; + + parameter width = 16; + localparam count = 1< into a constant array select. + // This is needed to make the following work as expected. + $dumpfile("work/array_dump.vcd"); + for (lp = 0; lp < 3; lp = lp+1) $dumpvars(0, array[lp]); + #1; + array[0] = 8'hff; + array[1] = 8'h00; + array[2] = 8'h55; + end +endmodule diff --git a/ivtest/ivltests/array_lval_select1.v b/ivtest/ivltests/array_lval_select1.v new file mode 100644 index 000000000..984f6391c --- /dev/null +++ b/ivtest/ivltests/array_lval_select1.v @@ -0,0 +1,123 @@ +// Check behaviour with out-of-range and undefined array indices +// on LHS of blocking procedural assignment. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + +reg array1[2:1]; +reg array2[1:0]; + +`ifndef VLOG95 +real array3[2:1]; +real array4[1:0]; +`endif + +integer index; + +reg failed; + +initial begin + failed = 0; + + array1[1] = 1'b0; + array1[2] = 1'b0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array1[0] = 1'b1; // Constant out of bounds select may be an error +`endif + $display("array = %b %b", array1[2], array1[1]); + if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1; + + array1[1] = 1'b0; + array1[2] = 1'b0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array1[3] = 1'b1; // Constant out of bounds select may be an error +`endif + $display("array = %b %b", array1[2], array1[1]); + if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1; + + array2[0] = 1'b0; + array2[1] = 1'b0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array2['bx] = 1'b1; // Constant undefined out of bounds select may be an error +`endif + $display("array = %b %b", array2[1], array2[0]); + if ((array2[0] !== 1'b0) || (array2[1] !== 1'b0)) failed = 1; + + index = 0; + array1[1] = 1'b0; + array1[2] = 1'b0; + array1[index] = 1'b1; + $display("array = %b %b", array1[2], array1[1]); + if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1; + + index = 3; + array1[1] = 1'b0; + array1[2] = 1'b0; + array1[index] = 1'b1; + $display("array = %b %b", array1[2], array1[1]); + if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1; + + index = 'bx; + array2[0] = 1'b0; + array2[1] = 1'b0; + array2[index] = 1'b1; + $display("array = %b %b", array2[1], array2[0]); + if ((array2[0] !== 1'b0) || (array2[1] !== 1'b0)) failed = 1; + +`ifndef VLOG95 + array3[1] = 0.0; + array3[2] = 0.0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array3[0] = 1.0; // Constant out of bounds select may be an error +`endif + $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + array3[1] = 0.0; + array3[2] = 0.0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array3[3] = 1.0; // Constant out of bounds select may be an error +`endif + $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + array4[0] = 0.0; + array4[1] = 0.0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array4['bx] = 1.0; // Constant undefined out of bounds select may be an error +`endif + $display("array = %0g %0g", array4[1], array4[0]); + if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1; + + index = 0; + array3[1] = 0.0; + array3[2] = 0.0; + array3[index] = 1.0; + $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + index = 3; + array3[1] = 0.0; + array3[2] = 0.0; + array3[index] = 1.0; + $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + index = 'bx; + array4[0] = 0.0; + array4[1] = 0.0; + array4[index] = 1.0; + $display("array = %0g %0g", array4[1], array4[0]); + if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1; +`endif + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/array_lval_select2.v b/ivtest/ivltests/array_lval_select2.v new file mode 100644 index 000000000..8fb3a5e22 --- /dev/null +++ b/ivtest/ivltests/array_lval_select2.v @@ -0,0 +1,123 @@ +// Check behaviour with out-of-range and undefined array indices +// on LHS of non-blocking procedural assignment. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + +reg array1[2:1]; +reg array2[1:0]; + +`ifndef VLOG95 +real array3[2:1]; +real array4[1:0]; +`endif + +integer index; + +reg failed; + +initial begin + failed = 0; + + array1[1] <= 1'b0; + array1[2] <= 1'b0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array1[0] <= 1'b1; // Constant out of bounds select may be an error +`endif + #1 $display("array = %b %b", array1[2], array1[1]); + if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1; + + array1[1] <= 1'b0; + array1[2] <= 1'b0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array1[3] <= 1'b1; // Constant out of bounds select may be an error +`endif + #1 $display("array = %b %b", array1[2], array1[1]); + if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1; + + array2[0] <= 1'b0; + array2[1] <= 1'b0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array2['bx] <= 1'b1; // Constant undefined out of bounds select may be an error +`endif + #1 $display("array = %b %b", array2[1], array2[0]); + if ((array2[0] !== 1'b0) || (array2[1] !== 1'b0)) failed = 1; + + index = 0; + array1[1] <= 1'b0; + array1[2] <= 1'b0; + array1[index] <= 1'b1; + #1 $display("array = %b %b", array1[2], array1[1]); + if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1; + + index = 3; + array1[1] <= 1'b0; + array1[2] <= 1'b0; + array1[index] <= 1'b1; + #1 $display("array = %b %b", array1[2], array1[1]); + if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1; + + index = 'bx; + array2[0] <= 1'b0; + array2[1] <= 1'b0; + array2[index] <= 1'b1; + #1 $display("array = %b %b", array2[1], array2[0]); + if ((array2[0] !== 1'b0) || (array2[1] !== 1'b0)) failed = 1; + +`ifndef VLOG95 + array3[1] <= 0.0; + array3[2] <= 0.0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array3[0] <= 1.0; // Constant out of bounds select may be an error +`endif + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + array3[1] <= 0.0; + array3[2] <= 0.0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array3[3] <= 1.0; // Constant out of bounds select may be an error +`endif + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + array4[0] <= 0.0; + array4[1] <= 0.0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + array4['bx] <= 1.0; // Constant undefined out of bounds select may be an error +`endif + #1 $display("array = %0g %0g", array4[1], array4[0]); + if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1; + + index = 0; + array3[1] <= 0.0; + array3[2] <= 0.0; + array3[index] <= 1.0; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + index = 3; + array3[1] <= 0.0; + array3[2] <= 0.0; + array3[index] <= 1.0; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + + index = 'bx; + array4[0] <= 0.0; + array4[1] <= 0.0; + array4[index] <= 1.0; + #1 $display("array = %0g %0g", array4[1], array4[0]); + if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1; +`endif + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/array_lval_select3a.v b/ivtest/ivltests/array_lval_select3a.v new file mode 100644 index 000000000..655c820b0 --- /dev/null +++ b/ivtest/ivltests/array_lval_select3a.v @@ -0,0 +1,113 @@ +// Check behaviour with out-of-range and undefined array indices +// on LHS of procedural continuous (reg) assignment. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + +reg [1:0] array1[2:1]; +reg [1:0] array2[1:0]; + +reg [1:0] var1; + +`ifndef VLOG95 +real array3[2:1]; +real array4[1:0]; + +real var2; +`endif + +reg failed; + +initial begin + failed = 0; + + array1[1] = 2'd0; + array1[2] = 2'd0; + + array2[0] = 2'd0; + array2[1] = 2'd0; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array1[0] = 2'd1; + #1 $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd0) || (array1[2] !== 2'd0)) failed = 1; + deassign array1[0]; +`endif + + assign array1[1] = 2'd1; + #1 $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd1) || (array1[2] !== 2'd0)) failed = 1; + deassign array1[1]; + + assign array1[2] = var1; + var1 = 2'd1; + #1 $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd0) || (array1[2] !== 2'd1)) failed = 1; + var1 = 2'd2; + #1 $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd0) || (array1[2] !== 2'd2)) failed = 1; + deassign array1[2]; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array1[3] = var1; + #1 $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd0) || (array1[2] !== 2'd0)) failed = 1; + deassign array1[3]; + + assign array2['bx] = 2'd1; + #1 $display("array = %h %h", array2[1], array2[0]); + if ((array2[0] !== 2'd0) || (array2[1] !== 2'd0)) failed = 1; + deassign array2['bx]; +`endif + +`ifndef VLOG95 + array3[1] = 0.0; + array3[2] = 0.0; + + array4[0] = 0.0; + array4[1] = 0.0; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array3[0] = 1.0; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + deassign array3[0]; +`endif + + assign array3[1] = 1.0; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 1.0) || (array3[2] != 0.0)) failed = 1; + deassign array3[1]; + + assign array3[2] = var2; + var2 = 1.0; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 1.0)) failed = 1; + var2 = 2.0; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 2.0)) failed = 1; + deassign array3[2]; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array3[3] = var2; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + deassign array3[3]; + + assign array4['bx] = 1.0; + #1 $display("array = %0g %0g", array4[1], array4[0]); + if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1; + deassign array4['bx]; +`endif +`endif + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/array_lval_select3b.v b/ivtest/ivltests/array_lval_select3b.v new file mode 100644 index 000000000..ca9333755 --- /dev/null +++ b/ivtest/ivltests/array_lval_select3b.v @@ -0,0 +1,14 @@ +// Check behaviour with variable array indices on LHS of procedural +// continuous (reg) assignment. This should be rejected by the compiler. +module top; + +reg array1[2:1]; + +integer index = 1; + +initial begin + assign array1[index] = 1'b1; + deassign array1[index]; +end + +endmodule diff --git a/ivtest/ivltests/array_lval_select3c.v b/ivtest/ivltests/array_lval_select3c.v new file mode 100644 index 000000000..2c8a3b8d6 --- /dev/null +++ b/ivtest/ivltests/array_lval_select3c.v @@ -0,0 +1,117 @@ +// Check behaviour with out-of-range and undefined array indices +// on LHS of procedural continuous (reg) assignment. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + +reg [1:0] array1[2:1]; +reg [1:0] array2[1:0]; + +reg [1:0] var1; + +`ifndef VLOG95 +real array3[2:1]; +real array4[1:0]; + +real var2; +`endif + +reg failed; + +initial begin + failed = 0; + + array1[1] = 2'd0; + array1[2] = 2'd0; + + array2[0] = 2'd0; + array2[1] = 2'd0; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array1[0] = 2'd1; + #1 $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd0) || (array1[2] !== 2'd0)) failed = 1; + deassign array1[0]; +`endif + +/* This is not supported at present + assign array1[1] = 2'd1; + #1 $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd1) || (array1[2] !== 2'd0)) failed = 1; + deassign array1[1]; + + assign array1[2] = var1; + var1 = 2'd1; + #1 $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd0) || (array1[2] !== 2'd1)) failed = 1; + var1 = 2'd2; + #1 $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd0) || (array1[2] !== 2'd2)) failed = 1; + deassign array1[2]; +*/ + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array1[3] = var1; + #1 $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd0) || (array1[2] !== 2'd0)) failed = 1; + deassign array1[3]; + + assign array2['bx] = 2'd1; + #1 $display("array = %h %h", array2[1], array2[0]); + if ((array2[0] !== 2'd0) || (array2[1] !== 2'd0)) failed = 1; + deassign array2['bx]; +`endif + +`ifndef VLOG95 + array3[1] = 0.0; + array3[2] = 0.0; + + array4[0] = 0.0; + array4[1] = 0.0; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array3[0] = 1.0; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + deassign array3[0]; +`endif + +/* This is not supported at present + assign array3[1] = 1.0; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 1.0) || (array3[2] != 0.0)) failed = 1; + deassign array3[1]; + + assign array3[2] = var2; + var2 = 1.0; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 1.0)) failed = 1; + var2 = 2.0; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 2.0)) failed = 1; + deassign array3[2]; +*/ + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign array3[3] = var2; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + deassign array3[3]; + + assign array4['bx] = 1.0; + #1 $display("array = %0g %0g", array4[1], array4[0]); + if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1; + deassign array4['bx]; +`endif +`endif + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/array_lval_select4a.v b/ivtest/ivltests/array_lval_select4a.v new file mode 100644 index 000000000..8b5e7090c --- /dev/null +++ b/ivtest/ivltests/array_lval_select4a.v @@ -0,0 +1,110 @@ +// Check behaviour with out-of-range and undefined array indices +// on LHS of procedural continuous (net) assignment. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + `define SUPPORT_REAL_NETS_IN_IVTEST +`endif + +module top; + +wire [1:0] array1[2:1]; +wire [1:0] array2[1:0]; + +reg [1:0] var1; + +assign array1[1] = 2'd0; +assign array1[2] = 2'd0; + +assign array2[0] = 2'd0; +assign array2[1] = 2'd0; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +wire real array3[2:1]; +wire real array4[1:0]; + +real var2; + +assign array3[1] = 0.0; +assign array3[2] = 0.0; + +assign array4[0] = 0.0; +assign array4[1] = 0.0; +`endif + +reg failed; + +initial begin + failed = 0; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + force array1[0] = 2'd1; + #1 $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd0) || (array1[2] !== 2'd0)) failed = 1; + release array1[0]; +`endif + + force array1[1] = 2'd1; + #1 $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd1) || (array1[2] !== 2'd0)) failed = 1; + release array1[1]; + + force array1[2] = var1; + var1 = 2'd1; + #1 $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd0) || (array1[2] !== 2'd1)) failed = 1; + var1 = 2'd2; + #1 $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd0) || (array1[2] !== 2'd2)) failed = 1; + release array1[2]; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + force array1[3] = var1; + #1 $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd0) || (array1[2] !== 2'd0)) failed = 1; + release array1[3]; + + force array2['bx] = 2'd1; + #1 $display("array = %h %h", array2[1], array2[0]); + if ((array2[0] !== 2'd0) || (array2[1] !== 2'd0)) failed = 1; + release array2['bx]; +`endif + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST + force array3[0] = 1.0; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + release array3[0]; + + force array3[1] = 1.0; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 1.0) || (array3[2] != 0.0)) failed = 1; + release array3[1]; + + force array3[2] = var2; + var2 = 1.0; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 1.0)) failed = 1; + var2 = 2.0; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 2.0)) failed = 1; + release array3[2]; + + force array3[3] = var2; + #1 $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1; + release array3[3]; + + force array4['bx] = 1.0; + #1 $display("array = %0g %0g", array4[1], array4[0]); + if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1; + release array4['bx]; +`endif + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/array_lval_select4b.v b/ivtest/ivltests/array_lval_select4b.v new file mode 100644 index 000000000..d0915ef66 --- /dev/null +++ b/ivtest/ivltests/array_lval_select4b.v @@ -0,0 +1,14 @@ +// Check behaviour with variable array indices on LHS of procedural +// continuous (net) assignment. This should be rejected by the compiler. +module top; + +wire array1[2:1]; + +integer index = 1; + +initial begin + force array1[index] = 1'b1; + release array1[index]; +end + +endmodule diff --git a/ivtest/ivltests/array_lval_select5.v b/ivtest/ivltests/array_lval_select5.v new file mode 100644 index 000000000..809bb19b9 --- /dev/null +++ b/ivtest/ivltests/array_lval_select5.v @@ -0,0 +1,68 @@ +// Check behaviour with out-of-range and undefined array indices +// on LHS of continuous assignment. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + `define SUPPORT_REAL_NETS_IN_IVTEST +`endif + +module top; + +wire [1:0] array1[2:1]; +wire [1:0] array2[1:0]; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +assign array1[0] = 2'd0; +`endif +assign array1[1] = 2'd1; +assign array1[2] = 2'd2; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +assign array1[3] = 2'd3; +`endif + +assign array2[0] = 2'd0; +assign array2[1] = 2'd1; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +assign array2['bx] = 2'd2; +`endif + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +wire real array3[2:1]; +wire real array4[1:0]; + +assign array3[0] = 0.0; +assign array3[1] = 1.0; +assign array3[2] = 2.0; +assign array3[3] = 3.0; + +assign array4[0] = 0.0; +assign array4[1] = 1.0; +assign array4['bx] = 2.0; +`endif + +reg failed; + +initial begin + #1 failed = 0; + + $display("array = %h %h", array1[2], array1[1]); + if ((array1[1] !== 2'd1) || (array1[2] !== 2'd2)) failed = 1; + + $display("array = %h %h", array2[1], array2[0]); + if ((array2[0] !== 2'd0) || (array2[1] !== 2'd1)) failed = 1; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST + $display("array = %0g %0g", array3[2], array3[1]); + if ((array3[1] != 1.0) || (array3[2] != 2.0)) failed = 1; + + $display("array = %0g %0g", array4[1], array4[0]); + if ((array4[0] != 0.0) || (array4[1] != 1.0)) failed = 1; +`endif + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/array_lval_select6.v b/ivtest/ivltests/array_lval_select6.v new file mode 100644 index 000000000..a22602a4f --- /dev/null +++ b/ivtest/ivltests/array_lval_select6.v @@ -0,0 +1,128 @@ +// tests using array elements as indices/selects in an array lval select +`timescale 1ns/100ps +module tb; + +reg [7:0] a[7:0]; +real r[7:0]; +wire [2:0] idx[7:0]; + +genvar g; +for (g = 0; g < 8; g=g+1) + assign idx[g] = g; + +reg pass; +integer i; +initial begin + pass = 1'b1; + + // zero everything out + for (i = 0; i < 8; i = i + 1) begin + a[i] = 8'h0; + r[i] = 0.0; + end + + // test using one in a part select + a[1][idx[1]*4 +: 4] = 4'ha; + if (a[1] != 8'ha0) begin + $display("FAILED part select, expected a0, got %x", a[1]); + pass = 1'b0; + end + + // test using one in an index + a[idx[2]] = 8'hbc; + if (a[2] != 8'hbc) begin + $display("FAILED word index, expected bc, got %x", a[2]); + pass = 1'b0; + end + + // and now both... + a[idx[3]][idx[0]*4 +: 4] = 4'hd; + if (a[3] != 8'h0d) begin + $display("FAILED word index and part select, expected 0d, got %x", a[3]); + pass = 1'b0; + end + + // non-blocking, in part select + a[4][idx[1]*4 +: 4] <= 4'he; + if (a[4] != 8'h00) begin + $display("FAILED NB assign with part select 1, expected 00, got %x", a[4]); + pass = 1'b0; + end + #0.1; + if (a[4] != 8'he0) begin + $display("FAILED NB assign with part select 2, expected e0, got %x", a[4]); + pass = 1'b0; + end + + // non-blocking, in index + a[idx[5]] <= 8'h12; + if (a[5] != 8'h00) begin + $display("FAILED NB assign with word index 1, expected 00, got %x", a[4]); + pass = 1'b0; + end + #0.1; + if (a[5] != 8'h12) begin + $display("FAILED NB assign with word index 2, expected 12, got %x", a[4]); + pass = 1'b0; + end + + // non-blocking, index and part select + a[idx[6]][idx[0]*4 +: 4] <= 4'h3; + if (a[6] != 8'h00) begin + $display("FAILED NB assign with both 1, expected 00, got %x", a[4]); + pass = 1'b0; + end + #0.1; + if (a[6] != 8'h03) begin + $display("FAILED NB assign with both 2, expected 03, got %x", a[4]); + pass = 1'b0; + end + + // NB, both, with a delay + a[idx[7]][idx[1]*4 +: 4] <= #(idx[1]) 4'h4; + #0.1; + if (a[7] != 8'h00) begin + $display("FAILED NB assign with both and delay 1, expected 00, got %x", a[4]); + pass = 1'b0; + end + #1.1; + if (a[7] != 8'h40) begin + $display("FAILED NB assign with both and delay 2, expected 40, got %x", a[4]); + pass = 1'b0; + end + + // real array index + r[idx[0]] = 1.1; + if (r[0] != 1.1) begin + $display("FAILED real word, expected 1.0, got %f", r[0]); + pass = 1'b0; + end + + // NB to real array + r[idx[1]] <= 2.2; + if (r[1] != 0.0) begin + $display("FAILED NB assign real word 1, expected 0.0 got %f", r[1]); + pass = 1'b0; + end + #0.1; + if (r[1] != 2.2) begin + $display("FAILED NB assign real word 2, expected 2.2 got %f", r[1]); + pass = 1'b0; + end + + // NB to real array with delay + r[idx[2]] <= #(idx[2]) 3.3; + #1.1; + if (r[2] != 0.0) begin + $display("FAILED NB assign with delay to real word 1, expected 0.0 got %f", r[1]); + pass = 1'b0; + end + #1.0; + if (r[2] != 3.3) begin + $display("FAILED NB assign with delay to real word 2, expected 3.3 got %f", r[1]); + pass = 1'b0; + end + + if (pass) $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/array_packed.v b/ivtest/ivltests/array_packed.v new file mode 100644 index 000000000..f84213381 --- /dev/null +++ b/ivtest/ivltests/array_packed.v @@ -0,0 +1,86 @@ +// Check that packed arrays of all sorts get elaborated without an error and +// that the resulting type has the right packed width. + +module test; + +typedef bit bit2; +typedef logic [1:0] vector; + +bit2 [1:0] b; +vector [2:0] l; + +typedef enum logic [7:0] { + A +} E; + +typedef E [1:0] EP; +typedef EP [2:0] EPP; + +E e; +EP ep1; +E [1:0] ep2; +EP [2:0] epp1; +EPP epp2; +EPP [3:0] eppp; + +typedef struct packed { + longint x; +} S1; + +typedef struct packed { + time t; + integer i; + + logic [1:0] x; + bit [3:0] y; + int z; + shortint w; + + E e; + EP ep; + + S1 s; +} S2; + +localparam S_SIZE = 64 + 32 + 2 + 4 + 32 + 16 + 8 + 8*2 + 64; + +typedef S2 [3:0] SP; +typedef SP [9:0] SPP; + +S2 s; +SP sp1; +S2 [3:0] sp2; +SP [9:0] spp1; +SPP spp2; +SPP [1:0] sppp; + +bit failed = 1'b0; + +initial begin + // Packed arrays of basic types + failed |= $bits(b) !== 2; + failed |= $bits(l) !== 2 * 3; + + // Packed arrays of enums + failed |= $bits(e) !== 8; + failed |= $bits(ep1) !== $bits(e) * 2; + failed |= $bits(ep2) !== $bits(ep1); + failed |= $bits(epp1) !== $bits(ep1) * 3; + failed |= $bits(epp2) !== $bits(epp1); + failed |= $bits(eppp) !== $bits(epp1) * 4; + + // Packed arrays of structs + failed |= $bits(s) !== S_SIZE; + failed |= $bits(sp1) != $bits(s) * 4; + failed |= $bits(sp2) != $bits(sp1); + failed |= $bits(spp1) != $bits(sp1) * 10; + failed |= $bits(spp1) != $bits(spp2); + failed |= $bits(sppp) != $bits(spp1) * 2; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/array_packed_2d.v b/ivtest/ivltests/array_packed_2d.v new file mode 100644 index 000000000..5139ec738 --- /dev/null +++ b/ivtest/ivltests/array_packed_2d.v @@ -0,0 +1,106 @@ +// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test different ways of accessing a 2D packed array. + +module array_packed_2d(); + +reg [1:4][7:0] vec; +reg [4:1][7:0] vec2; +integer i; + +initial begin +// test 1: assign using variable index +for(i = 1; i <= 4; i = i + 1) + vec[i] = i * 2; + +// display whole vector +$display("%h", vec); + +// $display using variable index +for(i = 1; i <= 4; i = i + 1) + $display(vec[i]); + +// $display using constant index +$display(vec[1]); +$display(vec[2]); +$display(vec[3]); +$display(vec[4]); + + +// test 2: assign using a constant index +vec[1] = 2; +vec[2] = 4; +vec[3] = 6; +vec[4] = 8; + +// display whole vector +$display("%h", vec); + +// $display using variable index +for(i = 1; i <= 4; i = i + 1) + $display(vec[i]); + +// $display using constant index +$display(vec[1]); +$display(vec[2]); +$display(vec[3]); +$display(vec[4]); + +////////////////////////////////////////// + +// test 1: assign using variable index +for(i = 1; i <= 4; i = i + 1) + vec2[i] = i * 2; + +// display whole vector +$display("%h", vec2); + +// $display using variable index +for(i = 1; i <= 4; i = i + 1) + $display(vec2[i]); + +// $display using constant index +$display(vec2[1]); +$display(vec2[2]); +$display(vec2[3]); +$display(vec2[4]); + + +// test 2: assign using a constant index +vec2[1] = 2; +vec2[2] = 4; +vec2[3] = 6; +vec2[4] = 8; + +// display whole vector +$display("%h", vec2); + +// $display using variable index +for(i = 1; i <= 4; i = i + 1) + $display(vec2[i]); + +// $display using constant index +$display(vec2[1]); +$display(vec2[2]); +$display(vec2[3]); +$display(vec2[4]); +end + +endmodule diff --git a/ivtest/ivltests/array_packed_sysfunct.v b/ivtest/ivltests/array_packed_sysfunct.v new file mode 100644 index 000000000..76e6b62f7 --- /dev/null +++ b/ivtest/ivltests/array_packed_sysfunct.v @@ -0,0 +1,103 @@ +// This tests system functions operationg on packed arrays +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test (); + + // parameters for array sizes + localparam WA = 4; + localparam WB = 6; + localparam WC = 8; + + function int wdt (input int i); + wdt = 2 + 2*i; + endfunction + + // 2D packed arrays + logic [WA-1:0] [WB-1:0] [WC-1:0] abg; // big endian array + logic [0:WA-1] [0:WB-1] [0:WC-1] alt; // little endian array + + // error counter + bit err = 0; + + // indexing variable + int i; + + initial begin + // big endian + + // full array + if ($dimensions(abg) != 3) begin $display("FAILED -- $dimensions(abg) = %0d", $dimensions(abg)); err=1; end; + if ($bits (abg) != WA*WB*WC) begin $display("FAILED -- $bits (abg) = %0d", $bits (abg)); err=1; end; + for (i=1; i<=3; i=i+1) begin + if ($left (abg , i) != wdt(i )-1) begin $display("FAILED -- $left (abg , %0d) = %0d", i, $left (abg , i)); err=1; end; + if ($right (abg , i) != 0 ) begin $display("FAILED -- $right (abg , %0d) = %0d", i, $right (abg , i)); err=1; end; + if ($low (abg , i) != 0 ) begin $display("FAILED -- $low (abg , %0d) = %0d", i, $low (abg , i)); err=1; end; + if ($high (abg , i) != wdt(i )-1) begin $display("FAILED -- $high (abg , %0d) = %0d", i, $high (abg , i)); err=1; end; + if ($increment(abg , i) != 1 ) begin $display("FAILED -- $increment(abg , %0d) = %0d", i, $increment(abg , i)); err=1; end; + if ($size (abg , i) != wdt(i ) ) begin $display("FAILED -- $size (abg , %0d) = %0d", i, $size (abg , i)); err=1; end; + end + // half array + if ($dimensions(abg[1:0]) != 3) begin $display("FAILED -- $dimensions(abg[1:0]) = %0d", $dimensions(abg[1:0])); err=1; end; + if ($bits (abg[1:0]) != 2*WB*WC) begin $display("FAILED -- $bits (abg[1:0]) = %0d", $bits (abg[1:0])); err=1; end; + for (i=1; i<=3; i=i+1) begin + if ($left (abg[1:0], i) != wdt(i )-1) begin $display("FAILED -- $left (abg[1:0], %0d) = %0d", i, $left (abg[1:0], i)); err=1; end; + if ($right (abg[1:0], i) != 0 ) begin $display("FAILED -- $right (abg[1:0], %0d) = %0d", i, $right (abg[1:0], i)); err=1; end; + if ($low (abg[1:0], i) != 0 ) begin $display("FAILED -- $low (abg[1:0], %0d) = %0d", i, $low (abg[1:0], i)); err=1; end; + if ($high (abg[1:0], i) != wdt(i )-1) begin $display("FAILED -- $high (abg[1:0], %0d) = %0d", i, $high (abg[1:0], i)); err=1; end; + if ($increment(abg[1:0], i) != 1 ) begin $display("FAILED -- $increment(abg[1:0], %0d) = %0d", i, $increment(abg[1:0], i)); err=1; end; + if ($size (abg[1:0], i) != wdt(i ) ) begin $display("FAILED -- $size (abg[1:0], %0d) = %0d", i, $size (abg[1:0], i)); err=1; end; + end + // single array element + if ($dimensions(abg[0]) != 2) begin $display("FAILED -- $dimensions(abg[0]) = %0d", $dimensions(abg[0])); err=1; end; + if ($bits (abg[0]) != WB*WC) begin $display("FAILED -- $bits (abg[0]) = %0d", $bits (abg[0])); err=1; end; + for (i=1; i<=2; i=i+1) begin + if ($left (abg[0] , i) != wdt(i+1)-1) begin $display("FAILED -- $left (abg[0] , %0d) = %0d", i, $left (abg[0] , i)); err=1; end; + if ($right (abg[0] , i) != 0 ) begin $display("FAILED -- $right (abg[0] , %0d) = %0d", i, $right (abg[0] , i)); err=1; end; + if ($low (abg[0] , i) != 0 ) begin $display("FAILED -- $low (abg[0] , %0d) = %0d", i, $low (abg[0] , i)); err=1; end; + if ($high (abg[0] , i) != wdt(i+1)-1) begin $display("FAILED -- $high (abg[0] , %0d) = %0d", i, $high (abg[0] , i)); err=1; end; + if ($increment(abg[0] , i) != 1 ) begin $display("FAILED -- $increment(abg[0] , %0d) = %0d", i, $increment(abg[0] , i)); err=1; end; + if ($size (abg[0] , i) != wdt(i+1) ) begin $display("FAILED -- $size (abg[0] , %0d) = %0d", i, $size (abg[0] , i)); err=1; end; + end + + // little endian + + // full array + if ($dimensions(alt) != 3) begin $display("FAILED -- $dimensions(alt) = %0d", $dimensions(alt)); err=1; end; + if ($bits (alt) != WA*WB*WC) begin $display("FAILED -- $bits (alt) = %0d", $bits (alt)); err=1; end; + for (i=1; i<=3; i=i+1) begin + if ($left (alt , i) != 0 ) begin $display("FAILED -- $left (alt , %0d) = %0d", i, $left (alt , i)); err=1; end; + if ($right (alt , i) != wdt(i )-1) begin $display("FAILED -- $right (alt , %0d) = %0d", i, $right (alt , i)); err=1; end; + if ($low (alt , i) != 0 ) begin $display("FAILED -- $low (alt , %0d) = %0d", i, $low (alt , i)); err=1; end; + if ($high (alt , i) != wdt(i )-1) begin $display("FAILED -- $high (alt , %0d) = %0d", i, $high (alt , i)); err=1; end; + if ($increment(alt , i) != -1 ) begin $display("FAILED -- $increment(alt , %0d) = %0d", i, $increment(alt , i)); err=1; end; + if ($size (alt , i) != wdt(i ) ) begin $display("FAILED -- $size (alt , %0d) = %0d", i, $size (alt , i)); err=1; end; + end + // half array + if ($dimensions(alt[0:1]) != 3) begin $display("FAILED -- $dimensions(alt[0:1]) = %0d", $dimensions(alt[0:1])); err=1; end; + if ($bits (alt[0:1]) != 2*WB*WC) begin $display("FAILED -- $bits (alt[0:1]) = %0d", $bits (alt[0:1])); err=1; end; + for (i=1; i<=3; i=i+1) begin + if ($left (alt[0:1], i) != 0 ) begin $display("FAILED -- $left (alt[0:1], %0d) = %0d", i, $left (alt[0:1], i)); err=1; end; + if ($right (alt[0:1], i) != wdt(i )-1) begin $display("FAILED -- $right (alt[0:1], %0d) = %0d", i, $right (alt[0:1], i)); err=1; end; + if ($low (alt[0:1], i) != 0 ) begin $display("FAILED -- $low (alt[0:1], %0d) = %0d", i, $low (alt[0:1], i)); err=1; end; + if ($high (alt[0:1], i) != wdt(i )-1) begin $display("FAILED -- $high (alt[0:1], %0d) = %0d", i, $high (alt[0:1], i)); err=1; end; + if ($increment(alt[0:1], i) != -1 ) begin $display("FAILED -- $increment(alt[0:1], %0d) = %0d", i, $increment(alt[0:1], i)); err=1; end; + if ($size (alt[0:1], i) != wdt(i ) ) begin $display("FAILED -- $size (alt[0:1], %0d) = %0d", i, $size (alt[0:1], i)); err=1; end; + end + // single array element + if ($dimensions(alt[0]) != 2) begin $display("FAILED -- $dimensions(alt) = %0d", $dimensions(alt)); err=1; end; + if ($bits (alt[0]) != WB*WC) begin $display("FAILED -- $bits (alt) = %0d", $bits (alt)); err=1; end; + for (i=1; i<=2; i=i+1) begin + if ($left (alt[0] , i) != 0 ) begin $display("FAILED -- $left (alt[0] , %0d) = %0d", i, $left (alt[0] , i)); err=1; end; + if ($right (alt[0] , i) != wdt(i+1)-1) begin $display("FAILED -- $right (alt[0] , %0d) = %0d", i, $right (alt[0] , i)); err=1; end; + if ($low (alt[0] , i) != 0 ) begin $display("FAILED -- $low (alt[0] , %0d) = %0d", i, $low (alt[0] , i)); err=1; end; + if ($high (alt[0] , i) != wdt(i+1)-1) begin $display("FAILED -- $high (alt[0] , %0d) = %0d", i, $high (alt[0] , i)); err=1; end; + if ($increment(alt[0] , i) != -1 ) begin $display("FAILED -- $increment(alt[0] , %0d) = %0d", i, $increment(alt[0] , i)); err=1; end; + if ($size (alt[0] , i) != wdt(i+1) ) begin $display("FAILED -- $size (alt[0] , %0d) = %0d", i, $size (alt[0] , i)); err=1; end; + end + + if (!err) $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/array_packed_value_list.v b/ivtest/ivltests/array_packed_value_list.v new file mode 100644 index 000000000..73c63a18c --- /dev/null +++ b/ivtest/ivltests/array_packed_value_list.v @@ -0,0 +1,67 @@ +// This tests assigning value lists to packed arrays +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test (); + + // parameters for array sizes + localparam WA = 4; + localparam WB = 4; + + // 2D packed arrays + logic [WA-1:0] [WB-1:0] abg0, abg1, abg2, abg3, abg4, abg5, abg6, abg7, abg8, abg9; // big endian array + logic [0:WA-1] [0:WB-1] alt0, alt1, alt2, alt3, alt4, alt5, alt6, alt7, alt8, alt9; // little endian array + + // error counter + bit err = 0; + + initial begin + abg0 = '{ 3 ,2 ,1, 0 }; + abg1 = '{0:4, 1:5, 2:6, 3:7}; + abg2 = '{default:13}; + abg3 = '{2:15, default:13}; + abg4 = '{WA { {WB/2 {2'b10}} }}; + abg5 = '{WA { {3'b101, {WB/2-1{2'b10}}} }}; + abg6 = '{WA { {WB/2-1{2'b10}} }}; + abg7 [WA/2-1:0 ] = '{WA/2{ {WB/2 {2'b10}} }}; + abg8 [WA -1:WA/2] = '{WA/2{ {WB/2 {2'b01}} }}; + abg9 = '{err+0, err+1, err+2, err+3}; + // check + if (abg0 !== 16'b0011_0010_0001_0000) begin $display("FAILED -- abg0 = 'b%b", abg0); err=1; end + if (abg1 !== 16'b0111_0110_0101_0100) begin $display("FAILED -- abg1 = 'b%b", abg1); err=1; end + if (abg2 !== 16'b1101_1101_1101_1101) begin $display("FAILED -- abg2 = 'b%b", abg2); err=1; end + if (abg3 !== 16'b1101_1111_1101_1101) begin $display("FAILED -- abg3 = 'b%b", abg3); err=1; end + if (abg4 !== 16'b1010_1010_1010_1010) begin $display("FAILED -- abg4 = 'b%b", abg4); err=1; end + if (abg5 !== 16'b0110_0110_0110_0110) begin $display("FAILED -- abg5 = 'b%b", abg5); err=1; end + if (abg6 !== 16'b0010_0010_0010_0010) begin $display("FAILED -- abg6 = 'b%b", abg6); err=1; end + if (abg7 !== 16'bxxxx_xxxx_1010_1010) begin $display("FAILED -- abg7 = 'b%b", abg7); err=1; end + if (abg8 !== 16'b1010_1010_xxxx_xxxx) begin $display("FAILED -- abg8 = 'b%b", abg8); err=1; end + if (abg9 !== 16'b0000_0001_0010_0011) begin $display("FAILED -- abg9 = 'b%b", abg9); err=1; end + + alt0 = '{ 3 ,2 ,1, 0 }; + alt1 = '{0:4, 1:5, 2:6, 3:7}; + alt2 = '{default:13}; + alt3 = '{2:15, default:13}; + alt4 = '{WA { {WB/2 {2'b10}} }}; + alt5 = '{WA { {3'b101, {WB/2-1{2'b10}}} }}; + alt6 = '{WA { {WB/2-1{2'b10}} }}; + alt7 [0 :WA/2-1] = '{WA/2{ {WB/2 {2'b10}} }}; + alt8 [WA/2:WA -1] = '{WA/2{ {WB/2 {2'b01}} }}; + alt9 = '{err+0, err+1, err+2, err+3}; + // check + if (alt0 !== 16'b0011_0010_0001_0000) begin $display("FAILED -- alt0 = 'b%b", alt0); err=1; end + if (alt1 !== 16'b0100_0101_0110_0111) begin $display("FAILED -- alt1 = 'b%b", alt1); err=1; end + if (alt2 !== 16'b1101_1101_1101_1101) begin $display("FAILED -- alt2 = 'b%b", alt2); err=1; end + if (alt3 !== 16'b1101_1101_1111_1101) begin $display("FAILED -- alt3 = 'b%b", alt3); err=1; end + if (alt4 !== 16'b1010_1010_1010_1010) begin $display("FAILED -- alt4 = 'b%b", alt4); err=1; end + if (alt5 !== 16'b0110_0110_0110_0110) begin $display("FAILED -- alt5 = 'b%b", alt5); err=1; end + if (alt6 !== 16'b0010_0010_0010_0010) begin $display("FAILED -- alt6 = 'b%b", alt6); err=1; end + if (alt7 !== 16'b1010_1010_xxxx_xxxx) begin $display("FAILED -- alt7 = 'b%b", alt7); err=1; end + if (alt8 !== 16'bxxxx_xxxx_1010_1010) begin $display("FAILED -- alt8 = 'b%b", alt8); err=1; end + if (alt9 !== 16'b0000_0001_0010_0011) begin $display("FAILED -- alt9 = 'b%b", alt9); err=1; end + + if (!err) $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/array_packed_write_read.v b/ivtest/ivltests/array_packed_write_read.v new file mode 100644 index 000000000..88e3f1904 --- /dev/null +++ b/ivtest/ivltests/array_packed_write_read.v @@ -0,0 +1,314 @@ +// This tests unalligned write/read access to packed arrays +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test (); + + // parameters for array sizes + localparam WA = 4; + localparam WB = 4; + + // 2D packed array parameters +// localparam [WA-1:0] [WB-1:0] param_bg = {WA*WB{1'b1}}; + + // 2D packed arrays + logic [WA-1:0] [WB-1:0] abg0, abg1, abg2, abg3, abg4, abg5, abg6, abg7, abg8, abg9; // big endian array + logic [0:WA-1] [0:WB-1] alt0, alt1, alt2, alt3, alt4, alt5, alt6, alt7, alt8, alt9; // little endian array + logic [WA*WB:0] a1d0, a1d1, a1d2, a1d3, a1d4, a1d5, a1d6, a1d7, a1d8, a1d9; // 1D array + logic signed [WA-1:0] [WB-1:0] asg0, asg1, asg2, asg3, asg4, asg5, asg6, asg7, asg8, asg9; // signed big endian array + + // error counter + bit err = 0; + + initial begin + // test write to array LHS=RHS + abg0 = {WA*WB{1'bx}}; + abg1 = {WA*WB{1'bx}}; abg1 = {WA *WB +0{1'b1}}; + abg2 = {WA*WB{1'bx}}; abg2 [WA/2-1:0 ] = {WA/2*WB +0{1'b1}}; + abg3 = {WA*WB{1'bx}}; abg3 [WA -1:WA/2] = {WA/2*WB +0{1'b1}}; + abg4 = {WA*WB{1'bx}}; abg4 [ 0 ] = {1 *WB +0{1'b1}}; + abg5 = {WA*WB{1'bx}}; abg5 [WA -1 ] = {1 *WB +0{1'b1}}; + abg6 = {WA*WB{1'bx}}; abg6 [ 0 ][WB/2-1:0 ] = {1 *WB/2+0{1'b1}}; + abg7 = {WA*WB{1'bx}}; abg7 [WA -1 ][WB -1:WB/2] = {1 *WB/2+0{1'b1}}; + abg8 = {WA*WB{1'bx}}; abg8 [ 0 ][ 0 ] = {1 *1 +0{1'b1}}; + abg9 = {WA*WB{1'bx}}; abg9 [WA -1 ][WB -1 ] = {1 *1 +0{1'b1}}; + // check + if (abg0 !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- L=R -- abg0 = 'b%b", abg0); err=1; end + if (abg1 !== 16'b1111_1111_1111_1111) begin $display("FAILED -- L=R -- abg1 = 'b%b", abg1); err=1; end + if (abg2 !== 16'bxxxx_xxxx_1111_1111) begin $display("FAILED -- L=R -- abg2 = 'b%b", abg2); err=1; end + if (abg3 !== 16'b1111_1111_xxxx_xxxx) begin $display("FAILED -- L=R -- abg3 = 'b%b", abg3); err=1; end + if (abg4 !== 16'bxxxx_xxxx_xxxx_1111) begin $display("FAILED -- L=R -- abg4 = 'b%b", abg4); err=1; end + if (abg5 !== 16'b1111_xxxx_xxxx_xxxx) begin $display("FAILED -- L=R -- abg5 = 'b%b", abg5); err=1; end + if (abg6 !== 16'bxxxx_xxxx_xxxx_xx11) begin $display("FAILED -- L=R -- abg6 = 'b%b", abg6); err=1; end + if (abg7 !== 16'b11xx_xxxx_xxxx_xxxx) begin $display("FAILED -- L=R -- abg7 = 'b%b", abg7); err=1; end + if (abg8 !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- L=R -- abg8 = 'b%b", abg8); err=1; end + if (abg9 !== 16'b1xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- L=R -- abg9 = 'b%b", abg9); err=1; end + + // test write to array LHSR -- abg0 = 'b%b", abg0); err=1; end + if (abg1 !== 16'b0111_1111_1111_1111) begin $display("FAILED -- L>R -- abg1 = 'b%b", abg1); err=1; end + if (abg2 !== 16'bxxxx_xxxx_0111_1111) begin $display("FAILED -- L>R -- abg2 = 'b%b", abg2); err=1; end + if (abg3 !== 16'b0111_1111_xxxx_xxxx) begin $display("FAILED -- L>R -- abg3 = 'b%b", abg3); err=1; end + if (abg4 !== 16'bxxxx_xxxx_xxxx_0111) begin $display("FAILED -- L>R -- abg4 = 'b%b", abg4); err=1; end + if (abg5 !== 16'b0111_xxxx_xxxx_xxxx) begin $display("FAILED -- L>R -- abg5 = 'b%b", abg5); err=1; end + if (abg6 !== 16'bxxxx_xxxx_xxxx_xx01) begin $display("FAILED -- L>R -- abg6 = 'b%b", abg6); err=1; end + if (abg7 !== 16'b01xx_xxxx_xxxx_xxxx) begin $display("FAILED -- L>R -- abg7 = 'b%b", abg7); err=1; end + //if (abg8 !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- L>R -- abg8 = 'b%b", abg8); err=1; end + //if (abg9 !== 16'b1xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- L>R -- abg9 = 'b%b", abg9); err=1; end + + // test write to array LHS=RHS + alt0 = {WA*WB{1'bx}}; + alt1 = {WA*WB{1'bx}}; alt1 = {WA *WB +0{1'b1}}; + alt2 = {WA*WB{1'bx}}; alt2 [0 :WA/2-1] = {WA/2*WB +0{1'b1}}; + alt3 = {WA*WB{1'bx}}; alt3 [WA/2:WA -1] = {WA/2*WB +0{1'b1}}; + alt4 = {WA*WB{1'bx}}; alt4 [0 ] = {1 *WB +0{1'b1}}; + alt5 = {WA*WB{1'bx}}; alt5 [ WA -1] = {1 *WB +0{1'b1}}; + alt6 = {WA*WB{1'bx}}; alt6 [0 ][0 :WB/2-1] = {1 *WB/2+0{1'b1}}; + alt7 = {WA*WB{1'bx}}; alt7 [ WA -1][WB/2:WB -1] = {1 *WB/2+0{1'b1}}; + alt8 = {WA*WB{1'bx}}; alt8 [0 ][0 ] = {1 *1 +0{1'b1}}; + alt9 = {WA*WB{1'bx}}; alt9 [ WA -1][ WB -1] = {1 *1 +0{1'b1}}; + // check + if (alt0 !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- L=R -- alt0 = 'b%b", alt0); err=1; end + if (alt1 !== 16'b1111_1111_1111_1111) begin $display("FAILED -- L=R -- alt1 = 'b%b", alt1); err=1; end + if (alt2 !== 16'b1111_1111_xxxx_xxxx) begin $display("FAILED -- L=R -- alt2 = 'b%b", alt2); err=1; end + if (alt3 !== 16'bxxxx_xxxx_1111_1111) begin $display("FAILED -- L=R -- alt3 = 'b%b", alt3); err=1; end + if (alt4 !== 16'b1111_xxxx_xxxx_xxxx) begin $display("FAILED -- L=R -- alt4 = 'b%b", alt4); err=1; end + if (alt5 !== 16'bxxxx_xxxx_xxxx_1111) begin $display("FAILED -- L=R -- alt5 = 'b%b", alt5); err=1; end + if (alt6 !== 16'b11xx_xxxx_xxxx_xxxx) begin $display("FAILED -- L=R -- alt6 = 'b%b", alt6); err=1; end + if (alt7 !== 16'bxxxx_xxxx_xxxx_xx11) begin $display("FAILED -- L=R -- alt7 = 'b%b", alt7); err=1; end + if (alt8 !== 16'b1xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- L=R -- alt8 = 'b%b", alt8); err=1; end + if (alt9 !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- L=R -- alt9 = 'b%b", alt9); err=1; end + + // test write to array LHSR -- alt0 = 'b%b", alt0); err=1; end + if (alt1 !== 16'b0111_1111_1111_1111) begin $display("FAILED -- L>R -- alt1 = 'b%b", alt1); err=1; end + if (alt2 !== 16'b0111_1111_xxxx_xxxx) begin $display("FAILED -- L>R -- alt2 = 'b%b", alt2); err=1; end + if (alt3 !== 16'bxxxx_xxxx_0111_1111) begin $display("FAILED -- L>R -- alt3 = 'b%b", alt3); err=1; end + if (alt4 !== 16'b0111_xxxx_xxxx_xxxx) begin $display("FAILED -- L>R -- alt4 = 'b%b", alt4); err=1; end + if (alt5 !== 16'bxxxx_xxxx_xxxx_0111) begin $display("FAILED -- L>R -- alt5 = 'b%b", alt5); err=1; end + if (alt6 !== 16'b01xx_xxxx_xxxx_xxxx) begin $display("FAILED -- L>R -- alt6 = 'b%b", alt6); err=1; end + if (alt7 !== 16'bxxxx_xxxx_xxxx_xx01) begin $display("FAILED -- L>R -- alt7 = 'b%b", alt7); err=1; end + //if (alt8 !== 16'b1xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- L>R -- alt8 = 'b%b", alt8); err=1; end + //if (alt9 !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- L>R -- alt9 = 'b%b", alt9); err=1; end + + // assign a constant value to the array + abg1 = {WA*WB{1'b1}}; + abg2 = {WA*WB{1'b1}}; + abg3 = {WA*WB{1'b1}}; + abg4 = {WA*WB{1'b1}}; + abg5 = {WA*WB{1'b1}}; + abg6 = {WA*WB{1'b1}}; + abg7 = {WA*WB{1'b1}}; + abg8 = {WA*WB{1'b1}}; + abg9 = {WA*WB{1'b1}}; + + // test read from array LHS=RHS + a1d1 = {WA*WB+1{1'bx}}; a1d1[WA *WB -1+0:0] = abg1 ; + a1d2 = {WA*WB+1{1'bx}}; a1d2[WA/2*WB -1+0:0] = abg2 [WA/2-1:0 ] ; + a1d3 = {WA*WB+1{1'bx}}; a1d3[WA/2*WB -1+0:0] = abg3 [WA -1:WA/2] ; + a1d4 = {WA*WB+1{1'bx}}; a1d4[1 *WB -1+0:0] = abg4 [ 0 ] ; + a1d5 = {WA*WB+1{1'bx}}; a1d5[1 *WB -1+0:0] = abg5 [WA -1 ] ; + a1d6 = {WA*WB+1{1'bx}}; a1d6[1 *WB/2-1+0:0] = abg6 [ 0 ][WB/2-1:0 ]; + a1d7 = {WA*WB+1{1'bx}}; a1d7[1 *WB/2-1+0:0] = abg7 [WA -1 ][WB -1:WB/2]; + a1d8 = {WA*WB+1{1'bx}}; a1d8[1 *1 -1+0:0] = abg8 [ 0 ][ 0 ]; + a1d9 = {WA*WB+1{1'bx}}; a1d9[1 *1 -1+0:0] = abg9 [WA -1 ][WB -1 ]; + // check + if (a1d1 !== 17'bx_1111_1111_1111_1111) begin $display("FAILED -- L=R BE -- a1d1 = 'b%b", a1d1); err=1; end + if (a1d2 !== 17'bx_xxxx_xxxx_1111_1111) begin $display("FAILED -- L=R BE -- a1d2 = 'b%b", a1d2); err=1; end + if (a1d3 !== 17'bx_xxxx_xxxx_1111_1111) begin $display("FAILED -- L=R BE -- a1d3 = 'b%b", a1d3); err=1; end + if (a1d4 !== 17'bx_xxxx_xxxx_xxxx_1111) begin $display("FAILED -- L=R BE -- a1d4 = 'b%b", a1d4); err=1; end + if (a1d5 !== 17'bx_xxxx_xxxx_xxxx_1111) begin $display("FAILED -- L=R BE -- a1d5 = 'b%b", a1d5); err=1; end + if (a1d6 !== 17'bx_xxxx_xxxx_xxxx_xx11) begin $display("FAILED -- L=R BE -- a1d6 = 'b%b", a1d6); err=1; end + if (a1d7 !== 17'bx_xxxx_xxxx_xxxx_xx11) begin $display("FAILED -- L=R BE -- a1d7 = 'b%b", a1d7); err=1; end + if (a1d8 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- L=R BE -- a1d8 = 'b%b", a1d8); err=1; end + if (a1d9 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- L=R BE -- a1d9 = 'b%b", a1d9); err=1; end + + // test read from array LHS>RHS + a1d1 = {WA*WB+1{1'bx}}; a1d1[WA *WB -1+1:0] = abg1 ; + a1d2 = {WA*WB+1{1'bx}}; a1d2[WA/2*WB -1+1:0] = abg2 [WA/2-1:0 ] ; + a1d3 = {WA*WB+1{1'bx}}; a1d3[WA/2*WB -1+1:0] = abg3 [WA -1:WA/2] ; + a1d4 = {WA*WB+1{1'bx}}; a1d4[1 *WB -1+1:0] = abg4 [ 0 ] ; + a1d5 = {WA*WB+1{1'bx}}; a1d5[1 *WB -1+1:0] = abg5 [WA -1 ] ; + a1d6 = {WA*WB+1{1'bx}}; a1d6[1 *WB/2-1+1:0] = abg6 [ 0 ][WB/2-1:0 ]; + a1d7 = {WA*WB+1{1'bx}}; a1d7[1 *WB/2-1+1:0] = abg7 [WA -1 ][WB -1:WB/2]; + a1d8 = {WA*WB+1{1'bx}}; a1d8[1 *1 -1+1:0] = abg8 [ 0 ][ 0 ]; + a1d9 = {WA*WB+1{1'bx}}; a1d9[1 *1 -1+1:0] = abg9 [WA -1 ][WB -1 ]; + // check + if (a1d1 !== 17'b0_1111_1111_1111_1111) begin $display("FAILED -- L>R BE -- a1d1 = 'b%b", a1d1); err=1; end + if (a1d2 !== 17'bx_xxxx_xxx0_1111_1111) begin $display("FAILED -- L>R BE -- a1d2 = 'b%b", a1d2); err=1; end + if (a1d3 !== 17'bx_xxxx_xxx0_1111_1111) begin $display("FAILED -- L>R BE -- a1d3 = 'b%b", a1d3); err=1; end + if (a1d4 !== 17'bx_xxxx_xxxx_xxx0_1111) begin $display("FAILED -- L>R BE -- a1d4 = 'b%b", a1d4); err=1; end + if (a1d5 !== 17'bx_xxxx_xxxx_xxx0_1111) begin $display("FAILED -- L>R BE -- a1d5 = 'b%b", a1d5); err=1; end + if (a1d6 !== 17'bx_xxxx_xxxx_xxxx_x011) begin $display("FAILED -- L>R BE -- a1d6 = 'b%b", a1d6); err=1; end + if (a1d7 !== 17'bx_xxxx_xxxx_xxxx_x011) begin $display("FAILED -- L>R BE -- a1d7 = 'b%b", a1d7); err=1; end + if (a1d8 !== 17'bx_xxxx_xxxx_xxxx_xx01) begin $display("FAILED -- L>R BE -- a1d8 = 'b%b", a1d8); err=1; end + if (a1d9 !== 17'bx_xxxx_xxxx_xxxx_xx01) begin $display("FAILED -- L>R BE -- a1d9 = 'b%b", a1d9); err=1; end + + // test read from array LHSR LE -- a1d1 = 'b%b", a1d1); err=1; end + if (a1d2 !== 17'bx_xxxx_xxx0_1111_1111) begin $display("FAILED -- L>R LE -- a1d2 = 'b%b", a1d2); err=1; end + if (a1d3 !== 17'bx_xxxx_xxx0_1111_1111) begin $display("FAILED -- L>R LE -- a1d3 = 'b%b", a1d3); err=1; end + if (a1d4 !== 17'bx_xxxx_xxxx_xxx0_1111) begin $display("FAILED -- L>R LE -- a1d4 = 'b%b", a1d4); err=1; end + if (a1d5 !== 17'bx_xxxx_xxxx_xxx0_1111) begin $display("FAILED -- L>R LE -- a1d5 = 'b%b", a1d5); err=1; end + if (a1d6 !== 17'bx_xxxx_xxxx_xxxx_x011) begin $display("FAILED -- L>R LE -- a1d6 = 'b%b", a1d6); err=1; end + if (a1d7 !== 17'bx_xxxx_xxxx_xxxx_x011) begin $display("FAILED -- L>R LE -- a1d7 = 'b%b", a1d7); err=1; end + if (a1d8 !== 17'bx_xxxx_xxxx_xxxx_xx01) begin $display("FAILED -- L>R LE -- a1d8 = 'b%b", a1d8); err=1; end + if (a1d9 !== 17'bx_xxxx_xxxx_xxxx_xx01) begin $display("FAILED -- L>R LE -- a1d9 = 'b%b", a1d9); err=1; end + + // test read from array LHS (real, index=0, thr.), expected 1.0, got %s", res); + pass = 1'b0; + end + $sformat(res, "%3.1f", rarr[index]); + if (res != "1.0") begin + $display("Failed &A<> (real, index=0, sig.), expected 1.0, got %s", res); + pass = 1'b0; + end + if (rarr[index] != 1.0) begin + $display("Failed var select (real, index=0), expected 1.0"); + pass = 1'b0; + end + + $sformat(res, "%3b", arr[index+base]); + if (res != "001") begin + $display("Failed &A<> (reg, index=0, thr.), expected 001, got %s", res); + pass = 1'b0; + end + $sformat(res, "%3b", arr[index]); + if (res != "001") begin + $display("Failed &A<> (reg, index=0, sig.), expected 001, got %s", res); + pass = 1'b0; + end + if (arr[index] != 3'b001) begin + $display("Failed var select (reg, index=0), expected 3'b001"); + pass = 1'b0; + end + + // Check an undefined array word select. + index = 'bx; + $sformat(res, "%3.1f", rarr[index+base]); + if (res != "0.0") begin + $display("Failed &A<> (real, index=x, thr.), expected 0.0, got %s", res); + pass = 1'b0; + end + $sformat(res, "%3.1f", rarr[index]); + if (res != "0.0") begin + $display("Failed &A<> (real, index=x, sig.), expected 0.0, got %s", res); + pass = 1'b0; + end + if (rarr[index] != 0.0) begin + $display("Failed var select (real, index=x), expected 0.0"); + pass = 1'b0; + end + + $sformat(res, "%3b", arr[index+base]); + if (res != "xxx") begin + $display("Failed &A<> (reg, index=x, thr.), expected xxx, got %s", res); + pass = 1'b0; + end + $sformat(res, "%3b", arr[index]); + if (res != "xxx") begin + $display("Failed &A<> (reg, index=x, sig.), expected xxx, got %s", res); + pass = 1'b0; + end + if (arr[index] != 3'bxxx) begin + $display("Failed var select (reg, index=x), expected 3'bxxx"); + pass = 1'b0; + end + + // Check a before the array word select. + index = -1; + $sformat(res, "%3.1f", rarr[index+base]); + if (res != "0.0") begin + $display("Failed &A<> (real, index=-1, thr.), expected 0.0, got %s", res); + pass = 1'b0; + end + $sformat(res, "%3.1f", rarr[index]); + if (res != "0.0") begin + $display("Failed &A<> (real, index=-1, sig.), expected 0.0, got %s", res); + pass = 1'b0; + end + if (rarr[index] != 0.0) begin + $display("Failed var select (real, index=-1), expected 0.0"); + pass = 1'b0; + end + + $sformat(res, "%3b", arr[index+base]); + if (res != "xxx") begin + $display("Failed &A<> (reg, index=-1, thr.), expected xxx, got %s", res); + pass = 1'b0; + end + $sformat(res, "%3b", arr[index]); + if (res != "xxx") begin + $display("Failed &A<> (reg, index=-1, sig.), expected xxx, got %s", res); + pass = 1'b0; + end + if (arr[index] != 3'bxxx) begin + $display("Failed var select (reg, index=-1), expected 3'bxxx"); + pass = 1'b0; + end + + // Check an after the array word select. + index = 2; + $sformat(res, "%3.1f", rarr[index+base]); + if (res != "0.0") begin + $display("Failed &A<> (real, index=2, thr.), expected 0.0, got %s", res); + pass = 1'b0; + end + $sformat(res, "%3.1f", rarr[index]); + if (res != "0.0") begin + $display("Failed &A<> (real, index=2, sig.), expected 0.0, got %s", res); + pass = 1'b0; + end + if (rarr[index] != 0.0) begin + $display("Failed var select (real, index=2), expected 0.0"); + pass = 1'b0; + end + + $sformat(res, "%3b", arr[index+base]); + if (res != "xxx") begin + $display("Failed &A<> (reg, index=2, thr.), expected xxx, got %s", res); + pass = 1'b0; + end + $sformat(res, "%3b", arr[index]); + if (res != "xxx") begin + $display("Failed &A<> (reg, index=2, sig.), expected xxx, got %s", res); + pass = 1'b0; + end + if (arr[index] != 3'bxxx) begin + $display("Failed var select (reg, index=2), expected 3'bxxx"); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/array_size.v b/ivtest/ivltests/array_size.v new file mode 100644 index 000000000..852de2e5a --- /dev/null +++ b/ivtest/ivltests/array_size.v @@ -0,0 +1,31 @@ +module test; + + parameter width = 16; + localparam count = 1< +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for array querying functions for unpacked arrays +// (IEEE Std 1800-2012 7.11) + +module array_unpacked_sysfunct(); + bit [7:0] bit_darray []; + //bit bit_darray []; // not available yet + bit [7:0] array [2:4]; + bit [7:0] reverse_array[5:3]; + bit [2:8] packed_array; + bit [4:1] reverse_packed_array; + +initial begin + string test_msg = "13 characters"; + bit_darray = new[5]; + + if($left(bit_darray) != 0 || $right(bit_darray) != 4) begin + $display("FAILED 1"); + $finish(); + end + + if($left(array) != 2 || $right(array) != 4) begin + $display("FAILED 2"); + $finish(); + end + + if($left(reverse_array) != 5 || $right(reverse_array) != 3) begin + $display("FAILED 3"); + $finish(); + end + + if($left(test_msg) != 0 || $right(test_msg) != 12) begin + $display("FAILED 4"); + $finish(); + end + + if($left(packed_array) != 2 || $right(packed_array) != 8) begin + $display("FAILED 5"); + $finish(); + end + + if($left(reverse_packed_array) != 4 || $right(reverse_packed_array) != 1) begin + $display("FAILED 6"); + $finish(); + end + + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/array_word_check.v b/ivtest/ivltests/array_word_check.v new file mode 100644 index 000000000..9d960a0de --- /dev/null +++ b/ivtest/ivltests/array_word_check.v @@ -0,0 +1,20 @@ +module top; + reg [7:0] array [1:0]; + reg \array[0] ; + reg \array[1] ; + integer idx; + + initial begin + $dumpfile("work/dup.vcd"); + $dumpvars(0, array[0]); + idx = 1; + $dumpvars(0, array[idx]); + $dumpvars(0, top); + array[0] = 8'd0; + #1 + array[0] = 8'd1; + #1 + \array[0] = 1'b1; + \array[1] = 1'b0; + end +endmodule diff --git a/ivtest/ivltests/array_word_width.v b/ivtest/ivltests/array_word_width.v new file mode 100644 index 000000000..97c59299a --- /dev/null +++ b/ivtest/ivltests/array_word_width.v @@ -0,0 +1,10 @@ +module top; + reg [15:0] array [1:0]; + + initial begin + array[1] = 15'd48; + + // This should display 0003 + $displayh(array[1]>>4); + end +endmodule diff --git a/ivtest/ivltests/array_word_width2.v b/ivtest/ivltests/array_word_width2.v new file mode 100644 index 000000000..e827709e5 --- /dev/null +++ b/ivtest/ivltests/array_word_width2.v @@ -0,0 +1,16 @@ +module top; + wire [3:0] array [1:0]; + integer sel; + + assign array[0] = 4'h0; + assign array[1] = 4'h1; + + initial begin + #1; + $display(" %h %h", array[0], array[1]); + // This is only a problem for a wire (net array)! + sel = 0; + $display(" %h %h", array[sel], array[sel+1]); + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/assign3.2A.v b/ivtest/ivltests/assign3.2A.v new file mode 100644 index 000000000..f9d32018e --- /dev/null +++ b/ivtest/ivltests/assign3.2A.v @@ -0,0 +1,77 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate assign identifier = expression ; + +module main ; + +wire a; +wire [31:0] b; +wire [15:0] c; + +reg [31:0] val; +reg error; + +assign a = val [0]; // Pull single bit +assign b = val; // full variable +assign c = val[31:16]; // Top portion bit select + +initial + begin + error = 0; + if(a != 1'bx) + begin + $display("FAILED - 3.2A assign ident = expr"); + error = 1; + end + if(b != 32'bx) + begin + $display("FAILED - 3.2A assign ident = expr"); + error = 1; + end + if(c != 16'bx) + begin + $display("FAILED - 3.2A assign ident = expr"); + error = 1; + end + #1 ; + val = 32'h87654321; + #1 ; + if(a != 1'b1) + begin + $display("FAILED - 3.2A assign ident = expr"); + error = 1; + end + if(b != 32'h87654321) + begin + $display("FAILED - 3.2A assign ident = expr"); + error = 1; + end + if(c != 16'h8765) + begin + $display("FAILED - 3.2A assign ident = expr"); + error = 1; + end + if(error == 0) + $display("PASSED"); + + $finish ; + end + + +endmodule diff --git a/ivtest/ivltests/assign3.2B.v b/ivtest/ivltests/assign3.2B.v new file mode 100644 index 000000000..47dd30e5e --- /dev/null +++ b/ivtest/ivltests/assign3.2B.v @@ -0,0 +1,76 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate assign { ident0, ident1 } = expression ; + +module main ; + +wire a; +wire [30:0] b; +wire [14:0] c; + +reg [31:0] val; +reg error; + +assign {b,a} = val; // full variable +assign {c,a} = val[31:16]; // Top portion bit select + +initial + begin + error = 0; + if(a != 1'bx) + begin + $display("FAILED - assign 3.2B assign ident = expr"); + error = 1; + end + if(b != 31'bx) + begin + $display("FAILED - assign 3.2B assign ident = expr"); + error = 1; + end + if(c != 14'bx) + begin + $display("FAILED - assign 3.2B assign ident = expr"); + error = 1; + end + #1 ; + val = 32'h87654321; + #1 ; + if(a != 1'b1) + begin + $display("FAILED - 3.2A assign ident = expr"); + error = 1; + end + if(b != (32'h87654321) >> 1) + begin + $display("FAILED - 3.2A assign ident = expr"); + error = 1; + end + if(c != (16'h8765) >> 1) + begin + $display("FAILED - 3.2A assign ident = expr"); + error = 1; + end + if(error == 0) + $display("PASSED"); + + $finish ; + end + + +endmodule diff --git a/ivtest/ivltests/assign3.2C.v b/ivtest/ivltests/assign3.2C.v new file mode 100644 index 000000000..83864910c --- /dev/null +++ b/ivtest/ivltests/assign3.2C.v @@ -0,0 +1,77 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate assign procedural assign ident = expr; + +module main ; + + +reg [31:0] value; +reg control; +reg clock; +reg error; + +always @(posedge clock) + value = 3; + +always @(control) + if(control) + assign value = 2; + else + deassign value ; + + +// Setup a clock generator. +always begin + #2; + clock = ~clock; + end + +initial + begin + clock = 0; + error = 0; + # 3; + if(value != 3) + begin + $display("FAILED - assign3.2C - procedural assignment(1)"); + error = 1; + end + # 2; + control = 1; + # 1; + if(value != 2) + begin + $display("FAILED - assign3.2C - procedural assignment(2)"); + error = 1; + end + # 3 ; + control = 0; + # 2; + if(value != 3) + begin + $display("FAILED - assign3.2C - procedural assignment(3)"); + error = 1; + end + + if(error == 0) $display ("PASSED"); + $finish ; + + end + +endmodule diff --git a/ivtest/ivltests/assign3.2D.v b/ivtest/ivltests/assign3.2D.v new file mode 100644 index 000000000..bca646225 --- /dev/null +++ b/ivtest/ivltests/assign3.2D.v @@ -0,0 +1,77 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate assign procedural assign {ident1,ident0} = expr; + +module main ; + + +reg a,b,c,d; +reg control; +reg clock; +reg error; + +always @(posedge clock) + {a,b,c,d} = 4'h3; + +always @(control) + if(control) + assign {a,b,c,d} = 4'h2; + else + deassign {a,b,c,d} ; + + +// Setup a clock generator. +always begin + #2; + clock = ~clock; + end + +initial + begin + clock = 0; + error = 0; + # 3; + if({a,b,c,d} !== 3) + begin + $display("FAILED - assign3.2D - procedural assignment(1)"); + error = 1; + end + # 2; + control = 1; + # 1; + if({a,b,c,d} !== 2) + begin + $display("FAILED - assign3.2D - procedural assignment(2)"); + error = 1; + end + # 3 ; + control = 0; + # 2; + if({a,b,c,d} !== 3) + begin + $display("FAILED - assign3.2D - procedural assignment(3)"); + error = 1; + end + + if(error == 0) $display ("PASSED"); + $finish ; + + end + +endmodule diff --git a/ivtest/ivltests/assign3.2E.v b/ivtest/ivltests/assign3.2E.v new file mode 100644 index 000000000..0fb3b9abb --- /dev/null +++ b/ivtest/ivltests/assign3.2E.v @@ -0,0 +1,77 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate assign procedural assign {ident[1],ident[0]} = expr ERR; + +module main ; + + +reg [31:0] value; +reg control; +reg clock; +reg error; + +always @(posedge clock) + {value[3],value[2],value[1],value[0]} = 3; + +always @(control) + if(control) + assign {value[3],value[2],value[1],value[0]} = 4'h2; + else + deassign {value[3],value[2],value[1],value[0]} ; + + +// Setup a clock generator. +always begin + #2; + clock = ~clock; + end + +initial + begin + clock = 0; + error = 0; + # 3; + if(value != 3) + begin + $display("FAILED - assign3.2E - procedural assignment(1)"); + error = 1; + end + # 2; + control = 1; + # 1; + if(value != 2) + begin + $display("FAILED - assign3.2E - procedural assignment(2)"); + error = 1; + end + # 3 ; + control = 0; + # 2; + if(value != 3) + begin + $display("FAILED - assign3.2E - procedural assignment(3)"); + error = 1; + end + + if(error == 0) $display ("PASSED"); + $finish ; + + end + +endmodule diff --git a/ivtest/ivltests/assign_add.v b/ivtest/ivltests/assign_add.v new file mode 100644 index 000000000..09d28ea04 --- /dev/null +++ b/ivtest/ivltests/assign_add.v @@ -0,0 +1,24 @@ +/* + * assign_sum + * Demonstrate continuous assign of a sum. + */ + +module main; + + reg [8:0] A, B; + wire [9:0] sum = A + B; + + initial begin + A = 51; + B = 39; + #1 $display("%b + %b = %b", A, B, sum); + if (sum !== 90) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/assign_deassign_pv.v b/ivtest/ivltests/assign_deassign_pv.v new file mode 100644 index 000000000..4f218d5f2 --- /dev/null +++ b/ivtest/ivltests/assign_deassign_pv.v @@ -0,0 +1,59 @@ +module test; + reg fail = 1'b0; + reg [3:0] bus = 4'b0; + + initial begin + // Check the initial value. + if (bus !== 4'b0) begin + $display("FAILED: initial value, got %b, expected 0000.", bus); + fail = 1'b1; + end + + // Check a bit assign and verify a normal bit assign does nothing. + #1 assign bus[0] = 1'b1; + bus[0] = 1'bz; + if (bus !== 4'b0001) begin + $display("FAILED: assign of bus[0], got %b, expected 0001.", bus); + fail = 1'b1; + end + + // Check a part assign. + #1 assign bus[3:2] = 2'b11; + if (bus !== 4'b1101) begin + $display("FAILED: assign of bus[3:2], got %b, expected 1101.", bus); + fail = 1'b1; + end + + // Check that we can change an unassigned bit. + #1 bus[1] = 1'bz; + if (bus !== 4'b11z1) begin + $display("FAILED: assignment of bus[1], got %b, expected 11z1.", bus); + fail = 1'b1; + end + + // Check a bit deassign. + #1 deassign bus[0]; + bus = 4'b000z; + if (bus !== 4'b110z) begin + $display("FAILED: deassign of bus[0], got %b, expected 110z.", bus); + fail = 1'b1; + end + + // Check a part deassign (we keep the old value if not changed). + #1 deassign bus[3:2]; + bus[3] = 1'b0; + if (bus !== 4'b010z) begin + $display("FAILED: deassign of bus[3:2], got %b, expected 010z.", bus); + fail = 1'b1; + end + + // Check an assign from the upper thread bits >= 8. + #1 assign bus[2:1] = 2'bx1; + if (bus !== 4'b0x1z) begin + $display("FAILED: assign of bus[2:1], got %b, expected 0x1z.", bus); + fail = 1'b1; + end + + if (!fail) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/assign_delay.v b/ivtest/ivltests/assign_delay.v new file mode 100644 index 000000000..96020a96c --- /dev/null +++ b/ivtest/ivltests/assign_delay.v @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test captures the essence of PR#40, namely the possibility + * that the continuous assign from a reg to a wire may have a delay. + */ +module test; + wire a; + reg b; + + assign #10 a = b; + + initial begin + b = 0; + # 20 b = 1; + # 5 if (a !== 0) begin + $display("FAILED -- a is %b", a); + $finish; + end + + # 6 if (a !== 1) begin + $display("FAILED -- a is %b, should be 1", a); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/assign_deq.v b/ivtest/ivltests/assign_deq.v new file mode 100644 index 000000000..8797d3602 --- /dev/null +++ b/ivtest/ivltests/assign_deq.v @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2000 Steven Wilson (stevew@homeaddress.org) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test looks for == operation in a continuous assignment. + */ +module test; + +integer a; +integer b; +wire result; +integer error; + +assign result = (a == b); + +initial + begin + a = 0; + b = 0; + error = 0; + #5 ; + if( result !== 1'b1) + error =1; + a = 1; + #5; + if( result !== 1'b0) + error =1; + + b = 1; + #5 ; + if( result !== 1'b1) + error =1; + + a = 1002; + b = 1001; + #5 ; + if( result !== 1'b0) + error =1; + a = 1001; + #5 ; + if( result !== 1'b1) + error =1; + + if(error === 0) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/assign_ge.v b/ivtest/ivltests/assign_ge.v new file mode 100644 index 000000000..1aa5dc80c --- /dev/null +++ b/ivtest/ivltests/assign_ge.v @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2000 Steven Wilson (stevew@homeaddress.org) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test looks for >= operation in a continuous assignment. + */ +module test; + +integer a; +integer b; +wire result; +integer error; + +assign result = (a >= b); + +initial + begin + a = 0; + b = 0; + error = 0; + #5 ; + if( result !== 1'b1) + error =1; + a = 1; + #5; + if( result !== 1'b1) + error =1; + + b = 1; + #5 ; + if( result !== 1'b1) + error =1; + + a = 1001; + b = 1002; + #5 ; + if( result !== 1'b0) + error =1; + a = 1003; + #5 ; + if( result !== 1'b1) + error =1; + + if(error === 0) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/assign_le.v b/ivtest/ivltests/assign_le.v new file mode 100644 index 000000000..89447f999 --- /dev/null +++ b/ivtest/ivltests/assign_le.v @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2000 Steven Wilson (stevew@homeaddress.org) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test looks for <= operation in a continuous assignment. + */ +module test; + +integer a; +integer b; +wire result; +integer error; + +assign result = (a <= b); + +initial + begin + a = 0; + b = 0; + error = 0; + #5 ; + if( result !== 1'b1) + error =1; + a = 1; + #5; + if( result !== 1'b0) + error =1; + + b = 1; + #5 ; + if( result !== 1'b1) + error =1; + + a = 1001; + b = 1002; + #5 ; + if( result !== 1'b1) + error =1; + a = 1003; + #5 ; + if( result !== 1'b0) + error =1; + + if(error === 0) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/assign_mem1.v b/ivtest/ivltests/assign_mem1.v new file mode 100644 index 000000000..82d270e94 --- /dev/null +++ b/ivtest/ivltests/assign_mem1.v @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2000 Chris Lattner + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This isn't computationally complicated, but can trip up a vvm + * code generation error. + */ +module test; + reg [15:0] is[1:0]; + reg [4:0] i; + + initial begin + i = 0; + is[0] = i; // Notice the different widths. + if (is[0] !== 16'd0) begin + $display("FAILED -- is[0] --> %b", is[0]); + $finish; + end + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/assign_mem2.v b/ivtest/ivltests/assign_mem2.v new file mode 100644 index 000000000..ffc3d3591 --- /dev/null +++ b/ivtest/ivltests/assign_mem2.v @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2000 Chris Lattner + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +module test; + reg [31:0] buff[256*2*2-1:0]; + reg [31:0] x; + + initial + begin + buff[0] = 0; + x = 256; + buff[x+0] = 1234; + + if (buff[0] != 0) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/assign_nb1.v b/ivtest/ivltests/assign_nb1.v new file mode 100644 index 000000000..701bb4aba --- /dev/null +++ b/ivtest/ivltests/assign_nb1.v @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2000 Peter monta (pmonta@pacbell.net) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// Reworked by SDW to be self checking +module main; + + reg [7:0] x; + reg [7:0] y; + reg [2:0] i; // Was a wire.. + reg error; + + initial begin + #5; + x[i] <= #1 0; + y[i] = 0; + end + +initial + begin + error = 0; + #1; + i = 1; + #7; + if(x[i] !== 1'b0) + begin + $display("FAILED - x[1] != 0"); + error = 1; + end + if(y[i] !== 1'b0) + begin + $display("FAILED - y[1] != 0"); + error = 1; + end + if(error === 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/assign_nb2.v b/ivtest/ivltests/assign_nb2.v new file mode 100644 index 000000000..4a09446a8 --- /dev/null +++ b/ivtest/ivltests/assign_nb2.v @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Catch problems with non-zero lsb values in l-value expressions. + */ +module main; + + reg [7:1] a = 6'b111111; + reg [7:1] b = 6'b000010; + + integer q; + reg [7:1] x; + reg PCLK = 1; + always @(posedge PCLK) + for (q=1; q<=7; q=q+1) + x[q] <= #1 a[q] & b[q]; + + always #5 PCLK = !PCLK; + + initial begin +// $dumpfile("dump.vcd"); +// $dumpvars(0, main); + #50 $display("done: x=%b", x); + + if (x !== 6'b000010) + $display("FAILED -- x = %b", x); + else + $display("PASSED"); + + $finish; + end + + +endmodule // main diff --git a/ivtest/ivltests/assign_neq.v b/ivtest/ivltests/assign_neq.v new file mode 100644 index 000000000..ea0012a43 --- /dev/null +++ b/ivtest/ivltests/assign_neq.v @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2000 Steven Wilson (stevew@homeaddress.org) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test looks for != operation in a continuous assignment. + */ +module test; + +integer a; +integer b; +wire result; +integer error; + +assign result = (a != b); + +initial + begin + a = 0; + b = 0; + error = 0; + #5 ; + if( result === 1'b1) + error =1; + a = 1; + #5; + if( result === 1'b0) + error =1; + + b = 1; + #5 ; + if( result === 1'b1) + error =1; + + a = 1002; + b = 1001; + #5 ; + if( result === 1'b0) + error =1; + a = 1001; + #5 ; + if( result === 1'b1) + error =1; + + if(error === 0) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/assign_op_concat.v b/ivtest/ivltests/assign_op_concat.v new file mode 100644 index 000000000..2f6d1ba65 --- /dev/null +++ b/ivtest/ivltests/assign_op_concat.v @@ -0,0 +1,25 @@ +module test(); + +reg [3:0] count; +reg carry; + +reg failed = 0; + +integer i; + +initial begin + {carry, count} = 0; + for (i = 0; i < 32; i += 1) begin + $display("%b %b", carry, count); + if (count !== i[3:0]) failed = 1; + if (carry !== i[4]) failed = 1; + {carry, count} += 1; + end + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/assign_op_type.v b/ivtest/ivltests/assign_op_type.v new file mode 100644 index 000000000..b96e34413 --- /dev/null +++ b/ivtest/ivltests/assign_op_type.v @@ -0,0 +1,36 @@ +module test(); + +reg signed [3:0] a; +reg [7:0] b; +reg signed [7:0] c; +reg signed [7:0] d; +reg signed [7:0] e; + +reg failed = 0; + +initial begin + a = -1; + b = 4; + c = 4; + d = 4; + e = 4; + b += a; + c += a; + {d} += a; + e[7:0] += a; + $display("%0d", b); + if (b !== 19) failed = 1; + $display("%0d", c); + if (c !== 3) failed = 1; + $display("%0d", d); + if (d !== 19) failed = 1; + $display("%0d", e); + if (e !== 19) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/attrib.v b/ivtest/ivltests/attrib.v new file mode 100644 index 000000000..783756b5f --- /dev/null +++ b/ivtest/ivltests/attrib.v @@ -0,0 +1,41 @@ +// This test program is mostly about the parser parsing the attribute +// attached to the main.dut.Q reg below. + +module main; + + reg CK; + always begin + #10 CK = 0; + #10 CK = 1; + end + + reg [3:0] D; + wire [3:0] Q; + test dut (.Q(Q), .D(D), .CK(CK)); + + initial begin + D = 0; + @(posedge CK) #1 $display("Q=%b, D=%b", Q, D); + if (Q !== D) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main + +module test (Q, D, CK); + + output [3:0] Q; + input [3:0] D; + input CK; + + (* REGISTER_DUPLICATION = "no" *) + reg [3:0] Q; + always @(posedge CK) + Q <= D; + +endmodule // test diff --git a/ivtest/ivltests/attrib01_module.v b/ivtest/ivltests/attrib01_module.v new file mode 100644 index 000000000..6e3fa2da6 --- /dev/null +++ b/ivtest/ivltests/attrib01_module.v @@ -0,0 +1,28 @@ +(* this_is_module_bar *) +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= ~inp; + +endmodule + +(* this_is_module_foo *) +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + bar bar_instance (clk, rst, inp, out); + + initial begin + $display("PASSED"); + end + +endmodule + diff --git a/ivtest/ivltests/attrib02_port_decl.v b/ivtest/ivltests/attrib02_port_decl.v new file mode 100644 index 000000000..0c2d43550 --- /dev/null +++ b/ivtest/ivltests/attrib02_port_decl.v @@ -0,0 +1,30 @@ +module bar(clk, rst, inp, out); + (* this_is_clock = 1 *) + input wire clk; + (* this_is_reset = 1 *) + input wire rst; + input wire inp; + (* an_output_register = 1*) + output reg out; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out); + (* this_is_the_master_clock *) + input wire clk; + input wire rst; + input wire inp; + output wire out; + + bar bar_instance (clk, rst, inp, out); + + initial begin + $display("PASSED"); + end + +endmodule + diff --git a/ivtest/ivltests/attrib03_parameter.v b/ivtest/ivltests/attrib03_parameter.v new file mode 100644 index 000000000..3c17b1071 --- /dev/null +++ b/ivtest/ivltests/attrib03_parameter.v @@ -0,0 +1,33 @@ +module bar(clk, rst, inp, out); + + (* bus_width *) + parameter WIDTH = 2; + + (* an_attribute_on_localparam = 55 *) + localparam INCREMENT = 5; + + input wire clk; + input wire rst; + input wire [WIDTH-1:0] inp; + output reg [WIDTH-1:0] out; + + always @(posedge clk) + if (rst) out <= 0; + else out <= inp + INCREMENT; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire [7:0] inp; + output wire [7:0] out; + + bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out); + + initial begin + $display("PASSED"); + end + +endmodule + diff --git a/ivtest/ivltests/attrib04_net_var.v b/ivtest/ivltests/attrib04_net_var.v new file mode 100644 index 000000000..6164914ab --- /dev/null +++ b/ivtest/ivltests/attrib04_net_var.v @@ -0,0 +1,37 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + (* this_is_a_prescaler *) + reg [7:0] counter; + + (* temp_wire *) + wire out_val; + + always @(posedge clk) + counter <= counter + 1; + + assign out_val = inp ^ counter[4]; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= out_val; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + bar bar_instance (clk, rst, inp, out); + + initial begin + $display("PASSED"); + end + +endmodule + diff --git a/ivtest/ivltests/attrib05_port_conn.v b/ivtest/ivltests/attrib05_port_conn.v new file mode 100644 index 000000000..4de6429a7 --- /dev/null +++ b/ivtest/ivltests/attrib05_port_conn.v @@ -0,0 +1,27 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out_a, out_b); + input wire clk; + input wire rst; + input wire inp; + output wire out_a; + output wire out_b; + + bar bar_instance_1 ( (* this_is_clock *) .clk(clk), .rst(rst), .inp(inp), .out(out_a) ); + bar bar_instance_2 ( clk, (* this_is_reset *) rst, inp, out_b ); + + initial begin + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/attrib06_operator_suffix.v b/ivtest/ivltests/attrib06_operator_suffix.v new file mode 100644 index 000000000..f0d7b3573 --- /dev/null +++ b/ivtest/ivltests/attrib06_operator_suffix.v @@ -0,0 +1,28 @@ +module bar(clk, rst, inp_a, inp_b, out); + input wire clk; + input wire rst; + input wire [7:0] inp_a; + input wire [7:0] inp_b; + output reg [7:0] out; + + always @(posedge clk) + if (rst) out <= 0; + else out <= inp_a + (* ripple_adder *) inp_b; + +endmodule + +module foo(clk, rst, inp_a, inp_b, out); + input wire clk; + input wire rst; + input wire [7:0] inp_a; + input wire [7:0] inp_b; + output wire [7:0] out; + + bar bar_instance (clk, rst, inp_a, inp_b, out); + + initial begin + $display("PASSED"); + end + +endmodule + diff --git a/ivtest/ivltests/attrib07_func_call.v b/ivtest/ivltests/attrib07_func_call.v new file mode 100644 index 000000000..8e995d934 --- /dev/null +++ b/ivtest/ivltests/attrib07_func_call.v @@ -0,0 +1,24 @@ +module foo(clk, rst, inp_a, inp_b, out); + input wire clk; + input wire rst; + input wire [7:0] inp_a; + input wire [7:0] inp_b; + output reg [7:0] out; + + function [7:0] do_add; + input [7:0] inp_a; + input [7:0] inp_b; + + do_add = inp_a + inp_b; + endfunction + + always @(posedge clk) + if (rst) out <= 0; + else out <= do_add (* combinational_adder *) (inp_a, inp_b); + + initial begin + $display("PASSED"); + end + +endmodule + diff --git a/ivtest/ivltests/attrib08_mod_inst.v b/ivtest/ivltests/attrib08_mod_inst.v new file mode 100644 index 000000000..13822d3a6 --- /dev/null +++ b/ivtest/ivltests/attrib08_mod_inst.v @@ -0,0 +1,27 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + (* my_module_instance = 99 *) + bar bar_instance (clk, rst, inp, out); + + initial begin + $display("PASSED"); + end + +endmodule + diff --git a/ivtest/ivltests/attrib09_case.v b/ivtest/ivltests/attrib09_case.v new file mode 100644 index 000000000..3c1d74da3 --- /dev/null +++ b/ivtest/ivltests/attrib09_case.v @@ -0,0 +1,31 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire [1:0] inp; + output reg [1:0] out; + + always @(inp) + (* full_case, parallel_case *) + case(inp) + 2'd0: out <= 2'd3; + 2'd1: out <= 2'd2; + 2'd2: out <= 2'd1; + 2'd3: out <= 2'd0; + endcase + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire [1:0] inp; + output wire [1:0] out; + + bar bar_instance (clk, rst, inp, out); + + initial begin + $display("PASSED"); + end + +endmodule + diff --git a/ivtest/ivltests/automatic_error1.v b/ivtest/ivltests/automatic_error1.v new file mode 100644 index 000000000..9a5b2f64c --- /dev/null +++ b/ivtest/ivltests/automatic_error1.v @@ -0,0 +1,13 @@ +module automatic_error(); + +task automatic auto_task; + +reg local; + +local = 1; + +endtask + +initial auto_task.local = 0; + +endmodule diff --git a/ivtest/ivltests/automatic_error10.v b/ivtest/ivltests/automatic_error10.v new file mode 100644 index 000000000..1a595070c --- /dev/null +++ b/ivtest/ivltests/automatic_error10.v @@ -0,0 +1,15 @@ +module automatic_error(); + +reg global; + +task automatic auto_task; + +reg local; + +begin:block + force global = local; +end + +endtask + +endmodule diff --git a/ivtest/ivltests/automatic_error11.v b/ivtest/ivltests/automatic_error11.v new file mode 100644 index 000000000..a3c77c65c --- /dev/null +++ b/ivtest/ivltests/automatic_error11.v @@ -0,0 +1,19 @@ +`begin_keywords "1364-2005" +module automatic_error(); + +task automatic auto_task; + +integer local; + +begin + $monitor("%0d", local); + #1 local = 0; + #1 local = 1; +end + +endtask + +initial auto_task; + +endmodule +`end_keywords diff --git a/ivtest/ivltests/automatic_error12.v b/ivtest/ivltests/automatic_error12.v new file mode 100644 index 000000000..ef6e1e23f --- /dev/null +++ b/ivtest/ivltests/automatic_error12.v @@ -0,0 +1,18 @@ +`begin_keywords "1364-2005" +module automatic_error(); + +task automatic auto_task; + +integer local; + +begin + local = 1; + $strobe("%0d", local); +end + +endtask + +initial auto_task; + +endmodule +`end_keywords diff --git a/ivtest/ivltests/automatic_error13.v b/ivtest/ivltests/automatic_error13.v new file mode 100644 index 000000000..b2d64a39b --- /dev/null +++ b/ivtest/ivltests/automatic_error13.v @@ -0,0 +1,18 @@ +`begin_keywords "1364-2005" +module automatic_error(); + +task automatic auto_task; + +integer local; + +begin + local = 1; + $fstrobe(1, "%0d", local); +end + +endtask + +initial auto_task; + +endmodule +`end_keywords diff --git a/ivtest/ivltests/automatic_error2.v b/ivtest/ivltests/automatic_error2.v new file mode 100644 index 000000000..475754e9b --- /dev/null +++ b/ivtest/ivltests/automatic_error2.v @@ -0,0 +1,13 @@ +module automatic_error(); + +task automatic auto_task; + +reg local; + +begin:block + local <= #1 0; +end + +endtask + +endmodule diff --git a/ivtest/ivltests/automatic_error3.v b/ivtest/ivltests/automatic_error3.v new file mode 100644 index 000000000..4063988f9 --- /dev/null +++ b/ivtest/ivltests/automatic_error3.v @@ -0,0 +1,17 @@ +`begin_keywords "1364-2005" +module automatic_error(); + +reg global; + +task automatic auto_task; + +begin:block + reg local; + + global <= @(local) 0; +end + +endtask + +endmodule +`end_keywords diff --git a/ivtest/ivltests/automatic_error4.v b/ivtest/ivltests/automatic_error4.v new file mode 100644 index 000000000..7f45077f0 --- /dev/null +++ b/ivtest/ivltests/automatic_error4.v @@ -0,0 +1,15 @@ +module automatic_error(); + +reg global; + +task automatic auto_task; + +reg local; + +begin:block + @(local || global); +end + +endtask + +endmodule diff --git a/ivtest/ivltests/automatic_error5.v b/ivtest/ivltests/automatic_error5.v new file mode 100644 index 000000000..9117765bb --- /dev/null +++ b/ivtest/ivltests/automatic_error5.v @@ -0,0 +1,15 @@ +module automatic_error(); + +reg global; + +task automatic auto_task; + +reg local; + +begin:block + assign local = global; +end + +endtask + +endmodule diff --git a/ivtest/ivltests/automatic_error6.v b/ivtest/ivltests/automatic_error6.v new file mode 100644 index 000000000..e62622a16 --- /dev/null +++ b/ivtest/ivltests/automatic_error6.v @@ -0,0 +1,15 @@ +module automatic_error(); + +reg global; + +task automatic auto_task; + +reg local; + +begin:block + deassign local; +end + +endtask + +endmodule diff --git a/ivtest/ivltests/automatic_error7.v b/ivtest/ivltests/automatic_error7.v new file mode 100644 index 000000000..4afb0c37d --- /dev/null +++ b/ivtest/ivltests/automatic_error7.v @@ -0,0 +1,15 @@ +module automatic_error(); + +reg global; + +task automatic auto_task; + +reg local; + +begin:block + assign global = local; +end + +endtask + +endmodule diff --git a/ivtest/ivltests/automatic_error8.v b/ivtest/ivltests/automatic_error8.v new file mode 100644 index 000000000..769415b72 --- /dev/null +++ b/ivtest/ivltests/automatic_error8.v @@ -0,0 +1,15 @@ +module automatic_error(); + +reg global; + +task automatic auto_task; + +reg local; + +begin:block + force local = global; +end + +endtask + +endmodule diff --git a/ivtest/ivltests/automatic_error9.v b/ivtest/ivltests/automatic_error9.v new file mode 100644 index 000000000..3364e9156 --- /dev/null +++ b/ivtest/ivltests/automatic_error9.v @@ -0,0 +1,15 @@ +module automatic_error(); + +reg global; + +task automatic auto_task; + +reg local; + +begin:block + release local; +end + +endtask + +endmodule diff --git a/ivtest/ivltests/automatic_events.v b/ivtest/ivltests/automatic_events.v new file mode 100644 index 000000000..a82396040 --- /dev/null +++ b/ivtest/ivltests/automatic_events.v @@ -0,0 +1,58 @@ +module automatic_events(); + +reg [5:1] any; + +integer i; + +initial begin + any = 5'b00000; + #200; + for (i = 1; i <= 5; i = i + 1) begin + #10 any[i] = 1; + #10 any[i] = 0; + end +end + +task automatic report_events; + +input integer n; + +reg [5:1] pos; +reg [5:1] neg; + +integer i; +integer j; + +begin + #n; + pos = 5'b00000; + neg = 5'b00000; + fork + for (i = 1; i <= 5; i = i + 1) begin + #10 neg[i] = 1; + #10 pos[i] = 1; + #10 neg[i] = 0; + #10 pos[i] = 0; + end + for (j = 1; j <= 20; j = j + 1) begin + @( any[1] or posedge pos[1] or negedge neg[1] + or any[2] or posedge pos[2] or negedge neg[2] + or any[3] or posedge pos[3] or negedge neg[3] + or any[4] or posedge pos[4] or negedge neg[4] + or any[5] or posedge pos[5] or negedge neg[5] ); + #n $display("task %0d triggered: %b %b %b %4d", n, any, pos, neg, $time); + end + join +end + +endtask + +initial begin + fork + report_events(1); + report_events(2); + join + $finish(0); +end + +endmodule diff --git a/ivtest/ivltests/automatic_events2.v b/ivtest/ivltests/automatic_events2.v new file mode 100644 index 000000000..4e3447562 --- /dev/null +++ b/ivtest/ivltests/automatic_events2.v @@ -0,0 +1,58 @@ +module automatic_events(); + +reg [5:1] any; + +integer k; + +initial begin + any = 5'b00000; + #200; + for (k = 1; k <= 5; k = k + 1) begin + #10 any[k] = 1; + #10 any[k] = 0; + end +end + +task automatic report_events; + +input integer n; + +begin:task_body + reg [5:1] pos; + reg [5:1] neg; + + #n; + pos = 5'b00000; + neg = 5'b00000; + fork:task_threads + integer i; + integer j; + + for (i = 1; i <= 5; i = i + 1) begin + #10 neg[i] = 1; + #10 pos[i] = 1; + #10 neg[i] = 0; + #10 pos[i] = 0; + end + for (j = 1; j <= 20; j = j + 1) begin + @( any[1] or posedge pos[1] or negedge neg[1] + or any[2] or posedge pos[2] or negedge neg[2] + or any[3] or posedge pos[3] or negedge neg[3] + or any[4] or posedge pos[4] or negedge neg[4] + or any[5] or posedge pos[5] or negedge neg[5] ); + #n $display("task %0d triggered: %b %b %b %4d", n, any, pos, neg, $time); + end + join +end + +endtask + +initial begin + fork + report_events(1); + report_events(2); + join + $finish(0); +end + +endmodule diff --git a/ivtest/ivltests/automatic_events3.v b/ivtest/ivltests/automatic_events3.v new file mode 100644 index 000000000..c2d4a6820 --- /dev/null +++ b/ivtest/ivltests/automatic_events3.v @@ -0,0 +1,96 @@ +module automatic_events3(); + +reg [1:0] Source; + +initial begin + Source[0] = 1'b0; + forever begin + #20 Source[0] = 1'b1; + #20 Source[0] = 1'b0; + end +end + +initial begin + Source[1] = 1'b0; + #15; + forever begin + #10 Source[1] = 1'bx; + #10 Source[1] = 1'b1; + #10 Source[1] = 1'bx; + #10 Source[1] = 1'b0; + end +end + +task automatic ReportPosEdge0; + +begin + @(posedge Source[0]); + $display("Time %t : Source[0] rise", $time); +end + +endtask + +task automatic ReportNegEdge0; + +begin + @(negedge Source[0]); + $display("Time %t : Source[0] fall", $time); +end + +endtask + +task automatic ReportAnyEdge0; + +time t; + +begin + @(Source[0]) t = $time; + #1 $display("Time %t : Source[0] edge", t); +end + +endtask + +task automatic ReportPosEdge1; + +begin + @(posedge Source[1]); + $display("Time %t : Source[1] rise", $time); +end + +endtask + +task automatic ReportNegEdge1; + +begin + @(negedge Source[1]); + $display("Time %t : Source[1] fall", $time); +end + +endtask + +task automatic ReportAnyEdge1; + +time t; + +begin + @(Source[1]) t = $time; + #1 $display("Time %t : Source[1] edge", t); +end + +endtask + +initial begin + #1; + fork + repeat(2) ReportPosEdge0; + repeat(2) ReportNegEdge0; + repeat(4) ReportAnyEdge0; + + repeat(4) ReportPosEdge1; + repeat(4) ReportNegEdge1; + repeat(8) ReportAnyEdge1; + join + $finish(0); +end + +endmodule diff --git a/ivtest/ivltests/automatic_task.v b/ivtest/ivltests/automatic_task.v new file mode 100644 index 000000000..d4eac430e --- /dev/null +++ b/ivtest/ivltests/automatic_task.v @@ -0,0 +1,31 @@ +module automatic_task(); + +task automatic fill_array; + +input [7:0] value; + +reg [7:0] array[3:0]; + +event step; + +fork + begin + #10 array[0] = value; ->step; + #10 array[1] = array[0]; ->step; + #10 array[2] = array[1]; ->step; + #10 array[3] = array[2]; ->step; + end + begin + @step $display(array[0], array[1], array[2], array[3]); + @step $display(array[0], array[1], array[2], array[3]); + @step $display(array[0], array[1], array[2], array[3]); + @step $display(array[0], array[1], array[2], array[3]); + end +join + +endtask + +initial #1 fill_array(1); +initial #2 fill_array(2); + +endmodule diff --git a/ivtest/ivltests/automatic_task2.v b/ivtest/ivltests/automatic_task2.v new file mode 100644 index 000000000..e9922fd17 --- /dev/null +++ b/ivtest/ivltests/automatic_task2.v @@ -0,0 +1,31 @@ +module automatic_task(); + +task automatic fill_array; + +input [7:0] value; + +reg [7:0] array[3:0]; + +integer i; + +fork + begin + #10 array[0] = value; + #10 array[1] = array[0]; + #10 array[2] = array[1]; + #10 array[3] = array[2]; + end + begin + @(array[0]) $display(array[0], array[1], array[2], array[3]); + @(array[1]) $display(array[0], array[1], array[2], array[3]); + @(array[2]) $display(array[0], array[1], array[2], array[3]); + @(array[3]) $display(array[0], array[1], array[2], array[3]); + end +join + +endtask + +initial #1 fill_array(1); +initial #2 fill_array(2); + +endmodule diff --git a/ivtest/ivltests/automatic_task3.v b/ivtest/ivltests/automatic_task3.v new file mode 100644 index 000000000..fda60e78e --- /dev/null +++ b/ivtest/ivltests/automatic_task3.v @@ -0,0 +1,26 @@ +module automatic_task(); + +reg [7:0] array[3:0]; + +task automatic fill_array; + +input [7:0] value; + +integer i, j; + +fork + for (i = 0; i < 4; i = i + 1) begin + #10 array[i] = value; + end + for (j = 0; j < 4; j = j + 1) begin + @(array[j]) $display(array[0], array[1], array[2], array[3]); + @(array[j]) $display(array[0], array[1], array[2], array[3]); + end +join + +endtask + +initial #1 fill_array(1); +initial #2 fill_array(2); + +endmodule diff --git a/ivtest/ivltests/basicexpr.v b/ivtest/ivltests/basicexpr.v new file mode 100644 index 000000000..bc87a7861 --- /dev/null +++ b/ivtest/ivltests/basicexpr.v @@ -0,0 +1,85 @@ +// +// Copyright (c) 2002 Steven Wilson (steve@ka6s.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Synth of basic reg form +// +// +module basicreg ( clk, d, q); +input clk, d; +output [2:0] q; +reg [2:0] q; + +always @(posedge clk) + begin + q <= d + d; + end + +endmodule + +module test ; + +reg clk, d; + +wire [2:0] q; + +basicreg u_reg (clk,d,q); + +initial + begin +// $dumpfile("test.vcd"); +// $dumpvars(0,test); + clk = 0; + d = 0; + # 1; + clk = 1; + # 1; + if (q !== 3'b0) + begin + $display("FAILED - Q isn't 0 on first edge"); + $finish; + end + d = 1; + # 1; + clk = 0; + # 1; + if (q !== 3'b0) + begin + $display("FAILED - Q isn't 0 after first falling edge"); + $finish; + end + # 1; + clk = 1; + # 1; + if (q !== 3'b010) + begin + #1 ; + $display("FAILED - Q isn't 2 2nd raising edge"); + $finish; + end + # 1; + clk = 0; + # 1; + if (q !== 3'b010) + begin + $display("FAILED - Q isn't 2 after 2nd falling edge"); + $finish; + end + $display("PASSED"); + + end +endmodule diff --git a/ivtest/ivltests/basicexpr2.v b/ivtest/ivltests/basicexpr2.v new file mode 100644 index 000000000..1972ee208 --- /dev/null +++ b/ivtest/ivltests/basicexpr2.v @@ -0,0 +1,61 @@ +// +// Copyright (c) 2002 Steven Wilson (steve@ka6s.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Synth of basic expression assign with add +// +// +module adder (q,a,b ); +input a,b; +output [1:0] q; + +assign q = {1'b0,a} +{1'b0,b}; + +endmodule + +module test ; + +reg d; + +wire [1:0] q; + +adder u_add (.q(q),.a(d),.b(d)); + +(* ivl_synthesis_off *) +initial + begin +// $dumpfile("test.vcd"); +// $dumpvars(0,test); + d = 0; + # 1; + if (q !== 2'b0) + begin + $display("FAILED - Q isn't 0 "); + $finish; + end + #1 ; + d = 1; + # 1; + if (q !== 2'b10) + begin + $display("FAILED - Q isn't 2 "); + $finish; + end + $display("PASSED"); + + end +endmodule diff --git a/ivtest/ivltests/basicexpr3.v b/ivtest/ivltests/basicexpr3.v new file mode 100644 index 000000000..c2e913b32 --- /dev/null +++ b/ivtest/ivltests/basicexpr3.v @@ -0,0 +1,61 @@ +// +// Copyright (c) 2002 Steven Wilson (steve@ka6s.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Synth of basic expression assign with add +// +// +module mul (q,a,b ); +input a,b; +output [1:0] q; + +assign q = {1'b0,a} * {1'b0,b}; + +endmodule + +module test ; + +reg d; + +wire [1:0] q; + +mul u_mul (.q(q),.a(d),.b(d)); + +(* ivl_synthesis_off *) +initial + begin +// $dumpfile("test.vcd"); +// $dumpvars(0,test); + d = 0; + # 1; + if (q !== 2'b0) + begin + $display("FAILED - Q isn't 0 "); + $finish; + end + #1 ; + d = 1; + # 1; + if (q !== 2'b01) + begin + $display("FAILED - Q isn't 2 "); + $finish; + end + $display("PASSED"); + + end +endmodule diff --git a/ivtest/ivltests/basicexpr4.v b/ivtest/ivltests/basicexpr4.v new file mode 100644 index 000000000..489a27844 --- /dev/null +++ b/ivtest/ivltests/basicexpr4.v @@ -0,0 +1,61 @@ +// +// Copyright (c) 2002 Steven Wilson (steve@ka6s.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Synth of basic expression assign with add +// +// +module adder (q,a,b ); +input a,b; +output [1:0] q; + +assign q = a + b; + +endmodule + +module test ; + +reg d; + +wire [1:0] q; + +adder u_add (.q(q),.a(d),.b(d)); + +(* ivl_synthesis_off *) +initial + begin +// $dumpfile("test.vcd"); +// $dumpvars(0,test); + d = 0; + # 1; + if (q !== 2'b0) + begin + $display("FAILED - Q isn't 0 "); + $finish; + end + #1 ; + d = 1; + # 1; + if (q !== 2'b10) + begin + $display("FAILED - Q isn't 2 "); + $finish; + end + $display("PASSED"); + + end +endmodule diff --git a/ivtest/ivltests/basiclatch.v b/ivtest/ivltests/basiclatch.v new file mode 100644 index 000000000..d3e5aec2f --- /dev/null +++ b/ivtest/ivltests/basiclatch.v @@ -0,0 +1,80 @@ +// +// Copyright (c) 2002 Steven Wilson (steve@ka6s.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Synth of basic latch form +// +// +module basiclatch ( clk, d, q); +input clk, d; +output q; +reg q; + +always @ (clk or d) + if(~clk) + q = d; + +endmodule + +module tbench ; + +reg clk, d; + +basiclatch u_reg (clk,d,q); + +initial + begin + clk = 0; + d = 0; + #1 ; + if(q !== 0) + begin + $display("FAILED - initial value not 0"); + $finish; + end + #1 ; + clk = 1; + # 1; + d = 1; + # 1; + if(q !== 0) + begin + $display("FAILED - Didn't latch initial 0"); + $finish; + end + #1 + clk = 0; + # 1; + if(q !== 1) + begin + $display("FAILED - Didn't pass 1 after latch dropped"); + $finish; + end + #1 + clk = 1; + # 1; + d = 0; + # 1; + if(q !== 1) + begin + $display("FAILED - Didn't latch 1 after latch dropped"); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/basicreg.v b/ivtest/ivltests/basicreg.v new file mode 100644 index 000000000..dc802e3c1 --- /dev/null +++ b/ivtest/ivltests/basicreg.v @@ -0,0 +1,81 @@ +// +// Copyright (c) 2002 Steven Wilson (steve@ka6s.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Synth of basic reg form +// +// +module basicreg ( clk, d, q); +input clk, d; +output q; +reg q; + +(* ivl_synthesis_on *) +always @(posedge clk) + q <= d; + +endmodule + +module tbench ; + +reg clk, d; + +basicreg u_reg (clk,d,q); + +(* ivl_synthesis_off *) +initial + begin + clk = 0; + d = 0; + # 1; + clk = 1; + # 1; + if (q !== 0) + begin + $display("FAILED - Q isn't 0 on first edge"); + $finish; + end + d = 1; + # 1; + clk = 0; + # 1; + if (q !== 0) + begin + $display("FAILED - Q isn't 0 after first falling edge"); + $finish; + end + # 1; + d = 1; + clk = 1; + # 1; + if (q !== 1) + begin + $display("FAILED - Q isn't 1 2nd raising edge"); + $finish; + end + # 1; + clk = 0; + # 1; + if (q !== 1) + begin + $display("FAILED - Q isn't 1 after 2nd falling edge"); + $finish; + end + $display("PASSED"); + + end +endmodule diff --git a/ivtest/ivltests/basicstate.v b/ivtest/ivltests/basicstate.v new file mode 100644 index 000000000..0c943a9b1 --- /dev/null +++ b/ivtest/ivltests/basicstate.v @@ -0,0 +1,95 @@ +// +// Copyright (c) 2002 Steven Wilson (steve@ka6s.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: synth basic state machine form +// +// +module sm ( clk,rst,st); +input clk,rst; +output [1:0] st; + +reg [1:0] st; + +always @(posedge clk or posedge rst) + if (rst) + st <= 2'b0; + else + case (st) + 2'b00: st <= 2'b01; + 2'b01: st <= 2'b11; + 2'b11: st <= 2'b10; + 2'b10: st <= 2'b00; + endcase +endmodule + +module test ; + +reg clk,rst; + +wire [1:0] st; + +sm u_sm ( clk,rst,st); + +always #5 clk = ~clk; + +initial + begin +// $dumpfile("test.vcd"); +// $dumpvars(0,test); + clk = 0; + rst = 1; + @(posedge clk); + #1 ; + rst = 0; + if(st !== 2'b00) + begin + $display("FAILED - SM didn't initialize"); + $finish; + end + @(posedge clk); + #1 ; + if(st !== 2'b01) + begin + $display("FAILED - SM didn't xsn to 01"); + $finish; + end + @(posedge clk); + #1 ; + if(st !== 2'b11) + begin + $display("FAILED - SM didn't xsn to 11"); + $finish; + end + @(posedge clk); + #1 ; + if(st !== 2'b10) + begin + $display("FAILED - SM didn't xsn to 10"); + $finish; + end + @(posedge clk); + #1 ; + if(st !== 2'b00) + begin + $display("FAILED - SM didn't xsn to 00"); + $finish; + end + $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/basicstate2.v b/ivtest/ivltests/basicstate2.v new file mode 100644 index 000000000..7041c783a --- /dev/null +++ b/ivtest/ivltests/basicstate2.v @@ -0,0 +1,99 @@ +// +// Copyright (c) 2002 Steven Wilson (steve@ka6s.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Synth 2nd basic sm form +// +// +module sm ( clk,rst,st); +input clk,rst; +output [1:0] st; + +reg [1:0] st,next_st; + +always @(posedge clk or posedge rst) + if (rst) + st <= 2'b0; + else + st <= next_st; + +always @(st) + case (st) + 2'b00: next_st <= 2'b01; + 2'b01: next_st <= 2'b11; + 2'b11: next_st <= 2'b10; + 2'b10: next_st <= 2'b00; + endcase + +endmodule + +module test ; + +reg clk,rst; + +wire [1:0] st; + +sm u_sm ( clk,rst,st); + +always #5 clk = ~clk; + +initial + begin +// $dumpfile("test.vcd"); +// $dumpvars(0,test); + clk = 0; + rst = 1; + @(posedge clk); + #1 ; + rst = 0; + if(st !== 2'b00) + begin + $display("FAILED - SM didn't initialize"); + $finish; + end + @(posedge clk); + #1 ; + if(st !== 2'b01) + begin + $display("FAILED - SM didn't xsn to 01"); + $finish; + end + @(posedge clk); + #1 ; + if(st !== 2'b11) + begin + $display("FAILED - SM didn't xsn to 11"); + $finish; + end + @(posedge clk); + #1 ; + if(st !== 2'b10) + begin + $display("FAILED - SM didn't xsn to 10"); + $finish; + end + @(posedge clk); + #1 ; + if(st !== 2'b00) + begin + $display("FAILED - SM didn't xsn to 00"); + $finish; + end + $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/big_int.v b/ivtest/ivltests/big_int.v new file mode 100644 index 000000000..ef2269f5a --- /dev/null +++ b/ivtest/ivltests/big_int.v @@ -0,0 +1,163 @@ +// Note: when __ICARUS_UNSIZED__ is not defined, this test assumes integers +// are 32 bits wide. +module main(); + + reg [34:0] my_reg; + reg error; + reg [34:0] ref_val; + reg [34:0] ref_val2; + reg [7:0] count; + + + initial + begin + error = 0; + + // Create reference value that is bigger than 32 bits... + ref_val = 0; + ref_val[0] = 1; + ref_val[34] = 1; + $display("*:%d", ref_val); + + ref_val2 = 35'h7ffffffff; + $display("*:%d", ref_val2); + + // Trivial test to see that small unsized integers still work. + my_reg = 100; + if (my_reg != 'h64) + begin + error = 1; + $display("Error: expected 100"); + end + + my_reg = 17179869185; + $display("1:%d", my_reg); + +`ifdef __ICARUS_UNSIZED__ + // Ordinary compilers will truncate unsized integer + // constants to 32bits. Icarus Verilog is more generous. + if (my_reg !== 35'h4_00000001) begin + error = 1; + $display("Error: expected 17179869185"); + end + +`else + // Unsized integers bigger than 32 bits are truncated... + // Value below has bit 34 and bit 0 set to '1' + if (my_reg != 1) + begin + error = 1; + $display("Error: expected 1"); + end +`endif + + // Another unsized integer, but this time 'd specifier... + my_reg = 'd17179869184; + $display("2:%d", my_reg); + +`ifdef __ICARUS_UNSIZED__ + // Ordinary compilers will truncate unsized integer + // constants to 32bits. Icarus Verilog is more generous. + if (my_reg !== 35'h4_00000000) begin + error = 1; + $display("Error: expected 17179869184"); + end + +`else + if (my_reg != 0) + begin + error = 1; + $display("Error: expected 1"); + end +`endif + + // This should finally work! + my_reg = 35'sd17179869185; + $display("3:%d", my_reg); + + if (my_reg != ref_val) + begin + error = 1; + $display("Error: expected 17179869185"); + end + + // This should work too. + my_reg = 35'd 17179869185; + $display("4:%d", my_reg); + + if (my_reg != ref_val) + begin + error = 1; + $display("Error: expected 17179869185"); + end + + // Overflow... + my_reg = 35'd 34359738369; + $display("5:%d", my_reg); + + if (my_reg != 1) + begin + error = 1; + $display("Error: expected 1"); + end + + // Just no overflow + my_reg = 35'd 34359738367; + $display("6:%d", my_reg); + + if (my_reg != ref_val2) + begin + error = 1; + $display("Error: expected 34359738367"); + end + +`ifdef __ICARUS_UNSIZED__ + // Since Icarus Verilog doesn't truncate constant values, + // the whole idea of truncating then sign-extending the result + // to go into the wide reg does not apply. So skip this + // test. +`else + // Unsized integers bigger than 32 bits are truncated... + // Here all the bits are set. Since there is no 'd prefix, + // it will be sign extended later on. + my_reg = 17179869183; + $display("7:%d", my_reg); + + if (my_reg != ref_val2) + begin + error = 1; + $display("Error: expected 34359738367"); + end +`endif + // Unsized integers bigger than 32 bits are truncated... + // Here all the bits are set. Since there *IS* a 'd prefix + // it will NOT be sign extended later on. + my_reg = 'd17179869183; + $display("8:%d", my_reg); + +`ifdef __ICARUS_UNSIZED__ + if (my_reg != 'd17179869183) + begin + error = 1; + $display("Error: expected 'd17179869183"); + end +`else + if (my_reg != 'd4294967295) + begin + error = 1; + $display("Error: expected 4294967295"); + end +`endif + if (error==1) + begin + $display("FAILED"); + end + else + begin + $display("PASSED"); + end + + $finish; + end + +endmodule diff --git a/ivtest/ivltests/binary_nand.v b/ivtest/ivltests/binary_nand.v new file mode 100644 index 000000000..b77f80db3 --- /dev/null +++ b/ivtest/ivltests/binary_nand.v @@ -0,0 +1,78 @@ +// +// Copyright (c) 2002 Stephen Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// Binary ~& (nand) operator. + + +module main; + + reg A, B; + reg result1; + wire result2 = A ~& B; + + initial + begin + A = 0; + B = 0; + #1 result1 = A ~& B; + if (result1 !== 1'b1) begin + $display("FAILED"); + $finish; + end + if (result2 !== 1'b1) begin + $display("FAILED"); + $finish; + end + + A = 1; + #1 result1 = A ~& B; + if (result1 !== 1'b1) begin + $display("FAILED"); + $finish; + end + if (result2 !== 1'b1) begin + $display("FAILED"); + $finish; + end + + B = 1; + #1 result1 = A ~& B; + if (result1 !== 1'b0) begin + $display("FAILED"); + $finish; + end + if (result2 !== 1'b0) begin + $display("FAILED"); + $finish; + end + + A = 0; + #1 result1 = A ~& B; + if (result1 !== 1'b1) begin + $display("FAILED"); + $finish; + end + if (result2 !== 1'b1) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/binary_nor.v b/ivtest/ivltests/binary_nor.v new file mode 100644 index 000000000..54e13bdeb --- /dev/null +++ b/ivtest/ivltests/binary_nor.v @@ -0,0 +1,78 @@ +// +// Copyright (c) 2002 Stephen Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// Binary ~| (nor) operator. + + +module main; + + reg A, B; + reg result1; + wire result2 = A ~| B; + + initial + begin + A = 0; + B = 0; + #1 result1 = A ~| B; + if (result1 !== 1'b1) begin + $display("FAILED"); + $finish; + end + if (result2 !== 1'b1) begin + $display("FAILED"); + $finish; + end + + A = 1; + #1 result1 = A ~| B; + if (result1 !== 1'b0) begin + $display("FAILED"); + $finish; + end + if (result2 !== 1'b0) begin + $display("FAILED"); + $finish; + end + + B = 1; + #1 result1 = A ~| B; + if (result1 !== 1'b0) begin + $display("FAILED"); + $finish; + end + if (result2 !== 1'b0) begin + $display("FAILED"); + $finish; + end + + A = 0; + #1 result1 = A ~| B; + if (result1 !== 1'b0) begin + $display("FAILED"); + $finish; + end + if (result2 !== 1'b0) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/bitp1.v b/ivtest/ivltests/bitp1.v new file mode 100644 index 000000000..f550c53c1 --- /dev/null +++ b/ivtest/ivltests/bitp1.v @@ -0,0 +1,42 @@ +module test; + + bit b; + bit [9:0] b10; + bit signed bs; + bit unsigned bu; + bit signed [6:0] bs7; + bit unsigned [5:0] bu6; + + initial + begin + b = 1; + b10 = 100; + bs = 0; + bu = 1; + bs7 = -17; + bu6 = 21; + #1; + if (b * b10 !== 100) begin + $display ("FAILED 1"); + $finish; + end + if (bs * b10 !== 0) begin + $display ("FAILED 2" ); + $finish; + end + if (bu * b10 !== 100) begin + $display ("FAILED 3"); + $finish; + end + if (bs7 * 1 !== -17) begin + $display ("FAILED 4"); + $finish; + end + if (bu6 * b !== 21) begin + $display ("FAILED 5"); + $finish; + end + $display ("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/bits.v b/ivtest/ivltests/bits.v new file mode 100644 index 000000000..0b5d400ef --- /dev/null +++ b/ivtest/ivltests/bits.v @@ -0,0 +1,34 @@ +module main; + + reg foo_reg; + byte foo_byte; + int foo_int; + shortint foo_shortint; + longint foo_longint; + + initial begin + if ($bits(foo_reg) != 1) begin + $display("FAILED"); + $finish; + end + if ($bits(foo_byte) != 8) begin + $display("FAILED"); + $finish; + end + if ($bits(foo_int) != 32) begin + $display("FAILED"); + $finish; + end + if ($bits(foo_shortint) != 16) begin + $display("FAILED"); + $finish; + end + if ($bits(foo_longint) != 64) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/bits2.v b/ivtest/ivltests/bits2.v new file mode 100644 index 000000000..3226d4b01 --- /dev/null +++ b/ivtest/ivltests/bits2.v @@ -0,0 +1,55 @@ +module main; + + reg foo_reg; + byte foo_byte; + int foo_int; + shortint foo_shortint; + longint foo_longint; + bit foo_bit; + bit [13:0] foo14_bit; + logic foo_logic; + logic [10:0] foo11_logic; + + + initial begin + if ($bits(foo_reg) != 1) begin + $display("FAILED"); + $finish; + end + if ($bits(foo_byte) != 8) begin + $display("FAILED"); + $finish; + end + if ($bits(foo_int) != 32) begin + $display("FAILED"); + $finish; + end + if ($bits(foo_shortint) != 16) begin + $display("FAILED"); + $finish; + end + if ($bits(foo_longint) != 64) begin + $display("FAILED"); + $finish; + end + if ($bits(foo_bit) != 1) begin + $display("FAILED"); + $finish; + end + if ($bits(foo14_bit) != 14) begin + $display("FAILED"); + $finish; + end + if ($bits(foo_logic) != 1) begin + $display("FAILED"); + $finish; + end + if ($bits(foo11_logic) != 11) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + + end + +endmodule // main diff --git a/ivtest/ivltests/bitsel.v b/ivtest/ivltests/bitsel.v new file mode 100644 index 000000000..c0334b126 --- /dev/null +++ b/ivtest/ivltests/bitsel.v @@ -0,0 +1,13 @@ +module m; + + reg [15:8] r; + integer i; + +initial + begin + r = 8'b01101001; + for (i = 8; i <= 15; i = i + 1) + $display(r[i]); + end + +endmodule diff --git a/ivtest/ivltests/bitsel10.v b/ivtest/ivltests/bitsel10.v new file mode 100644 index 000000000..b34965c39 --- /dev/null +++ b/ivtest/ivltests/bitsel10.v @@ -0,0 +1,69 @@ +module main; + + wire [7:0] bus; + reg [7:0] HiZ; + assign bus = HiZ; + + reg E; + reg D; + reg CLK; + BUFT drv (bus[0], D, E, CLK); + + bufif0 drv0 (bus[0], D, E); + + initial begin + HiZ = 8'hzz; + D = 1; + E = 1; + CLK = 0; + #1 CLK = 1; + #1 if (bus !== 8'bzzzzzzz1) begin + $display("FAILED"); + $finish; + end + + if (drv.D !== D) begin + $display("FAILED (D)"); + $finish; + end + + E = 0; + #1 if (bus !== 8'bzzzzzzz1) begin + $display("FAILED"); + $finish; + end + + D = 0; + CLK = 0; + #1 CLK = 1; + + if (drv.D !== D) begin + $display("FAILED (D)"); + $finish; + end + + #1 D = 1; + #1 if (bus !== 8'bzzzzzzz1) begin + $display("FAILED"); + $finish; + end + + if (drv.D !== D) begin + $display("FAILED (D)"); + $finish; + end + $display("bus=%b, D=%b, drv.D=%b, E=%b, drv.save=%b", bus, D, drv.D, E, drv.save); + $display("PASSED"); + end // initial begin + +endmodule // main + +module BUFT(inout wire TO, input wire D, input wire E, input wire CLK); + + reg save; + assign TO = E? save : 2'bz; + + always @(posedge CLK) + save <= D; + +endmodule // BUFT diff --git a/ivtest/ivltests/bitsel2.v b/ivtest/ivltests/bitsel2.v new file mode 100644 index 000000000..d5ba45fd1 --- /dev/null +++ b/ivtest/ivltests/bitsel2.v @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2000 Steve Wilson (stevew@home.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This checks bit select from/to vectors with odd bit arrangements. + */ +module test; + + reg [1:4] a; + reg [4:1] b; + integer i; + + initial begin + a = 4'b1100; + for (i = 1 ; i <= 4 ; i = i + 1) + b[i] = a[i]; + + $display("a=%b, b=%b", a, b); + if (b !== 4'b0011) begin + $display("FAILED -- b == %b", b); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/bitsel3.v b/ivtest/ivltests/bitsel3.v new file mode 100644 index 000000000..02fc09a96 --- /dev/null +++ b/ivtest/ivltests/bitsel3.v @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2000 Steve Wilson (stevew@home.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This checks bit select from/to vectors with odd bit arrangements. + */ +module test; + + reg [4:1] a; + reg [1:4] b; + integer i; + + initial begin + a = 4'b1100; + for (i = 1 ; i <= 4 ; i = i + 1) + b[i] = a[i]; + + $display("a=%b, b=%b", a, b); + if (b !== 4'b0011) begin + $display("FAILED -- b == %b", b); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/bitsel4.v b/ivtest/ivltests/bitsel4.v new file mode 100644 index 000000000..563a41789 --- /dev/null +++ b/ivtest/ivltests/bitsel4.v @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Bit select of a net (a wire) using the index of a for loop. + */ + +module main; + + // Make a vector of bits, an array of functors in practice, and + // create a net that hooks to that array backwards. + reg [4:0] vect = 5'b10100; + wire [4:0] tmp = { vect[0], vect[1], vect[2], vect[3], vect[4] }; + + reg [2:0] idx; + initial begin + #1 $display("vect=%b, tmp=%b", vect, tmp); + + for (idx = 0 ; idx < 5 ; idx = idx + 1) begin + $display("idx=%d: vect=%b, tmp=%b", idx, vect[idx], tmp[idx]); + if (tmp[idx] !== vect[4-idx]) begin + $display("FAILED"); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/bitsel5.v b/ivtest/ivltests/bitsel5.v new file mode 100644 index 000000000..7fa2de3f7 --- /dev/null +++ b/ivtest/ivltests/bitsel5.v @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Bit select of a net (a wire) using the index of a for loop. + */ + +module main; + + // Make a vector of bits, an array of functors in practice, and + // create a net that hooks to that array backwards. + reg [5:1] vect = 5'b10100; + wire [5:1] tmp = { vect[1], vect[2], vect[3], vect[4], vect[5] }; + + reg [2:0] idx; + initial begin + #1 $display("vect=%b, tmp=%b", vect, tmp); + + for (idx = 1 ; idx <= 5 ; idx = idx + 1) begin + $display("idx=%d: vect=%b, tmp=%b", idx, vect[idx], tmp[idx]); + if (tmp[idx] !== vect[6-idx]) begin + $display("FAILED"); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/bitsel6.v b/ivtest/ivltests/bitsel6.v new file mode 100644 index 000000000..bc533b790 --- /dev/null +++ b/ivtest/ivltests/bitsel6.v @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test was inspired by PR#539. We check that the calculated bit + * select of a net in a continuous assignment gets bits in the right + * order and position. The trick here is that the bits are numbered + * from MSB to LSB. + */ + +module main; + + reg [0:63] target0 = 64'h0040200000000000; + reg [1:64] target1 = 64'h0040200000000000; + reg [6:0] idx; + + wire mux0 = target0[idx]; + wire mux1 = target1[idx+1]; + + initial begin + $display( "Using constant indices:" ); + $display( " %b=v[ 9]", target0[ 9] ); + if (target0[9] !== 1'b1) begin + $display("FAILED -- target0[9] != 1"); + $finish; + end + + $display( " %b=v[18]", target0[18] ); + if (target0[18] !== 1'b1) begin + $display("FAILED -- target0[18] != 1"); + $finish; + end + + $display( " %b=v[45]", target0[45] ); + if (target0[45] !== 1'b0) begin + $display("FAILED -- target0[45] != 0"); + $finish; + end + + $display( " %b=v[54]", target0[54] ); + if (target0[54] !== 1'b0) begin + $display("FAILED -- target0[54] != 0"); + $finish; + end + + $display( "Using calcuated indices:" ); + for (idx = 0 ; idx < 64 ; idx = idx + 1) begin + #1 $display("target0[%2d]=%b, mux0=%b", idx, target0[idx], mux0); + $display("target1[%2d]=%b, mux1=%b", idx+1, target1[idx+1], mux1); + + if (target0[idx] !== mux0) begin + $display("FAILED -- target0[idx] != mux0"); + $finish; + end + + if (target1[idx+1] !== mux1) begin + $display("FAILED -- target1[idx+1] != mux1"); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/bitsel7.v b/ivtest/ivltests/bitsel7.v new file mode 100644 index 000000000..0ace21fce --- /dev/null +++ b/ivtest/ivltests/bitsel7.v @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test was inspired by PR#539. We check that the calculated bit + * select of a net in a continuous assignment gets bits in the right + * order and position. The trick here is that the bits are numbered + * from MSB to LSB. + */ + +module main; + + reg [63:0] target0 = 64'h0040_2000_0000_0000; + reg [64:1] target1 = 64'h0040_2000_0000_0000; + reg [6:0] idx; + + wire mux0 = target0[idx]; + wire mux1 = target1[idx+1]; + + initial begin + $display( "Using constant indices:" ); + $display( " %b=v[45]", target0[45] ); + if (target0[45] !== 1'b1) begin + $display("FAILED -- target0[45] != 1"); + $finish; + end + + $display( " %b=v[54]", target0[54] ); + if (target0[54] !== 1'b1) begin + $display("FAILED -- target0[54] != 1"); + $finish; + end + + $display( " %b=v[18]", target0[18] ); + if (target0[18] !== 1'b0) begin + $display("FAILED -- target0[18] != 0"); + $finish; + end + + $display( " %b=v[ 9]", target0[9] ); + if (target0[9] !== 1'b0) begin + $display("FAILED -- target0[ 9] != 0"); + $finish; + end + + $display( "Using calcuated indices:" ); + for (idx = 0 ; idx < 64 ; idx = idx + 1) begin + #1 $display("target0[%2d]=%b, mux0=%b", idx, target0[idx], mux0); + $display("target1[%2d]=%b, mux1=%b", idx+1, target1[idx+1], mux1); + + if (target0[idx] !== mux0) begin + $display("FAILED -- target0[idx] != mux0"); + $finish; + end + + if (target1[idx+1] !== mux1) begin + $display("FAILED -- target1[idx+1] != mux1"); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/bitsel8.v b/ivtest/ivltests/bitsel8.v new file mode 100644 index 000000000..20c8a438a --- /dev/null +++ b/ivtest/ivltests/bitsel8.v @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test was derived from PR615.v + **/ +module main(); + parameter INIT_00 = 32'hffffffff; + reg [4:0] c; + initial begin + + c = 0; + $display("%b",INIT_00[c]); + if (INIT_00[c] !== 1'b1) begin + $display("FAILED"); + $finish; + end + + c = 1; + $display("%b",INIT_00[c]); + if (INIT_00[c] !== 1'b1) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/bitsel9.v b/ivtest/ivltests/bitsel9.v new file mode 100644 index 000000000..a3c24967a --- /dev/null +++ b/ivtest/ivltests/bitsel9.v @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test was derived from PR617.v + **/ +module main(); + parameter INIT_00 = 32'hffffffff; + reg [17:0] t; + reg [8:0] c; + + initial begin + t = {17'd0,INIT_00[0]}<<1; + $display("%b",t); + if (t !== 18'b00_0000_0000_0000_0010) begin + $display("FAILED"); + $finish; + end + + c = 0; + t = {17'd0,INIT_00[c]}<<1; + $display("%b",t); + if (t !== 18'b00_0000_0000_0000_0010) begin + $display("FAILED"); + $finish; + end + + c = 16; + t = {17'd0,INIT_00[c]}<<1; + $display("%b",t); + if (t !== 18'b00_0000_0000_0000_0010) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/bitwidth.v b/ivtest/ivltests/bitwidth.v new file mode 100644 index 000000000..75bd9fa2d --- /dev/null +++ b/ivtest/ivltests/bitwidth.v @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + wire [31:0] A; + wire [24:0] B; + reg [15:0] C; + + assign A = B; + assign B = C; + + initial begin + C = 0; + #1 if (A !== 32'h0) begin + $display("FAILED -- A === %h", A); + $finish; + end + + C = -1; + #1 if (A !== 32'h00_00_ff_ff) begin + $display("FAILED -- A == %h instead of 0000ffff", A); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/bitwidth2.v b/ivtest/ivltests/bitwidth2.v new file mode 100644 index 000000000..33454e702 --- /dev/null +++ b/ivtest/ivltests/bitwidth2.v @@ -0,0 +1,15 @@ +module ternary; + + wire [5:0] a; + wire [6:0] b; + wire c; + + wire [5:0] d = c ? a : b; + + initial + begin + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/bitwidth3.v b/ivtest/ivltests/bitwidth3.v new file mode 100644 index 000000000..97518b525 --- /dev/null +++ b/ivtest/ivltests/bitwidth3.v @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2004 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +module main(); + + reg [4:0] sum; + + initial begin + + // Self-determined expressions take their size from the + // operands. The compiler should thus make the constant + // expression below exactly 4 bits wide. + + $display("Should be 0001: %b", 4'd7 + 4'd10); + + if ($bits(4'd7 + 4'd10) != 4) begin + $display("FAILED -- bit width should be 4: %d", + $bits(4'd7 + 4'd10)); + $finish; + end + + // When assigning to an l-value, the expression, and + // by extension the operands, take on the width of the + // left side. This expansion should be passed all the + // way down the expression. + + sum = 4'd7 + 4'd10; + $display("Should be 10001: %b", sum); + + if (sum !== 5'b1_0001) begin + $display("FAILED -- expression truncated?"); + $finish; + end + + $display("PASSED"); + end + + +endmodule diff --git a/ivtest/ivltests/blankport.v b/ivtest/ivltests/blankport.v new file mode 100644 index 000000000..dae2e90b2 --- /dev/null +++ b/ivtest/ivltests/blankport.v @@ -0,0 +1,67 @@ +// +// Copyright (c) 1999 Stephan Boettcher (stephan@nevis1.nevis.columbia.edu) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - PR 204 report - validates correct use of blank ports. + +module none; + reg x; +endmodule // none + +module empty(); + reg x; +endmodule // none + +module one (a); + input a; + reg x; +endmodule // one + +module two (a, b); + input a, b; + reg x; +endmodule // two + +module three (a, b, c); + input a, b, c; + reg x; +endmodule // two + +module main; + + wire w1, w2, w3, w4, w5, w6, w7, w8, w9; + + none U1 (); + empty U2 (); + one U3 (); + one U4 (w1); + one U5 (.a(w2)); + two U6 (); + two U7 (,); + two U8 (w3,); + two U9 (,w4); + two Ua (w5,w6); + two Ub (.a(w7)); + two Uc (.b(w8)); + two Ud (.b(w8),.a(w9)); + three Ue (); + //three Uf (,); //XXXX I doubt this is legal... ? + three Ug (,,); + + initial $display("PASSED"); + +endmodule // main diff --git a/ivtest/ivltests/block_only_with_var_def.v b/ivtest/ivltests/block_only_with_var_def.v new file mode 100644 index 000000000..6cfba41da --- /dev/null +++ b/ivtest/ivltests/block_only_with_var_def.v @@ -0,0 +1,14 @@ +module a; + initial begin : b + reg x; + end + initial fork : c + reg x; + join + + initial begin + a.b.x = 1'b0; + a.c.x = 1'b1; + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/blocking_repeat_ec.v b/ivtest/ivltests/blocking_repeat_ec.v new file mode 100644 index 000000000..d8a010bab --- /dev/null +++ b/ivtest/ivltests/blocking_repeat_ec.v @@ -0,0 +1,41 @@ +module top; + reg pass = 1'b1; + + integer count; + reg clk = 0, in = 0; + reg result; + + always #10 clk = ~clk; + always #20 in = ~in; + + initial begin + count = 3; + result = repeat(count) @(posedge clk) in; + if ($simtime != 30 && result != 1'b0) begin + $display("Failed blocking repeat(3) at %0t, expected 1'b0, got %b", + $simtime, result); + pass = 1'b0; + end + + #15; + count = 0; + result = repeat(count) @(posedge clk) in; + if ($simtime != 45 && result != 1'b1) begin + $display("Failed blocking repeat(0) at %0t, expected 1'b1, got %b", + $simtime, result); + pass = 1'b0; + end + + #20; + count = -1; + result = repeat(count) @(posedge clk) in; + if ($simtime != 55 && result != 1'b0) begin + $display("Failed blocking repeat(0) at %0t, expected 1'b0, got %b", + $simtime, result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/blocksynth1.v b/ivtest/ivltests/blocksynth1.v new file mode 100644 index 000000000..fd3a32725 --- /dev/null +++ b/ivtest/ivltests/blocksynth1.v @@ -0,0 +1,57 @@ +/* + * blocksyn1.v + * This tests synthesis where statements in a block override previous + * statements in a block and also uses other previous statements in the + * block. Note in this example that the flag assignment is completely + * overruled by the conditional that is directly after it. + */ +module main; + + reg [1:0] out; + reg flag; + reg [1:0] sel; + + (* ivl_synthesis_on, ivl_combinational *) + always @* + begin + case (sel) + 2'b00: out = 2'b11; + 2'b01: out = 2'b10; + 2'b10: out = 2'b01; + 2'b11: out = 2'b00; + endcase // case(sel) + + // This flag is completely overridden by the contintional, so + // the synthesizer should drop it. + flag = 1'b0; + if (out == 2'b00) + flag = 1'b1; + else + flag = 1'b0; + end + + reg [2:0] idx; + reg test; + + (* ivl_synthesis_off *) + initial begin + for (idx = 0 ; idx < 7 ; idx = idx + 1) begin + sel = idx[1:0]; + #1 if (out !== ~sel) begin + $display("FAILED -- sel=%b, out=%b, flag=%b", sel, out, flag); + $finish; + end + + test = (out == 2'b00)? 1'b1 : 1'b0; + + if (test !== flag) begin + $display("FAILED -- test=%b, sel=%b, out=%b, flag=%b", + test, sel, out, flag); + $finish; + end + end // for (idx = 0 ; idx < 7 ; idx = idx + 1) + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/blocksynth2.v b/ivtest/ivltests/blocksynth2.v new file mode 100644 index 000000000..5eb77d375 --- /dev/null +++ b/ivtest/ivltests/blocksynth2.v @@ -0,0 +1,58 @@ +/* + * blocksyn1.v + * This tests synthesis where statements in a block override previous + * statements in a block and also uses other previous statements in the + * block. Note in this example that the flag assignment is completely + * overruled by the conditional that is directly after it. + */ +module main; + + reg [1:0] out; + reg flag; + reg [1:0] sel; + + (* ivl_synthesis_on, ivl_combinational *) + always @* + begin + out = 2'b00; + case (sel) + 2'b00: out = 2'b11; + 2'b01: out = 2'b10; + 2'b10: out = 2'b01; + // out for sel==2'b11 should be inherited from previous statement + endcase // case(sel) + + // This flag is completely overridden by the conditional, so + // the synthesizer should drop it. + flag = 1'b0; + if (out == 2'b00) + flag = 1'b1; + else + flag = 1'b0; + end + + reg [2:0] idx; + reg test; + + (* ivl_synthesis_off *) + initial begin + for (idx = 0 ; idx < 7 ; idx = idx + 1) begin + sel = idx[1:0]; + #1 if (out !== ~sel) begin + $display("FAILED -- sel=%b, out=%b, flag=%b", sel, out, flag); + $finish; + end + + test = (out == 2'b00)? 1'b1 : 1'b0; + + if (test !== flag) begin + $display("FAILED -- test=%b, sel=%b, out=%b, flag=%b", + test, sel, out, flag); + $finish; + end + end // for (idx = 0 ; idx < 7 ; idx = idx + 1) + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/blocksynth3.v b/ivtest/ivltests/blocksynth3.v new file mode 100644 index 000000000..ee540a1ae --- /dev/null +++ b/ivtest/ivltests/blocksynth3.v @@ -0,0 +1,56 @@ +/* + * blocksyn1.v + * This tests synthesis where statements in a block override previous + * statements in a block and also uses other previous statements in the + * block. Note in this example that the flag assignment is completely + * overruled by the conditional that is directly after it. + */ +module main; + + reg [1:0] out; + reg flag; + reg [1:0] sel; + + (* ivl_synthesis_on, ivl_combinational *) + always @* + begin + out = 2'b00; + case (sel) + 2'b00: out = 2'b11; + 2'b01: out = 2'b10; + 2'b10: out = 2'b01; + endcase // case(sel) + + // This flag is overridded by the true clause, so the + // synthesizer should move the first assignment to the + // else clause of the if. + flag = 1'b0; + if (out == 2'b00) + flag = 1'b1; + end + + reg [2:0] idx; + reg test; + + (* ivl_synthesis_off *) + initial begin + for (idx = 0 ; idx < 7 ; idx = idx + 1) begin + sel = idx[1:0]; + #1 if (out !== ~sel) begin + $display("FAILED -- sel=%b, out=%b, flag=%b", sel, out, flag); + $finish; + end + + test = (out == 2'b00)? 1'b1 : 1'b0; + + if (test !== flag) begin + $display("FAILED -- test=%b, sel=%b, out=%b, flag=%b", + test, sel, out, flag); + $finish; + end + end // for (idx = 0 ; idx < 7 ; idx = idx + 1) + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/bnot.v b/ivtest/ivltests/bnot.v new file mode 100644 index 000000000..9320515e9 --- /dev/null +++ b/ivtest/ivltests/bnot.v @@ -0,0 +1,42 @@ +module test; + reg a,b; + integer x; + initial begin + x=10; + + // ok + a=x; + + // fails at run time with + // vvm_func.cc:49: failed assertion `v.nbits == p.nbits' + // Abort (core dumped) + b = ~x; + + if (b === 1'b1) + $display("PASSED"); + else + $display("FAILED --- b = %b", b); + + end // initial begin +endmodule // test + + + +/* + * Copyright (c) 2000 Gerard A. Allan (gaa@ee.ed.ac.uk) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ diff --git a/ivtest/ivltests/bool1.v b/ivtest/ivltests/bool1.v new file mode 100644 index 000000000..04be7e43e --- /dev/null +++ b/ivtest/ivltests/bool1.v @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2005 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test the bool type used as an index to a for loop, and in a + * few other minor cases. + */ +module main; + + reg bool [31:0] idx; + reg logic [7:0] tmp; + + initial begin + + idx = 7; + tmp = 7; + $display("Dispay of 7s: %d, %d", idx, tmp); + + for (idx = 0 ; idx < 17 ; idx = idx + 1) begin + tmp = idx[7:0]; + if (tmp != idx[7:0]) begin + $display("FAILED -- %b != %b", tmp, idx[7:0]); + $finish; + end + + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/br1000.v b/ivtest/ivltests/br1000.v new file mode 100644 index 000000000..c03257b5f --- /dev/null +++ b/ivtest/ivltests/br1000.v @@ -0,0 +1,36 @@ +module loop(); + +reg [3:0] a; +reg [3:0] b; +reg [3:0] c; +reg [3:0] d; + +integer i; + +always @* begin + for (i = 0; i < 4; i = i + 1) begin + b[i] = a[i]; + $display("process 1 : %0d %b", i, b); + end +end + +always @* begin + for (i = 0; i < 4; i = i + 1) begin + d[i] = c[i]; + $display("process 2 : %0d %b", i, d); + end +end + +initial begin + #0; + a = 5; + #0; + c = 6; + #0; + if ((b === 5) && (c === 6)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br1001.v b/ivtest/ivltests/br1001.v new file mode 100644 index 000000000..08bf64153 --- /dev/null +++ b/ivtest/ivltests/br1001.v @@ -0,0 +1,20 @@ +module submod(inout a); + +endmodule + +module topmod(); + +wand x; +wor y; + +submod m1(.a(x)); +submod m2(.a(y)); + +initial begin + if ((x === 1'bz) && (y === 1'bz)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br1003a.v b/ivtest/ivltests/br1003a.v new file mode 100644 index 000000000..10c22457e --- /dev/null +++ b/ivtest/ivltests/br1003a.v @@ -0,0 +1,34 @@ +timeunit 100ps / 10ps; + +class testclass; + task delay(output [63:0] t); + begin + $printtimescale(top); + $printtimescale; + #5ns t = $time; + end + endtask +endclass + +module top(); + +timeunit 1ns / 1ps; + +testclass tc; + +reg [63:0] t1; +reg [63:0] t2; + +initial begin + $printtimescale; + tc = new; + tc.delay(t1); + t2 = $time; + $display("%0d %0d", t1, t2); + if ((t1 === 50) && (t2 === 5)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br1003b.v b/ivtest/ivltests/br1003b.v new file mode 100644 index 000000000..a4888818e --- /dev/null +++ b/ivtest/ivltests/br1003b.v @@ -0,0 +1,29 @@ +timeunit 100ps / 10ps; + +task delay(output [63:0] t); + begin + $printtimescale(top); + $printtimescale; + #5ns t = $time; + end +endtask + +module top(); + +timeunit 1ns / 1ps; + +reg [63:0] t1; +reg [63:0] t2; + +initial begin + $printtimescale; + delay(t1); + t2 = $time; + $display("%0d %0d", t1, t2); + if ((t1 === 50) && (t2 === 5)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br1003c.v b/ivtest/ivltests/br1003c.v new file mode 100644 index 000000000..1cf6f2ec5 --- /dev/null +++ b/ivtest/ivltests/br1003c.v @@ -0,0 +1,29 @@ +timeunit 100ps / 10ps; + +function [63:0] delay(input dummy); + begin + $printtimescale(top); + $printtimescale; + delay = 5ns; + end +endfunction + +module top(); + +timeunit 1ns / 1ps; + +reg [63:0] t1; +reg [63:0] t2; + +initial begin + $printtimescale; + t1 = delay(0); + t2 = 5ns; + $display("%0d %0d", t1, t2); + if ((t1 === 50) && (t2 === 5)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br1003d.v b/ivtest/ivltests/br1003d.v new file mode 100644 index 000000000..6cf38ba82 --- /dev/null +++ b/ivtest/ivltests/br1003d.v @@ -0,0 +1,33 @@ +timeunit 100ps / 10ps; + +package testpackage; + task delay(output [63:0] t); + begin + $printtimescale(top); + $printtimescale; + #5ns t = $time; + end + endtask +endpackage + +module top(); + +timeunit 1ns / 1ps; + +import testpackage::delay; + +reg [63:0] t1; +reg [63:0] t2; + +initial begin + $printtimescale; + delay(t1); + t2 = $time; + $display("%0d %0d", t1, t2); + if ((t1 === 50) && (t2 === 5)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br1004.v b/ivtest/ivltests/br1004.v new file mode 100644 index 000000000..427dfe88b --- /dev/null +++ b/ivtest/ivltests/br1004.v @@ -0,0 +1,25 @@ +package foobar; + +class aclass; + bit tested = 0; + + task test; + begin + $display("Testing classes in packages"); + tested = 1; + end + endtask +endclass + aclass bar = new; +endpackage + +module test; + import foobar::*; + initial begin + bar.test; + if (bar.tested) + $display("PASSED"); + else + $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/br1005.v b/ivtest/ivltests/br1005.v new file mode 100644 index 000000000..c66737174 --- /dev/null +++ b/ivtest/ivltests/br1005.v @@ -0,0 +1,38 @@ +class aclass; + reg [3:0] q[$]; +endclass + +module test; + +aclass a; + +reg [3:0] d; + +reg failed = 0; + +initial begin + a = new; + a.q.push_back(4'd1); + a.q.push_back(4'd2); + a.q.push_back(4'd3); + a.q.push_back(4'd4); + d = a.q.pop_front(); + $display("%h", d); + if (d !== 4'd1) failed = 1; + d = a.q.pop_front(); + $display("%h", d); + if (d !== 4'd2) failed = 1; + d = a.q.pop_front(); + $display("%h", d); + if (d !== 4'd3) failed = 1; + d = a.q.pop_front(); + $display("%h", d); + if (d !== 4'd4) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br1006.v b/ivtest/ivltests/br1006.v new file mode 100644 index 000000000..26e82f6f4 --- /dev/null +++ b/ivtest/ivltests/br1006.v @@ -0,0 +1,39 @@ +module dut( + input wire [3:0] i, + output wire [3:0] o +); + +assign o = i; + +specify + (i[3:0] => o[3:0]) = (1, 1); +endspecify + +endmodule + +module top(); + +reg [3:0] i; +wire [3:0] o; + +dut dut(i, o); + +reg failed = 0; + +initial begin + $monitor($time,,i,,o); + #1 i = 4'd1; + #0 if (o !== 4'bx) failed = 1; + #1 i = 4'd2; + #0 if (o !== 4'd1) failed = 1; + #1; + #0 if (o !== 4'd2) failed = 1; + #1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br1007.v b/ivtest/ivltests/br1007.v new file mode 100644 index 000000000..fdb2354b2 --- /dev/null +++ b/ivtest/ivltests/br1007.v @@ -0,0 +1,38 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module test(); + +reg [4:1] value; + +reg failed; + +initial begin + failed = 0; + value = 4'b0000; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + value[5] = 1'b1; +`endif + $display("%b", value); + if (value !== 4'b0000) failed = 1; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + value[5:5] = 1'b1; +`endif + $display("%b", value); + if (value !== 4'b0000) failed = 1; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + value[5:4] = 2'b11; +`else + value[4] = 1'b1; +`endif + $display("%b", value); + if (value !== 4'b1000) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br1008.v b/ivtest/ivltests/br1008.v new file mode 100644 index 000000000..195ef41d6 --- /dev/null +++ b/ivtest/ivltests/br1008.v @@ -0,0 +1,14 @@ + +module test(); + + wire [3:0] a = 4'd0; + + wire signed [3:0] b[1:0]; + + assign b[0] = $signed(a); + + initial begin + $display("b = [%b %b]", b[1], b[0]); + end + +endmodule diff --git a/ivtest/ivltests/br1015a.v b/ivtest/ivltests/br1015a.v new file mode 100644 index 000000000..7d2d36f1f --- /dev/null +++ b/ivtest/ivltests/br1015a.v @@ -0,0 +1,32 @@ +module test(); + +function parity(input bit_array[3:0]); + +integer i; + +begin + parity = 0; + for (i = 0; i < 4; i = i + 1) begin + $display("%b", bit_array[i]); + parity ^= bit_array[i]; + end +end + +endfunction + +reg a[3:0]; +reg p; + +initial begin + a[0] = 1; + a[1] = 0; + a[2] = 1; + a[3] = 1; + p = parity(a); + if (p === 1) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br1015b.v b/ivtest/ivltests/br1015b.v new file mode 100644 index 000000000..7d2d36f1f --- /dev/null +++ b/ivtest/ivltests/br1015b.v @@ -0,0 +1,32 @@ +module test(); + +function parity(input bit_array[3:0]); + +integer i; + +begin + parity = 0; + for (i = 0; i < 4; i = i + 1) begin + $display("%b", bit_array[i]); + parity ^= bit_array[i]; + end +end + +endfunction + +reg a[3:0]; +reg p; + +initial begin + a[0] = 1; + a[1] = 0; + a[2] = 1; + a[3] = 1; + p = parity(a); + if (p === 1) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br1019.v b/ivtest/ivltests/br1019.v new file mode 100644 index 000000000..b062510c3 --- /dev/null +++ b/ivtest/ivltests/br1019.v @@ -0,0 +1,30 @@ +module sub(input [3:0] value); + +wire [3:0] array[1:0]; +reg [3:0] monitor; + +assign array[0] = $unsigned(value); + +always @(array[0]) begin + monitor = array[0]; +end + +endmodule + +module top; + +wire [3:0] value; + +sub sub1(value); +sub sub2(value); + +initial begin + force value = 5; + #0; + if ((sub1.monitor === 5) && (sub2.monitor === 5)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br1025.v b/ivtest/ivltests/br1025.v new file mode 100644 index 000000000..17d28e06b --- /dev/null +++ b/ivtest/ivltests/br1025.v @@ -0,0 +1,30 @@ +function int f (int arg); + + begin:b // comment to remove bug + + int i; + f = 0; + for (i=0; iRHS -- array_bg0 = 'b%b", array_bg0); err=err+1; end + if (array_bg1 !== 16'b0111_1111_1111_1111) begin $display("FAILED -- LHS>RHS -- array_bg1 = 'b%b", array_bg1); err=err+1; end + if (array_bg2 !== 16'bxxxx_xxxx_0111_1111) begin $display("FAILED -- LHS>RHS -- array_bg2 = 'b%b", array_bg2); err=err+1; end + if (array_bg3 !== 16'b0111_1111_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_bg3 = 'b%b", array_bg3); err=err+1; end + if (array_bg4 !== 16'bxxxx_xxxx_xxxx_0111) begin $display("FAILED -- LHS>RHS -- array_bg4 = 'b%b", array_bg4); err=err+1; end + if (array_bg5 !== 16'b0111_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_bg5 = 'b%b", array_bg5); err=err+1; end + if (array_bg6 !== 16'bxxxx_xxxx_xxxx_xx01) begin $display("FAILED -- LHS>RHS -- array_bg6 = 'b%b", array_bg6); err=err+1; end + if (array_bg7 !== 16'b01xx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_bg7 = 'b%b", array_bg7); err=err+1; end + //if (array_bg8 !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS>RHS -- array_bg8 = 'b%b", array_bg8); err=err+1; end + //if (array_bg9 !== 16'b1xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_bg9 = 'b%b", array_bg9); err=err+1; end + + // test write to array LHS=RHS + array_lt0 = {WA*WB{1'bx}}; + array_lt1 = {WA*WB{1'bx}}; array_lt1 = {WA *WB +0{1'b1}}; + array_lt2 = {WA*WB{1'bx}}; array_lt2 [0 :WA/2-1] = {WA/2*WB +0{1'b1}}; + array_lt3 = {WA*WB{1'bx}}; array_lt3 [WA/2:WA -1] = {WA/2*WB +0{1'b1}}; + array_lt4 = {WA*WB{1'bx}}; array_lt4 [0 ] = {1 *WB +0{1'b1}}; + array_lt5 = {WA*WB{1'bx}}; array_lt5 [ WA -1] = {1 *WB +0{1'b1}}; + array_lt6 = {WA*WB{1'bx}}; array_lt6 [0 ][0 :WB/2-1] = {1 *WB/2+0{1'b1}}; + array_lt7 = {WA*WB{1'bx}}; array_lt7 [ WA -1][WB/2:WB -1] = {1 *WB/2+0{1'b1}}; + array_lt8 = {WA*WB{1'bx}}; array_lt8 [0 ][0 ] = {1 *1 +0{1'b1}}; + array_lt9 = {WA*WB{1'bx}}; array_lt9 [ WA -1][ WB -1] = {1 *1 +0{1'b1}}; + // check + if (array_lt0 !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS=RHS -- array_lt0 = 'b%b", array_lt0); err=err+1; end + if (array_lt1 !== 16'b1111_1111_1111_1111) begin $display("FAILED -- LHS=RHS -- array_lt1 = 'b%b", array_lt1); err=err+1; end + if (array_lt2 !== 16'b1111_1111_xxxx_xxxx) begin $display("FAILED -- LHS=RHS -- array_lt2 = 'b%b", array_lt2); err=err+1; end + if (array_lt3 !== 16'bxxxx_xxxx_1111_1111) begin $display("FAILED -- LHS=RHS -- array_lt3 = 'b%b", array_lt3); err=err+1; end + if (array_lt4 !== 16'b1111_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS=RHS -- array_lt4 = 'b%b", array_lt4); err=err+1; end + if (array_lt5 !== 16'bxxxx_xxxx_xxxx_1111) begin $display("FAILED -- LHS=RHS -- array_lt5 = 'b%b", array_lt5); err=err+1; end + if (array_lt6 !== 16'b11xx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS=RHS -- array_lt6 = 'b%b", array_lt6); err=err+1; end + if (array_lt7 !== 16'bxxxx_xxxx_xxxx_xx11) begin $display("FAILED -- LHS=RHS -- array_lt7 = 'b%b", array_lt7); err=err+1; end + if (array_lt8 !== 16'b1xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS=RHS -- array_lt8 = 'b%b", array_lt8); err=err+1; end + if (array_lt9 !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS=RHS -- array_lt9 = 'b%b", array_lt9); err=err+1; end + + // test write to array LHSRHS -- array_lt0 = 'b%b", array_lt0); err=err+1; end + if (array_lt1 !== 16'b0111_1111_1111_1111) begin $display("FAILED -- LHS>RHS -- array_lt1 = 'b%b", array_lt1); err=err+1; end + if (array_lt2 !== 16'b0111_1111_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_lt2 = 'b%b", array_lt2); err=err+1; end + if (array_lt3 !== 16'bxxxx_xxxx_0111_1111) begin $display("FAILED -- LHS>RHS -- array_lt3 = 'b%b", array_lt3); err=err+1; end + if (array_lt4 !== 16'b0111_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_lt4 = 'b%b", array_lt4); err=err+1; end + if (array_lt5 !== 16'bxxxx_xxxx_xxxx_0111) begin $display("FAILED -- LHS>RHS -- array_lt5 = 'b%b", array_lt5); err=err+1; end + if (array_lt6 !== 16'b01xx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_lt6 = 'b%b", array_lt6); err=err+1; end + if (array_lt7 !== 16'bxxxx_xxxx_xxxx_xx01) begin $display("FAILED -- LHS>RHS -- array_lt7 = 'b%b", array_lt7); err=err+1; end + //if (array_lt8 !== 16'b1xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_lt8 = 'b%b", array_lt8); err=err+1; end + //if (array_lt9 !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS>RHS -- array_lt9 = 'b%b", array_lt9); err=err+1; end + + // assign a constant value to the array + array_bg1 = {WA*WB{1'b1}}; + array_bg2 = {WA*WB{1'b1}}; + array_bg3 = {WA*WB{1'b1}}; + array_bg4 = {WA*WB{1'b1}}; + array_bg5 = {WA*WB{1'b1}}; + array_bg6 = {WA*WB{1'b1}}; + array_bg7 = {WA*WB{1'b1}}; + array_bg8 = {WA*WB{1'b1}}; + array_bg9 = {WA*WB{1'b1}}; + + // test read from array LHS=RHS + array_1d1 = {WA*WB+1{1'bx}}; array_1d1[WA *WB -1+0:0] = array_bg1 ; + array_1d2 = {WA*WB+1{1'bx}}; array_1d2[WA/2*WB -1+0:0] = array_bg2 [WA/2-1:0 ] ; + array_1d3 = {WA*WB+1{1'bx}}; array_1d3[WA/2*WB -1+0:0] = array_bg3 [WA -1:WA/2] ; + array_1d4 = {WA*WB+1{1'bx}}; array_1d4[1 *WB -1+0:0] = array_bg4 [ 0 ] ; + array_1d5 = {WA*WB+1{1'bx}}; array_1d5[1 *WB -1+0:0] = array_bg5 [WA -1 ] ; + array_1d6 = {WA*WB+1{1'bx}}; array_1d6[1 *WB/2-1+0:0] = array_bg6 [ 0 ][WB/2-1:0 ]; + array_1d7 = {WA*WB+1{1'bx}}; array_1d7[1 *WB/2-1+0:0] = array_bg7 [WA -1 ][WB -1:WB/2]; + array_1d8 = {WA*WB+1{1'bx}}; array_1d8[1 *1 -1+0:0] = array_bg8 [ 0 ][ 0 ]; + array_1d9 = {WA*WB+1{1'bx}}; array_1d9[1 *1 -1+0:0] = array_bg9 [WA -1 ][WB -1 ]; + // check + if (array_1d1 !== 17'bx_1111_1111_1111_1111) begin $display("FAILED -- LHS=RHS BE -- array_1d1 = 'b%b", array_1d1); err=err+1; end + if (array_1d2 !== 17'bx_xxxx_xxxx_1111_1111) begin $display("FAILED -- LHS=RHS BE -- array_1d2 = 'b%b", array_1d2); err=err+1; end + if (array_1d3 !== 17'bx_xxxx_xxxx_1111_1111) begin $display("FAILED -- LHS=RHS BE -- array_1d3 = 'b%b", array_1d3); err=err+1; end + if (array_1d4 !== 17'bx_xxxx_xxxx_xxxx_1111) begin $display("FAILED -- LHS=RHS BE -- array_1d4 = 'b%b", array_1d4); err=err+1; end + if (array_1d5 !== 17'bx_xxxx_xxxx_xxxx_1111) begin $display("FAILED -- LHS=RHS BE -- array_1d5 = 'b%b", array_1d5); err=err+1; end + if (array_1d6 !== 17'bx_xxxx_xxxx_xxxx_xx11) begin $display("FAILED -- LHS=RHS BE -- array_1d6 = 'b%b", array_1d6); err=err+1; end + if (array_1d7 !== 17'bx_xxxx_xxxx_xxxx_xx11) begin $display("FAILED -- LHS=RHS BE -- array_1d7 = 'b%b", array_1d7); err=err+1; end + if (array_1d8 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS=RHS BE -- array_1d8 = 'b%b", array_1d8); err=err+1; end + if (array_1d9 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS=RHS BE -- array_1d9 = 'b%b", array_1d9); err=err+1; end + + // test read from array LHS>RHS + array_1d1 = {WA*WB+1{1'bx}}; array_1d1[WA *WB -1+1:0] = array_bg1 ; + array_1d2 = {WA*WB+1{1'bx}}; array_1d2[WA/2*WB -1+1:0] = array_bg2 [WA/2-1:0 ] ; + array_1d3 = {WA*WB+1{1'bx}}; array_1d3[WA/2*WB -1+1:0] = array_bg3 [WA -1:WA/2] ; + array_1d4 = {WA*WB+1{1'bx}}; array_1d4[1 *WB -1+1:0] = array_bg4 [ 0 ] ; + array_1d5 = {WA*WB+1{1'bx}}; array_1d5[1 *WB -1+1:0] = array_bg5 [WA -1 ] ; + array_1d6 = {WA*WB+1{1'bx}}; array_1d6[1 *WB/2-1+1:0] = array_bg6 [ 0 ][WB/2-1:0 ]; + array_1d7 = {WA*WB+1{1'bx}}; array_1d7[1 *WB/2-1+1:0] = array_bg7 [WA -1 ][WB -1:WB/2]; + array_1d8 = {WA*WB+1{1'bx}}; array_1d8[1 *1 -1+1:0] = array_bg8 [ 0 ][ 0 ]; + array_1d9 = {WA*WB+1{1'bx}}; array_1d9[1 *1 -1+1:0] = array_bg9 [WA -1 ][WB -1 ]; + // check + if (array_1d1 !== 17'b0_1111_1111_1111_1111) begin $display("FAILED -- LHS>RHS BE -- array_1d1 = 'b%b", array_1d1); err=err+1; end + if (array_1d2 !== 17'bx_xxxx_xxx0_1111_1111) begin $display("FAILED -- LHS>RHS BE -- array_1d2 = 'b%b", array_1d2); err=err+1; end + if (array_1d3 !== 17'bx_xxxx_xxx0_1111_1111) begin $display("FAILED -- LHS>RHS BE -- array_1d3 = 'b%b", array_1d3); err=err+1; end + if (array_1d4 !== 17'bx_xxxx_xxxx_xxx0_1111) begin $display("FAILED -- LHS>RHS BE -- array_1d4 = 'b%b", array_1d4); err=err+1; end + if (array_1d5 !== 17'bx_xxxx_xxxx_xxx0_1111) begin $display("FAILED -- LHS>RHS BE -- array_1d5 = 'b%b", array_1d5); err=err+1; end + if (array_1d6 !== 17'bx_xxxx_xxxx_xxxx_x011) begin $display("FAILED -- LHS>RHS BE -- array_1d6 = 'b%b", array_1d6); err=err+1; end + if (array_1d7 !== 17'bx_xxxx_xxxx_xxxx_x011) begin $display("FAILED -- LHS>RHS BE -- array_1d7 = 'b%b", array_1d7); err=err+1; end + if (array_1d8 !== 17'bx_xxxx_xxxx_xxxx_xx01) begin $display("FAILED -- LHS>RHS BE -- array_1d8 = 'b%b", array_1d8); err=err+1; end + if (array_1d9 !== 17'bx_xxxx_xxxx_xxxx_xx01) begin $display("FAILED -- LHS>RHS BE -- array_1d9 = 'b%b", array_1d9); err=err+1; end + + // test read from array LHSRHS LE -- array_1d1 = 'b%b", array_1d1); err=err+1; end + if (array_1d2 !== 17'bx_xxxx_xxx0_1111_1111) begin $display("FAILED -- LHS>RHS LE -- array_1d2 = 'b%b", array_1d2); err=err+1; end + if (array_1d3 !== 17'bx_xxxx_xxx0_1111_1111) begin $display("FAILED -- LHS>RHS LE -- array_1d3 = 'b%b", array_1d3); err=err+1; end + if (array_1d4 !== 17'bx_xxxx_xxxx_xxx0_1111) begin $display("FAILED -- LHS>RHS LE -- array_1d4 = 'b%b", array_1d4); err=err+1; end + if (array_1d5 !== 17'bx_xxxx_xxxx_xxx0_1111) begin $display("FAILED -- LHS>RHS LE -- array_1d5 = 'b%b", array_1d5); err=err+1; end + if (array_1d6 !== 17'bx_xxxx_xxxx_xxxx_x011) begin $display("FAILED -- LHS>RHS LE -- array_1d6 = 'b%b", array_1d6); err=err+1; end + if (array_1d7 !== 17'bx_xxxx_xxxx_xxxx_x011) begin $display("FAILED -- LHS>RHS LE -- array_1d7 = 'b%b", array_1d7); err=err+1; end + if (array_1d8 !== 17'bx_xxxx_xxxx_xxxx_xx01) begin $display("FAILED -- LHS>RHS LE -- array_1d8 = 'b%b", array_1d8); err=err+1; end + if (array_1d9 !== 17'bx_xxxx_xxxx_xxxx_xx01) begin $display("FAILED -- LHS>RHS LE -- array_1d9 = 'b%b", array_1d9); err=err+1; end + + // test read from array LHS +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for bug report #942: VHDL function bodies in arch declaration not +// supported + +module br942_test(); +logic clk, rst, q; +e dut(clk, rst, q); + +initial begin + rst = 1; + clk = 0; + #1; + + clk = 1; + #1; + + rst = 0; + clk = 0; + if(q !== 1'b0) begin + $display("FAILED 1"); + $finish(); + end + #1; + + clk = 1; + #1; + + clk = 0; + if(q !== 1'b1) begin + $display("FAILED 2"); + $finish(); + end + #1; + clk = 1; + #1; + + if(q !== 1'b0) begin + $display("FAILED 3"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/br942.vhd b/ivtest/ivltests/br942.vhd new file mode 100644 index 000000000..93bd64e08 --- /dev/null +++ b/ivtest/ivltests/br942.vhd @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity e is + port ( + clk : in std_logic; + rst : in std_logic; + q : out std_logic); +end e; + +architecture a of e is + + signal r : std_logic; + + function invert ( + i : std_logic) + return std_logic is + begin + return not i; + end invert; +begin + + q <= r; + + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + r <= '0'; + else + r <= invert(r); + end if; + end if; + end process; +end a; diff --git a/ivtest/ivltests/br943_944.v b/ivtest/ivltests/br943_944.v new file mode 100644 index 000000000..b2a76d3d9 --- /dev/null +++ b/ivtest/ivltests/br943_944.v @@ -0,0 +1,54 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for bug reports: +// #943: VHDL enum values not available outside of switch statements +// #944: VHDL enum type declaration generates syntax errors + +module bg943_test(); +logic clk, rst, q; +e dut(clk, rst, q); + +initial begin + clk = 0; + rst = 1; + #1; + + clk = 1; + #1; + if(q !== 1'b0) begin + $display("FAILED 1"); + $finish(); + end + #1; + + clk = 0; + rst = 0; + #1; + + clk = 1; + #1; + if(q !== 1'b1) begin + $display("FAILED 2"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/br943_944.vhd b/ivtest/ivltests/br943_944.vhd new file mode 100644 index 000000000..ae5f1c6e4 --- /dev/null +++ b/ivtest/ivltests/br943_944.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity e is + port ( + clk : in std_logic; + rst : in std_logic; + q : out std_logic); +end e; + +architecture a of e is + + type t is (one, zero); + signal r : t; + +begin + + q <= '1' when r = one else '0'; + + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + r <= zero; + else + case r is + when zero => r <= one; + when others => r <= zero; + end case; + end if; + end if; + end process; +end a; diff --git a/ivtest/ivltests/br946.v b/ivtest/ivltests/br946.v new file mode 100644 index 000000000..72770bc37 --- /dev/null +++ b/ivtest/ivltests/br946.v @@ -0,0 +1,16 @@ +module test(); + +integer src; +reg dst; + +initial begin + assign dst = src; + src = 1; + #1 $display(dst); + if (dst === 1) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br947.v b/ivtest/ivltests/br947.v new file mode 100644 index 000000000..af026f37e --- /dev/null +++ b/ivtest/ivltests/br947.v @@ -0,0 +1,37 @@ +// Regression test for SF bug 947 : Procedural continuous assignment +// affects other structural connections to source vector. + +`timescale 1ns/1ps + +module test(); + +wire delay0; +wire delay1; +wire delay2; +reg select; +reg out; + +assign #100 delay0 = 1; +assign #100 delay1 = delay0; +assign #100 delay2 = delay1; + +always @(select) begin + if (select) + assign out = delay2; + else + assign out = delay0; +end + +initial begin + $monitor($time,, delay0,, delay1,, delay2,, out); + select = 0; + #250; + select = 1; + #300; + if ((delay0 == 1) && (delay1 == 1) && (delay2 == 1) && (out == 1)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br948.v b/ivtest/ivltests/br948.v new file mode 100644 index 000000000..63ed238f8 --- /dev/null +++ b/ivtest/ivltests/br948.v @@ -0,0 +1,70 @@ +module top; + reg pass; + reg in; + reg pout; + wire out; + + function invert; + input in; + // When this is a named block the compiler creates a fork/join to + // create the new scope. The problem with this is that of_EXEC_UFUNC + // opcode does not work correctly since the vthread_run(child) call + // returns when the join is executed which then copies the return value + // before the function body code has actually run. This causes the + // results to be delayed by one call. Does this need to be split into + // two functions. One that acts like fork and copies the input values + // and one that acts like join and returns the function result? + // It appears that procedural user function calls work correctly since + // they use fork/join to call the user function. + // Both V0.9 and development have this problem. + begin: block_name + invert = ~in; + $display("Function should return %b when given %b.", invert, in); + end + endfunction + + assign out = invert(in); + + initial begin + pass = 1'b1; + + in = 1'b0; + #1; + if (out !== 1'b1) begin + $display("CA result was %b when given %b, expect 1'b1.", out, in); + pass = 1'b0; + end + pout = invert(in); + if (pout !== 1'b1) begin + $display("Result was %b when given %b, expect 1'b1.", pout, in); + pass = 1'b0; + end + + in = 1'b1; + #1; + if (out !== 1'b0) begin + $display("CA result was %b when given %b, expect 1'b0.", out, in); + pass = 1'b0; + end + pout = invert(in); + if (pout !== 1'b0) begin + $display("Result was %b when given %b, expect 1'b0.", pout, in); + pass = 1'b0; + end + + in = 1'bz; + #1; + if (out !== 1'bx) begin + $display("CA result was %b when given %b, expect 1'bx.", out, in); + pass = 1'b0; + end + pout = invert(in); + if (pout !== 1'bx) begin + $display("Result was %b when given %b, expect 1'bx.", pout, in); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/br955.v b/ivtest/ivltests/br955.v new file mode 100644 index 000000000..b11729b5a --- /dev/null +++ b/ivtest/ivltests/br955.v @@ -0,0 +1,107 @@ +`timescale 1 ps / 1 ps + +module mux_2_to_1 + ( + input sel_i, + input [1:0] dat_i, + output dat_o + ); + + assign dat_o = sel_i && dat_i[1] || ~sel_i && dat_i[0]; + +endmodule + +module mux_n_to_1 + #( + parameter sel_w = 4, + parameter n_inputs = 2**sel_w + ) + ( + input [n_inputs-1:0] inputs_i, + input [sel_w-1:0] sel_i, + output output_o + ); + + genvar i,j; + generate + if(sel_w == 1) begin + mux_2_to_1 mux_simple + ( + .sel_i(sel_i), + .dat_i(inputs_i), + .dat_o(output_o) + ); + end else begin + wire [n_inputs-2:0] inter_w; + + for(i=0; i Z) = (0.1, 0.2); + (EN => Z) = (0.3, 0.4); + endspecify +endmodule + +module ckt (out, in, en); + output out; + input in, en; + + TBUF_X2 dut (.A ( in ) , .EN ( en ) , .Z ( out ) ) ; +endmodule + +module top; + wire out; + reg in, en; + + ckt dut(out, in, en); + + initial begin + $monitor($realtime,,out,"=",in,,en); + $sdf_annotate("ivltests/br960a.sdf", dut); + in = 1'b0; + en = 1'b0; + $display("Max (X->Z)"); + // X -> Z = max(enable)) + #10; + en = 1'b1; + $display("Fall (Z->0)"); + // Z -> 0 = tf(enable) + #10; + en = 1'b0; + $display("Rise (0->Z)"); + // 0 -> Z = tr(enable) + #5; + in = 1'b1; + #5; + en = 1'b1; + $display("Rise (Z->1)"); + // Z -> 1 = tr(enable) + #10; + en = 1'b0; + $display("Fall (1->Z)"); + // 1 -> Z = tf(enable) + #10; + end +endmodule diff --git a/ivtest/ivltests/br960b.sdf b/ivtest/ivltests/br960b.sdf new file mode 100644 index 000000000..4a4c2f3b3 --- /dev/null +++ b/ivtest/ivltests/br960b.sdf @@ -0,0 +1,13 @@ +(DELAYFILE + (TIMESCALE 1ns) + + (CELL + (CELLTYPE "TBUF_X2") + (INSTANCE dut) + (DELAY (ABSOLUTE + (IOPATH A Z (0.2) (0.3) (0.4)) + (IOPATH EN Z (1.2) (1.3) (1.4)) + )) + ) + +) diff --git a/ivtest/ivltests/br960b.v b/ivtest/ivltests/br960b.v new file mode 100644 index 000000000..3c393a543 --- /dev/null +++ b/ivtest/ivltests/br960b.v @@ -0,0 +1,56 @@ +`timescale 1ns/10ps + +module TBUF_X2 (A, EN, Z); + input A; + input EN; + output Z; + + bufif1(Z, A, EN); + + specify + (A => Z) = (0.1, 0.2); + (EN => Z) = (0.3, 0.4); + endspecify +endmodule + +module ckt (out, in, en); + output out; + input in, en; + + TBUF_X2 dut (.A ( in ) , .EN ( en ) , .Z ( out ) ) ; +endmodule + +module top; + wire out; + reg in, en; + + ckt dut(out, in, en); + + initial begin + $monitor($realtime,,out,"=",in,,en); + $sdf_annotate("ivltests/br960b.sdf", dut); + in = 1'b0; + en = 1'b0; + $display("Max (X->Z)"); + // X -> Z = max(enable)) + #10; + en = 1'b1; + $display("Fall (Z->0)"); + // Z -> 0 = tf(enable) + #10; + en = 1'b0; + $display("To High-Z (0->Z)"); + // 0 -> Z = to High-Z + #5; + in = 1'b1; + #5; + en = 1'b1; + $display("Rise (Z->1)"); + // Z -> 1 = tr(enable) + #10; + en = 1'b0; + $display("To High-Z (1->Z)"); + // 1 -> Z = to High-Z + #10; + end +endmodule diff --git a/ivtest/ivltests/br960c.sdf b/ivtest/ivltests/br960c.sdf new file mode 100644 index 000000000..94dafb089 --- /dev/null +++ b/ivtest/ivltests/br960c.sdf @@ -0,0 +1,13 @@ +(DELAYFILE + (TIMESCALE 1ns) + + (CELL + (CELLTYPE "TBUF_X2") + (INSTANCE dut) + (DELAY (ABSOLUTE + (IOPATH A Z () () (0.2) (0.3) (0.4) (0.5)) + (IOPATH EN Z () () (1.2) (1.3) (1.4) (1.5)) + )) + ) + +) diff --git a/ivtest/ivltests/br960c.v b/ivtest/ivltests/br960c.v new file mode 100644 index 000000000..a48cc5b69 --- /dev/null +++ b/ivtest/ivltests/br960c.v @@ -0,0 +1,52 @@ +`timescale 1ns/10ps + +module TBUF_X2 (A, EN, Z); + input A; + input EN; + output Z; + + bufif1(Z, A, EN); + + specify + (A => Z) = (0.1, 0.2); + (EN => Z) = (0.3, 0.4); + endspecify +endmodule + +module ckt (out, in, en); + output out; + input in, en; + + TBUF_X2 dut (.A ( in ) , .EN ( en ) , .Z ( out ) ) ; +endmodule + +module top; + wire out; + reg in, en; + + ckt dut(out, in, en); + + initial begin + $monitor($realtime,,out,"=",in,,en); + $sdf_annotate("ivltests/br960c.sdf", dut); + in = 1'b0; + en = 1'b0; + $display("Max (X->Z)"); + // X -> Z = max(enable)) + #10; + en = 1'b1; + $display("Z->0"); + #10; + en = 1'b0; + $display("0->Z"); + #5; + in = 1'b1; + #5; + en = 1'b1; + $display("Z->1"); + #10; + en = 1'b0; + $display("1->Z"); + #10; + end +endmodule diff --git a/ivtest/ivltests/br960d.sdf b/ivtest/ivltests/br960d.sdf new file mode 100644 index 000000000..89b76f109 --- /dev/null +++ b/ivtest/ivltests/br960d.sdf @@ -0,0 +1,13 @@ +(DELAYFILE + (TIMESCALE 1ns) + + (CELL + (CELLTYPE "TBUF_X2") + (INSTANCE dut) + (DELAY (ABSOLUTE + (IOPATH A Z (0.2)) + (IOPATH EN Z (1.2)) + )) + ) + +) diff --git a/ivtest/ivltests/br960d.v b/ivtest/ivltests/br960d.v new file mode 100644 index 000000000..940bfa6bc --- /dev/null +++ b/ivtest/ivltests/br960d.v @@ -0,0 +1,56 @@ +`timescale 1ns/10ps + +module TBUF_X2 (A, EN, Z); + input A; + input EN; + output Z; + + bufif1(Z, A, EN); + + specify + (A => Z) = (0.1, 0.2); + (EN => Z) = (0.3, 0.4); + endspecify +endmodule + +module ckt (out, in, en); + output out; + input in, en; + + TBUF_X2 dut (.A ( in ) , .EN ( en ) , .Z ( out ) ) ; +endmodule + +module top; + wire out; + reg in, en; + + ckt dut(out, in, en); + + initial begin + $monitor($realtime,,out,"=",in,,en); + $sdf_annotate("ivltests/br960d.sdf", dut); + in = 1'b0; + en = 1'b0; + $display("Max (X->Z)"); + // X -> Z = max(enable)) + #10; + en = 1'b1; + $display("Fall (Z->0)"); + // Z -> 0 = tr(enable) + #10; + en = 1'b0; + $display("Rise (0->Z)"); + // 0 -> Z = tr(enable) + #5; + in = 1'b1; + #5; + en = 1'b1; + $display("Rise (Z->1)"); + // Z -> 1 = tr(enable) + #10; + en = 1'b0; + $display("Fall (1->Z)"); + // 1 -> Z = tr(enable) + #10; + end +endmodule diff --git a/ivtest/ivltests/br961.v b/ivtest/ivltests/br961.v new file mode 100644 index 000000000..d44272b72 --- /dev/null +++ b/ivtest/ivltests/br961.v @@ -0,0 +1,26 @@ +module test; + +localparam w = 8; + +function [w-1:0] copy; + +input [w-1:0] w; + +begin + copy = w; +end + +endfunction + +reg [w-1:0] value; + +initial begin + value = copy(21); + $display("%d", value); + if (value === 21) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br961a.v b/ivtest/ivltests/br961a.v new file mode 100644 index 000000000..68e770e24 --- /dev/null +++ b/ivtest/ivltests/br961a.v @@ -0,0 +1,14 @@ +// Check the compiler fails gracefully +module test; + +function [w-1:0] copy; + +input [w-1:0] z; + +begin + copy = z; +end + +endfunction + +endmodule diff --git a/ivtest/ivltests/br962.v b/ivtest/ivltests/br962.v new file mode 100644 index 000000000..298af4558 --- /dev/null +++ b/ivtest/ivltests/br962.v @@ -0,0 +1,39 @@ +// Regression test for br962 - based on test case provided in bug report +module qtest; + parameter width = 32; + parameter depth = 32; + + reg [width-1:0] values[$]; + reg [$clog2(depth)+width-1:0] sum1; + reg [$clog2(depth)+width-1:0] sum2; + + task new_sample; + input [width-1:0] data; + + int i; + + begin + reg [width-1:0] popped; + if (values.size >= depth) + sum1 = sum1 - values.pop_back(); + sum1 = sum1 + data; + values.push_front(data); + sum2 = 0; + for (i = 0; i < values.size; i++) begin + sum2 = sum2 + values[i]; + end + $display("sum1 = %d sum2 = %d", sum1, sum2); + if (sum1 !== sum2) begin + $display("FAILED"); + $finish; + end + end + endtask + + initial begin + sum1 = 0; + repeat (2*depth) new_sample({$random}); + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/br963.v b/ivtest/ivltests/br963.v new file mode 100644 index 000000000..086f39c21 --- /dev/null +++ b/ivtest/ivltests/br963.v @@ -0,0 +1,40 @@ +// Regression test for br962 - based on test case provided in bug report +module qtest; + parameter width = 32; + parameter depth = 32; + + reg [width-1:0] values[$]; + reg [$clog2(depth)+width-1:0] sum1; + reg [$clog2(depth)+width-1:0] sum2; + + task new_sample; + input [width-1:0] data; + int i; + begin + reg [width-1:0] popped; + if (values.size >= depth) + begin : foo + popped = values.pop_back(); + sum1 = sum1 - popped; + end + sum1 = sum1 + data; + values.push_front(data); + sum2 = 0; + for (i = 0; i < values.size; i++) begin + sum2 = sum2 + values[i]; + end + $display("sum1 = %d sum2 = %d", sum1, sum2); + if (sum1 !== sum2) begin + $display("FAILED"); + $finish; + end + end + endtask + + initial begin + sum1 = 0; + repeat (2*depth) new_sample({$random}); + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/br965.v b/ivtest/ivltests/br965.v new file mode 100644 index 000000000..78043fa11 --- /dev/null +++ b/ivtest/ivltests/br965.v @@ -0,0 +1,29 @@ +module top; + +wire [2:0] value = 2; + +shim shim( + .bit0(value[0]), + .bit1(value[1]), + .bit2(value[2]) +); + +endmodule + +module shim( + inout wire bit0, + inout wire bit1, + inout wire bit2 +); + +wire [2:0] value = {bit2, bit1, bit0}; + +initial begin + #1 $display(value); + if (value === 2) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br967.v b/ivtest/ivltests/br967.v new file mode 100644 index 000000000..4663050e6 --- /dev/null +++ b/ivtest/ivltests/br967.v @@ -0,0 +1,16 @@ +module test(); + +integer count = 0; + +initial begin + repeat (10.4) begin + count = count + 1; + $display(count); + end + if (count === 10) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br968.v b/ivtest/ivltests/br968.v new file mode 100644 index 000000000..7738a7f2d --- /dev/null +++ b/ivtest/ivltests/br968.v @@ -0,0 +1,42 @@ +module top; + reg passed; + reg [7:0] val; + reg signed [7:0] sval; + real rval; + + initial begin + passed = 1'b1; + val = 8'hff; + sval = 8'hff; + /* Check a constant unsigned value cast to signed. */ + rval = $itor($signed(8'hff)); + if (rval != -1.0) begin + $display("Failed unsigned constant cast to signed conversion, ", + "expected -1.0, got %g.", rval); + passed = 1'b0; + end + /* Check an unsigned variable cast to signed. */ + rval = $itor($signed(val)); + if (rval != -1.0) begin + $display("Failed unsigned variable cast to signed conversion, ", + "expected -1.0, got %g.", rval); + passed = 1'b0; + end + /* Check a constant signed value. */ + rval = $itor(8'shff); + if (rval != -1.0) begin + $display("Failed signed constant conversion, ", + "expected -1.0, got %g.", rval); + passed = 1'b0; + end + /* Check a variable signed value. */ + rval = $itor(sval); + if (rval != -1.0) begin + $display("Failed signed variable conversion, ", + "expected -1.0, got %g.", rval); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/br971.v b/ivtest/ivltests/br971.v new file mode 100644 index 000000000..8aeb4463a --- /dev/null +++ b/ivtest/ivltests/br971.v @@ -0,0 +1,21 @@ +// Icarus doesn't properly support variable expressions on the right hand +// side of a procedural CA - see bug 605. + +module test(); + +reg [1:0] addr; +reg [3:0] memory[3:0]; +reg [3:0] data; + +initial begin + assign data = memory[addr]; + addr = 1; + memory[addr] = 2; + #0 $display("%d", data); + if (data === 2) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br972.v b/ivtest/ivltests/br972.v new file mode 100644 index 000000000..4de404e51 --- /dev/null +++ b/ivtest/ivltests/br972.v @@ -0,0 +1,29 @@ +module test(); + +reg in; +wire out; + +assign out = out | in; + +reg failed; + +initial begin + #1 in = 0; + #0 $display("out = %b", out); + if (out !== 1'bx) failed = 1; + #1 in = 1; + #0 $display("out = %b", out); + if (out !== 1'b1) failed = 1; + #1 in = 0; + #0 $display("out = %b", out); + if (out !== 1'b1) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); + + $finish; +end + +endmodule diff --git a/ivtest/ivltests/br973.v b/ivtest/ivltests/br973.v new file mode 100644 index 000000000..fb275f917 --- /dev/null +++ b/ivtest/ivltests/br973.v @@ -0,0 +1,20 @@ +// Regression test for bug #973 + +module test(); + +typedef enum bit { A0, A1 } A; +typedef enum logic { B0, B1 } B; +typedef enum reg { C0, C1 } C; + +A enum1; +B enum2; +C enum3; + +initial begin + if ($bits(enum1) == 1 && $bits(enum2) == 1 && $bits(enum3) == 1) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br974a.v b/ivtest/ivltests/br974a.v new file mode 100644 index 000000000..19744df64 --- /dev/null +++ b/ivtest/ivltests/br974a.v @@ -0,0 +1,40 @@ +typedef logic data_t; + +module dut(i, o); + +input data_t i; +output data_t o; + +always @* o = i; + +endmodule + +module test(); + +data_t i, o; + +dut dut(i, o); + +reg failed = 0; + +initial begin + i = 1'b0; + #0 $display(i,,o); + if (o !== 1'b0) failed = 1; + i = 1'b1; + #0 $display(i,,o); + if (o !== 1'b1) failed = 1; + i = 1'bx; + #0 $display(i,,o); + if (o !== 1'bx) failed = 1; + i = 1'bz; + #0 $display(i,,o); + if (o !== 1'bz) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br974b.v b/ivtest/ivltests/br974b.v new file mode 100644 index 000000000..e2b99f052 --- /dev/null +++ b/ivtest/ivltests/br974b.v @@ -0,0 +1,29 @@ +module dut(i, o); + +input logic [3:0] i; +output logic [3:0] o; + +always @* o = i; + +endmodule + +module test(); + +logic [3:0] i, o; + +dut dut(i, o); + +reg failed = 0; + +initial begin + i = 4'b01xz; + #0 $display("%b %b", i, o); + if (o !== 4'b01xz) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br974c.v b/ivtest/ivltests/br974c.v new file mode 100644 index 000000000..9759f89f0 --- /dev/null +++ b/ivtest/ivltests/br974c.v @@ -0,0 +1,32 @@ +module dut(i, o); + +input [3:0] i; +output [3:0] o; + +wire logic [3:0] i; +reg [3:0] o; + +always @* o = i; + +endmodule + +module test(); + +logic [3:0] i, o; + +dut dut(i, o); + +reg failed = 0; + +initial begin + i = 4'b01xz; + #0 $display("%b %b", i, o); + if (o !== 4'b01xz) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br975.v b/ivtest/ivltests/br975.v new file mode 100644 index 000000000..fe8f1f9ee --- /dev/null +++ b/ivtest/ivltests/br975.v @@ -0,0 +1,23 @@ +// Test error handling for duplicate variable declarations. + +module bug(); + +typedef struct packed { + logic value; +} data_t; + +typedef enum { A, B } enum_t; + +wire w1; +wire w1; + +data_t d1; +data_t d1; + +enum_t e1; +enum_t e1; + +reg r1; +reg r1; + +endmodule diff --git a/ivtest/ivltests/br977.v b/ivtest/ivltests/br977.v new file mode 100644 index 000000000..3e5364536 --- /dev/null +++ b/ivtest/ivltests/br977.v @@ -0,0 +1,14 @@ +`define DECLAREINT(name, i) integer name=i + +module foo(); + +`DECLAREINT(bar, 2); + +initial begin + if (bar === 2) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br978.v b/ivtest/ivltests/br978.v new file mode 100644 index 000000000..699c189a7 --- /dev/null +++ b/ivtest/ivltests/br978.v @@ -0,0 +1,16 @@ +module test(); + +wire [15:0] data = 8; +wire [15:0] result; + +assign result = data + $ivlh_to_unsigned(8, 16); + +initial begin + #1 $display("result = %0d", result); + if (result === 16) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br979.v b/ivtest/ivltests/br979.v new file mode 100644 index 000000000..97ef08a56 --- /dev/null +++ b/ivtest/ivltests/br979.v @@ -0,0 +1,28 @@ +`define my_macro(a,b) localparam `` i``a``b``j = 8'h``a``b; \ +\ + +module test(); + +`my_macro(0,1) + +`my_macro( 2, 3) + +`my_macro( 4 , 5 ) + +reg failed = 0; + +initial begin + $display("%h", i01j); + if (i01j !== 8'h01) failed = 1; + $display("%h", i23j); + if (i23j !== 8'h23) failed = 1; + $display("%h", i45j); + if (i45j !== 8'h45) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br982.v b/ivtest/ivltests/br982.v new file mode 100644 index 000000000..e695ab718 --- /dev/null +++ b/ivtest/ivltests/br982.v @@ -0,0 +1,15 @@ +module example; + task simple_task; + input in; + output out; + begin + out = in; + end + endtask + + reg x = 0; + initial begin + simple_task(x); + $finish; + end +endmodule diff --git a/ivtest/ivltests/br982a.v b/ivtest/ivltests/br982a.v new file mode 100644 index 000000000..e96e04cf3 --- /dev/null +++ b/ivtest/ivltests/br982a.v @@ -0,0 +1,14 @@ +module example; + function simple_func; + input in; + begin + simple_func = in; + end + endfunction + + reg x = 0; + initial begin + x = simple_func(x,x); + $finish; + end +endmodule diff --git a/ivtest/ivltests/br982b.v b/ivtest/ivltests/br982b.v new file mode 100644 index 000000000..e09fab4f1 --- /dev/null +++ b/ivtest/ivltests/br982b.v @@ -0,0 +1,15 @@ +module example; + task simple_task; + input in; + output out; + begin + out = in; + end + endtask + + reg x = 0; + initial begin + simple_task(x,x,x); + $finish; + end +endmodule diff --git a/ivtest/ivltests/br985.v b/ivtest/ivltests/br985.v new file mode 100644 index 000000000..aee114a32 --- /dev/null +++ b/ivtest/ivltests/br985.v @@ -0,0 +1,48 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +module br985_test; +logic [3:0] sel; +logic value, spi_sdo; +bug3 dut(sel, value, spi_sdo); + +initial begin + int i; + sel = 4'b0000; + + #1 if(spi_sdo !== 1'b1) + begin + $display("FAILED"); + $finish(); + end + + for(i = 1; i < 16; i = i + 1) + begin + sel = i; + #1 if(spi_sdo !== 1'b0) + begin + $display("FAILED"); + $finish(); + end + end + + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br985.vhd b/ivtest/ivltests/br985.vhd new file mode 100644 index 000000000..a3b2e217f --- /dev/null +++ b/ivtest/ivltests/br985.vhd @@ -0,0 +1,19 @@ +-- Reduced test case, bug originally found in 4DSP's fmc110_ctrl.vhd +library ieee; + use ieee.std_logic_1164.all; + +entity bug3 is +port ( + sel : in std_logic_vector(3 downto 0); + value : in std_logic; + spi_sdo : out std_logic +); +end bug3; + +architecture bug3_syn of bug3 is +begin + +-- no problem if the "not" is taken out +spi_sdo <= not or_reduce(sel); + +end bug3_syn; diff --git a/ivtest/ivltests/br986.v b/ivtest/ivltests/br986.v new file mode 100644 index 000000000..67109dc5e --- /dev/null +++ b/ivtest/ivltests/br986.v @@ -0,0 +1,30 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +module br987_test; +logic clk_i, clk_ib, clk_o; +bug3 dut(clk_i, clk_ib, clk_o); + +initial begin + // it is enough to have the test unit compiled + $display("PASSED"); +end + +endmodule + diff --git a/ivtest/ivltests/br986.vhd b/ivtest/ivltests/br986.vhd new file mode 100644 index 000000000..25aa16b48 --- /dev/null +++ b/ivtest/ivltests/br986.vhd @@ -0,0 +1,53 @@ +-- Reduced test case, bug originally found in 4DSP's fmc110_ctrl.vhd +library ieee; + use ieee.std_logic_1164.all; + +entity bug3 is +port ( + clk1_i : in std_logic; + clk1_ib : in std_logic; + clk1_o : out std_logic +); +end bug3; + +architecture bug3_syn of bug3 is + +component IBUFDS generic ( + DIFF_TERM : boolean := FALSE +); port( + O : out std_logic; + I : in std_logic; + IB : in std_logic +); end component; + +begin + +ibufds1 : ibufds + generic map ( + DIFF_TERM => TRUE -- change to "1" and vhdlpp is happy + ) +port map ( + i => clk1_i, + ib => clk1_ib, + o => clk1_o +); + +end bug3_syn; + +entity ibufds is +generic ( + DIFF_TERM : boolean := FALSE +); +port ( + i : in std_logic; + ib : in std_logic; + o : out std_logic +); +end ibufds; + +architecture ibufds_sim of ibufds is + +begin +o <= i; + +end ibufds_sim; diff --git a/ivtest/ivltests/br987.v b/ivtest/ivltests/br987.v new file mode 100644 index 000000000..2a65a152f --- /dev/null +++ b/ivtest/ivltests/br987.v @@ -0,0 +1,32 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +module br987_test; +logic clk, trig, data_o; +bug5 dut(clk, trig, data_o); + +initial begin + trig = 1; + clk = 0; + #1 clk = ~clk; + #1 clk = ~clk; + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br987.vhd b/ivtest/ivltests/br987.vhd new file mode 100644 index 000000000..dedd232f4 --- /dev/null +++ b/ivtest/ivltests/br987.vhd @@ -0,0 +1,20 @@ +-- Reduced test case, bug originally found in 4DSP's fmc110_ads5400_ctrl.vhd +entity bug5 is +port ( + clk : in std_logic; + trig : in std_logic; + data_o : out std_logic +); +end bug5; + +architecture bug5_syn of bug5 is +begin + +dummy:process(clk) +begin + if (trig = '1') then + --data_o <= '1'; -- uncomment this and everythings's OK + end if; +end process dummy; + +end bug5_syn; diff --git a/ivtest/ivltests/br988.v b/ivtest/ivltests/br988.v new file mode 100644 index 000000000..287a2f9da --- /dev/null +++ b/ivtest/ivltests/br988.v @@ -0,0 +1,20 @@ +module test(); + +parameter P = 1'b1; + +generate + if (P) begin : outer + begin : inner + reg [1:0] a = 2; + end + end +endgenerate + +initial begin + if (outer.inner.a == 2) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br990.v b/ivtest/ivltests/br990.v new file mode 100644 index 000000000..8dfbcb1f8 --- /dev/null +++ b/ivtest/ivltests/br990.v @@ -0,0 +1,17 @@ +module dut #(parameter a = 1, b = 2, c = 3) (); + +initial begin + $display("%0d %0d %0d", a, b, c); + if (b === 2) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule + +module top(); + +dut #(.a(4), .b(), .c(5)) dut(); + +endmodule diff --git a/ivtest/ivltests/br991a.v b/ivtest/ivltests/br991a.v new file mode 100644 index 000000000..16ab01d96 --- /dev/null +++ b/ivtest/ivltests/br991a.v @@ -0,0 +1,36 @@ +module test(); + +reg clk; +reg [1:0] state; + +always begin + case (state) + 0 : state = 1; + 1 : state = 2; + default : /* do nothing */ ; + endcase + @(posedge clk); +end + +reg failed = 0; + +initial begin + clk = 0; + state = 0; + #1 clk = 1; + #1 clk = 0; + if (state !== 1) failed = 1; + #1 clk = 1; + #1 clk = 0; + if (state !== 2) failed = 1; + #1 clk = 1; + #1 clk = 0; + if (state !== 2) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br991b.v b/ivtest/ivltests/br991b.v new file mode 100644 index 000000000..3ae5d5bb4 --- /dev/null +++ b/ivtest/ivltests/br991b.v @@ -0,0 +1,27 @@ +// These don't do anything useful, but check for compiler errors. + +module test(); + +integer i; + +always begin + for (i = 0; i < 10; i = i + 1) ; +end + +always begin + repeat (1) ; +end + +always begin + while (1) ; +end + +always begin + do ; while (1); +end + +always begin + forever ; +end + +endmodule diff --git a/ivtest/ivltests/br993a.v b/ivtest/ivltests/br993a.v new file mode 100644 index 000000000..9478b750e --- /dev/null +++ b/ivtest/ivltests/br993a.v @@ -0,0 +1,54 @@ +module br993a(); + +reg clk; +reg a; +reg b; +reg [1:0] q; + +(* ivl_synthesis_on *) +always @(posedge clk) begin + q <= 0; + if (a) q <= 1; + if (b) q <= 2; +end +(* ivl_synthesis_off *) + +reg failed; +initial begin + clk = 0; + + a = 0; + b = 0; + #1 clk = 1; + #1 clk = 0; + $display("%d", q); + if (q !== 2'd0) failed = 1; + + a = 1; + b = 0; + #1 clk = 1; + #1 clk = 0; + $display("%d", q); + if (q !== 2'd1) failed = 1; + + a = 1; + b = 1; + #1 clk = 1; + #1 clk = 0; + $display("%d", q); + if (q !== 2'd2) failed = 1; + + a = 0; + b = 1; + #1 clk = 1; + #1 clk = 0; + $display("%d", q); + if (q !== 2'd2) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br993b.v b/ivtest/ivltests/br993b.v new file mode 100644 index 000000000..70e03bf90 --- /dev/null +++ b/ivtest/ivltests/br993b.v @@ -0,0 +1,60 @@ +module br993a(); + +reg clk; +reg a; +reg b; +reg [1:0] q; + +(* ivl_synthesis_on *) +always @(posedge clk) begin + if (a) q <= 1; + if (b) q <= 2; +end +(* ivl_synthesis_off *) + +reg failed; +initial begin + clk = 0; + + a = 1; + b = 1; + #1 clk = 1; + #1 clk = 0; + $display("%d", q); + if (q !== 2'd2) failed = 1; + + a = 0; + b = 0; + #1 clk = 1; + #1 clk = 0; + $display("%d", q); + if (q !== 2'd2) failed = 1; + + a = 1; + b = 0; + #1 clk = 1; + #1 clk = 0; + $display("%d", q); + if (q !== 2'd1) failed = 1; + + a = 0; + b = 0; + #1 clk = 1; + #1 clk = 0; + $display("%d", q); + if (q !== 2'd1) failed = 1; + + a = 0; + b = 1; + #1 clk = 1; + #1 clk = 0; + $display("%d", q); + if (q !== 2'd2) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br994.v b/ivtest/ivltests/br994.v new file mode 100644 index 000000000..395244ba6 --- /dev/null +++ b/ivtest/ivltests/br994.v @@ -0,0 +1,41 @@ +module test(); + +reg clk; +reg sel; +reg [7:0] a; +reg [6:0] b; +reg [5:0] q; + +(* ivl_synthesis_on *) +always @(posedge clk) begin + if (sel) + q <= b; + else + q <= a; +end +(* ivl_synthesis_off *) + +reg failed; + +initial begin + a = 'haa; + b = 'hbb; + clk = 0; + sel = 0; + #1 clk = 1; + #1 clk = 0; + $display("%h", q); + if (q !== 6'h2a) failed = 1; + sel = 1; + #1 clk = 1; + #1 clk = 0; + $display("%h", q); + if (q !== 6'h3b) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br995.v b/ivtest/ivltests/br995.v new file mode 100644 index 000000000..aad1de3e9 --- /dev/null +++ b/ivtest/ivltests/br995.v @@ -0,0 +1,19 @@ +module dpram #( + parameter aw=8, + parameter dw=8 +) (input clka, clkb, wena, + input [aw-1:0] addra, addrb, + input [dw-1:0] dina, + output [dw-1:0] doutb +); +// minimalist dual-port RAM model, hope most tools can synthesize it +localparam sz=(32'b1<= |1'bx. + +module bug(); + +wire y = 1'b1 >= 1'bx; + +initial begin + #0 $display("%b", y); + if (y !== 1'bx) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh142.v b/ivtest/ivltests/br_gh142.v new file mode 100644 index 000000000..438d88668 --- /dev/null +++ b/ivtest/ivltests/br_gh142.v @@ -0,0 +1,8 @@ +module test(); + +parameter y = 1; +parameter a = 0; + +parameter x = y ? a : b; + +endmodule diff --git a/ivtest/ivltests/br_gh15.v b/ivtest/ivltests/br_gh15.v new file mode 100644 index 000000000..81717a219 --- /dev/null +++ b/ivtest/ivltests/br_gh15.v @@ -0,0 +1,18 @@ +// Regression test for GitHub issue 15 : Icarus does undef propagation of +// const adds incorrectly + +module bug(); + +wire [3:0] y; + +assign y = 4'bxx00 + 2'b00; + +initial begin + #0 $display("%b", y); + if (y === 4'bxxxx) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh152.v b/ivtest/ivltests/br_gh152.v new file mode 100644 index 000000000..97856880e --- /dev/null +++ b/ivtest/ivltests/br_gh152.v @@ -0,0 +1,5 @@ +module d(); + nand n2(w1, + + nand n1(w2); +endmodule diff --git a/ivtest/ivltests/br_gh157.v b/ivtest/ivltests/br_gh157.v new file mode 100644 index 000000000..1b05f1886 --- /dev/null +++ b/ivtest/ivltests/br_gh157.v @@ -0,0 +1,15 @@ +module dut(); + +localparam x = 2; + +initial $display("%0d", x); + +endmodule + +module test(); + +dut dut(); + +defparam dut.x = 1; + +endmodule diff --git a/ivtest/ivltests/br_gh162.v b/ivtest/ivltests/br_gh162.v new file mode 100644 index 000000000..6410fa4d9 --- /dev/null +++ b/ivtest/ivltests/br_gh162.v @@ -0,0 +1,14 @@ +module test(); + +localparam value = {16384{4'b1001}}; + +wire [65535:0] q = value; + +initial begin + if (q === value) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh163.v b/ivtest/ivltests/br_gh163.v new file mode 100644 index 000000000..a89476586 --- /dev/null +++ b/ivtest/ivltests/br_gh163.v @@ -0,0 +1,12 @@ +module m; + task t1; + input make_me_crash i; + begin + end + endtask + task t2; + input integer i; + begin + end + endtask +endmodule diff --git a/ivtest/ivltests/br_gh164a.v b/ivtest/ivltests/br_gh164a.v new file mode 100644 index 000000000..7ccd4a909 --- /dev/null +++ b/ivtest/ivltests/br_gh164a.v @@ -0,0 +1,27 @@ +module test; + +bit [7:0] mema[]; +bit [7:0] memb[]; + +reg failed = 0; + +initial begin + mema = new[4] ('{8'd1,8'd2,8'd3,8'd4}); + $display("%x %x %x %x", mema[0], mema[1], mema[2], mema[3]); + memb = new[4] (mema); + $display("%x %x %x %x", memb[0], memb[1], memb[2], memb[3]); + if (memb[0] !== 8'd1 || memb[1] !== 8'd2 || memb[2] !== 8'd3 || memb[3] !== 8'd4) failed = 1; + memb = new[5] (memb); + $display("%x %x %x %x %x", memb[0], memb[1], memb[2], memb[3], memb[4]); + if (memb[0] !== 8'd1 || memb[1] !== 8'd2 || memb[2] !== 8'd3 || memb[3] !== 8'd4 || memb[4] !== 8'b0) failed = 1; + memb = new[3] (memb); + $display("%x %x %x", memb[0], memb[1], memb[2]); + if (memb[0] !== 8'd1 || memb[1] !== 8'd2 || memb[2] !== 8'd3) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh164b.v b/ivtest/ivltests/br_gh164b.v new file mode 100644 index 000000000..392f07325 --- /dev/null +++ b/ivtest/ivltests/br_gh164b.v @@ -0,0 +1,27 @@ +module test; + +reg [7:0] mema[]; +reg [7:0] memb[]; + +reg failed = 0; + +initial begin + mema = new[4] ('{8'd1,8'd2,8'd3,8'd4}); + $display("%x %x %x %x", mema[0], mema[1], mema[2], mema[3]); + memb = new[4] (mema); + $display("%x %x %x %x", memb[0], memb[1], memb[2], memb[3]); + if (memb[0] !== 8'd1 || memb[1] !== 8'd2 || memb[2] !== 8'd3 || memb[3] !== 8'd4) failed = 1; + memb = new[5] (memb); + $display("%x %x %x %x %x", memb[0], memb[1], memb[2], memb[3], memb[4]); + if (memb[0] !== 8'd1 || memb[1] !== 8'd2 || memb[2] !== 8'd3 || memb[3] !== 8'd4 || memb[4] !== 8'bx) failed = 1; + memb = new[3] (memb); + $display("%x %x %x", memb[0], memb[1], memb[2]); + if (memb[0] !== 8'd1 || memb[1] !== 8'd2 || memb[2] !== 8'd3) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh164c.v b/ivtest/ivltests/br_gh164c.v new file mode 100644 index 000000000..d0b299818 --- /dev/null +++ b/ivtest/ivltests/br_gh164c.v @@ -0,0 +1,27 @@ +module test; + +int mema[]; +int memb[]; + +reg failed = 0; + +initial begin + mema = new[4] ('{8'd1,8'd2,8'd3,8'd4}); + $display("%x %x %x %x", mema[0], mema[1], mema[2], mema[3]); + memb = new[4] (mema); + $display("%x %x %x %x", memb[0], memb[1], memb[2], memb[3]); + if (memb[0] !== 8'd1 || memb[1] !== 8'd2 || memb[2] !== 8'd3 || memb[3] !== 8'd4) failed = 1; + memb = new[5] (memb); + $display("%x %x %x %x %x", memb[0], memb[1], memb[2], memb[3], memb[4]); + if (memb[0] !== 8'd1 || memb[1] !== 8'd2 || memb[2] !== 8'd3 || memb[3] !== 8'd4 || memb[4] !== 8'b0) failed = 1; + memb = new[3] (memb); + $display("%x %x %x", memb[0], memb[1], memb[2]); + if (memb[0] !== 8'd1 || memb[1] !== 8'd2 || memb[2] !== 8'd3) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh164d.v b/ivtest/ivltests/br_gh164d.v new file mode 100644 index 000000000..cbdbbda92 --- /dev/null +++ b/ivtest/ivltests/br_gh164d.v @@ -0,0 +1,27 @@ +module test; + +real mema[]; +real memb[]; + +reg failed = 0; + +initial begin + mema = new[4] ('{1.5,2.5,3.5,4.5}); + $display("%f %f %f %f", mema[0], mema[1], mema[2], mema[3]); + memb = new[4] (mema); + $display("%f %f %f %f", memb[0], memb[1], memb[2], memb[3]); + if (memb[0] != 1.5 || memb[1] != 2.5 || memb[2] != 3.5 || memb[3] != 4.5) failed = 1; + memb = new[5] (memb); + $display("%f %f %f %f %f", memb[0], memb[1], memb[2], memb[3], memb[4]); + if (memb[0] != 1.5 || memb[1] != 2.5 || memb[2] != 3.5 || memb[3] != 4.5 || memb[4] != 0.0) failed = 1; + memb = new[3] (memb); + $display("%f %f %f", memb[0], memb[1], memb[2]); + if (memb[0] != 1.5 || memb[1] != 2.5 || memb[2] != 3.5) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh164e.v b/ivtest/ivltests/br_gh164e.v new file mode 100644 index 000000000..93bfac076 --- /dev/null +++ b/ivtest/ivltests/br_gh164e.v @@ -0,0 +1,27 @@ +module test; + +string mema[]; +string memb[]; + +reg failed = 0; + +initial begin + mema = new[4] ('{"A","B","C","D"}); + $display("%s %s %s %s", mema[0], mema[1], mema[2], mema[3]); + memb = new[4] (mema); + $display("%s %s %s %s", memb[0], memb[1], memb[2], memb[3]); + if (memb[0] != "A" || memb[1] != "B" || memb[2] != "C" || memb[3] != "D") failed = 1; + memb = new[5] (memb); + $display("%s %s %s %s %s", memb[0], memb[1], memb[2], memb[3], memb[4]); + if (memb[0] != "A" || memb[1] != "B" || memb[2] != "C" || memb[3] != "D" || memb[4] != "") failed = 1; + memb = new[3] (memb); + $display("%s %s %s", memb[0], memb[1], memb[2]); + if (memb[0] != "A" || memb[1] != "B" || memb[2] != "C") failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh165.v b/ivtest/ivltests/br_gh165.v new file mode 100644 index 000000000..e7a4966ce --- /dev/null +++ b/ivtest/ivltests/br_gh165.v @@ -0,0 +1,22 @@ +module test; + +task automatic foo(input int id); + #1000 $display("task %0d finished at time %0t", id, $time); +endtask + +initial begin + $display("main thread started at time %0t", $time); + fork + #1 foo(1); + #2 foo(2); + join_none + #5; + $display("main thread continued at time %0t", $time); + fork + #1 foo(3); + #2 foo(4); + join_any + $display("main thread finished at time %0t", $time); +end + +endmodule diff --git a/ivtest/ivltests/br_gh167a.v b/ivtest/ivltests/br_gh167a.v new file mode 100644 index 000000000..20b6388fe --- /dev/null +++ b/ivtest/ivltests/br_gh167a.v @@ -0,0 +1,19 @@ +class my_class; + task run_test(); + $display("PASSED"); + endtask +endclass + +class extended_class extends my_class; +endclass + +module test(); + +extended_class obj; + +initial begin + obj = new(); + obj.run_test(); +end + +endmodule diff --git a/ivtest/ivltests/br_gh167b.v b/ivtest/ivltests/br_gh167b.v new file mode 100644 index 000000000..994294502 --- /dev/null +++ b/ivtest/ivltests/br_gh167b.v @@ -0,0 +1,19 @@ +class my_class; + task run_test(); + $display("PASSED"); + endtask +endclass + +module test(); + +class extended_class extends my_class; +endclass + +extended_class obj; + +initial begin + obj = new(); + obj.run_test(); +end + +endmodule diff --git a/ivtest/ivltests/br_gh175.v b/ivtest/ivltests/br_gh175.v new file mode 100644 index 000000000..0c3392442 --- /dev/null +++ b/ivtest/ivltests/br_gh175.v @@ -0,0 +1,96 @@ + +module dut (output reg[31:0] size, + output reg signed [31:0] ival, + output reg [31:0] hval); + parameter string foo = "1234"; + string tmp; + real rval; + + initial begin + size = foo.len(); + ival = foo.atoi(); + hval = foo.atohex(); + rval = foo.atoreal(); + + tmp = foo; + $display("foo=%0s, tmp=%0s", foo, tmp); + if (tmp != foo) begin + $display("FAILED"); + $finish; + end + $display("rval=%f", rval); + if (rval != ival) begin + $display("FAILED -- rval=%f, ival=%0d", rval, ival); + $finish; + end + end +endmodule // dut + +module main; + + wire [31:0] dut0_size, dut1_size, dut2_size; + wire signed [31:0] dut0_ival, dut1_ival, dut2_ival; + wire unsigned [31:0] dut0_hval, dut1_hval, dut2_hval; + + + // Instantate module with string parameter, use default value. + dut dut0 (dut0_size, dut0_ival, dut0_hval); + + // Instantate module with string parameter, use override value. + dut #(.foo("12345")) dut1 (dut1_size, dut1_ival, dut1_hval); + + // Instantate module with string parameter, use defparam value. + defparam dut2.foo = "123456"; + dut dut2 (dut2_size, dut2_ival, dut2_hval); + + initial begin + #100 ; + $display("dut0_size=%0d", dut0_size); + if (dut0_size !== 4) begin + $display("FAILED"); + $finish; + end + $display("dut1_size=%0d", dut1_size); + if (dut1_size !== 5) begin + $display("FAILED"); + $finish; + end + $display("dut2_size=%0d", dut2_size); + if (dut2_size !== 6) begin + $display("FAILED"); + $finish; + end + $display("dut0_ival=%0d", dut0_ival); + if (dut0_ival !== 1234) begin + $display("FAILED"); + $finish; + end + $display("dut1_ival=%0d", dut1_ival); + if (dut1_ival !== 12345) begin + $display("FAILED"); + $finish; + end + $display("dut2_ival=%0d", dut2_ival); + if (dut2_ival !== 123456) begin + $display("FAILED"); + $finish; + end + $display("dut0_hval=%0h", dut0_hval); + if (dut0_hval !== 32'h1234) begin + $display("FAILED"); + $finish; + end + $display("dut1_hval=%0h", dut1_hval); + if (dut1_hval !== 32'h12345) begin + $display("FAILED"); + $finish; + end + $display("dut2_hval=%0h", dut2_hval); + if (dut2_hval !== 32'h123456) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + $finish; + end +endmodule // main diff --git a/ivtest/ivltests/br_gh177a.v b/ivtest/ivltests/br_gh177a.v new file mode 100644 index 000000000..3104def33 --- /dev/null +++ b/ivtest/ivltests/br_gh177a.v @@ -0,0 +1,51 @@ + +class test_t; + enum bit [1:0] { X, Y } foo; + + task go; + foo = X; + $display("test_t.foo=%b (X==0)", foo); + if (foo !== X) begin + $display("FAILED"); + $finish; + end + foo = Y; + $display("test_t.foo=%b (Y==1)", foo); + if (foo !== Y) begin + $display("FAILED"); + $finish; + end + endtask +endclass // test_t + +module main; + typedef enum bit [1:0] { X, Y } xy_t; + xy_t foo; + + initial begin + foo = Y; + $display("foo=%b (Y==1)", foo); + if (foo !== Y) begin + $display("FAILED"); + $finish; + end + foo = X; + $display("foo=%b (X==0)", foo); + if (foo !== X) begin + $display("FAILED"); + $finish; + end + end + + test_t bar; + initial begin + bar = new; + bar.go(); + end + + initial begin + #1 $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/br_gh177b.v b/ivtest/ivltests/br_gh177b.v new file mode 100644 index 000000000..03ed6555e --- /dev/null +++ b/ivtest/ivltests/br_gh177b.v @@ -0,0 +1,52 @@ + +class test_t; + typedef enum bit [1:0] { U, V } uv_t; + uv_t foo; + + task go; + foo = U; + $display("test_t.foo=%b (U==0)", foo); + if (foo !== U) begin + $display("FAILED"); + $finish; + end + foo = V; + $display("test_t.foo=%b (V==1)", foo); + if (foo !== V) begin + $display("FAILED"); + $finish; + end + endtask +endclass // test_t + +module main; + typedef enum bit [1:0] { X, Y } xy_t; + xy_t foo; + + initial begin + foo = Y; + $display("foo=%b (Y==1)", foo); + if (foo !== Y) begin + $display("FAILED"); + $finish; + end + foo = X; + $display("foo=%b (X==0)", foo); + if (foo !== X) begin + $display("FAILED"); + $finish; + end + end + + test_t bar; + initial begin + bar = new; + bar.go(); + end + + initial begin + #1 $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/br_gh18.v b/ivtest/ivltests/br_gh18.v new file mode 100644 index 000000000..36d0463d4 --- /dev/null +++ b/ivtest/ivltests/br_gh18.v @@ -0,0 +1,16 @@ +// Regression test for GitHub issue 18 : Icarus does undef propagation of +// const multiplies incorrectly. + +module bug(); + +wire [3:0] y = 4'b0 * 4'bx; + +initial begin + #0 $display("%b", y); + if (y === 4'bxxxx) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh19.v b/ivtest/ivltests/br_gh19.v new file mode 100644 index 000000000..cb04839c5 --- /dev/null +++ b/ivtest/ivltests/br_gh19.v @@ -0,0 +1,16 @@ +// Regression test for GitHub issue 19 : Icarus only using the lowest 32 +// bits of right shift operand. + +module bug(); + +wire [3:0] y = 4'b1 << 33'h100000000; + +initial begin + #0 $display("%b", y); + if (y === 4'b0000) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh194.v b/ivtest/ivltests/br_gh194.v new file mode 100644 index 000000000..355a860f8 --- /dev/null +++ b/ivtest/ivltests/br_gh194.v @@ -0,0 +1,26 @@ + +module string_example; + + function int example( string my_string ); + if( my_string[1] != 8'h65 ) begin + return 1; + end else begin + return 0; + end + endfunction // example + + string test_string; + initial begin + test_string = "Hello, World"; + if (test_string[0] !== 8'h48) begin + $display("FAILED -- test+string[0] = %h", test_string[0]); + $finish; + end + if (example(test_string) === 1) begin + $display("FAILED -- example(test_string) returned error."); + $finish; + end + $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/br_gh198.v b/ivtest/ivltests/br_gh198.v new file mode 100644 index 000000000..b24c6014b --- /dev/null +++ b/ivtest/ivltests/br_gh198.v @@ -0,0 +1,46 @@ +module octal(); + +reg [5:0] var1; +reg [4:0] var2; + +initial begin + var1 = 6'o00; $displayo($signed(var1)); + var1 = 6'o01; $displayo($signed(var1)); + var1 = 6'o02; $displayo($signed(var1)); + var1 = 6'o03; $displayo($signed(var1)); + var1 = 6'o04; $displayo($signed(var1)); + var1 = 6'o05; $displayo($signed(var1)); + var1 = 6'o06; $displayo($signed(var1)); + var1 = 6'o07; $displayo($signed(var1)); + var1 = 6'o10; $displayo($signed(var1)); + var1 = 6'o20; $displayo($signed(var1)); + var1 = 6'o30; $displayo($signed(var1)); + var1 = 6'o40; $displayo($signed(var1)); + var1 = 6'o50; $displayo($signed(var1)); + var1 = 6'o60; $displayo($signed(var1)); + var1 = 6'o70; $displayo($signed(var1)); + var1 = 6'o17; $displayo($signed(var1)); + var1 = 6'o26; $displayo($signed(var1)); + var1 = 6'o35; $displayo($signed(var1)); + var1 = 6'o44; $displayo($signed(var1)); + var1 = 6'o53; $displayo($signed(var1)); + var1 = 6'o62; $displayo($signed(var1)); + var1 = 6'o71; $displayo($signed(var1)); + $display(""); + var2 = 6'o00; $displayo($signed(var2)); + var2 = 6'o01; $displayo($signed(var2)); + var2 = 6'o02; $displayo($signed(var2)); + var2 = 6'o03; $displayo($signed(var2)); + var2 = 6'o04; $displayo($signed(var2)); + var2 = 6'o05; $displayo($signed(var2)); + var2 = 6'o06; $displayo($signed(var2)); + var2 = 6'o07; $displayo($signed(var2)); + var2 = 6'o10; $displayo($signed(var2)); + var2 = 6'o20; $displayo($signed(var2)); + var2 = 6'o30; $displayo($signed(var2)); + var2 = 6'o17; $displayo($signed(var2)); + var2 = 6'o26; $displayo($signed(var2)); + var2 = 6'o35; $displayo($signed(var2)); +end + +endmodule diff --git a/ivtest/ivltests/br_gh199a.v b/ivtest/ivltests/br_gh199a.v new file mode 100644 index 000000000..0637deeca --- /dev/null +++ b/ivtest/ivltests/br_gh199a.v @@ -0,0 +1,24 @@ +module bug(); + reg [31:0] n1, d1, q1, m1; + reg [63:0] n2, d2, q2, m2; + + initial begin + n1 = 32'h8000_0000; + d1 = 32'hFFFF_FFFF; + q1 = $signed(n1) / $signed(d1); + $display("32 bit quotient = 0x%08h;", q1); + m1 = $signed(n1) % $signed(d1); + $display("32 bit modulus = 0x%08h;", m1); + n2 = 64'h8000_0000_0000_0000; + d2 = 64'hFFFF_FFFF_FFFF_FFFF; + q2 = $signed(n2) / $signed(d2); + $display("64 bit quotient = 0x%016h;", q2); + m2 = $signed(n2) % $signed(d2); + $display("64 bit modulus = 0x%016h;", m2); + if ((q1 === 32'h8000_0000) && (q2 === 64'h8000_0000_0000_0000) + && (m1 === 32'h0000_0000) && (m2 === 64'h0000_0000_0000_0000)) + $display("PASSED"); + else + $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/br_gh199b.v b/ivtest/ivltests/br_gh199b.v new file mode 100644 index 000000000..761ca0f6c --- /dev/null +++ b/ivtest/ivltests/br_gh199b.v @@ -0,0 +1,23 @@ +module bug(); + localparam signed [31:0] n1 = 32'h8000_0000; + localparam signed [31:0] d1 = 32'hFFFF_FFFF; + localparam signed [31:0] q1 = n1 / d1; + localparam signed [31:0] m1 = n1 % d1; + + localparam signed [63:0] n2 = 64'h8000_0000_0000_0000; + localparam signed [63:0] d2 = 64'hFFFF_FFFF_FFFF_FFFF; + localparam signed [63:0] q2 = n2 / d2; + localparam signed [63:0] m2 = n2 % d2; + + initial begin + $display("32 bit quotient = 0x%08h;", q1); + $display("32 bit modulus = 0x%08h;", m1); + $display("64 bit quotient = 0x%016h;", q2); + $display("64 bit modulus = 0x%016h;", m2); + if ((q1 === 32'h8000_0000) && (q2 === 64'h8000_0000_0000_0000) + && (m1 === 32'h0000_0000) && (m2 === 64'h0000_0000_0000_0000)) + $display("PASSED"); + else + $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/br_gh19a.v b/ivtest/ivltests/br_gh19a.v new file mode 100644 index 000000000..6c9250773 --- /dev/null +++ b/ivtest/ivltests/br_gh19a.v @@ -0,0 +1,19 @@ +// Regression test for GitHub issue 19 : Icarus only using the lowest 32 +// bits of right shift operand (run-time test) + +module bug(); + +reg a; +reg y; + +initial begin + a = 1; + y = 1 >> {a, 64'b0}; + $display("%b", y); + if (y === 1'b0) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh19b.v b/ivtest/ivltests/br_gh19b.v new file mode 100644 index 000000000..a33d82192 --- /dev/null +++ b/ivtest/ivltests/br_gh19b.v @@ -0,0 +1,17 @@ +// Regression test for GitHub issue 19 : Icarus only using the lowest 32 +// bits of right shift operand (run-time test) + +module bug(); + +wire a = 1; +wire y = 1 >> {a, 64'b0}; + +initial begin + #0 $display("%b", y); + if (y === 1'b0) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh209.v b/ivtest/ivltests/br_gh209.v new file mode 100644 index 000000000..dd6385a20 --- /dev/null +++ b/ivtest/ivltests/br_gh209.v @@ -0,0 +1,10 @@ +module test(); + +integer f; + +initial begin + f = $fopen("work/br_gh209.dat"); + $fwrite(f, "%c%c%c%c", 8'h00, 8'h01, 8'h02, 8'h03); +end + +endmodule diff --git a/ivtest/ivltests/br_gh219.v b/ivtest/ivltests/br_gh219.v new file mode 100644 index 000000000..f4366dc39 --- /dev/null +++ b/ivtest/ivltests/br_gh219.v @@ -0,0 +1,24 @@ +module Main(); + + logic[2:0] a = 3'b111; + logic signed[2:0] a_signed = 3'b111; + + logic[2:0] b = 0; + + logic[3:0] c0; + logic[3:0] c1; + + initial begin + c0 = 4'($signed(a)) + b; + c1 = 4'(a_signed) + b; + + $display("c0: %b", c0); + $display("c1: %b", c1); + + if (c0 === 4'b1111 && c1 === 4'b1111) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/br_gh22.v b/ivtest/ivltests/br_gh22.v new file mode 100644 index 000000000..27c567567 --- /dev/null +++ b/ivtest/ivltests/br_gh22.v @@ -0,0 +1,21 @@ +// Regression test for GitHub issue 22 + +module bug(); + +reg [1:0] a; +reg [2:0] b; +wire [3:0] y; + +assign y = {a >> {22{b}}, a << (0 <<< b)}; + +initial begin + b = 7; + a = 3; + #1 $display("%b", y); + if (y === 4'b0011) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh220.v b/ivtest/ivltests/br_gh220.v new file mode 100644 index 000000000..c3033574d --- /dev/null +++ b/ivtest/ivltests/br_gh220.v @@ -0,0 +1,14 @@ +module Main(); + logic[4:0] r5; + + initial begin + r5 = 5'(3'd7 + 3'd6); + $display("r5 = %b, %d", r5, r5); + + if (r5 === 5'b01101) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/br_gh224.v b/ivtest/ivltests/br_gh224.v new file mode 100644 index 000000000..abebd4a4f --- /dev/null +++ b/ivtest/ivltests/br_gh224.v @@ -0,0 +1,28 @@ +package MyPackage; + +typedef enum logic [1:0] { + A = 2'b00, + B = 2'b01, + C = 2'b10 +} MyEnum; + +endpackage + +module test(); + +import MyPackage::*; + +localparam MyB = B; + +localparam C = 4; + +initial begin + $display("B = %0d", MyB); + $display("C = %0d", C); + if (MyB === 1 && C === 4) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh226.v b/ivtest/ivltests/br_gh226.v new file mode 100644 index 000000000..677fd3a2e --- /dev/null +++ b/ivtest/ivltests/br_gh226.v @@ -0,0 +1,17 @@ +module test(); + +struct packed { + logic [15:0] value; +} data; + +initial begin + data.value[7:0] = 8'h55; + data.value[15:8] = 8'haa; + if (data !== 16'haa55) begin + $display("FAILED -- data=%h", data); + $finish; + end + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh230.v b/ivtest/ivltests/br_gh230.v new file mode 100644 index 000000000..6b87691d1 --- /dev/null +++ b/ivtest/ivltests/br_gh230.v @@ -0,0 +1,9 @@ +module test(); + +reg [7:0] array[3:0][3:0]; + +initial begin + $dumpvars(0, array[0][0][0]); +end + +endmodule diff --git a/ivtest/ivltests/br_gh231.v b/ivtest/ivltests/br_gh231.v new file mode 100644 index 000000000..556c7d153 --- /dev/null +++ b/ivtest/ivltests/br_gh231.v @@ -0,0 +1,18 @@ +module bug; + +reg [4:0] a = 5'b01010; + +reg failed = 0; + +initial begin + foreach (a[i]) begin + $display("Value of a[%0d]=%0d", i, a[i]); + if (a[i] !== i[0]) failed = 1; + end + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh243.v b/ivtest/ivltests/br_gh243.v new file mode 100644 index 000000000..38d55819a --- /dev/null +++ b/ivtest/ivltests/br_gh243.v @@ -0,0 +1,23 @@ +module test(); + +bit [3:0] array[15:0]; + +reg failed = 0; + +integer i; + +initial begin + for (i = 0; i < 16; i++) begin + array[i] = i; + end + for (i = 0; i < 16; i++) begin + $display("%b", array[i]); + if (array[i] != i) failed = 1; + end + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh244a.v b/ivtest/ivltests/br_gh244a.v new file mode 100644 index 000000000..0eafc2b6a --- /dev/null +++ b/ivtest/ivltests/br_gh244a.v @@ -0,0 +1,24 @@ +module test; + + wire [63:0] out; + reg [5:0] in; + + integer i = 0; + assign out = 2 ** in; + + reg failed = 0; + + initial begin + for (i = 0; i < 64; i = i + 1) begin + in = i; + #10; + $display("%d: %b", i, out); + if (out !== 64'd1 << i) + failed = 1; + end + if (failed) + $display("FAILED"); + else + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/br_gh244b.v b/ivtest/ivltests/br_gh244b.v new file mode 100644 index 000000000..276fb11a5 --- /dev/null +++ b/ivtest/ivltests/br_gh244b.v @@ -0,0 +1,23 @@ +module test; + + reg [63:0] out; + reg [5:0] in; + + integer i = 0; + + reg failed = 0; + + initial begin + for (i = 0; i < 64; i = i + 1) begin + in = i; + out = 2 ** in; + $display("%d: %b", i, out); + if (out !== 64'd1 << i) + failed = 1; + end + if (failed) + $display("FAILED"); + else + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/br_gh25a.v b/ivtest/ivltests/br_gh25a.v new file mode 100644 index 000000000..a3b3d84b2 --- /dev/null +++ b/ivtest/ivltests/br_gh25a.v @@ -0,0 +1,22 @@ +// Regression test for GitHub issue 25 +// This should result in a compile-time error when the language generation +// is 1364-2005 or earlier. + +function test(input i); + +begin + test = i; +end + +endfunction + +module tb; + +initial begin + if (test(1)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh25b.v b/ivtest/ivltests/br_gh25b.v new file mode 100644 index 000000000..e168e0419 --- /dev/null +++ b/ivtest/ivltests/br_gh25b.v @@ -0,0 +1,25 @@ +// Regression test for GitHub issue 25 +// This should result in a compile-time error when the language generation +// is 1364-2005 or earlier. + +task test(input i, output o); + +begin + o = i; +end + +endtask + +module tb; + +reg passed = 0; + +initial begin + test(1, passed); + if (passed) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh26.v b/ivtest/ivltests/br_gh26.v new file mode 100644 index 000000000..f465a163b --- /dev/null +++ b/ivtest/ivltests/br_gh26.v @@ -0,0 +1,19 @@ +// Regression test for GitHub issue 26 +// This is invalid code and should result in a compile-time error + +module tb; + +wire [3:0] a, y; + +test uut (.a(a), .y(y)); + +endmodule + +module test(a, b, y); + +input [3:0] a; +output [3:0] y; + +assign y = a; + +endmodule diff --git a/ivtest/ivltests/br_gh265.v b/ivtest/ivltests/br_gh265.v new file mode 100644 index 000000000..9f04dba6f --- /dev/null +++ b/ivtest/ivltests/br_gh265.v @@ -0,0 +1,11 @@ +module test(); + +typedef bit [3:0] array_t[]; + +array_t array; + +initial begin + array = 8'd1 << 4; +end + +endmodule diff --git a/ivtest/ivltests/br_gh277a.v b/ivtest/ivltests/br_gh277a.v new file mode 100644 index 000000000..0828a1736 --- /dev/null +++ b/ivtest/ivltests/br_gh277a.v @@ -0,0 +1,31 @@ +module dut; + +function y(input x); + y = x; +endfunction + +reg a, b; +reg c, d; + +always @* begin + c = y(a); + d = y(b); +end + +endmodule + +module tb; + +dut dut(); + +initial begin + #1 dut.a = 0; + #1 dut.b = 1; + #1 $display(dut.a,,dut.b,,dut.c,,dut.d); + if (dut.c === 0 && dut.d === 1) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh277b.v b/ivtest/ivltests/br_gh277b.v new file mode 100644 index 000000000..82380a996 --- /dev/null +++ b/ivtest/ivltests/br_gh277b.v @@ -0,0 +1,35 @@ +module dut; + +reg a, b, c; +reg d; + +function z(input x, input y); + z = x + y; +endfunction + +function y(input x); + y = z(x, b) + z(x, c); +endfunction + +always_comb begin + d = y(a); +end + +endmodule + +module tb; + +dut dut(); + +initial begin + #1 dut.a = 0; + #1 dut.b = 0; + #1 dut.c = 1; + #1 $display(dut.a,,dut.b,,dut.c,,dut.d); + if (dut.d === 1) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh28.v b/ivtest/ivltests/br_gh28.v new file mode 100644 index 000000000..89484ace9 --- /dev/null +++ b/ivtest/ivltests/br_gh28.v @@ -0,0 +1,24 @@ +// Regression test for GitHub issue #28 : Insufficient string escaping +// when writing vvp script. + +module tb; + +wire [63:0] y; + +\test_str="hello" uut (y); + +initial begin + #1 $display("%s", y); + if (y === "hello") + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule + +module \test_str="hello" (output [63:0] \port="y" ); + +assign \port="y" = "hello"; + +endmodule diff --git a/ivtest/ivltests/br_gh280.v b/ivtest/ivltests/br_gh280.v new file mode 100644 index 000000000..553f1e83e --- /dev/null +++ b/ivtest/ivltests/br_gh280.v @@ -0,0 +1,27 @@ +module enumtestcase(); + +typedef enum logic { STATE_A, STATE_B } t_STATE; + +t_STATE state; + +bit select; + +reg failed = 0; + +initial begin + select = 0; + state = select ? STATE_B : STATE_A; + $display(state); + if (state != STATE_A) failed = 1; + select = 1; + state = select ? STATE_B : STATE_A; + $display(state); + if (state != STATE_B) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh281.v b/ivtest/ivltests/br_gh281.v new file mode 100644 index 000000000..e184d57b7 --- /dev/null +++ b/ivtest/ivltests/br_gh281.v @@ -0,0 +1,23 @@ + +module main; + + int variable = 0; + + // A void function returns no value, so can be called + // like a task, but without a warning about unused + // results. + function void test_incr(input int arg); + variable = variable + arg; + endfunction // test_incr + + initial begin + variable = 0; + test_incr(5); + if (variable !== 5) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/br_gh281b.v b/ivtest/ivltests/br_gh281b.v new file mode 100644 index 000000000..00c3cca67 --- /dev/null +++ b/ivtest/ivltests/br_gh281b.v @@ -0,0 +1,23 @@ + +module main; + + int variable = 0; + + // A void function returns no value, so can be called + // like a task, but without a warning about unused + // results. It does not have to take any arguments. + function void test_incr(); + variable = variable + 1; + endfunction // test_incr + + initial begin + variable = 0; + test_incr(); + if (variable !== 1) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/br_gh283a.v b/ivtest/ivltests/br_gh283a.v new file mode 100644 index 000000000..ad30cf838 --- /dev/null +++ b/ivtest/ivltests/br_gh283a.v @@ -0,0 +1,22 @@ +module bug(); + +reg [31:0] d; +reg [31:0] x; +reg [31:0] y; +reg [31:0] z; + +initial begin + d = 32'hffff0000; + x = 32'hffffffff << d; + y = 32'hffffffff >> d; + z = 32'hffffffff >>> d; + $display("%h", x); + $display("%h", y); + $display("%h", z); + if (x === 32'd0 && y === 32'd0 && z === 32'd0) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh283b.v b/ivtest/ivltests/br_gh283b.v new file mode 100644 index 000000000..e7195c92c --- /dev/null +++ b/ivtest/ivltests/br_gh283b.v @@ -0,0 +1,22 @@ +module bug(); + +reg [64:0] d; +reg [31:0] x; +reg [31:0] y; +reg [31:0] z; + +initial begin + d = 65'h1_0000_0000_0000_0000; + x = 32'hffffffff << d; + y = 32'hffffffff >> d; + z = 32'hffffffff >>> d; + $display("%h", x); + $display("%h", y); + $display("%h", z); + if (x === 32'd0 && y === 32'd0 && z === 32'd0) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh283c.v b/ivtest/ivltests/br_gh283c.v new file mode 100644 index 000000000..d730d0c82 --- /dev/null +++ b/ivtest/ivltests/br_gh283c.v @@ -0,0 +1,22 @@ +module bug(); + +reg d; +reg [31:0] x; +reg [31:0] y; +reg [31:0] z; + +initial begin + d = 1; + x = 32'hffffffff << {d, 64'd0}; + y = 32'hffffffff >> {d, 64'd0}; + z = 32'hffffffff >>> {d, 64'd0}; + $display("%h", x); + $display("%h", y); + $display("%h", z); + if (x === 32'd0 && y === 32'd0 && z === 32'd0) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh289a.v b/ivtest/ivltests/br_gh289a.v new file mode 100644 index 000000000..b11c24d30 --- /dev/null +++ b/ivtest/ivltests/br_gh289a.v @@ -0,0 +1,36 @@ +package pkg; + +typedef enum logic [3:0] { + ABC = 4'h1 +} enum_t; + +typedef struct packed { + enum_t item; +} w_enum; + +typedef struct packed { + logic [3:0] item; +} w_logic; + +typedef union packed { + w_enum el1; + w_logic el2; +} foo_t; + +endpackage + +module main(); + +import pkg::*; + +foo_t val; + +initial begin + val.el1.item = ABC; + if (val.el2.item === 4'h1) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh289b.v b/ivtest/ivltests/br_gh289b.v new file mode 100644 index 000000000..d00d7877a --- /dev/null +++ b/ivtest/ivltests/br_gh289b.v @@ -0,0 +1,26 @@ +package p; + + localparam a = 1, b = 2; + + typedef enum { A = a, B = b } enum_t; + +endpackage + +module a(); + + localparam a = 3, b = 4; + + import p::*; + + enum_t e; + + initial begin + e = A; + $display(e); + if (e === 1) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/br_gh289c.v b/ivtest/ivltests/br_gh289c.v new file mode 100644 index 000000000..c2340fcbc --- /dev/null +++ b/ivtest/ivltests/br_gh289c.v @@ -0,0 +1,26 @@ +package p; + + localparam a = 1, b = 2; + + typedef logic [b:a] vector_t; + +endpackage + +module a(); + + localparam a = 1, b = 4; + + import p::*; + + vector_t v; + + initial begin:blk + v = ~0; + $display("%b", v); + if (v === 2'b11) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/br_gh289d.v b/ivtest/ivltests/br_gh289d.v new file mode 100644 index 000000000..4b773c974 --- /dev/null +++ b/ivtest/ivltests/br_gh289d.v @@ -0,0 +1,18 @@ +module p #(parameter a = 1, b = 2) (); + + typedef logic [b:a] vector_t; + + vector_t v; + + initial begin + v = ~0; + #b $display("%m %0d %0d %b", a, b, v); + end +endmodule + +module m; + +p #(1,2) p1(); +p #(1,4) p2(); + +endmodule diff --git a/ivtest/ivltests/br_gh30.v b/ivtest/ivltests/br_gh30.v new file mode 100644 index 000000000..b38005bbd --- /dev/null +++ b/ivtest/ivltests/br_gh30.v @@ -0,0 +1,15 @@ +// Regression test for GitHub issue #30 : failed assertion in eval_tree.cc +module bug(); + +wire [3:0] y; + +assign y = 1 * (1 ? (1.0 * 0) : 1); + +initial begin + if (y === 4'd0) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh306a.v b/ivtest/ivltests/br_gh306a.v new file mode 100644 index 000000000..8062a0097 --- /dev/null +++ b/ivtest/ivltests/br_gh306a.v @@ -0,0 +1,24 @@ +module counter(out, clk, reset); + + parameter WIDTH = 8; + + output [WIDTH-1 : 0] out; + input clk, reset; + + reg [WIDTH-1 : 0] out; + wire clk, reset; + +(* ivl_synthesis_on *) + always @(posedge clk) + out <= out + 1; + + always @(posedge reset) + assign out = 0; + + always @(negedge reset) + deassign out; +(* ivl_synthesis_off *) + +initial $display("PASSED"); + +endmodule // counter diff --git a/ivtest/ivltests/br_gh306b.v b/ivtest/ivltests/br_gh306b.v new file mode 100644 index 000000000..85ccd3625 --- /dev/null +++ b/ivtest/ivltests/br_gh306b.v @@ -0,0 +1,24 @@ +module counter(out, clk, reset); + + parameter WIDTH = 8; + + output [WIDTH-1 : 0] out; + input clk, reset; + + reg [WIDTH-1 : 0] out; + wire clk, reset; + +(* ivl_synthesis_on *) + always @(posedge clk) + out <= out + 1; + + always @(posedge reset) + force out = 0; + + always @(negedge reset) + release out; +(* ivl_synthesis_off *) + +initial $display("PASSED"); + +endmodule // counter diff --git a/ivtest/ivltests/br_gh307.v b/ivtest/ivltests/br_gh307.v new file mode 100644 index 000000000..65b7ab851 --- /dev/null +++ b/ivtest/ivltests/br_gh307.v @@ -0,0 +1,37 @@ + +typedef struct packed { + logic b; +} single_bit; + +typedef struct packed { + single_bit b1; + single_bit b2; +} two_bits; + +module simple(input two_bits b2in, + output two_bits b2out); + assign b2out.b1.b = b2in.b1.b; +endmodule // simple + +module main; + + two_bits src; + wire two_bits dst; + + simple copy(src, dst); + assign dst.b2.b = src.b2.b; + + initial begin + src.b1.b = 1'b1; + src.b2.b = 1'b0; + #1 ; // Let values settle. + $display("src=%b (s.b. 10), dst=%b (s.b. 10)", src, dst); + if (src !== 2'b10 || dst !== 2'b10) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/br_gh309.v b/ivtest/ivltests/br_gh309.v new file mode 100644 index 000000000..dbb061368 --- /dev/null +++ b/ivtest/ivltests/br_gh309.v @@ -0,0 +1,15 @@ +module test(); + +`define TEST_MACRO(arg) arg + +reg [3:0] value; + +initial begin + value = `TEST_MACRO({2'b01, 2'b10}); + if (value === 4'b0110) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh315.v b/ivtest/ivltests/br_gh315.v new file mode 100644 index 000000000..2442b2086 --- /dev/null +++ b/ivtest/ivltests/br_gh315.v @@ -0,0 +1,104 @@ +`timescale 1ns/1ns + +module hct74245( + input dir, + input nOE, + inout [7:0] A, + inout [7:0] B, + output [7:0] C // Added to demonstrate that a straight dependency timing works correctly +); + + // HCT typical @ 5v according to https://assets.nexperia.com/documents/data-sheet/74HC_HCT245.pdf + + specify + (A *> C) = 100; // This delay works OK + (A *> B) = 10; // The rest of these delays do not work + (B *> A) = 10; // not respected + (dir *> A) = 16;// not respected + (dir *> B) = 16;// not respected + (nOE *> A) = 16;// not respected + (nOE *> B) = 16;// not respected + endspecify + + assign A=nOE? 8'bzzzzzzzz : dir?8'bzzzzzzzz:B; + assign B=nOE? 8'bzzzzzzzz : dir?A:8'bzzzzzzzz; + assign C=A; // THIS IS DELAYED BY 100 + + // HAVE TO USE THIS APPROACH TO MAKE TIMINGS WORK AT ALL + // assign #16 A=nOE? 8'bzzzzzzzz :dir?8'bzzzzzzzz:B; + // assign #16 B=nOE? 8'bzzzzzzzz :dir?A: 8'bzzzzzzzz; + +endmodule + +module tb(); + + tri [7:0]A; + tri [7:0]B; + + tri [7:0]C; // 'C' IS NOT PART OF ORIGINAL DESIGN - HOWEVER THIS TIMING IS RESPECTED COS THERE ARE NO CONDITIONALS IN THE ASSIGNMENT + + reg [7:0] Vb=8'b00000000; + reg [7:0] Va=8'b11111111; + + reg dir; + reg nOE; + + assign B=Vb; + assign A=Va; + + hct74245 buf245(.A, .B, .dir, .nOE); + + integer timer; + + reg failed = 0; + + initial begin + $display("disable output , set dir a->b"); + dir <= 1; // A->B + nOE <= 1; + Va=8'b11111111; + Vb=8'bzzzzzzzz; + + #50 // time to settle + + // NOW throw outputs on and time how long it takes for expected output to appear. + + // It should take 16 to propagate from nOE -> B but the change is instantaneous + + $display("enable output - B will change immediately"); + + timer=$time; + nOE <= 0; + wait(B === 8'b11111111); + if ($time - timer < 16) begin + $display("%6d", $time, " ERROR TOO QUICK - EXPECTED nOE->B = 16ns - BUT TOOK %-d", ($time - timer)); + failed = 1; + end + else + $display("%6d", $time, " OK - TOOK %-d", ($time - timer)); + + + #50 // settle + + // Change data in - This should take 10 to propagate A->B but is instantaneous + $display("change A - B will change immediately (but C is delayed as expected by 100)"); + + Va=8'b00000000; + + timer=$time; + nOE <= 0; + wait(B === 8'b00000000); + if ($time - timer < 10) begin + $display("%6d", $time, " ERROR TOO QUICK - EXPECTED A->B = 10ns - BUT TOOK %-d", ($time - timer)); + failed = 1; + end + else + $display("%6d", $time, " OK - TOOK %-d", ($time - timer)); + + if (failed) + $display("FAILED"); + else + $display("PASSED"); + + end +endmodule diff --git a/ivtest/ivltests/br_gh316a.v b/ivtest/ivltests/br_gh316a.v new file mode 100644 index 000000000..7a48c4ad7 --- /dev/null +++ b/ivtest/ivltests/br_gh316a.v @@ -0,0 +1,42 @@ +module dut(input EN, input I, output O); + +assign O = EN ? I : 1'bz; + +specify + (I => O) = (2); + (EN *> O) = (4); +endspecify + +endmodule + +module test(); + +reg EN; +reg I; +tri O; + +pulldown(O); + +dut dut(EN, I, O); + +reg failed = 0; + +initial begin + $monitor($time,,EN,,I,,O); + EN = 0; + #4; + #0 if (O !== 0) failed = 1; + #1 I = 1; + #1 EN = 1; + #3; + #0 if (O !== 0) failed = 1; + #1; + #0 if (O !== 1) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh316b.v b/ivtest/ivltests/br_gh316b.v new file mode 100644 index 000000000..281085f81 --- /dev/null +++ b/ivtest/ivltests/br_gh316b.v @@ -0,0 +1,66 @@ +module dut(input EN1, input I1, output O1, + input EN2, input I2, output O2); + +assign O1 = EN1 ? I1 : 1'bz; +assign O2 = EN2 ? I2 : 1'bz; + +specify + (I1 => O1) = (2); + (EN1 *> O1) = (4); + (I2 => O2) = (3); + (EN2 *> O2) = (4); +endspecify + +endmodule + +module test(); + +reg EN1; +reg EN2; +reg I1; +reg I2; +tri O; + +pulldown(O); + +dut dut(EN1, I1, O, EN2, I2, O); + +reg failed = 0; + +initial begin + $monitor($time,,EN1,,I1,,EN2,,I2,,O); + EN1 = 0; + EN2 = 0; + #4; + #0 if (O !== 0) failed = 1; + I1 = 1; + I2 = 1; + #1; + EN1 = 1; + #3; + #0 if (O !== 0) failed = 1; + #1; + #0 if (O !== 1) failed = 1; + I1 = 0; + #1; + #0 if (O !== 1) failed = 1; + #1; + #0 if (O !== 0) failed = 1; + EN1 = 0; + EN2 = 1; + #3; + #0 if (O !== 0) failed = 1; + #1; + #0 if (O !== 1) failed = 1; + I2 = 0; + #2; + #0 if (O !== 1) failed = 1; + #1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh316c.v b/ivtest/ivltests/br_gh316c.v new file mode 100644 index 000000000..7d756c35b --- /dev/null +++ b/ivtest/ivltests/br_gh316c.v @@ -0,0 +1,66 @@ +module dut(input EN, input DIR, inout A, inout B); + +assign A = EN && DIR == 0 ? B : 1'bz; +assign B = EN && DIR == 1 ? A : 1'bz; + +specify + (A => B) = (2); + (B => A) = (3); + (EN => A) = (4); + (EN => B) = (4); +endspecify + +endmodule + +module test(); + +wire EN1; +wire EN2; +wire I1; +wire I2; +tri O; + +pulldown(O); + +dut dut1(EN1, 1'b1, I1, O); +dut dut2(EN2, 1'b0, O, I2); + +reg failed = 0; + +initial begin + $monitor($time,,EN1,,I1,,EN2,,I2,,O); + force EN1 = 0; + force EN2 = 0; + #4; + #0 if (O !== 0) failed = 1; + force I1 = 1; + force I2 = 1; + #1; + force EN1 = 1; + #3; + #0 if (O !== 0) failed = 1; + #1; + #0 if (O !== 1) failed = 1; + force I1 = 0; + #1; + #0 if (O !== 1) failed = 1; + #1; + #0 if (O !== 0) failed = 1; + force EN1 = 0; + force EN2 = 1; + #3; + #0 if (O !== 0) failed = 1; + #1; + #0 if (O !== 1) failed = 1; + force I2 = 0; + #2; + #0 if (O !== 1) failed = 1; + #1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh33.v b/ivtest/ivltests/br_gh33.v new file mode 100644 index 000000000..9128a3161 --- /dev/null +++ b/ivtest/ivltests/br_gh33.v @@ -0,0 +1,24 @@ +// Regression test for GitHub issue #33. + +module tb; + + reg [3:0] mem [0:15] [0:15]; + + task cycle; + input [3:0] a, b, c; + reg [3:0] tmp; + begin + tmp = mem[a][b]; + mem[a][b] = c; + $display("a=%d, b=%d, c=%d -> old=%d, new=%d", a, b, c, tmp, mem[a][b]); + end + endtask + + initial begin + cycle( 7, 0, 1); + cycle(15, 0, 2); + cycle( 7, 0, 3); + cycle(15, 0, 4); + end + +endmodule diff --git a/ivtest/ivltests/br_gh330.v b/ivtest/ivltests/br_gh330.v new file mode 100644 index 000000000..1a005181f --- /dev/null +++ b/ivtest/ivltests/br_gh330.v @@ -0,0 +1,607 @@ +module naughty_module( + input clk, + input [71:0] pzw, + input [95:0] xy_d, + input [23:0] pbit, + output [95:0] xas, + output [95:0] yas +); + +initial $display("PASSED"); + +function [3:0] xa; + input pbit; + input [1:0] ix_in; + input [1:0] iy_in; + input [3:0] pzw; +begin + xa = + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h0} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h1} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h2} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h3} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h4} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h5} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h6} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h7} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h0} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h1} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h2} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h3} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h4} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h5} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h6} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h7} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h0} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h1} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h2} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h3} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h4} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h5} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h6} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h7} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h0} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h1} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h2} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h3} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h4} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h5} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h6} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h7} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h0} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h1} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h2} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h3} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h4} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h5} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h6} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h7} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h0} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h1} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h2} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h3} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h4} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h5} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h6} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h7} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h0} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h1} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h2} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h3} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h4} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h5} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h6} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h7} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h0} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h1} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h2} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h3} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h4} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h5} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h6} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h7} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h0} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h1} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h2} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h3} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h4} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h5} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h6} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h7} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h0} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h1} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h2} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h3} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h4} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h5} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h6} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h7} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h0} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h1} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h2} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h3} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h4} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h5} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h6} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h7} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h0} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h1} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h2} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h3} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h4} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h5} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h6} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h7} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h0} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h1} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h2} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h3} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h4} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h5} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h6} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h7} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h0} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h1} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h2} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h3} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h4} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h5} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h6} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h7} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h0} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h1} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h2} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h3} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h4} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h5} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h6} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h7} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h0} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h1} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h2} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h3} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h4} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h5} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h6} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h7} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h0} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h1} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h2} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h3} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h4} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h5} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h6} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h7} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h0} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h1} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h2} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h3} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h4} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h5} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h6} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h7} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h0} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h1} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h2} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h3} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h4} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h5} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h6} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h7} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h0} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h1} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h2} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h3} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h4} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h5} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h6} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h7} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h0} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h1} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h2} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h3} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h4} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h5} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h6} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h7} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h0} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h1} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h2} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h3} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h4} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h5} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h6} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h7} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h0} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h1} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h2} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h3} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h4} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h5} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h6} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h7} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h0} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h1} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h2} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h3} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h4} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h5} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h6} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h7} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h0} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h1} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h2} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h3} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h4} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h5} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h6} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h7} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h0} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h1} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h2} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h3} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h4} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h5} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h6} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h7} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h0} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h1} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h2} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h3} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h4} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h5} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h6} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h7} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h0} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h1} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h2} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h3} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h4} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h5} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h6} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h7} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h0} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h1} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h2} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h3} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h4} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h5} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h6} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h7} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h0} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h1} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h2} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h3} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h4} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h5} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h6} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h7} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h0} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h1} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h2} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h3} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h4} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h5} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h6} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h7} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h0} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h1} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h2} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h3} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h4} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h5} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h6} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h7} ? 4'h3 : + 4'h0; +end +endfunction + +function [3:0] ya; + input pbit; + input [1:0] ix_in; + input [1:0] iy_in; + input [3:0] pzw; +begin + ya = + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h0} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h1} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h2} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h3} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h4} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h5} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h6} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h0, 3'h7} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h0} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h1} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h2} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h3} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h4} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h5} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h6} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h1, 3'h7} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h0} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h1} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h2} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h3} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h4} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h5} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h6} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h2, 3'h7} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h0} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h1} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h2} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h3} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h4} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h5} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h6} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h0, 2'h3, 3'h7} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h0} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h1} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h2} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h3} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h4} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h5} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h6} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h0, 3'h7} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h0} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h1} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h2} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h3} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h4} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h5} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h6} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h1, 3'h7} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h0} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h1} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h2} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h3} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h4} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h5} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h6} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h2, 3'h7} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h0} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h1} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h2} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h3} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h4} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h5} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h6} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h1, 2'h3, 3'h7} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h0} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h1} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h2} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h3} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h4} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h5} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h6} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h0, 3'h7} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h0} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h1} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h2} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h3} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h4} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h5} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h6} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h1, 3'h7} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h0} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h1} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h2} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h3} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h4} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h5} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h6} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h2, 3'h7} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h0} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h1} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h2} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h3} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h4} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h5} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h6} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h2, 2'h3, 3'h7} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h0} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h1} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h2} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h3} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h4} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h5} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h6} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h0, 3'h7} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h0} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h1} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h2} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h3} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h4} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h5} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h6} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h1, 3'h7} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h0} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h1} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h2} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h3} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h4} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h5} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h6} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h2, 3'h7} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h0} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h1} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h2} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h3} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h4} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h5} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h6} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h0, 2'h3, 2'h3, 3'h7} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h0} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h1} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h2} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h3} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h4} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h5} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h6} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h0, 3'h7} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h0} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h1} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h2} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h3} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h4} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h5} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h6} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h1, 3'h7} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h0} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h1} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h2} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h3} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h4} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h5} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h6} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h2, 3'h7} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h0} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h1} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h2} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h3} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h4} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h5} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h6} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h0, 2'h3, 3'h7} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h0} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h1} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h2} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h3} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h4} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h5} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h6} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h0, 3'h7} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h0} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h1} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h2} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h3} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h4} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h5} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h6} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h1, 3'h7} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h0} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h1} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h2} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h3} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h4} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h5} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h6} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h2, 3'h7} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h0} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h1} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h2} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h3} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h4} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h5} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h6} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h1, 2'h3, 3'h7} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h0} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h1} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h2} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h3} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h4} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h5} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h6} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h0, 3'h7} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h0} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h1} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h2} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h3} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h4} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h5} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h6} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h1, 3'h7} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h0} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h1} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h2} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h3} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h4} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h5} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h6} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h2, 3'h7} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h0} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h1} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h2} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h3} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h4} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h5} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h6} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h2, 2'h3, 3'h7} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h0} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h1} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h2} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h3} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h4} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h5} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h6} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h0, 3'h7} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h0} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h1} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h2} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h3} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h4} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h5} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h6} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h1, 3'h7} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h0} ? 4'h5 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h1} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h2} ? 4'h8 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h3} ? 4'h7 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h4} ? 4'h4 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h5} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h6} ? 4'h1 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h2, 3'h7} ? 4'h2 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h0} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h1} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h2} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h3} ? 4'h9 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h4} ? 4'h6 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h5} ? 4'h3 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h6} ? 4'h0 : + {pbit, ix_in, iy_in, pzw} == {1'h1, 2'h3, 2'h3, 3'h7} ? 4'h0 : + 4'h0; +end +endfunction + + + reg [95:0] r_xa; + reg [95:0] r_ya; + + + always @(posedge clk) + begin + r_xa[ 3: 0] <= xa(pbit[ 0], xy_d[ 1: 0], xy_d[ 3: 2], pzw[ 2: 0]); + r_xa[ 7: 4] <= xa(pbit[ 1], xy_d[ 5: 4], xy_d[ 7: 6], pzw[ 5: 3]); + r_xa[11: 8] <= xa(pbit[ 2], xy_d[ 9: 8], xy_d[11:10], pzw[ 8: 6]); + r_xa[15: 12] <= xa(pbit[ 3], xy_d[13:12], xy_d[15:14], pzw[11: 9]); + r_xa[19: 16] <= xa(pbit[ 4], xy_d[17:16], xy_d[19:18], pzw[14:12]); + r_xa[23: 20] <= xa(pbit[ 5], xy_d[21:20], xy_d[23:22], pzw[17:15]); + r_xa[27: 24] <= xa(pbit[ 6], xy_d[25:24], xy_d[27:26], pzw[20:18]); + r_xa[31: 28] <= xa(pbit[ 7], xy_d[29:28], xy_d[31:30], pzw[23:21]); + r_xa[35: 32] <= xa(pbit[ 8], xy_d[33:32], xy_d[35:34], pzw[26:24]); + r_xa[39: 36] <= xa(pbit[ 9], xy_d[37:36], xy_d[39:38], pzw[29:27]); + r_xa[43: 40] <= xa(pbit[10], xy_d[41:40], xy_d[43:42], pzw[32:30]); + r_xa[47: 44] <= xa(pbit[11], xy_d[45:44], xy_d[47:46], pzw[35:33]); + r_xa[51: 48] <= xa(pbit[12], xy_d[49:48], xy_d[51:50], pzw[38:36]); + r_xa[55: 52] <= xa(pbit[13], xy_d[53:52], xy_d[55:54], pzw[41:39]); + r_xa[59: 56] <= xa(pbit[14], xy_d[57:56], xy_d[59:58], pzw[44:42]); + r_xa[63: 60] <= xa(pbit[15], xy_d[61:60], xy_d[63:62], pzw[47:45]); + r_xa[67: 64] <= xa(pbit[16], xy_d[65:64], xy_d[67:66], pzw[50:48]); + r_xa[71: 68] <= xa(pbit[17], xy_d[69:68], xy_d[71:70], pzw[53:51]); + r_xa[75: 72] <= xa(pbit[18], xy_d[73:72], xy_d[75:74], pzw[56:54]); + r_xa[79: 76] <= xa(pbit[19], xy_d[77:76], xy_d[79:78], pzw[59:57]); + r_xa[83: 80] <= xa(pbit[20], xy_d[81:80], xy_d[83:82], pzw[62:60]); + r_xa[87: 84] <= xa(pbit[21], xy_d[85:84], xy_d[87:86], pzw[65:63]); + r_xa[91: 88] <= xa(pbit[22], xy_d[89:88], xy_d[91:90], pzw[68:66]); + r_xa[95: 92] <= xa(pbit[23], xy_d[93:92], xy_d[95:94], pzw[71:69]); + + r_ya[ 3: 0] <= ya(pbit[ 0], xy_d[ 1: 0], xy_d[ 3: 2], pzw[ 2: 0]); + r_ya[ 7: 4] <= ya(pbit[ 1], xy_d[ 5: 4], xy_d[ 7: 6], pzw[ 5: 3]); + r_ya[11: 8] <= ya(pbit[ 2], xy_d[ 9: 8], xy_d[11:10], pzw[ 8: 6]); + r_ya[15: 12] <= ya(pbit[ 3], xy_d[13:12], xy_d[15:14], pzw[11: 9]); + r_ya[19: 16] <= ya(pbit[ 4], xy_d[17:16], xy_d[19:18], pzw[14:12]); + r_ya[23: 20] <= ya(pbit[ 5], xy_d[21:20], xy_d[23:22], pzw[17:15]); + r_ya[27: 24] <= ya(pbit[ 6], xy_d[25:24], xy_d[27:26], pzw[20:18]); + r_ya[31: 28] <= ya(pbit[ 7], xy_d[29:28], xy_d[31:30], pzw[23:21]); + r_ya[35: 32] <= ya(pbit[ 8], xy_d[33:32], xy_d[35:34], pzw[26:24]); + r_ya[39: 36] <= ya(pbit[ 9], xy_d[37:36], xy_d[39:38], pzw[29:27]); + r_ya[43: 40] <= ya(pbit[10], xy_d[41:40], xy_d[43:42], pzw[32:30]); + r_ya[47: 44] <= ya(pbit[11], xy_d[45:44], xy_d[47:46], pzw[35:33]); + r_ya[51: 48] <= ya(pbit[12], xy_d[49:48], xy_d[51:50], pzw[38:36]); + r_ya[55: 52] <= ya(pbit[13], xy_d[53:52], xy_d[55:54], pzw[41:39]); + r_ya[59: 56] <= ya(pbit[14], xy_d[57:56], xy_d[59:58], pzw[44:42]); + r_ya[63: 60] <= ya(pbit[15], xy_d[61:60], xy_d[63:62], pzw[47:45]); + r_ya[67: 64] <= ya(pbit[16], xy_d[65:64], xy_d[67:66], pzw[50:48]); + r_ya[71: 68] <= ya(pbit[17], xy_d[69:68], xy_d[71:70], pzw[53:51]); + r_ya[75: 72] <= ya(pbit[18], xy_d[73:72], xy_d[75:74], pzw[56:54]); + r_ya[79: 76] <= ya(pbit[19], xy_d[77:76], xy_d[79:78], pzw[59:57]); + r_ya[83: 80] <= ya(pbit[20], xy_d[81:80], xy_d[83:82], pzw[62:60]); + r_ya[87: 84] <= ya(pbit[21], xy_d[85:84], xy_d[87:86], pzw[65:63]); + r_ya[91: 88] <= ya(pbit[22], xy_d[89:88], xy_d[91:90], pzw[68:66]); + r_ya[95: 92] <= ya(pbit[23], xy_d[93:92], xy_d[95:94], pzw[71:69]); + end + + assign xas = r_xa; + assign yas = r_ya; + +endmodule diff --git a/ivtest/ivltests/br_gh337.v b/ivtest/ivltests/br_gh337.v new file mode 100644 index 000000000..c086df43b --- /dev/null +++ b/ivtest/ivltests/br_gh337.v @@ -0,0 +1,41 @@ +`ifdef __ICARUS__ + `define SUPPORT_TWO_STATE_NETS_IN_IVTEST +`endif + +module test(); + +int x2; +int z2; + +function int y2(int x); +endfunction + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +wire int w2 = y2(x2); +`else +wire integer w2 = 0; +`endif + +integer x4; +integer z4; + +function integer y4(integer x); +endfunction + +wire integer w4 = y4(x4); + +initial begin + #1; + $display(w2); + z2 = y2(x2); + $display(z2); + $display(w4); + z4 = y4(x4); + $display(z4); + if (w2 === 0 && z2 === 0 && w4 === 'bx && z4 === 'bx) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh345.v b/ivtest/ivltests/br_gh345.v new file mode 100644 index 000000000..9de50d24b --- /dev/null +++ b/ivtest/ivltests/br_gh345.v @@ -0,0 +1,100 @@ +// Based on https://github.com/YosysHQ/yosys/blob/master/tests/various/const_func.v +// +// ISC License +// +// Copyright (C) 2012 - 2020 Claire Wolf +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + +module Example(outA, outB, outC, outD); + parameter OUTPUT = "FOO"; + output wire [23:0] outA; + output wire [23:0] outB; + output reg outC, outD; + function automatic [23:0] flip; + input [23:0] inp; + flip = ~inp; + endfunction + + generate + if (flip(OUTPUT) == flip("BAR")) + assign outA = OUTPUT; + else + assign outA = 0; + + case (flip(OUTPUT)) + flip("FOO"): assign outB = OUTPUT; + flip("BAR"): assign outB = 0; + flip("BAZ"): assign outB = "HI"; + endcase + + genvar i; + initial outC = 0; + for (i = 0; i != flip(flip(OUTPUT[15:8])); i = i + 1) + if (i + 1 == flip(flip("O"))) + initial #1 outC = 1; + endgenerate + + integer j; + initial begin + outD = 1; + for (j = 0; j != flip(flip(OUTPUT[15:8])); j = j + 1) + if (j + 1 == flip(flip("O"))) + outD = 0; + end +endmodule + +module top(out); + wire [23:0] a1, a2, a3, a4; + wire [23:0] b1, b2, b3, b4; + wire c1, c2, c3, c4; + wire d1, d2, d3, d4; + Example e1(a1, b1, c1, d1); + Example #("FOO") e2(a2, b2, c2, d2); + Example #("BAR") e3(a3, b3, c3, d3); + Example #("BAZ") e4(a4, b4, c4, d4); + + output wire [24 * 8 - 1 + 4 :0] out; + assign out = { + a1, a2, a3, a4, + b1, b2, b3, b4, + c1, c2, c3, c4, + d1, d2, d3, d4}; + + initial begin + #2; + $display("%h %h %h %h", a1, a2, a3, a4); + $display("%h %h %h %h", b1, b2, b3, b4); + $display(c1,,c2,,c3,,c4); + $display(d1,,d2,,d3,,d4); + if((a1 === 0) + && (a2 === 0) + && (a3 === "BAR") + && (a4 === 0) + && (b1 === "FOO") + && (b2 === "FOO") + && (b3 === 0) + && (b4 === "HI") + && (c1 === 1) + && (c2 === 1) + && (c3 === 0) + && (c4 === 0) + && (d1 === 0) + && (d2 === 0) + && (d3 === 1) + && (d4 === 1)) + $display("PASSED"); + else + $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/br_gh356a.v b/ivtest/ivltests/br_gh356a.v new file mode 100644 index 000000000..0de02ca05 --- /dev/null +++ b/ivtest/ivltests/br_gh356a.v @@ -0,0 +1,41 @@ +module dut(input EN, input I, inout O); + +assign O = EN ? I : 1'bz; + +specify + (I => O) = (2); + (EN *> O) = (4); +endspecify + +endmodule + +module test(); + +reg EN; +reg I; +tri0 O; + +dut dut(EN, I, O); + +reg failed = 0; + +initial begin + $monitor($time,,EN,,I,,O); + EN = 0; + #4; + #0 if (O !== 0) failed = 1; + #1 I = 1; + #1 EN = 1; + #3; + #0 if (O !== 0) failed = 1; + #1; + #0 if (O !== 1) failed = 1; + + #1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh356b.v b/ivtest/ivltests/br_gh356b.v new file mode 100644 index 000000000..797ab9461 --- /dev/null +++ b/ivtest/ivltests/br_gh356b.v @@ -0,0 +1,43 @@ +module dut(input EN, input I, inout O); + +assign O = EN ? I : 1'bz; + +specify + (I => O) = (2); + (EN *> O) = (4); +endspecify + +endmodule + +module test(); + +reg EN; +reg I; +tri O; + +pulldown(O); + +dut dut(EN, I, O); + +reg failed = 0; + +initial begin + $monitor($time,,EN,,I,,O); + EN = 0; + #4; + #0 if (O !== 0) failed = 1; + #1 I = 1; + #1 EN = 1; + #3; + #0 if (O !== 0) failed = 1; + #1; + #0 if (O !== 1) failed = 1; + + #1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh361.v b/ivtest/ivltests/br_gh361.v new file mode 100644 index 000000000..3027b5988 --- /dev/null +++ b/ivtest/ivltests/br_gh361.v @@ -0,0 +1,29 @@ +module a(); +// Need to add enumerations to packages. + typedef enum logic[4:0] { + EXC_A = 0, + EXC_B = 1, + EXC_C = 2 + } exc_code_t; +// Need to search up the parent scope searching for the enum definition. + function exc_code_t func1(bit inx); + exc_code_t rVal; + case(inx) + 1 : rVal = EXC_C; + 0: rVal = EXC_B; + default: rVal = EXC_A; + endcase + return(rVal); + endfunction + exc_code_t exc_code; + initial begin +// Need to compare the base enumeration definition to check compatibility. + exc_code = func1(1'b1); + if(exc_code== EXC_C) begin + $display("PASSED"); + $finish; + end + $display("FAILED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/br_gh365.v b/ivtest/ivltests/br_gh365.v new file mode 100644 index 000000000..bc7914eff --- /dev/null +++ b/ivtest/ivltests/br_gh365.v @@ -0,0 +1,32 @@ +module tb(); + +typedef enum logic [1:0] { + IDLE = 0, + RESET = 1, + START = 2, + WAITFOR = 3 +} stateType; + +stateType state; + +string workingString = "WORKING"; + +initial begin + $display("DIRECT ASSIGNED STRING is ", workingString); + #10; + state = IDLE; +end + +string state_txt; + +always @* begin + case(state) + IDLE : state_txt = "IDLE"; + RESET : state_txt = "RST"; + START : state_txt = "STRT"; + WAITFOR : state_txt = "WAIT"; + endcase + $display("Controller's new state is %s",state_txt); +end + +endmodule diff --git a/ivtest/ivltests/br_gh366.v b/ivtest/ivltests/br_gh366.v new file mode 100644 index 000000000..42446fa47 --- /dev/null +++ b/ivtest/ivltests/br_gh366.v @@ -0,0 +1,10 @@ +`define PATH /usr/local/bin/ +`define STRINGIFY(x) `"x`" + +module test(); + +initial begin + $display( `STRINGIFY(`PATH) ); +end + +endmodule diff --git a/ivtest/ivltests/br_gh368.v b/ivtest/ivltests/br_gh368.v new file mode 100644 index 000000000..7881775d7 --- /dev/null +++ b/ivtest/ivltests/br_gh368.v @@ -0,0 +1,29 @@ +module top; + +task test_task; + begin + fork + begin + $display("Process #1"); + #20 + $display("Process #1 -- completes"); + end + begin + // Here's a timeout task. It should only complete if + // something in process #1 fails to complete. As such, + // it operates as a failsafe. + #1 + $display("Process #2"); + #200 + $display("Process #2 -- completes"); + end + join_any; + disable fork; + + $display("Test task completes"); + end +endtask + +initial test_task; + +endmodule diff --git a/ivtest/ivltests/br_gh37.v b/ivtest/ivltests/br_gh37.v new file mode 100644 index 000000000..861544fc1 --- /dev/null +++ b/ivtest/ivltests/br_gh37.v @@ -0,0 +1,16 @@ +// Regression test for GitHub issue #37 +module test; + wire [5:0] a; + wire [15:0] y; + + assign a = ~0; + assign y = 1 ? ~a >>> 5 : 0; + + initial begin + #10 $display("%b", y); + if (y === 16'b1111111111111110) + $display("PASSED"); + else + $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/br_gh374.v b/ivtest/ivltests/br_gh374.v new file mode 100644 index 000000000..416ca3b27 --- /dev/null +++ b/ivtest/ivltests/br_gh374.v @@ -0,0 +1,13 @@ +`define OPT1_DISPLAY $display("opt1"); +`define OPT2_DISPLAY $display("opt2"); + +`define INDIRECT_OPT(OPTN) ```OPTN``_DISPLAY + + +module t; + + initial begin + `INDIRECT_OPT(OPT1) + `INDIRECT_OPT(OPT2) + end +endmodule diff --git a/ivtest/ivltests/br_gh377.v b/ivtest/ivltests/br_gh377.v new file mode 100644 index 000000000..99fa9412c --- /dev/null +++ b/ivtest/ivltests/br_gh377.v @@ -0,0 +1,5 @@ +module test(); + +parameter name = 1; + +endmodule diff --git a/ivtest/ivltests/br_gh383a.v b/ivtest/ivltests/br_gh383a.v new file mode 100644 index 000000000..7af4e1e3f --- /dev/null +++ b/ivtest/ivltests/br_gh383a.v @@ -0,0 +1,22 @@ +module test; + logic [7:0] i, x[], y[], z[]; + + + initial begin + x = new [4]; + + for (i = 0; i < 4; i = i + 1) x[i] = 1 + i; + y = x; + z = new [4](x); + for (i = 0; i < 4; i = i + 1) y[i] = 4 - i; + for (i = 0; i < 4; i = i + 1) z[i] = 8 - i; + // Expected output: + // 1 2 3 4 + // 4 3 2 1 + // 8 7 6 5 + $display(x[0],,x[1],,x[2],,x[3]); + $display(y[0],,y[1],,y[2],,y[3]); + $display(z[0],,z[1],,z[2],,z[3]); + end + +endmodule diff --git a/ivtest/ivltests/br_gh383b.v b/ivtest/ivltests/br_gh383b.v new file mode 100644 index 000000000..b1d1f56c2 --- /dev/null +++ b/ivtest/ivltests/br_gh383b.v @@ -0,0 +1,22 @@ +module test; + bit [7:0] i, x[], y[], z[]; + + + initial begin + x = new [4]; + + for (i = 0; i < 4; i = i + 1) x[i] = 1 + i; + y = x; + z = new [4](x); + for (i = 0; i < 4; i = i + 1) y[i] = 4 - i; + for (i = 0; i < 4; i = i + 1) z[i] = 8 - i; + // Expected output: + // 1 2 3 4 + // 4 3 2 1 + // 8 7 6 5 + $display(x[0],,x[1],,x[2],,x[3]); + $display(y[0],,y[1],,y[2],,y[3]); + $display(z[0],,z[1],,z[2],,z[3]); + end + +endmodule diff --git a/ivtest/ivltests/br_gh383c.v b/ivtest/ivltests/br_gh383c.v new file mode 100644 index 000000000..240f6d566 --- /dev/null +++ b/ivtest/ivltests/br_gh383c.v @@ -0,0 +1,33 @@ +module test; + string x[], y[], z[]; + string src[0:7]; + int i; + + initial begin + src[0] = "a"; + src[1] = "b"; + src[2] = "c"; + src[3] = "d"; + src[4] = "e"; + src[5] = "f"; + src[6] = "g"; + src[7] = "h"; + + x = new [4]; + + for (i = 0; i < 4; i = i + 1) x[i] = src[i]; + + y = x; + z = new [4](x); + for (i = 0; i < 4; i = i + 1) y[i] = src[3 - i]; + for (i = 0; i < 4; i = i + 1) z[i] = src[7 - i]; + // Expected output: + // a b c d + // d c b a + // h g f e + $display(x[0],,x[1],,x[2],,x[3]); + $display(y[0],,y[1],,y[2],,y[3]); + $display(z[0],,z[1],,z[2],,z[3]); + end + +endmodule diff --git a/ivtest/ivltests/br_gh383d.v b/ivtest/ivltests/br_gh383d.v new file mode 100644 index 000000000..3e97ea8b6 --- /dev/null +++ b/ivtest/ivltests/br_gh383d.v @@ -0,0 +1,33 @@ +module test; + real x[], y[], z[]; + real src[0:7]; + int i; + + initial begin + src[0] = 1.0; + src[1] = 2.0; + src[2] = 3.0; + src[3] = 4.0; + src[4] = 5.0; + src[5] = 6.0; + src[6] = 7.0; + src[7] = 8.0; + + x = new [4]; + + for (i = 0; i < 4; i = i + 1) x[i] = src[i]; + + y = x; + z = new [4](x); + for (i = 0; i < 4; i = i + 1) y[i] = src[3 - i]; + for (i = 0; i < 4; i = i + 1) z[i] = src[7 - i]; + // Expected output: + // 1.00000 2.00000 3.00000 4.00000 + // 4.00000 3.00000 2.00000 1.00000 + // 8.00000 7.00000 6.00000 5.00000 + $display(x[0],,x[1],,x[2],,x[3]); + $display(y[0],,y[1],,y[2],,y[3]); + $display(z[0],,z[1],,z[2],,z[3]); + end + +endmodule diff --git a/ivtest/ivltests/br_gh386a.v b/ivtest/ivltests/br_gh386a.v new file mode 100644 index 000000000..f263b85c6 --- /dev/null +++ b/ivtest/ivltests/br_gh386a.v @@ -0,0 +1,23 @@ +module test(); + +typedef enum logic [8:0] { ILLEGAL, IA, IB } inst_t; + +inst_t ipb_inst; + +typedef struct packed { + inst_t inst; + logic iw; +} ipb_data_t; + +ipb_data_t ipb_d; + +initial begin + ipb_d.inst = IA; + ipb_inst = ipb_d.inst; + if (ipb_inst === IA) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh386b.v b/ivtest/ivltests/br_gh386b.v new file mode 100644 index 000000000..ec4d4fa1e --- /dev/null +++ b/ivtest/ivltests/br_gh386b.v @@ -0,0 +1,25 @@ +module test(); + +typedef enum logic [8:0] { ILLEGAL, IA, IB } inst_t; + +inst_t ipb_inst; + +typedef struct packed { + inst_t inst; + logic iw; +} ipb_data_t; + +ipb_data_t ipb_d; + +assign ipb_inst = ipb_d.inst; + +initial begin + ipb_d.inst = IA; + #1; + if (ipb_inst === IA) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh386c.v b/ivtest/ivltests/br_gh386c.v new file mode 100644 index 000000000..c843eda78 --- /dev/null +++ b/ivtest/ivltests/br_gh386c.v @@ -0,0 +1,9 @@ +module test(); + +typedef enum { a, b, c } enum_type; + +enum_type enum_value; + +assign enum_value = 1; + +endmodule diff --git a/ivtest/ivltests/br_gh386d.v b/ivtest/ivltests/br_gh386d.v new file mode 100644 index 000000000..ccd5771a7 --- /dev/null +++ b/ivtest/ivltests/br_gh386d.v @@ -0,0 +1,10 @@ +// This is currently unsupported, but is legal code. +module test(); + +typedef enum { a, b, c } enum_type; + +enum_type enum_value; + +assign enum_value = enum_type'(1); + +endmodule diff --git a/ivtest/ivltests/br_gh388.v b/ivtest/ivltests/br_gh388.v new file mode 100644 index 000000000..e6aadb7ba --- /dev/null +++ b/ivtest/ivltests/br_gh388.v @@ -0,0 +1,36 @@ +package test_pkg; + + class uvm_object; + function new (); + print("new uvm_object"); + endfunction : new + + virtual function void print (string str); + $display (str); + endfunction : print + endclass : uvm_object + + class uvm_report_object extends uvm_object; + function new (); + print("new uvm_report_object"); + endfunction : new + endclass : uvm_report_object + +endpackage : test_pkg + +module m; + import test_pkg::*; + uvm_report_object r_0; + uvm_object u_0; + + initial begin : test + #100; + u_0 = new(); + r_0 = new(); + + u_0.print("u_0"); + r_0.print("r_0"); + + end : test + +endmodule : m diff --git a/ivtest/ivltests/br_gh390a.v b/ivtest/ivltests/br_gh390a.v new file mode 100644 index 000000000..4c99903de --- /dev/null +++ b/ivtest/ivltests/br_gh390a.v @@ -0,0 +1,47 @@ +package test_pkg; + + virtual class uvm_void; + endclass : uvm_void + + class uvm_object extends uvm_void; + function new (string name = "uvm_object"); + $display("uvm_object::new(%s)", name); // XXXX + m_name = name; + endfunction : new + + virtual function void print (); + $display ("uvm_object::Print: m_name=%s", m_name); + endfunction : print + + string m_name; + + endclass : uvm_object + + class uvm_report_object extends uvm_object; + function new (string name = "uvm_report_object"); + // super.new must be the first statement in a constructor. + // If it is not, generate an error. + $display("uvm_report_object::new"); + super.new (name); + $display("uvm_report_object::new"); + endfunction : new + endclass : uvm_report_object + +endpackage : test_pkg + +module m; + import test_pkg::*; + uvm_object u0; + uvm_report_object u1; + + initial begin : test + #100; + $display ("Hello World"); + u0 = new (); + u0.print(); + u1 = new (); + u1.print(); + + end : test + +endmodule : m diff --git a/ivtest/ivltests/br_gh390b.v b/ivtest/ivltests/br_gh390b.v new file mode 100644 index 000000000..62375778a --- /dev/null +++ b/ivtest/ivltests/br_gh390b.v @@ -0,0 +1,44 @@ +package test_pkg; + + virtual class uvm_void; + endclass : uvm_void + + class uvm_object extends uvm_void; + + string m_name; + + function new (string name = "uvm_object"); + $display("uvm_object::new(%s)", name); // XXXX + m_name = name; + endfunction : new + + virtual function void print (); + $display ("uvm_object::Print: m_name=%s", m_name); + endfunction : print + + endclass : uvm_object + + class uvm_report_object extends uvm_object; + function new (string name = "uvm_report_object"); + super.new (name); + endfunction : new + endclass : uvm_report_object + +endpackage : test_pkg + +module m; + import test_pkg::*; + uvm_object u0; + uvm_report_object u1; + + initial begin : test + #100; + $display ("Hello World"); + u0 = new (); + u0.print(); + u1 = new (); + u1.print(); + + end : test + +endmodule : m diff --git a/ivtest/ivltests/br_gh391.v b/ivtest/ivltests/br_gh391.v new file mode 100644 index 000000000..4dca810b6 --- /dev/null +++ b/ivtest/ivltests/br_gh391.v @@ -0,0 +1,40 @@ +package test_pkg; + + class uvm_phase; + function void print(string str); + $display(str); + endfunction + endclass : uvm_phase + + class uvm_component; + virtual function void build_phase(uvm_phase phase); + phase.print("building"); + endfunction : build_phase + + virtual task run_phase(uvm_phase phase); + phase.print("running"); + endtask : run_phase + + virtual task run_all(); + uvm_phase p0; + + p0 = new(); + + this.build_phase(p0); + this.run_phase(p0); + endtask : run_all + + endclass : uvm_component + +endpackage : test_pkg + +module m; + import test_pkg::*; + uvm_component u0; + + initial begin : test + u0 = new(); + u0.run_all(); + end : test + +endmodule : m diff --git a/ivtest/ivltests/br_gh4.v b/ivtest/ivltests/br_gh4.v new file mode 100644 index 000000000..1142b4ef0 --- /dev/null +++ b/ivtest/ivltests/br_gh4.v @@ -0,0 +1,14 @@ +program test; + + class a; + function new(string str); + $display(str); + endfunction + endclass // a + + initial begin + a m_a; + m_a = new("PASSED"); + end + +endprogram diff --git a/ivtest/ivltests/br_gh411.v b/ivtest/ivltests/br_gh411.v new file mode 100644 index 000000000..79b26dcb4 --- /dev/null +++ b/ivtest/ivltests/br_gh411.v @@ -0,0 +1,12 @@ +module test(); + +function void do_nothing(); + ; +endfunction + +initial begin + do_nothing(); + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh412.v b/ivtest/ivltests/br_gh412.v new file mode 100644 index 000000000..f59cc785d --- /dev/null +++ b/ivtest/ivltests/br_gh412.v @@ -0,0 +1,16 @@ +module top; + int mbx[$]; + + initial begin + $display("mbx.size() == %0d", mbx.size()); + wait(mbx.size()); + $display("mbx.size() == %0d", mbx.size()); + $display("PASSED"); + end + + initial begin + #100 $display ("Push an item"); + mbx.push_back(1); + end +endmodule + diff --git a/ivtest/ivltests/br_gh414.v b/ivtest/ivltests/br_gh414.v new file mode 100644 index 000000000..877d3f021 --- /dev/null +++ b/ivtest/ivltests/br_gh414.v @@ -0,0 +1,39 @@ + +module tb; + string txt_i, txt_r, txt_h; + + int val_i; + int val_h; + real val_r; + + + initial begin + txt_i = "123"; + txt_r = "1.25"; + txt_h = "dead"; + val_i = txt_i.atoi(); + val_r = txt_r.atoreal(); + val_h = txt_h.atohex(); + + $display("txt_i=%s, val_i=%0d", txt_i, val_i); + if (val_i !== 123) begin + $display("FAILED"); + $finish; + end + + $display("txt_r=%s, val_r=%0f", txt_r, val_r); + if (val_r != 1.25) begin + $display("FAILED"); + $finish; + end + + $display("txt_h=%s, val_h=%0h", txt_h, val_h); + if (val_h !== 'hdead) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/br_gh418.v b/ivtest/ivltests/br_gh418.v new file mode 100644 index 000000000..10ff4cd4e --- /dev/null +++ b/ivtest/ivltests/br_gh418.v @@ -0,0 +1,23 @@ +module m; + + reg [31:0] count = 0; + + function void func1(); + count++; + if (count < 10) func2(); + endfunction + + function void func2(); + count++; + if (count < 10) func1(); + endfunction + + initial begin + func1(); + if (count == 10) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/br_gh433.v b/ivtest/ivltests/br_gh433.v new file mode 100644 index 000000000..0aa0937f3 --- /dev/null +++ b/ivtest/ivltests/br_gh433.v @@ -0,0 +1,26 @@ +module top; + reg passed; + int q[$]; + + initial begin + passed = 1'b1; + q.push_front(10); + q.pop_back(); // This should emit a warning + if (q.size() != 0) begin + $display("FAILED: pop_back() did not pop value when called as a task."); + passed = 1'b0; + end + + q.delete(); + q.push_front(20); + q.pop_front(); // This should emit a warning + if (q.size() != 0) begin + $display("FAILED: pop_front() did not pop value when called as a task."); + passed = 1'b0; + end + + q.size(); + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/br_gh435.v b/ivtest/ivltests/br_gh435.v new file mode 100644 index 000000000..c2020e0e9 --- /dev/null +++ b/ivtest/ivltests/br_gh435.v @@ -0,0 +1,10 @@ +`define display_passed \ + initial begin // comment \ + $display("PASSED"); \ + end + +module test(); + +`display_passed + +endmodule diff --git a/ivtest/ivltests/br_gh436.v b/ivtest/ivltests/br_gh436.v new file mode 100644 index 000000000..477f00983 --- /dev/null +++ b/ivtest/ivltests/br_gh436.v @@ -0,0 +1,37 @@ + +// This program should emit: +// m_argv[0] = str0 +// LARGE: 4 +// LARGE: 4 (2) +// m_argv[1] = str1 +// LARGE: 4 +// LARGE: 4 (2) +// + +module m; + + string m_argv [$]; + + function int size_function(input string val); + size_function = val.len(); + endfunction // size_function + + initial begin + m_argv.push_back ("str0"); + m_argv.push_back ("str1"); + + foreach (m_argv[i]) begin + $display("m_argv[%0d] = %s", i, m_argv[i]); + if(m_argv[i].len() >= 2) begin + $display ("LARGE: %0d", m_argv[i].len()); + end else begin + $display("FAILED: m_argv[i].len() == %0d", m_argv[i].len()); + end + if(size_function(m_argv[i]) >= 2) begin + $display ("LARGE: %0d (2)", size_function(m_argv[i])); + end else begin + $display("FAILED: size_function(m_argv[i]) == %0d", size_function(m_argv[i])); + end + end + end +endmodule : m diff --git a/ivtest/ivltests/br_gh437.v b/ivtest/ivltests/br_gh437.v new file mode 100644 index 000000000..22c808c93 --- /dev/null +++ b/ivtest/ivltests/br_gh437.v @@ -0,0 +1,26 @@ +package ivl_uvm_pkg; + virtual class uvm_test; + task ok; + $display("PASSED"); + endtask + endclass : uvm_test +endpackage : ivl_uvm_pkg + +package test_pkg; + import ivl_uvm_pkg::*; + class sanity_test extends uvm_test; + endclass : sanity_test +endpackage : test_pkg + +module m; + + import test_pkg::*; + + sanity_test obj; + + initial begin + obj = new; + obj.ok; + end + +endmodule : m diff --git a/ivtest/ivltests/br_gh440.v b/ivtest/ivltests/br_gh440.v new file mode 100644 index 000000000..54ef9b1f8 --- /dev/null +++ b/ivtest/ivltests/br_gh440.v @@ -0,0 +1,55 @@ +package t; + class c; + virtual function create (string name=""); + return null; // Error: logic returning a null + endfunction + + endclass : c +endpackage + +module m; + import t::*; + int idx, idx2; + + c carr [0:1][0:3]; + + class c2; + static c sval; + c val; + c arr [0:1]; + task check; + if (sval == null) $display("Empty"); // Okay + if (val == null) $display("Empty"); // Okay + if (arr[0] == null) $display("Empty"); // Okay + endtask + endclass + + + // An implicit logic return type is given a NULL + function tmp(); + return null; // Error: logic returning a null + endfunction + + c cls; + + logic val; + + initial begin + idx = 0; + idx2 = 0; + if (cls == null) $display("Empty"); // Okay + if (carr[0][0] == null) $display("Empty"); // Okay + if (carr[idx][idx2] == null) $display("Empty"); // Okay + if (0 == null) $display("Empty"); // Error: logic comp null + val = 1|null; // Error: logic binop null + val = 1< triggerA; +end + +always @(triggerA) begin + countA = countA + 1; +end + +always_comb begin + $display("%0t: B", $time); + o2 = i1; + o3 = i2; + -> triggerB; +end + +always @(triggerB) begin + countB = countB + 1; +end + +initial begin + #1 i1 = 1; + #1 i2 = 1; + #1; + if (countA === 2 && countB === 3) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh508b.v b/ivtest/ivltests/br_gh508b.v new file mode 100644 index 000000000..bc546ad2a --- /dev/null +++ b/ivtest/ivltests/br_gh508b.v @@ -0,0 +1,30 @@ +module test; + +event i1, i2, i3; + +integer countA, countB; + +always @(i1 or i2) begin + $display("%0t: A", $time); + countA = countA + 1; +end + +always @(i2 or i3) begin + $display("%0t: B", $time); + countB = countB + 1; +end + +initial begin + countA = 0; + countB = 0; + #1 ->i1; + #1 ->i2; + #1 ->i3; + #1; + if (countA === 2 && countB === 2) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh515.v b/ivtest/ivltests/br_gh515.v new file mode 100644 index 000000000..b415edb47 --- /dev/null +++ b/ivtest/ivltests/br_gh515.v @@ -0,0 +1,27 @@ +module test; + +reg [7:0] array[7:0]; + +reg [2:0] index; + +reg [7:0] value; + +reg failed = 0; + +initial begin + array[0] = 1; + index = 7; + value = array[index + 1]; + $display("%h", value); + if (value !== 8'bx) failed = 1; + value = array[index + 3'd1]; + $display("%h", value); + if (value !== 8'd1) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh527.v b/ivtest/ivltests/br_gh527.v new file mode 100644 index 000000000..97b572c31 --- /dev/null +++ b/ivtest/ivltests/br_gh527.v @@ -0,0 +1,29 @@ +typedef struct packed { + union packed { + logic[2:0] a; + logic[2:0] b; + } u; +} s1; + +module top(); + +s1 source; +logic result; + +logic failed = 0; + +initial begin + source.u.a = 3'b000; + result = | source.u.b; + if (result !== 1'b0) failed = 1; + source.u.a = 3'b001; + result = | source.u.b; + if (result !== 1'b1) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh530.v b/ivtest/ivltests/br_gh530.v new file mode 100644 index 000000000..013c0cd58 --- /dev/null +++ b/ivtest/ivltests/br_gh530.v @@ -0,0 +1,13 @@ +module dut(a,); + + input wire a; + +endmodule + +module top; + + wire a; + + dut i(.*); + +endmodule diff --git a/ivtest/ivltests/br_gh531.v b/ivtest/ivltests/br_gh531.v new file mode 100644 index 000000000..fdf2dcb79 --- /dev/null +++ b/ivtest/ivltests/br_gh531.v @@ -0,0 +1,69 @@ +module top; + +function automatic [2:1] f1(input [3:0] i); + begin + f1[0] = i[0]; + f1[1] = i[1]; + f1[2] = i[2]; + f1[3] = i[3]; + end +endfunction + +function automatic [3:0] f2(input [2:1] i); + begin + f2[0] = i[0]; + f2[1] = i[1]; + f2[2] = i[2]; + f2[3] = i[3]; + end +endfunction + +function automatic [2:1] f3(input [3:0] i); + begin + f3[1:0] = i[1:0]; + f3[3:2] = i[3:2]; + end +endfunction + +function automatic [3:0] f4(input [2:1] i); + begin + f4[1:0] = i[1:0]; + f4[3:2] = i[3:2]; + end +endfunction + +function automatic [2:1] f5(input [3:0] i); + reg [2:1] tmp; + begin + tmp[3:0] = 4'b0000; + tmp[3:0] |= i[3:0]; + f5 = tmp; + end +endfunction + +function automatic [3:0] f6(input [2:1] i); + reg [3:0] tmp; + begin + tmp[3:0] = 4'b0000; + tmp[3:0] |= i[3:0]; + f6 = tmp; + end +endfunction + +localparam C1 = f1(4'b0011); +localparam C2 = f2(2'b01); +localparam C3 = f3(4'b0011); +localparam C4 = f4(2'b01); +localparam C5 = f5(4'b0011); +localparam C6 = f6(2'b01); + +initial begin + $display("C1 %b", C1); + $display("C2 %b", C2); + $display("C3 %b", C3); + $display("C4 %b", C4); + $display("C5 %b", C5); + $display("C6 %b", C6); +end + +endmodule diff --git a/ivtest/ivltests/br_gh533.v b/ivtest/ivltests/br_gh533.v new file mode 100644 index 000000000..c27f69d85 --- /dev/null +++ b/ivtest/ivltests/br_gh533.v @@ -0,0 +1,6 @@ +module top; + genvar i; + for (i = 100; i < 101; i = i + 1) + for (i = 100; i < 101; i = i + 1) + initial $display("%b %0d", i, $bits(i)); +endmodule diff --git a/ivtest/ivltests/br_gh540.v b/ivtest/ivltests/br_gh540.v new file mode 100644 index 000000000..611405747 --- /dev/null +++ b/ivtest/ivltests/br_gh540.v @@ -0,0 +1,64 @@ +module top( + pi_wi, // port implicit, wire implicit + pi_ws, // port implicit, wire signed + pi_wu, // port implicit, wire unsigned + + ps_wi, // port signed, wire implicit + ps_ws, // port signed, wire signed + ps_wu, // port signed, wire unsigned + + pu_wi, // port unsigned, wire implicit + pu_ws, // port unsigned, wire signed + pu_wu // port unsigned, wire unsigned +); + +output pi_wi; +output pi_ws; +output pi_wu; + +output signed ps_wi; +output signed ps_ws; +output signed ps_wu; + +output unsigned pu_wi; +output unsigned pu_ws; +output unsigned pu_wu; + +wire pi_wi = 1'b1; +wire ps_wi = 1'b1; +wire pu_wi = 1'b1; + +wire signed pi_ws = 1'b1; +wire signed ps_ws = 1'b1; +wire signed pu_ws = 1'b1; + +wire unsigned pi_wu = 1'b1; +wire unsigned ps_wu = 1'b1; +wire unsigned pu_wu = 1'b1; + +reg [1:0] value; + +reg failed = 0; + +initial begin + #1; + + value = pi_wi; $display("%b", value); if (value !== 2'b01) failed = 1; + value = pi_ws; $display("%b", value); if (value !== 2'b11) failed = 1; + value = pi_wu; $display("%b", value); if (value !== 2'b01) failed = 1; + + value = ps_wi; $display("%b", value); if (value !== 2'b11) failed = 1; + value = ps_ws; $display("%b", value); if (value !== 2'b11) failed = 1; + value = ps_wu; $display("%b", value); if (value !== 2'b11) failed = 1; + + value = pu_wi; $display("%b", value); if (value !== 2'b01) failed = 1; + value = pu_ws; $display("%b", value); if (value !== 2'b11) failed = 1; + value = pu_wu; $display("%b", value); if (value !== 2'b01) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh553.v b/ivtest/ivltests/br_gh553.v new file mode 100644 index 000000000..dabca13c6 --- /dev/null +++ b/ivtest/ivltests/br_gh553.v @@ -0,0 +1,32 @@ +module dut; + +integer id; + +endmodule + +module test; + +dut inst[4]; + +integer i; + +reg failed = 0; + +initial begin + inst[0].id = 0; + inst[1].id = 1; + inst[2].id = 2; + inst[3].id = 3; + + if (inst[0].id !== 0) failed = 1; + if (inst[1].id !== 1) failed = 1; + if (inst[2].id !== 2) failed = 1; + if (inst[3].id !== 3) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh556.v b/ivtest/ivltests/br_gh556.v new file mode 100644 index 000000000..7da165456 --- /dev/null +++ b/ivtest/ivltests/br_gh556.v @@ -0,0 +1,18 @@ +module test; + +wire real array[1:0]; + +reg [7:0] index; + +real value; + +initial begin + index = 3; + value = array[index]; + if (value == 0.0) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh567.v b/ivtest/ivltests/br_gh567.v new file mode 100644 index 000000000..f0a4c7dd5 --- /dev/null +++ b/ivtest/ivltests/br_gh567.v @@ -0,0 +1,26 @@ +module test; + +wire [7:0] val[3:0]; + +genvar i; + +for (i = 3; i >= 0; i = i - 1) begin + assign val[i] = i; +end + +integer j; + +reg failed = 0; + +initial begin + for (j = 3; j >= 0; j = j - 1) begin + $display(val[j]); + if (val[j] != j) failed = 1; + end + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh568.v b/ivtest/ivltests/br_gh568.v new file mode 100644 index 000000000..b4ff5888b --- /dev/null +++ b/ivtest/ivltests/br_gh568.v @@ -0,0 +1,26 @@ +module test; + +wire [7:0] val[3:0]; + +genvar i; + +for (i = 3; i >= 0; i--) begin + assign val[i] = i; +end + +integer j; + +reg failed = 0; + +initial begin + for (j = 3; j >= 0; j = j - 1) begin + $display(val[j]); + if (val[j] != j) failed = 1; + end + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh6.v b/ivtest/ivltests/br_gh6.v new file mode 100644 index 000000000..fe15eb4c7 --- /dev/null +++ b/ivtest/ivltests/br_gh6.v @@ -0,0 +1,26 @@ +// Adapted from test case supplied in github issue #6 + +module bug(); + +reg a; +wire y; + +assign y = |(-a); + +reg failed = 0; + +initial begin + a = 0; + #1 $display("a = %b y = %b", a, y); + if (y !== 0) failed = 1; + a = 1; + #1 $display("a = %b y = %b", a, y); + if (y !== 1) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh60a.v b/ivtest/ivltests/br_gh60a.v new file mode 100644 index 000000000..ec0ea6fe7 --- /dev/null +++ b/ivtest/ivltests/br_gh60a.v @@ -0,0 +1,8 @@ +// Regression test for GitHub issue #60 part 1 - sized numeric constants +// must have size greater than zero. + +module test(); + +localparam Value = 0'b0; + +endmodule diff --git a/ivtest/ivltests/br_gh62.v b/ivtest/ivltests/br_gh62.v new file mode 100644 index 000000000..91621f144 --- /dev/null +++ b/ivtest/ivltests/br_gh62.v @@ -0,0 +1,22 @@ +// Regression test for GitHub issue #62 : assert on invalid verilog input + +module test(); + +reg [15:0] memory[3:0]; + +reg [15:0] vector; + +reg [3:0] value; + +initial begin + value = memory[0][0]; + value = memory[0][0][3:0]; + value = memory[0][0][0 +: 4]; + value = memory[0][0][4 -: 4]; + value = vector[0][0]; + value = vector[0][3:0]; + value = vector[0][0 +: 4]; + value = vector[0][4 -: 4]; +end + +endmodule diff --git a/ivtest/ivltests/br_gh7.v b/ivtest/ivltests/br_gh7.v new file mode 100644 index 000000000..d2680dec9 --- /dev/null +++ b/ivtest/ivltests/br_gh7.v @@ -0,0 +1,21 @@ +// Regression test for GitHub issue 7 : Undef propagation in power operator. + +module bug(); + +reg [3:0] a; +reg [3:0] y; + +reg failed = 0; + +initial begin + a = 4'd1 / 4'd0; + y = 4'd2 ** a; + $display("%b", a); + $display("%b", y); + if (y !== 4'bxxxx) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh72a.v b/ivtest/ivltests/br_gh72a.v new file mode 100644 index 000000000..7d5339ec6 --- /dev/null +++ b/ivtest/ivltests/br_gh72a.v @@ -0,0 +1,18 @@ +module modname; +`define macro1(arg1=d1) $display(`"arg1`"); +`define macro2(arg1=d1, arg2=d2) $display(`"arg1 arg2`"); + initial begin + `macro1() // Works + `macro1(1) // Works + + `macro2() // Cause wrong number of arguments error + `macro2(1) // Cause wrong number of arguments error + `macro2(1,2) // Works + + `macro2(,) // Works + `macro2(1,) // Works + `macro2(1,2) // Works + + `macro2(,2) // Works + end +endmodule diff --git a/ivtest/ivltests/br_gh72b.v b/ivtest/ivltests/br_gh72b.v new file mode 100644 index 000000000..0a0ba1cdd --- /dev/null +++ b/ivtest/ivltests/br_gh72b.v @@ -0,0 +1,9 @@ +module modname; +`define macro1(arg1) $display(`"arg1`"); +`define macro2(arg1=d1, arg2) $display(`"arg1 arg2`"); + initial begin + `macro1(1) + + `macro2(1,2) + end +endmodule diff --git a/ivtest/ivltests/br_gh72b_fail.v b/ivtest/ivltests/br_gh72b_fail.v new file mode 100644 index 000000000..fecfe1bbf --- /dev/null +++ b/ivtest/ivltests/br_gh72b_fail.v @@ -0,0 +1,12 @@ +module modname; +`define macro1(arg1) $display(`"arg1`"); +`define macro2(arg1=d1, arg2) $display(`"arg1 arg2`"); + initial begin + `macro1(1,2) // should fail + `macro1(,2) // should fail + + `macro2() // should fail + `macro2(1) // should fail + `macro2(1,2,3) // should fail + end +endmodule diff --git a/ivtest/ivltests/br_gh79.v b/ivtest/ivltests/br_gh79.v new file mode 100644 index 000000000..6c4c931b3 --- /dev/null +++ b/ivtest/ivltests/br_gh79.v @@ -0,0 +1,20 @@ +module test(); + +reg [3:0] BadNumber; + +initial begin + BadNumber = 4'b_; + BadNumber = 4'b_1; + BadNumber = 4'b1_; + BadNumber = 4'o_; + BadNumber = 4'o_1; + BadNumber = 4'o1_; + BadNumber = 4'd_; + BadNumber = 4'd_1; + BadNumber = 4'd1_; + BadNumber = 4'h_; + BadNumber = 4'h_1; + BadNumber = 4'h1_; +end + +endmodule diff --git a/ivtest/ivltests/br_gh8.v b/ivtest/ivltests/br_gh8.v new file mode 100644 index 000000000..271fe5fa3 --- /dev/null +++ b/ivtest/ivltests/br_gh8.v @@ -0,0 +1,34 @@ +// Regression test for GitHub issue 8 : Signedness handling in binary +// bitwise operations of constants. + +module bug(); + +localparam value1 = 4'sb1010 | 4'sb0000; +localparam value2 = 4'sb1010 + 4'sb0000; +localparam value3 = ~4'sb0101; +localparam value4 = -4'sb0101; + +reg signed [4:0] result; + +reg failed = 0; + +initial begin + result = value1; + $display("%b", result); + if (result !== 5'b11010) failed = 1; + result = value2; + $display("%b", result); + if (result !== 5'b11010) failed = 1; + result = value3; + $display("%b", result); + if (result !== 5'b11010) failed = 1; + result = value4; + $display("%b", result); + if (result !== 5'b11011) failed = 1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh9.v b/ivtest/ivltests/br_gh9.v new file mode 100644 index 000000000..0cad67a19 --- /dev/null +++ b/ivtest/ivltests/br_gh9.v @@ -0,0 +1,38 @@ +// Regression test for GitHub issue 9 : Efficiency of verinum and vpp_net +// pow() functions. + +module bug(); + +reg [5:0] ra; +reg [5:0] ry; + +wire [5:0] wa = 3; +wire [5:0] wy = wa ** 123456789; + +localparam [5:0] pa = 3; +localparam [5:0] py = pa ** 123456789; + +reg failed = 0; + +initial begin + #0; + + ra = 3; + ry = ra ** 123456789; + + $display("%b", ry); + if (ry !== 6'b110011) failed = 1; + + $display("%b", wy); + if (wy !== 6'b110011) failed = 1; + + $display("%b", py); + if (py !== 6'b110011) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99a.v b/ivtest/ivltests/br_gh99a.v new file mode 100644 index 000000000..480859330 --- /dev/null +++ b/ivtest/ivltests/br_gh99a.v @@ -0,0 +1,18 @@ +module test(); + +wire [7:0] value; +wire pass; + +assign value[3:0] = 4'd2; + +assign pass = (value === 8'bzzzz0010); + +initial begin + #2 $display("%b %b", value, pass); + if (pass === 1) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99b.v b/ivtest/ivltests/br_gh99b.v new file mode 100644 index 000000000..cbc925864 --- /dev/null +++ b/ivtest/ivltests/br_gh99b.v @@ -0,0 +1,18 @@ +module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4'd2; + +assign value2 = value1 + 8'd1; + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 8'bx) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99c.v b/ivtest/ivltests/br_gh99c.v new file mode 100644 index 000000000..8c7ce9939 --- /dev/null +++ b/ivtest/ivltests/br_gh99c.v @@ -0,0 +1,18 @@ +module test(); + +wire signed [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4'd2; + +assign value2 = abs(value1); + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 8'bx) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99d.v b/ivtest/ivltests/br_gh99d.v new file mode 100644 index 000000000..dc3ceb29e --- /dev/null +++ b/ivtest/ivltests/br_gh99d.v @@ -0,0 +1,19 @@ +module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4'd2; + +assign value2 = value1 + 0.0; + +initial begin + // value1 gets cast to real, so 'z' bits are converted to '0'. + #2 $display("%b %b", value1, value2); + if (value2 === 8'b00000010) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99e.v b/ivtest/ivltests/br_gh99e.v new file mode 100644 index 000000000..b7b730768 --- /dev/null +++ b/ivtest/ivltests/br_gh99e.v @@ -0,0 +1,19 @@ +module test(); + +wire [7:0] value1; +wire bit [7:0] value2; + +assign value1[3:0] = 4'd2; + +assign value2 = value1; + +initial begin + // value1 gets cast to 2-state, so 'z' bits are converted to '0'. + #2 $display("%b %b", value1, value2); + if (value2 === 8'b00000010) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99f.v b/ivtest/ivltests/br_gh99f.v new file mode 100644 index 000000000..24e4ddebc --- /dev/null +++ b/ivtest/ivltests/br_gh99f.v @@ -0,0 +1,19 @@ +module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4'd2; + +assign value2 = $itor(value1); + +initial begin + // 'z' bits are converted to '0'. + #2 $display("%b %b", value1, value2); + if (value2 === 8'b00000010) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99g.v b/ivtest/ivltests/br_gh99g.v new file mode 100644 index 000000000..41bff0c64 --- /dev/null +++ b/ivtest/ivltests/br_gh99g.v @@ -0,0 +1,18 @@ +module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4'd2; + +buf buffer[7:0](value2, value1); + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 8'bxxxx0010) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99h.v b/ivtest/ivltests/br_gh99h.v new file mode 100644 index 000000000..4cadd9314 --- /dev/null +++ b/ivtest/ivltests/br_gh99h.v @@ -0,0 +1,18 @@ +module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4'd2; + +not buffer[7:0](value2, value1); + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 8'bxxxx1101) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99i.v b/ivtest/ivltests/br_gh99i.v new file mode 100644 index 000000000..7a3e7f54e --- /dev/null +++ b/ivtest/ivltests/br_gh99i.v @@ -0,0 +1,18 @@ +module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4'd2; + +bufif1 buffer[7:0](value2, value1, 1'b1); + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 8'bxxxx0010) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99j.v b/ivtest/ivltests/br_gh99j.v new file mode 100644 index 000000000..8abe38b1d --- /dev/null +++ b/ivtest/ivltests/br_gh99j.v @@ -0,0 +1,18 @@ +module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4'd2; + +nmos buffer[7:0](value2, value1, 1'b1); + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 8'bzzzz0010) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99k.v b/ivtest/ivltests/br_gh99k.v new file mode 100644 index 000000000..3f4119631 --- /dev/null +++ b/ivtest/ivltests/br_gh99k.v @@ -0,0 +1,18 @@ +module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4'd2; + +cmos buffer[7:0](value2, value1, 1'b1, 1'b0); + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 8'bzzzz0010) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99l.v b/ivtest/ivltests/br_gh99l.v new file mode 100644 index 000000000..111e87fca --- /dev/null +++ b/ivtest/ivltests/br_gh99l.v @@ -0,0 +1,18 @@ +module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4'd2; + +assign value2 = value1 | 8'd1; + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 8'bxxxx0011) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99m.v b/ivtest/ivltests/br_gh99m.v new file mode 100644 index 000000000..a363862bc --- /dev/null +++ b/ivtest/ivltests/br_gh99m.v @@ -0,0 +1,18 @@ +module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4'd2; + +assign #1 value2 = value1; + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 8'bzzzz0010) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99o.v b/ivtest/ivltests/br_gh99o.v new file mode 100644 index 000000000..4f06941c9 --- /dev/null +++ b/ivtest/ivltests/br_gh99o.v @@ -0,0 +1,18 @@ +module test(); + +wire [7:0] value1; +wire value2; + +assign value1[3:0] = 4'd2; + +assign value2 = |value1; + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 1'b1) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99p.v b/ivtest/ivltests/br_gh99p.v new file mode 100644 index 000000000..5dc3ad94e --- /dev/null +++ b/ivtest/ivltests/br_gh99p.v @@ -0,0 +1,18 @@ +module test(); + +wire [7:0] value1; +wire [9:0] value2; + +assign value1[3:0] = 4'd2; + +assign value2 = {1'b0, value1, 1'b1}; + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 10'b0zzzz00101) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99q.v b/ivtest/ivltests/br_gh99q.v new file mode 100644 index 000000000..554308032 --- /dev/null +++ b/ivtest/ivltests/br_gh99q.v @@ -0,0 +1,18 @@ +module test(); + +wire [7:0] value1; +wire [15:0] value2; + +assign value1[3:0] = 4'd2; + +assign value2 = {2{value1}}; + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 16'bzzzz0010zzzz0010) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99r.v b/ivtest/ivltests/br_gh99r.v new file mode 100644 index 000000000..0e63910dc --- /dev/null +++ b/ivtest/ivltests/br_gh99r.v @@ -0,0 +1,18 @@ +module test(); + +wire [7:0] value1; +wire [9:0] value2; + +assign value1[3:0] = 4'd2; + +assign value2 = $signed(value1); + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 10'bzzzzzz0010) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99s.v b/ivtest/ivltests/br_gh99s.v new file mode 100644 index 000000000..e9b0e4396 --- /dev/null +++ b/ivtest/ivltests/br_gh99s.v @@ -0,0 +1,18 @@ +module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign value1[3:0] = 4'd2; + +assign (weak1,weak0) value2 = value1; + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 8'bzzzz0010) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99t.v b/ivtest/ivltests/br_gh99t.v new file mode 100644 index 000000000..cfd9a9627 --- /dev/null +++ b/ivtest/ivltests/br_gh99t.v @@ -0,0 +1,20 @@ +module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign (strong1,weak0) value1[3:0] = 4'b1010; + +nmos buffer[7:0](value2, value1, 1'b1); + +assign (strong1,weak0) value2 = 8'b00110011; + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 8'b00111011) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99u.v b/ivtest/ivltests/br_gh99u.v new file mode 100644 index 000000000..88c0b1cbc --- /dev/null +++ b/ivtest/ivltests/br_gh99u.v @@ -0,0 +1,20 @@ +module test(); + +wire [7:0] value1; +wire [7:0] value2; + +assign (strong1,weak0) value1[3:0] = 4'b1010; + +cmos buffer[7:0](value2, value1, 1'b1, 1'b0); + +assign (strong1,weak0) value2 = 8'b00110011; + +initial begin + #2 $display("%b %b", value1, value2); + if (value2 === 8'b00111011) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99v.v b/ivtest/ivltests/br_gh99v.v new file mode 100644 index 000000000..c6c086dad --- /dev/null +++ b/ivtest/ivltests/br_gh99v.v @@ -0,0 +1,26 @@ +module test(); + +wire [7:0] value1; +reg [7:0] value2; + +reg clk; + +assign value1[3:0] = 4'b1010; + +always @(posedge clk) begin + value2 <= value1; +end + +(* ivl_synthesis_off *) +initial begin + #1 clk = 0; + #1 clk = 1; + #1 clk = 0; + $display("%b %b", value1, value2); + if (value2 === 8'bzzzz1010) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99w.v b/ivtest/ivltests/br_gh99w.v new file mode 100644 index 000000000..3d4cf104e --- /dev/null +++ b/ivtest/ivltests/br_gh99w.v @@ -0,0 +1,27 @@ +module test(); + +wire [7:0] value1; +reg [7:0] value2; + +reg en; + +assign value1[3:0] = 4'b1010; + +always @* begin + if (en) + value2 <= value1; +end + +(* ivl_synthesis_off *) +initial begin + #1 en = 0; + #1 en = 1; + #1 en = 0; + $display("%b %b", value1, value2); + if (value2 === 8'bzzzz1010) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_gh99x.v b/ivtest/ivltests/br_gh99x.v new file mode 100644 index 000000000..29a127d4d --- /dev/null +++ b/ivtest/ivltests/br_gh99x.v @@ -0,0 +1,30 @@ +module test(); + +wire [7:0] value1; +reg [7:0] value2; + +reg clk; + +assign value1[3:0] = 4'b1010; + +always @(posedge clk) begin + value2[3:0] <= value1; +end + +(* ivl_synthesis_off *) +initial begin + #1 clk = 0; + #1 clk = 1; + #1 clk = 0; + $display("%b %b", value1, value2); +`ifdef __ICARUS_SYNTH__ + if (value2 === 8'bzzzz1010) +`else + if (value2 === 8'bxxxx1010) +`endif + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_ml20150315.v b/ivtest/ivltests/br_ml20150315.v new file mode 100644 index 000000000..90ae65b6e --- /dev/null +++ b/ivtest/ivltests/br_ml20150315.v @@ -0,0 +1,16 @@ +// Regression test for bug reported by Niels Moeller on +// 15-Mar-2015 via the iverilog-devel mailing list. +module test(); + +wire [7:0] my_net; + +assign my_net[3:0] = 1; +assign my_net[7:4] = 2; + +initial begin + #1 $monitor("At time %0t, field 1 = %h, field 2 = %h", + $time, my_net[3:0], my_net[7:4]); + #1 $finish(0); +end + +endmodule diff --git a/ivtest/ivltests/br_ml20150315b.v b/ivtest/ivltests/br_ml20150315b.v new file mode 100644 index 000000000..3bce10fcb --- /dev/null +++ b/ivtest/ivltests/br_ml20150315b.v @@ -0,0 +1,13 @@ +// Regression test for bug reported by Niels Moeller on +// 15-Mar-2015 via the iverilog-devel mailing list. +// Unpacked structs are not supported yet, but should +// be handled gracefully. +module test(); + +typedef struct { + logic value; +} data_t; + +data_t d; + +endmodule diff --git a/ivtest/ivltests/br_ml20150321.v b/ivtest/ivltests/br_ml20150321.v new file mode 100644 index 000000000..1ce9c743a --- /dev/null +++ b/ivtest/ivltests/br_ml20150321.v @@ -0,0 +1,89 @@ +// Regression test for bug reported by Niels Moeller on 21-Mar-2015 via +// iverilog-devel mailing list. Extended to cover similar problems. This +// is just testing compiler error recovery. + +module test(); + +integer array[3:0]; + +integer i1; + +always @* begin + for (i1 = 0; i1 < 4; i1 = i1 + 1) begin + array[i1] = undeclared; + end +end + +integer i2; + +always @* begin + for (i2 = 0; i2 < 4; i2 = i2 + 1) begin + undeclared = array[i2]; + end +end + +integer i3; + +always @* begin + for (i3 = undeclared; i3 < 4; i3 = i3 + 1) begin + array[i3] = i3; + end +end + +integer i4; + +always @* begin + for (i4 = 0; i4 < undeclared; i4 = i4 + 1) begin + array[i4] = i4; + end +end + +integer i5; + +always @* begin + for (i5 = 0; i5 < 4; i5 = i5 + undeclared) begin + array[i5] = i5; + end +end + +integer i6; + +always @* begin + i6 = 0; + while (i6 < undeclared) begin + array[i6] = i6; + i6 = i6 + 1; + end +end + +integer i7; + +always @* begin + i7 = 0; + while (i7 < 4) begin + array[i7] = undeclared; + i7 = i7 + 1; + end +end + +integer i8; + +always @* begin + i8 = 0; + repeat (undeclared) begin + array[i8] = i8; + i8 = i8 + 1; + end +end + +integer i9; + +always @* begin + i9 = 0; + repeat (4) begin + array[i9] = undeclared; + i9 = i9 + 1; + end +end + +endmodule diff --git a/ivtest/ivltests/br_ml20150424.v b/ivtest/ivltests/br_ml20150424.v new file mode 100644 index 000000000..89339532f --- /dev/null +++ b/ivtest/ivltests/br_ml20150424.v @@ -0,0 +1,16 @@ +// Regression test for bug reported by Orson on 24-Apr-15 via iverilog_devel. + +module test(); + +localparam value = $ivlh_to_unsigned((1000 / ($signed(13'd50))), 12); + +initial begin + $display("%d", value); + if (value === 20) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule + diff --git a/ivtest/ivltests/br_ml20150606.v b/ivtest/ivltests/br_ml20150606.v new file mode 100644 index 000000000..d04af02d6 --- /dev/null +++ b/ivtest/ivltests/br_ml20150606.v @@ -0,0 +1,26 @@ +module dut(input [3:0] DataI, output [3:0] DataO); + +wire [3:0] DataI; +reg [3:0] DataO; + +always @* DataO = DataI; + +endmodule + +module top(); + +reg [3:0] DataI; +wire [3:0] DataO; + +dut dut(DataI, DataO); + +initial begin + DataI = 5; + #1; + if (DataO === 5) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_ml20171017.v b/ivtest/ivltests/br_ml20171017.v new file mode 100644 index 000000000..c0ba66d92 --- /dev/null +++ b/ivtest/ivltests/br_ml20171017.v @@ -0,0 +1,14 @@ +module test(output [7:0] dataout[1:0]); + +assign dataout[0] = 8'h55; +assign dataout[1] = 8'haa; + +initial begin + #0; + if (dataout[0] === 8'h55 && dataout[1] === 8'haa) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_ml20180227.v b/ivtest/ivltests/br_ml20180227.v new file mode 100644 index 000000000..1467e95e1 --- /dev/null +++ b/ivtest/ivltests/br_ml20180227.v @@ -0,0 +1,11 @@ +module test(); + +string str; +reg [127:0] bitstr; + +initial begin + str = "hello"; + bitstr = str; +end + +endmodule diff --git a/ivtest/ivltests/br_ml20180309a.v b/ivtest/ivltests/br_ml20180309a.v new file mode 100644 index 000000000..098ae0b17 --- /dev/null +++ b/ivtest/ivltests/br_ml20180309a.v @@ -0,0 +1,20 @@ +module test(); + + string str1 = "abcd"; + string str2 = "efgh"; + + typedef logic [31:0] vector; + + vector data[1:0]; + + initial begin + data[0] = vector'(str1); + data[1] = vector'(str2); + $display("%s %s", data[0], data[1]); + if (data[0] === "abcd" && data[1] === "efgh") + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/br_ml20180309b.v b/ivtest/ivltests/br_ml20180309b.v new file mode 100644 index 000000000..df29a6683 --- /dev/null +++ b/ivtest/ivltests/br_ml20180309b.v @@ -0,0 +1,20 @@ +module test(); + + string str1 = "abcd"; + string str2 = "efgh"; + + typedef bit [31:0] vector; + + vector data[1:0]; + + initial begin + data[0] = vector'(str1); + data[1] = vector'(str2); + $display("%s %s", data[0], data[1]); + if (data[0] === "abcd" && data[1] === "efgh") + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/br_ml20181012a.v b/ivtest/ivltests/br_ml20181012a.v new file mode 100644 index 000000000..0356d2272 --- /dev/null +++ b/ivtest/ivltests/br_ml20181012a.v @@ -0,0 +1,5 @@ +module test(); + +reg [0] illegal; + +endmodule diff --git a/ivtest/ivltests/br_ml20181012b.v b/ivtest/ivltests/br_ml20181012b.v new file mode 100644 index 000000000..41fa9b474 --- /dev/null +++ b/ivtest/ivltests/br_ml20181012b.v @@ -0,0 +1,5 @@ +module test(); + +reg [] illegal; + +endmodule diff --git a/ivtest/ivltests/br_ml20181012c.v b/ivtest/ivltests/br_ml20181012c.v new file mode 100644 index 000000000..c3ae19b51 --- /dev/null +++ b/ivtest/ivltests/br_ml20181012c.v @@ -0,0 +1,5 @@ +module test(); + +reg [$] illegal; + +endmodule diff --git a/ivtest/ivltests/br_ml20181012d.v b/ivtest/ivltests/br_ml20181012d.v new file mode 100644 index 000000000..2a72aec5d --- /dev/null +++ b/ivtest/ivltests/br_ml20181012d.v @@ -0,0 +1,5 @@ +module test(); + +reg illegal[0]; + +endmodule diff --git a/ivtest/ivltests/br_ml20190806a.v b/ivtest/ivltests/br_ml20190806a.v new file mode 100644 index 000000000..2f94a0591 --- /dev/null +++ b/ivtest/ivltests/br_ml20190806a.v @@ -0,0 +1,42 @@ +primitive latch(q, e, d); + +output q; +input e; +input d; + +reg q; + +initial q = 1'b0; + +table +// e d | q | q+ | + 1 1 : ? : 1 ; + 1 0 : ? : 0 ; + 0 ? : ? : - ; +endtable + +endprimitive + +module test(); + +wire q; +reg e; +reg d; +reg r; + +latch latch(q, e, d); + +always @(q) begin + r = q; +end + +initial begin + #1; + // check that the always process executed before the initial process + if (r === 0) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_ml20190806b.v b/ivtest/ivltests/br_ml20190806b.v new file mode 100644 index 000000000..7e8abba1b --- /dev/null +++ b/ivtest/ivltests/br_ml20190806b.v @@ -0,0 +1,41 @@ +primitive latch(q, e, d); + +output q; +input e; +input d; + +reg q; + +table +// e d | q | q+ | + 1 1 : ? : 1 ; + 1 0 : ? : 0 ; + 0 ? : ? : - ; +endtable + +endprimitive + +module test(); + +wire q; +reg e; +reg d; +reg r; + +latch latch(q, e, d); + +always @(q) begin + r = 1; +end + +initial begin + #1; + $display("%b %b", q, r); + // the 'x' should propagate to q before the start of simulation + if (r === 1'bx && q === 1'bx) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_ml20190814.sdf b/ivtest/ivltests/br_ml20190814.sdf new file mode 100644 index 000000000..b007f0372 --- /dev/null +++ b/ivtest/ivltests/br_ml20190814.sdf @@ -0,0 +1,55 @@ +(DELAYFILE + +(SDFVERSION "3.0" ) + +(DESIGN "top") + +(DATE "Tue Aug 13 18:03:42 2019") + +(VENDOR "XILINX") + +(PROGRAM "Vivado") + +(VERSION "2019.1") + +(DIVIDER /) + +(TIMESCALE 1ps) + +(CELL + + (CELLTYPE "BUFGCE") + + (INSTANCE clk_IBUF_BUFG_inst) + + (DELAY + + (PATHPULSEPERCENT (30.0)) + + (ABSOLUTE + + (IOPATH I O (40.0:47.0:47.0) (40.0:47.0:47.0)) + + ) + + ) + + (TIMINGCHECK + + (SETUPHOLD (posedge CE) (posedge I) (84.0:275.0:275.0) (0.0:0.0:0.0)) + + (SETUPHOLD (negedge CE) (posedge I) (84.0:275.0:275.0) (0.0:0.0:0.0)) + + (PERIOD (posedge I) (1499.0:1499.0:1499.0)) + + (PERIOD (negedge I) (1499.0:1499.0:1499.0)) + + (WIDTH (negedge CE) (550.0:550.0:550.0)) + + (WIDTH (posedge CE) (550.0:550.0:550.0)) + + ) + +) + +) diff --git a/ivtest/ivltests/br_ml20190814.v b/ivtest/ivltests/br_ml20190814.v new file mode 100644 index 000000000..84ff7e615 --- /dev/null +++ b/ivtest/ivltests/br_ml20190814.v @@ -0,0 +1,39 @@ +`timescale 1ns/1ps + +module BUFGCE( + output O, + input I, + input CE +); + +bufif1(O, I, CE); + +specify + (I => O) = (0.1, 0.2); + (CE => O) = (0.3, 0.4); +endspecify + +endmodule + +module dut( + output out, + input in, + input en +); + +BUFGCE clk_IBUF_BUFG_inst(.O(out), .I(in), .CE(en)); + +endmodule + +module top; + +wire out; +reg in, en; + +dut dut(out, in, en); + +initial begin + $sdf_annotate("ivltests/br_ml20190814.sdf", dut); +end + +endmodule diff --git a/ivtest/ivltests/br_ml20191221.v b/ivtest/ivltests/br_ml20191221.v new file mode 100644 index 000000000..999c42dec --- /dev/null +++ b/ivtest/ivltests/br_ml20191221.v @@ -0,0 +1,24 @@ +module test; + +integer i; + +class myclass; + integer j; + function void init(); + j = i; + endfunction +endclass + +myclass c; + +initial begin + i = 1; + c = new; + c.init(); + if (c.j === 1) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_mw20171108.v b/ivtest/ivltests/br_mw20171108.v new file mode 100644 index 000000000..cb0da8bcd --- /dev/null +++ b/ivtest/ivltests/br_mw20171108.v @@ -0,0 +1,76 @@ +module bug(); + +function signed [31:0] fpreal( + input real in +); + +real m; +real r; + +begin + m = 1 << 16; + r = in * m; + fpreal = $rtoi(r); +end + +endfunction + +function signed [31:0] fpdiv( + input signed [31:0] a, + input signed [31:0] b +); + +reg signed [47:0] r; + +begin + r = a << 16; + fpdiv = r / b; +end + +endfunction + +function signed [31:0] fpmul( + input signed [31:0] a, + input signed [31:0] b +); + +reg signed [47:0] r; + +begin + r = a * b; + fpmul = r >>> 16; +end + +endfunction + +function signed [31:0] fppow( + input signed [31:0] a, + input real b +); + +real ar; +real r; + +begin + ar = $itor(a) / (1 << 16); + r = ar ** b; + fppow = fpreal(r); +end + +endfunction + +wire signed [31:0] a = 1 << 16; +wire signed [31:0] b = 4 << 16; + +wire signed [31:0] c = fpdiv(a, b); +wire signed [31:0] d = fppow(c, 2.0); + +initial begin + #1 $display("(%0f / %0f)**2.0 = %0f", a / 65536.0, b / 65536.0, d / 65536.0); + if (d === 32'h0000_1000) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/br_mw20200501.v b/ivtest/ivltests/br_mw20200501.v new file mode 100644 index 000000000..1e055f4ed --- /dev/null +++ b/ivtest/ivltests/br_mw20200501.v @@ -0,0 +1,16 @@ +module test(); + +reg [9:0] buffer[$]; +reg [9:0] out; + +initial begin + buffer.push_back(3); + out = buffer.pop_front(); + $display("out = %0d", out); + if (out === 3) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/bufif.v b/ivtest/ivltests/bufif.v new file mode 100644 index 000000000..deb131f74 --- /dev/null +++ b/ivtest/ivltests/bufif.v @@ -0,0 +1,91 @@ +// Copyright (c) 2000 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + + +/* + * This module implements what essentially amounts to an array of DFF + * devices with output enable. This test checks the operation of the + * bufif0 and bufif1 devices. + */ +module grayGap (ad, clk, read, write); + + output [31:0] ad; + input clk, read, write; + + reg [15:0] regff; + + bufif0 ad_drv [31:0] (ad, {16'b0, regff}, read); + + always @(posedge clk) + if (write) regff = ad[15:0]; + + +endmodule + + +module main; + + wire [31:0] ad; + reg clk, read, write; + + reg [31:0] ad_val; + reg ad_en; + + bufif1 ad_drv[31:0] (ad, ad_val, ad_en); + + grayGap test (ad, clk, read, write); + + always #10 clk = ~clk; + + initial begin + clk = 1; + read = 1; + write = 0; + $monitor($time, "ad=%b", ad); + + // Set up to write a value into the grayGap register. + @(negedge clk) + ad_val = 32'haaaa_aaaa; + read = 1; + write = 1; + ad_en = 1; + + // The posedge has passed, now set up to read that value + // out. Turn all the drivers off for a moment, to see that the + // line becomes tri-state... + @(negedge clk) + ad_en = 0; + write = 0; + + // Now read the value. + #1 read = 0; + + #1 $display("Wrote %h, got %h", ad_val, ad); + + if (ad !== 32'b0000_0000_0000_0000_1010_1010_1010_1010) begin + $display("FAILED -- ad is %b", ad); + $finish; + end + + #2 read = 1; + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/busbug.v b/ivtest/ivltests/busbug.v new file mode 100644 index 000000000..1ea1dfc62 --- /dev/null +++ b/ivtest/ivltests/busbug.v @@ -0,0 +1,12 @@ +module busbug (); + reg x,y,z; + initial begin + x=1'b0; + y=1'b0; + z=1'b1; + $display("%b%b=%b", + x ^ y, x ^ (y ^ z), + {x ^ y, x ^ (y ^ z)} + ); + end +endmodule diff --git a/ivtest/ivltests/ca_64delay.v b/ivtest/ivltests/ca_64delay.v new file mode 100644 index 000000000..73df10f51 --- /dev/null +++ b/ivtest/ivltests/ca_64delay.v @@ -0,0 +1,75 @@ +/* + * Verify that the continuous assignments support a delay that is + * greater than 32 bits. The top delays are in seconds and the other + * delays are in ps. The second delays all require more than 32 bits + * to work correctly. They will use the /d version. + */ + +`timescale 1s/1s +module gt32b; + wire real rlval; + wire rval; + wire aval[1:0]; + wire [7:0] psval; + + assign #1 rlval = 1.0; + assign #2 rval = 1'b1; + assign #3 aval[0] = 1'b0; + assign #4 psval[1] = 1'b1; + + initial begin + $timeformat(-12, 0, " ps", 16); + #1; + $display("dl:gt32b- %t", $realtime); + end + + always @(rlval) begin + $display("rl:gt32b- %t", $realtime); + end + + always @(rval) begin + $display("rg:gt32b- %t", $realtime); + end + + always @(aval[0]) begin + $display("ar:gt32b- %t", $realtime); + end + + always @(psval) begin + $display("ps:gt32b- %t", $realtime); + end +endmodule + +`timescale 1ps/1ps +module ls32b; + wire real rlval; + wire rval; + wire aval[1:0]; + wire [7:0] psval; + + assign #1 rlval = 1.0; + assign #2 rval = 1'b1; + assign #3 aval[0] = 1'b0; + assign #4 psval[1] = 1'b1; + + initial begin + #1; + $display("dl:ls32b- %t", $realtime); + end + + always @(rlval) begin + $display("rl:ls32b- %t", $realtime); + end + + always @(rval) begin + $display("rg:ls32b- %t", $realtime); + end + + always @(aval[0]) begin + $display("ar:ls32b- %t", $realtime); + end + + always @(psval) begin + $display("ps:ls32b- %t", $realtime); + end +endmodule diff --git a/ivtest/ivltests/ca_force.v b/ivtest/ivltests/ca_force.v new file mode 100644 index 000000000..72f86232e --- /dev/null +++ b/ivtest/ivltests/ca_force.v @@ -0,0 +1,52 @@ +module top; + reg pass; + reg in; + wire ca; + + assign ca = in; + + initial begin + pass = 1'b1; + if (ca !== 1'bx || in !== 1'bx) begin + $display("Failed T0 check, in %b, ca %b", in, ca); + pass = 1'b0; + end + + in = 1'b0; + #1; + if (ca !== 1'b0 || in !== 1'b0) begin + $display("Failed 0 check, in %b, ca %b", in, ca); + pass = 1'b0; + end + + in = 1'b1; + #1; + if (ca !== 1'b1 || in !== 1'b1) begin + $display("Failed 1 check, in %b, ca %b", in, ca); + pass = 1'b0; + end + + force ca = 1'b0; + #1; + if (ca !== 1'b0 || in !== 1'b1) begin + $display("Failed force 0 check, in %b, ca %b", in, ca); + pass = 1'b0; + end + + in = 1'bx; + #1; + if (ca !== 1'b0 || in !== 1'bx) begin + $display("Failed change a check, in %b, ca %b", in, ca); + pass = 1'b0; + end + + force ca = 1'b1; + #1; + if (ca !== 1'b1 || in !== 1'bx) begin + $display("Failed force 1 check, in %b, ca %b", in, ca); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/ca_func.v b/ivtest/ivltests/ca_func.v new file mode 100644 index 000000000..5847f2854 --- /dev/null +++ b/ivtest/ivltests/ca_func.v @@ -0,0 +1,30 @@ +module example(); + +reg [7:0] scale, a, b; + +wire [7:0] c; + +function [7:0] scaled; + +input [7:0] value; + +begin + scaled = value * scale; +end + +endfunction + +assign c = scaled(a) + scaled(b); + +initial begin + #1 a = 2; + #1 scale = 2; + #1 b = 3; + #1 $display(c); + if (c === 10) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/ca_mult.v b/ivtest/ivltests/ca_mult.v new file mode 100644 index 000000000..e0579ae38 --- /dev/null +++ b/ivtest/ivltests/ca_mult.v @@ -0,0 +1,13 @@ +module top; + real in; + wire signed [31:0] tmp; + + assign tmp = $rtoi(in*2.0); + + initial begin + for (in=-1.0; in <= 1.0; in=in+1.0) begin + #1 $display(tmp, " %.5f", in); + end + //$display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/ca_pow_signed.v b/ivtest/ivltests/ca_pow_signed.v new file mode 100644 index 000000000..b227f3ce3 --- /dev/null +++ b/ivtest/ivltests/ca_pow_signed.v @@ -0,0 +1,45 @@ +module top; + reg passed = 1'b1; + + reg signed [15:0] a, b; + + /* Currently the result can only be as big as a native long! */ + wire signed [31:0] r = a ** b; + + initial begin + + a = 5; + b = 2; + #1 + if (r != 25) begin + $display("Failed: 5 ** 2 gave %d, expected 25", r); + passed = 1'b0; + end + + a = -5; + b = 3; + #1 + if (r != -125) begin + $display("Failed: -5 ** 3 gave %d, expected -125", r); + passed = 1'b0; + end + + a = 2; + b = 30; + #1 + if (r != 1_073_741_824) begin + $display("Failed: 2 ** 30 gave %d, expected 1,073,741,824", r); + passed = 1'b0; + end + + a = -2; + b = 31; + #1 + if (r != -2_147_483_648) begin + $display("Failed: -2 ** 31 gave %d, expected -2,147,483,648", r); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/ca_pow_synth.v b/ivtest/ivltests/ca_pow_synth.v new file mode 100644 index 000000000..15222ee5c --- /dev/null +++ b/ivtest/ivltests/ca_pow_synth.v @@ -0,0 +1,31 @@ +module top; + reg pass = 1'b1; + reg [2:0] in; + real rin; + wire out, rout; + + assign out = ('d4 == in**2'd2); + assign rout = (4.0 == rin**2); + + initial begin + in = 'd0; rin = 0.0; + #1 if (out != 1'b0 && rout != 1'b0) begin + $display("FAILED 0/0.0 check"); + pass = 1'b0; + end + + #1 in = 'd1; rin = 1.0; + #1 if (out != 1'b0 && rout != 1'b0) begin + $display("FAILED 1/1.0 check"); + pass = 1'b0; + end + + #1 in = 'd2; rin = 2.0; + #1 if (out != 1'b1 && rout != 1'b1) begin + $display("FAILED 2/2.0 check"); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/ca_pow_unsigned.v b/ivtest/ivltests/ca_pow_unsigned.v new file mode 100644 index 000000000..462c8a566 --- /dev/null +++ b/ivtest/ivltests/ca_pow_unsigned.v @@ -0,0 +1,41 @@ +module top; + reg passed = 1'b1; + + reg [199:0] a, b; + wire [199:0] r; + + assign #1 r = a ** b; + + initial begin + a = 'd5; + + b = 'd2; // A simple test. + #2; + if (r != 'd25) begin + $display("Failed: 5 ** 2 gave %d, expected 25", r); + passed = 1'b0; + end + + b = 'd55; // A 128 bit value. + #2; + if (r != 200'd277555756156289135105907917022705078125) begin + $display("Failed: 5 ** 55\n gave %0d", r); + $display(" expected 277555756156289135105907917022705078125"); + passed = 1'b0; + end + + b = 'd86; // A 200 bit value. + #2; + if (r != 200'd1292469707114105741986576081359316958696581423282623291015625) begin + $display("Failed: 5 ** 55\n gave %0d", r); + $display(" expected 1292469707114105741986576081359316958696581423282623291015625"); + passed = 1'b0; + end + if (r != 'd5**'d86) begin + $display("Failed: compile-time/run-time value mismatch."); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/ca_real_logical.v b/ivtest/ivltests/ca_real_logical.v new file mode 100644 index 000000000..6f195fc60 --- /dev/null +++ b/ivtest/ivltests/ca_real_logical.v @@ -0,0 +1,231 @@ +module top; + parameter parg0 = 0.0; + parameter parg1 = 1.0; + parameter parg2 = 2.0; + parameter pargi = 1.0/0.0; // Inf. + parameter pargn = $sqrt(-1.0); // NaN. + real arg0, arg1, arg2, argi, argn; + reg pass; + + wire r_p0_b = !parg0; + wire r_p1_b = !parg1; + wire r_p2_b = !parg2; + wire r_pi_b = !pargi; + wire r_pn_b = !pargn; + + wire r_0_b = !arg0; + wire r_1_b = !arg1; + wire r_2_b = !arg2; + wire r_i_b = !argi; + wire r_n_b = !argn; + + wire r_p01_a = parg0 && parg1; + wire r_p02_a = parg0 && parg2; + wire r_p12_a = parg1 && parg2; + + wire r_01_a = arg0 && arg1; + wire r_02_a = arg0 && arg2; + wire r_12_a = arg1 && arg2; + + wire r_p00_o = parg0 || 0; + wire r_p01_o = parg0 || parg1; + wire r_p02_o = parg0 || parg2; + + wire r_00_o = arg0 || 0; + wire r_01_o = arg0 || arg1; + wire r_02_o = arg0 || arg2; + + wire r_p0_t = parg0 ? 1'b1 : 1'b0; + wire r_p1_t = parg1 ? 1'b1 : 1'b0; + wire r_p2_t = parg2 ? 1'b1 : 1'b0; + wire r_pi_t = pargi ? 1'b1 : 1'b0; + wire r_pn_t = pargn ? 1'b1 : 1'b0; + + wire r_0_t = arg0 ? 1'b1 : 1'b0; + wire r_1_t = arg1 ? 1'b1 : 1'b0; + wire r_2_t = arg2 ? 1'b1 : 1'b0; + wire r_i_t = argi ? 1'b1 : 1'b0; + wire r_n_t = argn ? 1'b1 : 1'b0; + + initial begin + pass = 1'b1; + + arg0 = 0.0; + arg1 = 1.0; + arg2 = 2.0; + argi = 1.0/0.0; // Inf. + argn = $sqrt(-1.0); // NaN. + + #1; + + /* Check ! on a constant real value. */ + if (r_p0_b !== 1'b1) begin + $display("Failed: CA constant !0.0, expected 1'b1, got %b", r_p0_b); + pass = 1'b0; + end + + if (r_p1_b !== 1'b0) begin + $display("Failed: CA constant !1.0, expected 1'b0, got %b", r_p1_b); + pass = 1'b0; + end + + if (r_p2_b !== 1'b0) begin + $display("Failed: CA constant !2.0, expected 1'b0, got %b", r_p2_b); + pass = 1'b0; + end + + if (r_pi_b !== 1'b0) begin + $display("Failed: CA constant !Inf, expected 1'b0, got %b", r_pi_b); + pass = 1'b0; + end + + if (r_pn_b !== 1'b0) begin + $display("Failed: CA constant !NaN, expected 1'b0, got %b", r_pn_b); + pass = 1'b0; + end + + /* Check ! on a real variable. */ + if (r_0_b !== 1'b1) begin + $display("Failed: !0.0, expected 1'b1, got %b", r_0_b); + pass = 1'b0; + end + + if (r_1_b !== 1'b0) begin + $display("Failed: !1.0, expected 1'b0, got %b", r_1_b); + pass = 1'b0; + end + + if (r_2_b !== 1'b0) begin + $display("Failed: !2.0, expected 1'b0, got %b", r_2_b); + pass = 1'b0; + end + + if (r_i_b !== 1'b0) begin + $display("Failed: !Inf, expected 1'b0, got %b", r_i_b); + pass = 1'b0; + end + + if (r_n_b !== 1'b0) begin + $display("Failed: !NaN, expected 1'b0, got %b", r_n_b); + pass = 1'b0; + end + + /* Check && on a constant real value. */ + if (r_p01_a !== 1'b0) begin + $display("Failed: constant 0.0 && 1.0, expected 1'b0, got %b", r_p01_a); + pass = 1'b0; + end + + if (r_p02_a !== 1'b0) begin + $display("Failed: constant 0.0 && 2.0, expected 1'b0, got %b", r_p02_a); + pass = 1'b0; + end + + if (r_p12_a !== 1'b1) begin + $display("Failed: constant 1.0 && 2.0, expected 1'b1, got %b", r_p12_a); + pass = 1'b0; + end + + /* Check && on a real variable. */ + if (r_01_a !== 1'b0) begin + $display("Failed: 0.0 && 1.0, expected 1'b0, got %b", r_01_a); + pass = 1'b0; + end + + if (r_02_a !== 1'b0) begin + $display("Failed: 0.0 && 2.0, expected 1'b0, got %b", r_02_a); + pass = 1'b0; + end + + if (r_12_a !== 1'b1) begin + $display("Failed: 1.0 && 2.0, expected 1'b1, got %b", r_12_a); + pass = 1'b0; + end + + /* Check || on a constant real value. */ + if (r_p00_o !== 1'b0) begin + $display("Failed: constant 0.0 || 0, expected 1'b0, got %b", r_p00_o); + pass = 1'b0; + end + + if (r_p01_o !== 1'b1) begin + $display("Failed: constant 0.0 || 1.0, expected 1'b1, got %b", r_p01_o); + pass = 1'b0; + end + + if (r_p02_o !== 1'b1) begin + $display("Failed: constant 0.0 || 2.0, expected 1'b1, got %b", r_p02_o); + pass = 1'b0; + end + + /* Check || on a real variable. */ + if (r_00_o !== 1'b0) begin + $display("Failed: 0.0 || 0, expected 1'b0, got %b", r_00_o); + pass = 1'b0; + end + + if (r_01_o !== 1'b1) begin + $display("Failed: 0.0 || 1.0, expected 1'b1, got %b", r_01_o); + pass = 1'b0; + end + + if (r_02_o !== 1'b1) begin + $display("Failed: 0.0 || 2.0, expected 1'b1, got %b", r_02_o); + pass = 1'b0; + end + + /* Check the ternary with a constant real cond. value. */ + if (r_p0_t !== 1'b0) begin + $display("Failed: constant 0.0 ? ..., expected 1'b0, got %b", r_p0_t); + pass = 1'b0; + end + + if (r_p1_t !== 1'b1) begin + $display("Failed: constant 1.0 ? ..., expected 1'b1, got %b", r_p1_t); + pass = 1'b0; + end + + if (r_p2_t !== 1'b1) begin + $display("Failed: constant 2.0 ? ..., expected 1'b1, got %b", r_p2_t); + pass = 1'b0; + end + + if (r_pi_t !== 1'b1) begin + $display("Failed: constant Inf ? ..., expected 1'b1, got %b", r_pi_t); + pass = 1'b0; + end + + if (r_pn_t !== 1'b1) begin + $display("Failed: constant NaN ? ..., expected 1'b1, got %b", r_pn_t); + pass = 1'b0; + end + + /* Check the ternary with a real cond. variable. */ + if (r_0_t !== 1'b0) begin + $display("Failed: 0.0 ? ..., expected 1'b0, got %b", r_0_t); + pass = 1'b0; + end + + if (r_1_t !== 1'b1) begin + $display("Failed: 1.0 ? ..., expected 1'b1, got %b", r_1_t); + pass = 1'b0; + end + + if (r_2_t !== 1'b1) begin + $display("Failed: 2.0 ? ..., expected 1'b1, got %b", r_2_t); + pass = 1'b0; + end + + if (r_i_t !== 1'b1) begin + $display("Failed: Inf ? ..., expected 1'b1, got %b", r_i_t); + pass = 1'b0; + end + + if (r_n_t !== 1'b1) begin + $display("Failed: NaN ? ..., expected 1'b1, got %b", r_n_t); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/ca_time.v b/ivtest/ivltests/ca_time.v new file mode 100644 index 000000000..b62d12bcd --- /dev/null +++ b/ivtest/ivltests/ca_time.v @@ -0,0 +1,17 @@ +`timescale 1ns/1ns +module top; + reg itrig = 1'b0; + wire [31:0] tm, stm; + + assign tm = itrig * $time; + assign stm = itrig * $stime; + + initial begin + $monitor(tm,, stm); + #1 itrig = 1'b1; + #1 itrig = 1'b0; + #1 itrig = 1'b1; + #1 itrig = 1'b0; + end + +endmodule diff --git a/ivtest/ivltests/ca_time_real.v b/ivtest/ivltests/ca_time_real.v new file mode 100644 index 000000000..6ebdec762 --- /dev/null +++ b/ivtest/ivltests/ca_time_real.v @@ -0,0 +1,16 @@ +`timescale 1ns/1ns +module top; + real rtrig = 0.0; + wire real rtm; + + assign rtm = rtrig * $realtime; + + initial begin + $monitor(rtm); + #1 rtrig = 1.0; + #1 rtrig = 0.0; + #1 rtrig = 1.0; + #1 rtrig = 0.0; + end + +endmodule diff --git a/ivtest/ivltests/ca_time_smtm.v b/ivtest/ivltests/ca_time_smtm.v new file mode 100644 index 000000000..e0ebaf2a5 --- /dev/null +++ b/ivtest/ivltests/ca_time_smtm.v @@ -0,0 +1,16 @@ +`timescale 1ns/1ns +module top; + reg itrig = 1'b0; + wire [31:0] smtm; + + assign smtm = itrig * $simtime; + + initial begin + $monitor(smtm); + #1 itrig = 1'b1; + #1 itrig = 1'b0; + #1 itrig = 1'b1; + #1 itrig = 1'b0; + end + +endmodule diff --git a/ivtest/ivltests/ca_var_delay.v b/ivtest/ivltests/ca_var_delay.v new file mode 100644 index 000000000..6d5d5e220 --- /dev/null +++ b/ivtest/ivltests/ca_var_delay.v @@ -0,0 +1,73 @@ +`timescale 1ns/100ps + +module top; + reg pass = 1'b1; + integer idelay = 2; + real rdelay = 2.0; + real rin = 1.0; + reg ctl = 1'b1; + wire outr, outi, muxr, muxi; + wire real rout; + reg in = 1'b1; + + assign #(idelay) outi = in; + assign #(rdelay) outr = ~in; + assign #(rdelay) rout = rin; + assign #(idelay) muxi = ctl ? in : 1'b0; + assign #(rdelay) muxr = ctl ? ~in : 1'b1; + + initial begin + // Wait for everything to settle including the delay value! + #2.1; + if (outi !== 1'b1 || outr !== 1'b0 || rout != 1.0) begin + $display("FAILED: initial value, expected 1'b1/1'b0/1.0, got %b/%b/%f", + outi, outr, rout); + pass = 1'b0; + end + if (muxi !== 1'b1 || muxr !== 1'b0) begin + $display("FAILED: initial value (mux), expected 1'b1/1'b0, got %b/%b", + muxi, muxr); + pass = 1'b0; + end + + in = 1'b0; + rin = 2.0; + #1.9; + if (outi !== 1'b1 || outr !== 1'b0 || rout != 1.0) begin + $display("FAILED: mid value, expected 1'b1/1'b0/1.0, got %b/%b/%f", + outi, outr, rout); + pass = 1'b0; + end + if (muxi !== 1'b1 || muxr !== 1'b0) begin + $display("FAILED: mid value (mux), expected 1'b1/1'b0, got %b/%b", + muxi, muxr); + pass = 1'b0; + end + #0.2; + if (outi !== 1'b0 || outr !== 1'b1 || rout != 2.0) begin + $display("FAILED: final value, expected 1'b0/1'b1/2.0, got %b/%b/%f", + outi, outr, rout); + pass = 1'b0; + end + if (muxi !== 1'b0 || muxr !== 1'b1) begin + $display("FAILED: final value (mux), expected 1'b0/1'b1, got %b/%b", + muxi, muxr); + pass = 1'b0; + end + + idelay = 3; + in = 1'b1; + #2.9; + if (outi !== 1'b0) begin + $display("FAILED: initial change, expected 1'b0, got %b", outi); + pass = 1'b0; + end + #0.2; + if (outi !== 1'b1) begin + $display("FAILED: initial change, expected 1'b1, got %b", outi); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/case1.v b/ivtest/ivltests/case1.v new file mode 100644 index 000000000..3828d2a93 --- /dev/null +++ b/ivtest/ivltests/case1.v @@ -0,0 +1,32 @@ +module main; + + reg [3:0] cond; + reg [2:0] t; + + always @* + case (cond&4'b1110) + 'h0: t = 7; + 'h2: t = 6; + 'h4: t = 5; + 'h6: t = 4; + 'h8: t = 3; + 'ha: t = 2; + 'hc: t = 1; + 'he: t = 0; + endcase + + integer i; + initial begin + + for (i = 0 ; i < 8 ; i = i + 1) begin + cond = i << 1; + #1 if (t !== (7 - i)) begin + $display("FAILED -- i=%d, cond=%b, t=%b", i, cond, t); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/case2.v b/ivtest/ivltests/case2.v new file mode 100644 index 000000000..8337b3a89 --- /dev/null +++ b/ivtest/ivltests/case2.v @@ -0,0 +1,36 @@ +module main; + + reg [3:0] cond; + reg [2:0] t, q; + + always @* begin + case (cond&4'b1110) + 'h0: t = 7; + 'h2: t = 6; + 'h4: t = 5; + 'h6: t = 4; + 'h8: t = 3; + 'ha: t = 2; + 'hc: t = 1; + 'he: t = 0; + endcase // case(cond&4'b1110) + + q = ~t; + + end // always @ * + + integer i; + initial begin + + for (i = 0 ; i < 8 ; i = i + 1) begin + cond = i << 1; + #1 if (q !== ( 3'b111 & ~(7 - i))) begin + $display("FAILED -- i=%d, cond=%b, q=%b", i, cond, q); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/case3.8A.v b/ivtest/ivltests/case3.8A.v new file mode 100644 index 000000000..7157e02ce --- /dev/null +++ b/ivtest/ivltests/case3.8A.v @@ -0,0 +1,66 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate case/endcase - no default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 or val2) + case (val1 & val2 ) + 3'b000: result = 0; + 3'b001: result = 1 ; + 3'b010: result = 2; + endcase + +initial + begin + error = 0; + + val1 = 3'b0; + val2 = 3'b0; + #1 if(result !==0) + begin + $display("FAILED case 3.8A - case (expr) lab1: "); + error = 1; + end + + val1 = 3'b001; + val2 = 3'b011; + #1 if(result !==1) + begin + $display("FAILED case 3.8A - case (expr) lab2: "); + error = 1; + end + + + val1 = 3'b111; // Should get no-action - expr = 3'b011 + #1 if(result !==1) + begin + $display("FAILED case 3.8A - case (expr) lab1: "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/case3.8B.v b/ivtest/ivltests/case3.8B.v new file mode 100644 index 000000000..6e109d71a --- /dev/null +++ b/ivtest/ivltests/case3.8B.v @@ -0,0 +1,66 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate case/endcase w/ label list - no default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 or val2) + case (val1 & val2 ) + 3'b000,3'b001: result = 0; + 3'b101: result = 1 ; + 3'b110,3'b111,3'b100: result = 2; + endcase + +initial + begin + error = 0; + + val1 = 3'b0; + val2 = 3'b0; + #1 if(result !==0) + begin + $display("FAILED case 3.8B - case (expr) lab1: "); + error = 1; + end + + val1 = 3'b101; + val2 = 3'b111; + #1 if(result !==1) + begin + $display("FAILED case 3.8B - case (expr) lab2: "); + error = 1; + end + + + val1 = 3'b110; + #1 if(result !==2) + begin + $display("FAILED case 3.8B - case (expr) lab1: "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/case3.8C.v b/ivtest/ivltests/case3.8C.v new file mode 100644 index 000000000..ff43f5caa --- /dev/null +++ b/ivtest/ivltests/case3.8C.v @@ -0,0 +1,65 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate case/endcase w/ null_statement - no default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 or val2) + case (val1 & val2 ) + 3'b000,3'b001: result = 0; + 3'b101: ; + 3'b011: result = 1; + endcase + +initial + begin + error = 0; + + val1 = 3'b0; + val2 = 3'b0; + #1 if(result !==0) + begin + $display("FAILED case 3.8C - case (expr) lab1: "); + error = 1; + end + val1 = 3'b111; + val2 = 3'b011; + #1 if(result !==1) + begin + $display("FAILED case 3.8C - case (expr) lab2: "); + error = 1; + end + + + val2 = 3'b101; // Should activate null statement and get no action + #1 if(result !==1) + begin + $display("FAILED case 3.8C - case (expr) lab1: "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/case3.8D.v b/ivtest/ivltests/case3.8D.v new file mode 100644 index 000000000..ef58cadf4 --- /dev/null +++ b/ivtest/ivltests/case3.8D.v @@ -0,0 +1,86 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate case with labels of x and z. Should be match + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 ) + case (val1) + 3'b000: result = 0; + 3'b001: result = 1 ; + 3'b010: result = 2; + 3'bx11: result = 4; + 3'bz11: result = 5; + endcase + +initial + begin + error = 0; + #1; + val1 = 3'b0; + #1; + if(result !== 0) + begin + $display("FAILED case 3.8D - case (expr) lab1: "); + error = 1; + end + #1; + val1 = 3'b001; + #1; + if(result !== 1) + begin + $display("FAILED case 3.8D - case (expr) lab2: "); + error = 1; + end + + #1 ; + val1 = 3'b010; + #1; + if(result !== 2) + begin + $display("FAILED case 3.8D - case (expr) lab3: "); + error = 1; + end + #1 ; + val1 = 3'bz11; + #1; + if(result !== 5) + begin + $display("FAILED case 3.8D - case (expr) lab5: "); + error = 1; + end + + #1 ; + val1 = 3'bx11; + #1; + if(result !== 4) + begin + $display("FAILED case 3.8D - case (expr) lab4: "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/case3.v b/ivtest/ivltests/case3.v new file mode 100644 index 000000000..f1ac8fe60 --- /dev/null +++ b/ivtest/ivltests/case3.v @@ -0,0 +1,46 @@ +module switch (q,a,b,c,d,sel); +input a,b,c,d; +input [1:0] sel; +output q; +reg q; +always @ * + case (sel) + 2'b00: q = a; + 2'b01: q = b; + 2'b10: q = c; + 2'b11: q = d; + endcase + +endmodule + +module test ; +reg [1:0] sel; +reg a,b,c,d; +wire q; + +switch u_switch (q,a,b,c,d,sel); + +initial + begin + a = 0; + b = 0; + c = 0; + d = 0; + sel = 2'b00; + + #1; + if(q !== 1'b0) + begin + $display("FAILED"); + $finish; + end + a = 1; + #1; + if(q !== 1'b1) + begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/case4.v b/ivtest/ivltests/case4.v new file mode 100644 index 000000000..5e07aea19 --- /dev/null +++ b/ivtest/ivltests/case4.v @@ -0,0 +1,45 @@ +/* + * This tests the synthesis of a very sparse case statement. The + * combinational case statement below specifies only two of 256 + * possible selections, with all the remaining left to the default. + * What's more, all the inputs to the MUX are constant, giving + * even further opportunity for optimization. + */ +module main; + + reg [7:0] val; + reg [7:0] out; + + (* ivl_combinational *) + always @ (val) begin + case (val) + 8'h2a: out = 8'h40 ; + 8'h1f: out = 8'h20 ; + default: out = 8'h04 ; + endcase + end + + integer idx; + (* ivl_synthesis_off *) initial begin + for (idx = 0 ; idx < 256 ; idx = idx + 1) begin + val <= idx; + #1 ; + if (val == 8'h2a) begin + if (out !== 8'h40) begin + $display("FAILED -- val=%h, out=%h (%b)", val, out, out); + $finish; + end + end else if (val == 8'h1f) begin + if (out !== 8'h20) begin + $display("FAILED -- val=%h, out=%h (%b)", val, out, out); + $finish; + end + end else if (out !== 8'h04) begin + $display("FAILED -- val=%h, out=%h (%b)", val, out, out); + $finish; + end + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/case5-syn-fail.v b/ivtest/ivltests/case5-syn-fail.v new file mode 100644 index 000000000..5a170a4cb --- /dev/null +++ b/ivtest/ivltests/case5-syn-fail.v @@ -0,0 +1,57 @@ +`begin_keywords "1364-2005" +/* + * This tests the synthesis of a case statement that has an empty case. + */ +module main; + + reg clk, bit, foo; + + // Synchronous device that toggles whenever enabled by a high bit. + always @(posedge clk) + case (bit) + 1'b0: ; + 1'b1: foo <= ~foo; + endcase // case(bit) + + (* ivl_synthesis_off *) + always begin + #5 clk = 1; + #5 clk = 0; + end + + (* ivl_synthesis_off *) + initial begin + clk = 0; + bit = 0; + foo = 0; + # 6 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo); + if (bit !== 0 || foo !== 0) begin + $display("FAILED"); + $finish; + end + + #10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo); + if (bit !== 0 || foo !== 0) begin + $display("FAILED"); + $finish; + end + + bit <= 1; + #10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo); + if (bit !== 1 || foo !== 1) begin + $display("FAILED"); + $finish; + end + + #10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo); + if (bit !== 1 || foo !== 0) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main +`end_keywords diff --git a/ivtest/ivltests/case5.v b/ivtest/ivltests/case5.v new file mode 100644 index 000000000..50735feed --- /dev/null +++ b/ivtest/ivltests/case5.v @@ -0,0 +1,59 @@ +`begin_keywords "1364-2005" +/* + * This tests the synthesis of a case statement that has an empty case. + */ +module main; + + reg clk, bit, foo, clr; + + // Synchronous device that toggles whenever enabled by a high bit. + always @(posedge clk or posedge clr) + if (clr) foo = 0; + else case (bit) + 1'b0: ; + 1'b1: foo <= ~foo; + endcase // case(bit) + + (* ivl_synthesis_off *) + always begin + #5 clk = 1; + #5 clk = 0; + end + + (* ivl_synthesis_off *) + initial begin + clk = 0; + bit = 0; + clr = 1; + # 6 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo); + if (bit !== 0 || foo !== 0) begin + $display("FAILED"); + $finish; + end + clr = 0; + + #10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo); + if (bit !== 0 || foo !== 0) begin + $display("FAILED"); + $finish; + end + + bit <= 1; + #10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo); + if (bit !== 1 || foo !== 1) begin + $display("FAILED"); + $finish; + end + + #10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo); + if (bit !== 1 || foo !== 0) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main +`end_keywords diff --git a/ivtest/ivltests/case6.v b/ivtest/ivltests/case6.v new file mode 100644 index 000000000..c380120ab --- /dev/null +++ b/ivtest/ivltests/case6.v @@ -0,0 +1,41 @@ +`begin_keywords "1364-2005" +/* + * This tests the synthesis of a case statement that has an empty case. + */ +module main; + + reg bit, foo; + + // Combinational device that sends 1 or 0 to foo, to follow bit. + always @* + begin + foo = 0; + case (bit) + 1'b0: ; + 1'b1: foo = 1; + endcase // case(bit) + end + + (* ivl_synthesis_off *) + initial begin + bit = 0; + + # 6 $display("bit=%b, foo=%b", bit, foo); + if (bit !== 0 || foo !== 0) begin + $display("FAILED"); + $finish; + end + + bit <= 1; + #10 $display("bit=%b, foo=%b", bit, foo); + if (bit !== 1 || foo !== 1) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main +`end_keywords diff --git a/ivtest/ivltests/case7.v b/ivtest/ivltests/case7.v new file mode 100644 index 000000000..beb36d128 --- /dev/null +++ b/ivtest/ivltests/case7.v @@ -0,0 +1,45 @@ +`begin_keywords "1364-2005" +/* + * This tests the synthesis of a case statement that has an empty case. + */ +module main; + + reg bit, foo, bar; + + // Combinational device that sends 1 or 0 to foo, to follow bit. + // This tests the special situation that the case condition only sets + // some of the bits that the case as a whole sets. This is OK if + // the bits that are sometimes not set are covered elsewhere. + always @* + begin + foo = 0; + bar = 0; + case (bit) + 1'b0: bar = 1; + 1'b1: foo = 1; + endcase // case(bit) + end + + (* ivl_synthesis_off *) + initial begin + bit = 0; + + # 6 $display("bit=%b, foo=%b, bar=%b", bit, foo, bar); + if (bit !== 0 || foo !== 0 || bar !== 1) begin + $display("FAILED"); + $finish; + end + + bit <= 1; + #10 $display("bit=%b, foo=%b, bar=%b", bit, foo, bar); + if (bit !== 1 || foo !== 1 || bar !== 0) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main +`end_keywords diff --git a/ivtest/ivltests/case_priority.v b/ivtest/ivltests/case_priority.v new file mode 100644 index 000000000..3261e0615 --- /dev/null +++ b/ivtest/ivltests/case_priority.v @@ -0,0 +1,23 @@ +`timescale 10ns/1ps + +module main; + logic [1:0] counter = 2'b00; + logic clk = 1'b0; + + initial forever #1 clk <= ~clk; + + always @(posedge clk) begin + counter <= counter + 2'd1; + + priority case (counter) + 2'd0: $display("case 0"); + 2'd1: $display("case 1"); + 2'd3: $display("case 3"); + endcase // priority case (counter) + + if (counter == 2'd3) begin + $display("PASSED"); + $finish(0); + end + end +endmodule diff --git a/ivtest/ivltests/case_unique.v b/ivtest/ivltests/case_unique.v new file mode 100644 index 000000000..8dd8af863 --- /dev/null +++ b/ivtest/ivltests/case_unique.v @@ -0,0 +1,23 @@ +`timescale 10ns/1ps + +module main; + logic [1:0] counter = 2'b00; + logic clk = 1'b0; + + initial forever #1 clk <= ~clk; + + always @(posedge clk) begin + counter <= counter + 2'd1; + + unique case (counter) + 2'd0: $display("case 0"); + 2'd1: $display("case 1"); + 2'd3: $display("case 3"); + endcase // priority case (counter) + + if (counter == 2'd3) begin + $display("PASSED"); + $finish(0); + end + end +endmodule diff --git a/ivtest/ivltests/case_wo_default.v b/ivtest/ivltests/case_wo_default.v new file mode 100644 index 000000000..aaed97e40 --- /dev/null +++ b/ivtest/ivltests/case_wo_default.v @@ -0,0 +1,52 @@ + +module test + (output reg [1:0] foo, + input wire foo_en1, foo_en2 + /* */); + + always @* begin + foo = 0; + case (1'b1) + foo_en1 : foo = 1; + foo_en2 : foo = 2; + endcase + end +endmodule // test + +module main; + wire [1:0] foo; + reg foo_en1, foo_en2; + + test dut (.foo(foo), .foo_en1(foo_en1), .foo_en2(foo_en2)); + + task fail; + begin + $display("FAILED -- foo=%b, foo_en1=%b, foo_en2=%b", + foo, foo_en1, foo_en2); + $finish; + end + endtask // fail + + initial begin + foo_en1 = 0; + foo_en2 = 0; + + #1 if (foo !== 2'd0) + fail; + + foo_en2 = 1; + #1 if (foo !== 2'd2) + fail; + + foo_en1 = 1; + #1 if (foo !== 2'd1) + fail; + + foo_en2 = 0; + #1 if (foo !== 2'd1) + fail; + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/casesynth1.v b/ivtest/ivltests/casesynth1.v new file mode 100644 index 000000000..c6df7c953 --- /dev/null +++ b/ivtest/ivltests/casesynth1.v @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2006 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + * $Id: casesynth1.v,v 1.1 2006/01/01 01:01:31 stevewilliams Exp $" + */ + + +module main; + + reg clk, rst, set; + reg [3:0] out, load; + reg [1:0] op; + + (* ivl_synthesis_on *) + always @(posedge clk or posedge rst) + if (rst) begin + out <= 0; + + end else if (set) begin + out <= load; + + end else + case (op) + 2'b01: /* increment */ out <= out + 1; + 2'b10: /* decrement */ out <= out - 1; + 2'b11: /* Invert */ out <= ~out; + /* Other ops cause out to not change. */ + endcase // case(mod) + + + (* ivl_synthesis_off *) + initial begin + /* Test rst behavior. */ + op = 2'b00; + rst = 1; + set = 0; + load = 0; + clk = 0; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b0000) begin + $display("FAILED -- out=%b (reset)", out); + $finish; + end + + /* Test set behavior */ + rst = 0; + set = 1; + load = 4'b0100; + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b0100) begin + $display("FAILED -- out=%b (load)", out); + $finish; + end + + /* Test increment behavior */ + op = 2'b01; + rst = 0; + set = 0; + load = 0; + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b0101) begin + $display("FAILED -- out=%b (increment 1)", out); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b0110) begin + $display("FAILED -- out=%b (increment 2)", out); + $finish; + end + + /* Test invert behavior */ + op = 2'b11; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b1001) begin + $display("FAILED == out=%b (invert)", out); + $finish; + end + + /* Test NO-OP behavior */ + op = 2'b00; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b1001) begin + $display("FAILED -- out=%b (noop)", out); + $finish; + end + + /* Test decrement behavior */ + op = 2'b10; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b1000) begin + $display("FAILED -- out=%b (decrement 1)", out); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b0111) begin + $display("FAILED -- out=%b (decrement 2)", out); + $finish; + end + + $display("PASSED"); + $finish; + end +endmodule // main diff --git a/ivtest/ivltests/casesynth2.v b/ivtest/ivltests/casesynth2.v new file mode 100644 index 000000000..980b5e897 --- /dev/null +++ b/ivtest/ivltests/casesynth2.v @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2006 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + * $Id: casesynth2.v,v 1.1 2006/01/01 02:26:18 stevewilliams Exp $" + */ + + +module main; + + reg clk, rst, set; + reg [3:0] out, load; + reg carry; + reg [1:0] op; + + (* ivl_synthesis_on *) + always @(posedge clk or posedge rst) + if (rst) begin + out <= 0; + carry <= 0; + + end else if (set) begin + out <= load; + carry <= 0; + + end else + case (op) + 2'b01: /* increment */ {carry, out} <= {carry, out} + 1; + 2'b10: /* decrement */ {carry, out} <= {carry, out} - 1; + 2'b11: /* Invert */ out <= ~out; + /* Other ops cause out to not change. */ + endcase // case(mod) + + + (* ivl_synthesis_off *) + initial begin + /* Test rst behavior. */ + op = 2'b00; + rst = 1; + set = 0; + load = 0; + clk = 0; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b0000 || carry !== 1'b0) begin + $display("FAILED -- out=%b, carry=%b (reset)", out, carry); + $finish; + end + + /* Test set behavior */ + rst = 0; + set = 1; + load = 4'b1110; + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b1110 || carry !== 1'b0) begin + $display("FAILED -- out=%b, carry=%b (load)", out, carry); + $finish; + end + + /* Test increment behavior */ + op = 2'b01; + rst = 0; + set = 0; + load = 0; + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b1111 || carry !== 1'b0) begin + $display("FAILED -- out=%b, carry=%b (increment 1)", out, carry); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b0000 || carry !== 1'b1) begin + $display("FAILED -- out=%b, carry=%b (increment 2)", out, carry); + $finish; + end + + /* Test invert behavior */ + op = 2'b11; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b1111 || carry !== 1'b1) begin + $display("FAILED == out=%b, carry=%b (invert)", out, carry); + $finish; + end + + /* Test NO-OP behavior */ + op = 2'b00; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b1111 || carry !== 1'b1) begin + $display("FAILED -- out=%b, carry=%b (noop)", out, carry); + $finish; + end + + /* Test decrement behavior */ + op = 2'b10; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b1110) begin + $display("FAILED -- out=%b, carry=%b (decrement 1)", out, carry); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b1101) begin + $display("FAILED -- out=%b, carry=%b (decrement 2)", out, carry); + $finish; + end + + $display("PASSED"); + $finish; + end +endmodule // main diff --git a/ivtest/ivltests/casesynth3.v b/ivtest/ivltests/casesynth3.v new file mode 100644 index 000000000..84b1d719b --- /dev/null +++ b/ivtest/ivltests/casesynth3.v @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2006 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + * $Id: casesynth3.v,v 1.1 2006/01/21 21:53:09 stevewilliams Exp $" + */ + +/* + * This case tests the handling very wide (but sparse) case statements. + */ + +module main; + + reg clk, rst, set; + reg [3:0] out, load; + reg [10:0] op; + + (* ivl_synthesis_on *) + always @(posedge clk or posedge rst) + if (rst) begin + out <= 0; + + end else if (set) begin + out <= load; + + end else + case (op) + 10'b0000000001: /* increment */ out <= out + 1; + 10'b1000000000: /* decrement */ out <= out - 1; + 10'b1000000001: /* Invert */ out <= ~out; + /* Other ops cause out to not change. */ + endcase // case(mod) + + + (* ivl_synthesis_off *) + initial begin + /* Test rst behavior. */ + op = 10'b0000000000; + rst = 1; + set = 0; + load = 0; + clk = 0; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b0000) begin + $display("FAILED -- out=%b (reset)", out); + $finish; + end + + /* Test set behavior */ + rst = 0; + set = 1; + load = 4'b0100; + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b0100) begin + $display("FAILED -- out=%b (load)", out); + $finish; + end + + /* Test increment behavior */ + op = 10'b0000000001; + rst = 0; + set = 0; + load = 0; + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b0101) begin + $display("FAILED -- out=%b (increment 1)", out); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b0110) begin + $display("FAILED -- out=%b (increment 2)", out); + $finish; + end + + /* Test invert behavior */ + op = 10'b1000000001; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b1001) begin + $display("FAILED == out=%b (invert)", out); + $finish; + end + + /* Test NO-OP behavior */ + op = 10'b0000000000; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b1001) begin + $display("FAILED -- out=%b (noop)", out); + $finish; + end + + /* Test decrement behavior */ + op = 10'b1000000000; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b1000) begin + $display("FAILED -- out=%b (decrement 1)", out); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (out !== 4'b0111) begin + $display("FAILED -- out=%b (decrement 2)", out); + $finish; + end + + $display("PASSED"); + $finish; + end +endmodule // main diff --git a/ivtest/ivltests/casesynth4.v b/ivtest/ivltests/casesynth4.v new file mode 100644 index 000000000..25b7f4452 --- /dev/null +++ b/ivtest/ivltests/casesynth4.v @@ -0,0 +1,63 @@ + +module test + (output reg a, + output reg b, + input wire [1:0] sel, + input wire d + /* */); + + always @* begin + b = d; + case (sel) + 0: + begin + a = 0; + b = 1; + end + 1: + begin + a = 1; + b = 0; + end + default: + begin + a = d; + end + endcase // case (sel) + end // always @ * + +endmodule // test + +module main; + reg [1:0] sel; + reg d; + wire a, b; + + test dut (.a(a), .b(b), .sel(sel), .d(d)); + + initial begin + d = 0; + sel = 0; + #1 if (a!==0 || b!==1) begin + $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b); + $finish; + end + sel = 1; + #1 if (a!==1 || b!==0) begin + $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b); + $finish; + end + sel = 2; + #1 if (a!==0 || b!==0) begin + $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b); + $finish; + end + d = 1; + #1 if (a!==1 || b!==1) begin + $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/casesynth5.v b/ivtest/ivltests/casesynth5.v new file mode 100644 index 000000000..c1944d690 --- /dev/null +++ b/ivtest/ivltests/casesynth5.v @@ -0,0 +1,63 @@ + +module test + (output reg a, + output reg b, + input wire [1:0] sel, + input wire d + /* */); + + always @* begin + b = d; + case (sel) + 0: + begin + a = 0; + b = 1; + end + 1: + begin + a = 1; + //b = 0; // Pick up input from d instead. + end + default: + begin + a = d; + end + endcase // case (sel) + end // always @ * + +endmodule // test + +module main; + reg [1:0] sel; + reg d; + wire a, b; + + test dut (.a(a), .b(b), .sel(sel), .d(d)); + + initial begin + d = 0; + sel = 0; + #1 if (a!==0 || b!==1) begin + $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b); + $finish; + end + sel = 1; + #1 if (a!==1 || b!==0) begin + $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b); + $finish; + end + sel = 2; + #1 if (a!==0 || b!==0) begin + $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b); + $finish; + end + d = 1; + #1 if (a!==1 || b!==1) begin + $display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/casesynth6.v b/ivtest/ivltests/casesynth6.v new file mode 100644 index 000000000..d19489362 --- /dev/null +++ b/ivtest/ivltests/casesynth6.v @@ -0,0 +1,80 @@ + +module test + (output reg [4:0] q, + input wire [31:0] sel + /* */); + + always @* begin + casez (sel) + 32'b1zzz_zzzz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd0; + 32'b01zz_zzzz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd1; + 32'b001z_zzzz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd2; + 32'b0001_zzzz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd3; + 32'b0000_1zzz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd4; + 32'b0000_01zz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd5; + 32'b0000_001z_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd6; + 32'b0000_0001_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd7; + + 32'b0000_0000_1zzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd8; + 32'b0000_0000_01zz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd9; + 32'b0000_0000_001z_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd10; + 32'b0000_0000_0001_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd11; + 32'b0000_0000_0000_1zzz__zzzz_zzzz_zzzz_zzzz: q = 5'd12; + 32'b0000_0000_0000_01zz__zzzz_zzzz_zzzz_zzzz: q = 5'd13; + 32'b0000_0000_0000_001z__zzzz_zzzz_zzzz_zzzz: q = 5'd14; + 32'b0000_0000_0000_0001__zzzz_zzzz_zzzz_zzzz: q = 5'd15; + + 32'b0000_0000_0000_0000__1zzz_zzzz_zzzz_zzzz: q = 5'd16; + 32'b0000_0000_0000_0000__01zz_zzzz_zzzz_zzzz: q = 5'd17; + 32'b0000_0000_0000_0000__001z_zzzz_zzzz_zzzz: q = 5'd18; + 32'b0000_0000_0000_0000__0001_zzzz_zzzz_zzzz: q = 5'd19; + 32'b0000_0000_0000_0000__0000_1zzz_zzzz_zzzz: q = 5'd20; + 32'b0000_0000_0000_0000__0000_01zz_zzzz_zzzz: q = 5'd21; + 32'b0000_0000_0000_0000__0000_001z_zzzz_zzzz: q = 5'd22; + 32'b0000_0000_0000_0000__0000_0001_zzzz_zzzz: q = 5'd23; + + 32'b0000_0000_0000_0000__0000_0000_1zzz_zzzz: q = 5'd24; + 32'b0000_0000_0000_0000__0000_0000_01zz_zzzz: q = 5'd25; + 32'b0000_0000_0000_0000__0000_0000_001z_zzzz: q = 5'd26; + 32'b0000_0000_0000_0000__0000_0000_0001_zzzz: q = 5'd27; + 32'b0000_0000_0000_0000__0000_0000_0000_1zzz: q = 5'd28; + 32'b0000_0000_0000_0000__0000_0000_0000_01zz: q = 5'd29; + 32'b0000_0000_0000_0000__0000_0000_0000_001z: q = 5'd30; + 32'b0000_0000_0000_0000__0000_0000_0000_0001: q = 5'd31; + default: q = 5'd0; + endcase + end // always @ * + +endmodule // test + +module main; + reg [31:0] sel; + wire [4:0] q; + + test dut (.q(q), .sel(sel)); + + integer idx; + integer rept; + reg [31:0] mask, setb; + initial begin + sel = 0; + #1 if (q !== 5'd0) begin + $display("FAILED -- sel=%b, q=%b", sel, q); + $finish; + end + + for (idx = 0 ; idx < 32 ; idx = idx+1) begin + mask = 32'h7fff_ffff >> idx; + setb = mask + 32'd1; + for (rept = 0 ; rept < 4 ; rept = rept+1) begin + sel = setb | (mask & $random); + #1 if (q !== idx[4:0]) begin + $display("FAILED -- sel=%b, q=%b, idx=%0d", sel, q, idx); + $finish; + end + end + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/casesynth7.v b/ivtest/ivltests/casesynth7.v new file mode 100644 index 000000000..fe2f4e427 --- /dev/null +++ b/ivtest/ivltests/casesynth7.v @@ -0,0 +1,30 @@ +// Incomplete case statements in asynchronous logic are dangerous in +// synthesisable code, as in real hardware the inferred latch will be +// sensitive to glitches as the case select value changes. Check that +// the compiler outputs a warning for this. +module mux( + +input wire [2:0] sel, +input wire [2:0] i1, +input wire [2:0] i2, +input wire [2:0] i3, +input wire [2:0] i4, +output reg [2:0] o + +); + +(* ivl_synthesis_on *) +always @* begin + case (sel) + 0 : o = 0; + 1 : o = i1; + 2 : o = i2; + 3 : o = i3; + 4 : o = i4; + endcase +end +(* ivl_synthesis_off *) + +initial $display("PASSED"); + +endmodule diff --git a/ivtest/ivltests/casesynth8.v b/ivtest/ivltests/casesynth8.v new file mode 100644 index 000000000..4a9775e8e --- /dev/null +++ b/ivtest/ivltests/casesynth8.v @@ -0,0 +1,32 @@ +// We don't (currently) support a case statement where both the case select +// and one or more case items are variables in asynchronous logic synthesis. +// Check the compiler handles and rejects this code. +module mux( + +input wire [2:0] sel, +input wire [2:0] i1, +input wire [2:0] i2, +input wire [2:0] i3, +input wire [2:0] i4, +input wire [2:0] i5, +output reg [2:0] o + +); + +(* ivl_synthesis_on *) +always @* begin + case (sel) + 0 : o = 0; + 1 : o = i1; + 2 : o = i2; + 3 : o = i3; + i5 : o = i4; + default: + o = 3'bx; + endcase +end +(* ivl_synthesis_off *) + +initial $display("PASSED"); + +endmodule diff --git a/ivtest/ivltests/casesynth9.v b/ivtest/ivltests/casesynth9.v new file mode 100644 index 000000000..bfdff229b --- /dev/null +++ b/ivtest/ivltests/casesynth9.v @@ -0,0 +1,49 @@ +module mux( + +input wire [1:0] sel, +input wire [2:0] i0, +input wire [2:0] i1, +input wire [2:0] i2, +input wire [2:0] i3, +input wire [2:0] i4, +output reg [2:0] o + +); + +always @* begin + case (sel) + 0 : o = i0; + 1 : o = i1; + 2 : o = i2; + 3 : o = i3; + 2 : o = i4; + endcase +end + +endmodule + +module test(); + +reg [1:0] sel; +wire [2:0] out; + +mux mux(sel, 3'd0, 3'd1, 3'd2, 3'd3, 3'd4, out); + +reg failed; + +(* ivl_synthesis_off *) +initial begin + failed = 0; + sel = 0; + repeat (4) begin + #1 $display("%d : %b", sel, out); + if (out !== sel) failed = 1; + sel = sel + 1; + end + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/casex3.9A.v b/ivtest/ivltests/casex3.9A.v new file mode 100644 index 000000000..7ea2f9d91 --- /dev/null +++ b/ivtest/ivltests/casex3.9A.v @@ -0,0 +1,66 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casex/endcase w/ known labels - no default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 or val2) + casex (val1 & val2 ) + 3'b000: result = 0; + 3'b001: result = 1 ; + 3'b010: result = 2; + endcase + +initial + begin + error = 0; + + val1 = 3'b0; + val2 = 3'b0; + if(result !=0) + begin + $display("FAILED case 3.9A - case (expr) lab1: "); + error = 1; + end + + val1 = 3'b001; + val2 = 3'b011; + if(result !=1) + begin + $display("FAILED case 3.9A - case (expr) lab2: "); + error = 1; + end + + + val1 = 3'b111; // Should get no-action - expr = 3'b011 + if(result !=1) + begin + $display("FAILED case 3.9A - case (expr) lab1: "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/casex3.9B.v b/ivtest/ivltests/casex3.9B.v new file mode 100644 index 000000000..dd25bff6a --- /dev/null +++ b/ivtest/ivltests/casex3.9B.v @@ -0,0 +1,66 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casex/endcase X in case(expr) - no default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 or val2) + casex (val1 & val2 ) + 3'b000: result = 0; + 3'b001: result = 1 ; + 3'b010: result = 2; + endcase + +initial + begin + error = 0; + + val1 = 3'b0; + val2 = 3'b0x0; + if(result !=0) + begin + $display("FAILED case 3.9B - casex (expr contains x) lab1: "); + error = 1; + end + + val1 = 3'b001; + val2 = 3'b0x1; + if(result !=1) + begin + $display("FAILED case 3.9B - casex (expr contains x) lab2: "); + error = 1; + end + + + val1 = 3'b111; // Should get no-action - expr = 3'b011 + if(result !=1) + begin + $display("FAILED case 3.9B - casex (expr contains x) lab1: "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/casex3.9C.v b/ivtest/ivltests/casex3.9C.v new file mode 100644 index 000000000..21e25b8ba --- /dev/null +++ b/ivtest/ivltests/casex3.9C.v @@ -0,0 +1,66 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casex/endcase - label w/ X no default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 or val2) + casex (val1 & val2 ) + 3'b000: result = 0; + 3'b0x1: result = 1 ; + 3'b010: result = 2; + endcase + +initial + begin + error = 0; + + val1 = 3'b0; + val2 = 3'b0; + if(result !=0) + begin + $display("FAILED casex 3.9C - label w/ x: "); + error = 1; + end + + val1 = 3'b001; + val2 = 3'b011; + if(result !=1) + begin + $display("FAILED casex 3.9C - label w/ x: "); + error = 1; + end + + + val1 = 3'b111; // Should get no-action - expr = 3'b011 + if(result !=1) + begin + $display("FAILED casex 3.9C - label w/ x "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/casex3.9D.v b/ivtest/ivltests/casex3.9D.v new file mode 100644 index 000000000..68f6786fd --- /dev/null +++ b/ivtest/ivltests/casex3.9D.v @@ -0,0 +1,67 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casex/endcase w/ null_statement - no default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 or val2) + casex (val1 & val2 ) + 3'b000,3'b001: result = 0; + 3'b10x: ; + 3'b001: result = 1; + endcase + +initial + begin + error = 0; + + val1 = 3'b0; + val2 = 3'b0; + if(result !=0) + begin + $display("FAILED casex 3.9D - lab w/ null expr: "); + error = 1; + end + + val1 = 3'b001; + val2 = 3'b011; + if(result !=1) + begin + $display("FAILED casex 3.9D - lab w/ null expr: "); + error = 1; + end + + + val1 = 3'b111; // Should get no-action - expr = 3'b010 + val2 = 3'b010; + if(result !=1) + begin + $display("FAILED casex 3.9D - lab w/ null expr: "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/casex3.9E.v b/ivtest/ivltests/casex3.9E.v new file mode 100644 index 000000000..2dc094128 --- /dev/null +++ b/ivtest/ivltests/casex3.9E.v @@ -0,0 +1,68 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casex/endcase w/ null_statement as default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 or val2) + casex (val1 & val2 ) + 3'b000,3'b001: result = 0; + 3'b11x: result = 2; + 3'b001: result = 1; + default result = 3; + endcase + +initial + begin + error = 0; + + val1 = 3'b0; + val2 = 3'b0; + if(result !=0) + begin + $display("FAILED casex 3.9E - default: "); + error = 1; + end + + val1 = 3'b001; + val2 = 3'b011; + if(result !=1) + begin + $display("FAILED casex 3.9E - default: "); + error = 1; + end + + + val1 = 3'b111; // Should get no-action - expr = 3'b010 + val2 = 3'b010; + if(result !=3) + begin + $display("FAILED casex 3.9E - default: "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/casex_synth.v b/ivtest/ivltests/casex_synth.v new file mode 100644 index 000000000..023495147 --- /dev/null +++ b/ivtest/ivltests/casex_synth.v @@ -0,0 +1,46 @@ +/* + */ +module main; + + reg [1:0] sel, in; + reg [1:0] out; + + (* ivl_combinational *) + always @* + casex (sel) + 2'b0?: out = 2'b10; + 2'b10: out = in[0]; + 2'b11: out = in[1]; + endcase // casex(sel) + + (* ivl_synthesis_off *) + initial begin + in = 2'b10; + + sel = 0; + #1 if (out !== 2'b10) begin + $display("FAILED -- sel=%b, out=%b", sel, out); + $finish; + end + + sel = 1; + #1 if (out !== 2'b10) begin + $display("FAILED -- sel=%b, out=%b", sel, out); + $finish; + end + + sel = 2; + #1 if (out !== 2'b00) begin + $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out); + $finish; + end + + sel = 3; + #1 if (out !== 2'b01) begin + $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/casez3.10A.v b/ivtest/ivltests/casez3.10A.v new file mode 100644 index 000000000..a6e4e8a2c --- /dev/null +++ b/ivtest/ivltests/casez3.10A.v @@ -0,0 +1,66 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casez/endcase w/ known labels - no default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 or val2) + casez (val1 & val2 ) + 3'b000: result = 0; + 3'b001: result = 1 ; + 3'b010: result = 2; + endcase + +initial + begin + error = 0; + + val1 = 3'b0; + val2 = 3'b0; + if(result !=0) + begin + $display("FAILED casez 3.10A - case (expr) lab1: "); + error = 1; + end + + val1 = 3'b001; + val2 = 3'b011; + if(result !=1) + begin + $display("FAILED casez 3.10A - case (expr) lab2: "); + error = 1; + end + + + val1 = 3'b111; // Should get no-action - expr = 3'b011 + if(result !=1) + begin + $display("FAILED casez 3.10A - case (expr) lab1: "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/casez3.10B.v b/ivtest/ivltests/casez3.10B.v new file mode 100644 index 000000000..94bc9483a --- /dev/null +++ b/ivtest/ivltests/casez3.10B.v @@ -0,0 +1,63 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casez/endcase w/ z in expr no default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 ) + casez (val1) + 3'b000: result = 0; + 3'b010: result = 1 ; + 3'b110: result = 2; + endcase + +initial + begin + error = 0; + + val1 = 3'b0z0 ; + if(result !=0) + begin + $display("FAILED casez 3.10B - case (expr) lab1: "); + error = 1; + end + + val1 = 3'b01z; + if(result !=1) + begin + $display("FAILED casez 3.10B - case (expr) lab2: "); + error = 1; + end + + val1 = 3'b111; // Should get no-action - expr = 3'b011 + if(result !=1) + begin + $display("FAILED casez 3.10B - case (expr) lab1: "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/casez3.10C.v b/ivtest/ivltests/casez3.10C.v new file mode 100644 index 000000000..31da4be84 --- /dev/null +++ b/ivtest/ivltests/casez3.10C.v @@ -0,0 +1,63 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casez/endcase w/ z in label - no match case + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 ) + casez (val1) + 5'b0000z: result = 0; + 5'b001z0: result = 1 ; + 5'b01zz0: result = 2; + endcase + +initial + begin + error = 0; + + val1 = 5'b0000z ; + if(result !=0) + begin + $display("FAILED casez 3.10C - case (expr) lab1: "); + error = 1; + end + + val1 = 5'b001z0; + if(result !=1) + begin + $display("FAILED casez 3.10C - case (expr) lab2: "); + error = 1; + end + + val1 = 5'b1zzzz; // Should get no-action - expr = 3'b011 + if(result !=1) + begin + $display("FAILED casez 3.10C - case (expr) lab1: "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/casez3.10D.v b/ivtest/ivltests/casez3.10D.v new file mode 100644 index 000000000..eaf51e986 --- /dev/null +++ b/ivtest/ivltests/casez3.10D.v @@ -0,0 +1,64 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casez/endcase w/ default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 ) + casez (val1) + 5'b0000z: result = 0; + 5'b001z0: result = 1 ; + 5'b01zz0: result = 2; + default: result = 4; + endcase + +initial + begin + error = 0; + + val1 = 5'b0000z ; + if(result !=0) + begin + $display("FAILED casez 3.10D - case (expr) lab1: "); + error = 1; + end + + val1 = 5'b001z0; + if(result !=1) + begin + $display("FAILED casez 3.10D - case (expr) lab2: "); + error = 1; + end + + val1 = 5'b1zzzz; // Should get no-action - expr = 3'b011 + if(result !=4) + begin + $display("FAILED casez 3.10D - case (expr) lab1: "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/casez3.10E.v b/ivtest/ivltests/casez3.10E.v new file mode 100644 index 000000000..c411672c1 --- /dev/null +++ b/ivtest/ivltests/casez3.10E.v @@ -0,0 +1,64 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate casez/endcase w/ default + +module main (); + +reg error; +reg [2:0] val1,val2; +reg [2:0] result ; + +always @( val1 ) + casez (val1) + 5'b0000z: result = 0; + 5'b001?0: result = 1 ; + 5'b01?z0: result = 2; + default: result = 4; + endcase + +initial + begin + error = 0; + + val1 = 5'b0000z ; + if(result !=0) + begin + $display("FAILED casez 3.10D - case (expr) lab1: "); + error = 1; + end + + val1 = 5'b001z0; + if(result !=1) + begin + $display("FAILED casez 3.10D - case (expr) lab2: "); + error = 1; + end + + val1 = 5'b1zzzz; // Should get no-action - expr = 3'b011 + if(result !=4) + begin + $display("FAILED casez 3.10D - case (expr) lab1: "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/cast_int.v b/ivtest/ivltests/cast_int.v new file mode 100644 index 000000000..8159f4ba8 --- /dev/null +++ b/ivtest/ivltests/cast_int.v @@ -0,0 +1,99 @@ +module top; + reg pass = 1'b1; + real in, bin; + wire [7:0] out = in; + wire signed [34:0] big = bin; + + initial begin +// $monitor(in,, out,, bin,, big); + bin = 8589934592.5; // 2**33+0.5 overflows a 32 bit long. + #1; + if (big !== 35'sd8589934593) begin + $display("Failed: multiword check, expected 8589934593, got %d", big); + pass = 1'b0; + end + + if (out !== 'b0) begin + $display("Failed: initial value, expected 8'b0, got %b", out); + pass = 1'b0; + end + + in = 0.499999; + bin = -25.5; // This test a different branch (small result -> big vec.). + #1; + if (big !== -26) begin + $display("Failed: small value multiword check, expected -26, got %d", out); + pass = 1'b0; + end + + if (out !== 8'b0) begin + $display("Failed: rounding value (down, +), expected 8'b0, got %b", out); + pass = 1'b0; + end + + in = -0.499999; + #1; + if (out !== 8'b0) begin + $display("Failed: rounding value (down, -), expected 8'b0, got %b", out); + pass = 1'b0; + end + + in = 0.5; + #1; + if (out !== 8'b01) begin + $display("Failed: rounding value (up, +), expected 8'b01, got %b", out); + pass = 1'b0; + end + + in = -0.5; + #1; + if (out !== 8'b11111111) begin + $display("Failed: rounding value (up, -), expected 8'b11111111, got %b", out); + pass = 1'b0; + end + + in = 256.0; + #1; + if (out !== 8'b0) begin + $display("Failed: overflow expected 8'b0, got %b", out); + pass = 1'b0; + end + + in = 511.0; + #1; + if (out !== 8'b11111111) begin + $display("Failed: pruning expected 8'b11111111, got %b", out); + pass = 1'b0; + end + + in = 1.0/0.0; + #1; + if (out !== 8'bxxxxxxxx) begin + $display("Failed: +inf expected 8'bxxxxxxxx, got %b", out); + pass = 1'b0; + end + + in = -1.0/0.0; + #1; + if (out !== 8'bxxxxxxxx) begin + $display("Failed: -inf expected 8'bxxxxxxxx, got %b", out); + pass = 1'b0; + end + + in = $sqrt(-1.0); + #1; + if (out !== 8'bxxxxxxxx) begin + $display("Failed: nan expected 8'bxxxxxxxx, got %b", out); + pass = 1'b0; + end + + in = 8589934720.5; + #1; + if (out !== 129) begin + $display("Failed: overflow value expected 129, got %d", out); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/cast_int_ams.v b/ivtest/ivltests/cast_int_ams.v new file mode 100644 index 000000000..4df23bee3 --- /dev/null +++ b/ivtest/ivltests/cast_int_ams.v @@ -0,0 +1,17 @@ +module top; + reg pass = 1'b1; + real in; + wire [7:0] out = in; + + initial begin +// $monitor(in,, out); + in = sqrt(-1.0); + #1; + if (out !== 8'bxxxxxxxx) begin + $display("Failed: nan expected 8'bxxxxxxxx, got %b", out); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/cast_real.v b/ivtest/ivltests/cast_real.v new file mode 100644 index 000000000..ca4a72be4 --- /dev/null +++ b/ivtest/ivltests/cast_real.v @@ -0,0 +1,76 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test casting integers to real + +module cast_real(); + int i; + logic [3:0] l; + logic signed [3:0] sl; + real a, b, c, d, e; + +initial begin + // Initalization using an integer variable + i = 5; + a = real'(i); + + // ..and logic + l = 4'b1010; + b = real'(l); + + sl = 4'b1010; + c = real'(sl); + + // Initialization using an integer constant + d = real'(11); + e = real'(-7); + + if (a != 5.0) + begin + $display("FAILED #1 a = %f", a); + $finish(); + end + + if (b != 10.0) + begin + $display("FAILED #2 b = %f", b); + $finish(); + end + + if (c != -6.0) + begin + $display("FAILED #3 c = %f", c); + $finish(); + end + + if (d != 11.0) + begin + $display("FAILED #4 d = %f", d); + $finish(); + end + + if (e != -7.0) + begin + $display("FAILED #5 e = %f", e); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/cast_real_signed.v b/ivtest/ivltests/cast_real_signed.v new file mode 100644 index 000000000..d7acc096b --- /dev/null +++ b/ivtest/ivltests/cast_real_signed.v @@ -0,0 +1,37 @@ +module top; + reg pass = 1'b1; + reg signed [7:0] in; + wire real out = in; + + initial begin +// $monitor(in,, out); + #1; + if (out != 0.0) begin + $display("Failed: initial value, expected 0.0, got %g", out); + pass = 1'b0; + end + + in = 0; + #1; + if (out != 0.0) begin + $display("Failed: 0 value, expected 0.0, got %g", out); + pass = 1'b0; + end + + in = 1; + #1; + if (out != 1.0) begin + $display("Failed: 1 value, expected 1.0, got %g", out); + pass = 1'b0; + end + + in = -1; + #1; + if (out != -1.0) begin + $display("Failed: -1 value, expected -1.0, got %g", out); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/cast_real_unsigned.v b/ivtest/ivltests/cast_real_unsigned.v new file mode 100644 index 000000000..ad1bc4697 --- /dev/null +++ b/ivtest/ivltests/cast_real_unsigned.v @@ -0,0 +1,37 @@ +module top; + reg pass = 1'b1; + reg [7:0] in; + wire real out = in; + + initial begin +// $monitor(in,, out); + #1; + if (out != 0.0) begin + $display("Failed: initial value, expected 0.0, got %g", out); + pass = 1'b0; + end + + in = 0; + #1; + if (out != 0.0) begin + $display("Failed: 0 value, expected 0.0, got %g", out); + pass = 1'b0; + end + + in = 1; + #1; + if (out != 1.0) begin + $display("Failed: 1 value, expected 1.0, got %g", out); + pass = 1'b0; + end + + in = -1; + #1; + if (out != 255.0) begin + $display("Failed: -1 value, expected -255.0, got %g", out); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/cfunc_assign_op_mixed.v b/ivtest/ivltests/cfunc_assign_op_mixed.v new file mode 100644 index 000000000..3f4ebb98c --- /dev/null +++ b/ivtest/ivltests/cfunc_assign_op_mixed.v @@ -0,0 +1,146 @@ +`ifdef __ICARUS__ + `define SUPPORT_REAL_MODULUS_IN_IVTEST +`endif + +module test(); + +function integer add2(input integer x); +begin + x += 2.0; + add2 = x; +end +endfunction + +function integer sub2(input integer x); +begin + x -= 2.0; + sub2 = x; +end +endfunction + +function integer mul2(input integer x); +begin + x *= 2.0; + mul2 = x; +end +endfunction + +function integer div2(input integer x); +begin + x /= 2.0; + div2 = x; +end +endfunction + +function integer mod2(input integer x); +begin +`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST + x %= 2.0; +`else + x %= 2; +`endif + mod2 = x; +end +endfunction + +localparam add2_5 = add2(5); +localparam sub2_5 = sub2(5); +localparam mul2_5 = mul2(5); +localparam div2_5 = div2(5); +localparam mod2_5 = mod2(5); + +function integer add3(input integer x); +begin + add3 = x; + add3 += 3.0; +end +endfunction + +function integer sub3(input integer x); +begin + sub3 = x; + sub3 -= 3.0; +end +endfunction + +function integer mul3(input integer x); +begin + mul3 = x; + mul3 *= 3.0; +end +endfunction + +function integer div3(input integer x); +begin + div3 = x; + div3 /= 3.0; +end +endfunction + +function integer mod3(input integer x); +begin + mod3 = x; +`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST + mod3 %= 3.0; +`else + mod3 %= 3; +`endif +end +endfunction + +localparam add3_5 = add3(5); +localparam sub3_5 = sub3(5); +localparam mul3_5 = mul3(5); +localparam div3_5 = div3(5); +localparam mod3_5 = mod3(5); + +reg failed = 0; + +initial begin + $display("add2_5 = %0f", add2_5); + if (add2_5 != add2(5)) failed = 1; + if (add2_5 != 7) failed = 1; + + $display("sub2_5 = %0f", sub2_5); + if (sub2_5 != sub2(5)) failed = 1; + if (sub2_5 != 3) failed = 1; + + $display("mul2_5 = %0f", mul2_5); + if (mul2_5 != mul2(5)) failed = 1; + if (mul2_5 != 10) failed = 1; + + $display("div2_5 = %0f", div2_5); + if (div2_5 != div2(5)) failed = 1; + if (div2_5 != 2) failed = 1; + + $display("mod2_5 = %0f", mod2_5); + if (mod2_5 != mod2(5)) failed = 1; + if (mod2_5 != 1) failed = 1; + + $display("add3_5 = %0f", add3_5); + if (add3_5 != add3(5)) failed = 1; + if (add3_5 != 8) failed = 1; + + $display("sub3_5 = %0f", sub3_5); + if (sub3_5 != sub3(5)) failed = 1; + if (sub3_5 != 2) failed = 1; + + $display("mul3_5 = %0f", mul3_5); + if (mul3_5 != mul3(5)) failed = 1; + if (mul3_5 != 15) failed = 1; + + $display("div3_5 = %0f", div3_5); + if (div3_5 != div3(5)) failed = 1; + if (div3_5 != 1) failed = 1; + + $display("mod3_5 = %0f", mod3_5); + if (mod3_5 != mod3(5)) failed = 1; + if (mod3_5 != 2) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/cfunc_assign_op_pv.v b/ivtest/ivltests/cfunc_assign_op_pv.v new file mode 100644 index 000000000..2b6c78d86 --- /dev/null +++ b/ivtest/ivltests/cfunc_assign_op_pv.v @@ -0,0 +1,356 @@ +module test(); + +function [31:0] pre_inc(input [31:0] x); +begin + ++x[23:8]; + pre_inc = x; +end +endfunction + +function [31:0] pre_dec(input [31:0] x); +begin + --x[23:8]; + pre_dec = x; +end +endfunction + +function [31:0] post_inc(input [31:0] x); +begin + x[23:8]++; + post_inc = x; +end +endfunction + +function [31:0] post_dec(input [31:0] x); +begin + x[23:8]--; + post_dec = x; +end +endfunction + +localparam pre_inc_5 = pre_inc({8'h55, 16'd5, 8'haa}); +localparam pre_dec_5 = pre_dec({8'h55, 16'd5, 8'haa}); + +localparam post_inc_5 = post_inc({8'h55, 16'd5, 8'haa}); +localparam post_dec_5 = post_dec({8'h55, 16'd5, 8'haa}); + +function [31:0] add2(input [31:0] x); +begin + x[23:8] += 2; + add2 = x; +end +endfunction + +function [31:0] sub2(input [31:0] x); +begin + x[23:8] -= 2; + sub2 = x; +end +endfunction + +function [31:0] mul2(input [31:0] x); +begin + x[23:8] *= 2; + mul2 = x; +end +endfunction + +function [31:0] div2(input [31:0] x); +begin + x[23:8] /= 2; + div2 = x; +end +endfunction + +function [31:0] mod2(input [31:0] x); +begin + x[23:8] %= 2; + mod2 = x; +end +endfunction + +function [31:0] and6(input [31:0] x); +begin + x[23:8] &= 16'h6666; + and6 = x; +end +endfunction + +function [31:0] or6(input [31:0] x); +begin + x[23:8] |= 16'h6666; + or6 = x; +end +endfunction + +function [31:0] xor6(input [31:0] x); +begin + x[23:8] ^= 16'h6666; + xor6 = x; +end +endfunction + +function [31:0] lsl2(input [31:0] x); +begin + x[23:8] <<= 2; + lsl2 = x; +end +endfunction + +function [31:0] lsr2(input [31:0] x); +begin + x[23:8] >>= 2; + lsr2 = x; +end +endfunction + +function [31:0] asl2(input [31:0] x); +begin + x[23:8] <<<= 2; + asl2 = x; +end +endfunction + +function [31:0] asr2(input [31:0] x); +begin + x[23:8] >>>= 2; + asr2 = x; +end +endfunction + +localparam add2_5 = add2({8'h55, 16'd5, 8'haa}); +localparam sub2_5 = sub2({8'h55, 16'd5, 8'haa}); +localparam mul2_5 = mul2({8'h55, 16'd5, 8'haa}); +localparam div2_5 = div2({8'h55, 16'd5, 8'haa}); +localparam mod2_5 = mod2({8'h55, 16'd5, 8'haa}); + +localparam and6_f = and6(32'h55ffffaa); +localparam or6_0 = or6(32'h550000aa); +localparam xor6_f = xor6(32'h55ffffaa); + +localparam lsl2_p25 = lsl2({8'h55, 16'sd25, 8'haa}); +localparam lsr2_m25 = lsr2({8'h55, -16'sd25, 8'haa}); +localparam asl2_m25 = asl2({8'h55, -16'sd25, 8'haa}); +localparam asr2_m25 = asr2({8'h55, -16'sd25, 8'haa}); + +function [31:0] add3(input [31:0] x); +begin + add3 = x; + add3[23:8] += 3; +end +endfunction + +function [31:0] sub3(input [31:0] x); +begin + sub3 = x; + sub3[23:8] -= 3; +end +endfunction + +function [31:0] mul3(input [31:0] x); +begin + mul3 = x; + mul3[23:8] *= 3; +end +endfunction + +function [31:0] div3(input [31:0] x); +begin + div3 = x; + div3[23:8] /= 3; +end +endfunction + +function [31:0] mod3(input [31:0] x); +begin + mod3 = x; + mod3[23:8] %= 3; +end +endfunction + +function [31:0] and9(input [31:0] x); +begin + and9 = x; + and9[23:8] &= 16'h9999; +end +endfunction + +function [31:0] or9(input [31:0] x); +begin + or9 = x; + or9[23:8] |= 16'h9999; +end +endfunction + +function [31:0] xor9(input [31:0] x); +begin + xor9 = x; + xor9[23:8] ^= 16'h9999; +end +endfunction + +function [31:0] lsl3(input [31:0] x); +begin + lsl3 = x; + lsl3[23:8] <<= 3; +end +endfunction + +function [31:0] lsr3(input [31:0] x); +begin + lsr3 = x; + lsr3[23:8] >>= 3; +end +endfunction + +function [31:0] asl3(input [31:0] x); +begin + asl3 = x; + asl3[23:8] <<<= 3; +end +endfunction + +function [31:0] asr3(input [31:0] x); +begin + asr3 = x; + asr3[23:8] >>>= 3; +end +endfunction + +localparam add3_5 = add3({8'h55, 16'd5, 8'haa}); +localparam sub3_5 = sub3({8'h55, 16'd5, 8'haa}); +localparam mul3_5 = mul3({8'h55, 16'd5, 8'haa}); +localparam div3_5 = div3({8'h55, 16'd5, 8'haa}); +localparam mod3_5 = mod3({8'h55, 16'd5, 8'haa}); + +localparam and9_f = and9(32'h55ffffaa); +localparam or9_0 = or9(32'h550000aa); +localparam xor9_f = xor9(32'h55ffffaa); + +localparam lsl3_p25 = lsl3({8'h55, 16'sd25, 8'haa}); +localparam lsr3_m25 = lsr3({8'h55, -16'sd25, 8'haa}); +localparam asl3_m25 = asl3({8'h55, -16'sd25, 8'haa}); +localparam asr3_m25 = asr3({8'h55, -16'sd25, 8'haa}); + +reg failed = 0; + +initial begin + $display("pre_inc_5 = %0h", pre_inc_5); + if (pre_inc_5 !== pre_inc({8'h55, 16'd5, 8'haa})) failed = 1; + if (pre_inc_5 !== 32'h550006aa) failed = 1; + + $display("pre_dec_5 = %0h", pre_dec_5); + if (pre_dec_5 !== pre_dec({8'h55, 16'd5, 8'haa})) failed = 1; + if (pre_dec_5 !== 32'h550004aa) failed = 1; + + $display("post_inc_5 = %0h", post_inc_5); + if (post_inc_5 !== post_inc({8'h55, 16'd5, 8'haa})) failed = 1; + if (post_inc_5 !== 32'h550006aa) failed = 1; + + $display("post_dec_5 = %0h", post_dec_5); + if (post_dec_5 !== post_dec({8'h55, 16'd5, 8'haa})) failed = 1; + if (post_dec_5 !== 32'h550004aa) failed = 1; + + $display("add2_5 = %0h", add2_5); + if (add2_5 !== add2({8'h55, 16'd5, 8'haa})) failed = 1; + if (add2_5 !== 32'h550007aa) failed = 1; + + $display("sub2_5 = %0h", sub2_5); + if (sub2_5 !== sub2({8'h55, 16'd5, 8'haa})) failed = 1; + if (sub2_5 !== 32'h550003aa) failed = 1; + + $display("mul2_5 = %0h", mul2_5); + if (mul2_5 !== mul2({8'h55, 16'd5, 8'haa})) failed = 1; + if (mul2_5 !== 32'h55000aaa) failed = 1; + + $display("div2_5 = %0h", div2_5); + if (div2_5 !== div2({8'h55, 16'd5, 8'haa})) failed = 1; + if (div2_5 !== 32'h550002aa) failed = 1; + + $display("mod2_5 = %0h", mod2_5); + if (mod2_5 !== mod2({8'h55, 16'd5, 8'haa})) failed = 1; + if (mod2_5 !== 32'h550001aa) failed = 1; + + $display("and6_f = %h", and6_f); + if (and6_f !== and6(32'h55ffffaa)) failed = 1; + if (and6_f !== 32'h556666aa) failed = 1; + + $display(" or6_0 = %h", or6_0); + if (or6_0 !== or6(32'h550000aa)) failed = 1; + if (or6_0 !== 32'h556666aa) failed = 1; + + $display("xor6_f = %h", xor6_f); + if (xor6_f !== xor6(32'h55ffffaa)) failed = 1; + if (xor6_f !== 32'h559999aa) failed = 1; + + $display("lsl2_p25 = %0h", lsl2_p25); + if (lsl2_p25 !== lsl2({8'h55, 16'sd25, 8'haa})) failed = 1; + if (lsl2_p25 !== 32'h550064aa) failed = 1; + + $display("lsr2_m25 = %0h", lsr2_m25); + if (lsr2_m25 !== lsr2({8'h55, -16'sd25, 8'haa})) failed = 1; + if (lsr2_m25 !== 32'h553ff9aa) failed = 1; + + $display("asl2_m25 = %0h", asl2_m25); + if (asl2_m25 !== asl2({8'h55, -16'sd25, 8'haa})) failed = 1; + if (asl2_m25 !== 32'h55ff9caa) failed = 1; + + $display("asr2_m25 = %0h", asr2_m25); + if (asr2_m25 !== asr2({8'h55, -16'sd25, 8'haa})) failed = 1; + if (asr2_m25 !== 32'h553ff9aa) failed = 1; + + $display("add3_5 = %0h", add3_5); + if (add3_5 !== add3({8'h55, 16'd5, 8'haa})) failed = 1; + if (add3_5 !== 32'h550008aa) failed = 1; + + $display("sub3_5 = %0h", sub3_5); + if (sub3_5 !== sub3({8'h55, 16'd5, 8'haa})) failed = 1; + if (sub3_5 !== 32'h550002aa) failed = 1; + + $display("mul3_5 = %0h", mul3_5); + if (mul3_5 !== mul3({8'h55, 16'd5, 8'haa})) failed = 1; + if (mul3_5 !== 32'h55000faa) failed = 1; + + $display("div3_5 = %0h", div3_5); + if (div3_5 !== div3({8'h55, 16'd5, 8'haa})) failed = 1; + if (div3_5 !== 32'h550001aa) failed = 1; + + $display("mod3_5 = %0h", mod3_5); + if (mod3_5 !== mod3({8'h55, 16'd5, 8'haa})) failed = 1; + if (mod3_5 !== 32'h550002aa) failed = 1; + + $display("and9_f = %h", and9_f); + if (and9_f !== and9(32'h55ffffaa)) failed = 1; + if (and9_f !== 32'h559999aa) failed = 1; + + $display(" or9_0 = %h", or9_0); + if (or9_0 !== or9(32'h550000aa)) failed = 1; + if (or9_0 !== 32'h559999aa) failed = 1; + + $display("xor9_f = %h", xor9_f); + if (xor9_f !== xor9(32'h55ffffaa)) failed = 1; + if (xor9_f !== 32'h556666aa) failed = 1; + + $display("lsl3_p25 = %0h", lsl3_p25); + if (lsl3_p25 !== lsl3({8'h55, 16'sd25, 8'haa})) failed = 1; + if (lsl3_p25 !== 32'h5500c8aa) failed = 1; + + $display("lsr3_m25 = %0h", lsr3_m25); + if (lsr3_m25 !== lsr3({8'h55, -16'sd25, 8'haa})) failed = 1; + if (lsr3_m25 !== 32'h551ffcaa) failed = 1; + + $display("asl3_m25 = %0h", asl3_m25); + if (asl3_m25 !== asl3({8'h55, -16'sd25, 8'haa})) failed = 1; + if (asl3_m25 !== 32'h55ff38aa) failed = 1; + + $display("asr3_m25 = %0h", asr3_m25); + if (asr3_m25 !== asr3({8'h55, -16'sd25, 8'haa})) failed = 1; + if (asr3_m25 !== 32'h551ffcaa) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/cfunc_assign_op_real.v b/ivtest/ivltests/cfunc_assign_op_real.v new file mode 100644 index 000000000..7f5770a14 --- /dev/null +++ b/ivtest/ivltests/cfunc_assign_op_real.v @@ -0,0 +1,200 @@ +`ifdef __ICARUS__ + `define SUPPORT_REAL_MODULUS_IN_IVTEST +`endif + +module test(); + +function real pre_inc(input real x); +begin + ++x; + pre_inc = x; +end +endfunction + +function real pre_dec(input real x); +begin + --x; + pre_dec = x; +end +endfunction + +function real post_inc(input real x); +begin + x++; + post_inc = x; +end +endfunction + +function real post_dec(input real x); +begin + x--; + post_dec = x; +end +endfunction + +localparam pre_inc_5 = pre_inc(5); +localparam pre_dec_5 = pre_dec(5); + +localparam post_inc_5 = post_inc(5); +localparam post_dec_5 = post_dec(5); + +function real add2(input real x); +begin + x += 2; + add2 = x; +end +endfunction + +function real sub2(input real x); +begin + x -= 2; + sub2 = x; +end +endfunction + +function real mul2(input real x); +begin + x *= 2; + mul2 = x; +end +endfunction + +function real div2(input real x); +begin + x /= 2; + div2 = x; +end +endfunction + +`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST +function real mod2(input real x); +begin + x %= 2; + mod2 = x; +end +endfunction +`endif + +localparam add2_5 = add2(5); +localparam sub2_5 = sub2(5); +localparam mul2_5 = mul2(5); +localparam div2_5 = div2(5); +`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST +localparam mod2_5 = mod2(5); +`endif + +function real add3(input real x); +begin + add3 = x; + add3 += 3; +end +endfunction + +function real sub3(input real x); +begin + sub3 = x; + sub3 -= 3; +end +endfunction + +function real mul3(input real x); +begin + mul3 = x; + mul3 *= 3; +end +endfunction + +function real div4(input real x); +begin + div4 = x; + div4 /= 4; +end +endfunction + +`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST +function real mod3(input real x); +begin + mod3 = x; + mod3 %= 3; +end +endfunction +`endif + +localparam add3_5 = add3(5); +localparam sub3_5 = sub3(5); +localparam mul3_5 = mul3(5); +localparam div4_5 = div4(5); +`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST +localparam mod3_5 = mod3(5); +`endif + +reg failed = 0; + +initial begin + $display("pre_inc_5 = %0f", pre_inc_5); + if (pre_inc_5 != pre_inc(5)) failed = 1; + if (pre_inc_5 != 6.0) failed = 1; + + $display("pre_dec_5 = %0f", pre_dec_5); + if (pre_dec_5 != pre_dec(5)) failed = 1; + if (pre_dec_5 != 4.0) failed = 1; + + $display("post_inc_5 = %0f", post_inc_5); + if (post_inc_5 != post_inc(5)) failed = 1; + if (post_inc_5 != 6.0) failed = 1; + + $display("post_dec_5 = %0f", post_dec_5); + if (post_dec_5 != post_dec(5)) failed = 1; + if (post_dec_5 != 4.0) failed = 1; + + $display("add2_5 = %0f", add2_5); + if (add2_5 != add2(5)) failed = 1; + if (add2_5 != 7.0) failed = 1; + + $display("sub2_5 = %0f", sub2_5); + if (sub2_5 != sub2(5)) failed = 1; + if (sub2_5 != 3.0) failed = 1; + + $display("mul2_5 = %0f", mul2_5); + if (mul2_5 != mul2(5)) failed = 1; + if (mul2_5 != 10.0) failed = 1; + + $display("div2_5 = %0f", div2_5); + if (div2_5 != div2(5)) failed = 1; + if (div2_5 != 2.5) failed = 1; + +`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST + $display("mod2_5 = %0f", mod2_5); + if (mod2_5 != mod2(5)) failed = 1; + if (mod2_5 != 1.0) failed = 1; +`endif + + $display("add3_5 = %0f", add3_5); + if (add3_5 != add3(5)) failed = 1; + if (add3_5 != 8.0) failed = 1; + + $display("sub3_5 = %0f", sub3_5); + if (sub3_5 != sub3(5)) failed = 1; + if (sub3_5 != 2.0) failed = 1; + + $display("mul3_5 = %0f", mul3_5); + if (mul3_5 != mul3(5)) failed = 1; + if (mul3_5 != 15.0) failed = 1; + + $display("div4_5 = %0f", div4_5); + if (div4_5 != div4(5)) failed = 1; + if (div4_5 != 1.25) failed = 1; + +`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST + $display("mod3_5 = %0f", mod3_5); + if (mod3_5 != mod3(5)) failed = 1; + if (mod3_5 != 2.0) failed = 1; +`endif + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/cfunc_assign_op_vec.v b/ivtest/ivltests/cfunc_assign_op_vec.v new file mode 100644 index 000000000..ce1029d9f --- /dev/null +++ b/ivtest/ivltests/cfunc_assign_op_vec.v @@ -0,0 +1,356 @@ +module test(); + +function integer pre_inc(input integer x); +begin + ++x; + pre_inc = x; +end +endfunction + +function integer pre_dec(input integer x); +begin + --x; + pre_dec = x; +end +endfunction + +function integer post_inc(input integer x); +begin + x++; + post_inc = x; +end +endfunction + +function integer post_dec(input integer x); +begin + x--; + post_dec = x; +end +endfunction + +localparam pre_inc_5 = pre_inc(5); +localparam pre_dec_5 = pre_dec(5); + +localparam post_inc_5 = post_inc(5); +localparam post_dec_5 = post_dec(5); + +function integer add2(input integer x); +begin + x += 2; + add2 = x; +end +endfunction + +function integer sub2(input integer x); +begin + x -= 2; + sub2 = x; +end +endfunction + +function integer mul2(input integer x); +begin + x *= 2; + mul2 = x; +end +endfunction + +function integer div2(input integer x); +begin + x /= 2; + div2 = x; +end +endfunction + +function integer mod2(input integer x); +begin + x %= 2; + mod2 = x; +end +endfunction + +function [3:0] and6(input [3:0] x); +begin + x &= 4'h6; + and6 = x; +end +endfunction + +function [3:0] or6(input [3:0] x); +begin + x |= 4'h6; + or6 = x; +end +endfunction + +function [3:0] xor6(input [3:0] x); +begin + x ^= 4'h6; + xor6 = x; +end +endfunction + +function integer lsl2(input integer x); +begin + x <<= 2; + lsl2 = x; +end +endfunction + +function integer lsr2(input integer x); +begin + x >>= 2; + lsr2 = x; +end +endfunction + +function integer asl2(input integer x); +begin + x <<<= 2; + asl2 = x; +end +endfunction + +function integer asr2(input integer x); +begin + x >>>= 2; + asr2 = x; +end +endfunction + +localparam add2_5 = add2(5); +localparam sub2_5 = sub2(5); +localparam mul2_5 = mul2(5); +localparam div2_5 = div2(5); +localparam mod2_5 = mod2(5); + +localparam and6_f = and6(4'hf); +localparam or6_0 = or6(4'h0); +localparam xor6_f = xor6(4'hf); + +localparam lsl2_p25 = lsl2( 25); +localparam lsr2_m25 = lsr2(-25); +localparam asl2_m25 = asl2(-25); +localparam asr2_m25 = asr2(-25); + +function integer add3(input integer x); +begin + add3 = x; + add3 += 3; +end +endfunction + +function integer sub3(input integer x); +begin + sub3 = x; + sub3 -= 3; +end +endfunction + +function integer mul3(input integer x); +begin + mul3 = x; + mul3 *= 3; +end +endfunction + +function integer div3(input integer x); +begin + div3 = x; + div3 /= 3; +end +endfunction + +function integer mod3(input integer x); +begin + mod3 = x; + mod3 %= 3; +end +endfunction + +function [3:0] and9(input [3:0] x); +begin + and9 = x; + and9 &= 4'h9; +end +endfunction + +function [3:0] or9(input [3:0] x); +begin + or9 = x; + or9 |= 4'h9; +end +endfunction + +function [3:0] xor9(input [3:0] x); +begin + xor9 = x; + xor9 ^= 4'h9; +end +endfunction + +function integer lsl3(input integer x); +begin + lsl3 = x; + lsl3 <<= 3; +end +endfunction + +function integer lsr3(input integer x); +begin + lsr3 = x; + lsr3 >>= 3; +end +endfunction + +function integer asl3(input integer x); +begin + asl3 = x; + asl3 <<<= 3; +end +endfunction + +function integer asr3(input integer x); +begin + asr3 = x; + asr3 >>>= 3; +end +endfunction + +localparam add3_5 = add3(5); +localparam sub3_5 = sub3(5); +localparam mul3_5 = mul3(5); +localparam div3_5 = div3(5); +localparam mod3_5 = mod3(5); + +localparam and9_f = and9(4'hf); +localparam or9_0 = or9(4'h0); +localparam xor9_f = xor9(4'hf); + +localparam lsl3_p25 = lsl3( 25); +localparam lsr3_m25 = lsr3(-25); +localparam asl3_m25 = asl3(-25); +localparam asr3_m25 = asr3(-25); + +reg failed = 0; + +initial begin + $display("pre_inc_5 = %0d", pre_inc_5); + if (pre_inc_5 !== pre_inc(5)) failed = 1; + if (pre_inc_5 !== 6) failed = 1; + + $display("pre_dec_5 = %0d", pre_dec_5); + if (pre_dec_5 !== pre_dec(5)) failed = 1; + if (pre_dec_5 !== 4) failed = 1; + + $display("post_inc_5 = %0d", post_inc_5); + if (post_inc_5 !== post_inc(5)) failed = 1; + if (post_inc_5 !== 6) failed = 1; + + $display("post_dec_5 = %0d", post_dec_5); + if (post_dec_5 !== post_dec(5)) failed = 1; + if (post_dec_5 !== 4) failed = 1; + + $display("add2_5 = %0d", add2_5); + if (add2_5 !== add2(5)) failed = 1; + if (add2_5 !== 7) failed = 1; + + $display("sub2_5 = %0d", sub2_5); + if (sub2_5 !== sub2(5)) failed = 1; + if (sub2_5 !== 3) failed = 1; + + $display("mul2_5 = %0d", mul2_5); + if (mul2_5 !== mul2(5)) failed = 1; + if (mul2_5 !== 10) failed = 1; + + $display("div2_5 = %0d", div2_5); + if (div2_5 !== div2(5)) failed = 1; + if (div2_5 !== 2) failed = 1; + + $display("mod2_5 = %0d", mod2_5); + if (mod2_5 !== mod2(5)) failed = 1; + if (mod2_5 !== 1) failed = 1; + + $display("and6_f = %h", and6_f); + if (and6_f !== and6(4'hf)) failed = 1; + if (and6_f !== 4'h6) failed = 1; + + $display("or6_0 = %h", or6_0); + if (or6_0 !== or6(4'h0)) failed = 1; + if (or6_0 !== 4'h6) failed = 1; + + $display("xor6_f = %h", xor6_f); + if (xor6_f !== xor6(4'hf)) failed = 1; + if (xor6_f !== 4'h9) failed = 1; + + $display("lsl2_p25 = %0d", lsl2_p25); + if (lsl2_p25 !== lsl2( 25)) failed = 1; + if (lsl2_p25 !== 100) failed = 1; + + $display("lsr2_m25 = %0h", lsr2_m25); + if (lsr2_m25 !== lsr2(-25)) failed = 1; + if (lsr2_m25 !== 32'h3ffffff9) failed = 1; + + $display("asl2_m25 = %0d", asl2_m25); + if (asl2_m25 !== asl2(-25)) failed = 1; + if (asl2_m25 !== -100) failed = 1; + + $display("asr2_m25 = %0d", asr2_m25); + if (asr2_m25 !== asr2(-25)) failed = 1; + if (asr2_m25 !== -7) failed = 1; + + $display("add3_5 = %0d", add3_5); + if (add3_5 !== add3(5)) failed = 1; + if (add3_5 !== 8) failed = 1; + + $display("sub3_5 = %0d", sub3_5); + if (sub3_5 !== sub3(5)) failed = 1; + if (sub3_5 !== 2) failed = 1; + + $display("mul3_5 = %0d", mul3_5); + if (mul3_5 !== mul3(5)) failed = 1; + if (mul3_5 !== 15) failed = 1; + + $display("div3_5 = %0d", div3_5); + if (div3_5 !== div3(5)) failed = 1; + if (div3_5 !== 1) failed = 1; + + $display("mod3_5 = %0d", mod3_5); + if (mod3_5 !== mod3(5)) failed = 1; + if (mod3_5 !== 2) failed = 1; + + $display("and9_f = %h", and9_f); + if (and9_f !== and9(4'hf)) failed = 1; + if (and9_f !== 4'h9) failed = 1; + + $display("or9_0 = %h", or9_0); + if (or9_0 !== or9(4'h0)) failed = 1; + if (or9_0 !== 4'h9) failed = 1; + + $display("xor9_f = %h", xor9_f); + if (xor9_f !== xor9(4'hf)) failed = 1; + if (xor9_f !== 4'h6) failed = 1; + + $display("lsl3_p25 = %0d", lsl3_p25); + if (lsl3_p25 !== lsl3( 25)) failed = 1; + if (lsl3_p25 !== 200) failed = 1; + + $display("lsr3_m25 = %0h", lsr3_m25); + if (lsr3_m25 !== lsr3(-25)) failed = 1; + if (lsr3_m25 !== 32'h1ffffffc) failed = 1; + + $display("asl3_m25 = %0d", asl3_m25); + if (asl3_m25 !== asl3(-25)) failed = 1; + if (asl3_m25 !== -200) failed = 1; + + $display("asr3_m25 = %0d", asr3_m25); + if (asr3_m25 !== asr3(-25)) failed = 1; + if (asr3_m25 !== -4) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/check_constant_1.v b/ivtest/ivltests/check_constant_1.v new file mode 100644 index 000000000..971dcf2cc --- /dev/null +++ b/ivtest/ivltests/check_constant_1.v @@ -0,0 +1,7 @@ +module top_module(); + +integer Value1; + +parameter Value2 = Value1; + +endmodule diff --git a/ivtest/ivltests/check_constant_10.v b/ivtest/ivltests/check_constant_10.v new file mode 100644 index 000000000..0c0ed7838 --- /dev/null +++ b/ivtest/ivltests/check_constant_10.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[N:0]; + +assign Array[0][0] = In[0]; +assign Array[0][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][7:1]; +end + +endmodule diff --git a/ivtest/ivltests/check_constant_11.v b/ivtest/ivltests/check_constant_11.v new file mode 100644 index 000000000..64faa6232 --- /dev/null +++ b/ivtest/ivltests/check_constant_11.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[N][0] = In[0]; +assign Array[0][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][7:1]; +end + +endmodule diff --git a/ivtest/ivltests/check_constant_12.v b/ivtest/ivltests/check_constant_12.v new file mode 100644 index 000000000..d25bc1f12 --- /dev/null +++ b/ivtest/ivltests/check_constant_12.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[0][7:1] = In[7:N]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][7:1]; +end + +endmodule diff --git a/ivtest/ivltests/check_constant_13.v b/ivtest/ivltests/check_constant_13.v new file mode 100644 index 000000000..8f1cb2a7f --- /dev/null +++ b/ivtest/ivltests/check_constant_13.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[0][7:1] = In[N:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][7:1]; +end + +endmodule diff --git a/ivtest/ivltests/check_constant_14.v b/ivtest/ivltests/check_constant_14.v new file mode 100644 index 000000000..33b7ff7ba --- /dev/null +++ b/ivtest/ivltests/check_constant_14.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[0][7:N] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][7:1]; +end + +endmodule diff --git a/ivtest/ivltests/check_constant_15.v b/ivtest/ivltests/check_constant_15.v new file mode 100644 index 000000000..cfe87a781 --- /dev/null +++ b/ivtest/ivltests/check_constant_15.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[0][N:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][7:1]; +end + +endmodule diff --git a/ivtest/ivltests/check_constant_16.v b/ivtest/ivltests/check_constant_16.v new file mode 100644 index 000000000..40647455e --- /dev/null +++ b/ivtest/ivltests/check_constant_16.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[N][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][7:1]; +end + +endmodule diff --git a/ivtest/ivltests/check_constant_17.v b/ivtest/ivltests/check_constant_17.v new file mode 100644 index 000000000..7a13fe0a0 --- /dev/null +++ b/ivtest/ivltests/check_constant_17.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[N][0] = In[0]; +assign Array[0][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][7:N]; +end + +endmodule diff --git a/ivtest/ivltests/check_constant_18.v b/ivtest/ivltests/check_constant_18.v new file mode 100644 index 000000000..30d073372 --- /dev/null +++ b/ivtest/ivltests/check_constant_18.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[0][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][N:1]; +end + +endmodule diff --git a/ivtest/ivltests/check_constant_19.v b/ivtest/ivltests/check_constant_19.v new file mode 100644 index 000000000..d3e8bda50 --- /dev/null +++ b/ivtest/ivltests/check_constant_19.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[0][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:N] = Array[0][7:1]; +end + +endmodule diff --git a/ivtest/ivltests/check_constant_2.v b/ivtest/ivltests/check_constant_2.v new file mode 100644 index 000000000..863279bea --- /dev/null +++ b/ivtest/ivltests/check_constant_2.v @@ -0,0 +1,15 @@ +module sub_module(); + +parameter Value1 = 0; + +endmodule + +module top_module(); + +integer Value2; + +sub_module sub_module(); + +defparam sub_module.Value1 = Value2; + +endmodule diff --git a/ivtest/ivltests/check_constant_20.v b/ivtest/ivltests/check_constant_20.v new file mode 100644 index 000000000..cab15c827 --- /dev/null +++ b/ivtest/ivltests/check_constant_20.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[0][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[N:0] = Array[0][7:1]; +end + +endmodule diff --git a/ivtest/ivltests/check_constant_3.v b/ivtest/ivltests/check_constant_3.v new file mode 100644 index 000000000..60ef9139c --- /dev/null +++ b/ivtest/ivltests/check_constant_3.v @@ -0,0 +1,9 @@ +module top_module(); + +integer Value1; + +integer Value2 = Value1; + +initial $display("PASSED"); + +endmodule diff --git a/ivtest/ivltests/check_constant_4.v b/ivtest/ivltests/check_constant_4.v new file mode 100644 index 000000000..4ed2b7298 --- /dev/null +++ b/ivtest/ivltests/check_constant_4.v @@ -0,0 +1,8 @@ +module top_module(); + +integer N; + +(* attr = N *) +initial $display(N); + +endmodule diff --git a/ivtest/ivltests/check_constant_5.v b/ivtest/ivltests/check_constant_5.v new file mode 100644 index 000000000..a833d2cb6 --- /dev/null +++ b/ivtest/ivltests/check_constant_5.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [7:N] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[0][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][7:1]; +end + +endmodule diff --git a/ivtest/ivltests/check_constant_6.v b/ivtest/ivltests/check_constant_6.v new file mode 100644 index 000000000..625a7c493 --- /dev/null +++ b/ivtest/ivltests/check_constant_6.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [N:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[0][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][7:1]; +end + +endmodule diff --git a/ivtest/ivltests/check_constant_7.v b/ivtest/ivltests/check_constant_7.v new file mode 100644 index 000000000..b3f5d71c4 --- /dev/null +++ b/ivtest/ivltests/check_constant_7.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:N] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[0][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][7:1]; +end + +endmodule diff --git a/ivtest/ivltests/check_constant_8.v b/ivtest/ivltests/check_constant_8.v new file mode 100644 index 000000000..af983e741 --- /dev/null +++ b/ivtest/ivltests/check_constant_8.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [N:0] Array[7:0]; + +assign Array[0][0] = In[0]; +assign Array[0][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][7:1]; +end + +endmodule diff --git a/ivtest/ivltests/check_constant_9.v b/ivtest/ivltests/check_constant_9.v new file mode 100644 index 000000000..0b410b904 --- /dev/null +++ b/ivtest/ivltests/check_constant_9.v @@ -0,0 +1,17 @@ +module top_module( + input wire [2:0] N, + input wire [7:0] In, + output reg [7:0] Out +); + +wire [7:0] Array[7:N]; + +assign Array[0][0] = In[0]; +assign Array[0][7:1] = In[7:1]; + +initial begin + Out[0] = Array[0][0]; + Out[7:1] = Array[0][7:1]; +end + +endmodule diff --git a/ivtest/ivltests/clkgen_bit.v b/ivtest/ivltests/clkgen_bit.v new file mode 100644 index 000000000..27eebfce0 --- /dev/null +++ b/ivtest/ivltests/clkgen_bit.v @@ -0,0 +1,39 @@ +/* + * Author: Oswaldo Cadenas + * + * The test checks the module bit ouput type accepts default + * initialization value. + */ + +module clkgen(output bit clk = 0); + +initial begin + #100; + disable checking; + disable gen; + $display ("PASSED"); + $finish; +end + +initial begin + fork + gen; + checking; + join +end + +task gen; + forever #10 clk = ~clk; +endtask + +task checking; + forever begin + #1; + if (clk ==! 1'b0 && clk ==! 1'b1 ) begin + $display ("FAILED!"); + $finish; + end + end +endtask + +endmodule diff --git a/ivtest/ivltests/clkgen_logic.v b/ivtest/ivltests/clkgen_logic.v new file mode 100644 index 000000000..d6179c7cc --- /dev/null +++ b/ivtest/ivltests/clkgen_logic.v @@ -0,0 +1,40 @@ +/* + * Author: Oswaldo Cadenas + * + * The test checks the module logic ouput type accepts default + * initialization value. If no default value is given to logic output + * type then this test fails. + */ + +module clkgen(output logic clk = 0); + +initial begin + #100; + disable checking; + disable gen; + $display ("PASSED"); + $finish; +end + +initial begin + fork + gen; + checking; + join +end + +task gen; + forever #10 clk = ~clk; +endtask + +task checking; + forever begin + #1; + if (clk === 1'bx ) begin + $display ("FAILED!"); + $finish; + end + end +endtask + +endmodule diff --git a/ivtest/ivltests/clkgen_net.v b/ivtest/ivltests/clkgen_net.v new file mode 100644 index 000000000..4e7374bcd --- /dev/null +++ b/ivtest/ivltests/clkgen_net.v @@ -0,0 +1,46 @@ +/* + * Author: Oswaldo Cadenas + * + * The test checks that an unspecified output type is elaborated as Net. + * If an intial value is given to an unspecified ouput type it does + * not compile. + */ + +module clkgen(output clk); + +logic iclk = 'x; +assign clk = iclk; + +initial begin + #100; + disable checking; + disable gen; + $display ("PASSED"); + $finish; +end + +initial begin + fork + checking; + gen; + join +end + + +task gen; + begin + iclk = 0; + forever #10 iclk = ~iclk; + end +endtask + +task checking; + forever begin + #1; + if (clk === 1'bx ) begin + $display ("FAILED!"); + $finish; + end + end +endtask +endmodule diff --git a/ivtest/ivltests/clkgen_reg.v b/ivtest/ivltests/clkgen_reg.v new file mode 100644 index 000000000..26ed5ee40 --- /dev/null +++ b/ivtest/ivltests/clkgen_reg.v @@ -0,0 +1,40 @@ +/* + * Author: Oswaldo Cadenas + * + * The test checks the module reg ouput type accepts default + * initialization value. If no default value is given to reg output + * type then this test fails. + */ + +module clkgen(output reg clk = 0); + +initial begin + #100; + disable checking; + disable gen; + $display ("PASSED"); + $finish; +end + +initial begin + fork + gen; + checking; + join +end + +task gen; + forever #10 clk = ~clk; +endtask + +task checking; + forever begin + #1; + if (clk === 1'bx ) begin + $display ("FAILED!"); + $finish; + end + end +endtask + +endmodule diff --git a/ivtest/ivltests/clog2-signal.v b/ivtest/ivltests/clog2-signal.v new file mode 100644 index 000000000..e854f7c55 --- /dev/null +++ b/ivtest/ivltests/clog2-signal.v @@ -0,0 +1,9 @@ +module top; + integer in; + + initial begin + in = 2; + if ($clog2(in) != 1) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/clog2.v b/ivtest/ivltests/clog2.v new file mode 100644 index 000000000..cbf7af942 --- /dev/null +++ b/ivtest/ivltests/clog2.v @@ -0,0 +1,358 @@ +// Still need to check real wires and what they return! +module top; + // Any unsized negative value will be 32 bits or more! + parameter pm1 = $clog2(-1); + parameter prm1 = $clog2(-1.0); + parameter prm30 = $clog2(-(2**31-1)); + parameter prm31 = $clog2(-(2**31)); + parameter prm32 = $clog2(-(33'sd2**32)); + parameter prm67 = $clog2(-(68'sd2**67)); + parameter p0 = $clog2(0); + parameter p1 = $clog2(1); + parameter p2 = $clog2(2); + parameter p3 = $clog2(3); + parameter p4 = $clog2(4); + parameter p5 = $clog2(5); + parameter p8 = $clog2(8); + parameter p8r = $clog2(8.49999); + parameter p128 = $clog2(129'h100000000000000000000000000000000); + parameter p128p = $clog2(129'sd2**128); + // These all return 'bx. + parameter pminf = $clog2(-1.0/0.0); // -Inf + parameter pinf = $clog2(1.0/0.0); // +Inf + parameter px = $clog2('bx); + + reg [$clog2(8)-1:0] reg8 = 'b0; + + reg pass = 1'b1; + + integer result; + + reg [128:0] in; + wire [7:0] out = $clog2(in); + + real rin; + wire [7:0] rout = $clog2(rin); + + wire real rin2 = rin * 2.0; + wire [7:0] rout2 = $clog2(rin2); + + initial begin + + /* Test the elab_pexpr implementation. */ + + if ($bits(reg8) !== 3) begin + $display("Failed register size, expected 3, got %d", $bits(reg8)); + pass = 1'b0; + end + + if (pm1 !== 32) begin + $display("Failed with param. -1, expected 32, got %d", pm1); + pass = 1'b0; + end + if (prm1 !== 32) begin + $display("Failed with param. -1.0, expected 32, got %d", prm1); + pass = 1'b0; + end + if (prm30 !== 32) begin + $display("Failed with param. -(2**30-1), expected 32, got %d", prm30); + pass = 1'b0; + end + if (prm31 !== 32) begin + $display("Failed with param. -(2**31), expected 32, got %d", prm31); + pass = 1'b0; + end + if (prm32 !== 32) begin + $display("Failed with param. -(2**32), expected 32, got %d", prm32); + pass = 1'b0; + end + if (prm67 !== 67) begin + $display("Failed with param. -(2**67), expected 67, got %d", prm67); + pass = 1'b0; + end + if (p0 !== 0) begin + $display("Failed with param. 0, expected 0, got %d", p0); + pass = 1'b0; + end + if (p1 !== 0) begin + $display("Failed with param. 1, expected 0, got %d", p1); + pass = 1'b0; + end + if (p2 !== 1) begin + $display("Failed with param. 2, expected 1, got %d", p2); + pass = 1'b0; + end + if (p3 !== 2) begin + $display("Failed with param. 3, expected 2, got %d", p3); + pass = 1'b0; + end + if (p4 !== 2) begin + $display("Failed with param. 4, expected 2, got %d", p4); + pass = 1'b0; + end + if (p5 !== 3) begin + $display("Failed with param. 5, expected 3, got %d", p5); + pass = 1'b0; + end + if (p8 !== 3) begin + $display("Failed with param. 8, expected 3, got %d", p8); + pass = 1'b0; + end + if (p8r !== 3) begin + $display("Failed with param. 8 (real), expected 3, got %d", p8r); + pass = 1'b0; + end + if (p128 !== 128) begin + $display("Failed with param. 129'h10...0, expected 128, got %d", p128); + pass = 1'b0; + end + if (p128p !== 128) begin + $display("Failed with param. 2**128, expected 128, got %d", p128p); + pass = 1'b0; + end + if (pinf !== 32'bx) begin + $display("Failed with param. Inf, expected 32'bx, got %b", pinf); + pass = 1'b0; + end + if (pminf !== 32'bx) begin + $display("Failed with param. -Inf, expected 32'bx, got %b", pminf); + pass = 1'b0; + end + if (px !== 32'bx) begin + $display("Failed with param. `bx, expected 32'bx, got %b", px); + pass = 1'b0; + end + + /* Test the eval_tree implementation. */ + + // Any unsized negative value will be 32 bits or more! + result = $clog2(-1); + if (result !== 32) begin + $display("Failed with -1, expected 32, got %d", result); + pass = 1'b0; + end + + result = $clog2(-1.0); + if (result !== 32) begin + $display("Failed with -1.0, expected 32, got %d", result); + pass = 1'b0; + end + + result = $clog2(-(2**31)); + if (result !== 32) begin + $display("Failed with -(2**31), expected 32, got %d", result); + pass = 1'b0; + end + + result = $clog2(-(33'sd2**32)); + if (result !== 32) begin + $display("Failed with -(2**32), expected 32, got %d", result); + pass = 1'b0; + end + + result = $clog2(-(68'sd2**67)); + if (result !== 67) begin + $display("Failed with -(2**67), expected 67, got %d", result); + pass = 1'b0; + end + + result = $clog2(0); + if (result !== 0) begin + $display("Failed with 0, expected 0, got %d", result); + pass = 1'b0; + end + result = $clog2(1); + if (result !== 0) begin + $display("Failed with 1, expected 0, got %d", result); + pass = 1'b0; + end + + result = $clog2(2); + if (result !== 1) begin + $display("Failed with 2, expected 1, got %d", result); + pass = 1'b0; + end + + result = $clog2(3); + if (result !== 2) begin + $display("Failed with 3, expected 2, got %d", result); + pass = 1'b0; + end + result = $clog2(4); + if (result !== 2) begin + $display("Failed with 4, expected 2, got %d", result); + pass = 1'b0; + end + + result = $clog2(5); + if (result !== 3) begin + $display("Failed with 5, expected 3, got %d", result); + pass = 1'b0; + end + result = $clog2(8); + if (result !== 3) begin + $display("Failed with 8, expected 3, got %d", result); + pass = 1'b0; + end + result = $clog2(8.1); + if (result !== 3) begin + $display("Failed with 8.1, expected 3, got %d", result); + pass = 1'b0; + end + result = $clog2(8.49999); + if (result !== 3) begin + $display("Failed with 8.49999, expected 3, got %d", result); + pass = 1'b0; + end + result = $clog2(8.5); + if (result !== 4) begin + $display("Failed with 8.5, expected 4, got %d", result); + pass = 1'b0; + end + + result = $clog2(129'h100000000000000000000000000000000); + if (result !== 128) begin + $display("Failed with 129'h10...0, expected 128, got %d", result); + pass = 1'b0; + end + + result = $clog2(129'sd2**128); + if (result !== 128) begin + $display("Failed with 2**128, expected 128, got %d", result); + pass = 1'b0; + end + + result = $clog2(1.0/0.0); // Inf + if (result !== 32'bx) begin + $display("Failed with Inf, expected 32'bx, got %b", result); + pass = 1'b0; + end + + result = $clog2(-1.0/0.0); // -Inf + if (result !== 32'bx) begin + $display("Failed with -Inf, expected 32'bx, got %b", result); + pass = 1'b0; + end + + result = $clog2('bx); + if (result !== 32'bx) begin + $display("Failed with `bx, expected 32'bx, got %b", result); + pass = 1'b0; + end + + /* Test the CA statements and the vpi implementation. */ + + in = -1; // This is not an unsized value ('in' is 129 bits)! + #1 if (out != 129) begin + $display("Failed CA with -1, expected 129, got %d", out); + pass = 1'b0; + end + + in = 0; + #1 if (out !== 0) begin + $display("Failed CA with 0, expected 0, got %d", out); + pass = 1'b0; + end + in = 1; + #1 if (out !== 0) begin + $display("Failed CA with 1, expected 0, got %d", out); + pass = 1'b0; + end + + in = 2; + #1 if (out !== 1) begin + $display("Failed CA with 2, expected 1, got %d", out); + pass = 1'b0; + end + + in = 3; + #1 if (out !== 2) begin + $display("Failed CA with 3, expected 2, got %d", out); + pass = 1'b0; + end + in = 4; + #1 if (out !== 2) begin + $display("Failed CA with 4, expected 2, got %d", out); + pass = 1'b0; + end + + in = 5; + #1 if (out !== 3) begin + $display("Failed CA with 5, expected 3, got %d", out); + pass = 1'b0; + end + in = 8; + #1 if (out !== 3) begin + $display("Failed CA with 8, expected 3, got %d", out); + pass = 1'b0; + end + + rin = -1.0; // This is an unsized value (reals are unsized)! + #1 if (rout !== 32 && rout2 !== 32) begin + $display("Failed CA with -1.0, expected 32/32, got %d/%d", rout, rout2); + pass = 1'b0; + end + rin = 8.1; + #1 if (rout !== 3 && rout2 !== 4) begin + $display("Failed CA with 8.1, expected 3/4, got %d/%d", rout, rout2); + pass = 1'b0; + end + rin = 8.49999; + #1 if (rout !== 3 && rout2 !== 4) begin + $display("Failed CA with 8.49999, expected 3/4, got %d/%d", rout, rout2); + pass = 1'b0; + end + rin = 8.5; + #1 if (rout !== 4 && rout2 !== 5) begin + $display("Failed CA with 8.5, expected 4/5, got %d/%d", rout, rout2); + pass = 1'b0; + end + + in = 129'h100000000000000000000000000000000; + #1 if (out !== 128) begin + $display("Failed CA with 129'h10...0, expected 128, got %d", out); + pass = 1'b0; + end + + in = 2**128; + #1 if (out !== 128) begin + $display("Failed CA with 2**128, expected 128, got %d", out); + pass = 1'b0; + end + + in = 'bx; + #1 if (out !== 8'bx) begin + $display("Failed CA with 'bx, expected 8'bx, got %b", out); + pass = 1'b0; + end + + rin = 1.0/0.0; + #1 if (rout !== 8'bx && rout2 !== 8'bx) begin + $display("Failed CA with Inf, expected 8'bx/8'bx got %b/%b", rout, rout2); + pass = 1'b0; + end + rin = -1.0/0.0; + #1 if (rout !== 8'bx && rout2 !== 8'bx) begin + $display("Failed CA with -Inf, expected 8'bx/8'bx got %b/%b", rout, rout2); + pass = 1'b0; + end + + /* Check that the result is sign extended correctly. */ + // Compile time generated. + in = $clog2(1.0/0.0); + if (in !== 129'bx) begin + $display("Failed sign extended Inf (C), expected 129'bx got %b", in); + pass = 1'b0; + end + + // Run time generated. + rin = 1.0; + in = $clog2(rin/0.0); + if (in !== 129'bx) begin + $display("Failed sign extended Inf (RT), expected 129'bx got %b", in); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/cmdline_parm1.v b/ivtest/ivltests/cmdline_parm1.v new file mode 100644 index 000000000..2312d7ea4 --- /dev/null +++ b/ivtest/ivltests/cmdline_parm1.v @@ -0,0 +1,18 @@ +/* + * This program tests the simple parameter override from the command + * line. This program should be compiled with the -Pmain.foo=2 argument. + */ +module main; + + parameter foo = 1; + + initial begin + if (foo != 2) begin + $display("FAILED: %m.foo = %d", foo); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/cmos.v b/ivtest/ivltests/cmos.v new file mode 100644 index 000000000..925f0334c --- /dev/null +++ b/ivtest/ivltests/cmos.v @@ -0,0 +1,40 @@ +module top; + reg nctl, pctl, b; + wire a, c; + initial begin + $monitor(a,c,,"%v",a,,"%v",c,,b,,nctl,,pctl); + b = 0; + nctl = 0; + pctl = 1; + #1 nctl = 1; pctl = 0; + #1 nctl = 1; pctl = 1; + #1 nctl = 0; pctl = 0; + #1 nctl = 1'bx; pctl = 0; + #1 nctl = 1; pctl = 1'bx; + #1 nctl = 1'bx; pctl = 1; + #1 nctl = 0; pctl = 1'bx; + #1 nctl = 1'bx; pctl = 1'bx; + + #1 b = 1; nctl = 0; pctl = 1; + #1 nctl = 1; pctl = 0; + #1 nctl = 1; pctl = 1; + #1 nctl = 0; pctl = 0; + #1 nctl = 1'bx; pctl = 0; + #1 nctl = 1; pctl = 1'bx; + #1 nctl = 1'bx; pctl = 1; + #1 nctl = 0; pctl = 1'bx; + #1 nctl = 1'bx; pctl = 1'bx; + + #1 b = 1'bx; nctl = 0; pctl = 1; + #1 b = 1'bx; nctl = 1; pctl = 0; + #1 b = 1'bx; nctl = 1'bx; pctl = 1'bx; + + #1 b = 1'bz; nctl = 0; pctl = 1; + #1 b = 1'bz; nctl = 1; pctl = 0; + #1 b = 1'bz; nctl = 1'bx; pctl = 1'bx; + end + + nmos n1 (a, b, nctl); + pmos p1 (a, b, pctl); + cmos c1 (c, b, nctl, pctl); +endmodule diff --git a/ivtest/ivltests/cmpi.v b/ivtest/ivltests/cmpi.v new file mode 100644 index 000000000..b1350bfc2 --- /dev/null +++ b/ivtest/ivltests/cmpi.v @@ -0,0 +1,68 @@ + +module main; + + reg [7:0] val; + + initial begin + val = 120; + + if (8'd5 < val) begin + $display("OK"); + end else begin + $display("FAILED"); + $finish; + end + + if (8'd5 <= val) begin + $display("OK"); + end else begin + $display("FAILED"); + $finish; + end + + if (8'd121 > val) begin + $display("OK"); + end else begin + $display("FAILED"); + $finish; + end + + if (8'd121 >= val) begin + $display("OK"); + end else begin + $display("FAILED"); + $finish; + end + + if (val > 8'd5) begin + $display("OK"); + end else begin + $display("FAILED"); + $finish; + end + + if (val >= 8'd5) begin + $display("OK"); + end else begin + $display("FAILED"); + $finish; + end + + if (val < 8'd121) begin + $display("OK"); + end else begin + $display("FAILED"); + $finish; + end + + if (val <= 8'd121) begin + $display("OK"); + end else begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/comment1.v b/ivtest/ivltests/comment1.v new file mode 100644 index 000000000..eeaa15b8a --- /dev/null +++ b/ivtest/ivltests/comment1.v @@ -0,0 +1,5 @@ +/* )* */ +/* (* /* *) */ +module test(); +initial $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/comp1000.v b/ivtest/ivltests/comp1000.v new file mode 100644 index 000000000..4ac75285e --- /dev/null +++ b/ivtest/ivltests/comp1000.v @@ -0,0 +1,1190 @@ +// +// Copyright (c) 2000 Paul Campbell (paul@verifarm.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +module compl1000; + reg [158:143]r0; + reg [128:104]r1; + reg [200:173]r2; + reg [165:162]r3; + reg [150:129]r4; + reg [123:93]r5; + reg [55:54]r6; + reg [24:3]r7; + reg [109:93]r8; + reg [30:14]r9; + reg [184:174]r10; + reg [59:30]r11; + reg [153:124]r12; + reg [248:221]r13; + reg [258:250]r14; + reg [158:147]r15; + reg [54:48]r16; + reg [159:136]r17; + reg [214:187]r18; + reg [60:29]r19; + reg [71:71]r20; + reg [177:169]r21; + reg [219:205]r22; + reg [24:21]r23; + reg [153:141]r24; + reg [85:54]r25; + reg [227:202]r26; + reg [251:237]r27; + reg [98:73]r28; + reg [24:0]r29; + reg [166:135]r30; + reg [184:183]r31; + reg [219:189]r32; + reg [81:54]r33; + reg [164:148]r34; + reg [170:158]r35; + reg [171:168]r36; + reg [255:226]r37; + reg [197:191]r38; + reg [113:105]r39; + reg [221:198]r40; + reg [135:104]r41; + reg [153:143]r42; + reg [281:253]r43; + reg [101:76]r44; + reg [24:12]r45; + reg [217:203]r46; + reg [244:218]r47; + reg [128:111]r48; + reg [136:107]r49; + reg [260:242]r50; + reg [157:156]r51; + reg [242:220]r52; + reg [278:255]r53; + reg [196:194]r54; + reg [148:121]r55; + reg [71:63]r56; + reg [166:157]r57; + reg [200:180]r58; + reg [230:199]r59; + reg [212:191]r60; + reg [264:248]r61; + reg [136:124]r62; + reg [131:117]r63; + reg [148:126]r64; + reg [51:30]r65; + reg [166:140]r66; + reg [166:143]r67; + reg [44:27]r68; + reg [259:248]r69; + reg [167:143]r70; + reg [210:189]r71; + reg [73:50]r72; + reg [225:205]r73; + reg [255:240]r74; + reg [208:194]r75; + reg [222:217]r76; + reg [217:189]r77; + reg [100:83]r78; + reg [275:255]r79; + reg [39:34]r80; + reg [98:72]r81; + reg [55:25]r82; + reg [246:240]r83; + reg [170:157]r84; + reg [218:198]r85; + reg [225:223]r86; + reg [186:172]r87; + reg [241:213]r88; + reg [263:238]r89; + reg [272:253]r90; + reg [105:103]r91; + reg [211:209]r92; + reg [89:82]r93; + reg [30:9]r94; + reg [246:241]r95; + reg [170:147]r96; + reg [229:224]r97; + reg [107:83]r98; + reg [60:54]r99; + reg [154:154]r100; + reg [105:97]r101; + reg [127:104]r102; + reg [219:190]r103; + reg [114:98]r104; + reg [267:251]r105; + reg [169:145]r106; + reg [64:45]r107; + reg [227:224]r108; + reg [186:176]r109; + reg [101:84]r110; + reg [219:194]r111; + reg [11:9]r112; + reg [236:222]r113; + reg [271:240]r114; + reg [232:218]r115; + reg [78:74]r116; + reg [191:191]r117; + reg [242:227]r118; + reg [135:108]r119; + reg [24:15]r120; + reg [250:233]r121; + reg [125:102]r122; + reg [165:140]r123; + reg [63:63]r124; + reg [235:206]r125; + reg [264:237]r126; + reg [241:234]r127; + reg [188:188]r128; + reg [71:59]r129; + reg [181:170]r130; + reg [106:83]r131; + reg [245:229]r132; + reg [239:219]r133; + reg [10:8]r134; + reg [45:45]r135; + reg [23:22]r136; + reg [197:178]r137; + reg [57:50]r138; + reg [264:253]r139; + reg [53:36]r140; + reg [187:164]r141; + reg [153:140]r142; + reg [235:226]r143; + reg [236:228]r144; + reg [262:238]r145; + reg [76:55]r146; + reg [49:25]r147; + reg [191:163]r148; + reg [197:170]r149; + reg [151:143]r150; + reg [126:122]r151; + reg [188:173]r152; + reg [93:78]r153; + reg [175:175]r154; + reg [249:247]r155; + reg [214:200]r156; + reg [60:43]r157; + reg [263:233]r158; + reg [54:34]r159; + reg [202:184]r160; + reg [250:240]r161; + reg [99:80]r162; + reg [175:165]r163; + reg [189:188]r164; + reg [52:38]r165; + reg [74:48]r166; + reg [232:202]r167; + reg [24:13]r168; + reg [209:180]r169; + reg [173:147]r170; + reg [264:243]r171; + reg [115:99]r172; + reg [94:91]r173; + reg [195:188]r174; + reg [36:33]r175; + reg [136:114]r176; + reg [82:56]r177; + reg [204:173]r178; + reg [116:111]r179; + reg [124:103]r180; + reg [76:71]r181; + reg [178:163]r182; + reg [156:149]r183; + reg [124:110]r184; + reg [240:220]r185; + reg [164:151]r186; + reg [133:104]r187; + reg [59:46]r188; + reg [47:42]r189; + reg [219:189]r190; + reg [99:87]r191; + reg [86:73]r192; + reg [222:191]r193; + reg [23:7]r194; + reg [239:238]r195; + reg [240:222]r196; + reg [27:4]r197; + reg [191:160]r198; + reg [106:84]r199; + reg [22:8]r200; + reg [204:191]r201; + reg [133:115]r202; + reg [225:207]r203; + reg [126:95]r204; + reg [161:147]r205; + reg [193:164]r206; + reg [69:61]r207; + reg [130:116]r208; + reg [142:124]r209; + reg [50:20]r210; + reg [175:154]r211; + reg [102:87]r212; + reg [114:85]r213; + reg [225:223]r214; + reg [131:127]r215; + reg [24:19]r216; + reg [84:84]r217; + reg [223:223]r218; + reg [171:159]r219; + reg [76:47]r220; + reg [162:139]r221; + reg [67:41]r222; + reg [88:74]r223; + reg [60:44]r224; + reg [114:104]r225; + reg [142:141]r226; + reg [262:236]r227; + reg [16:12]r228; + reg [66:51]r229; + reg [40:24]r230; + reg [150:141]r231; + reg [209:199]r232; + reg [152:148]r233; + reg [162:147]r234; + reg [82:80]r235; + reg [245:214]r236; + reg [35:12]r237; + reg [18:3]r238; + reg [270:246]r239; + reg [183:170]r240; + reg [122:121]r241; + reg [60:42]r242; + reg [99:91]r243; + reg [61:51]r244; + reg [154:150]r245; + reg [5:3]r246; + reg [275:246]r247; + reg [113:92]r248; + reg [136:118]r249; + reg [94:71]r250; + reg [104:91]r251; + reg [169:139]r252; + reg [22:14]r253; + reg [255:236]r254; + reg [213:186]r255; + initial begin + r0 = 32'h3d24; + r1 = 32'h70fd; + r2 = 32'h47aa; + r3 = 32'h39ed; + r4 = 32'h2ca3; + r5 = 32'he68; + r6 = 32'h1160; + r7 = 32'h5636; + r8 = 32'h2305; + r9 = 32'h1257; + r10 = 32'h4e74; + r11 = 32'h3835; + r12 = 32'h3857; + r13 = 32'h3f6f; + r14 = 32'h7b33; + r15 = 32'h2f37; + r16 = 32'h10a; + r17 = 32'h6cff; + r18 = 32'h3f3; + r19 = 32'h70e2; + r20 = 32'h4cb3; + r21 = 32'h510; + r22 = 32'h1837; + r23 = 32'h425; + r24 = 32'h1488; + r25 = 32'h5731; + r26 = 32'h1388; + r27 = 32'h6ee0; + r28 = 32'h559b; + r29 = 32'h4bff; + r30 = 32'h180e; + r31 = 32'h1252; + r32 = 32'h52d4; + r33 = 32'h4576; + r34 = 32'h36f1; + r35 = 32'h6246; + r36 = 32'h7aaf; + r37 = 32'h37fb; + r38 = 32'h4272; + r39 = 32'h62fd; + r40 = 32'h6cbb; + r41 = 32'h4825; + r42 = 32'h25c7; + r43 = 32'h19da; + r44 = 32'h5ace; + r45 = 32'h794f; + r46 = 32'h5ebb; + r47 = 32'h5cd0; + r48 = 32'h4209; + r49 = 32'h38de; + r50 = 32'h7502; + r51 = 32'h2c8c; + r52 = 32'h378f; + r53 = 32'h5252; + r54 = 32'hb5d; + r55 = 32'h561; + r56 = 32'h4504; + r57 = 32'h180f; + r58 = 32'h6672; + r59 = 32'h52f7; + r60 = 32'h10c7; + r61 = 32'h4ce9; + r62 = 32'h569; + r63 = 32'h72b3; + r64 = 32'h4df0; + r65 = 32'h1a72; + r66 = 32'h2846; + r67 = 32'h70e5; + r68 = 32'h3008; + r69 = 32'h2003; + r70 = 32'h6009; + r71 = 32'h6cb5; + r72 = 32'h5e8b; + r73 = 32'h668b; + r74 = 32'h487; + r75 = 32'h4eca; + r76 = 32'h241e; + r77 = 32'h451a; + r78 = 32'h2c06; + r79 = 32'h3ebf; + r80 = 32'h5590; + r81 = 32'h22c; + r82 = 32'h9b; + r83 = 32'h347; + r84 = 32'h2c92; + r85 = 32'h3db6; + r86 = 32'hf44; + r87 = 32'h391a; + r88 = 32'h1237; + r89 = 32'h6ff2; + r90 = 32'h6cc5; + r91 = 32'hca7; + r92 = 32'h152a; + r93 = 32'h8eb; + r94 = 32'h4c43; + r95 = 32'h6277; + r96 = 32'h7b1; + r97 = 32'h7cc8; + r98 = 32'h63a2; + r99 = 32'h1a62; + r100 = 32'h165; + r101 = 32'h48d8; + r102 = 32'h399e; + r103 = 32'h5975; + r104 = 32'h40ae; + r105 = 32'h3d61; + r106 = 32'h39ab; + r107 = 32'h69f; + r108 = 32'h2801; + r109 = 32'h1828; + r110 = 32'h298d; + r111 = 32'h661e; + r112 = 32'h52d9; + r113 = 32'h3bc0; + r114 = 32'h5cb7; + r115 = 32'h7fac; + r116 = 32'h7e76; + r117 = 32'hf93; + r118 = 32'h4165; + r119 = 32'h3b68; + r120 = 32'h4258; + r121 = 32'h54b2; + r122 = 32'h2378; + r123 = 32'h6186; + r124 = 32'h547a; + r125 = 32'h7b5c; + r126 = 32'h4115; + r127 = 32'h68b6; + r128 = 32'h554f; + r129 = 32'h4550; + r130 = 32'hcfc; + r131 = 32'h3f55; + r132 = 32'h5f7d; + r133 = 32'h40d2; + r134 = 32'h3aa8; + r135 = 32'h7b56; + r136 = 32'h575c; + r137 = 32'h687f; + r138 = 32'h702c; + r139 = 32'h1cee; + r140 = 32'h362d; + r141 = 32'h73d2; + r142 = 32'h39c8; + r143 = 32'h5003; + r144 = 32'h4d1a; + r145 = 32'h2472; + r146 = 32'h1b4e; + r147 = 32'h5852; + r148 = 32'h3bf2; + r149 = 32'h1c41; + r150 = 32'h5b37; + r151 = 32'h1462; + r152 = 32'h17a1; + r153 = 32'h825; + r154 = 32'h6384; + r155 = 32'h432c; + r156 = 32'h7c70; + r157 = 32'h2b94; + r158 = 32'h5456; + r159 = 32'h7887; + r160 = 32'h802; + r161 = 32'h18e2; + r162 = 32'h244c; + r163 = 32'h6c55; + r164 = 32'h770a; + r165 = 32'h224a; + r166 = 32'h6aa0; + r167 = 32'h1070; + r168 = 32'h62cd; + r169 = 32'h4fbe; + r170 = 32'h2f01; + r171 = 32'h1952; + r172 = 32'h5a5b; + r173 = 32'h656e; + r174 = 32'h5b2e; + r175 = 32'h6586; + r176 = 32'h538d; + r177 = 32'h471a; + r178 = 32'h2a57; + r179 = 32'h6fd2; + r180 = 32'h2fbd; + r181 = 32'h4418; + r182 = 32'h3233; + r183 = 32'h3821; + r184 = 32'h5048; + r185 = 32'h1824; + r186 = 32'h61e0; + r187 = 32'h4f33; + r188 = 32'h76c5; + r189 = 32'h2ceb; + r190 = 32'h127f; + r191 = 32'h7103; + r192 = 32'h6d02; + r193 = 32'h6856; + r194 = 32'h58b; + r195 = 32'h59fb; + r196 = 32'h30c3; + r197 = 32'h1397; + r198 = 32'h6cfd; + r199 = 32'h42da; + r200 = 32'h1f39; + r201 = 32'h26f4; + r202 = 32'h5922; + r203 = 32'h2f61; + r204 = 32'h5c44; + r205 = 32'h656; + r206 = 32'h2837; + r207 = 32'h7bc1; + r208 = 32'h7168; + r209 = 32'h7a91; + r210 = 32'h53ca; + r211 = 32'h54c4; + r212 = 32'h6091; + r213 = 32'h7371; + r214 = 32'h37d0; + r215 = 32'h6bd; + r216 = 32'h2687; + r217 = 32'h5e88; + r218 = 32'h2f85; + r219 = 32'h4f31; + r220 = 32'h692f; + r221 = 32'h1eba; + r222 = 32'h2407; + r223 = 32'h1d42; + r224 = 32'h4d87; + r225 = 32'h7085; + r226 = 32'h68b1; + r227 = 32'h6cdf; + r228 = 32'h315f; + r229 = 32'h4711; + r230 = 32'h138; + r231 = 32'h28ad; + r232 = 32'h44d8; + r233 = 32'h6dfb; + r234 = 32'h2d88; + r235 = 32'h3eb4; + r236 = 32'h3f9e; + r237 = 32'h7be1; + r238 = 32'h575c; + r239 = 32'h53ca; + r240 = 32'h2de5; + r241 = 32'h61ad; + r242 = 32'h3d9f; + r243 = 32'h41c0; + r244 = 32'h1124; + r245 = 32'h22a2; + r246 = 32'h7986; + r247 = 32'h4c4e; + r248 = 32'h5094; + r249 = 32'h128; + r250 = 32'h396a; + r251 = 32'h38be; + r252 = 32'h3567; + r253 = 32'h2c57; + r254 = 32'h4d66; + r255 = 32'h345b; + #10; r201 = $stime; + #10; r153 = ( ~ ( r189)); + #10; r200 = (3'h7 !== r2); + #10; r186 = r155; + #10; r208 = (((((( ( + ( (((16'h46d9 || r190) - $time) > (r127 >= (2'h0 !== r81))))) || ( | ( r150))) > r11) !== ((20'h617c * ( & ( r207))) > (r158 && (31'h6f3f - 19'h3eb3)))) * 17'h5321) - 25'h116f) ^ ((((($stime === r219) <= ($stime | (r43 < ((($stime ^ (( ( & ( ( ( & ( 26'h3af4)) | ( | ( 12'h8c7))))) && (r97 | 7'h3)) && 17'h7a8a)) == 9'h84) + ((18'h7e64 >= r240) >= r111))))) ^ 8'ha9) ^ ( - ( r15))) & (( ( & ( $time)) == r235) >= (( ( | ( r90)) || (r56 & r182)) !== r72)))); + #10; r175 = (($time / ((15'h7f3d === ( ( & ( r1)) == r2)) >= ((9'h78 % ( ( ^ ( ( - ( (r164 & (2'h2 >= (((((6'h1f == 28'h4032) / ( | ( 16'h5821))) | 28'h7b43) >= (r191 & $stime)) < ( + ( ((2'h3 % (12'hf20 - 16'h2734)) ? ( + ( (16'h1317 && 31'h16ee))) : (r137 < (6'h27 >= 3'h2)))))))))))) & ((( ( - ( (r169 ? ((r155 != 31'h60f0) >= ((r166 % (15'h587f - 30'h5197)) < r187)) : (((23'h220b <= 20'h46a) & (29'h584 > (10'h17 - 19'h53b7))) != ( & ( ( | ( (9'h1d0 <= 2'h0))))))))) ? r92 : ((($time <= 27'h6600) < (5'h13 ^ r99)) <= ( ! ( (((17'h2640 ? 2'h1 : r189) > $time) >= r248))))) ? (3'h2 - (9'h97 == ( ^ ( 4'h5)))) : ((1'h0 ? ( ( ! ( r34)) && ((r61 >= r73) == ((r184 === (19'h2c6c != 19'h34df)) | ( ~ ( r72))))) : 19'h64ff) >= (( ( ! ( (r24 !== ((7'h2b >= 1'h1) && ( ~ ( 4'he)))))) <= ( ^ ( r86))) / 12'hff3))) % (r35 < ( - ( 13'h8b9)))))) && r67))) - (((8'h12 !== (14'h2d97 <= ((r183 !== (((((r19 | r178) | (32'h743d != (r199 > ((28'h6bbb - 9'hc1) / ( + ( 18'h25d4)))))) | r255) < ( ( | ( (r12 | ((r255 % (30'h5e7b >= 11'h753)) < ( ( ~ ( 29'hc71)) || (20'h1ffc <= 17'h7cc5)))))) !== ((r181 * (((11'h18f || 17'h7265) ? 29'h485f : 4'he) == ( ( ~ ( 14'h1c84)) + 23'h298c))) || (((20'h79b3 ? (25'h1681 * 4'h9) : (12'ha6e * 26'h3ed1)) <= (r84 | (1'h1 % 2'h3))) ^ (r0 < ( ( ! ( 10'h336)) % (10'h149 / 3'h4))))))) || (r184 <= 26'h55e8))) ? 5'h17 : ( & ( (1'h0 >= r248)))))) + r191) | r65)); + #10; r28 = ( ( ! ( ($time <= r162))) !== r91); + #10; r125 = ($stime === ( - ( r231))); + #10; r237 = r93; + #10; r150 = (( ( - ( r183)) & ( ~ ( (23'h3dd8 === $time)))) > r75); + #10; r59 = (23'h7ddf * $stime); + #10; r157 = (3'h4 + (r27 | ( ^ ( (r175 ^ 8'h7b))))); + #10; r65 = r109; + #10; r241 = r88; + #10; r96 = 7'h62; + #10; r229 = (r248 + (r37 >= $time)); + #10; r112 = r160; + #10; r73 = 26'h5f00; + #10; r72 = r17; + #10; r2 = ( ( | ( (r124 + (( ( | ( (7'hf && (r196 ? r84 : ( ( & ( r51)) / r215))))) <= r7) <= ( | ( (r250 + ((20'h6268 % r214) / r19)))))))) * ( ( ! ( ((r249 % ($stime && (r140 * ( - ( ((r104 / 4'h4) <= (( ( + ( r250)) - ( | ( r68))) & ( ~ ( $time))))))))) || (r96 > (23'h4f58 < r185))))) !== 27'h5720)); + #10; r66 = r133; + #10; r199 = ( & ( (r2 % ( ^ ( ( - ( ( - ( r20))))))))); + #10; r47 = r109; + #10; r55 = (r96 / (r204 | ( + ( (((14'h519 / ((32'h2b24 ? ( ( | ( ( ^ ( r184)))) * (r123 < r123)) : ((((((r37 - (5'h13 == 10'h211)) == ( ! ( $time))) * 19'h76aa) >= ( ( | ( r211)) != r116)) ^ ( + ( 10'h25c))) ? (31'h68d3 !== (28'h6b7 ? ((($stime || ( + ( 25'h7c9a))) | (r74 === ( & ( 31'h28e9)))) % ( + ( ((1'h0 && 28'h6335) | ( - ( 13'h130c)))))) : 1'h0)) : ((r115 || ( | ( ( ( ~ ( r133)) && ((23'h30d3 ^ 32'h4295) % (18'h417d >= 22'h51c3)))))) && (((23'h7803 != ( ( ! ( 14'h1906)) ^ (19'h837 > 2'h2))) * (r198 <= (23'h1ee0 <= r55))) >= $stime)))) < ( ( ^ ( ((16'h5ded | (r217 / 17'h171e)) || 1'h0))) > r250))) < (8'h89 && (r15 | ( - ( r224))))) !== (((r244 === (((r229 <= 28'h441b) - ( ( | ( ((r244 - ((29'h24d7 != 17'h334f) == (8'h9f ^ 32'h3180))) ^ ( ^ ( (r238 * (21'h5f35 / 20'h5115))))))) * ( ( + ( ( - ( ( ~ ( (19'h79a9 ^ 24'h5d6a))))))) % r113))) > (((((r92 * (r232 * (22'h261f <= 14'h2bc3))) & (((20'h309a & 22'h7de2) && r181) < ((19'h7534 | 29'h18ae) > r188))) == ((((13'h46f && 25'h1d09) % r161) - ( ^ ( 30'h7cd8))) + ( - ( ((22'h6d8b || 29'h3b) ^ (21'h24f3 > 8'h7f)))))) | (r59 && (r191 >= ( ( & ( (12'h473 & 7'h69))) <= ((30'h162e !== 27'h1a0d) | 18'h5c9a))))) & (r182 - (( ( ~ ( (23'h70cb * (24'h246d > 2'h1)))) - (( ( & ( 26'h6e6c)) == 28'h21af) !== 8'h6f)) % (4'h4 >= r168)))))) != (( ( ~ ( r31)) && ( ( + ( r130)) / r96)) > 19'h1be5)) / ( ~ ( ( + ( ( ( ! ( (((r154 ? (r253 !== ( | ( (1'h0 % 22'h7fd4)))) : ((r133 > (29'h70f ? 6'h3a : 19'hff4)) === 26'h9dd)) <= r109) != 4'h2))) * ( & ( 4'h4))))))))))))); + #10; r70 = r113; + #10; r111 = ( ! ( ( ( ^ ( ( - ( ( | ( ( | ( ((r207 * ((((r224 !== (15'h2f78 < 32'h5844)) > (r246 === ( + ( ( ! ( r150)))))) >= r24) && 2'h1)) * r208))))))))) || ( ( ^ ( ((((r144 % r39) < ( - ( ((9'h103 + ( ( & ( ( ~ ( (r176 || (2'h1 ^ 3'h1)))))) ? $stime : r132)) ^ ( + ( (27'h3a07 ? ( ( ^ ( r12)) && ( ( & ( r164)) - ( + ( (2'h0 > 29'h1ec3))))) : r114))))))) && r126) && ((15'h4051 !== (r0 >= 27'h7733)) ^ (((22'h3da3 | ( ( & ( ( ^ ( r90)))) & 2'h1)) / 2'h1) === (r51 % r189)))))) !== (r252 == 4'h5))))); + #10; r162 = 6'h25; + #10; r183 = ( ( - ( (r110 ? ( ^ ( ( ( + ( ((26'h7b30 != 7'h4c) - r124))) * $time))) : ( + ( (r178 * r22)))))) ^ ((r155 && r52) < (r118 ^ ( ( | ( ( ( ! ( (24'h35fc ^ ((( ( & ( ((r53 - r49) >= 5'ha))) ? r251 : r162) <= 21'h5575) ? (r163 != (( ( ~ ( r203)) - r130) + r153)) : r97)))) == (((r154 | ( ! ( (r105 | r241)))) !== ((18'h6bbe + ( ^ ( (r193 !== ( ^ ( r26)))))) == 6'h1d)) - ((((((((11'h11f || 7'h25) ? r117 : (3'h4 > 19'h2c65)) + ((29'h1842 | 18'h1c77) + ( | ( 13'h19b)))) == $stime) != 11'h491) - 18'h69a8) & (((r206 ? ( - ( (30'hd83 ^ (30'h7ac6 | 2'h2)))) : (((10'h9d && 32'h5721) === $time) !== (r190 === (9'hd9 / 27'h2d)))) && (r232 || (r76 > ( + ( 25'hd8b))))) < $stime)) == r191))))) + $time)))); + #10; r30 = r66; + #10; r60 = (22'h3eec ^ (11'h1dd ^ 9'h113)); + #10; r229 = ( ~ ( 5'hc)); + #10; r180 = ( ^ ( ( & ( r127)))); + #10; r30 = r124; + #10; r149 = ( - ( (30'h743 === ((((((13'hc2 * (( ( & ( 30'h12da)) + 26'h7fc3) + ($stime ? ( ( ~ ( 27'h75f6)) | (r62 !== ( - ( 21'h3b14)))) : r238))) !== (r248 == 30'h7a43)) || 22'hfbe) * $stime) ? r240 : r4) >= (12'hd38 ^ (r147 + ((r36 - 23'h1ed1) ? ((r123 >= ( ( ~ ( (( ( + ( ( ~ ( (15'h32ce / 32'h6ae6))))) | 12'hf22) > $stime))) ? (((r200 == ($stime && r86)) >= (( ( & ( (1'h0 <= 22'h4156))) != 2'h3) === ((r118 && r106) * r249))) || 16'h629a) : (28'h6bec !== r65))) % ((21'h5864 * 2'h0) % $time)) : ((( ( & ( ( ~ ( ( ~ ( (((17'h19fd != 2'h1) > (23'h4f5d & 26'h14e6)) >= ( & ( r236))))))))) === ( ( ^ ( ((r146 && ( ( + ( 26'h40d8)) % (11'h5ba ? 16'h7254 : 32'h7877))) != 22'h3cba))) !== ( ( - ( ( ! ( r162)))) / 2'h3))) != ( ^ ( (r135 & ( ~ ( (((26'hc01 !== r252) || ((4'hd | 8'h62) > ( & ( 16'h4d14)))) == 18'h6094))))))) & (( ( ~ ( r147)) > r72) !== 13'h1f75))))))))); + #10; r173 = 5'h0; + #10; r103 = $time; + #10; r239 = $time; + #10; r23 = r22; + #10; r77 = ((13'h16b3 == ( & ( r9))) / ( - ( ($time && 5'h1c)))); + #10; r132 = ((r22 >= (r212 ^ (((($stime === ((r241 % (( ( | ( ($time % ((11'h4b7 && 2'h3) >= ( ! ( 32'h71f5)))))) - $stime) ? (r98 && 2'h3) : ( ^ ( (21'h384f === 27'h85))))) <= ( ! ( (20'h4d8 <= $time))))) !== (r147 == (r51 / r226))) | r15) / r114))) ? r208 : (( ( ~ ( ( + ( $stime)))) != r7) == ( ( - ( ( ! ( ( ( - ( ( ( & ( ((( ( ~ ( 22'h2cd1)) != (((14'h176d <= 29'h32ef) + (16'h23d1 != 2'h1)) * ((1'h0 ^ 14'hf5b) + r98))) || r212) === (r154 ? 5'h4 : ((((6'h18 !== 4'h7) / (27'h2c4d & 14'h1ea)) > ( | ( $time))) > (( ( + ( 22'h2996)) !== 32'h70cf) && (r135 - r79))))))) | (r98 / r221)))) + ( ^ ( (r198 !== (9'h10d === 7'h11))))))))) - ( ~ ( 30'h1aa4))))); + #10; r43 = (28'h3e31 != ( - ( ((r204 ? ( ~ ( r214)) : r7) && 16'h2745)))); + #10; r161 = ($stime % (( ( | ( (r185 % ( ^ ( r104))))) % ($time * (((r170 | 17'h229d) ? ((($stime >= (23'h16aa & (r64 != ((r100 & (r61 | $stime)) === r136)))) === 27'h349d) ? ((( ( & ( 4'h8)) ? ( + ( r122)) : ( ! ( ( ^ ( r70))))) > ( ~ ( r159))) + r79) : (7'h72 ^ (r55 / ( + ( ( | ( ( ^ ( ( ( ~ ( (23'h7fda + 10'h17))) * ( - ( r1)))))))))))) : ( ! ( ( ( - ( $stime)) % ( ~ ( 5'h2)))))) >= ( ( ^ ( r226)) * r107)))) <= 31'h78c1)); + #10; r132 = ((1'h0 === r227) != 24'h6058); + #10; r128 = 3'h1; + #10; r15 = 19'h5239; + #10; r17 = 15'ha01; + #10; r77 = ((r242 === r221) * (r179 !== r249)); + #10; r87 = (32'h57ec | r63); + #10; r116 = r136; + #10; r20 = r148; + #10; r53 = 30'h6650; + #10; r140 = r198; + #10; r246 = ($stime / ( ( | ( $stime)) / ( ( ! ( ( + ( r215)))) & 20'h3e0e))); + #10; r69 = r246; + #10; r172 = r163; + #10; r94 = r157; + #10; r107 = $stime; + #10; r74 = ( + ( ( - ( $time)))); + #10; r130 = r195; + #10; r197 = (29'ha48 > ((((r121 ^ r165) <= r124) & r226) ^ ((((((r79 * ( ( ~ ( (4'h7 != ( ~ ( r188))))) ^ r70)) & ( ( & ( ((r140 - ( ( ! ( ((32'h6c24 >= 7'h2d) == (2'h1 || 32'h1866)))) || 29'h16f1)) > (2'h1 || ( + ( ($stime == (r68 | 11'h34b)))))))) == r193)) !== r211) | r227) % (r16 == (r10 && (r229 / 4'hc)))) + (r242 ^ r117)))); + #10; r130 = (20'h23ae | 18'h14b8); + #10; r136 = 9'h20; + #10; r249 = 15'h1805; + #10; r224 = 1'h0; + #10; r47 = r200; + #10; r153 = 21'h2587; + #10; r137 = 29'h4926; + #10; r241 = ( | ( (r228 ? ((((27'h60f7 < ( ^ ( ( ( ^ ( ( - ( (r82 / 8'hb9))))) & ( ( ^ ( r124)) >= (r222 ^ (($stime ^ ( & ( ( ! ( 8'h30))))) * r146))))))) == r4) | ($time % (1'h0 / ( | ( (( ( | ( ( ^ ( ((( ( ^ ( 29'h3ca3)) / (8'h37 == 26'h3dbc)) + ((30'h160b >= 23'h7433) ^ r114)) >= (18'h2332 ? (20'h14e1 / (18'h1626 && 28'h64b1)) : r88)))))) < r219) ^ ( ( - ( ( & ( ( + ( ( ( ! ( (25'h7e80 | 5'h14))) > ( - ( (16'h12d2 || 9'h1c2)))))))))) ? $time : $stime))))))) !== r104) : ((((r252 || r121) | ((6'h37 == (((17'h697e === r43) + (18'h44f4 % 5'h1a)) ? r117 : r30)) < $stime)) + ((((r167 ? ( | ( (r87 + ( ! ( (19'h6a46 < r109)))))) : ( ! ( 16'hb75))) == 32'h4122) | r99) / (((15'h25b8 === ( ^ ( r158))) == ( ( ~ ( 23'h693a)) - ( | ( ( ^ ( r249)))))) / (r168 ? ( ( ^ ( r95)) - $time) : r204)))) * (r139 !== 24'h3813))))); + #10; r166 = ( ( - ( ((r111 === r215) && r112))) | ((((($stime != r97) / ((22'h6297 != (((20'h58b | (r76 ? $time : (r57 > (( ( - ( 22'h52e5)) - (14'h105e === 4'hc)) ^ ( & ( (28'h7a38 || 14'h3a92))))))) | (23'h2ee7 / (r70 + r159))) > 17'h862)) >= (24'h4bd6 > $stime))) < (((((22'h38cf * r181) - ( + ( (r36 == r49)))) !== 18'h15e4) & r185) ^ ( ^ ( 19'h2b9c)))) == ( & ( r150))) == ( & ( r137)))); + #10; r236 = ( ( + ( ((((((r148 || ( ( ~ ( ( - ( ( ~ ( r254)))))) != (6'h20 <= r133))) > 26'h163c) !== ( & ( (($time === r13) != 15'h637b)))) === 24'h7118) < ( + ( r42))) / r251))) ? (r43 % (6'h2 === ( + ( r209)))) : ($stime == ( + ( r82)))); + #10; r35 = 32'h194c; + #10; r242 = 12'h485; + #10; r163 = r152; + #10; r143 = (r53 >= ((r240 || 4'h8) / r146)); + #10; r32 = r221; + #10; r161 = (((((r79 || 17'h2a79) % $time) !== ($stime + (9'h164 > (r94 * 18'h8a0)))) | (((r104 ^ ((r190 > r53) + $time)) >= r217) > r32)) - r130); + #10; r10 = ( & ( ((( ( ! ( r18)) > r102) & ((7'h2c > $time) || (r33 < ( ! ( ($stime - (((18'h2403 && (((2'h3 <= 7'h46) & r199) + (r138 == ( ( + ( (25'h643f !== 6'h1))) + r82)))) ^ (( ( + ( ( ! ( ((21'h2864 && 4'h9) || (22'h1c12 == 9'he3)))))) || ( ( - ( ((31'h23bf ^ 11'h44f) !== (21'h2257 || 20'h3d63)))) !== (r128 < ( ! ( (21'h49bf + 25'h936)))))) !== ((($stime ^ ( + ( (7'h52 != 23'h5ce2)))) * ((26'h33f0 | 2'h3) % ( ( ~ ( 24'hafc)) !== r32))) != (r219 == 28'h20f3)))) != r20))))))) | 16'h3a6a))); + #10; r15 = (24'h31d2 != r30); + #10; r210 = (r97 | ((8'h4 || r34) ^ (r72 == 11'h724))); + #10; r214 = ((((( ( ~ ( ( ( & ( 23'h74ba)) > (r92 + (r77 + 4'h1))))) == r26) || ($time != ((12'heb1 < ( ^ ( ((17'h21be - ($stime >= ((r174 - r230) >= (((30'h1aa7 % 29'h622f) + ( ! ( 12'h297))) ^ (15'h4020 && r79))))) === r159)))) != $time))) * ((((13'h836 ^ ( ( | ( ((r120 && ( + ( ( + ( ((8'he + 30'h2a02) !== r44)))))) % 27'h4d2c))) | ( & ( (r238 | r214))))) !== (26'h327a != (4'h5 === ( ( ! ( ( & ( ( & ( (((13'h1896 & 22'h33) % ( + ( 29'h63e4))) + r148))))))) == $time)))) / r173) / ( - ( r12)))) / r109) && (23'h44f8 > ( ( ! ( $time)) + r205))); + #10; r182 = ( ( ~ ( 28'h4852)) === 11'h1d2); + #10; r11 = ( ^ ( ( ! ( (r142 && ( & ( ((r127 <= r51) - 32'h6ebd)))))))); + #10; r221 = 9'h20; + #10; r97 = ($time + (11'he8 != (( ( ! ( ($time ^ 2'h3))) % (((r175 - (31'h5de9 + 2'h2)) / r70) <= r189)) % ( ( | ( ((r1 || ( ( & ( (5'h11 >= ((7'h3c <= r198) > 16'h5796)))) | 28'h32a)) ^ ((r221 & (($time ^ ((((r220 % (20'h6874 + 4'h0)) !== r219) + 14'h1bd8) / 30'h7574)) + r251)) < (19'h11a4 > r61))))) === ( - ( (((r253 + 30'h72b5) < r68) && (((15'h6bf0 > r153) < $stime) !== 6'h20)))))))); + #10; r205 = (((24'h1906 != (( ( ~ ( ( | ( ( - ( $stime)))))) == r74) / 18'h6640)) === r94) + (((27'h1683 == (14'h13fa < ( & ( r72)))) > r48) * (((((r173 == (4'hd | ((13'ha23 && 1'h1) <= ( ! ( (9'h1ea ? ( ~ ( 16'h4ec3)) : ( ( ! ( ( ~ ( (27'h3b76 == 18'h6606))))) * ( ( - ( (23'h3f36 ^ 27'h1521))) % r231)))))))) & ( ( - ( 14'he7b)) <= ( | ( ( - ( 12'h1d)))))) + r168) <= r217) >= $stime))); + #10; r231 = (r213 | (((30'h7dd6 && r127) == (r109 | 29'h1794)) != r130)); + #10; r150 = ( - ( $stime)); + #10; r116 = (r139 > (( ( | ( r219)) <= (29'h25ec && ( ! ( 4'h9)))) / ( ( ~ ( r79)) > (r25 ^ 1'h1)))); + #10; r56 = 24'h6d7b; + #10; r214 = ( ! ( ( + ( r90)))); + #10; r207 = 19'h5602; + #10; r116 = ( ( + ( r130)) <= ( ( ^ ( 6'ha)) < r200)); + #10; r220 = (((15'h5ceb + 6'h25) === ( ~ ( 11'h1dd))) < r161); + #10; r10 = r63; + #10; r63 = $time; + #10; r214 = r201; + #10; r225 = $stime; + #10; r58 = r103; + #10; r78 = ( ( ! ( ( ! ( r28)))) <= ( ( & ( ( ~ ( ( - ( (r165 && r66))))))) >= ( ~ ( 6'hd)))); + #10; r243 = 1'h0; + #10; r25 = ((((21'h9f5 == ((((r24 >= r227) || ( ^ ( (r63 === ( & ( (r92 >= 21'hc2d))))))) < (32'h71e6 % r124)) - 25'h51f4)) && ( ~ ( 5'h17))) != ((r138 || (8'h91 === ( & ( (( ( | ( ( | ( r186)))) | r196) !== r186))))) && r103)) + 12'h5cf); + #10; r175 = (r171 * r99); + #10; r193 = ( ~ ( 29'h5007)); + #10; r141 = r64; + #10; r22 = (5'h11 + ( - ( ((26'h2b69 ^ $stime) <= (((r129 < (((( ( ! ( 7'h23)) + (4'h5 === (6'h35 >= 24'h20d7))) || (( ( & ( r226)) & (16'h6572 >= (r173 ^ 18'h2888))) - $stime)) ? $stime : 15'hb3d) * ( ! ( ( | ( r3)))))) < (( ( & ( ((( ( - ( ( ( ~ ( r109)) % ( ^ ( ( + ( 2'h3))))))) >= ($stime < r136)) ? 7'h5b : ( & ( ( & ( (((18'h71e * 8'haa) <= (22'h651b - 26'h499e)) | r83)))))) === r134))) == (((20'h65de & (r227 % 7'h63)) > ( + ( r213))) >= ((9'h18b == 16'h7f14) && ((( ( | ( r78)) < ( ( ~ ( (27'h3ae8 + 31'h566b))) + ($stime >= (16'h55d9 % 17'h7bb4)))) < 28'h3f8b) <= ((r132 != (( ( ^ ( 29'h5761)) ? (6'h5 != 3'h5) : r21) !== r23)) === (2'h0 === r235)))))) == (r49 && ( ! ( 9'h11a))))) < r188))))); + #10; r49 = ( ^ ( (((((25'h4e96 === r46) && r73) > ( ^ ( ( | ( ( ( | ( 10'h1b2)) & ((r159 - ( ( & ( r109)) / $time)) >= 14'h1323))))))) - r165) % (r28 > r247)))); + #10; r4 = 30'h3703; + #10; r165 = r95; + #10; r39 = ( + ( (r224 == r178))); + #10; r248 = $stime; + #10; r209 = ((12'h657 | ($stime ^ ( ^ ( (r198 != ((22'h1825 + r140) === 26'h5d53)))))) == ( ~ ( (( ( & ( ((r21 % (($time | ( ( ! ( (r6 == (((21'h2c09 == 3'h5) == (4'h7 ? 18'h3c25 : 25'h3224)) !== (r13 !== (16'h68df <= 20'haf4)))))) % 9'hc5)) >= $time)) ? 8'hef : (r247 & (r180 ^ ((((16'h31e9 - ($stime & 10'h1bc)) && (18'h7f94 | ($time ? r16 : ((5'hb ? 29'h7896 : 19'h5aba) ^ (19'h52e0 === 1'h0))))) == (((24'h201f !== ( | ( ( ! ( 5'h1f))))) || ( ~ ( ( ~ ( r100))))) / ((r60 ? (r99 || (9'h6 ? 10'h2fe : 27'h72e7)) : (r234 <= (11'h74b % 30'h6ba6))) > ( & ( ((29'h4113 !== 29'h4226) && (5'h1e > 15'h3bb0))))))) != ( ( + ( ((1'h1 - 1'h1) >= (r31 * ($time ? 22'h7283 : (10'h25c == 1'h0)))))) & (r57 === (9'h1e9 < r56))))))))) >= 7'h17) != r163)))); + #10; r1 = (r78 % r79); + #10; r101 = ( ( ! ( (((r143 - 30'h78e0) / (14'h1c2e - (((( ( ~ ( 27'h5102)) !== 23'h5656) * ( + ( (r127 >= (((((31'h4150 == 9'h7f) ? (21'h40b0 >= 1'h1) : 20'h7e04) >= ( | ( 31'h6fed))) ? ( ( + ( r11)) && (15'h1543 && (8'h45 < 24'h382b))) : r189) > (r201 <= r171)))))) && ($stime > r42)) && ( & ( 14'h39ec))))) == r110))) === ((($time / ( - ( ( ! ( ( + ( 1'h1))))))) & r199) !== 12'h112)); + #10; r111 = $time; + #10; r58 = r34; + #10; r1 = (21'h4628 & (r206 >= r167)); + #10; r130 = (( ( ^ ( r212)) + r148) !== ((r51 !== ( + ( ( ~ ( ((8'h68 == $stime) > ( & ( $time)))))))) || 6'h0)); + #10; r12 = (( ( & ( ( ( - ( (((r233 && (r155 || r64)) > (r224 != ((19'h1e80 * (24'h7122 & ( ( ! ( r79)) | (r81 >= r68)))) != 11'h3de))) ? ((r139 > (21'h58b4 < (($time - ($time | 1'h0)) === (((14'hf05 | 9'h90) ? (r180 - ( - ( ( ~ ( 4'h3))))) : ( - ( 12'h8e9))) >= ((9'h195 > ((13'h19a8 < 23'h5a73) && 7'h21)) && $stime))))) ^ r46) : ((r171 !== ((((9'h120 != (2'h0 % ( + ( r237)))) & ( ! ( 3'h6))) || (( ( & ( (31'h7 || 23'h777a))) !== ( - ( (r102 + (1'h0 + 26'h4b6a))))) & $time)) * r78)) !== ( ^ ( $stime)))))) != 13'haee))) ? r59 : (29'h3976 / r181)) % r221); + #10; r246 = r187; + #10; r122 = 32'h7516; + #10; r63 = r192; + #10; r68 = 21'h5966; + #10; r221 = (( ( - ( (r154 === 2'h3))) && ( ( ~ ( ( - ( $stime)))) > $stime)) ^ ((27'h464f <= r132) < 24'h4012)); + #10; r179 = r107; + #10; r15 = 26'h1958; + #10; r27 = (r197 != r242); + #10; r251 = (2'h1 <= 7'h69); + #10; r252 = (r50 <= r231); + #10; r228 = r192; + #10; r181 = r218; + #10; r129 = ((r187 & (($time || (r85 > ( ~ ( r13)))) > 32'h2b02)) | ($stime !== ( ( ^ ( r164)) + ( ^ ( ( & ( ((((((( ( - ( 9'h133)) - r240) && 10'h1e0) <= 12'h481) >= ( ( ~ ( (r78 !== (r132 | r63)))) % ( + ( ( - ( ((r159 & ( & ( 29'h376e))) >= ((1'h1 || 30'h4e92) && (19'h1691 & 26'h2629))))))))) * (r200 == ((r202 > (((r83 % (14'h2086 == 12'h1ca)) > ( & ( r246))) <= (((6'h7 + 23'h27fb) ? (1'h0 !== 15'h3dbc) : $time) - (r117 <= (9'hcb != 19'h31ef))))) ? 2'h0 : ( ( - ( 8'hb7)) || r65)))) ? ((r92 != ( ( - ( ( ( ! ( 25'hc76)) && 17'h27e3))) >= ($time == (r196 ? (((19'h842 != 17'h44a4) && ( ^ ( 3'h3))) / r124) : 1'h1)))) * ( ^ ( r17))) : (10'h300 <= (($time | (r161 !== $time)) - r55))) & ( + ( ( + ( $time)))))))))))); + #10; r69 = (( ( ! ( r209)) != 27'h73e0) / 30'h5ff5); + #10; r36 = ( ^ ( (($stime % 22'h7f73) / ( ! ( (r60 / r187)))))); + #10; r195 = r61; + #10; r148 = ( ! ( ((r1 != r174) & r111))); + #10; r61 = r232; + #10; r86 = (11'h627 / (( ( | ( r110)) < ( ^ ( 25'he53))) > (((( ( & ( (20'h1ed3 - 4'h9))) < ( ^ ( ( & ( 15'h48a3))))) | ((r73 % r163) && (((($stime !== ((r195 || ((18'h61d8 | (2'h2 + 32'h6491)) ? ((9'h1bd & 21'hdab) * (16'h597b == 5'h15)) : 27'h1e00)) & r87)) ? ((16'h6477 | r71) > ( ( ! ( 17'h49a5)) == r179)) : (( ( - ( ( ( ! ( ( & ( 26'h2396)))) + (19'h3d37 & (30'h1edf === 18'h2788))))) && (((r165 != 14'h13b0) ? r203 : $time) >= (r242 + r68))) <= r147)) ? ( ~ ( $time)) : (r189 + r151)) >= 8'h98))) === 25'h4203) ? $time : ((29'h133a ^ ( - ( (r137 !== 6'h1d)))) || ((( ( + ( r50)) || ((r216 === 32'h7fe7) >= (9'h13d >= r229))) && ( + ( 19'h2336))) & r246))))); + #10; r19 = (r85 | (24'h5e3d ^ ( ^ ( (r246 == (18'h6068 & ( & ( r152)))))))); + #10; r4 = ( + ( $time)); + #10; r152 = ((( ( - ( r140)) | ((1'h0 ? (1'h1 && r199) : (( ( + ( r212)) == r72) * ((r4 !== 5'h3) > (($stime >= 31'h742c) <= (13'h131c < r213))))) > (r246 || ((r116 < (((r189 < ( & ( ($stime === ( ( ^ ( r100)) | r189))))) !== ((r96 | ( ( ^ ( (r40 & r20))) * r167)) - (((r219 || 5'ha) === r185) != 20'h34fd))) | 17'h2d95)) + (( ( + ( (r114 % 25'hab5))) <= (( ( | ( r206)) || ( & ( ((18'h2670 & ( + ( ( & ( 14'h24d9))))) ? (14'h3df < (r253 | 19'h514e)) : (r5 * ((29'h88e != 15'h202c) <= (25'h7dd4 || 21'h4915))))))) === 7'h7d)) === 32'h2450))))) / r139) >= ( ^ ( ( ( ^ ( ( | ( 31'hc9a)))) >= 27'h5ce1)))); + #10; r83 = r149; + #10; r106 = (((r142 + (18'hff6 - r189)) ? ( & ( (r109 && 30'hb4f))) : ( - ( ( | ( ( | ( r115))))))) <= r180); + #10; r227 = ( ! ( ( ! ( ($stime / ((r194 * 26'h6311) === ((r105 % r76) != ((r79 != (1'h0 || (((2'h3 >= ( ^ ( 4'h4))) - 23'h5b50) > r48))) ^ 27'h702)))))))); + #10; r38 = r32; + #10; r177 = (r151 ^ ( & ( r53))); + #10; r132 = r245; + #10; r135 = ( + ( (r141 - ((r169 != r178) !== ( | ( (r241 != ( & ( ((r102 & ( ~ ( ( ! ( r18))))) ^ r25)))))))))); + #10; r121 = ( | ( 18'h61eb)); + #10; r253 = (((r123 >= 13'h18f9) & 26'h1e42) === ( + ( (r185 < r245)))); + #10; r58 = r52; + #10; r1 = (( ( - ( 21'h3df1)) === r43) && r195); + #10; r180 = ( ( | ( ( + ( 23'h51f6)))) | $time); + #10; r147 = r50; + #10; r212 = (r48 / ( | ( ( ( - ( ( & ( (r78 & r199))))) ^ (((r190 != ( & ( (r11 * (( ( - ( (($stime <= ((5'hd ? 11'h55e : 21'h7496) === (6'h23 % 15'h406b))) || r52))) / $time) > 18'h68f1))))) - ((($stime == r49) & r191) > (( ( ^ ( (13'h11e6 - 2'h0))) === (((8'h77 > ((( ( & ( 18'h6c31)) + r247) + (r154 < ( ! ( 15'h2dda)))) >= ( ( - ( $time)) ^ ((4'h0 * 19'h3e9c) | r11)))) != (r70 != ((((18'h2d84 != 2'h3) != r202) / ((29'hf27 !== 29'h5512) + r43)) !== (18'h1db < ( & ( r221)))))) / r255)) || ( + ( (r32 + (r106 - r168))))))) || $time))))); + #10; r140 = (r210 - ((((r91 >= 25'h6118) & r15) >= $time) - (((((23'h4c9c ? r228 : ( ( + ( 27'h4433)) == (r117 == ((($stime | (($stime | ( & ( 23'h52a9))) === (r138 || r157))) === r106) * (r190 != $stime))))) | ( + ( r200))) - 28'h7a48) === 12'h1be) / ((r45 - ($stime + 4'h2)) != (( ( + ( (27'h7bf7 | (((27'h1e92 % 5'h17) ? 17'h4f68 : r240) >= ( + ( ( ( & ( ( - ( ((27'h6ca1 | 4'h5) ? (1'h0 ? 15'h551a : 19'h3554) : (2'h1 ^ 24'h62bd)))))) > ( ~ ( r248))))))))) ^ r123) * r183))))); + #10; r116 = ((($time * (7'hd !== $stime)) >= 12'h528) + 2'h2); + #10; r16 = r182; + #10; r188 = ( - ( 15'haa4)); + #10; r235 = ($stime ? ( ~ ( (30'h4340 > $stime))) : r134); + #10; r206 = (21'h355e && 16'h3c42); + #10; r32 = ( - ( (22'h3162 < ((r236 === 17'h4e9f) != ( ~ ( r231)))))); + #10; r2 = 4'h4; + #10; r227 = ( - ( ( ~ ( r70)))); + #10; r123 = r227; + #10; r52 = 11'h62c; + #10; r187 = ( & ( (28'h554a !== r129))); + #10; r15 = ( ! ( ( - ( ((14'h23b | ((24'h5d96 < ( ( ^ ( r81)) % ((26'h13a2 - (((10'h2d4 <= (((7'h1d < 23'h784b) <= 2'h0) <= r41)) % ( ( - ( r76)) >= (7'h54 || ((20'h667a * 7'h4a) != (16'h3c25 | 18'h732))))) ? (r125 ? ( ( ^ ( (r6 == (32'h1414 + 30'h61ef)))) & (r75 != 27'h17c1)) : (r157 - ($stime / ( ( ^ ( 1'h1)) ? ( ! ( 22'h5660)) : r112)))) : (r244 & ((1'h0 >= r112) === ((r203 >= r3) + ( ( | ( 12'h2a8)) < (30'h838 + 17'hb72))))))) - r84))) | ( ( ^ ( ((23'h151 / ( ( ~ ( ( ( ^ ( ((6'h29 - 11'h624) % $stime))) + ( ! ( ((32'h5711 ? 3'h6 : 28'h4941) % (19'haad === 12'h299))))))) + 14'h340c)) ^ 12'he4f))) !== r64))) | (( ( | ( ( ( ! ( ( ( & ( ( ( | ( ( | ( 9'h1a2)))) / ( ^ ( (11'h15b ? (r141 == $time) : ( | ( r242)))))))) == (24'h338 == r170)))) !== 20'h28f8))) <= (((r75 >= ( ~ ( ((( ( & ( 16'h5800)) && ( ~ ( r186))) & ((r215 / r60) <= (((32'h1ce6 | 15'h3e47) <= (1'h0 <= 29'h3f9c)) !== ((23'h5d5d <= 23'ha77) | (9'h20 < 22'h43a4))))) % ((9'h39 + r179) || r82))))) - ( ~ ( r243))) > $stime)) ? ((r105 > (r217 + 27'h2e68)) ? r223 : r81) : r31)))))); + #10; r228 = r194; + #10; r187 = 7'h29; + #10; r109 = ( ( ^ ( ((13'h1f6 >= r210) + r112))) > r235); + #10; r121 = 13'h5bb; + #10; r213 = ((r30 * 18'h2845) === ( ! ( r237))); + #10; r180 = ((r241 | (((r106 - (( ( + ( ( ~ ( ( + ( 28'he39)))))) !== ( - ( (($stime | ($stime != (((r139 % r97) !== r94) >= r251))) ^ r45)))) | r97)) === (r79 < ((r109 * 2'h0) !== ( & ( 27'h3293))))) / (((r238 + 15'h60cb) == ((( ( + ( ( | ( r65)))) <= ( & ( 29'h7fa4))) > (($stime | (((r24 < ( - ( 10'h116))) % ((($stime >= (14'h2dac | 4'h2)) / (5'h1 && (11'h68e != 12'hfd))) | r57)) - r252)) ? 30'h2533 : r239)) < r117)) === r175))) % 25'h5022); + #10; r7 = (( ( | ( (15'h7910 && ( & ( (r66 <= r105)))))) < (29'h6770 % ( ^ ( r24)))) + (r27 - (($time * (( ( ~ ( ( ( & ( r72)) || ( ~ ( ((16'h613e ? (6'h18 + r105) : ((r58 ^ ( ( - ( 1'h0)) > (15'hd9d | 12'h8d8))) > ($time === r11))) + ((r60 + r170) >= (30'h109b ^ ( - ( ( + ( (19'h3346 ? 12'hf5 : 21'h2119))))))))))))) < 5'hf) - $time)) !== ( ~ ( ((r246 >= (((r90 - 14'h34ad) != ( | ( 25'h6134))) && ( ( ! ( ( ( | ( ( | ( (r152 | r232))))) | ( ~ ( (r196 || r35)))))) || ( - ( ( & ( ((r73 >= ( & ( $time))) || ( - ( (23'h1d25 !== ( + ( (20'h672d === 24'h194b)))))))))))))) == ( ( & ( r34)) !== (r30 / ( & ( (( ( ^ ( 17'h6d41)) ? ( + ( ( ~ ( (11'h77f || ((1'h0 - 31'h185d) == (28'h1b96 ^ 15'h2a2a))))))) : $stime) != ((19'h7835 == ( ! ( 32'h4eb6))) || ( ! ( (( ( ^ ( $time)) ^ ( + ( (16'h1f16 + 22'h17f)))) == r118))))))))))))))); + #10; r21 = 24'h1fe8; + #10; r145 = (( ( - ( 17'h64a4)) !== ((r131 > (r109 | ( ( ~ ( 14'hd50)) + (r228 !== (( ( ~ ( ((29'hc3f - (( ( | ( 27'h6286)) <= 18'h6b93) === 31'h2432)) && ($stime || ( ( | ( 23'h35a)) <= 32'h496))))) && r113) == r175))))) <= r252)) && r171); + #10; r210 = ( - ( (r171 != (r235 > r32)))); + #10; r212 = ( & ( ( ~ ( ((r90 != r45) & 11'h491))))); + #10; r158 = ( - ( 14'h3cb)); + #10; r152 = (r137 == ( & ( ( + ( ( ~ ( 18'h3802))))))); + #10; r152 = r114; + #10; r28 = (r72 % r210); + #10; r69 = ( & ( ( ( - ( ( ~ ( (( ( ^ ( (((((22'h7b4e < ( ( & ( (7'hb > 31'h50d8))) ^ (4'hb / (17'h3b5d == 7'hf)))) & r220) % (8'h4e < ( ! ( 18'h2d17)))) - r130) * (16'h4fd5 * ((( ( ^ ( 24'h716d)) && ( ! ( r221))) >= $stime) == (31'h4a6f > ((r24 & ( ( ^ ( 30'h309)) <= (29'h475 == 28'h2d97))) >= ( & ( ((30'h151f <= 22'h6762) * 17'h646b)))))))))) - ( ( | ( r45)) * r211)) == ((r114 / $stime) === (21'h2915 != ( ~ ( ( ! ( $time))))))))))) == ((r197 || 27'h73e0) <= 14'h3d7)))); + #10; r60 = (( ( | ( r187)) == ( ( - ( r55)) + (((11'h335 > (r232 != r5)) == (r89 ? ( ( | ( $time)) !== r6) : ((22'h6cc5 && (9'h161 <= $stime)) <= $stime))) <= r123))) / (((( ( ~ ( $stime)) >= ( | ( r221))) < ( - ( r115))) !== ( ( ! ( (( ( ^ ( (( ( & ( r95)) + (13'h49d < ( | ( 18'h1a82)))) !== ((r78 != (r34 >= ( ( ! ( (14'h588 | 16'h507))) && (1'h1 > 12'hbfd)))) && (r91 + r249))))) !== ( ^ ( ( ( | ( r205)) == r71)))) == 15'h113d))) === 32'h60ad)) / ( + ( ( - ( 15'h7b84)))))); + #10; r213 = ( ( + ( 3'h0)) / (8'hc6 < r26)); + #10; r27 = 19'h54d6; + #10; r235 = (10'h2ce || (14'h18b5 * ((($stime & ( ( ~ ( ( ^ ( (((((r39 ? ($stime % 7'h68) : ( ( ^ ( 7'h38)) || (14'h99b % 24'h613f))) != (r116 < r163)) | r154) ? ( - ( 22'h2d1e)) : 12'hf49) - ((((((19'hee0 + 25'h4274) === r189) + 21'h1c66) * 25'h2b72) && ( ~ ( (( ( ~ ( 18'h4339)) & 6'h3e) % ( + ( (10'h218 | 19'h4ea1))))))) == ( ( - ( r117)) | ( ( | ( r118)) | (r63 !== ( + ( ( ~ ( 27'h3763))))))))))))) < r82)) & r142) == ( + ( (23'h74ab && ( ~ ( r108)))))))); + #10; r3 = 24'h3a7b; + #10; r60 = ( ( ! ( 22'h5ca)) | ( ! ( (r38 / (r0 ^ ((30'h7151 ^ ( ( + ( 1'h0)) ^ (4'hc || (r49 > (14'h1287 % ( | ( (3'h2 !== (((26'h1516 != 4'ha) + 19'h7343) < (r225 * ( & ( 27'h380d)))))))))))) < r55)))))); + #10; r209 = $stime; + #10; r88 = 30'h47b0; + #10; r190 = ( ( - ( r25)) != (r230 % r145)); + #10; r242 = (((r31 ^ r98) ^ (( ( | ( r110)) < ((( ( - ( ((( ( | ( (r147 != r193))) | 15'h2197) && ( ~ ( ((((9'h1b / 3'h6) - (16'h66b5 !== 13'h15aa)) <= (r188 || (24'h1e3f >= 30'h41da))) <= (r181 / ((11'h317 - 30'h7563) <= (32'h1a3a && 8'h20))))))) * $stime))) ? ( & ( ( & ( 21'h5bc5)))) : (3'h2 - 10'h332)) % r29) <= r182)) == r131)) ^ (24'h3d27 && (28'h3b13 !== 20'h1322))); + #10; r227 = 23'h11c3; + #10; r242 = ((21'h5910 == (19'h6d6f - ( ! ( ( | ( r100)))))) <= ( + ( (r208 - ( ( ^ ( ( & ( ( ~ ( r170)))))) / (((r216 && r115) != (r68 ? (1'h1 * r149) : 2'h3)) && r233)))))); + #10; r178 = r186; + #10; r44 = ( ( - ( r213)) && ((r59 % r72) / r65)); + #10; r26 = ( - ( r97)); + #10; r120 = $time; + #10; r251 = r73; + #10; r78 = 25'h4661; + #10; r105 = ((27'h3d8e | r115) || 19'h65b7); + #10; r212 = (11'h727 > r67); + #10; r198 = r128; + #10; r59 = ( + ( r140)); + #10; r125 = 19'h6ff4; + #10; r99 = ( ( + ( r41)) === 30'h295e); + #10; r197 = r17; + #10; r5 = (r172 === r139); + #10; r252 = (((17'h64d7 ^ 4'hd) + ( ( | ( ((13'h19cb && r127) % ( + ( (25'h69d4 >= ( + ( 17'h956)))))))) > (((( ( ~ ( 18'h5835)) | ((((r63 | 22'h33eb) < 19'h7c40) | 22'h1c7e) % ( ( - ( (r77 >= ($stime ? 21'h1762 : (((4'ha > 14'h2fb0) < 16'h2d72) | ( - ( ( ! ( 32'h2f02))))))))) + ( + ( ( ( ~ ( (r60 ? $time : r244))) >= 28'h67c5)))))) <= (r106 & 32'h28a6)) != r242) / 6'h39))) == ( & ( 9'h1e2))); + #10; r58 = r119; + #10; r102 = 17'h597e; + #10; r148 = r206; + #10; r22 = (r194 ^ ( | ( 26'h249c))); + #10; r133 = (((r34 | (20'h12d2 === r166)) != ($stime !== ( ^ ( (($time == r53) == ( - ( 4'h6))))))) !== ( ~ ( 5'h13))); + #10; r182 = r102; + #10; r165 = ((r60 / r30) % r33); + #10; r20 = ( ( + ( r17)) != r90); + #10; r102 = (((r105 - (20'h3e12 < 24'h5669)) > (((21'h12ed != ( ( | ( (r82 > ( ( ! ( ( & ( (r187 < ( + ( ((12'haa1 === 4'h8) + (32'h2954 % 11'h3be))))))))) + (21'h74de * 3'h4))))) - ( ~ ( 16'h6332)))) / ((r178 || ( - ( 30'h6f10))) | 31'h5072)) ? ( ( ~ ( (( ( ~ ( (r197 >= $time))) >= r254) > (r51 ^ 5'h5)))) !== ((((r82 > ((r40 != (r68 < ((((23'ha77 * 20'h39dc) * (31'h87c / 16'h5e84)) | (32'h666b % (13'haac >= 31'h757c))) === 6'h5))) || (r254 <= ((((7'h3c / r179) + r196) != r61) !== ((11'h27e - r0) <= (($stime >= r0) / 15'h2676)))))) !== r49) * ( - ( ((r106 && ( ~ ( 23'h50ed))) >= (11'h77e < ( ^ ( ( ~ ( 2'h1))))))))) !== $time)) : ((r242 >= ($time !== (r169 > (18'h129 == 32'h4fe8)))) < ( & ( (((32'h925 || r56) ? r180 : 18'h5ecc) === (( ( - ( 14'h23fa)) & (r203 == ( | ( (17'h78cf <= ( - ( (r223 | ((1'h1 < 14'h251f) ? 5'h1c : (28'h52ce >= 27'h1c52)))))))))) - r233))))))) <= (( ( ~ ( ( ^ ( ($stime / r49))))) + r27) !== $time)); + #10; r21 = ((r8 ? 2'h1 : (( ( ~ ( (r82 + $time))) < r44) | r98)) / r188); + #10; r4 = r126; + #10; r91 = 11'h2c3; + #10; r113 = 18'h3ed2; + #10; r47 = r29; + #10; r128 = ( ( | ( 9'h35)) ^ 27'h35ad); + #10; r120 = r110; + #10; r54 = ((r68 !== ( ! ( r28))) == (25'h571a & ( ( - ( ((r161 & 23'h6f59) !== ((r150 || 18'h6a2f) | 5'h19)))) || ( ~ ( ( ~ ( ( ( ~ ( $stime)) ^ r68)))))))); + #10; r246 = ((23'h18f0 ^ r230) + ((((18'h4781 ^ r148) > (((r247 - 2'h3) == $stime) >= ((((r170 || (r209 !== ((6'h18 % r248) === r170))) > r2) || ((((4'h5 + ((( ( + ( 4'h9)) & (31'h206f <= 32'h74e0)) <= ($time / (12'ha4e !== 12'h1b8))) > $stime)) === ($time > (((r98 <= r156) | r171) || ( - ( ((2'h0 > 29'h52a5) - r155)))))) & (r80 ^ $stime)) == r118)) == ((r122 % ( ( ^ ( 9'h61)) === ( ^ ( ( & ( r57)))))) ^ ((((r168 || ((r149 > (r65 - ( | ( 16'h3096)))) >= $stime)) < ( | ( (20'h30d5 - r250)))) != (((( ( | ( 8'h72)) ^ r193) < ( & ( (17'h13cf ^ (18'h57e0 <= 5'h1d))))) * r163) * (9'h1ff === ($time | 29'h1f07)))) > ($stime || ( | ( ( ^ ( ($stime > (r182 >= $time)))))))))))) === ((32'h7235 + ( + ( r63))) != (25'h5617 !== r193))) > (26'h3b84 <= r37))); + #10; r61 = ((( ( + ( ( - ( ( | ( (9'h123 < ((((r131 == $stime) !== r221) ^ $time) >= (26'h7d2b && (16'h4c88 === 28'h630e)))))))))) / (29'h2ad5 <= ( + ( ((r198 * ((r25 * (r33 + 4'h9)) <= r172)) != ((r173 >= 27'h16a3) < (r24 != 10'h27d))))))) & ($time / ($stime && ( + ( (23'h2212 ? (r86 <= ( ^ ( (10'h2f2 > (r126 / 30'hc28))))) : (r16 | ( - ( ( + ( (r0 <= (((14'h3e2f <= r129) < r115) !== ( - ( r156))))))))))))))) || 20'h118); + #10; r132 = ( ^ ( r44)); + #10; r100 = (r14 == ( | ( ((r236 != r163) & $stime)))); + #10; r46 = (30'hc90 - r136); + #10; r99 = (r38 + (r75 && ( ^ ( 1'h1)))); + #10; r110 = ((5'h1c + 12'hd0d) ? (( ( ! ( r29)) | ( ~ ( (5'h4 < (8'h1a != 9'h11))))) == r103) : ( & ( ((((r69 & ( & ( ( & ( r222))))) % ((6'h39 < ( + ( 10'hd3))) === r11)) ? (r252 === 6'h25) : ( ^ ( (( ( ! ( 20'h774a)) | 30'h2641) | ( | ( (((5'h4 !== r29) == ((r204 ^ r33) || 14'h465)) > (r161 <= r169)))))))) >= r231)))); + #10; r227 = (r186 ^ (($stime / ( - ( ((((30'h5a52 != (( ( ! ( 8'h49)) === (r202 | 8'h31)) == r148)) <= ( - ( (11'h388 & 11'h6fb)))) === r104) < r226)))) + 1'h1)); + #10; r62 = 19'h4ab; + #10; r231 = r234; + #10; r111 = (r230 * $time); + #10; r25 = $time; + #10; r186 = ( ( ! ( ( | ( $time)))) ^ r243); + #10; r235 = r235; + #10; r38 = ( & ( (( ( ! ( ( ! ( 15'h298c)))) / (((r103 % (5'ha >= r102)) ^ 16'h6162) / 24'h2416)) < ( ( - ( r135)) && ( & ( r148)))))); + #10; r49 = ((( ( ~ ( $time)) < (r116 % 23'h2cb1)) > (20'h4454 ? ( | ( (21'h198e | $stime))) : r116)) ^ (r55 ? r252 : ( ! ( (r154 ? ( ^ ( 16'h6adc)) : (23'h284 > (( ( - ( ( - ( 27'h2f79)))) <= r130) <= (( ( | ( ( ~ ( $stime)))) !== ((r25 ^ r1) === r199)) !== ($stime > ( ( & ( 23'h2b4)) < (r247 || 10'h190))))))))))); + #10; r169 = (((r12 | r195) > $stime) * ( ( + ( ( - ( (r20 >= (13'h508 === 18'h11fc)))))) || ( ! ( 18'h2923)))); + #10; r199 = $time; + #10; r224 = ( ~ ( ((23'h4d5 & r216) && r228))); + #10; r46 = 23'h79a5; + #10; r94 = 6'h1e; + #10; r46 = r181; + #10; r103 = (( ( ~ ( (((8'he6 - r129) < ((r204 + (10'h139 % r112)) < r75)) | ((r96 >= 25'h4652) != (r216 * r46))))) > ( ! ( ((20'h7cc1 < 19'h1460) || r74)))) & r190); + #10; r61 = ( ( & ( (r33 < (r53 <= r38)))) !== r135); + #10; r12 = ( + ( (( ( ! ( $stime)) || 3'h7) + (( ( ~ ( (3'h4 + ((r189 ? (30'hc61 > ( - ( (7'h21 ? ((((29'h5467 | 3'h2) || (31'h2f57 >= 11'h760)) ^ ((4'h0 & 16'h5c22) * 7'h39)) === ( + ( $time))) : (21'h546f > (1'h1 | ( ( - ( 4'h5)) * ( - ( 26'h144))))))))) : ( ! ( r186))) === r251)))) + r49) | r241)))); + #10; r173 = ( - ( r247)); + #10; r65 = $time; + #10; r57 = 10'h120; + #10; r230 = ( ( ~ ( (r203 * r115))) ? r16 : ( ~ ( ( ^ ( r204))))); + #10; r201 = (r58 <= r7); + #10; r63 = r217; + #10; r93 = (17'h70ab - ( ( ~ ( 5'hd)) ^ (( ( ~ ( ((( ( & ( ((17'h63e4 % ((((19'h70fc * 10'h1fa) === 23'h5ba5) - 25'h830) ^ r254)) - 1'h0))) != ( ^ ( (((( ( - ( r27)) & r177) % r226) / 8'h24) * r209)))) | 30'h1439) != 22'h7b4b))) / (r51 + r174)) <= ( + ( r65))))); + #10; r243 = 8'heb; + #10; r97 = ( ( & ( ((r126 % 15'h4856) < ( + ( r14))))) !== r25); + #10; r233 = 18'h5ffb; + #10; r157 = (r172 >= 29'h2fdf); + #10; r22 = ( | ( 5'hd)); + #10; r231 = r89; + #10; r144 = 26'hd4f; + #10; r83 = $stime; + #10; r108 = 12'hbe2; + #10; r45 = (r215 === (( ( + ( 30'h2e06)) <= r205) == (( ( | ( r142)) !== 13'h1108) == ( ( - ( ( ^ ( r253)))) == 31'h19c2)))); + #10; r22 = r84; + #10; r251 = ((( ( & ( ( ! ( r75)))) <= r183) * r79) < ((1'h0 !== 29'h11fc) !== r124)); + #10; r216 = (r168 && ( + ( r70))); + #10; r104 = (28'h322b ? $time : (r71 - ((r27 ? ( ( ! ( 18'h42a9)) < ($time === (12'hfca * (13'haae <= ( ( + ( ( - ( r86)))) + ( ( ^ ( 3'h3)) == r20)))))) : r86) | ((((22'h689 + ((11'h164 ? r93 : (31'h5fb0 / ( ~ ( ((((13'h228 === 30'h1aac) && (32'h6fa6 / 13'hce9)) - ((2'h0 & 14'h32e3) < (5'h5 > 9'h1f4))) && 14'h2bcb))))) % (17'h2ebf ? 2'h3 : ( & ( r237))))) <= ((r84 * ( ( | ( r121)) || r158)) * r54)) / ( ! ( r74))) != r209)))); + #10; r195 = (r229 ^ (r139 - ( ( ! ( ( - ( r80)))) !== ((10'h17b >= (r243 > (r164 != 2'h1))) < 5'hd)))); + #10; r234 = (r252 ^ (((r76 | r123) / r202) && r219)); + #10; r235 = ( | ( r121)); + #10; r163 = ( ( ! ( $time)) != (2'h3 ? r30 : (r38 % 26'h781f))); + #10; r118 = ( & ( r48)); + #10; r27 = ( | ( ( ! ( r110)))); + #10; r226 = (r163 * 20'h3fca); + #10; r170 = (r217 && r180); + #10; r22 = ((r234 > 27'h2e9d) / 6'h35); + #10; r158 = (1'h1 === 9'h122); + #10; r83 = r244; + #10; r189 = r11; + #10; r233 = ( & ( (4'h6 <= (((r254 / r74) + (r104 < ((31'h6871 !== ( ( ^ ( (r235 === $time))) ? (($time % r158) && (23'h4695 > ( ~ ( 9'h165)))) : r225)) || (( ( + ( r138)) - r213) < (r43 ^ ( | ( r91))))))) >= ($time + (r186 ? 27'h3860 : r182)))))); + #10; r29 = (((((5'hf + (r171 == $stime)) !== (30'h4076 === (((11'h1e2 <= (17'h234d || ( | ( 20'h6b6b)))) < r173) || 24'h400b))) | r90) % (22'h620b <= ((5'h4 * 19'h67f7) > r168))) & ( + ( $stime))); + #10; r251 = r250; + #10; r192 = r214; + #10; r126 = r114; + #10; r91 = (25'h4e2b + ((((r213 || ( ! ( (r79 % r144)))) !== (r251 ^ r127)) % 5'h1) == ( ( ^ ( 7'h2e)) * r254))); + #10; r156 = 23'h3c0; + #10; r224 = r158; + #10; r255 = (( ( ! ( ( & ( ( | ( r88)))))) == r179) >= (r137 || 31'h4d5f)); + #10; r69 = (((r77 || 15'h4f09) ^ ((( ( ~ ( ((r190 ? 4'h6 : ((r135 && ((r151 || 13'hb64) - ( ! ( (r38 % r115))))) != r54)) | ((((r8 + ( ( ~ ( ((22'h50de >= 4'h5) || (10'h3af !== 10'h188)))) < (((13'h8ac * 28'h65db) ^ ( - ( 32'h108))) - ((14'h13c7 == 28'h60f6) !== r253)))) < ($time - ((r11 & ( - ( (17'h29f6 == 25'h56c9)))) == (5'hb > r51)))) <= r88) < 15'h7b0f)))) * ( - ( r197))) & ( ( - ( r234)) >= ((((12'h529 < ((20'h486a <= (8'hbb == (r4 !== r114))) > ((r68 == 1'h0) - ((r172 ^ r108) >= ( ( ~ ( (22'h5e34 + 25'h35ec))) == r26))))) ? (r30 * ( ! ( (r65 != (((r105 | 3'h3) - ((3'h5 - 10'h315) - 25'h4df9)) | ((9'h1e6 ^ 21'h2aa2) - ((13'h17bb >= 21'h7f98) == $time))))))) : 17'h7c99) / ((r174 | ((r61 != (r233 == ( + ( ( ( | ( 20'h6357)) !== r173))))) != r219)) % (24'h6372 === ( | ( (((((15'h5a99 / 19'h2862) || (4'h0 & 28'h5982)) == r65) && $time) / (( ( + ( (12'h15f + 8'h97))) < r96) != (r100 <= (r142 >= 3'h3))))))))) * (( ( - ( (r30 !== ( | ( ((((2'h0 | 9'h61) && (14'h3841 && 11'h620)) !== (r236 / r38)) && r68)))))) & r95) ^ ( ~ ( r92)))))) < ( + ( (r76 === $stime))))) == ( ! ( ( ^ ( (((31'h5d2f >= r92) - (($stime >= r103) < ((r128 | 23'h22f1) % (20'h47b3 < ($time === ( | ( r180))))))) / 25'hb6e)))))); + #10; r233 = ((r44 >= ( ! ( ( & ( (21'h38fd || (r106 % (r184 & ( ~ ( (r158 & r174))))))))))) / (7'h38 % (r100 & ((r11 - r201) ? (r130 + ( ^ ( $stime))) : (( ( ~ ( (1'h1 ^ r76))) - ( & ( (3'h0 >= ( ( & ( r50)) != ($stime | r49)))))) + (30'h6282 * 29'hfe6)))))); + #10; r214 = (30'h1532 / ((((r137 && (r27 - $time)) | ((r222 >= ((r101 ? ( & ( (( ( + ( r93)) & ( ~ ( ( ~ ( ((12'ha8d && 10'h1b2) > r62)))))) + ( ~ ( r201))))) : r235) !== (($stime ^ ( | ( r92))) & (20'h3e39 > ((32'h39ff - (r181 === r17)) || r160))))) ^ (32'h4120 * ( - ( (22'h7d08 < ((32'h74fd != (( ( - ( 4'he)) >= ((23'h7cee <= r20) & ( + ( (20'h4711 / 32'h1bb6))))) + ((((21'h2fec === 13'hd08) === 7'h22) <= ( ( ! ( 17'h6a6)) == r109)) | ((9'h1c + (1'h0 | 29'h4e54)) >= $time)))) - 29'h5ff4))))))) !== r237) / 10'h256)); + #10; r26 = (27'h3abb & ($stime * r112)); + #10; r28 = (r212 < 4'hd); + #10; r128 = r109; + #10; r59 = $time; + #10; r180 = r37; + #10; r109 = 6'h10; + #10; r80 = (r0 > r215); + #10; r26 = 2'h1; + #10; r185 = (7'h76 !== ((((r221 - (((r159 !== ( ~ ( 16'h110b))) || (r133 % $stime)) & (r66 - 30'h5f20))) !== 8'h99) - r170) == (25'h345f !== (r78 ^ ( ( + ( ( ^ ( ( - ( (r196 ^ $time))))))) !== (5'h1 && (10'hee - (19'h4256 ^ r246)))))))); + #10; r146 = 26'h1c07; + #10; r69 = ( + ( r129)); + #10; r187 = (((r245 | ( & ( 6'h32))) == 28'h34e2) || r128); + #10; r38 = $stime; + #10; r233 = ( ^ ( 18'h57d6)); + #10; r174 = (22'h93b !== 20'h10d4); + #10; r150 = ( ( ^ ( r156)) && (((( ( | ( r211)) != r229) + (r249 - ((r17 ? ( + ( ( ~ ( (( ( ! ( ( & ( 31'h6a65)))) || r174) && r229))))) : (r109 - r100)) | (((31'h15d == (12'h2b & ( ( ! ( r246)) + $time))) <= r14) >= ((30'h34b2 != r120) - (((((r100 === (r251 ^ 22'h665)) ? ((19'h2712 || r233) - ((8'h17 * 32'h4a8) * (12'h98c % 11'h480))) : r56) > (r104 ^ r14)) - ( ~ ( ( - ( ( ( | ( (4'h2 !== 29'h34bc))) != ( & ( r57)))))))) >= ( ^ ( r63)))))))) && 7'h66) !== 14'h1b9f)); + #10; r162 = r235; + #10; r172 = (r216 > ($time > (28'h5158 % r196))); + #10; r184 = (( ( - ( r45)) != (((r130 >= ( ! ( (r19 === $stime)))) > (14'h520 / ( ^ ( 15'h5fdb)))) && $time)) === ( & ( (r242 && ( ^ ( (((r120 * r148) <= ((r231 < r248) | r48)) != r187))))))); + #10; r17 = 11'h50b; + #10; r55 = (12'h425 !== $time); + #10; r153 = r221; + #10; r74 = 29'h4919; + #10; r117 = r42; + #10; r28 = $time; + #10; r32 = (r204 ? ((r140 >= $time) > (r15 % ( | ( ((9'h109 * r58) * r240))))) : ( ( & ( ((5'h8 / r5) ? 3'h2 : r72))) > (3'h0 - ( ^ ( r104))))); + #10; r11 = (r105 | ((r67 >= (((((11'h6cc == 20'h5279) - (((( ( ^ ( 2'h0)) >= (25'h262e % (((1'h1 ^ 4'h5) < (32'h34e3 + 32'h3f3f)) ^ r81))) !== (3'h1 - r162)) & ( ( + ( ( ! ( r171)))) === ((r95 && 3'h1) % 11'h241))) < $time)) / 14'h3e43) - r219) - 5'h0)) % ((22'h6f46 < ( ( ^ ( ( ! ( ((15'h4328 == (9'h7a < r234)) > r75))))) && r179)) && ( & ( (r174 * r120)))))); + #10; r152 = ( ( & ( r53)) % (r193 - ((((r106 % r173) && r85) / $time) * ( - ( r82))))); + #10; r181 = r166; + #10; r189 = 23'h5062; + #10; r129 = 12'h998; + #10; r39 = 32'h51e9; + #10; r16 = (($time % 12'h63f) + r134); + #10; r223 = 12'h62; + #10; r51 = (( ( ^ ( 9'h6b)) & ( ! ( (28'h7eb0 | (r13 > (((r131 % (r176 != ((21'h7647 === ((22'h4cf1 ^ r217) * ( ( + ( 15'h40e1)) / r15))) ^ r191))) / ($stime || ( ( & ( ( ( - ( 7'h51)) <= ((19'h3479 > ((11'h518 > 25'h3c63) | (11'h243 ? 14'h3d56 : 11'h19e))) == (((25'h42 == 29'h4a37) > r19) * r255))))) && r196))) % r91)))))) + r104); + #10; r177 = (22'h187d + (23'h2808 < ((r46 >= ( - ( 8'hef))) & ((20'h68db != ( - ( r158))) + r185)))); + #10; r194 = $stime; + #10; r219 = r208; + #10; r94 = r73; + #10; r61 = ((r25 - 26'h3cec) && ( - ( (r171 & r51)))); + #10; r249 = (17'h1cad > $stime); + #10; r238 = (((r100 === r94) ? ((( ( + ( 31'h39d9)) == r226) === (r220 + $time)) === ( ^ ( ( ( ^ ( 20'h5654)) != ((r147 + ( | ( r163))) - $stime))))) : ((28'ha75 >= (19'h59e0 - 32'h11eb)) > 25'h2ad6)) > 6'h32); + #10; r176 = r71; + #10; r239 = ( & ( (r64 ? ( - ( 25'h3d72)) : r249))); + #10; r34 = ((((((r153 == r230) && (( ( ^ ( ((r127 != (((28'h4dc6 != ( ! ( ( ! ( 18'h3da9))))) - ( ! ( ((9'h12e % 4'h0) <= (19'h2020 | 20'h2df2))))) & r166)) != 24'h3de8))) === (((r106 == ( ( & ( ( ~ ( r47)))) % ( ~ ( ((r127 || r121) - (r238 !== (1'h1 >= 17'h5887))))))) - ( & ( (12'h8b2 <= 17'hb10)))) + ( + ( $time)))) ? 19'h55b5 : ( | ( ( ^ ( ( ! ( (r147 ? (24'h3adc && 20'h2e20) : (r121 % ((( ( ~ ( 15'h1caa)) <= r178) <= (r238 ? ( ! ( 27'h4907)) : (27'h1b95 && 19'h699e))) <= r225))))))))))) / r224) / r141) != ( + ( r154))) * (( ( ^ ( r176)) + 1'h0) || r214)); + #10; r195 = ( ( ! ( (20'h568d / ( ( | ( ( ( | ( (((r179 && ( ~ ( ( ( & ( ((14'h31b8 + 13'hab0) != 14'h758))) & ( ! ( 4'h6)))))) < (11'h7d9 % ( ! ( (21'h59ed != r91))))) - $stime))) + r10))) - r23)))) * 12'h86); + #10; r198 = ((r185 == (24'h38c1 & (29'h636c != ( - ( (((r236 >= ( & ( r244))) >= ( ( - ( ($time & ( + ( r76))))) ? 17'h7d27 : ( - ( 28'h42b0)))) - ( + ( (19'hb62 === ((8'hc9 && ( ^ ( r143))) || (23'h13e0 !== (((17'h5c98 < r59) === (r141 >= ( ( ^ ( 27'h5389)) || (8'h5c != 10'h2ba)))) <= r136)))))))))))) < ((((23'h68e8 >= r212) ? (r115 < ( ( ^ ( ( ^ ( $stime)))) & (((((4'h7 ? ((r7 - $time) & (17'h6c4b > (26'h1d90 !== (22'h6c66 < 6'h2f)))) : 26'h1f77) >= (20'h5a16 > ( ^ ( ( ^ ( ((11'h2f1 > 10'h3f7) ^ ( - ( 32'h719e))))))))) - $time) == 24'h11e0) * ( ( + ( r122)) - 5'h6)))) : r221) >= ( | ( ( + ( (14'h2a24 - (16'h6dd0 >= 25'h1376))))))) > r54)); + #10; r79 = (( ( + ( ( ( + ( (((((20'h5369 && r249) ? (((r87 == (((5'h0 ? 14'h2f85 : 14'h1dae) / 30'h3c96) !== ((18'h7d54 >= 27'h19b) / (32'h6e73 != 32'h6d1e)))) === 15'h25af) * ( + ( ( | ( (((24'h4069 !== 23'h5c26) && r36) && ( ! ( 29'h4aa6)))))))) : 9'h14e) / (9'h19b !== ( ( & ( $stime)) + 8'hb2))) || ((( ( | ( ((((26'h6ff8 ? 4'h9 : 10'h23d) ? (15'h1a1e || 17'h6cd9) : (11'h689 === 9'h1ac)) != 24'h16e8) == ( ( + ( r140)) & $time)))) & (30'h3029 > (4'ha * (r208 * ((8'h8b <= 27'h63d4) < r215))))) * (r123 > 3'h3)) | (27'h527f + r177))) + (19'h722e <= 6'h27)))) | (r183 >= ((7'h6a % ((10'h9e !== (r8 || ( ( ~ ( (r75 == (r104 !== ( & ( 7'h23)))))) != ((r222 / ( | ( 26'h1023))) !== $stime)))) > (r255 | $stime))) % ( ! ( 23'h34ec))))))) == (( ( - ( 21'h6210)) * r195) !== ((28'h4979 > r232) | r22))) ^ (r125 * (r212 ^ (r10 != (((r201 >= 9'h39) < (( ( ~ ( (31'h2ca8 && ((18'h7958 - (((31'h50bf == 7'h73) === (10'h184 < 7'h0)) || ( & ( r100)))) + 17'h3580)))) >= ((r69 !== (r86 - (( ( & ( $time)) | ( & ( ( - ( 22'h5f1b))))) > ( ~ ( $time))))) ? 29'h6b06 : ((r236 >= 1'h1) < r25))) && 19'h2808)) === $time))))); + #10; r100 = (((r202 <= ( ~ ( r244))) == (r147 ? ( ( & ( (( ( | ( r167)) == r42) == r141))) + ( ( + ( ( + ( (((r254 ? $time : 18'h1c54) | r79) >= ((r25 === r206) != (r38 % r148))))))) * (7'h67 >= r127))) : ( + ( ((( ( + ( (12'h4f9 !== ( | ( r221))))) == ((r156 && (11'h216 | (((22'h66d5 || ((22'h1dd4 - 25'hd54) & (26'h133f | 12'h270))) * ( ( ! ( (23'h6438 > 6'h5))) ? ( ( - ( 7'h7b)) & r203) : ((23'h5cb4 ^ 28'h1157) <= (32'h4b39 + 23'h3ce5)))) <= (((30'h76b5 ? r69 : (24'h216b != 28'h41db)) | ( + ( r123))) * ($stime !== ((28'hf8e >= 22'h7349) > r202)))))) ^ ((r9 != r99) || ( & ( (r224 >= r134)))))) || r56) ^ r235))))) ? r79 : ( ( ^ ( ((15'h2d1e !== ((((5'h11 >= $stime) | 6'h2a) * ((27'hfa0 < ( ~ ( ( | ( ( ~ ( r156))))))) & (11'hb2 * r48))) === r166)) == ( + ( (((r136 || ( + ( ((( ( - ( 5'h1b)) == ( ( + ( (19'h2300 / 10'h2df))) <= 2'h0)) ^ ( ( ! ( ( - ( 10'hd2)))) / (((27'h3b64 * 16'h3f17) - (10'h3d4 | 5'h18)) == r74))) * r112)))) < 28'h4d35) * ( | ( ( ( ! ( (29'h355f <= ( ! ( r124))))) | ((r221 | ( - ( ((r23 + r167) > ( ! ( r106)))))) % r22)))))))))) ^ ( ! ( ((r246 & 27'h151c) >= 5'h1e))))); + #10; r54 = 10'h1cf; + #10; r51 = ((r132 >= ( | ( (r228 && 24'h35b3)))) / 3'h7); + #10; r43 = (r28 > ( - ( (r24 % ((r100 & (r249 % r181)) ? 28'h6c6d : (26'h6a62 && (r47 > ((13'haae != (r63 == ( ! ( ((((r48 || 4'h4) ^ (r249 >= (18'h3348 ? 30'h2e36 : 23'hf79))) / ( & ( r72))) ^ ((r147 || (r217 >= (29'h77b4 >= 14'h585))) >= ( ^ ( 10'h1ba)))))))) % ((( ( + ( ( - ( $stime)))) | $stime) > 30'h2161) % ($time % (( ( ~ ( ( & ( 5'h3)))) == r206) || r203))))))))))); + #10; r49 = ( + ( (( ( ^ ( (32'h73e8 <= ((13'h372 < ((r196 / ( ! ( ( ( - ( (r29 / (17'h609c && 6'h2f)))) / r103)))) && ((r245 + 21'h5feb) === (r195 < (r240 % ((((23'h27da + 26'hc96) == ( & ( 25'h7a84))) >= ( ( - ( 29'h33a4)) !== (5'he * 3'h0))) % (( ( + ( 1'h0)) ^ (18'h6e7e != 30'h3fba)) & $stime))))))) * 16'h88f)))) * 10'h3fb) < ((($stime % 26'h3cd3) * ((((r63 !== 32'h1ea4) + (13'hd6c != 3'h4)) < (($time > 31'h6440) + ((r51 && ( ( ! ( r108)) == (r28 % 10'h25e))) ^ r75))) - 22'h20d8)) & 10'h396)))); + #10; r248 = 23'h1af5; + #10; r125 = 17'h1787; + #10; r156 = $time; + #10; r200 = (($stime ? 20'h295e : r19) != r135); + #10; r209 = (( ( ~ ( (((((r97 + r9) - 12'h97a) - r11) > ((((r69 == ( ~ ( (r37 / ( & ( (((26'h2658 == 3'h1) && (12'h375 && 11'h76f)) * r35))))))) != 10'h290) % (r169 && ( ! ( ( + ( (($time % (r31 % (r216 | (13'h4f9 * 11'hd9)))) / r216))))))) * r94)) / (r8 + r209)))) < 1'h0) > ( | ( r166))); + #10; r165 = (9'hd2 - r156); + #10; r126 = 7'h15; + #10; r90 = ((r171 != ( ( ~ ( ((((20'h4f9f <= (r116 & r103)) >= ((r111 % 15'h61e6) == r145)) == $stime) == 29'h475b))) && ( - ( (r207 ? r100 : ( ( - ( ( ! ( 9'hd0)))) / ( | ( $time)))))))) / r85); + #10; r82 = 26'h4010; + #10; r112 = r191; + #10; r222 = 9'h31; + #10; r185 = (( ( ~ ( ( & ( ($stime != (( ( | ( (1'h1 ^ $time))) != r163) < (((r136 === (r43 % $stime)) == r192) <= ( + ( (r211 ^ (20'h60aa != ( ^ ( (( ( ^ ( (4'h1 <= 20'h42af))) ? ( ! ( (1'h1 - 16'h105))) : (16'h18a6 && 10'h379)) | r63)))))))))))))) && (r71 ^ 30'h3a7e)) >= r52); + #10; r63 = (( ( ! ( 19'h71d2)) || r72) && r82); + #10; r67 = r122; + #10; r201 = (r110 ^ ( | ( ($stime ? ((r117 - 4'h5) && ( ( - ( (r35 / (18'h7494 == (22'h463d % ( & ( 22'h302e))))))) / (r141 % ((4'h2 | (r78 * 19'h741d)) <= ( + ( ($stime != 16'h441e))))))) : r252)))); + #10; r14 = 8'h25; + #10; r227 = ( ( ! ( (((( ( ! ( (((12'ha44 - 13'h5b3) ? ((r235 || ((((8'he9 ? 27'h1dce : 10'h4a) !== ( - ( 32'h4efe))) !== 24'h5642) > r86)) <= (7'h76 % ((((5'h1e | 28'h60ab) != (13'hd0a + 21'h76b8)) === ((19'h402 % 20'h77e0) || r205)) + r145))) : r242) == ( ! ( ( ( | ( ( | ( (r120 <= ( ( & ( 8'h25)) - $time)))))) > ( | ( ( ( - ( r5)) ? 11'h276 : ( ( ^ ( 31'hbc7)) <= r90)))))))))) - ( - ( (((( ( + ( r232)) && $stime) & $time) * r150) ? r41 : ( | ( ((18'h22f3 / 4'h6) == (r76 ? ( ( | ( ($stime && (5'h18 <= 12'h483)))) & $stime) : ((((9'h54 <= 32'h2f44) | (3'h5 <= 16'h57af)) > 30'h3427) < $time))))))))) - (( ( | ( ( ( ~ ( ( ! ( ((r235 > r232) ^ ( ^ ( ( | ( ( - ( 3'h0))))))))))) && r240))) + r116) - ( ( ^ ( ( ! ( r19)))) % (r176 != r71)))) ? (r82 != 19'h5d16) : ((((r247 + (r124 - ((10'h13b > r155) === (r73 / $stime)))) < r246) / ((r9 - r190) + ((r25 ^ ((25'h720b / ( ( | ( ((19'h3f50 && 4'h8) & (30'h1773 || 5'h13)))) > (r150 | 19'h5393))) || ((r12 >= (((17'h434d === 8'hd9) * 29'h5a0b) > r21)) & r129))) * ( ( - ( r99)) == r227)))) < (22'h791f <= 5'h1b))) + r18))) && ((8'h71 == 3'h7) !== r85)); + #10; r112 = $stime; + #10; r9 = ( ^ ( (r91 !== ( + ( ((r23 >= r175) | (((14'h144a + ((3'h6 * (r67 || ((( ( | ( (2'h2 != 22'h5093))) && 17'h18af) + (32'h3d27 > 9'h11)) - (((12'h474 && $time) != ((13'h1f06 * 4'he) == (6'h20 + 20'h106))) ? ( ! ( ( & ( ( - ( 18'h7b24)))))) : r173)))) != 6'h15)) + 4'h1) & $time))))))); + #10; r143 = 14'h2865; + #10; r123 = 6'h3d; + #10; r68 = (10'h296 * ( ^ ( ( ( + ( ((((((26'h6a45 - ( - ( ((27'h5a8b ^ (r216 || (19'h67a3 + 16'h4b36))) ^ ( + ( 2'h3)))))) && 14'h1816) || r144) * ( - ( r153))) / r192) ^ ((r128 * r13) & ( | ( r212)))))) != ((11'h5f0 ^ 9'h17e) == ((27'h62f3 > r48) | r84)))))); + #10; r233 = r38; + #10; r11 = r39; + #10; r138 = (( ( - ( 25'h745)) === (23'h560d >= ( | ( ( ~ ( r208)))))) ^ (((r193 % r112) % (25'h2df3 === 30'h2e15)) || r198)); + #10; r122 = 24'h62ec; + #10; r255 = 24'h4ba0; + #10; r107 = (((r202 || ((19'h6de4 | 18'h4463) | (7'h7 + (2'h0 % ( - ( ( ! ( ( ( ^ ( (r46 !== ((29'h1a74 ^ ( ( - ( 7'h69)) != ( ! ( 15'h777)))) - (((9'h90 / 29'h787c) && (29'h2626 !== 10'h11c)) | (5'hb == ( ! ( 14'h2aec)))))))) || r224))))))))) <= ((($stime % r96) || (( ( & ( ( ( ^ ( ((((((8'hc5 < 30'h3fbc) ? r59 : (26'h6bb6 !== 20'h4c53)) & ( ( ~ ( 32'h1e0d)) != ( - ( 14'h85c)))) !== ((r245 ? 18'h5cb8 : (6'h8 | 31'h321c)) != ((15'h260b - 18'h4db3) >= (18'h4dd >= 16'h703b)))) % r225) < r158))) + 22'h6c04))) >= (r216 + $time)) ? (((r243 | ( ~ ( ( ^ ( 3'h4))))) < ((((26'h5eda ? $time : (r243 + 32'h15fb)) != 31'h1d73) < ((r52 <= r10) < (((31'h5a7c === (r163 & (10'h2e4 >= 29'h1549))) || r119) != ($time !== r184)))) || ( ^ ( ( ( ~ ( (((12'h669 ^ (25'h5139 | 22'h54d2)) & r123) !== 7'h56))) != r7))))) / (r81 | 8'h39)) : ( ! ( r60)))) ? ( ^ ( r135)) : r94)) / 21'h5e3f); + #10; r80 = ((r16 ? r183 : ($time <= r178)) / ( + ( ( ( | ( ((r54 !== r222) + (( ( ~ ( ( + ( 3'h3)))) && ((((((( ( ! ( 2'h1)) != (23'h4dc1 || 25'h6418)) & ((15'h3134 + 2'h1) * (4'h4 ? 29'h7aeb : 24'h1db3))) || r131) < r248) + ($time & ( | ( r78)))) | ((((8'he9 || ((28'h64f2 != 31'h5ecb) == (5'h10 !== 16'h7020))) || (((20'h1b88 % 27'h7c75) - (1'h0 === 5'h0)) % ( | ( (12'h4b9 & 19'h5c3b))))) - (17'he76 <= 2'h3)) / ( ~ ( r73)))) <= (17'h386e | (r194 % ( - ( ( ! ( ($time - r125))))))))) > 15'h7f04)))) === 13'h1828)))); + #10; r37 = (($stime == ((r41 !== ( | ( 27'h1da6))) === (r35 === ( & ( 27'h2564))))) || ((16'h512e ? r184 : $stime) & 25'h56a4)); + #10; r96 = ( - ( ( ~ ( r31)))); + #10; r246 = $stime; + #10; r251 = 28'h62ae; + #10; r143 = r4; + #10; r123 = (r86 - $time); + #10; r65 = r247; + #10; r188 = r248; + #10; r89 = ( ( & ( r73)) & r43); + #10; r185 = 1'h1; + #10; r45 = (( ( | ( ( ^ ( 24'h1a2d)))) !== r2) <= ( + ( 22'h7447))); + #10; r92 = (($stime % ( ^ ( (((r236 ? (((((10'h240 ? 22'h7a0d : r163) * 20'h71a2) >= ( ( - ( r186)) < ((r104 * (((27'h7436 === 20'hbfb) || (13'h1d62 | 26'h6221)) != ((29'h823 && 6'h34) ^ r170))) % ( ( - ( r11)) % (((32'h611e / 31'h3c4c) + ( & ( 20'h30a4))) - ((12'h85b == 26'hfd9) < 22'h74bb)))))) | (24'h4b4e > ( ! ( ( | ( (( ( + ( (29'h63b9 >= 31'h5396))) < (28'h24a0 & (4'h5 | 6'h1c))) | ( - ( ((13'h6a7 & 5'h3) >= ( | ( 1'h0)))))))))))) % (r164 === r50)) : 13'h25d) == 19'h4390) || r105)))) | r180); + #10; r23 = (5'h5 ^ ( ! ( $stime))); + #10; r8 = ($time ? (32'h605f >= ((r233 > ( ~ ( ( ( ^ ( (r28 * 26'h48ea))) ^ (((16'h617e & (10'he4 / r234)) ? 29'h1e10 : ( ( & ( 11'h22)) | $stime)) * ( | ( ( - ( ((r200 | r159) == ((r226 < ((22'h50da ^ r22) >= (19'h5845 > ( + ( 16'h3e29))))) !== (( ( ! ( (29'h34fe && 6'hc))) !== ((26'h35c4 < 20'h5230) * (30'h14f8 === 6'he))) < (((10'hc9 >= 12'h616) / (24'h6357 ^ 29'he15)) >= 31'h2b58))))))))))))) - ( ( ^ ( 10'h2af)) == ((32'h50d6 < 24'h30c0) > 22'h570e)))) : r232); + #10; r245 = (r165 === (r147 === r18)); + #10; r57 = ( - ( r200)); + #10; r208 = ( | ( (r75 > 5'h2))); + #10; r153 = ( + ( r49)); + #10; r80 = ( ( - ( (r204 === ((4'h8 <= 14'h3eda) / r161)))) % ( ( | ( 17'h27bf)) != r40)); + #10; r230 = ((r196 & ((28'h44ec / r235) - ( ( | ( r84)) ^ ( | ( r199))))) & ( ( - ( (r215 % ((21'h63b8 < (r247 || ((9'h1b4 - 5'he) ? r129 : (((7'h48 / r63) < 30'h6df7) <= $time)))) - (r161 <= r141))))) == $time)); + #10; r58 = r227; + $displayb("r0 = ",r0); + $displayb("r1 = ",r1); + $displayb("r2 = ",r2); + $displayb("r3 = ",r3); + $displayb("r4 = ",r4); + $displayb("r5 = ",r5); + $displayb("r6 = ",r6); + $displayb("r7 = ",r7); + $displayb("r8 = ",r8); + $displayb("r9 = ",r9); + $displayb("r10 = ",r10); + $displayb("r11 = ",r11); + $displayb("r12 = ",r12); + $displayb("r13 = ",r13); + $displayb("r14 = ",r14); + $displayb("r15 = ",r15); + $displayb("r16 = ",r16); + $displayb("r17 = ",r17); + $displayb("r18 = ",r18); + $displayb("r19 = ",r19); + $displayb("r20 = ",r20); + $displayb("r21 = ",r21); + $displayb("r22 = ",r22); + $displayb("r23 = ",r23); + $displayb("r24 = ",r24); + $displayb("r25 = ",r25); + $displayb("r26 = ",r26); + $displayb("r27 = ",r27); + $displayb("r28 = ",r28); + $displayb("r29 = ",r29); + $displayb("r30 = ",r30); + $displayb("r31 = ",r31); + $displayb("r32 = ",r32); + $displayb("r33 = ",r33); + $displayb("r34 = ",r34); + $displayb("r35 = ",r35); + $displayb("r36 = ",r36); + $displayb("r37 = ",r37); + $displayb("r38 = ",r38); + $displayb("r39 = ",r39); + $displayb("r40 = ",r40); + $displayb("r41 = ",r41); + $displayb("r42 = ",r42); + $displayb("r43 = ",r43); + $displayb("r44 = ",r44); + $displayb("r45 = ",r45); + $displayb("r46 = ",r46); + $displayb("r47 = ",r47); + $displayb("r48 = ",r48); + $displayb("r49 = ",r49); + $displayb("r50 = ",r50); + $displayb("r51 = ",r51); + $displayb("r52 = ",r52); + $displayb("r53 = ",r53); + $displayb("r54 = ",r54); + $displayb("r55 = ",r55); + $displayb("r56 = ",r56); + $displayb("r57 = ",r57); + $displayb("r58 = ",r58); + $displayb("r59 = ",r59); + $displayb("r60 = ",r60); + $displayb("r61 = ",r61); + $displayb("r62 = ",r62); + $displayb("r63 = ",r63); + $displayb("r64 = ",r64); + $displayb("r65 = ",r65); + $displayb("r66 = ",r66); + $displayb("r67 = ",r67); + $displayb("r68 = ",r68); + $displayb("r69 = ",r69); + $displayb("r70 = ",r70); + $displayb("r71 = ",r71); + $displayb("r72 = ",r72); + $displayb("r73 = ",r73); + $displayb("r74 = ",r74); + $displayb("r75 = ",r75); + $displayb("r76 = ",r76); + $displayb("r77 = ",r77); + $displayb("r78 = ",r78); + $displayb("r79 = ",r79); + $displayb("r80 = ",r80); + $displayb("r81 = ",r81); + $displayb("r82 = ",r82); + $displayb("r83 = ",r83); + $displayb("r84 = ",r84); + $displayb("r85 = ",r85); + $displayb("r86 = ",r86); + $displayb("r87 = ",r87); + $displayb("r88 = ",r88); + $displayb("r89 = ",r89); + $displayb("r90 = ",r90); + $displayb("r91 = ",r91); + $displayb("r92 = ",r92); + $displayb("r93 = ",r93); + $displayb("r94 = ",r94); + $displayb("r95 = ",r95); + $displayb("r96 = ",r96); + $displayb("r97 = ",r97); + $displayb("r98 = ",r98); + $displayb("r99 = ",r99); + $displayb("r100 = ",r100); + $displayb("r101 = ",r101); + $displayb("r102 = ",r102); + $displayb("r103 = ",r103); + $displayb("r104 = ",r104); + $displayb("r105 = ",r105); + $displayb("r106 = ",r106); + $displayb("r107 = ",r107); + $displayb("r108 = ",r108); + $displayb("r109 = ",r109); + $displayb("r110 = ",r110); + $displayb("r111 = ",r111); + $displayb("r112 = ",r112); + $displayb("r113 = ",r113); + $displayb("r114 = ",r114); + $displayb("r115 = ",r115); + $displayb("r116 = ",r116); + $displayb("r117 = ",r117); + $displayb("r118 = ",r118); + $displayb("r119 = ",r119); + $displayb("r120 = ",r120); + $displayb("r121 = ",r121); + $displayb("r122 = ",r122); + $displayb("r123 = ",r123); + $displayb("r124 = ",r124); + $displayb("r125 = ",r125); + $displayb("r126 = ",r126); + $displayb("r127 = ",r127); + $displayb("r128 = ",r128); + $displayb("r129 = ",r129); + $displayb("r130 = ",r130); + $displayb("r131 = ",r131); + $displayb("r132 = ",r132); + $displayb("r133 = ",r133); + $displayb("r134 = ",r134); + $displayb("r135 = ",r135); + $displayb("r136 = ",r136); + $displayb("r137 = ",r137); + $displayb("r138 = ",r138); + $displayb("r139 = ",r139); + $displayb("r140 = ",r140); + $displayb("r141 = ",r141); + $displayb("r142 = ",r142); + $displayb("r143 = ",r143); + $displayb("r144 = ",r144); + $displayb("r145 = ",r145); + $displayb("r146 = ",r146); + $displayb("r147 = ",r147); + $displayb("r148 = ",r148); + $displayb("r149 = ",r149); + $displayb("r150 = ",r150); + $displayb("r151 = ",r151); + $displayb("r152 = ",r152); + $displayb("r153 = ",r153); + $displayb("r154 = ",r154); + $displayb("r155 = ",r155); + $displayb("r156 = ",r156); + $displayb("r157 = ",r157); + $displayb("r158 = ",r158); + $displayb("r159 = ",r159); + $displayb("r160 = ",r160); + $displayb("r161 = ",r161); + $displayb("r162 = ",r162); + $displayb("r163 = ",r163); + $displayb("r164 = ",r164); + $displayb("r165 = ",r165); + $displayb("r166 = ",r166); + $displayb("r167 = ",r167); + $displayb("r168 = ",r168); + $displayb("r169 = ",r169); + $displayb("r170 = ",r170); + $displayb("r171 = ",r171); + $displayb("r172 = ",r172); + $displayb("r173 = ",r173); + $displayb("r174 = ",r174); + $displayb("r175 = ",r175); + $displayb("r176 = ",r176); + $displayb("r177 = ",r177); + $displayb("r178 = ",r178); + $displayb("r179 = ",r179); + $displayb("r180 = ",r180); + $displayb("r181 = ",r181); + $displayb("r182 = ",r182); + $displayb("r183 = ",r183); + $displayb("r184 = ",r184); + $displayb("r185 = ",r185); + $displayb("r186 = ",r186); + $displayb("r187 = ",r187); + $displayb("r188 = ",r188); + $displayb("r189 = ",r189); + $displayb("r190 = ",r190); + $displayb("r191 = ",r191); + $displayb("r192 = ",r192); + $displayb("r193 = ",r193); + $displayb("r194 = ",r194); + $displayb("r195 = ",r195); + $displayb("r196 = ",r196); + $displayb("r197 = ",r197); + $displayb("r198 = ",r198); + $displayb("r199 = ",r199); + $displayb("r200 = ",r200); + $displayb("r201 = ",r201); + $displayb("r202 = ",r202); + $displayb("r203 = ",r203); + $displayb("r204 = ",r204); + $displayb("r205 = ",r205); + $displayb("r206 = ",r206); + $displayb("r207 = ",r207); + $displayb("r208 = ",r208); + $displayb("r209 = ",r209); + $displayb("r210 = ",r210); + $displayb("r211 = ",r211); + $displayb("r212 = ",r212); + $displayb("r213 = ",r213); + $displayb("r214 = ",r214); + $displayb("r215 = ",r215); + $displayb("r216 = ",r216); + $displayb("r217 = ",r217); + $displayb("r218 = ",r218); + $displayb("r219 = ",r219); + $displayb("r220 = ",r220); + $displayb("r221 = ",r221); + $displayb("r222 = ",r222); + $displayb("r223 = ",r223); + $displayb("r224 = ",r224); + $displayb("r225 = ",r225); + $displayb("r226 = ",r226); + $displayb("r227 = ",r227); + $displayb("r228 = ",r228); + $displayb("r229 = ",r229); + $displayb("r230 = ",r230); + $displayb("r231 = ",r231); + $displayb("r232 = ",r232); + $displayb("r233 = ",r233); + $displayb("r234 = ",r234); + $displayb("r235 = ",r235); + $displayb("r236 = ",r236); + $displayb("r237 = ",r237); + $displayb("r238 = ",r238); + $displayb("r239 = ",r239); + $displayb("r240 = ",r240); + $displayb("r241 = ",r241); + $displayb("r242 = ",r242); + $displayb("r243 = ",r243); + $displayb("r244 = ",r244); + $displayb("r245 = ",r245); + $displayb("r246 = ",r246); + $displayb("r247 = ",r247); + $displayb("r248 = ",r248); + $displayb("r249 = ",r249); + $displayb("r250 = ",r250); + $displayb("r251 = ",r251); + $displayb("r252 = ",r252); + $displayb("r253 = ",r253); + $displayb("r254 = ",r254); + $finish(0); + end +endmodule diff --git a/ivtest/ivltests/comp1001.v b/ivtest/ivltests/comp1001.v new file mode 100644 index 000000000..e59fa265f --- /dev/null +++ b/ivtest/ivltests/comp1001.v @@ -0,0 +1,1190 @@ +// +// Copyright (c) 2000 Paul Campbell (paul@verifarm.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +module compl1001; + reg [104:86]r0; + reg [261:230]r1; + reg [101:78]r2; + reg [216:215]r3; + reg [140:123]r4; + reg [70:53]r5; + reg [150:150]r6; + reg [143:133]r7; + reg [261:239]r8; + reg [228:211]r9; + reg [273:244]r10; + reg [42:21]r11; + reg [137:130]r12; + reg [103:96]r13; + reg [257:239]r14; + reg [230:205]r15; + reg [216:212]r16; + reg [64:40]r17; + reg [156:155]r18; + reg [103:94]r19; + reg [216:204]r20; + reg [170:165]r21; + reg [25:22]r22; + reg [125:105]r23; + reg [57:32]r24; + reg [261:250]r25; + reg [32:13]r26; + reg [251:246]r27; + reg [210:209]r28; + reg [121:119]r29; + reg [57:55]r30; + reg [255:253]r31; + reg [196:174]r32; + reg [26:26]r33; + reg [216:215]r34; + reg [238:224]r35; + reg [212:207]r36; + reg [32:11]r37; + reg [89:60]r38; + reg [246:237]r39; + reg [50:25]r40; + reg [43:29]r41; + reg [94:66]r42; + reg [235:222]r43; + reg [213:190]r44; + reg [102:81]r45; + reg [211:208]r46; + reg [108:91]r47; + reg [189:188]r48; + reg [97:84]r49; + reg [108:90]r50; + reg [124:116]r51; + reg [113:92]r52; + reg [278:254]r53; + reg [98:94]r54; + reg [43:42]r55; + reg [191:178]r56; + reg [230:211]r57; + reg [250:233]r58; + reg [236:229]r59; + reg [65:34]r60; + reg [155:132]r61; + reg [32:18]r62; + reg [253:253]r63; + reg [243:215]r64; + reg [133:109]r65; + reg [133:124]r66; + reg [66:51]r67; + reg [94:75]r68; + reg [31:23]r69; + reg [230:214]r70; + reg [75:55]r71; + reg [209:196]r72; + reg [200:181]r73; + reg [101:92]r74; + reg [43:34]r75; + reg [228:211]r76; + reg [171:169]r77; + reg [112:86]r78; + reg [257:252]r79; + reg [214:214]r80; + reg [279:254]r81; + reg [149:149]r82; + reg [80:53]r83; + reg [140:117]r84; + reg [265:238]r85; + reg [277:251]r86; + reg [71:45]r87; + reg [56:38]r88; + reg [95:91]r89; + reg [271:242]r90; + reg [187:174]r91; + reg [176:171]r92; + reg [100:88]r93; + reg [273:242]r94; + reg [137:111]r95; + reg [148:144]r96; + reg [168:159]r97; + reg [269:254]r98; + reg [149:145]r99; + reg [202:176]r100; + reg [37:26]r101; + reg [62:37]r102; + reg [47:36]r103; + reg [195:176]r104; + reg [124:93]r105; + reg [8:4]r106; + reg [170:161]r107; + reg [150:129]r108; + reg [54:40]r109; + reg [86:64]r110; + reg [132:111]r111; + reg [224:224]r112; + reg [262:232]r113; + reg [27:14]r114; + reg [99:97]r115; + reg [234:214]r116; + reg [66:52]r117; + reg [178:173]r118; + reg [83:52]r119; + reg [67:58]r120; + reg [110:82]r121; + reg [255:232]r122; + reg [41:19]r123; + reg [67:45]r124; + reg [179:178]r125; + reg [173:151]r126; + reg [35:20]r127; + reg [168:155]r128; + reg [129:112]r129; + reg [47:29]r130; + reg [199:186]r131; + reg [217:190]r132; + reg [241:212]r133; + reg [256:233]r134; + reg [129:116]r135; + reg [168:157]r136; + reg [230:211]r137; + reg [261:248]r138; + reg [39:27]r139; + reg [137:135]r140; + reg [169:142]r141; + reg [103:79]r142; + reg [118:118]r143; + reg [156:154]r144; + reg [234:208]r145; + reg [154:131]r146; + reg [211:183]r147; + reg [74:65]r148; + reg [161:145]r149; + reg [58:51]r150; + reg [268:253]r151; + reg [193:175]r152; + reg [148:120]r153; + reg [169:138]r154; + reg [213:210]r155; + reg [119:103]r156; + reg [104:83]r157; + reg [212:193]r158; + reg [172:172]r159; + reg [206:182]r160; + reg [176:159]r161; + reg [172:153]r162; + reg [119:110]r163; + reg [75:53]r164; + reg [5:5]r165; + reg [238:226]r166; + reg [258:230]r167; + reg [95:74]r168; + reg [231:216]r169; + reg [252:248]r170; + reg [98:79]r171; + reg [191:166]r172; + reg [161:154]r173; + reg [67:67]r174; + reg [214:207]r175; + reg [204:198]r176; + reg [131:118]r177; + reg [212:181]r178; + reg [258:248]r179; + reg [141:116]r180; + reg [201:198]r181; + reg [108:78]r182; + reg [83:72]r183; + reg [81:69]r184; + reg [144:140]r185; + reg [174:154]r186; + reg [191:171]r187; + reg [48:27]r188; + reg [260:251]r189; + reg [69:47]r190; + reg [259:246]r191; + reg [167:162]r192; + reg [245:237]r193; + reg [67:49]r194; + reg [133:108]r195; + reg [224:213]r196; + reg [126:108]r197; + reg [230:208]r198; + reg [80:59]r199; + reg [136:120]r200; + reg [62:44]r201; + reg [206:198]r202; + reg [284:254]r203; + reg [184:158]r204; + reg [32:13]r205; + reg [233:220]r206; + reg [69:59]r207; + reg [46:34]r208; + reg [181:156]r209; + reg [105:100]r210; + reg [240:228]r211; + reg [51:48]r212; + reg [149:144]r213; + reg [201:190]r214; + reg [234:215]r215; + reg [212:188]r216; + reg [98:79]r217; + reg [237:214]r218; + reg [105:96]r219; + reg [10:7]r220; + reg [134:105]r221; + reg [192:162]r222; + reg [202:180]r223; + reg [50:31]r224; + reg [50:26]r225; + reg [181:166]r226; + reg [146:117]r227; + reg [118:93]r228; + reg [222:202]r229; + reg [135:114]r230; + reg [78:51]r231; + reg [260:231]r232; + reg [172:142]r233; + reg [58:32]r234; + reg [245:232]r235; + reg [51:46]r236; + reg [198:167]r237; + reg [217:217]r238; + reg [130:121]r239; + reg [130:111]r240; + reg [28:0]r241; + reg [87:79]r242; + reg [60:58]r243; + reg [59:53]r244; + reg [200:178]r245; + reg [81:67]r246; + reg [110:104]r247; + reg [233:211]r248; + reg [139:129]r249; + reg [262:254]r250; + reg [177:175]r251; + reg [262:236]r252; + reg [111:94]r253; + reg [230:218]r254; + reg [191:164]r255; + initial begin + r0 = 32'h2eec; + r1 = 32'h1584; + r2 = 32'h47e5; + r3 = 32'h587f; + r4 = 32'hab8; + r5 = 32'h71e9; + r6 = 32'h4e49; + r7 = 32'h6794; + r8 = 32'h5c8e; + r9 = 32'h1a61; + r10 = 32'h55df; + r11 = 32'h2da5; + r12 = 32'h3d89; + r13 = 32'h76ab; + r14 = 32'h6d8e; + r15 = 32'h66ed; + r16 = 32'hc57; + r17 = 32'h615c; + r18 = 32'h29c0; + r19 = 32'h7ed1; + r20 = 32'h11c7; + r21 = 32'h5f7a; + r22 = 32'h59cc; + r23 = 32'h36df; + r24 = 32'h6217; + r25 = 32'h35da; + r26 = 32'h2827; + r27 = 32'h418b; + r28 = 32'h6fb; + r29 = 32'h7839; + r30 = 32'h114b; + r31 = 32'h4ca3; + r32 = 32'h3e6d; + r33 = 32'h6e1d; + r34 = 32'h5d63; + r35 = 32'h3797; + r36 = 32'h5a38; + r37 = 32'h6969; + r38 = 32'h8bb; + r39 = 32'h716b; + r40 = 32'hc42; + r41 = 32'h6ac3; + r42 = 32'h46ea; + r43 = 32'h3a78; + r44 = 32'h2b9c; + r45 = 32'h2fa6; + r46 = 32'hcbc; + r47 = 32'h45e6; + r48 = 32'h3e4b; + r49 = 32'h646; + r50 = 32'h4ce2; + r51 = 32'h76e9; + r52 = 32'h53d4; + r53 = 32'h327; + r54 = 32'h5359; + r55 = 32'h35be; + r56 = 32'h7c89; + r57 = 32'h747c; + r58 = 32'h6b9a; + r59 = 32'h1864; + r60 = 32'h6996; + r61 = 32'h2f40; + r62 = 32'h3d86; + r63 = 32'h5b1b; + r64 = 32'h1ca; + r65 = 32'h1216; + r66 = 32'hd10; + r67 = 32'h649e; + r68 = 32'h7727; + r69 = 32'h59e1; + r70 = 32'h48a8; + r71 = 32'h521f; + r72 = 32'h2928; + r73 = 32'h2423; + r74 = 32'h126b; + r75 = 32'h4707; + r76 = 32'h5fd4; + r77 = 32'h3b16; + r78 = 32'h300c; + r79 = 32'h7c6a; + r80 = 32'h2b87; + r81 = 32'h78c; + r82 = 32'hd80; + r83 = 32'h4c4c; + r84 = 32'h757b; + r85 = 32'h4487; + r86 = 32'h3e6c; + r87 = 32'h3496; + r88 = 32'hd19; + r89 = 32'h5098; + r90 = 32'h2a4f; + r91 = 32'hdd6; + r92 = 32'h3e02; + r93 = 32'h38f8; + r94 = 32'h4f6f; + r95 = 32'h71ba; + r96 = 32'h3adc; + r97 = 32'h5a68; + r98 = 32'h4884; + r99 = 32'hd4a; + r100 = 32'h68dd; + r101 = 32'h33c8; + r102 = 32'h127; + r103 = 32'h5ae8; + r104 = 32'h5818; + r105 = 32'h4679; + r106 = 32'h44f9; + r107 = 32'h9; + r108 = 32'h748a; + r109 = 32'h2074; + r110 = 32'h1593; + r111 = 32'h4ab1; + r112 = 32'h3be4; + r113 = 32'h6c27; + r114 = 32'h7331; + r115 = 32'hab0; + r116 = 32'h416; + r117 = 32'h2213; + r118 = 32'h41d; + r119 = 32'h429e; + r120 = 32'h1ea0; + r121 = 32'h3827; + r122 = 32'h46dd; + r123 = 32'h6c97; + r124 = 32'h6497; + r125 = 32'h6ada; + r126 = 32'h3b1c; + r127 = 32'h4eb7; + r128 = 32'h7779; + r129 = 32'h7c0a; + r130 = 32'h2d59; + r131 = 32'h1b54; + r132 = 32'h42b2; + r133 = 32'h397; + r134 = 32'h1151; + r135 = 32'h58fe; + r136 = 32'h9ea; + r137 = 32'h2dbe; + r138 = 32'h172d; + r139 = 32'h4e38; + r140 = 32'h1015; + r141 = 32'h337; + r142 = 32'h676c; + r143 = 32'h6cf3; + r144 = 32'h2338; + r145 = 32'h170f; + r146 = 32'h318e; + r147 = 32'h79ce; + r148 = 32'h18fc; + r149 = 32'h3643; + r150 = 32'h7986; + r151 = 32'h6b10; + r152 = 32'h7f4; + r153 = 32'h7520; + r154 = 32'h4fdd; + r155 = 32'h3b61; + r156 = 32'h49ae; + r157 = 32'h365d; + r158 = 32'h60a6; + r159 = 32'h2c4b; + r160 = 32'h117b; + r161 = 32'h7f4; + r162 = 32'h525; + r163 = 32'h3475; + r164 = 32'h23fe; + r165 = 32'h71c5; + r166 = 32'h443e; + r167 = 32'h1599; + r168 = 32'h7b77; + r169 = 32'h11ea; + r170 = 32'h6d9f; + r171 = 32'h564a; + r172 = 32'h64cd; + r173 = 32'h22d8; + r174 = 32'h3bad; + r175 = 32'h1b68; + r176 = 32'h615d; + r177 = 32'h473a; + r178 = 32'h282f; + r179 = 32'h1d5e; + r180 = 32'h5985; + r181 = 32'h378d; + r182 = 32'h5fbd; + r183 = 32'h3522; + r184 = 32'h6bef; + r185 = 32'h2d7c; + r186 = 32'h7fe6; + r187 = 32'h3cea; + r188 = 32'h659d; + r189 = 32'h28f9; + r190 = 32'hc24; + r191 = 32'h40af; + r192 = 32'h2eb9; + r193 = 32'h6b1f; + r194 = 32'h4581; + r195 = 32'h3a63; + r196 = 32'h381a; + r197 = 32'h42cb; + r198 = 32'h5105; + r199 = 32'h55f1; + r200 = 32'h3596; + r201 = 32'h6f4; + r202 = 32'h58e6; + r203 = 32'h78f8; + r204 = 32'h310a; + r205 = 32'h5ace; + r206 = 32'h146f; + r207 = 32'ha48; + r208 = 32'h422a; + r209 = 32'h17a3; + r210 = 32'h62ac; + r211 = 32'h3518; + r212 = 32'h7709; + r213 = 32'h786c; + r214 = 32'h63db; + r215 = 32'h240d; + r216 = 32'h3967; + r217 = 32'h6332; + r218 = 32'h3d92; + r219 = 32'h6fec; + r220 = 32'h3cbe; + r221 = 32'h6c27; + r222 = 32'h75af; + r223 = 32'h3e19; + r224 = 32'h410b; + r225 = 32'h6e83; + r226 = 32'h1004; + r227 = 32'h4ad7; + r228 = 32'h365d; + r229 = 32'h5720; + r230 = 32'h5abf; + r231 = 32'h5b3e; + r232 = 32'hd1f; + r233 = 32'h7cd4; + r234 = 32'h159b; + r235 = 32'h52fb; + r236 = 32'h3f25; + r237 = 32'h2292; + r238 = 32'h5fc9; + r239 = 32'h69ca; + r240 = 32'h5d77; + r241 = 32'h7f3f; + r242 = 32'h189c; + r243 = 32'h3cb5; + r244 = 32'h2ee1; + r245 = 32'h6755; + r246 = 32'h1ef7; + r247 = 32'h370a; + r248 = 32'h2b36; + r249 = 32'h743a; + r250 = 32'h1b77; + r251 = 32'hf1d; + r252 = 32'h5f68; + r253 = 32'h455e; + r254 = 32'h415f; + r255 = 32'h52c2; + #10; r73 = r189; + #10; r132 = 11'h783; + #10; r86 = ( ( & ( (14'h1136 ^ ((25'hd6c == $time) * r2)))) != 26'h1ef2); + #10; r246 = ( | ( 22'h6337)); + #10; r35 = (r155 * ((r190 > (((((((r127 % ( | ( r81))) & r150) | r11) !== (((r207 <= (22'h4d2b ? ((r158 == ( - ( r219))) | 13'hdae) : r43)) != ((r97 > ((r240 != ((26'h259a * 13'h465) >= (5'h2 * 11'h7ed))) % (((12'h279 < 28'h3026) || 4'h1) && r111))) & ( ! ( ( ! ( (16'h7a99 <= 4'h6))))))) & 26'h5fa4)) && (((r15 | (( ( | ( ( ~ ( (r235 && 31'h2eeb))))) / r90) !== r56)) <= ((22'h640f !== r182) <= (31'h1b37 !== ( ( | ( (((9'hc9 / 32'h7c3b) - (8'ha6 - 3'h2)) == ((12'h36b - 9'h171) < ( + ( 23'h425)))))) % r72)))) + $time)) > r1) !== 18'h6d7b)) >= 28'h6e25)); + #10; r144 = 4'h9; + #10; r206 = ( ( | ( 12'h4ff)) | 17'h43ef); + #10; r138 = $time; + #10; r74 = 22'h38ad; + #10; r49 = r2; + #10; r50 = ((31'h744c ? ((r164 && r191) >= 16'h6c50) : ((r137 / ((1'h0 ^ ((r169 >= (((20'h5ab3 == ( & ( ( & ( (21'hb12 < (7'h16 || 10'h24e))))))) != r155) - ( | ( ( + ( ( ( ! ( r166)) % (26'h296c > 32'h62ed)))))))) === ( + ( ( | ( r187)))))) - r92)) * r99)) >= r189); + #10; r150 = ((12'h24d != r248) / ( & ( (((r34 - ( ! ( 20'h40cd))) === (((7'h52 > (25'h7f1d || 1'h1)) && 5'h12) ? ( ^ ( (r61 && ( ~ ( ( ( + ( ( ! ( (r73 <= ( | ( ( ( & ( 28'h57c)) / (24'h60a8 < 28'h7acc))))))))) | (8'h61 < ( ! ( (r184 === ( ~ ( (r72 == (15'h508 / 24'h5073)))))))))))))) : r24)) | r86)))); + #10; r73 = ( ( + ( ( ( ~ ( ((((20'h23e2 === ((11'h649 ^ 21'hfee) | ((r35 % 30'h856) <= r67))) !== ((r183 || (((r19 / (15'h304d + 25'h523a)) && 17'h7692) - r178)) - (((((25'h34f5 || r199) === r255) <= r12) !== (((((5'hb / 5'h11) == (5'h17 | 24'h408)) / (r255 ^ r181)) && ( & ( 14'h2e37))) === ((17'h1e79 <= r84) / (r0 !== ( ^ ( (26'h587b <= 20'h7403))))))) >= ( - ( r184))))) !== ( - ( r248))) === $time))) * 12'h5))) || r191); + #10; r134 = (1'h1 === 24'h12a0); + #10; r214 = 30'h3839; + #10; r255 = 30'h242b; + #10; r7 = 9'h132; + #10; r130 = r65; + #10; r64 = r162; + #10; r174 = ((r91 <= (r231 + ( - ( 1'h1)))) <= ((((r93 <= (r183 / ( ( & ( ( ^ ( ( ^ ( 1'h1)))))) <= r75))) * 12'ha95) & r27) | ((((((20'hf1f === ((r175 >= 20'h3632) | ((r109 & (r88 < r248)) < 10'h2e5))) & r37) % $stime) || ( ( + ( ( ! ( r160)))) & r17)) > ( ( | ( (r124 & ( - ( ( - ( (22'hd2b != ( ! ( r196)))))))))) && r84)) | (r51 / 16'h5f0d)))); + #10; r41 = ( ( ^ ( ( ( ^ ( ((3'h6 >= (r215 & (31'h3d8b && ( ^ ( 5'h11))))) <= $time))) & ( & ( r7))))) * ( ( - ( (12'he7e ? ( + ( ((3'h2 ^ r250) & (r214 <= (r19 - r249))))) : (r140 | r104)))) || r250)); + #10; r195 = 9'h1ac; + #10; r242 = 21'h527c; + #10; r143 = ((((((r68 ? (6'h1e ? ( ^ ( 26'h4f04)) : ( - ( ( ( - ( $time)) - (( ( + ( r96)) !== (r185 / 6'h22)) ? r133 : r2))))) : r20) * ((28'h20ec % r109) / ( + ( ( ( & ( 1'h0)) | (13'h13f1 === ((r96 - r204) * ( | ( 1'h0))))))))) === ((23'h4c6b / (20'h7a3b === r184)) == (( ( ! ( ( ( + ( (((7'h59 ? ((3'h4 <= 13'had1) | 15'h1a5c) : r123) % $stime) == ( + ( (((15'h74fe === 2'h0) == ( + ( 3'h0))) <= ((26'h2e1 | 8'h3b) + (16'h76a4 == 26'h645a)))))))) + ( + ( ((r123 & (r37 != (r211 >= (21'hcee < 18'h2845)))) >= (27'h5efd ^ r116))))))) | ((25'h4cd6 + r74) ? r115 : ((r133 - ((r198 ? r55 : (($stime % 17'h38a5) | $time)) === ( ~ ( r217)))) ? (r250 !== 19'h49e1) : ( ! ( r15))))) == r224))) - ((r244 > (r229 - ( & ( (( ( + ( r244)) != ( ! ( ((29'h6d1b === 10'h364) - ((17'h43c9 & ( + ( r238))) == r113))))) % 30'h7539))))) & ( | ( 23'h4205)))) | 5'h19) <= ( ! ( r92))); + #10; r74 = r232; + #10; r31 = ( ( ~ ( r181)) && ( - ( 7'h8))); + #10; r75 = (6'h10 === r188); + #10; r75 = ( ( & ( $stime)) + ( - ( ((( ( | ( (16'h1c8a % 32'h503f))) ? ((r161 ^ r59) == ( ! ( ( - ( (((r191 === r182) == ( ( + ( ( | ( r168)))) > ( ( | ( 1'h1)) * (( ( ^ ( 32'h2923)) != (14'h3cd7 * 24'h1162)) > (25'h7bc2 - 6'hd))))) - r31)))))) : ((4'hd & ( ^ ( (r130 - ((r96 === r154) == (32'h2fba >= ( | ( 4'h3)))))))) >= ( & ( (((r253 !== 18'h4189) >= (11'h679 < r133)) * r109))))) != $time) !== ( ( ~ ( (((21'h5dd3 / (10'h22e ^ (( ( ! ( ( + ( ( & ( (21'h5c32 * 12'h7e))))))) - ((((16'h132e || 23'hf58) <= 21'h1302) ^ ((2'h1 | 4'hb) - r113)) & (r207 || 24'h1190))) || ((r224 && r246) > 7'h19)))) % ( ( ~ ( r150)) - ((1'h1 & 24'h7aa2) | ($stime !== r24)))) >= 14'h29de))) !== ( + ( 10'h207))))))); + #10; r195 = 4'h7; + #10; r129 = r208; + #10; r152 = r144; + #10; r9 = (( ( ! ( ( & ( (r39 >= r176))))) - 5'h6) ^ 12'h837); + #10; r159 = ( + ( ((r132 <= (((( ( + ( (24'h5c17 + r12))) == 24'h3ca7) > r164) >= ( ( ^ ( r114)) > r126)) < ((r0 & ( ~ ( (22'h7ece <= (((2'h3 % (r90 + ( ( + ( 6'h1)) | $stime))) | r51) !== (27'h1d94 == (r189 & r252))))))) ? 2'h0 : r110))) <= ((r124 % r178) <= ( ( & ( $time)) - (((r22 == 27'h4da6) != 19'h14be) ^ (r155 / r52))))))); + #10; r92 = (28'h4175 + ( - ( ((( ( ~ ( (4'hf % (($stime ? 5'hf : ((((4'h8 | (r118 !== 10'h222)) != ($time / r53)) ? ( ~ ( r49)) : ((r251 > r162) - r163)) == 17'h72a0)) && (16'h486b === r203))))) + r130) + 14'h3094) ? (((r153 | 12'h53b) + (((r97 ^ (28'h6257 > 4'h5)) !== ( & ( ( ( ^ ( ( | ( ( & ( 13'h1537)))))) != ((18'h18c7 != r154) & r105))))) != r241)) - r193) : ((14'hcba !== (r26 | ($time && ((22'h643d ^ ( ( ~ ( r117)) < (r206 === ( ^ ( ( ! ( ( ! ( (11'h3b3 >= 27'h6d33)))))))))) / 6'h2c)))) > ((25'h6f8d >= 26'h4258) == ( ( & ( (( ( ! ( ( ~ ( ( ( | ( 32'h41ba)) + ( ( ! ( 14'h2b91)) + r190)))))) <= (26'h5532 + 14'h12cb)) == (r232 % ((21'h2891 / r76) + ( + ( ( ( & ( ((8'h43 <= 24'h19c2) > ( & ( 25'h70d2))))) + ((31'h65e0 !== (10'h18a ^ 1'h1)) < r191))))))))) / ((16'h16d0 ? 26'h5ce4 : (r66 ? ( ! ( r127)) : ((((((18'h6d90 ^ 19'h2911) % (18'h5898 * 3'h0)) && $stime) !== ( ( & ( ( ~ ( 25'h56ef)))) - ( | ( r124)))) * ( | ( ( ! ( (r62 ? r238 : (22'h5c72 <= 28'h4c3))))))) != ( | ( 22'h388d))))) | (((( ( + ( r248)) !== ((r240 % 30'h5a83) - r4)) + 31'h131) || r147) & ((r36 | (((((15'h5184 > 29'h7846) + 15'h4959) ^ (r123 * r200)) / ($time & ( + ( (8'hc8 & 9'h1db))))) > 5'hd)) / ((r86 > 29'h4da1) !== r118))))))))))); + #10; r222 = (r106 * 32'h1826); + #10; r88 = ( ( ! ( ((((r249 != 18'h6b91) > ( ! ( ((r65 == r236) & 7'h59)))) ? r146 : ((r162 === $time) <= r135)) > (( ( + ( 32'h2513)) !== r252) || r147)))) <= ((32'h371b == r72) < 5'h1f)); + #10; r131 = r22; + #10; r48 = ( ( & ( (((( ( - ( ((r9 - 30'h63a0) * r22))) | ( - ( r212))) ^ 10'h1d5) === ( ^ ( 14'h2dbb))) % (9'h178 % (r241 !== ( ( | ( ( ~ ( (((21'h280 !== ((29'h1c0a - (1'h0 + 2'h3)) / (26'h2be2 * (r98 && ( & ( 22'hac0)))))) | (17'h5864 || r147)) <= (r51 ? ( ^ ( r226)) : (r15 != ( | ( (8'hb6 && 6'h34)))))))))) < (9'h1bb != r114))))))) === r208); + #10; r217 = ( | ( (r7 || ((r98 === (r212 === ( ( ! ( $time)) | (6'h3 + 23'h6819)))) / (r154 >= ( & ( r135))))))); + #10; r145 = ((7'h5d > r79) != ( - ( r98))); + #10; r22 = ( ~ ( 22'h43eb)); + #10; r115 = r221; + #10; r239 = (r198 !== (10'h79 !== (12'h444 ^ ((r204 && r214) % ( ~ ( r7)))))); + #10; r170 = ((r185 % 25'h5b50) - r104); + #10; r139 = (( ( ^ ( (((29'h158a && r170) ? r64 : 26'h4955) - (r100 >= r61)))) * r136) | r122); + #10; r78 = 7'h10; + #10; r72 = r70; + #10; r145 = ( | ( (8'h86 && r159))); + #10; r123 = $stime; + #10; r220 = ( ! ( ( ~ ( ((((r79 === 12'hd3) && r55) % ((r1 <= ((r226 % (( ( | ( r107)) != r227) < (($stime < r242) != ( ! ( ( ( ! ( 29'h6b4e)) * (r221 || ( ( ! ( 29'h162a)) > 25'h45be)))))))) !== ((( ( ! ( ( | ( (r179 <= $stime))))) && 20'h7a52) & r249) < 29'h58eb))) & 25'h4a32)) == (r63 == r136)))))); + #10; r31 = 32'h3c62; + #10; r216 = (r148 != r198); + #10; r140 = r215; + #10; r227 = ((r246 ? $stime : r163) && (((( ( ~ ( r157)) + 13'h1de6) / 2'h1) !== (($time <= (r195 & ( ^ ( r121)))) && ( ( ~ ( r165)) * ((r124 !== 13'h9f1) && (r226 == (r79 <= ((r188 | ((((r70 >= (29'h4a7 % 2'h3)) < ((8'hba >= 4'h5) || 24'h394b)) !== r140) + $time)) / r68))))))) && r193)); + #10; r168 = 2'h3; + #10; r208 = r211; + #10; r196 = ((((r227 < 24'h299e) != 10'hac) && (((r16 && ((r10 ? ($time / $stime) : r229) >= ( & ( (( ( | ( ( ( | ( 15'h5c9d)) / ( ^ ( (r242 !== r117)))))) && r200) <= ( & ( ( + ( ( ! ( r228))))))))))) - (7'h2c != (( ( & ( 17'hd65)) ^ $time) + (r82 >= r124)))) ? ( ^ ( r222)) : ( & ( ( ^ ( ((r146 != $stime) ^ ( ! ( (r4 % ( ^ ( r114)))))))))))) ^ r88); + #10; r200 = 12'h3e9; + #10; r158 = (24'h2147 - 4'h4); + #10; r72 = r219; + #10; r101 = ( | ( (r104 + r252))); + #10; r98 = (27'h401a ^ ( | ( ( ( ~ ( 13'h74a)) * (( ( ^ ( r121)) ? 5'hf : ( ( ^ ( 17'h6a2d)) % 2'h3)) != (r43 === (32'h2ec9 % ( - ( ( ~ ( (($time !== ((21'h583a + ( & ( r117))) * r30)) <= r167)))))))))))); + #10; r57 = ( ^ ( r87)); + #10; r54 = ( ( + ( ((( ( - ( r109)) ? 6'h9 : r99) - 28'h6c8c) + ((((((25'h46be && 14'h16f3) > r158) / r249) % (r168 || (r95 === ( + ( (((((r204 % $stime) <= ( + ( (27'hb65 != 6'h1b)))) <= ((r139 && (11'h577 || 27'h5dbd)) + 1'h1)) || ((((13'h9d1 !== 22'h14cf) | (26'h101a + 23'h31a9)) | ((7'h4b - 26'h63f8) | (30'ha4d * 32'h760))) < ( ( ^ ( 3'h1)) < r111))) < (((r215 & 32'h4838) / ( ( ^ ( (24'h2d6f || 28'h4fde))) && ((4'hb <= 9'h24) & r112))) | (r97 === (r76 < 8'h76))))))))) ^ ( ^ ( ((26'h3743 || ( ( - ( ( ! ( ((3'h4 * ((7'h66 !== 32'h4200) & 14'h2b24)) ? ( - ( r57)) : 21'h6ef))))) <= r70)) | ((r159 <= r181) - ( ( + ( (r36 || (r49 != (r185 === ( ^ ( ( ! ( 10'h2dc))))))))) === r150)))))) >= ( | ( ( ( & ( ( ! ( 22'h416f)))) !== (r137 + ( | ( $time)))))))))) ^ r148); + #10; r44 = (11'h11 || 13'h99d); + #10; r213 = r254; + #10; r101 = 31'h6ed; + #10; r190 = ( ^ ( r133)); + #10; r222 = (32'h2008 >= 24'h68a3); + #10; r12 = r13; + #10; r235 = ( + ( (r42 / $stime))); + #10; r50 = ( ( ^ ( ((r251 <= ((27'h6eee > ( & ( (($time ? r43 : $time) !== (7'h36 !== ((((((23'h6f4 != 26'h7c8b) & (32'h5eeb < 25'h6227)) | $stime) * (((29'h6a61 === 11'h6bf) & (30'h6956 / 21'h637d)) > r209)) + ( | ( (($time % (22'h3516 ? 11'h405 : 6'h5)) % (11'h49d >= (4'he ^ 17'h9e1)))))) + r82)))))) & r152)) * ((((((r53 & r240) != ((((r146 === ((14'h1ccc - r221) % 1'h0)) !== ((( ( | ( 23'h24bd)) & r79) >= (26'h2a62 / 23'h59d6)) !== r94)) < ( ( ! ( ( ~ ( ((26'h1762 / 12'h3bb) === ( ~ ( 20'h2582))))))) > r104)) * r190)) != (21'h5a98 >= r53)) && ($time * 13'h1dc3)) / $time) - r217)))) < (( ( - ( ( + ( (2'h2 !== r32))))) != ( ( ~ ( ( & ( (r130 != ((29'hc97 - $time) ^ ( - ( r18)))))))) - r102)) + r33)); + #10; r224 = r199; + #10; r74 = 31'he64; + #10; r92 = ((( ( ^ ( ((r138 ? (((((r82 == (r128 * (r32 % (15'h7083 <= r219)))) > ( + ( ( ~ ( 31'h75c7))))) && $time) <= 2'h3) | 23'h7c7b) : r20) + ((25'h4238 >= (( ( ~ ( r30)) < r97) ? (((((24'h5cda + r34) === 31'h60c9) != r72) == 11'h5c8) | (r92 / r77)) : (r26 != r174))) % (( ( + ( (((13'h507 + $time) < (r230 < r79)) / (( ( - ( ( & ( (21'h77de >= 21'h595c))))) & (6'h29 == r159)) == r120)))) ? (( ( ^ ( ($stime % ( & ( (r44 ^ 19'h4868)))))) || 29'h425) != ((((((27'h3be5 <= 21'h73b3) >= 5'h1e) - ( ! ( (24'h14b5 | 12'h81f)))) != (((31'h6c1a >= 7'h66) != (21'h2b37 * 5'hc)) | 26'h1e08)) ? $time : ((r238 && 9'he4) | $time)) / $time)) : ($stime || 10'h2af)) | 30'h6f3b))))) != ( & ( ( & ( (30'h2102 - (r214 ^ (r148 != r173)))))))) || r12) + $time); + #10; r20 = (r109 ? (((((r205 * r142) - ($time && (14'h12d7 & (25'h300a ^ $stime)))) != 8'h46) || ( ~ ( ( ( + ( ( ~ ( ($stime < ( ! ( ( ^ ( (r127 + r51)))))))))) == (r175 % ( ! ( (((r70 == r189) > (((r1 !== 9'h40) != (5'h3 !== r198)) + (r221 ^ 30'h283b))) || 29'h1a0c)))))))) + (((r220 + (26'h5440 != (2'h1 == 6'h2e))) & r219) & 28'h5a06)) : (14'h1a0a < 6'h15)); + #10; r253 = ( ! ( 32'h3419)); + #10; r95 = 16'h3cbd; + #10; r49 = 2'h1; + #10; r17 = (r251 <= r61); + #10; r151 = 4'h7; + #10; r136 = (r253 || ((r68 <= 30'h5ad3) != (3'h0 % ( + ( 27'h5cc2))))); + #10; r35 = (r153 & (r74 | ( ( & ( r94)) <= r72))); + #10; r120 = (30'h3c55 + ((r48 || r173) & r231)); + #10; r214 = ( ( & ( (r168 % ((((28'h55b2 ^ ( ( ! ( 8'h4b)) === 11'h221)) < r217) != ( ( ~ ( ((r213 / ( + ( ( ( | ( (((18'h5f95 * 8'h91) || (7'h17 & 16'h8ab)) && r127))) == 16'h5aae)))) * ( + ( ((r109 == ((((18'h3972 + 25'h7165) == (4'h4 >= 7'h58)) * (6'h2a - (28'h4a9a + 16'h768d))) != (r130 !== ((11'h36b < 17'h7bb9) / 31'h65db)))) ? ( | ( r139)) : ( - ( 28'h5d29)))))))) !== (((15'h7581 < 5'hd) + ((((20'h61ac ^ r219) < 1'h0) | (r79 ^ r25)) * (r90 < $time))) - ( ^ ( ( - ( (( ( + ( ( + ( r130)))) == (( ( ~ ( r200)) >= 24'h433) < 1'h1)) + 17'h7ce2)))))))) ^ (( ( & ( ((r161 + ( & ( ( ( ^ ( r63)) * (((r201 & (13'h1fa9 || 2'h3)) * ( ^ ( r103))) * r28))))) | 1'h1))) === $stime) > ( ^ ( ( ! ( r165))))))))) >= ((( ( | ( 3'h6)) | r66) | 5'h8) ? ( - ( r24)) : (r227 / ( ^ ( ((( ( ~ ( (((r63 * ( ( & ( (r92 / (24'h565a + 12'h647)))) - (r124 < r138))) || ( - ( (18'h1d84 | ((r186 - 28'h4f76) | ( ( - ( 4'h5)) != 25'h57d1)))))) ^ ((r196 >= ( | ( r186))) ? ((32'h15b6 & (26'h458a > ( ! ( r103)))) / r171) : r99)))) || (($stime - (((((r64 | r129) / 18'h31eb) | $stime) & (1'h0 / r226)) != ( + ( r173)))) != r3)) % (r109 >= 9'h119)) + (((((20'hf4b ? ( & ( (16'h394b > ($time * ( + ( (16'h480 === 32'h42fb))))))) : 24'h56a7) ? 22'h5ab9 : r136) === 14'h2f0a) <= r83) % r134))))))); + #10; r223 = (r227 ^ ( ! ( ((28'heb ? ( + ( (r213 | (20'h18bc >= r78)))) : ( & ( 10'h333))) | ((r132 != r21) - (r23 | r235)))))); + #10; r70 = $time; + #10; r76 = (r49 / (((( ( - ( r188)) && r46) <= (r73 * r159)) || (r109 ^ ( & ( 13'h12a8)))) / (( ( - ( $stime)) > (r165 / ((25'h7b9e * ( - ( ( ^ ( (((r28 + (r247 > ( - ( (2'h0 % 10'h360))))) % 13'h48d) ? (29'h6a6f - 27'h5199) : 22'h2db7)))))) < 17'h6a8e))) >= ( ^ ( ( - ( 5'h3))))))); + #10; r184 = ( & ( ( & ( r95)))); + #10; r244 = ( | ( (12'hb7 / 9'hb9))); + #10; r239 = 19'h7f7c; + #10; r246 = (r224 != ((($time < 11'h493) !== (18'h148b - r178)) == (7'h4c < (r198 && ( | ( ((((((r140 & ( ~ ( (( ( - ( 15'h988)) | r21) || ( ( ^ ( 11'h5c4)) <= (20'h7942 >= 15'hca5)))))) % r6) && (($stime + 6'h16) > ( & ( 13'h76d)))) > ( ( - ( r13)) >= ( ( + ( 13'hc6a)) / (r247 * r180)))) >= (7'h20 || (( ( ! ( (((12'haae > 10'h15a) && 16'h4261) > r16))) & ((r100 / (r60 + (r99 / (27'h2093 - 8'hd5)))) - r234)) & ( ( ! ( $time)) === $stime)))) >= r31))))))); + #10; r208 = r57; + #10; r120 = 26'h5f9c; + #10; r176 = 5'h2; + #10; r205 = ( ^ ( 31'h6209)); + #10; r219 = (1'h0 * ( | ( r56))); + #10; r9 = 19'h2d05; + #10; r112 = ( ( ~ ( ( + ( ( ^ ( r163)))))) <= ( - ( ( | ( (r78 % ( ( + ( ( ! ( $time)))) != (31'h4aff * r79)))))))); + #10; r163 = r143; + #10; r20 = (((r127 | 17'h3217) ^ r11) || (8'ha2 != (r189 === r201))); + #10; r45 = ((r171 ^ ( ! ( (r42 === 5'he)))) >= 13'h1b72); + #10; r72 = ( ( | ( ( + ( r110)))) - 10'h189); + #10; r238 = $stime; + #10; r234 = r199; + #10; r247 = r34; + #10; r138 = r206; + #10; r245 = ( | ( r167)); + #10; r253 = (( ( | ( 14'h394d)) != (( ( ^ ( (((10'h1c6 == r212) ? ( + ( ( ~ ( r148)))) : r51) ? ( ( ^ ( $time)) < r233) : (7'h3c ^ ( ^ ( 17'h7cde)))))) !== ( ( | ( r155)) !== r64)) <= r224)) % (( ( + ( (r79 === ((1'h1 <= (r81 / r68)) + (r139 != ((r180 ? ( + ( ( ! ( ( ~ ( r46)))))) : (r171 % r237)) * r102)))))) % ( ^ ( ( | ( r78))))) <= (17'h2b1f ^ ((17'h3160 ^ r59) > (((6'h3 + $time) * ((7'h3f !== $stime) ^ 3'h2)) ^ ((r181 > (r221 | (((r187 != ( - ( (((14'h3871 - 31'h1261) < (8'had / 6'ha)) & r192)))) || $time) ? ( + ( r154)) : $stime))) + ( & ( 21'hfbf)))))))); + #10; r193 = ( & ( 15'h1a54)); + #10; r143 = r132; + #10; r161 = ($time & ( ~ ( (r107 ^ $stime)))); + #10; r47 = r197; + #10; r72 = ((($time == 14'h3eb9) !== r242) < 12'hee0); + #10; r167 = ( ( ! ( ( + ( r50)))) + ( ^ ( (r231 * ((6'h26 <= ( ( ~ ( ( ( + ( ( - ( ((( ( + ( (2'h1 != 19'h3fa5))) === ((6'h11 % 4'h1) / (10'h37a / 30'h1e1c))) * 9'h1b6) != ( ( & ( (8'h22 === 2'h1))) * $stime)))))) * 13'h1daa))) * r192)) === 26'h5f03))))); + #10; r99 = ( ~ ( ( ~ ( r218)))); + #10; r66 = ( ( ~ ( ((( ( ^ ( ((11'h73f ? ($stime === ( ~ ( r187))) : ((((20'h4125 + $stime) | r85) == r13) === ((22'h47f0 & (r164 % ( & ( ( + ( (23'h1879 + 19'h28f2))))))) >= 4'hf))) * $stime))) === ( ^ ( 29'h67cf))) || ( | ( r240))) > ( - ( (r78 + (23'h272f && (r132 != (( ( & ( (($stime === (((16'hed3 * 1'h0) < $time) && ((6'h2 / 9'h101) ? (21'h637d - 26'h4190) : r63))) * ((((9'haf & 14'h2ce7) ? (2'h2 & 9'h197) : 9'hd5) <= ( ( + ( 27'h32c1)) && (9'h147 - 5'h11))) >= (r159 == (r200 <= 28'h3218)))))) ^ ( - ( ( + ( (r202 ? ( ( - ( 14'h190e)) % ((16'hffb >= 26'ha6d) + (23'h3a46 | 3'h4))) : r83)))))) % r246))))))))) ? ( ( ! ( ( ^ ( ((r117 === r65) & (r92 & r196)))))) / ((((((16'h4c37 !== ((r124 * r17) < (r161 + ((r55 === ( ( ~ ( r209)) & 10'h3fc)) % ( ( & ( ((7'h2f + 18'h274a) * (31'h4de5 < 12'hb26)))) >= ( ^ ( ((14'h3161 >= 25'h7632) * (25'h2a76 * 8'he))))))))) > ( ! ( ((10'h390 - r60) % (((13'h649 + ( - ( r187))) !== r61) | 19'h40eb))))) >= (19'h49d9 <= r1)) & (( ( & ( r174)) == r111) / 18'h4732)) - ( ( ! ( ( | ( (r232 > r110))))) + (r73 < $stime))) <= r163)) : ( ^ ( ( ! ( ((((r195 | ( ( | ( 22'h41f9)) ? (23'h754e / 6'h28) : (25'h7d32 == (4'h6 < 5'h1f)))) & ( | ( ( ( ! ( r87)) - r71)))) - ( ^ ( r179))) | ( ( & ( (3'h2 > $stime))) + ( ! ( r165))))))))); + #10; r9 = (26'h2a2e != 15'h83d); + #10; r125 = 15'h6f76; + #10; r245 = ( | ( 28'h74c2)); + #10; r157 = r203; + #10; r166 = ((21'h29d6 != (($time - r242) == ( ( & ( (((11'h323 && ( ~ ( (1'h1 + ((r68 / (((13'h18c8 + 15'h2554) % r147) === (9'h40 === (4'he || 1'h0)))) ^ ($time & r189)))))) | 30'h4919) <= r151))) < (r137 ? (r50 % (( ( - ( $time)) >= 19'hbdc) * r216)) : ( ( ~ ( (6'h3d | $stime))) <= 1'h0))))) <= ( ( - ( r229)) >= 22'h3540)); + #10; r138 = r246; + #10; r163 = 32'h357d; + #10; r251 = ( & ( ( - ( r85)))); + #10; r83 = ((23'h34a0 <= r246) === 11'h66b); + #10; r183 = (r152 || (($time ? (21'h6ca4 > 28'h650) : r140) != ($stime !== 27'h1214))); + #10; r171 = 32'h6d44; + #10; r180 = 9'h180; + #10; r167 = (r199 ? ( | ( r212)) : 23'h3844); + #10; r221 = 12'h1b; + #10; r198 = (r72 ? ( ! ( r4)) : ( - ( r213))); + #10; r97 = ( & ( 14'h290e)); + #10; r164 = 5'h3; + #10; r33 = ((($stime || (7'h9 >= 9'h1bf)) < 14'hb12) < ((r246 / ((r116 ? 20'h1b7c : ((r189 + 17'h6013) - $time)) % $stime)) == (r100 ^ ( ( ~ ( (r189 !== r96))) & r40)))); + #10; r154 = ( ( - ( ((26'h562a && r20) && (r167 | ( ( & ( (r219 | (r185 ? (r114 || ($time / r206)) : (1'h0 < $stime))))) ^ 21'h4aae))))) / ( ~ ( (r253 % ($stime * 15'h5c88))))); + #10; r25 = (r5 & r139); + #10; r205 = ( ( ! ( ( ! ( 29'h4196)))) && ((13'h19ed != (r149 != (24'h3ba0 !== ((r142 != (30'h3f71 || r189)) - ((((r109 / ((8'h1b % ( ( | ( r115)) === ( & ( ( | ( 30'h3325)))))) || ( + ( 6'h6)))) !== r180) || 26'h3874) - ((((15'h26a5 - ((((10'h36c % 18'h1c8) && (3'h0 <= 1'h0)) !== ( & ( (30'h1ae9 - 29'h35cf)))) > 23'h24e9)) || ( & ( (r194 * r105)))) & $stime) % ( ! ( (( ( + ( ( | ( r76)))) | ( ( ! ( ((3'h5 - 10'h2ec) + (32'h73bf & 20'h6da1)))) <= r79)) / r48))))))))) % r32)); + #10; r180 = ( ( | ( ((12'hc2a % ( + ( (((4'he < r151) >= ( ! ( r53))) >= (((( ( ! ( ((7'h1a ? ((21'h60e7 / 26'h652f) / ( ! ( 16'h3871))) : (29'h69c9 && (29'h415d >= 15'h4e98))) && (((27'h4d27 === 5'h11) == (5'h7 / 27'h23f2)) > ( + ( ( ~ ( 18'h3e82)))))))) != ( ( ! ( ( ( - ( r245)) != r141))) < (((r169 && 18'h2377) * ((19'hf5c && 21'h6ee0) || 2'h3)) / r178))) * ((((((16'h46dc >= 13'h54) >= (17'h793b >= 25'h35db)) < ((27'h7f99 > 23'h7718) != (12'hc9e == 3'h3))) || ( ( & ( (17'h2856 !== 18'h357))) * r241)) && ( ( ~ ( ((12'hfd6 * 14'h2446) / r102))) || ( ^ ( (r18 ? r25 : r123))))) == 5'h13)) ^ r185) | r245))))) !== (((r52 && ($time == r43)) !== ((14'h101e < ( ( + ( ( & ( ( ( + ( r195)) !== r50))))) || ( - ( 20'h140)))) != ((r48 != (r78 >= 6'h1c)) | (9'h8c ^ ( | ( 29'h4eb7)))))) < (((r199 + 11'h4f4) || r190) != 19'h5fcb))))) !== (((($time == ( + ( 4'hf))) / ( + ( (24'h4ff8 * ( ( ! ( ( - ( (((((r11 | (11'h26b - 6'h39)) ^ r52) & (($stime % (15'h3778 == 15'h3a4a)) % $stime)) ? ( ^ ( (r49 > r191))) : ( ^ ( ( & ( ((15'h721d >= 11'h498) !== 13'h113c)))))) == r247))))) !== 15'h3ec5))))) === r154) | ( & ( ((31'h5377 && ((r11 || ((((r70 > (r202 !== r43)) ? (r221 >= (((r255 == $stime) < ( | ( ( - ( 23'h36a7))))) != (13'h1664 !== 32'h669a))) : r32) | (((7'h56 && 5'h1b) && (r106 == r168)) !== ( & ( ((22'h15c7 && (r210 ^ ( - ( 30'h3a9c)))) ^ (((6'h12 | 1'h0) - (24'h3128 * 26'h265)) === (31'h947 | (28'h7be5 & 31'h336f)))))))) & ((r91 + ( + ( 17'h1d47))) & (( ( | ( 28'h2f2)) && ( ^ ( 26'h663d))) <= ( ~ ( ( ! ( ( ! ( (19'h5235 % (19'h3511 - 32'h5628)))))))))))) || (13'h82e | (r15 || (20'h145c != ( ( & ( r228)) == ( ( - ( (((2'h3 ? 10'h31f : 8'h32) + ( & ( 13'h567))) % ( ( ^ ( 5'h2)) <= r117)))) != (r138 == ( & ( 14'h2b3a)))))))))) && (8'h99 ^ ( & ( (((((r157 + (30'h3c00 || $stime)) / r106) === ($stime !== ( + ( ((9'h1b1 > ((19'h62e4 * 22'h2f20) - r190)) / 25'h38aa))))) != r200) % 1'h1))))))))); + #10; r29 = ( + ( 8'h46)); + #10; r70 = (r45 ? ((2'h0 > ( & ( ((((28'h54b0 != ((r240 <= r248) - ((r123 <= 20'h4d70) ^ (r183 == (r182 == ( + ( ( + ( (11'h50f && 24'h6d05)))))))))) == (9'h45 % ( & ( (20'h5daa | (((( ( + ( 7'h66)) && (23'h2117 && 5'h15)) ? r134 : 14'h2f50) > r236) != r231)))))) ? 8'hbc : ( ( ! ( (( ( | ( ((r70 * (18'h58fb ? r227 : (19'h4843 <= 23'h461d))) === ( ( + ( (7'h30 ? 13'h163e : 8'hb2))) & ((16'h7ef || 18'hef9) > (28'h3502 < 25'h15a7)))))) - 9'h1ad) - (((r129 | r81) > r41) || (r76 <= 17'h6b6e))))) & ( | ( r125)))) < ( + ( r6)))))) | ((r75 === (4'h3 !== (24'h4381 <= r157))) + r112)) : r244); + #10; r146 = (( ( + ( ( ( - ( 16'h6078)) + (r112 - ( | ( 26'h4c17)))))) <= (( ( - ( ((r203 | (((12'h954 ? ($stime | ( ! ( ( - ( ($time && (9'h1b3 !== 19'h3078))))))) : $time) == 19'h4592) >= ( ( - ( $stime)) > ( - ( 12'h242))))) >= ( | ( ( ( & ( 32'h6a4c)) <= r3)))))) * (6'h14 == ( | ( r84)))) * (((((((11'h412 - r64) === ( | ( ((r141 || ( ^ ( ($time !== $time)))) ^ ( ~ ( $stime)))))) * r242) ? (31'h4adf | (r170 && (($stime * (r75 ^ (4'h3 < 23'h1faa))) >= 14'h2445))) : ( + ( r186))) === r215) % r60) % ( ( & ( (4'h0 || $time))) ^ r179)))) > r82); + #10; r219 = ( | ( (9'h14b * ( ^ ( ($stime ^ 12'h40c)))))); + #10; r164 = ( + ( ( - ( 5'h18)))); + #10; r197 = (r243 % (( ( & ( r105)) && 25'h3a96) * (23'h1425 | $stime))); + #10; r50 = (((r217 & r223) !== $time) + r81); + #10; r185 = (5'h6 | (r31 >= r194)); + #10; r133 = (r210 / r112); + #10; r203 = $stime; + #10; r178 = (14'h258f <= 14'h1fb1); + #10; r235 = ((12'h62a == ((r235 - r30) ^ 11'h49b)) ? ( & ( 13'h1647)) : r237); + #10; r46 = (r241 !== (((((13'h1466 === ( ~ ( (((r106 - r139) >= ( ^ ( r97))) + 12'h69d)))) >= ( & ( ((r94 ^ r251) <= 10'h389)))) && 28'h116b) <= ( | ( ((( ( ! ( ((20'h14cc != ( & ( r45))) != r97))) + $time) == (( ( + ( ( ~ ( (11'h166 % (r79 ^ 15'h4c0a)))))) % ((27'h4742 + (r109 !== ( ! ( (r238 >= ((13'h1bc2 ? 27'h21ab : 12'h85d) / r65)))))) ? (( ( - ( 22'h3a77)) && (r24 === (( ( + ( 24'h42f9)) <= (17'h1d1c >= 30'hed9)) - ( - ( 31'h3f78))))) <= (r57 * (r252 !== r239))) : r117)) % r175)) === r66)))) ? ((r105 - r24) >= ( & ( 6'h3f))) : ( ~ ( ((((r27 || ((r72 != r105) === 30'h5332)) <= r58) < $time) > (r11 ^ ( & ( 28'h5de6)))))))); + #10; r14 = r60; + #10; r158 = 3'h0; + #10; r92 = 16'h5cb0; + #10; r168 = (22'h238a == ((29'h737d % ((($stime || (r170 & ((((30'h2570 ? r246 : (r90 == (((2'h2 <= 11'hb6) > (20'h333a ? 3'h0 : 19'h4cae)) ? 8'he0 : ((16'h63a % 19'h22bd) - 12'h78c)))) != (r152 ? (r232 ? (((29'h7a19 >= 28'h28d5) ? (12'hdd9 + 19'h6d4d) : 16'h2ab9) ^ (r196 / (5'h6 >= 31'h55a4))) : r35) : r73)) <= (20'h4ff2 - ( - ( ( + ( ( | ( 3'h0)))))))) % 5'h15))) * r34) !== $time)) || ( & ( 17'h1c43)))); + #10; r31 = ( + ( ((3'h6 ^ ( ^ ( (r30 * r118)))) % ( ( - ( ((r131 <= r109) | ( ( - ( ($time % ( ! ( 1'h1))))) + $time)))) / r228)))); + #10; r227 = r113; + #10; r69 = ( + ( ( | ( ((r175 * r252) >= 32'h458))))); + #10; r160 = r171; + #10; r99 = r171; + #10; r26 = ($time >= (14'h3a77 ^ r235)); + #10; r188 = (( ( ! ( 19'hce0)) ^ (r32 ? (($stime <= (r90 * 15'h5bc5)) < r45) : (30'h7f25 == ( ( & ( ( ( ~ ( ((r137 / 22'h505) && r114))) || r72))) != r210)))) === (r220 | r130)); + #10; r210 = r221; + #10; r241 = ( ( + ( r24)) + 10'h16e); + #10; r24 = ( + ( (3'h1 + 27'h6ef2))); + #10; r104 = ( + ( ( ~ ( r45)))); + #10; r39 = 12'h75f; + #10; r136 = ( - ( 5'h18)); + #10; r186 = $stime; + #10; r202 = 3'h6; + #10; r216 = 25'h70bd; + #10; r208 = r211; + #10; r143 = ( + ( (r114 < r197))); + #10; r118 = ((r187 * r55) <= ( & ( ( - ( ( - ( ((( ( ~ ( 14'h3306)) % (((15'h67f + ($stime ^ ($stime % ( ^ ( ((11'h82 < 18'h7222) ^ ( + ( 25'h1c3b)))))))) - (($stime <= ( ! ( ( ( | ( (29'h166e % 7'h22))) >= 21'h608)))) <= ( ^ ( ($time > r232))))) | r5)) > 2'h2) !== r89)))))))); + #10; r234 = 9'h1f5; + #10; r254 = r6; + #10; r39 = ( & ( $stime)); + #10; r238 = ((15'h7bb7 >= 29'h70ec) & 22'hf47); + #10; r65 = ((1'h1 - r123) + 12'h583); + #10; r27 = (r221 == (r115 < r95)); + #10; r204 = ( | ( 19'h10b)); + #10; r232 = (r78 / ( ~ ( (((((8'hfa < r34) * ( + ( (r91 != ($time + (3'h2 ? (21'h3c7a / r249) : (r205 * ((r71 % r26) && r39)))))))) | (1'h0 >= 21'h4545)) != 31'h1e16) !== (((5'hc / $time) == 27'h150d) !== 5'h1))))); + #10; r213 = (r116 || ( ( ~ ( 9'h1cc)) !== (((23'h10fb == (((((21'h5703 * $time) >= ((29'h1274 !== ( ( - ( 11'h56d)) | ( & ( ( + ( (6'h2 + 17'h129b))))))) >= ((( ( - ( r163)) > ((23'h2857 != 30'h64e4) / 5'h5)) || (((23'h7345 <= 21'hdf7) == r154) | r189)) > r117))) > (( ( + ( ( + ( r118)))) / 26'h7e4) <= ( + ( ( - ( ( + ( (( ( ^ ( 16'h3752)) & (11'h2b && 4'he)) != ( & ( r63))))))))))) < ( ( ^ ( r82)) == ( ( ^ ( (( ( + ( $time)) ? ( ( ~ ( $stime)) > r142) : (13'h19ae | ((25'hced != 12'h2ff) !== 30'h290b))) && (r108 > r38)))) || (29'h7ef2 | r0)))) * $stime)) == ($time ? r49 : ((30'h1631 != (r225 - r55)) - (27'h3be0 ^ ($time ? 14'h2bb1 : r25))))) | 9'h1b9))); + #10; r198 = ($stime <= ((2'h0 || (r230 * r145)) || ((r31 !== 20'h7fd3) !== (r98 % ( ~ ( ( + ( (r110 <= $time))))))))); + #10; r8 = 19'h16e0; + #10; r145 = r147; + #10; r125 = r193; + #10; r182 = 1'h0; + #10; r253 = ((10'h2de <= (25'h4a1d & r188)) < r181); + #10; r44 = (24'h2e9a * (((( ( | ( ((r29 & r182) == r131))) / (15'h6295 | 3'h7)) > 14'had2) & r100) & (((7'h1b !== $time) % ((( ( - ( ( ( & ( ( + ( (r208 | ( & ( ( + ( (1'h0 + 30'h6481)))))))))) / 10'h170))) != r170) === ((r216 && 20'h7e5a) || ((r115 && ( ~ ( ( & ( (r68 | (r149 < (r233 < r186)))))))) | r213))) || 15'h789)) && (r59 !== 8'hfc)))); + #10; r229 = ( + ( r72)); + #10; r155 = 19'h69ae; + #10; r56 = r65; + #10; r84 = $stime; + #10; r76 = $stime; + #10; r235 = ((( ( ! ( r97)) | (29'h463 >= (( ( - ( r73)) | (r115 + $stime)) % 5'h15))) & ((r67 * ((( ( + ( ( ~ ( ( | ( (2'h0 !== ( + ( (((6'h37 === 20'h7815) - (8'h25 & 26'h1ee9)) != 26'h152d)))))))))) % (r128 || (r140 * ( - ( ((1'h0 > r41) == 17'h2448)))))) !== (12'h312 * ( ( ! ( r17)) > 6'h36))) + ((r172 ^ r139) / ( & ( r127))))) || 29'h6f45)) ? (((r63 ^ ((($stime === 15'h3fb7) != (( ( ~ ( ((( ( ~ ( r77)) != ($time <= ( | ( (19'h51cb != 19'hea0))))) ^ ( | ( (((27'h7fb1 ^ 22'h2e65) !== 8'h56) !== r60)))) + (8'h5b === (((10'h93 == r244) <= (14'h2620 && 3'h5)) <= ((22'h77e0 >= 13'hb60) && ( ^ ( ( ~ ( 20'h754a)))))))))) % ((((r106 & r242) | (9'h1a <= 17'h67c)) + ((r119 ^ (r206 < (r194 + (1'h1 <= 4'ha)))) ^ ( ~ ( r34)))) | ( & ( $stime)))) + ( ~ ( (r166 != 13'h147d))))) * ( - ( ( ( ~ ( 3'h0)) % ( ! ( r53))))))) ? (r102 == 3'h7) : (r60 * ( ( & ( ((r30 > (r33 <= ( | ( $stime)))) ? ((r17 <= ( ( - ( 22'h7b0a)) ? ( & ( (( ( - ( ( & ( 3'h0)))) & (r90 != (3'h1 !== 7'h2c))) / (((5'h14 ? 9'h1f : 21'h5421) & 27'h6fd6) || ( - ( r105)))))) : ((7'h52 + (r82 & (20'h218f !== (19'hca5 > 28'h7ddb)))) && ( | ( 15'h5da5))))) === 2'h1) : r187))) || 15'h3aa5))) & r178) : 16'h50d3); + #10; r104 = r197; + #10; r173 = 31'h818; + #10; r205 = (((r254 >= ( & ( (r51 || 10'h2bd)))) | ((12'h778 ? (4'h3 && ((r82 == r40) < ((r68 <= ( ! ( ($time % r254)))) - ( ^ ( ( - ( r179))))))) : (((r196 ^ ( ! ( ( + ( r61))))) == (18'h6246 < r0)) !== ( | ( 23'h7fe)))) ^ r0)) & ( ( & ( ( | ( (10'h31a ? ((15'h5a76 != ((r49 > ( ( | ( (r106 % (( ( ~ ( 28'h4fd6)) - ( + ( 29'h7066))) > ((27'hc41 === 28'hd4b) | (6'h2d & 8'h64)))))) && ((r242 <= 24'h2822) | $stime))) && r169)) != $stime) : r56))))) ^ ( | ( (r180 ^ r203))))); + #10; r237 = (((((4'h5 - ( ^ ( (((((((6'h27 ? ((2'h0 & 25'h3301) < (6'h25 | 9'h1ec)) : r223) | 31'h65e1) >= ((((31'h4659 + 17'h5965) < ( | ( 11'h631))) !== ( ~ ( $time))) * (($time / (10'h7d && 1'h1)) ^ 3'h1))) & 15'h5e87) ^ ( ( ^ ( r233)) && ( | ( 24'h3d10)))) == r49) > ( - ( 2'h0)))))) - 5'h8) && 32'h3aa2) ? r27 : 27'h7c25) ? (25'h6fc1 !== (r8 & (((r82 >= 27'h5432) === ((25'h1d79 < ( ^ ( 22'h53a7))) < r44)) / 2'h1))) : (r98 <= ((18'h56be === 13'h1971) % (r188 | r126)))); + #10; r72 = (r29 / ((4'ha - (( ( - ( ((r110 == (r68 != r28)) && 23'h1d5d))) !== $time) & ( ! ( ((32'h122 >= r161) | 16'h36a9))))) < $stime)); + #10; r215 = r150; + #10; r32 = (23'h22ba & r68); + #10; r251 = ((((((((( ( & ( ((( ( + ( r230)) || ( ~ ( (10'h214 - 8'hca)))) & 29'h64fb) * r148))) <= $stime) == $time) - ((((((r247 >= r170) > ((r209 - r248) | ( ( - ( 15'h2d06)) ? 1'h1 : (14'h2f73 | 25'h3e87)))) % ( ( | ( r170)) > (r2 === ($stime > $time)))) !== r98) / ( + ( ( | ( r156))))) + ( + ( 30'h1f05)))) != r171) === (23'h16f4 & (((( ( + ( ( ( + ( ((10'h176 % 27'h709d) !== r155))) || ( ^ ( ( ( & ( 8'hbc)) != ( ^ ( 18'h426a)))))))) === r80) !== 23'h72f3) != r118) ^ (r122 - ( ! ( (r57 * (25'h14f1 === (r168 / r149))))))))) | (r65 / $time)) == r250) ? r193 : r163) && 32'h1880); + #10; r16 = ( - ( ( - ( ( - ( r182)))))); + #10; r82 = r63; + #10; r173 = 30'h254b; + #10; r120 = (14'hd78 ^ r193); + #10; r133 = ((r37 != r131) ^ r221); + #10; r215 = ((25'hb1f || ( ( & ( (((((r198 | ((28'h6191 / 4'h2) > ( & ( ((((25'h4f79 | 26'h5a16) ^ (3'h2 > 21'h51e3)) * 21'h31e8) >= (r25 / 26'h3a40)))))) !== (r33 % ( - ( (((((15'h2a8c % 1'h0) + 32'h5653) + r172) || $time) ^ 23'h5215))))) == r173) != (23'h1aaa == (13'hccb ? r24 : (r86 && ((( ( ! ( (r126 !== (28'h2588 == 29'h7d09)))) == (24'h10c2 > 22'h5f23)) || ( ! ( ( - ( r16))))) % ( ( & ( r0)) ^ r129)))))) <= 3'h0))) - r115)) && ( ^ ( ( + ( ( ^ ( $stime))))))); + #10; r98 = r156; + #10; r129 = (((r44 <= (((r14 > ( - ( r236))) < ((23'h5704 > (r163 === ((r136 != ( ( | ( 16'h7a29)) >= 21'h19b8)) !== (31'h53bd <= r38)))) != ( & ( 24'h332a)))) > (((((((r75 >= 23'h659f) !== (29'h2824 > r29)) <= ( + ( r103))) - (r69 * ((r222 != ( & ( r11))) <= $time))) || (r252 - r29)) >= (9'h0 != 30'h7bb1)) || ( ^ ( (r204 != r33)))))) + $time) & (( ( ~ ( r161)) == 18'h371b) - ( ( + ( ( + ( ( + ( ($stime > 10'h349))))))) == $time))); + #10; r224 = (25'h3bb6 ^ ((r169 !== ( + ( (($time <= r231) ? 12'h7e7 : ( ( ^ ( ( ~ ( r186)))) >= ( ~ ( ((r202 && ( & ( (11'h3f4 > (r148 < 24'h6a71))))) <= r104)))))))) == (((2'h2 % (((r226 < 2'h3) | (((2'h0 + (8'h1 || 7'h52)) !== ((r234 | ((( ( ! ( 12'h2fa)) + 23'h54ed) >= ( ! ( ( - ( 6'h1e))))) >= r230)) != 20'h7209)) - (14'hc55 % (r243 != r235)))) & (10'h110 > r103))) == ( ! ( r102))) || $time))); + #10; r15 = r135; + #10; r18 = r148; + #10; r179 = 13'h807; + #10; r144 = r116; + #10; r100 = r116; + #10; r44 = $time; + #10; r133 = 8'h67; + #10; r119 = $time; + #10; r155 = ( ! ( ( + ( r55)))); + #10; r241 = (r252 == ($time || r154)); + #10; r162 = 21'h4542; + #10; r154 = 25'h3c0a; + #10; r172 = ( & ( r130)); + #10; r152 = ( ~ ( r25)); + #10; r229 = r1; + #10; r238 = $stime; + #10; r180 = 21'h942; + #10; r231 = r199; + #10; r39 = r247; + #10; r46 = (23'h5bc != 3'h0); + #10; r166 = ( | ( ( | ( (13'h8cd ^ (((r12 || ( ( | ( 10'h14b)) && 12'h430)) === r195) & (30'h28c0 % ( ~ ( 27'h521b))))))))); + #10; r23 = r20; + #10; r102 = ( ( | ( r216)) | 27'h7337); + #10; r223 = ((1'h0 > $time) % r228); + #10; r42 = ( ^ ( ((r181 === r129) && ((r204 !== ((r112 ^ ( ( | ( 9'h199)) <= (r75 == ( ( ! ( 28'h5b63)) < ( ~ ( ((r96 <= (((15'h6ad0 !== 13'h5a1) <= ( ~ ( 24'h2def))) == ( ( ^ ( 24'h146e)) / (28'h13b1 >= 11'h94)))) || ( + ( (( ( ! ( 27'h51f3)) > ( & ( 10'h2c7))) - ( ^ ( ( ! ( 1'h0)))))))))))))) == ( ( ^ ( (( ( ^ ( (((32'h4dc3 - (r216 - 27'h503c)) <= 11'h1fd) | ( | ( r46))))) && 22'h5f72) === r74))) !== (r190 / ((r33 || ( | ( ( ( + ( r53)) !== (28'h1cb9 || ( ( | ( (1'h1 && 27'h699))) * ( & ( (16'h3dd0 === 17'h5fae))))))))) ^ ( | ( 12'h1de))))))) < r38)))); + #10; r174 = ( & ( 12'h666)); + #10; r79 = ((r135 && r189) != ( | ( r186))); + #10; r150 = (3'h3 * ((r251 !== ((9'h1ef - $stime) - (( ( - ( ( - ( r49)))) || r241) == ((( ( - ( 32'h4db1)) == ((r247 !== ((($stime + ((16'h42ad != 23'h2b27) ? r203 : (17'h2b91 % 27'h7fd3))) + ( ( & ( ( | ( 12'ha1b)))) !== ((21'h4286 % 22'h536e) ^ 16'h6608))) ? $stime : 14'h380a)) | ( ~ ( ((r115 & ((r16 + (30'h5605 & 17'h245)) - 19'h4ee4)) !== 14'h899))))) != ( ( ! ( r204)) >= (r58 + ((1'h0 === 8'h8b) + ((((9'h10 === r7) / r217) <= 5'ha) * r254))))) == ( ( & ( 6'hd)) && 11'h440))))) ^ ( - ( (r27 & ((r177 === (r226 != $stime)) | 9'hf)))))); + #10; r248 = r209; + #10; r5 = r51; + #10; r21 = 12'h97c; + #10; r51 = ( ( | ( ( ! ( (r174 > ( ( - ( 8'h2a)) >= ( ( + ( (( ( ~ ( r65)) + 8'h41) ^ 28'h7bc3))) / (13'hf60 * r126)))))))) >= ( ( - ( $stime)) <= ((r14 ^ (r25 >= 10'h344)) & ( ( - ( 21'h2549)) <= ((22'h7049 > 4'hd) ^ r172))))); + #10; r158 = (r89 !== (( ( ^ ( ((r215 <= r205) * ((r142 % 15'hce6) < r253)))) | r84) + ( & ( (r75 > ( - ( ( ( ! ( ( | ( (r183 > 26'h7d82))))) >= ( ~ ( (((r79 % ((r124 === ((r168 * ( ~ ( 19'h6332))) <= ( + ( ( + ( 32'h4365)))))) & ( ( ! ( ( - ( ( + ( 31'h67f5)))))) && r70))) >= (1'h1 & ( ( | ( ( ! ( $time)))) != ( & ( 7'h57))))) + r71))))))))))); + #10; r180 = ((r27 ? ($time - ( - ( ( ^ ( r86))))) : r20) - (( ( ~ ( (( ( ~ ( (30'h1d1e == ($time == (23'h196b === r86))))) & (21'h7750 >= ( ( ~ ( ( ( ! ( ($stime == 25'h47c6))) % ($stime && r93)))) / ($stime && ((r237 || r84) ^ ( | ( ( + ( r121))))))))) % ( - ( ( ( + ( r158)) + r54)))))) == ( ( | ( 16'h315f)) >= ((((( ( + ( ( ~ ( r74)))) + 20'h7b7f) || ( & ( ( + ( 23'h4708))))) | (( ( & ( (4'h6 === r209))) || 13'h9c8) / r229)) ^ ( | ( ((4'hf ? 24'h4865 : 16'h6051) > (10'h250 <= 16'h354))))) || (r139 === (6'h3e <= 16'h59a))))) || (r80 ? (($time != ( ~ ( ( ~ ( (r243 ? ((28'h741c % r164) + ( & ( ((( ( & ( r252)) || 26'h14dd) && r76) % r123)))) : 12'h35b)))))) ? (18'h36a6 === r202) : (((((27'h473b | r219) * r121) | (r30 >= (( ( ! ( 21'h52b8)) != (3'h0 <= (r38 % (((4'hf === 17'h45ca) % ( - ( 15'haa3))) === ((20'h6ddf > 31'h6ad1) !== $stime))))) < r48))) > r110) >= 6'h3d)) : r163))); + #10; r72 = (( ( ~ ( ( ( ~ ( ( ( - ( ( & ( ( ^ ( r217)))))) | (r180 == r234)))) <= 24'h480a))) % $stime) !== (24'h5c74 > ((r244 | ( ( ~ ( (((((23'h971 / ( | ( (13'h121f <= ( ( - ( 28'h6b51)) >= (12'hcfc || 2'h1)))))) ? ((r11 | ( - ( 32'h450d))) > r254) : ( ~ ( $stime))) + (r74 & r104)) || ( - ( r235))) | ((12'hafb % r158) - 17'h7d6b)))) ^ r225)) ? ( ! ( ( ~ ( ((((((((((29'h532 <= 16'h3d4b) ? r138 : r213) || (16'h52cf > (10'hc9 + 1'h1))) || $time) >= 16'h2a91) | ( & ( ( ^ ( r43))))) < ( ^ ( ( | ( (r91 | 2'h3)))))) / r186) * ($time / (r182 != r171))) < (( ( ! ( 19'hf53)) % r173) ^ r90)))))) : $stime))); + #10; r162 = (13'h1684 !== 20'h5bae); + #10; r125 = $time; + #10; r65 = ((21'h5040 % ( & ( (r168 / (r250 * r214))))) <= (21'h5bf != ( ~ ( $time)))); + #10; r132 = 14'h1f62; + #10; r35 = ( ! ( ( - ( (((((((8'h0 % ((( ( - ( ((17'h4f6 || 23'h241d) * (24'h3ec2 <= 31'h7ec8)))) / $time) >= (r114 & r213)) == (10'h33f === r79))) ? ( ~ ( 16'h7540)) : ($stime || ((r144 - 20'h7607) !== ( & ( 6'h7))))) == ( ( ~ ( ( ^ ( (r251 / ( ( ~ ( $stime)) < (((12'hcdd & 7'h6f) && (18'h7be < 16'h51a7)) || ( ( ! ( 31'h5b74)) ^ r127)))))))) + r254)) - r158) === ( | ( 11'h317))) ^ (r88 - ( ^ ( (( ( ^ ( r179)) | ((r137 <= r77) === ($stime == ( ( + ( (r190 !== ( ! ( 24'h667d))))) ^ $time)))) / r135))))) | (((r151 || ( ^ ( $stime))) >= r38) == (((( ( + ( ( ( - ( 3'h5)) > (((((11'h7ed > 23'h4848) + (12'hbf8 / 5'hb)) ^ r115) && ((32'h4a9d | (30'h66c5 & 30'h3e62)) >= 22'h14fe)) > (((r54 | (19'h3af4 ? 20'h63c8 : 3'h6)) | ((5'h19 | 2'h0) >= ( ~ ( 2'h2)))) === ( ( ^ ( ( ~ ( 5'h1d)))) != (r8 == (27'h69be % 32'h3b05)))))))) > 17'h6896) <= $time) * 9'h17e) >= (r253 | r11)))))))); + #10; r42 = 16'hf15; + #10; r139 = ((( ( & ( (14'h3f9d === ( ^ ( 21'h5f2f))))) + 2'h2) % 22'h5b3c) !== ( | ( ((( ( ! ( r51)) / r88) ? 9'h1a3 : $stime) > 9'h194)))); + #10; r8 = ( ( & ( 20'h40b8)) ? ( ( + ( (( ( + ( ($time | ((3'h4 <= r197) == r234)))) != r4) - (r114 * 23'h46dc)))) % r68) : r172); + #10; r181 = ( - ( ($stime % (23'h1d8f && ( - ( ( ( ^ ( $time)) | (r108 & r26)))))))); + #10; r159 = (((18'h535a % r30) * r65) >= ((( ( & ( ((((((r105 || 31'h4634) * ((r174 == (r61 || ( & ( ( + ( 6'he)))))) <= r233)) / $stime) || (((20'h55e8 * 20'h57da) != 27'h10ab) && (((( ( ^ ( (25'h574b != 25'h59bb))) % ((5'h13 === 17'h4256) !== (28'h5ecc !== 1'h1))) <= ( | ( r173))) !== $stime) || (( ( ! ( ($time >= (12'h42c | 23'h60eb)))) % (($stime >= 14'h23de) == r219)) > r65)))) && (18'h7c43 !== r96)) != (( ( - ( ( ( - ( ((r100 ? ( & ( r142)) : ( - ( r30))) === r236))) < ( ! ( r38))))) | $stime) - (( ( | ( r68)) < ( ^ ( (29'h6ea5 === ((((10'h243 === 31'h625f) > ( ~ ( 26'h75a))) - r95) <= ( | ( (r92 === $stime)))))))) > ( & ( ($stime >= r76)))))))) | r92) ^ (10'h2f2 !== $stime)) >= r103)); + #10; r35 = (31'h1e3a * 13'h289); + #10; r50 = ( ( + ( ( ( - ( 13'h1945)) & ( | ( ( ! ( r128))))))) * (((($stime >= 7'h61) || (((( ( ! ( (r180 > r44))) * (($stime >= (( ( + ( r106)) == ( ~ ( 32'h59e7))) || 5'h9)) && 13'hcd)) < ( ( & ( 15'h5791)) === ( + ( ($time - (((( ( ~ ( 30'h6092)) & r184) + 31'h27e1) == ((31'h1dfa + 7'h68) != ( ~ ( 22'h10ab)))) & (16'h30ab / r158))))))) ? 12'hcb7 : (31'h4c6d !== (26'h4e33 < ((20'h1dcd / ((( ( & ( (23'h3c7c < 4'h6))) % ( ( | ( 18'h6b37)) / (31'h56e7 - 9'h1b5))) - r174) >= 12'h281)) !== (r100 * r11))))) ^ r201)) * ( | ( 21'h41a0))) <= r130)); + #10; r17 = ( & ( ( + ( r76)))); + #10; r99 = ( ~ ( ((((r50 + (((r49 / (($stime * $stime) >= ( | ( r137)))) > (r27 <= 9'h151)) / ((((((r222 > r101) % r93) + ( ^ ( (3'h2 || ( - ( 28'h2340)))))) == ( ( ^ ( (r62 | (r201 === $time)))) <= 18'h6c9e)) > ( | ( r235))) <= ( ( ^ ( (((22'h402 | 12'h9b) | r92) * (r181 / ((r17 & $time) > r160))))) != r20)))) & (((r109 >= ((r237 == ( ( + ( ((((27'h7c62 > 5'h10) || 28'h4e87) | ((17'h62af === 21'h4f4) < ( ! ( 22'h4838)))) >= $stime))) && 23'h2eb3)) ^ ( ( ^ ( (r112 < (r212 > 6'h3d)))) ^ ((( ( + ( 8'hcc)) && 22'h6bf5) >= (r109 <= (((8'h3a == 25'h11d) == 19'h19b8) / ( & ( $time))))) ^ (32'h174d % 31'h75c7))))) / ((r37 >= ( ( ! ( ( ~ ( (r0 <= ((r215 * 27'h649a) + 20'h7c51)))))) < r221)) !== ( ^ ( r159)))) === r133)) + (23'h38d1 ? ((($stime ? ( - ( ( - ( ( ( & ( ($time < r66))) ? r170 : (( ( ^ ( ((20'h6ff5 * 26'h4341) - r78))) / r196) < r246)))))) : ( ( + ( ( ( | ( ( ^ ( 18'h3e9)))) ? r129 : r245))) % ( ! ( r128)))) / $time) * r156) : 16'h1426)) == 9'h114))); + #10; r102 = ( ^ ( ( ^ ( ((r211 ^ (r229 === r249)) < (((r17 * r174) * r229) <= ( ( & ( 26'h56cf)) || $time))))))); + #10; r7 = r109; + #10; r195 = (r100 - r246); + #10; r248 = ( ! ( ((r14 === (((r120 > ( ( | ( r100)) !== ( ! ( 2'h2)))) > (( ( & ( 6'h18)) % ( | ( 1'h0))) && ( + ( r251)))) / ( ~ ( ((r233 - 24'h7a6a) / r56))))) === ( ( - ( r104)) != ( ^ ( 1'h0)))))); + #10; r160 = r14; + #10; r164 = r57; + #10; r26 = ( ~ ( r63)); + #10; r20 = 27'h7948; + #10; r33 = (((r235 > ( ( + ( ((22'h4078 % 28'h43d5) ^ ( ( | ( ( + ( r216)))) == r196)))) || (((14'h3a11 - $stime) == ((r45 - 5'h5) ^ ( ~ ( ( ( + ( (((((11'h70b | 19'h604f) > (29'h2b8 * 4'h8)) ^ r130) && ( ( & ( (13'h2b5 - 14'h34f9))) ^ ($stime < 10'ha5))) < r19))) * (((( ( ^ ( (7'h51 === 9'h7d))) / ( & ( r242))) * ( + ( (r120 * (31'h3f97 != 27'h5c58))))) & 6'h2f) < ( ( & ( r148)) ^ ( + ( 14'hfd5))))))))) == ( ! ( r231))))) + r248) && ((r48 | (r187 | (r221 == ((r42 & r204) == r140)))) < r15)); + #10; r221 = (16'h49d1 || (r58 + ( ( + ( ( ^ ( r240)))) > r5))); + #10; r245 = ($time | $time); + #10; r80 = r72; + #10; r47 = $stime; + #10; r43 = r104; + #10; r128 = r105; + #10; r253 = r67; + #10; r145 = r81; + #10; r126 = 15'h9eb; + #10; r24 = r162; + #10; r233 = $time; + #10; r182 = ( ! ( (($time ^ (r171 === 11'h452)) - r95))); + #10; r94 = r219; + #10; r231 = (((((r234 == r75) - ( ^ ( $time))) | ( ( & ( ((((( ( + ( ((((19'h3cbc != 29'h50b3) === r179) === $time) >= 31'h7c7b))) > ( ( & ( ((r174 & (3'h0 - 18'h4c8f)) / 23'h16fc))) !== ( | ( ( ^ ( ((32'h1b5c * 24'h1c03) > r120))))))) || (( ( ^ ( r53)) != ((((8'hec <= 9'h169) !== $stime) === ( ( - ( 16'h304e)) < (26'h3834 <= 18'h58bc))) ? 25'h6ca3 : 27'h60a2)) >= 7'h74)) - $stime) !== ( ( & ( (r193 <= r106))) && ( & ( ((9'hc || r173) != r85))))) / ( ~ ( ((r82 / 25'h5809) <= ((r166 % (10'he3 - ( ! ( ( ( ~ ( ( + ( 21'h5ea1)))) ? 32'h6caa : $stime))))) === (($time !== 15'h2f0c) > ((r134 && r13) & r131))))))))) < ((19'h706d && ($time & (($time === 18'h786a) <= 13'h1ed6))) ? (r176 == r217) : (r15 < (19'h4b23 ^ 20'h3584))))) ? 19'h46f1 : 16'h10bc) ^ (28'h57a5 >= ( | ( $stime)))); + #10; r64 = (((( ( & ( ((((19'h1c36 >= 27'h1fc7) ^ r191) <= 18'h479f) && ((((((17'h38f5 / 16'h7871) > r19) < ( ^ ( ( ( ! ( r255)) <= ((r196 / $time) ? ( & ( r91)) : $stime))))) - (15'hc67 ^ ( ( ! ( (( ( | ( 10'h2bd)) == (9'hba > 4'h8)) + r104))) >= ( & ( r46))))) !== ( ( & ( r158)) - (( ( & ( 27'h5bca)) ^ ( ~ ( r185))) === (r208 | ( ! ( (((31'h3393 && 24'h16f4) <= (14'he7a / 15'h3c50)) & r73))))))) != ( ( ! ( 5'h14)) >= ( ( ^ ( 25'h2f7f)) / r25)))))) + ((7'h32 ^ (( ( + ( ((((r171 == ( - ( (24'h24c9 != 27'h188c)))) % (21'h1cd3 !== ((21'h4f82 !== 5'h5) !== (30'h592c && 31'h4d6)))) & ( ( | ( 32'h10e6)) * (r51 < (2'h3 && ( ! ( 9'hb5)))))) >= ((( ( - ( r100)) + (r94 < (4'h9 - 19'h7687))) / 30'h3d99) < ((22'h1717 <= (30'h7a58 ? 23'h26de : (2'h3 * 32'h15f2))) + r226))))) || r220) ^ r147)) & r163)) && 25'h4a4b) === r71) | 13'h13da); + #10; r247 = ((r64 >= (6'h6 - 30'h1466)) < 10'h89); + #10; r80 = 19'h4198; + #10; r186 = r249; + #10; r95 = r153; + #10; r32 = 17'h76a7; + #10; r81 = ((r230 & r127) >= ( ( ^ ( r166)) == (20'h625d % r106))); + #10; r150 = r47; + #10; r16 = ( ( ! ( ( - ( r127)))) == (20'h2d74 ^ ((( ( & ( ( + ( ($time === ( | ( r121))))))) - r238) | ((26'h7f81 | r147) || (16'h564f & r121))) | 29'h30a3))); + #10; r159 = 7'h5; + #10; r50 = r178; + #10; r198 = (( ( ! ( $stime)) <= 30'h3341) >= ( ~ ( (14'h2cc8 && ((((r238 === ( - ( ((18'h3731 || (21'h6044 > r225)) + $stime)))) && $stime) < ( ( - ( ( & ( ( ( + ( ( ~ ( 31'h5c4f)))) * r224))))) / (( ( | ( 17'h3bc0)) / r141) & r154))) ^ ((r176 + ((18'h3d71 === r214) ^ ((($stime >= r179) | ( + ( 6'h28))) % ((r91 + ((r10 <= ($stime % ( ! ( $stime)))) & (( ( & ( (24'h274b + 5'h1e))) == 30'h4efa) - (r23 > r185)))) !== (((r236 <= ( ~ ( ($time ? (20'h6978 > 25'he4c) : (29'h18de | 13'h19a7))))) & (($time > ((27'h7cd5 || 10'h2d1) / ( | ( 7'h69)))) != (((18'h6172 | 19'h59d4) == (30'h4c9b && 19'h2001)) !== ((15'h73ea % 20'h1953) ? r244 : r76)))) % (r143 ? (r59 > ( ^ ( r141))) : ((19'h13f7 < ( ^ ( (26'h7eda ^ 1'h1)))) != r136))))))) && $stime)))))); + #10; r100 = (((($stime ? r212 : ((r115 >= 13'hd24) === (( ( & ( ( + ( (( ( + ( r7)) != ((((17'h3105 ^ 16'h5f7b) != 28'h7cd2) && 7'h2) / ((r122 ? (20'h5bb0 != 26'h66d1) : (32'h251d * 30'h1913)) === r221))) / 4'h6))))) ? ((r54 && (24'h50eb / 3'h0)) - (r249 | r87)) : (( ( ^ ( ( ( ~ ( ( - ( ((18'h165 !== 18'h7eb7) || (29'h26d4 && 5'h6)))))) && (r36 <= (r140 % ((13'h1b93 && 10'h97) - (9'he6 % 10'h30e))))))) * ( ! ( ((((4'h3 && (14'h151b || 32'h7a7e)) * r208) % ( ^ ( r215))) < ( ^ ( 29'h2bb1)))))) + ((r123 <= 29'h381e) >= ((r177 <= $time) && 22'h6707)))) > r183))) <= (((30'h2485 > (7'h5b * (((r8 != 27'h4ad2) & r75) == r104))) & ((r222 + r255) + 2'h1)) > 7'h48)) < r195) & (r232 + ( - ( ( | ( 5'hc)))))); + #10; r111 = $time; + #10; r220 = ( ( & ( 32'h47c4)) != ( ( ~ ( (($stime <= $stime) >= (r22 !== ( ( | ( 15'h82b)) | r125))))) - 20'h65a5)); + #10; r103 = ((r212 & (r10 != (2'h2 | (r201 - ( ! ( ( ^ ( (r100 && (r69 % (r86 + 25'h2418))))))))))) % ((5'h5 || 3'h7) & (( ( + ( ( & ( (r236 + ((r25 & ( & ( ( ( ~ ( (29'h682e + ( ~ ( (23'h4ffa % 5'h7)))))) == 32'h6eb2)))) < r202)))))) == ( ^ ( 7'h56))) % (32'h14d5 + ( - ( ((3'h7 | ((((( ( - ( 27'h237d)) != ( | ( ( | ( 25'h1e5a))))) ^ ( ( ^ ( (r244 === (28'h502d - 32'h2e48)))) / (r147 < r167))) && r42) > (( ( ^ ( (((18'h3679 === 24'h3b03) * (1'h1 - 17'h6b4)) | 3'h1))) != r141) < ( ( + ( 30'h1484)) & ( | ( (((6'h3b === 20'h4cb9) % (23'h7809 !== 5'h7)) > 23'h79ca)))))) <= ( ( ! ( r254)) - r79))) <= ( ( + ( (r25 && $time))) % ((((22'h51e6 && (r206 * $stime)) !== r38) | r148) - r127))))))))); + #10; r55 = r221; + #10; r206 = r156; + #10; r180 = ( ~ ( 16'h2225)); + #10; r67 = ( + ( (((r203 && r69) === r123) != r202))); + #10; r75 = (( ( | ( ( ( | ( r9)) < (11'h3d9 === ( ! ( ( ( ^ ( r99)) === r224))))))) == 28'h2fb6) && ((30'h8c3 - r134) < 23'h5849)); + #10; r217 = (18'h2761 % (r56 | (($time < (20'h6ce0 * ( - ( (r235 * (( ( - ( ( | ( ((((6'h3a + 29'h3b2e) == 12'h6d5) + r79) > (r156 && ((26'h257f == 2'h2) || (9'h72 == 16'h41d9)))))))) * ( ( ! ( ((r48 - ( + ( (2'h3 + 14'hb38)))) ? r166 : r136))) !== ( | ( ( + ( r74)))))) != ($stime > ((26'h39cb !== r112) % ( ( - ( r124)) == r221))))))))) < r23))); + #10; r14 = (r167 <= ( ! ( (r106 >= r22)))); + #10; r254 = (r246 + ((((r132 && ((( ( + ( 6'h0)) < r228) === (25'h5358 === ($stime % 15'h7d8d))) == r28)) || $stime) ^ (r24 * ( ^ ( 13'h402)))) && ( ( | ( ((r100 + $time) === r249))) != ((19'h52e8 - 16'ha15) & (((1'h0 <= 23'h39c8) % ((19'h3f6b > ($time & r181)) >= r47)) + (( ( + ( ( | ( 2'h2)))) === r63) == r48)))))); + #10; r231 = $stime; + #10; r198 = ((13'he17 === (( ( ~ ( ( ^ ( (r249 === ( | ( ((( ( ~ ( ( | ( ( ( ! ( 24'h53e3)) & (21'h3e5d != 22'h7f09)))))) >= r72) == r147) > ( & ( ( ~ ( (7'h5c == r217))))))))))))) != r206) && ( ( - ( ( & ( (r203 / r196))))) & ($stime ^ ((7'hf && 6'h13) < 31'h2e8e))))) <= ((r29 >= r103) == 29'h4b73)); + #10; r208 = (r245 * 21'h176); + #10; r232 = ( ! ( ( ^ ( (r195 <= r240))))); + #10; r120 = $stime; + #10; r25 = $stime; + #10; r36 = (( ( | ( ( - ( ( ( | ( r63)) & (( ( | ( 10'h279)) % ($stime != r51)) != ((( ( ! ( r108)) ? (r28 && (r75 / 13'h302)) : ( | ( (r19 == 27'h2750)))) - (r135 + r97)) || $stime))))))) && ( & ( 29'h78e2))) >= 9'h9c); + #10; r126 = 27'h5db1; + #10; r7 = 27'h61d3; + #10; r254 = ( ^ ( 6'h32)); + #10; r76 = r9; + #10; r106 = r11; + #10; r115 = ((r69 > r37) && (r35 == r169)); + #10; r190 = r31; + #10; r39 = ( + ( (15'h2c29 ? r216 : ((13'h928 != ((r216 | r94) / ( ! ( (r8 !== (r209 & 8'hc6)))))) + 29'h1e5d)))); + #10; r77 = r166; + #10; r211 = r156; + #10; r229 = (8'h6d >= ( ~ ( $time))); + #10; r219 = ((r171 ? r116 : 25'h2ba2) | r103); + #10; r178 = ( ( - ( (( ( - ( (r111 || r145))) ? ((( ( & ( r207)) + (r100 + (r85 / (29'h7a89 == 29'h73df)))) != (r191 === 30'h24b3)) >= (r163 == ((r136 % ( ( | ( (11'h78f && ( | ( (2'h1 >= ( ( - ( 10'h1d4)) > (7'h39 % 26'h14d3)))))))) + r43)) / ($stime >= r192)))) : (r211 === 10'h381)) != ( - ( 6'h1f))))) > (r63 !== ( ~ ( (r71 / 15'h32a7))))); + #10; r235 = ($stime === r52); + #10; r181 = ( ! ( (( ( & ( (r72 | ((r82 - (r122 - r110)) / 3'h1)))) > (1'h0 != ( & ( r117)))) % r35))); + #10; r115 = 31'h222c; + #10; r21 = 10'hbc; + #10; r202 = (( ( & ( $time)) > ((r141 || (28'h91 || ( - ( 25'ha3e)))) || ((r78 & ((r252 > ( ~ ( 2'h1))) > (r235 ^ $stime))) && ( & ( 9'hbc))))) == $time); + #10; r255 = ( & ( 30'h67f1)); + #10; r65 = 13'h342; + #10; r208 = ( & ( (9'h148 !== ((((r86 - r205) | 16'h10c7) + $stime) / (r145 / ( ^ ( ( & ( 24'h4f19))))))))); + #10; r25 = (r242 ? ( ( | ( (((((9'hab + (r120 & ((( ( + ( ( - ( r5)))) ? r90 : r232) % ( ( | ( (11'h6ec ? r150 : r41))) && 22'h5c1a)) !== ((12'hd86 * ((4'h5 + r76) * $stime)) != ((( ( | ( 28'h378b)) === 5'h11) != r235) >= 5'hb))))) != (((r232 !== ((r240 * r116) * ( ^ ( (((18'h6629 < 31'h6fe7) * (28'h76b ^ 11'h18d)) > 32'h79d2))))) % (17'h4ad6 ? r19 : 29'h25f7)) | 28'h695e)) <= r176) !== 3'h2) === (9'h14f !== ((r71 % ( - ( (r82 > ((6'h1b ^ ( & ( 22'h355c))) | 21'h4af7))))) != ( + ( (( ( & ( ( ( + ( $stime)) | r247))) <= 12'h5ff) | 5'h1a)))))))) < r124) : ( + ( 25'h1324))); + #10; r216 = 16'h6943; + #10; r223 = $time; + #10; r182 = r155; + #10; r64 = (r73 - 31'h2134); + #10; r254 = 9'hfb; + #10; r180 = ( ( & ( ((r246 < (( ( ! ( r9)) <= r190) >= r25)) % (r150 != 6'hf)))) + 13'h1361); + #10; r26 = (( ( | ( r12)) | r21) - ( ~ ( ( ( ~ ( r129)) % (r99 < (r227 != (17'h1614 && ((r18 >= ((r85 % (r91 | r23)) <= 21'h2add)) === ( ( - ( r175)) === 15'h60cd))))))))); + #10; r58 = (((26'h4eb6 >= r67) & ( ( - ( ((($stime < ( ^ ( 24'h5968))) != ( ( & ( ( ^ ( r173)))) <= (($stime * (( ( + ( ((r216 > $stime) & r144))) || r153) & ( | ( ( ^ ( $stime)))))) <= 22'h5feb))) % ( ( ^ ( r192)) + ( + ( 9'h140)))))) | 16'h6670)) === ( ! ( ( - ( ( - ( ( ( | ( ( + ( ( + ( r128)))))) / ((( ( - ( (4'h3 !== r13))) | r212) >= (r48 + (18'h2621 != ( ( ! ( (6'h2b | r84))) / ((( ( ! ( ( - ( 1'h1)))) + r38) && ( ! ( r39))) == 21'h46a))))) != $stime))))))))); + #10; r227 = 4'ha; + #10; r151 = r208; + #10; r180 = (((r193 || r112) & (r198 !== r202)) | r46); + #10; r81 = (((r224 <= 27'h4c16) ? ((r96 == ((($time % (r59 && r245)) !== 28'h5b91) < ( | ( ( ^ ( 22'h78)))))) + 30'h1c62) : (r225 < ((18'h2d37 < ( ( ~ ( ( ^ ( 25'h73f9)))) == 4'h5)) ? ((r158 & r216) - (r243 !== r243)) : 24'h2bb7))) > 1'h1); + #10; r143 = r52; + #10; r222 = (( ( ^ ( r10)) + (22'h3a15 && ( ( ^ ( r163)) < 4'h8))) != ( ! ( ((r119 % ((r184 || ((((((18'h62e0 ? ((r123 > r7) * ( ^ ( r81))) : ( + ( ( & ( r60))))) === ( ^ ( (2'h2 ? ((18'h261a - 14'h226f) !== (10'h88 / 25'h5b0e)) : ((16'h4605 * 22'h6ac6) == 14'h32ee))))) % ((r135 * 25'h303b) && 13'h143b)) % r94) & ( ^ ( r16))) * ( - ( ((((((r183 & r178) && ( ( ! ( 19'h2f4b)) * (31'h7e35 + 12'h73e))) > (((18'h5c0c === 28'hb1c) > (1'h1 || 5'h1a)) ^ r54)) ? r222 : 25'h54cf) | (r131 - (r248 & r78))) == 18'h5932))))) % r73)) < r194)))); + #10; r241 = $stime; + #10; r4 = ( ( & ( r125)) <= (r41 ? ((23'h312d != r35) > r184) : ((19'h2838 + r31) == 25'h25bc))); + #10; r65 = r4; + #10; r68 = r86; + #10; r46 = 2'h2; + #10; r123 = ((((r247 || ($stime | r248)) ? ( ~ ( ($time & (r73 === r43)))) : 5'h16) > 25'h4e87) == r2); + #10; r177 = $time; + #10; r15 = ( ^ ( r236)); + #10; r236 = 25'hdf4; + #10; r186 = ( ( ^ ( (r163 % ((r186 ^ ( ( ! ( $stime)) * $time)) && r104)))) | 21'h3b98); + #10; r238 = (r170 + 1'h0); + #10; r167 = r11; + #10; r47 = ( ~ ( (r164 !== (27'h2b93 | 19'h3f3)))); + #10; r152 = 13'h1ae6; + #10; r136 = 11'h27f; + #10; r87 = r50; + #10; r44 = (r105 && ( ~ ( (((( ( | ( $stime)) / ( - ( 21'h58a3))) * 18'h2973) > ( ( - ( $time)) ? (((15'h3f4c ^ (r180 - ((r233 * $stime) !== r28))) | 15'h4cb7) - (r234 * ( ( ^ ( 7'h4d)) > (((r200 && 23'h14a0) != r159) <= ((( ( & ( ( ~ ( $time)))) - r226) | 16'h45eb) - r22))))) : r232)) === r165)))); + #10; r85 = (r147 > r18); + #10; r231 = ((8'h94 ^ 4'h5) ? (((r200 || ((($stime & r75) && 11'h0) & 32'h44a8)) || r49) - ( ^ ( (r204 | r161)))) : ( ( + ( (14'h1ec9 === ( - ( ( & ( (16'h1ac3 == r40)))))))) <= (( ( - ( r196)) % ( | ( ((30'h5eb9 | ( ( ^ ( ( ^ ( (((((15'ha3e + 3'h1) & r235) & (31'ha50 ^ ( + ( 21'h1246)))) != 4'ha) != ( ^ ( (6'h11 != r84)))))))) / ( ( ~ ( (r199 - ((((19'h6553 + 29'h2692) - 11'h87) & r215) != r247)))) & r129))) <= 10'h2d8)))) ^ (r63 == r161)))); + #10; r243 = ( + ( ( ! ( ( ! ( ($stime >= r141))))))); + #10; r225 = ((r227 ^ ( ^ ( (((r211 != r246) != 1'h0) / ((r151 / (r189 - ((2'h0 ? ( | ( ((17'h15be != 25'h57cd) || r18))) : r130) <= r133))) > ( ( - ( r177)) & r100)))))) ^ (30'h29af ? r155 : r154)); + #10; r188 = r9; + #10; r20 = 7'h30; + #10; r47 = r47; + #10; r58 = r172; + #10; r25 = 14'h2732; + #10; r120 = r209; + #10; r234 = r122; + #10; r109 = 32'h6179; + #10; r220 = $stime; + #10; r62 = 20'hf98; + #10; r123 = 30'h434c; + #10; r157 = ((9'hdf !== r221) != (r158 ^ 27'h7b5b)); + #10; r118 = r28; + #10; r225 = $stime; + #10; r144 = (r5 == ( ( & ( $time)) < ( ( + ( 19'h1ed0)) != 2'h1))); + #10; r134 = ( ^ ( 4'h6)); + #10; r6 = ( - ( 21'h63eb)); + #10; r81 = ( + ( ((((( ( + ( (($stime != (( ( - ( (30'h417 * 9'hd2))) !== (r98 && (31'h2b9b >= ( - ( ( | ( 4'h2))))))) / ( ! ( 21'h3fae)))) * r7))) !== ( ! ( r89))) + (32'h6ea2 + r41)) % (6'h2b === ($stime - ((12'h589 || 3'h4) | (((31'h73e9 ? ( ( | ( ( ( - ( r222)) >= ($time + (13'h126a * 30'h491b))))) ? r80 : ( ! ( ( ( + ( (20'h15ba >= 20'ha2))) >= (1'h0 === 32'h7b25))))) : ( + ( ( ( + ( r171)) / 14'h2d54)))) === 20'h2b36) ^ r30))))) !== ( ( ^ ( (r242 - $time))) && ( | ( r56)))) * ( ( + ( ( ! ( 6'h35)))) >= (r1 - r197))))); + #10; r156 = 18'h31e3; + #10; r11 = ( ~ ( r46)); + #10; r140 = r153; + #10; r230 = $time; + #10; r221 = ( ( ! ( 4'hb)) >= 11'h400); + #10; r228 = 10'haa; + #10; r125 = ((17'h2e5c > ( ~ ( (r130 - r65)))) > ((r27 - (((r7 == ( | ( (((r242 || ( ~ ( r127))) * ( + ( ((((r163 >= (18'h76bb == 3'h1)) & r140) ? (r137 == ((19'h1a8 && 20'h4b97) == 22'h44f5)) : r210) ? ($time / 23'h2b69) : r56)))) <= (16'h5540 + ( ! ( r90))))))) !== r76) & ( ! ( (r21 < 31'hbd9))))) + r248)); + #10; r160 = ((25'h1e99 & ( - ( (((r104 & (r27 | (((17'h320e || r91) - (r111 != 31'h23ab)) !== r116))) % (( ( ! ( r132)) <= 21'h7a3d) || (((r78 != ( ( ! ( ( ~ ( ( ! ( ( ( ^ ( 8'h8)) != 3'h6))))))) < ((((r197 == $time) + ( | ( ( ^ ( 17'h4d54))))) && 6'h9) - ( ^ ( (( ( ! ( 7'h48)) % ( ! ( 8'h7e))) != (24'h38e3 || r47))))))) + r108) >= r183))) ^ r103)))) && 20'h1ff0); + $displayb("r0 = ",r0); + $displayb("r1 = ",r1); + $displayb("r2 = ",r2); + $displayb("r3 = ",r3); + $displayb("r4 = ",r4); + $displayb("r5 = ",r5); + $displayb("r6 = ",r6); + $displayb("r7 = ",r7); + $displayb("r8 = ",r8); + $displayb("r9 = ",r9); + $displayb("r10 = ",r10); + $displayb("r11 = ",r11); + $displayb("r12 = ",r12); + $displayb("r13 = ",r13); + $displayb("r14 = ",r14); + $displayb("r15 = ",r15); + $displayb("r16 = ",r16); + $displayb("r17 = ",r17); + $displayb("r18 = ",r18); + $displayb("r19 = ",r19); + $displayb("r20 = ",r20); + $displayb("r21 = ",r21); + $displayb("r22 = ",r22); + $displayb("r23 = ",r23); + $displayb("r24 = ",r24); + $displayb("r25 = ",r25); + $displayb("r26 = ",r26); + $displayb("r27 = ",r27); + $displayb("r28 = ",r28); + $displayb("r29 = ",r29); + $displayb("r30 = ",r30); + $displayb("r31 = ",r31); + $displayb("r32 = ",r32); + $displayb("r33 = ",r33); + $displayb("r34 = ",r34); + $displayb("r35 = ",r35); + $displayb("r36 = ",r36); + $displayb("r37 = ",r37); + $displayb("r38 = ",r38); + $displayb("r39 = ",r39); + $displayb("r40 = ",r40); + $displayb("r41 = ",r41); + $displayb("r42 = ",r42); + $displayb("r43 = ",r43); + $displayb("r44 = ",r44); + $displayb("r45 = ",r45); + $displayb("r46 = ",r46); + $displayb("r47 = ",r47); + $displayb("r48 = ",r48); + $displayb("r49 = ",r49); + $displayb("r50 = ",r50); + $displayb("r51 = ",r51); + $displayb("r52 = ",r52); + $displayb("r53 = ",r53); + $displayb("r54 = ",r54); + $displayb("r55 = ",r55); + $displayb("r56 = ",r56); + $displayb("r57 = ",r57); + $displayb("r58 = ",r58); + $displayb("r59 = ",r59); + $displayb("r60 = ",r60); + $displayb("r61 = ",r61); + $displayb("r62 = ",r62); + $displayb("r63 = ",r63); + $displayb("r64 = ",r64); + $displayb("r65 = ",r65); + $displayb("r66 = ",r66); + $displayb("r67 = ",r67); + $displayb("r68 = ",r68); + $displayb("r69 = ",r69); + $displayb("r70 = ",r70); + $displayb("r71 = ",r71); + $displayb("r72 = ",r72); + $displayb("r73 = ",r73); + $displayb("r74 = ",r74); + $displayb("r75 = ",r75); + $displayb("r76 = ",r76); + $displayb("r77 = ",r77); + $displayb("r78 = ",r78); + $displayb("r79 = ",r79); + $displayb("r80 = ",r80); + $displayb("r81 = ",r81); + $displayb("r82 = ",r82); + $displayb("r83 = ",r83); + $displayb("r84 = ",r84); + $displayb("r85 = ",r85); + $displayb("r86 = ",r86); + $displayb("r87 = ",r87); + $displayb("r88 = ",r88); + $displayb("r89 = ",r89); + $displayb("r90 = ",r90); + $displayb("r91 = ",r91); + $displayb("r92 = ",r92); + $displayb("r93 = ",r93); + $displayb("r94 = ",r94); + $displayb("r95 = ",r95); + $displayb("r96 = ",r96); + $displayb("r97 = ",r97); + $displayb("r98 = ",r98); + $displayb("r99 = ",r99); + $displayb("r100 = ",r100); + $displayb("r101 = ",r101); + $displayb("r102 = ",r102); + $displayb("r103 = ",r103); + $displayb("r104 = ",r104); + $displayb("r105 = ",r105); + $displayb("r106 = ",r106); + $displayb("r107 = ",r107); + $displayb("r108 = ",r108); + $displayb("r109 = ",r109); + $displayb("r110 = ",r110); + $displayb("r111 = ",r111); + $displayb("r112 = ",r112); + $displayb("r113 = ",r113); + $displayb("r114 = ",r114); + $displayb("r115 = ",r115); + $displayb("r116 = ",r116); + $displayb("r117 = ",r117); + $displayb("r118 = ",r118); + $displayb("r119 = ",r119); + $displayb("r120 = ",r120); + $displayb("r121 = ",r121); + $displayb("r122 = ",r122); + $displayb("r123 = ",r123); + $displayb("r124 = ",r124); + $displayb("r125 = ",r125); + $displayb("r126 = ",r126); + $displayb("r127 = ",r127); + $displayb("r128 = ",r128); + $displayb("r129 = ",r129); + $displayb("r130 = ",r130); + $displayb("r131 = ",r131); + $displayb("r132 = ",r132); + $displayb("r133 = ",r133); + $displayb("r134 = ",r134); + $displayb("r135 = ",r135); + $displayb("r136 = ",r136); + $displayb("r137 = ",r137); + $displayb("r138 = ",r138); + $displayb("r139 = ",r139); + $displayb("r140 = ",r140); + $displayb("r141 = ",r141); + $displayb("r142 = ",r142); + $displayb("r143 = ",r143); + $displayb("r144 = ",r144); + $displayb("r145 = ",r145); + $displayb("r146 = ",r146); + $displayb("r147 = ",r147); + $displayb("r148 = ",r148); + $displayb("r149 = ",r149); + $displayb("r150 = ",r150); + $displayb("r151 = ",r151); + $displayb("r152 = ",r152); + $displayb("r153 = ",r153); + $displayb("r154 = ",r154); + $displayb("r155 = ",r155); + $displayb("r156 = ",r156); + $displayb("r157 = ",r157); + $displayb("r158 = ",r158); + $displayb("r159 = ",r159); + $displayb("r160 = ",r160); + $displayb("r161 = ",r161); + $displayb("r162 = ",r162); + $displayb("r163 = ",r163); + $displayb("r164 = ",r164); + $displayb("r165 = ",r165); + $displayb("r166 = ",r166); + $displayb("r167 = ",r167); + $displayb("r168 = ",r168); + $displayb("r169 = ",r169); + $displayb("r170 = ",r170); + $displayb("r171 = ",r171); + $displayb("r172 = ",r172); + $displayb("r173 = ",r173); + $displayb("r174 = ",r174); + $displayb("r175 = ",r175); + $displayb("r176 = ",r176); + $displayb("r177 = ",r177); + $displayb("r178 = ",r178); + $displayb("r179 = ",r179); + $displayb("r180 = ",r180); + $displayb("r181 = ",r181); + $displayb("r182 = ",r182); + $displayb("r183 = ",r183); + $displayb("r184 = ",r184); + $displayb("r185 = ",r185); + $displayb("r186 = ",r186); + $displayb("r187 = ",r187); + $displayb("r188 = ",r188); + $displayb("r189 = ",r189); + $displayb("r190 = ",r190); + $displayb("r191 = ",r191); + $displayb("r192 = ",r192); + $displayb("r193 = ",r193); + $displayb("r194 = ",r194); + $displayb("r195 = ",r195); + $displayb("r196 = ",r196); + $displayb("r197 = ",r197); + $displayb("r198 = ",r198); + $displayb("r199 = ",r199); + $displayb("r200 = ",r200); + $displayb("r201 = ",r201); + $displayb("r202 = ",r202); + $displayb("r203 = ",r203); + $displayb("r204 = ",r204); + $displayb("r205 = ",r205); + $displayb("r206 = ",r206); + $displayb("r207 = ",r207); + $displayb("r208 = ",r208); + $displayb("r209 = ",r209); + $displayb("r210 = ",r210); + $displayb("r211 = ",r211); + $displayb("r212 = ",r212); + $displayb("r213 = ",r213); + $displayb("r214 = ",r214); + $displayb("r215 = ",r215); + $displayb("r216 = ",r216); + $displayb("r217 = ",r217); + $displayb("r218 = ",r218); + $displayb("r219 = ",r219); + $displayb("r220 = ",r220); + $displayb("r221 = ",r221); + $displayb("r222 = ",r222); + $displayb("r223 = ",r223); + $displayb("r224 = ",r224); + $displayb("r225 = ",r225); + $displayb("r226 = ",r226); + $displayb("r227 = ",r227); + $displayb("r228 = ",r228); + $displayb("r229 = ",r229); + $displayb("r230 = ",r230); + $displayb("r231 = ",r231); + $displayb("r232 = ",r232); + $displayb("r233 = ",r233); + $displayb("r234 = ",r234); + $displayb("r235 = ",r235); + $displayb("r236 = ",r236); + $displayb("r237 = ",r237); + $displayb("r238 = ",r238); + $displayb("r239 = ",r239); + $displayb("r240 = ",r240); + $displayb("r241 = ",r241); + $displayb("r242 = ",r242); + $displayb("r243 = ",r243); + $displayb("r244 = ",r244); + $displayb("r245 = ",r245); + $displayb("r246 = ",r246); + $displayb("r247 = ",r247); + $displayb("r248 = ",r248); + $displayb("r249 = ",r249); + $displayb("r250 = ",r250); + $displayb("r251 = ",r251); + $displayb("r252 = ",r252); + $displayb("r253 = ",r253); + $displayb("r254 = ",r254); + $finish(0); + end +endmodule diff --git a/ivtest/ivltests/comp1001_fail3.v b/ivtest/ivltests/comp1001_fail3.v new file mode 100644 index 000000000..902ef6d58 --- /dev/null +++ b/ivtest/ivltests/comp1001_fail3.v @@ -0,0 +1,33 @@ +/* + * This is a reduced example from comp1001 to demonstrate a problem + * in the Icarus Verilog code generator. If the left && argument is + * replaced with a single 1'b1 which should be logically equivalent + * this will work correctly. It appears that the width of the + * expression is being calculated incorrectly. + */ +module top; + reg [119:110] r163; + reg [192:162] r222; + + initial begin + r163 = 10'h17d; + + r222 = (1'b1 + (22'h3a15 && ((^r163) < 4'h8))) != 1'bx; + + // ... the subexpression ^r163 is the 1-bit value 1'b1 + // = (1'b1 + (22'h3a15 && ((1'b1) < 4'h8))) != 1'bx + // ... the operands of && are self determined, but the widths of the + // operands of < must match + // = (1'b1 + (22'h3a15 && (4'h1 < 4'h8))) != 1'bx + // ... The && is a 1'bit result. + // = (1'b1 + 1'b1) != 1'bx + // ... Operands of != are sized to max of i and j, namely 1 in this case. + // = 1'b0 != 1'bx + // = 1'bx + // ... but the result is 31 bits, so the result is... + // = 31'b0x + + if (r222 !== 31'b0x) $display("FAILED -- r222=%b", r222); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/comp1001_fail4.v b/ivtest/ivltests/comp1001_fail4.v new file mode 100644 index 000000000..52b10954b --- /dev/null +++ b/ivtest/ivltests/comp1001_fail4.v @@ -0,0 +1,21 @@ +/* + * This is a reduced example from comp1001 to demonstrate a problem + * in the Icarus Verilog code generator. If one addition argument is + * replaced with a 1-bit register (instead of the constant 1'b1), + * evaluation is postponed to vvp, which works correctly. It appears + * that the width of the adder is calculated incorrectly when part + * of a comparison, but only in constant-propagation mode. + */ +module top; + reg [30:0] r2; + reg r1=1; + + initial begin + r2 = (1'b1+1'b1) != 1'bx; + // r2 = (1'b1+r1) != 1'bx; + $displayb("r2 = ",r2); + + if (r2 !== 31'b0x) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/comp1001_fail5.v b/ivtest/ivltests/comp1001_fail5.v new file mode 100644 index 000000000..9126f9b58 --- /dev/null +++ b/ivtest/ivltests/comp1001_fail5.v @@ -0,0 +1,26 @@ +module top; + reg passed; + reg [7:0] res; + reg zero; + reg one; + initial begin + passed = 1'b1; + zero = 1'b0; + one = 1'b1; +// res = 1'b1 ? !1'b0/1'b0 : 1'b0; + res = !1'b0/1'b0; + if (res !== 8'bx) begin + $display("FAILED: compiler."); + passed = 1'b0; + end + +// res = one ? !1'b0/zero : zero; + res = !1'b0/zero; + if (res !== 8'bx) begin + $display("FAILED: run-time."); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/compare_bool_reg.v b/ivtest/ivltests/compare_bool_reg.v new file mode 100644 index 000000000..141624925 --- /dev/null +++ b/ivtest/ivltests/compare_bool_reg.v @@ -0,0 +1,11 @@ +module main; + + reg bool [31:0] idx; + + initial begin + idx = 0; + if (idx < 17) $display("PASSED"); + else $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/complex_lidx.v b/ivtest/ivltests/complex_lidx.v new file mode 100644 index 000000000..e4f5e23b8 --- /dev/null +++ b/ivtest/ivltests/complex_lidx.v @@ -0,0 +1,25 @@ +module main; + + parameter MAP = 16'h0123; + parameter VAL = 32'h44_33_22_11; + wire [31:0] value; + + generate + genvar m, n; + for (m = 0 ; m < 4 ; m = m+1) begin : drv + for (n = 0 ; n < 8 ; n = n+1) begin : drv_n + assign value[8*MAP[4*m +: 4] + n] = VAL[8*m+n +: 1]; + end + end + endgenerate + + initial begin + #1 $display("value = %h", value); + if (value !== 32'h11_22_33_44) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/con_tri.v b/ivtest/ivltests/con_tri.v new file mode 100644 index 000000000..7824c82a0 --- /dev/null +++ b/ivtest/ivltests/con_tri.v @@ -0,0 +1,76 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test the ability to resolve resolve tri-state drivers onto a single + * signal. Use multiple continuous assignments to a wire to create + * multiple drivers, and use the ?: operator to tri-state the driven + * value based on the sel value. + */ + +module main; + + wire [1:0] out; + + reg [1:0] sel = 2'bzz; + reg [1:0] v0 = 0; + reg [1:0] v1 = 1; + reg [1:0] v2 = 2; + reg [1:0] v3 = 3; + + assign out = (sel == 2'b00)? v0 : 2'bz; + assign out = (sel == 2'b01)? v1 : 2'bz; + assign out = (sel == 2'b10)? v2 : 2'bz; + assign out = (sel == 2'b11)? v3 : 2'bz; + + initial begin + + #1 if (out !== 2'bxx) begin + $display("FAILED -- sel==%b, out==%b", sel, out); + $finish; + end + + sel = 0; + #1 if (out !== 2'b00) begin + $display("FAILED -- sel==%b, out==%b, v0==%b", sel, out, v0); + $finish; + end + + sel = 1; + #1 if (out !== 2'b01) begin + $display("FAILED -- sel==%b, out==%b", sel, out); + $finish; + end + + sel = 2; + #1 if (out !== 2'b10) begin + $display("FAILED -- sel==%b, out==%b", sel, out); + $finish; + end + + sel = 3; + #1 if (out !== 2'b11) begin + $display("FAILED -- sel==%b, out==%b", sel, out); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/concat1.v b/ivtest/ivltests/concat1.v new file mode 100644 index 000000000..7b1b9e42b --- /dev/null +++ b/ivtest/ivltests/concat1.v @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test that the repeat expression of a concatenation can have + * a parameter expression in it. + */ +module test; + parameter addrbits=10; + parameter HiAdrsBitVal = { 1'b1, { (addrbits-1) { 1'b0 } } }; + initial begin + if ($sizeof(HiAdrsBitVal) != 10) begin + $display("FAILED -- $sizeof(HiAdrsBitVal) is %d", + $sizeof(HiAdrsBitVal)); + $finish; + end + $display("HiAdrsBitVal=%b, size=%d", + HiAdrsBitVal, + $sizeof(HiAdrsBitVal)); + $display("PASSED"); + end // initial begin + + +endmodule // test diff --git a/ivtest/ivltests/concat2.v b/ivtest/ivltests/concat2.v new file mode 100644 index 000000000..38c4aaa10 --- /dev/null +++ b/ivtest/ivltests/concat2.v @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This tests that parameters can be used in concatenations if + * the expression it represents has definite width. This test + * is based on PR#282. + */ + +module t; + +parameter + SET = 1'b1, + CLR = 1'b0, + S1 = 2'd1, + HINC = 3'd4; + +//bit signif 12:11, 10 , 9 , 8 , 7, 6 , 5 , 4 , 3 ,2:0 +parameter + x = {S1,CLR,CLR,CLR,CLR,SET,SET,CLR,CLR,HINC }; + +initial begin + $display("x=%b, $sizeof(x)=%d", x, $sizeof(x)); + if (x !== 13'b0100001100100) begin + $display("FAILED -- x is %b", x); + $finish; + end + + if ($sizeof(x) != 13) begin + $display("FAILED -- x is %d'b%b", $sizeof(x), x); + $finish; + end + + $display("PASSED"); + +end + +endmodule diff --git a/ivtest/ivltests/concat3.v b/ivtest/ivltests/concat3.v new file mode 100644 index 000000000..a0bdc62b5 --- /dev/null +++ b/ivtest/ivltests/concat3.v @@ -0,0 +1,306 @@ +// Explore how procedural concatenations work in various contexts. +// Some of the checks are specific to the 1364-2005 standard. +// +// Cary R. cygcary@yahoo.com + +module main; + reg pass; + reg [31:0] a_c, b_c, c_c, d_c, a_r, b_r, c_r, d_r; + reg [127:0] y_c; + integer seed, fres; + // These will have the following value depending on the order. + // 1 = LSB->MSB, 2 = MSB->LSB, 3 = indeterminate. + integer sorder, uorder; + + initial begin + pass = 1'b1; + + /********** + * Try to find the order using $random. + **********/ + // Start from a known place. + seed = 0; + y_c = {$random(seed), $random(seed), $random(seed), $random(seed)}; + a_c = y_c[31:0]; + b_c = y_c[63:32]; + c_c = y_c[95:64]; + d_c = y_c[127:96]; + + // Make the reference values in a known order. + seed = 0; + a_r = $random(seed); + b_r = $random(seed); + c_r = $random(seed); + d_r = $random(seed); + + if (a_c === a_r && b_c === b_r && c_c === c_r && d_c == d_r) begin + $display("Concatenation of system functions is LSB -> MSB."); + sorder = 1; + end else if (a_c === d_r && b_c === c_r && c_c === b_r && d_c == a_r) begin + $display("Concatenation of system functions is MSB -> LSB."); + sorder = 2; + end else if ((a_c === a_r || a_c === b_r || a_c === c_r || a_c == d_r) && + (b_c === a_r || b_c === b_r || b_c === c_r || b_c == d_r) && + (c_c === a_r || c_c === b_r || c_c === c_r || c_c == d_r) && + (d_c === a_r || d_c === b_r || d_c === c_r || d_c == d_r)) + begin + $display("Concatenation of system functions is indeterminate."); + $display(" check:",, d_c,, c_c,, b_c,, a_c); + $display(" ref.:",, d_r,, c_r,, b_r,, a_r); + sorder = 3; + end else begin + $display("FAILED: system function concatenation order."); + $display(" check:",, d_c,, c_c,, b_c,, a_c); + $display(" ref.:",, d_r,, c_r,, b_r,, a_r); + pass = 1'b0; + end + + /********** + * Try to find the order using ufunc(). + **********/ + // Start from a known place. + fres = 0; + y_c = {ufunc(0), ufunc(0), ufunc(0), ufunc(0)}; + a_c = y_c[31:0]; + b_c = y_c[63:32]; + c_c = y_c[95:64]; + d_c = y_c[127:96]; + + // Make the reference values in a known order. + fres = 0; + a_r = ufunc(0); + b_r = ufunc(0); + c_r = ufunc(0); + d_r = ufunc(0); + + if (a_c === a_r && b_c === b_r && c_c === c_r && d_c == d_r) begin + $display("Concatenation of user functions is LSB -> MSB."); + uorder = 1; + end else if (a_c === d_r && b_c === c_r && c_c === b_r && d_c == a_r) begin + $display("Concatenation of user functions is MSB -> LSB."); + uorder = 2; + end else if ((a_c === a_r || a_c === b_r || a_c === c_r || a_c == d_r) && + (b_c === a_r || b_c === b_r || b_c === c_r || b_c == d_r) && + (c_c === a_r || c_c === b_r || c_c === c_r || c_c == d_r) && + (d_c === a_r || d_c === b_r || d_c === c_r || d_c == d_r)) + begin + $display("Concatenation of user functions is indeterminate."); + $display(" check:",, d_c,, c_c,, b_c,, a_c); + $display(" ref.:",, d_r,, c_r,, b_r,, a_r); + uorder = 3; + end else begin + $display("FAILED: user function concatenation order."); + $display(" check:",, d_c,, c_c,, b_c,, a_c); + $display(" ref.:",, d_r,, c_r,, b_r,, a_r); + pass = 1'b0; + end + + if (sorder != uorder) begin + $display("WARNING: system functions and user functions have a ", + "different order."); + end + + /********** + * Check to see if extra system functions are called and ignored. + * We do not care about the order for this test. + **********/ + // Start from a known place. + seed = 0; + // You must run the extra $random(), but drop the result. + c_c = {$random(seed), $random(seed), $random(seed), $random(seed), + $random(seed), $random(seed)}; + a_c = $random(seed); + + // Make the reference values in a known order. + seed = 0; + a_r = $random(seed); + a_r = $random(seed); + a_r = $random(seed); + a_r = $random(seed); + a_r = $random(seed); + a_r = $random(seed); + a_r = $random(seed); + + if (a_c !== a_r) begin + $display("FAILED: extra system functions in a concat. are not run."); + pass = 1'b0; + end + + /********** + * Check to see if extra user functions are called and ignored. + * We do not care about the order for this test. + **********/ + // Start from a known place. + fres = 0; + y_c = {ufunc(0), ufunc(0), ufunc(0), ufunc(0), ufunc(0), ufunc(0)}; + + if (fres != 6) begin + $display("FAILED: extra user functions in a concat. are not run."); + pass = 1'b0; + end + + // Icarus handles this in a different way so check it as well. + // Start from a known place. + fres = 0; + y_c = check_64({ufunc(0), ufunc(0), ufunc(0)}); + if (fres != 3) begin + $display("FAILED: extra ufunc in a concat. as an argument are not run."); + pass = 1'b0; + end + + /********** + * Check to see if a system function replicated 0 times is done correctly. + **********/ + // Start from a known place. + seed = 0; + // You must run the zero replication system call and then ignore it. + a_c = {{0{$random(seed)}}, $random(seed)}; + a_c = $random(seed); + + // Make a reference value. + seed = 0; + a_r = $random(seed); + a_r = $random(seed); + a_r = $random(seed); + + if (a_c !== a_r) begin + $display("FAILED: zero repl. system functions in a concat. are not run."); + pass = 1'b0; + end + + /********** + * Check to see if a user function replicated 0 times is done correctly. + **********/ + // Start from a known place. + fres = 0; + // You must run the zero replication user call and then ignore it. + a_c = {{0{ufunc(0)}}, ufunc(0)}; + + if (fres != 2) begin + $display("FAILED: zero repl. user functions in a concat. are not run."); + pass = 1'b0; + end + + /********** + * Check a simple replication of $random(). + **********/ + // Start from a known place. + seed = 0; + // This must run $random() only once. + y_c = {4{$random(seed)}}; + a_c = y_c[31:0]; + b_c = y_c[63:32]; + c_c = y_c[95:64]; + d_c = y_c[127:96]; + + // Start from a known place. + seed = 0; + a_r = $random(seed); + b_r = a_r; + c_r = a_r; + d_r = a_r; + + if (a_c !== a_r || b_c !== b_r || c_c !== c_r || d_c !== d_r) begin + $display("FAILED $random() replication, each replication is different."); + pass = 1'b0; + end + + /********** + * Check a replication of ufunc(). + **********/ + // Start from a known place. + fres = 0; + // This must run ufunc() only once. + y_c = {4{ufunc(0)}}; + a_c = y_c[31:0]; + b_c = y_c[63:32]; + c_c = y_c[95:64]; + d_c = y_c[127:96]; + + // Start from a known place. + fres = 0; + a_r = ufunc(0); + b_r = a_r; + c_r = a_r; + d_r = a_r; + + if (a_c !== a_r || b_c !== b_r || c_c !== c_r || d_c !== d_r) begin + $display("FAILED ufunc() replication, each replication is different."); + pass = 1'b0; + end + + /* + * A concatenation as an argument needs to pad or select as needed. + * We only check ufunc since it should be the same as $random and + * it has been tested above. + */ + + /********** + * Check that a concat is zero extended. + **********/ + // Start from a known place. + fres = 0; + y_c = check_64({ufunc(1)}); + a_c = y_c[31:0]; + b_c = y_c[63:32]; + c_c = y_c[95:64]; + d_c = y_c[127:96]; + + // Start from a known place. + fres = 0; + a_r = ufunc(1); + b_r = 32'h0; + c_r = 32'h0; + d_r = 32'h0; + + if (a_c !== a_r || b_c !== b_r || c_c !== c_r || d_c !== d_r) begin + $display("FAILED padded user function concatenation."); + $displayh(" check:",, d_c,, c_c,, b_c,, a_c); + $displayh(" ref.:",, d_r,, c_r,, b_r,, a_r); + pass = 1'b0; + end + + /********** + * Check that a $signed concat is sign extended. + **********/ + // Start from a known place. + fres = 0; + y_c = check_64($signed({ufunc(1)})); + a_c = y_c[31:0]; + b_c = y_c[63:32]; + c_c = y_c[95:64]; + d_c = y_c[127:96]; + + // Start from a known place. + fres = 0; + a_r = ufunc(1); + b_r = 32'hffffffff; + c_r = 32'h0; + d_r = 32'h0; + + if (a_c !== a_r || b_c !== b_r || c_c !== c_r || d_c !== d_r) begin + $display("FAILED sign padded user function concatenation."); + $displayh(" check:",, d_c,, c_c,, b_c,, a_c); + $displayh(" ref.:",, d_r,, c_r,, b_r,, a_r); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + + function [63:0] check_64; + input [63:0] in; + check_64 = in; + endfunction + + // This user function has a side effect (fres) so the result is call + // order dependent. + function integer ufunc; + input in; + begin + if (in) fres = fres - 1; + else fres = fres + 1; + ufunc = fres; + end + endfunction +endmodule diff --git a/ivtest/ivltests/concat4.v b/ivtest/ivltests/concat4.v new file mode 100644 index 000000000..073142c26 --- /dev/null +++ b/ivtest/ivltests/concat4.v @@ -0,0 +1,23 @@ +module top; + // These should create two ufunc calls each and the zero replication one + // will not be connected to anything. + wire [31:0] var1 = {{0{ufunc(0)}}, ufunc(0)}; + wire [31:0] var2 = {ufunc(0), {0{ufunc(0)}}}; + integer fres; + + initial begin + #1; + if (fres != 4) $display("FAILED, expected fres = 4, got %0d", fres); + else $display("PASSED"); + end + + function integer ufunc; + input in; + begin + if (fres === 32'bx) fres = 0; + if (in) fres = fres - 1; + else fres = fres + 1; + ufunc = fres; + end + endfunction +endmodule diff --git a/ivtest/ivltests/concat_zero_wid_fail.v b/ivtest/ivltests/concat_zero_wid_fail.v new file mode 100644 index 000000000..dfda7575a --- /dev/null +++ b/ivtest/ivltests/concat_zero_wid_fail.v @@ -0,0 +1,7 @@ +module top; + reg [7:0] result; + + initial begin + result = {{0{1'b1}}}; // This fails concatination has zero width. + end +endmodule diff --git a/ivtest/ivltests/concat_zero_wid_fail2.v b/ivtest/ivltests/concat_zero_wid_fail2.v new file mode 100644 index 000000000..d5e40ccb4 --- /dev/null +++ b/ivtest/ivltests/concat_zero_wid_fail2.v @@ -0,0 +1,17 @@ +module top; + + reg [2:0] bar = 1; + wire [3:0] foo; + + assign foo = { 1'b1, 0 ? 3'd0 : bar[2:0] }; + + initial begin + #1 if (foo !== 4'b1001) begin + $display("FAILED bar=%b, foo=%b", bar, foo); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/cond_band.v b/ivtest/ivltests/cond_band.v new file mode 100644 index 000000000..256c9a633 --- /dev/null +++ b/ivtest/ivltests/cond_band.v @@ -0,0 +1,34 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test some subtleties of bitwise and and if condition expressions. + */ +module test; + reg [31:0] c; + initial begin + c = 13; + if (c & 4) + begin + $display("PASSED"); + $finish; + end + $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/cond_wide.v b/ivtest/ivltests/cond_wide.v new file mode 100644 index 000000000..48036bebc --- /dev/null +++ b/ivtest/ivltests/cond_wide.v @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This progam catches the case where the truth value is really the + * reduction-OR of the condition expression, and not just the low bit. + */ +module test; + + reg [1:0] foo = 2'b10; + + initial #1 begin + while (foo) begin + $display("PASSED"); + $finish; + end + $display("FAILED -- foo = %b", foo); + end + +endmodule // test diff --git a/ivtest/ivltests/cond_wide2.v b/ivtest/ivltests/cond_wide2.v new file mode 100644 index 000000000..39871bae7 --- /dev/null +++ b/ivtest/ivltests/cond_wide2.v @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module foo; + + reg [2:0] cond; + reg test; + + initial begin + cond = 0; + test = cond ? 1'b1 : 1'b0; + + if (test !== 1'b0) begin + $display("FAILED -- cond=%b, test=%b", cond, test); + $finish; + end + + cond = 1; + test = cond ? 1'b1 : 1'b0; + + if (test !== 1) begin + $display("FAILED -- cond=%b, test=%b", cond, test); + $finish; + end + + cond = 2; + test = cond ? 1'b1 : 1'b0; + + if (test !== 1) begin + $display("FAILED -- cond=%b, test=%b", cond, test); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/condit1.v b/ivtest/ivltests/condit1.v new file mode 100644 index 000000000..5fa7fe3f9 --- /dev/null +++ b/ivtest/ivltests/condit1.v @@ -0,0 +1,46 @@ +`begin_keywords "1364-2005" +/* + * This tests the synthesis of a case statement that has an empty case. + */ +module main; + + reg bit, foo, bar; + + // Combinational device that sends 1 or 0 to foo, to follow bit. + // This tests the special situation that the if condition only sets + // some of the bits that the process as a whole sets. This is OK if + // the bits that are sometimes not set are covered elsewhere. + always @* + begin + foo = 0; + bar = 0; + + if (bit) + foo = 1; + else + bar = 1; + end + + (* ivl_synthesis_off *) + initial begin + bit = 0; + + # 6 $display("bit=%b, foo=%b, bar=%b", bit, foo, bar); + if (bit !== 0 || foo !== 0 || bar !== 1) begin + $display("FAILED"); + $finish; + end + + bit <= 1; + #10 $display("bit=%b, foo=%b, bar=%b", bit, foo, bar); + if (bit !== 1 || foo !== 1 || bar !== 0) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main +`end_keywords diff --git a/ivtest/ivltests/conditsynth1.v b/ivtest/ivltests/conditsynth1.v new file mode 100644 index 000000000..014a3a1b3 --- /dev/null +++ b/ivtest/ivltests/conditsynth1.v @@ -0,0 +1,77 @@ +module main; + + reg [2:0] Q; + reg clk, clr, up, down; + + (*ivl_synthesis_off *) + initial begin + clk = 0; + up = 0; + down = 0; + clr = 1; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin + $display("FAILED"); + $finish; + end + + up = 1; + clr = 0; + + #1 clk = 1; + #1 clk = 0; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3'b010) begin + $display("FAILED"); + $finish; + end + + up = 0; + down = 1; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3'b001) begin + $display("FAILED"); + $finish; + end + + down = 0; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3'b001) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end + + /* + * This statement models a snythesizable UP/DOWN counter. The up + * and down cases are enabled by up and down signals. If both + * signals are absent, the synthesizer should take the implicit + * case that Q <= Q; + */ + (* ivl_synthesis_on *) + always @(posedge clk, posedge clr) + if (clr) begin + Q <= 0; + end else begin + if (up) + Q <= Q + 1; + else if (down) + Q <= Q - 1; + end + +endmodule // main diff --git a/ivtest/ivltests/conditsynth2.v b/ivtest/ivltests/conditsynth2.v new file mode 100644 index 000000000..23d148f10 --- /dev/null +++ b/ivtest/ivltests/conditsynth2.v @@ -0,0 +1,98 @@ +module main; + + reg [2:0] Q; + reg clk, clr, up, down; + reg flag; + + (*ivl_synthesis_off *) + initial begin + clk = 0; + up = 0; + down = 0; + clr = 1; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin + $display("FAILED"); + $finish; + end + if (flag !== 0) begin + $display("FAILED"); + $finish; + end + + up = 1; + clr = 0; + + #1 clk = 1; + #1 clk = 0; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3'b010) begin + $display("FAILED"); + $finish; + end + if (flag !== 0) begin + $display("FAILED"); + $finish; + end + + up = 0; + down = 1; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3'b001) begin + $display("FAILED"); + $finish; + end + if (flag !== 0) begin + $display("FAILED"); + $finish; + end + + down = 0; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3'b001) begin + $display("FAILED"); + $finish; + end + + if (flag !== 1) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end + + /* + * This statement models a snythesizable UP/DOWN counter. The up + * and down cases are enabled by up and down signals. If both + * signals are absent, the synthesizer should take the implicit + * case that Q <= Q; + */ + (* ivl_synthesis_on *) + always @(posedge clk, posedge clr) + if (clr) begin + Q <= 0; + flag <= 0; + end else begin + if (up) + Q <= Q + 1; + else if (down) + Q <= Q - 1; + else + flag <= 1; + end + +endmodule // main diff --git a/ivtest/ivltests/conditsynth3.v b/ivtest/ivltests/conditsynth3.v new file mode 100644 index 000000000..46ef21511 --- /dev/null +++ b/ivtest/ivltests/conditsynth3.v @@ -0,0 +1,80 @@ +module main; + + reg [2:0] Q; + reg clk, clr, up; + + (*ivl_synthesis_off *) + initial begin + clk = 0; + up = 0; + clr = 1; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin + $display("FAILED"); + $finish; + end + + up = 1; + clr = 0; + + #1 clk = 1; + #1 clk = 0; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3'b010) begin + $display("FAILED"); + $finish; + end + + up = 0; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 3'b010) begin + $display("FAILED"); + $finish; + end + + clr = 1; + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end + + /* + * This statement models a snythesizable UP counter. The up + * count is enabled by the up signal. The clr is an asynchronous + * clear input. + * + * NOTE: This is bad style. Bad, bad style. It comes from a + * customer's customer, so I try to support it, but I'll moan + * about it. Much better (and clearer) is: + * + * if (clr) + * Q <= 0; + * else + * Q <= Q+1; + */ + (* ivl_synthesis_on *) + always @(posedge clk, posedge clr) begin + if (up) + Q = Q + 1; + if (clr) + Q = 0; + end + +endmodule // main diff --git a/ivtest/ivltests/const.v b/ivtest/ivltests/const.v new file mode 100644 index 000000000..5bcd4a31e --- /dev/null +++ b/ivtest/ivltests/const.v @@ -0,0 +1,63 @@ +// +// Copyright (c) 1999 Paul Bain (pdbain@adm.org) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - PR122 - Const define without length specification causes error. + +`timescale 1ns/1ns +module main( +clk, +dat +); + +parameter dat_width =32; +input clk; +output [dat_width-1:0] dat; +reg [dat_width-1:0] dat; +reg [32-1:0] exp_dat; +reg error; + +initial + begin + exp_dat = 0; + dat = 0; + end + +initial + begin + dat = #1 'h00010203; + exp_dat = #1 'h0010203; + error = 0; + #10; + for (exp_dat = 0; exp_dat != 4'hf; exp_dat = exp_dat + 1) + begin + dat = exp_dat; + #1 + if(dat !== exp_dat) + begin + $display("ERROR: dat = %h, exp_dat = %h",dat,exp_dat); + error = 1; + end + else + $display("Okay: dat = %h, exp_dat = %h",dat,exp_dat); + end + if(error === 0) + $display("PASSED"); + else + $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/const2.v b/ivtest/ivltests/const2.v new file mode 100644 index 000000000..26390de96 --- /dev/null +++ b/ivtest/ivltests/const2.v @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test checks that signed comparisons of constants work + * properly in conditional expressions. These cases are of + * interest because they are evaluated at compile time, so + * that dead code can be skipped. + */ +module main; + + initial begin + if ((0 < -255) || (0 > 255)) begin + $display("FAILED -- expression evaluated true"); + $finish; + end + + if ((0 <= -255) || (0 >= 255)) begin + $display("FAILED -- expression evaluated true"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/const3.v b/ivtest/ivltests/const3.v new file mode 100644 index 000000000..c29409467 --- /dev/null +++ b/ivtest/ivltests/const3.v @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg [7:0] testr; + wire [7:0] testw = {-5'd1, -3'sd1}; + + initial begin + #1 testr = {-5'd1, -3'sd1}; + if (testr !== 8'b11111_111) begin + $display("FAILED -- testr=%b", testr); + $finish; + end + + if (testw !== 8'b11111_111) begin + $display("FAILED -- testw=%b", testw); + $finish; + end + + $display("testr=%b", testr); + $display("testw=%b", testw); + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/const4.v b/ivtest/ivltests/const4.v new file mode 100644 index 000000000..3bf64097c --- /dev/null +++ b/ivtest/ivltests/const4.v @@ -0,0 +1,94 @@ +// +// Test the number format insanity +// +module test; + + integer err; + reg [31:0] i; + + // Ugly specification + initial begin + i = 659; + i = 'h 837FF; + i = 'o7460; + i = 4'b1001; + i = 5 'D 3; + i = 3'b01x; + i = 12'hx; + i = 16'hz; + i = -8 'd 6; + i = 4 'shf; + i = -4 'sd15; + end + + //always @(i) $display("%0t:\ti = %d", $time, i); + + // Potential ambiguities + initial begin + err = 0; + + i = # 9 1'd0; + + i = # 9_7 'D 3; + #100; + if (i != 'd3) begin + $display("'d3 != %0d", i); + err = 1; + end + + i = # 1 'h 123; + #100; + if (i != 'h123) begin + $display("'h123 != %0h", i); + err = 1; + end + + i = #(5 'D 3) 'D 3; + #100; + if (i != 'd3) begin + $display("'d3 != %0d", i); + err = 1; + end + + i = # 93 'h 837FF; + #100; + if (i != 'h837ff) begin + $display("'h837ff != %0h", i); + err = 1; + end + + i = # 33 20 'h 837ff - 1; + #100; + if (i != 'h837fe) begin + $display("'h837fe != %0h", i); + err = 1; + end + + i = # 69 - 20 'd 255 + 20'd1; + #100; + if (i[19:0] != 20'hf_ff_02) begin + $display("- 'd254 != %0d (%h)", i, i); + err = 1; + end + + i = #(27 - 20)'d 254 + 1; + #100; + if (i != 10'd255) begin + $display("'d255 != %0d", i); + err = 1; + end + + i = # 97.4 'h abcd; + #100; + if (i != 'habcd) begin + $display("'abcd != %0h", i); + err = 1; + end + + + if (err) + $display("FAILED"); + else + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/constadd.v b/ivtest/ivltests/constadd.v new file mode 100644 index 000000000..10180beb4 --- /dev/null +++ b/ivtest/ivltests/constadd.v @@ -0,0 +1,38 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate constant addition in vector range, and rhs. +// +// + +module main (); + +reg ['d4 + 'b110 : 0] val1; +reg [10'h1+ 'd9 : 0 ] val2 ; + +initial + begin + val1 = 11'h1 + 'd4; + val2 = 11'h2 + 6; + if((val1 === 11'h5) && (val2 === 11'h8)) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/constadd2.v b/ivtest/ivltests/constadd2.v new file mode 100644 index 000000000..6e0d91bd8 --- /dev/null +++ b/ivtest/ivltests/constadd2.v @@ -0,0 +1,31 @@ +// +// Copyright (c) 2001 Stephan Gehring +// +// (Modified by Stephan Williams to include PASS/FAIL messages.) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +module test; + reg [7:0] x; + initial begin + x = 'h4000 + 'hzz; // iverilog doesn't like 'hzz + if (x !== 8'hxx) begin + $display("FAILED -- x = %b", x); + $finish; + end + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/constadd3.v b/ivtest/ivltests/constadd3.v new file mode 100644 index 000000000..cedd1271f --- /dev/null +++ b/ivtest/ivltests/constadd3.v @@ -0,0 +1,10 @@ +module test; + integer i; + initial begin + i = 7+1; + if (i != 8) + $display ("FAILED -- i = %0d != 8", i); + else + $display ("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/constconcat1.v b/ivtest/ivltests/constconcat1.v new file mode 100644 index 000000000..e84ca4388 --- /dev/null +++ b/ivtest/ivltests/constconcat1.v @@ -0,0 +1,89 @@ +module test(); + +wire a; + +tri0 b; +tri1 c; + +tri1 d; +tri0 e; + +wire f; +wire g; + +wire h; +wire i; + +tri1 j; +tri0 k; + +wire l; + +tri0 m; +tri1 n; + +assign d = 1'b0; +assign e = 1'b1; + +assign f = 1'b0; +assign f = 1'b1; + +assign g = 1'b1; +assign g = 1'b0; + +assign (strong1,strong0) h = 1'b0; +assign ( weak1, weak0) h = 1'b1; + +assign ( weak1, weak0) i = 1'b0; +assign (strong1,strong0) i = 1'b1; + +assign (pull1,pull0) j = 1'b0; +assign (pull1,pull0) k = 1'b1; + +wire [1:0] A = {1'b1, a}; +wire [1:0] B = {1'b1, b}; +wire [1:0] C = {1'b1, c}; +wire [1:0] D = {1'b1, d}; +wire [1:0] E = {1'b1, e}; +wire [1:0] F = {1'b1, f}; +wire [1:0] G = {1'b1, g}; +wire [1:0] H = {1'b1, h}; +wire [1:0] I = {1'b1, i}; +wire [1:0] J = {1'b1, j}; +wire [1:0] K = {1'b1, k}; +wire [1:0] L = {1'b1, l}; +wire [1:0] M = {1'b1, m}; +wire [1:0] N = {1'b1, n}; + +reg failed; + +initial begin + failed = 0; #1; + + $display("A = %b, expect 1z", A); if (A !== 2'b1z) failed = 1; + $display("B = %b, expect 10", B); if (B !== 2'b10) failed = 1; + $display("C = %b, expect 11", C); if (C !== 2'b11) failed = 1; + $display("D = %b, expect 10", D); if (D !== 2'b10) failed = 1; + $display("E = %b, expect 11", E); if (E !== 2'b11) failed = 1; + $display("F = %b, expect 1x", F); if (F !== 2'b1x) failed = 1; + $display("G = %b, expect 1x", G); if (G !== 2'b1x) failed = 1; + $display("H = %b, expect 10", H); if (H !== 2'b10) failed = 1; + $display("I = %b, expect 11", I); if (I !== 2'b11) failed = 1; + $display("J = %b, expect 1x", J); if (J !== 2'b1x) failed = 1; + $display("K = %b, expect 1x", K); if (K !== 2'b1x) failed = 1; + force l = 1'b0; #1; + $display("L = %b, expect 10", L); if (L !== 2'b10) failed = 1; + force l = 1'b1; #1; + $display("L = %b, expect 11", L); if (L !== 2'b11) failed = 1; + force m = 1'b1; #1; + $display("M = %b, expect 11", M); if (M !== 2'b11) failed = 1; + force n = 1'b0; #1; + $display("N = %b, expect 10", N); if (N !== 2'b10) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/constconcat2.v b/ivtest/ivltests/constconcat2.v new file mode 100644 index 000000000..f415e41fe --- /dev/null +++ b/ivtest/ivltests/constconcat2.v @@ -0,0 +1,89 @@ +module test(); + +wire a; + +supply0 b; +supply1 c; + +supply1 d; +supply0 e; + +wire f; +wire g; + +wire h; +wire i; + +supply1 j; +supply0 k; + +wire l; + +supply0 m; +supply1 n; + +assign d = 1'b0; +assign e = 1'b1; + +assign f = 1'b0; +assign f = 1'b1; + +assign g = 1'b1; +assign g = 1'b0; + +assign (strong1,strong0) h = 1'b0; +assign ( weak1, weak0) h = 1'b1; + +assign ( weak1, weak0) i = 1'b0; +assign (strong1,strong0) i = 1'b1; + +assign (supply1,supply0) j = 1'b0; +assign (supply1,supply0) k = 1'b1; + +wire [1:0] A = {1'b1, a}; +wire [1:0] B = {1'b1, b}; +wire [1:0] C = {1'b1, c}; +wire [1:0] D = {1'b1, d}; +wire [1:0] E = {1'b1, e}; +wire [1:0] F = {1'b1, f}; +wire [1:0] G = {1'b1, g}; +wire [1:0] H = {1'b1, h}; +wire [1:0] I = {1'b1, i}; +wire [1:0] J = {1'b1, j}; +wire [1:0] K = {1'b1, k}; +wire [1:0] L = {1'b1, l}; +wire [1:0] M = {1'b1, m}; +wire [1:0] N = {1'b1, n}; + +reg failed; + +initial begin + failed = 0; #1; + + $display("A = %b, expect 1z", A); if (A !== 2'b1z) failed = 1; + $display("B = %b, expect 10", B); if (B !== 2'b10) failed = 1; + $display("C = %b, expect 11", C); if (C !== 2'b11) failed = 1; + $display("D = %b, expect 11", D); if (D !== 2'b11) failed = 1; + $display("E = %b, expect 10", E); if (E !== 2'b10) failed = 1; + $display("F = %b, expect 1x", F); if (F !== 2'b1x) failed = 1; + $display("G = %b, expect 1x", G); if (G !== 2'b1x) failed = 1; + $display("H = %b, expect 10", H); if (H !== 2'b10) failed = 1; + $display("I = %b, expect 11", I); if (I !== 2'b11) failed = 1; + $display("J = %b, expect 1x", J); if (J !== 2'b1x) failed = 1; + $display("K = %b, expect 1x", K); if (K !== 2'b1x) failed = 1; + force l = 1'b0; #1; + $display("L = %b, expect 10", L); if (L !== 2'b10) failed = 1; + force l = 1'b1; #1; + $display("L = %b, expect 11", L); if (L !== 2'b11) failed = 1; + force m = 1'b1; #1; + $display("M = %b, expect 11", M); if (M !== 2'b11) failed = 1; + force n = 1'b0; #1; + $display("N = %b, expect 10", N); if (N !== 2'b10) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc1.v b/ivtest/ivltests/constfunc1.v new file mode 100644 index 000000000..5c9bf4a51 --- /dev/null +++ b/ivtest/ivltests/constfunc1.v @@ -0,0 +1,53 @@ +module constfunc1(); + +function integer median; + +input integer a; +input integer b; +input integer c; + +begin + if (a < b) + begin + if (a < c) + median = (b < c) ? b : c; + else + median = a; + end + else + begin + if (a < c) + median = a; + else + median = (b < c) ? c : b; + end +end + +endfunction + +localparam value1 = median(1, 2, 3); +localparam value2 = median(1, 3, 2); +localparam value3 = median(2, 1, 3); +localparam value4 = median(2, 3, 1); +localparam value5 = median(3, 1, 2); +localparam value6 = median(3, 2, 1); + +initial begin + $display("value 1 = %0d", value1); + $display("value 2 = %0d", value2); + $display("value 3 = %0d", value3); + $display("value 4 = %0d", value4); + $display("value 5 = %0d", value5); + $display("value 6 = %0d", value6); + if ((value1 === 2) + && (value2 === 2) + && (value3 === 2) + && (value4 === 2) + && (value5 === 2) + && (value6 === 2)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc10.v b/ivtest/ivltests/constfunc10.v new file mode 100644 index 000000000..f3edb219b --- /dev/null +++ b/ivtest/ivltests/constfunc10.v @@ -0,0 +1,29 @@ +// Test forever statements inside a constant function +module constfunc10(); + +function [31:0] pow2(input [5:0] x); + +begin:body + pow2 = 1; + forever begin:loop + if (x == 0) disable body; + pow2 = 2 * pow2; + x = x - 1; + disable loop; + pow2 = 0; + end +end + +endfunction + +localparam val = pow2(8); + +initial begin + $display("%0d", val); + if (val === 256) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc11.v b/ivtest/ivltests/constfunc11.v new file mode 100644 index 000000000..324f1fd29 --- /dev/null +++ b/ivtest/ivltests/constfunc11.v @@ -0,0 +1,34 @@ +// Test repeat statements inside a constant function +module constfunc11(); + +function [31:0] pow2(input [5:0] x); + +begin:body + pow2 = 1; + repeat (x) begin + pow2 = 2 * pow2; + end +end + +endfunction + +localparam val0 = pow2(0); +localparam val1 = pow2(1); +localparam val2 = pow2(2); +localparam val3 = pow2(3); + +reg failed; + +initial begin + failed = 0; + $display("%0d", val0); if (val0 !== 1) failed = 1; + $display("%0d", val1); if (val1 !== 2) failed = 1; + $display("%0d", val2); if (val2 !== 4) failed = 1; + $display("%0d", val3); if (val3 !== 8) failed = 1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc12.v b/ivtest/ivltests/constfunc12.v new file mode 100644 index 000000000..16a9bddd1 --- /dev/null +++ b/ivtest/ivltests/constfunc12.v @@ -0,0 +1,121 @@ +// Test case statements inside a constant function +module constfunc12(); + +function [1:0] onehot_to_binary(input [3:1] x); + +case (x) + default : onehot_to_binary = 0; + 3'b001 : onehot_to_binary = 1; + 3'b010 : onehot_to_binary = 2; + 3'b100 : onehot_to_binary = 3; +endcase + +endfunction + +function [1:0] find_first_one(input [3:1] x); + +casez (x) + 3'b1?? : find_first_one = 3; + 3'b01? : find_first_one = 2; + 3'b001 : find_first_one = 1; + default : find_first_one = 0; +endcase + +endfunction + +function [1:0] find_first_zero(input [3:1] x); + +casex (x) + 3'b0zz : find_first_zero = 3; + 3'b10x : find_first_zero = 2; + 3'b110 : find_first_zero = 1; + default : find_first_zero = 0; +endcase + +endfunction + +function [1:0] match_real_value(input real x); + +case (x) + 1.0 : match_real_value = 1; + 2.0 : match_real_value = 2; + 3.0 : match_real_value = 3; + default : match_real_value = 0; +endcase + +endfunction + +localparam otb0 = onehot_to_binary(3'b000); +localparam otb1 = onehot_to_binary(3'b001); +localparam otb2 = onehot_to_binary(3'b010); +localparam otb3 = onehot_to_binary(3'b100); +localparam otb4 = onehot_to_binary(3'b101); +localparam otb5 = onehot_to_binary(3'b10z); +localparam otb6 = onehot_to_binary(3'bx01); + +localparam ffo0 = find_first_one(3'b000); +localparam ffo1 = find_first_one(3'b001); +localparam ffo2 = find_first_one(3'b01x); +localparam ffo3 = find_first_one(3'b1xx); +localparam ffo4 = find_first_one(3'bxx1); +localparam ffo5 = find_first_one(3'b00z); +localparam ffo6 = find_first_one(3'b0zz); +localparam ffo7 = find_first_one(3'bzzz); + +localparam ffz0 = find_first_zero(3'b111); +localparam ffz1 = find_first_zero(3'b110); +localparam ffz2 = find_first_zero(3'b10x); +localparam ffz3 = find_first_zero(3'b0xx); +localparam ffz4 = find_first_zero(3'bzzz); +localparam ffz5 = find_first_zero(3'b11x); +localparam ffz6 = find_first_zero(3'b1xx); +localparam ffz7 = find_first_zero(3'bxxx); + +localparam mrv0 = match_real_value(0.0); +localparam mrv1 = match_real_value(1.0); +localparam mrv2 = match_real_value(2.0); +localparam mrv3 = match_real_value(3.0); +localparam mrv4 = match_real_value(4.0); + +reg failed = 0; + +initial begin + $display("%d", otb0); if (otb0 !== 2'd0) failed = 1; + $display("%d", otb1); if (otb1 !== 2'd1) failed = 1; + $display("%d", otb2); if (otb2 !== 2'd2) failed = 1; + $display("%d", otb3); if (otb3 !== 2'd3) failed = 1; + $display("%d", otb4); if (otb4 !== 2'd0) failed = 1; + $display("%d", otb5); if (otb5 !== 2'd0) failed = 1; + $display("%d", otb6); if (otb6 !== 2'd0) failed = 1; + $display(""); + $display("%d", ffo0); if (ffo0 !== 2'd0) failed = 1; + $display("%d", ffo1); if (ffo1 !== 2'd1) failed = 1; + $display("%d", ffo2); if (ffo2 !== 2'd2) failed = 1; + $display("%d", ffo3); if (ffo3 !== 2'd3) failed = 1; + $display("%d", ffo4); if (ffo4 !== 2'd0) failed = 1; + $display("%d", ffo5); if (ffo5 !== 2'd1) failed = 1; + $display("%d", ffo6); if (ffo6 !== 2'd2) failed = 1; + $display("%d", ffo7); if (ffo7 !== 2'd3) failed = 1; + $display(""); + $display("%d", ffz0); if (ffz0 !== 2'd0) failed = 1; + $display("%d", ffz1); if (ffz1 !== 2'd1) failed = 1; + $display("%d", ffz2); if (ffz2 !== 2'd2) failed = 1; + $display("%d", ffz3); if (ffz3 !== 2'd3) failed = 1; + $display("%d", ffz4); if (ffz4 !== 2'd3) failed = 1; + $display("%d", ffz5); if (ffz5 !== 2'd1) failed = 1; + $display("%d", ffz6); if (ffz6 !== 2'd2) failed = 1; + $display("%d", ffz7); if (ffz7 !== 2'd3) failed = 1; + $display(""); + $display("%d", mrv0); if (mrv0 !== 2'd0) failed = 1; + $display("%d", mrv1); if (mrv1 !== 2'd1) failed = 1; + $display("%d", mrv2); if (mrv2 !== 2'd2) failed = 1; + $display("%d", mrv3); if (mrv3 !== 2'd3) failed = 1; + $display("%d", mrv4); if (mrv4 !== 2'd0) failed = 1; + $display(""); + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc13.v b/ivtest/ivltests/constfunc13.v new file mode 100644 index 000000000..7f5ab727f --- /dev/null +++ b/ivtest/ivltests/constfunc13.v @@ -0,0 +1,103 @@ +// Test mixed type/width case expressions inside a constant function +module constfunc13(); + +function [2:0] lookup1(input signed [2:0] value); + +begin + case (value) + 4'sb0100 : lookup1 = 1; + 3'sb100 : lookup1 = 2; + 2'sb10 : lookup1 = 3; + default : lookup1 = 4; + endcase + $display("case = %d", lookup1); +end + +endfunction + +function [2:0] lookup2(input signed [2:0] value); + +begin + case (value) + 4'b1100 : lookup2 = 1; + 3'sb100 : lookup2 = 2; + 2'sb10 : lookup2 = 3; + default : lookup2 = 4; + endcase + $display("case = %d", lookup2); +end + +endfunction + +function [2:0] lookup3(input real value); + +begin + case (value) + 4'b0001 : lookup3 = 1; + 3'sb010 : lookup3 = 2; + 2'sb11 : lookup3 = 3; + default : lookup3 = 4; + endcase + $display("case = %d", lookup3); +end + +endfunction + +function [2:0] lookup4(input signed [2:0] value); + +begin + case (value) + 4'b0110 : lookup4 = 1; + 3'sb110 : lookup4 = 2; + -1.0 : lookup4 = 3; + default : lookup4 = 4; + endcase + $display("case = %d", lookup4); +end + +endfunction + +localparam res11 = lookup1(3'sb100); +localparam res12 = lookup1(3'sb110); +localparam res13 = lookup1(3'sb010); + +localparam res21 = lookup2(3'sb100); +localparam res22 = lookup2(3'sb010); +localparam res23 = lookup2(3'sb110); + +localparam res31 = lookup3( 1.0); +localparam res32 = lookup3( 2.0); +localparam res33 = lookup3(-1.0); +localparam res34 = lookup3( 1.5); + +localparam res41 = lookup4(3'sb110); +localparam res42 = lookup4(3'sb111); +localparam res43 = lookup4(3'sb011); + +reg failed = 0; + +initial begin + $display("case = %d", res11); if (res11 != 2) failed = 1; + $display("case = %d", res12); if (res12 != 3) failed = 1; + $display("case = %d", res13); if (res13 != 4) failed = 1; + $display(""); + $display("case = %d", res21); if (res21 != 2) failed = 1; + $display("case = %d", res22); if (res22 != 3) failed = 1; + $display("case = %d", res23); if (res23 != 4) failed = 1; + $display(""); + $display("case = %d", res31); if (res31 != 1) failed = 1; + $display("case = %d", res32); if (res32 != 2) failed = 1; + $display("case = %d", res33); if (res33 != 3) failed = 1; + $display("case = %d", res34); if (res34 != 4) failed = 1; + $display(""); + $display("case = %d", res41); if (res41 != 2) failed = 1; + $display("case = %d", res42); if (res42 != 3) failed = 1; + $display("case = %d", res43); if (res43 != 4) failed = 1; + $display(""); + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc14.v b/ivtest/ivltests/constfunc14.v new file mode 100644 index 000000000..9a3b7e650 --- /dev/null +++ b/ivtest/ivltests/constfunc14.v @@ -0,0 +1,58 @@ +// Test concatenation inside a constant function +module constfunc14(); + +function [7:0] concat1(input [7:0] value); + +reg [3:0] tmp1; +reg [3:0] tmp2; + +begin + {tmp1, tmp2} = {value[3:0], value[7:4]}; + {concat1[3:0], concat1[7:4]} = {tmp2, tmp1}; +end + +endfunction + +function [7:0] concat2(input [7:0] value); + +reg [2:0] tmp1; +reg [3:0] tmp2; + +begin + {tmp1, tmp2} = {value[3:0], value[7:4]}; + {concat2[3:0], concat2[7:4]} = {tmp2, tmp1}; +end + +endfunction + +function [7:0] concat3(input [7:0] value); + +reg signed [2:0] tmp1; +reg signed [2:0] tmp2; + +begin + {tmp1, tmp2} = {value[2:0], value[6:4]}; + concat3[7:4] = tmp1; + concat3[3:0] = tmp2; +end + +endfunction + +localparam res1 = concat1(8'h5a); +localparam res2 = concat2(8'h5a); +localparam res3 = concat3(8'h5a); + +reg failed = 0; + +initial begin + $display("%h", res1); if (res1 !== 8'ha5) failed = 1; + $display("%h", res2); if (res2 !== 8'ha2) failed = 1; + $display("%h", res3); if (res3 !== 8'h2d) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc15.v b/ivtest/ivltests/constfunc15.v new file mode 100644 index 000000000..8d3bfe9dd --- /dev/null +++ b/ivtest/ivltests/constfunc15.v @@ -0,0 +1,68 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +// Test array variables inside a constant function +module constfunc14(); + +function [7:0] concat1(input [7:0] value); + +reg [3:0] tmp[1:2]; + +begin + {tmp[1], tmp[2]} = {value[3:0], value[7:4]}; + {concat1[3:0], concat1[7:4]} = {tmp[2], tmp[1]}; +end + +endfunction + +function [7:0] concat2(input [7:0] value); + +reg [3:0] tmp[1:2]; + +begin +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + {tmp[1], tmp[3]} = {value[3:0], value[7:4]}; + {concat2[3:0], concat2[7:4]} = {tmp[3], tmp[1]}; +`else + {tmp[1]} = {value[3:0]}; + {concat2[3:0], concat2[7:4]} = {4'bxxxx, tmp[1]}; +`endif +end + +endfunction + +function [7:0] concat3(input [7:0] value); + +reg [3:0] tmp[1:2]; + +begin +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + {tmp['bx], tmp[1]} = {value[3:0], value[7:4]}; + {concat3[3:0], concat3[7:4]} = {tmp['bx], tmp[1]}; +`else + {tmp[1]} = {value[7:4]}; + {concat3[3:0], concat3[7:4]} = {4'bxxxx, tmp[1]}; +`endif +end + +endfunction + +localparam res1 = concat1(8'ha5); +localparam res2 = concat2(8'ha5); +localparam res3 = concat2(8'ha5); + +reg failed = 0; + +initial begin + $display("%h", res1); if (res1 !== 8'h5a) failed = 1; + $display("%h", res2); if (res2 !== 8'h5x) failed = 1; + $display("%h", res3); if (res3 !== 8'h5x) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc2.v b/ivtest/ivltests/constfunc2.v new file mode 100644 index 000000000..8b4ae789c --- /dev/null +++ b/ivtest/ivltests/constfunc2.v @@ -0,0 +1,41 @@ +module constfunc2(); + +function integer factorial; + +input integer n; + +begin + if (n > 1) + factorial = n * factorial(n - 1); + else + factorial = n; +end + +endfunction + +localparam value1 = factorial(1); +localparam value2 = factorial(2); +localparam value3 = factorial(3); +localparam value4 = factorial(4); +localparam value5 = factorial(5); +localparam value6 = factorial(6); + +initial begin + $display("value 1 = %0d", value1); + $display("value 2 = %0d", value2); + $display("value 3 = %0d", value3); + $display("value 4 = %0d", value4); + $display("value 5 = %0d", value5); + $display("value 6 = %0d", value6); + if ((value1 === 1) + && (value2 === 2) + && (value3 === 6) + && (value4 === 24) + && (value5 === 120) + && (value6 === 720)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc3.v b/ivtest/ivltests/constfunc3.v new file mode 100644 index 000000000..4eabaade3 --- /dev/null +++ b/ivtest/ivltests/constfunc3.v @@ -0,0 +1,73 @@ +// Test binary operators in constant functions +module constfunc3(); + +function [7:0] Add(input [7:0] l, input [7:0] r); + Add = l + r; +endfunction + +function [7:0] Mul(input [7:0] l, input [7:0] r); + Mul = l * r; +endfunction + +function [7:0] Div(input [7:0] l, input [7:0] r); + Div = l / r; +endfunction + +function [7:0] Pow(input [7:0] l, input [7:0] r); + Pow = l ** r; +endfunction + +function [7:0] And(input [7:0] l, input [7:0] r); + And = l & r; +endfunction + +function [7:0] Shift(input [7:0] l, input [7:0] r); + Shift = l << r; +endfunction + +function [7:0] Logic(input [7:0] l, input [7:0] r); +begin + Logic[0] = l[0] && r[0]; + Logic[1] = l[1] && r[1]; + Logic[2] = l[2] && r[2]; + Logic[3] = l[3] && r[3]; + Logic[4] = l[4] || r[4]; + Logic[5] = l[5] || r[5]; + Logic[6] = l[6] || r[6]; + Logic[7] = l[7] || r[7]; +end +endfunction + +localparam [7:0] ResultAdd = Add(8'h0f, 8'h0f); +localparam [7:0] ResultMul = Mul(8'h0f, 8'h0f); +localparam [7:0] ResultDiv = Div(8'hf0, 8'h0f); +localparam [7:0] ResultPow = Pow(8'h02, 8'h05); +localparam [7:0] ResultAnd = And(8'h0f, 8'h55); +localparam [7:0] ResultShift = Shift(8'h55, 8'h03); +localparam [7:0] ResultLogic = Logic(8'h33, 8'h55); + +reg failed; + +initial begin + failed = 0; + $display("%h", ResultAdd); + $display("%h", ResultMul); + $display("%h", ResultDiv); + $display("%h", ResultPow); + $display("%h", ResultAnd); + $display("%h", ResultShift); + $display("%h", ResultLogic); + if (ResultAdd !== 8'h1e) failed = 1; + if (ResultMul !== 8'he1) failed = 1; + if (ResultDiv !== 8'h10) failed = 1; + if (ResultPow !== 8'h20) failed = 1; + if (ResultAnd !== 8'h05) failed = 1; + if (ResultShift !== 8'ha8) failed = 1; + if (ResultLogic !== 8'h71) failed = 1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc4.v b/ivtest/ivltests/constfunc4.v new file mode 100644 index 000000000..e73022868 --- /dev/null +++ b/ivtest/ivltests/constfunc4.v @@ -0,0 +1,56 @@ +// Test unary operators in constant functions +module constfunc4(); + +function [7:0] LInv(input [7:0] x); + LInv = ~x; +endfunction + +function [7:0] LNeg(input [7:0] x); + LNeg = -x; +endfunction + +function real RNeg(input real x); + RNeg = -x; +endfunction + +function LAnd(input [7:0] x); + LAnd = &x; +endfunction + +function LNot(input [7:0] x); + LNot = !x; +endfunction + +function RNot(input real x); + RNot = !x; +endfunction + +localparam [7:0] ResultLInv = LInv(8'h0f); +localparam [7:0] ResultLNeg = LNeg(8'h0f); +localparam real ResultRNeg = RNeg(15.0); +localparam ResultLAnd = LAnd(8'hff); +localparam ResultLNot = LNot(8'h00); +localparam ResultRNot = RNot(0.0); + +reg failed; + +initial begin + failed = 0; + $display("%h", ResultLInv); + $display("%h", ResultLNeg); + $display("%g", ResultRNeg); + $display("%b", ResultLAnd); + $display("%b", ResultLNot); + $display("%b", ResultRNot); + if (ResultLNeg !== 8'hf1) failed = 1; + if (ResultRNeg != -15.0) failed = 1; + if (ResultLAnd !== 1'b1) failed = 1; + if (ResultLNot !== 1'b1) failed = 1; + if (ResultRNot !== 1'b1) failed = 1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc4_ams.v b/ivtest/ivltests/constfunc4_ams.v new file mode 100644 index 000000000..12e89572f --- /dev/null +++ b/ivtest/ivltests/constfunc4_ams.v @@ -0,0 +1,35 @@ +// Test unary operators in constant functions +module constfunc4(); + +function [7:0] LAbs(input signed [7:0] x); + LAbs = abs(x); +endfunction + +function real RAbs(input real x); + RAbs = abs(x); +endfunction + +localparam [7:0] ResultLAb1 = LAbs(8'sh01); +localparam [7:0] ResultLAb2 = LAbs(8'shff); +localparam real ResultRAb1 = RAbs( 2.0); +localparam real ResultRAb2 = RAbs(-2.0); + +reg failed; + +initial begin + failed = 0; + $display("%h", ResultLAb1); + $display("%h", ResultLAb2); + $display("%g", ResultRAb1); + $display("%g", ResultRAb2); + if (ResultLAb1 !== 8'h01) failed = 1; + if (ResultLAb2 !== 8'h01) failed = 1; + if (ResultRAb1 != 2.0) failed = 1; + if (ResultRAb2 != 2.0) failed = 1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc5.v b/ivtest/ivltests/constfunc5.v new file mode 100644 index 000000000..4c0b805d9 --- /dev/null +++ b/ivtest/ivltests/constfunc5.v @@ -0,0 +1,25 @@ +// Test concatenation operator in constant functions +module constfunc5(); + +function [23:0] Concat(input [3:0] a, input [3:0] b); + Concat = {2{a, 4'hf, b}}; +endfunction + +localparam [23:0] Result1 = Concat(4'h5, 4'ha); +localparam [23:0] Result2 = Concat(4'ha, 4'h5); + +reg failed; + +initial begin + failed = 0; + $display("%h", Result1); + $display("%h", Result2); + if (Result1 !== 24'h5fa5fa) failed = 1; + if (Result2 !== 24'haf5af5) failed = 1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc6.v b/ivtest/ivltests/constfunc6.v new file mode 100644 index 000000000..64775c1ff --- /dev/null +++ b/ivtest/ivltests/constfunc6.v @@ -0,0 +1,54 @@ +// Test system function calls in constant functions +module constfunc6(); + +function [7:0] clog2(input [7:0] a); + clog2 = $clog2(a); +endfunction + +function real log10(input [7:0] a); + log10 = $log10(a); +endfunction + +function real sqrt(input real a); + sqrt = $sqrt(a); +endfunction + +function real pow_i(input [7:0] a, input [7:0] b); + pow_i = $pow(a, b); +endfunction + +function real pow_r(input real a, input real b); + pow_r = $pow(a, b); +endfunction + +localparam [7:0] clog2Result = clog2(25); + +localparam real log10Result = log10(100); + +localparam real sqrtResult = sqrt(25.0); + +localparam [7:0] powIResult = pow_i(4, 3); + +localparam real powRResult = pow_r(4.0, 3.0); + +reg failed; + +initial begin + failed = 0; + $display("%0d", clog2Result); + $display("%0g", log10Result); + $display("%0g", sqrtResult); + $display("%0d", powIResult); + $display("%0g", powRResult); + if (clog2Result !== 8'd5) failed = 1; + if (log10Result != 2.0) failed = 1; + if ( sqrtResult != 5.0) failed = 1; + if ( powIResult !== 8'd64) failed = 1; + if ( powRResult != 64.0) failed = 1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc6_ams.v b/ivtest/ivltests/constfunc6_ams.v new file mode 100644 index 000000000..2b084af50 --- /dev/null +++ b/ivtest/ivltests/constfunc6_ams.v @@ -0,0 +1,60 @@ +// Test system function calls in constant functions +module constfunc6(); + +function signed [7:0] abs_i(input signed [7:0] a); + abs_i = $abs(a); +endfunction + +function real abs_r(input real a); + abs_r = $abs(a); +endfunction + +function [7:0] min_i(input [7:0] a, input [7:0] b); + min_i = $min(a, b); +endfunction + +function [7:0] max_i(input [7:0] a, input [7:0] b); + max_i = $max(a, b); +endfunction + +function real min_r(input real a, input real b); + min_r = $min(a, b); +endfunction + +function real max_r(input real a, input real b); + max_r = $max(a, b); +endfunction + +localparam [7:0] absIResult = abs_i(-25); + +localparam [7:0] minIResult = min_i(25, 30); +localparam [7:0] maxIResult = max_i(25, 30); + +localparam real absRResult = abs_r(-25.0); + +localparam real minRResult = min_r(25.0, 30.0); +localparam real maxRResult = max_r(25.0, 30.0); + +reg failed; + +initial begin + failed = 0; + $display("%0d", absIResult); + $display("%0g", absRResult); + $display("%0d", minIResult); + $display("%0g", minRResult); + $display("%0d", maxIResult); + $display("%0g", maxRResult); + if ( absIResult !== 8'd25) failed = 1; + if ( absRResult != 25.0) failed = 1; + if ( minIResult !== 8'd25) failed = 1; + if ( minRResult != 25.0) failed = 1; + if ( maxIResult !== 8'd30) failed = 1; + if ( maxRResult != 30.0) failed = 1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc7.v b/ivtest/ivltests/constfunc7.v new file mode 100644 index 000000000..34233a924 --- /dev/null +++ b/ivtest/ivltests/constfunc7.v @@ -0,0 +1,155 @@ +// Check assignment operations in constant functions. +module constfunc7(); + +function real i_to_r(input signed [3:0] value); + i_to_r = value + 0.5; +endfunction + +function signed [3:0] r_to_i(input real value); + r_to_i = value; +endfunction + +function real u_to_r(input [3:0] value); + u_to_r = value + 0.5; +endfunction + +function [3:0] r_to_u(input real value); + r_to_u = value; +endfunction + +function [3:0] i_to_u(input signed [3:0] value); + i_to_u = value; +endfunction + +function signed [3:0] u_to_i(input [3:0] value); + u_to_i = value; +endfunction + +function [5:0] si_to_lu(input signed [3:0] value); + si_to_lu = value; +endfunction + +function signed [5:0] su_to_li(input [3:0] value); + su_to_li = value; +endfunction + +function [3:0] li_to_su(input signed [5:0] value); + li_to_su = value; +endfunction + +function signed [3:0] lu_to_si(input [5:0] value); + lu_to_si = value; +endfunction + +localparam i_to_r_res1 = i_to_r(-9); +localparam i_to_r_res2 = i_to_r(-8); +localparam i_to_r_res3 = i_to_r( 7); +localparam i_to_r_res4 = i_to_r( 8); + +localparam r_to_i_res1 = r_to_i(-8.5); +localparam r_to_i_res2 = r_to_i(-7.5); +localparam r_to_i_res3 = r_to_i( 6.5); +localparam r_to_i_res4 = r_to_i( 7.5); + +localparam u_to_r_res1 = u_to_r(-1); +localparam u_to_r_res2 = u_to_r( 1); +localparam u_to_r_res3 = u_to_r(15); +localparam u_to_r_res4 = u_to_r(17); + +localparam r_to_u_res1 = r_to_u(-0.5); +localparam r_to_u_res2 = r_to_u( 0.5); +localparam r_to_u_res3 = r_to_u(14.5); +localparam r_to_u_res4 = r_to_u(16.5); + +localparam i_to_u_res1 = i_to_u(-9); +localparam i_to_u_res2 = i_to_u(-8); +localparam i_to_u_res3 = i_to_u( 7); +localparam i_to_u_res4 = i_to_u( 8); + +localparam u_to_i_res1 = u_to_i(-1); +localparam u_to_i_res2 = u_to_i( 1); +localparam u_to_i_res3 = u_to_i(15); +localparam u_to_i_res4 = u_to_i(17); + +localparam si_to_lu_res1 = si_to_lu(-9); +localparam si_to_lu_res2 = si_to_lu(-8); +localparam si_to_lu_res3 = si_to_lu( 7); +localparam si_to_lu_res4 = si_to_lu( 8); + +localparam su_to_li_res1 = su_to_li(-1); +localparam su_to_li_res2 = su_to_li( 1); +localparam su_to_li_res3 = su_to_li(15); +localparam su_to_li_res4 = su_to_li(17); + +localparam li_to_su_res1 = li_to_su(-9); +localparam li_to_su_res2 = li_to_su(-8); +localparam li_to_su_res3 = li_to_su( 7); +localparam li_to_su_res4 = li_to_su( 8); + +localparam lu_to_si_res1 = lu_to_si(-1); +localparam lu_to_si_res2 = lu_to_si( 1); +localparam lu_to_si_res3 = lu_to_si(15); +localparam lu_to_si_res4 = lu_to_si(17); + +reg failed; + +initial begin + failed = 0; + + $display("%0g", i_to_r_res1); if (i_to_r_res1 != 7.5) failed = 1; + $display("%0g", i_to_r_res2); if (i_to_r_res2 != -7.5) failed = 1; + $display("%0g", i_to_r_res3); if (i_to_r_res3 != 7.5) failed = 1; + $display("%0g", i_to_r_res4); if (i_to_r_res4 != -7.5) failed = 1; + $display(""); + $display("%0d", r_to_i_res1); if (r_to_i_res1 !== 7) failed = 1; + $display("%0d", r_to_i_res2); if (r_to_i_res2 !== -8) failed = 1; + $display("%0d", r_to_i_res3); if (r_to_i_res3 !== 7) failed = 1; + $display("%0d", r_to_i_res4); if (r_to_i_res4 !== -8) failed = 1; + $display(""); + $display("%0g", u_to_r_res1); if (u_to_r_res1 != 15.5) failed = 1; + $display("%0g", u_to_r_res2); if (u_to_r_res2 != 1.5) failed = 1; + $display("%0g", u_to_r_res3); if (u_to_r_res3 != 15.5) failed = 1; + $display("%0g", u_to_r_res4); if (u_to_r_res4 != 1.5) failed = 1; + $display(""); + $display("%0d", r_to_u_res1); if (r_to_u_res1 !== 15) failed = 1; + $display("%0d", r_to_u_res2); if (r_to_u_res2 !== 1) failed = 1; + $display("%0d", r_to_u_res3); if (r_to_u_res3 !== 15) failed = 1; + $display("%0d", r_to_u_res4); if (r_to_u_res4 !== 1) failed = 1; + $display(""); + $display("%0d", i_to_u_res1); if (i_to_u_res1 !== 7) failed = 1; + $display("%0d", i_to_u_res2); if (i_to_u_res2 !== 8) failed = 1; + $display("%0d", i_to_u_res3); if (i_to_u_res3 !== 7) failed = 1; + $display("%0d", i_to_u_res4); if (i_to_u_res4 !== 8) failed = 1; + $display(""); + $display("%0d", u_to_i_res1); if (u_to_i_res1 !== -1) failed = 1; + $display("%0d", u_to_i_res2); if (u_to_i_res2 !== 1) failed = 1; + $display("%0d", u_to_i_res3); if (u_to_i_res3 !== -1) failed = 1; + $display("%0d", u_to_i_res4); if (u_to_i_res4 !== 1) failed = 1; + $display(""); + $display("%0d", si_to_lu_res1); if (si_to_lu_res1 !== 7) failed = 1; + $display("%0d", si_to_lu_res2); if (si_to_lu_res2 !== 56) failed = 1; + $display("%0d", si_to_lu_res3); if (si_to_lu_res3 !== 7) failed = 1; + $display("%0d", si_to_lu_res4); if (si_to_lu_res4 !== 56) failed = 1; + $display(""); + $display("%0d", su_to_li_res1); if (su_to_li_res1 !== 15) failed = 1; + $display("%0d", su_to_li_res2); if (su_to_li_res2 !== 1) failed = 1; + $display("%0d", su_to_li_res3); if (su_to_li_res3 !== 15) failed = 1; + $display("%0d", su_to_li_res4); if (su_to_li_res4 !== 1) failed = 1; + $display(""); + $display("%0d", li_to_su_res1); if (li_to_su_res1 !== 7) failed = 1; + $display("%0d", li_to_su_res2); if (li_to_su_res2 !== 8) failed = 1; + $display("%0d", li_to_su_res3); if (li_to_su_res3 !== 7) failed = 1; + $display("%0d", li_to_su_res4); if (li_to_su_res4 !== 8) failed = 1; + $display(""); + $display("%0d", lu_to_si_res1); if (lu_to_si_res1 !== -1) failed = 1; + $display("%0d", lu_to_si_res2); if (lu_to_si_res2 !== 1) failed = 1; + $display("%0d", lu_to_si_res3); if (lu_to_si_res3 !== -1) failed = 1; + $display("%0d", lu_to_si_res4); if (lu_to_si_res4 !== 1) failed = 1; + $display(""); + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc8.v b/ivtest/ivltests/constfunc8.v new file mode 100644 index 000000000..1938c1ff9 --- /dev/null +++ b/ivtest/ivltests/constfunc8.v @@ -0,0 +1,43 @@ +// Check variable initialisation in constant functions. +module constfunc8(); + +function real uninitialised_r(input dummy); + real value; + uninitialised_r = value; +endfunction + +function [7:0] uninitialised_2(input dummy); + reg bool [5:0] value; + uninitialised_2 = {1'b1, value, 1'b1}; +endfunction + +function [7:0] uninitialised_4(input dummy); + reg [5:0] value; + uninitialised_4 = {1'b1, value, 1'b1}; +endfunction + +localparam result_r = uninitialised_r(0); +localparam result_2 = uninitialised_2(0); +localparam result_4 = uninitialised_4(0); + +reg failed; + +initial begin + failed = 0; + + $display("%0g", result_r); + if (result_r != 0.0) failed = 1; + + $display("%b", result_2); + if (result_2 !== 8'b10000001) failed = 1; + + $display("%b", result_4); + if (result_4 !== 8'b1xxxxxx1) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/constfunc9.v b/ivtest/ivltests/constfunc9.v new file mode 100644 index 000000000..7e1188a75 --- /dev/null +++ b/ivtest/ivltests/constfunc9.v @@ -0,0 +1,29 @@ +// Test disable statements inside a constant function +module constfunc10(); + +function [31:0] pow2(input [5:0] x); + +begin:body + pow2 = 1; + while (1) begin:loop + if (x == 0) disable body; + pow2 = 2 * pow2; + x = x - 1; + disable loop; + pow2 = 0; + end +end + +endfunction + +localparam val = pow2(8); + +initial begin + $display("%0d", val); + if (val === 256) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/constmult.v b/ivtest/ivltests/constmult.v new file mode 100644 index 000000000..65dbd78c7 --- /dev/null +++ b/ivtest/ivltests/constmult.v @@ -0,0 +1,38 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate constant multiplication in array define. +// +// + +module main (); + +reg [5 * 2: 0] val1; +reg [10'h1 * 10: 0 ] val2 ; + +initial + begin + val1 = 11'h1 * 5; + val2 = 11'h2 * 4; + if((val1 === 11'h5) && (val2 === 11'h8)) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/consttern.v b/ivtest/ivltests/consttern.v new file mode 100644 index 000000000..9473b3fba --- /dev/null +++ b/ivtest/ivltests/consttern.v @@ -0,0 +1,12 @@ +module rega(A); +input [0:0] A; +endmodule + +module test(A); +input [0:0] A; + + rega a (.A(A[(5 > 4 ? 0 : 1) : 0])); + rega b (.A(A[(4 < 5 ? 0 : 1) : 0])); + + initial $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/contrib8.1.v b/ivtest/ivltests/contrib8.1.v new file mode 100644 index 000000000..f4cc167c7 --- /dev/null +++ b/ivtest/ivltests/contrib8.1.v @@ -0,0 +1,41 @@ +// Copyright (C) 1999 Motorola, Inc. + +// This program is free software; you can redistribute it and/or +// modify it under the terms of the GNU General Public License +// as published by the Free Software Foundation; either version 2 +// of the License, or (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +// +// 9/7/99 - SDW - Added if(!a) FAILED else PASSED + +module blahblah (); + parameter foo = 1; + + reg [31:0] a; + + initial + begin + test(a); + if(a != 1) + $display("FAILED - contrib 8.1 foo not passed into task - bad scope"); + else + $display("PASSED"); + end + + + task test; + output blah; + begin + blah = foo; + end + endtask // test + +endmodule // blahblah diff --git a/ivtest/ivltests/contrib8.2.v b/ivtest/ivltests/contrib8.2.v new file mode 100644 index 000000000..dec167142 --- /dev/null +++ b/ivtest/ivltests/contrib8.2.v @@ -0,0 +1,67 @@ +/* + * Copyright (c) 1998 Philips Semiconductors (Stefan.Thiede@sv.sc.philips.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +*/ +// 9/7/99 - SDW - Added a PASSED message - no functional checking needed + + +module test(); +wire [1:0] a; +wire [9:0] b; +wire [0:9] d; +a a1(.a(c)); +b b1(.a(a[0])); +c ci(.a({a, b})); +d d1(.a({d[0:9], a[1:0]}), .d(c)); +f f(a); +a a3(a[1]); +a a4({a[1]}); +g g({a,b}); +e e(); + +initial + $display("PASSED"); +endmodule + +module a(a); +input a; +endmodule + + +module b(.a(b)); +input b; +endmodule + +module c(.a({b, c}), ); +input [10:0] b; +input c; +endmodule + +module d(.a({b, c}), d); +input [10:0] b; +input c, d; +endmodule + +module e(); +endmodule + +module f({a, b}); +input a, b; +endmodule +module g(a); +input [11:0] a; +endmodule diff --git a/ivtest/ivltests/contrib8.3.v b/ivtest/ivltests/contrib8.3.v new file mode 100644 index 000000000..d889dc524 --- /dev/null +++ b/ivtest/ivltests/contrib8.3.v @@ -0,0 +1,34 @@ +/* + * Copyright (c) 1998 Philips Semiconductors (Stefan.Thiede@sv.sc.philips.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +*/ + +module test(); + +MUX_REG_8x8 PAGE_REG_B3 ( + .CLK (CLK), + /* + .IN (DATA_RES[31:24]), + .OUT (PAGE[31:24]), + .EN_IN (EN_B3), + .EN_OUT (PAGE_SEL), + */ + .TC (), + .TD (), + .TQ ()); + +endmodule diff --git a/ivtest/ivltests/contrib8.4.v b/ivtest/ivltests/contrib8.4.v new file mode 100644 index 000000000..828c75696 --- /dev/null +++ b/ivtest/ivltests/contrib8.4.v @@ -0,0 +1,28 @@ +/* + * Copyright (c) Peter Monta (pmonta@halibut.imedia.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +*/ + +module main; +wire [4:0] a; +reg [4:0] b; +initial +b = {5{a[4]}}; +// b = {5{1'b0}}; // this works +initial + $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/contrib8.5.v b/ivtest/ivltests/contrib8.5.v new file mode 100644 index 000000000..16f2e27fb --- /dev/null +++ b/ivtest/ivltests/contrib8.5.v @@ -0,0 +1,78 @@ +// +// Copyright (c) 1999 Steve Wilson (stevew@home.com) +// Based on code contributed by Peter Monta (pmonta@imedia.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate XOR op using non-blocking assignment +// + +module main; +reg [7:0] a; +reg b; +reg c; +reg error; + +initial + begin + #1; + error = 0; + for(a = 0; a <= 8'h1; a = a + 1) + begin + b = 0; + #1 ; + if(a) + begin + if(!c) + begin + $display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c); + error = 1; + end + end + if(!a) + begin + if(c) + begin + $display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c); + error = 1; + end + end + b = 1; + #1 ; + if(!a) + begin + if(!c) + begin + $display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c); + error = 1; + end + end + if(a) + begin + if(c) + begin + $display("FAILED - XOR a=%b,b=%b,c=%b",a,b,c); + error = 1; + end + end + end + if(!error) + $display("PASSED"); + end + +always @(a or b) + c <= a ^ b; +endmodule diff --git a/ivtest/ivltests/countdrivers1.v b/ivtest/ivltests/countdrivers1.v new file mode 100644 index 000000000..19d797a85 --- /dev/null +++ b/ivtest/ivltests/countdrivers1.v @@ -0,0 +1,210 @@ +module test(); + +wire n0; +wire n1; +wire n2; +wire n3; +wire n4; +wand n5; +wor n6; + +assign n1 = 1'b0; +assign n2 = 1'b1; +assign n3 = 1'bx; + +assign n4 = 1'b0; +assign n4 = 1'b0; +assign n4 = 1'b1; +assign n4 = 1'b1; +assign n4 = 1'b1; +assign n4 = 1'bx; + +assign n5 = 1'b0; +assign n5 = 1'b0; +assign n5 = 1'b0; +assign n5 = 1'b1; +assign n5 = 1'b1; +assign n5 = 1'bx; + +assign n6 = 1'b0; +assign n6 = 1'b1; +assign n6 = 1'b1; +assign n6 = 1'bx; +assign n6 = 1'bx; +assign n6 = 1'bx; + +integer multi; +integer forced; +integer countD; +integer count0; +integer count1; +integer countX; + +reg failed = 0; + +task check_results; + +input integer expected_multi; +input integer expected_forced; +input integer expected_countD; +input integer expected_count0; +input integer expected_count1; +input integer expected_countX; + +begin + $write("multi = %0d ", multi); + if (multi !== expected_multi) failed = 1; + if (expected_forced != -1) begin + $write("forced = %0d ", forced); + if (forced !== expected_forced) failed = 1; + end + if (expected_countD != -1) begin + $write("countD = %0d ", countD); + if (countD !== expected_countD) failed = 1; + end + if (expected_count0 != -1) begin + $write("count0 = %0d ", count0); + if (count0 !== expected_count0) failed = 1; + end + if (expected_count1 != -1) begin + $write("count1 = %0d ", count1); + if (count1 !== expected_count1) failed = 1; + end + if (expected_countX != -1) begin + $write("countX = %0d ", countX); + if (countX !== expected_countX) failed = 1; + end + $write("\n"); +end + +endtask + +initial begin + #0; // wait for initial values to propagate + + // test undriven net + multi = $countdrivers(n0); + check_results(0, -1, -1, -1, -1, -1); + multi = $countdrivers(n0, forced); + check_results(0, 0, -1, -1, -1, -1); + multi = $countdrivers(n0, forced, countD); + check_results(0, 0, 0, -1, -1, -1); + multi = $countdrivers(n0, forced, countD, count0); + check_results(0, 0, 0, 0, -1, -1); + multi = $countdrivers(n0, forced, countD, count0, count1); + check_results(0, 0, 0, 0, 0, -1); + multi = $countdrivers(n0, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + force n0 = 1'bx; + multi = $countdrivers(n0, forced, countD, count0, count1, countX); + check_results(0, 1, 0, 0, 0, 0); + + // test net driven to 0 + multi = $countdrivers(n1); + check_results(0, -1, -1, -1, -1, -1); + multi = $countdrivers(n1, forced); + check_results(0, 0, -1, -1, -1, -1); + multi = $countdrivers(n1, forced, countD); + check_results(0, 0, 1, -1, -1, -1); + multi = $countdrivers(n1, forced, countD, count0); + check_results(0, 0, 1, 1, -1, -1); + multi = $countdrivers(n1, forced, countD, count0, count1); + check_results(0, 0, 1, 1, 0, -1); + multi = $countdrivers(n1, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + force n1 = 1'bx; + multi = $countdrivers(n1, forced, countD, count0, count1, countX); + check_results(0, 1, 1, 1, 0, 0); + + // test net driven to 1 + multi = $countdrivers(n2); + check_results(0, -1, -1, -1, -1, -1); + multi = $countdrivers(n2, forced); + check_results(0, 0, -1, -1, -1, -1); + multi = $countdrivers(n2, forced, countD); + check_results(0, 0, 1, -1, -1, -1); + multi = $countdrivers(n2, forced, countD, count0); + check_results(0, 0, 1, 0, -1, -1); + multi = $countdrivers(n2, forced, countD, count0, count1); + check_results(0, 0, 1, 0, 1, -1); + multi = $countdrivers(n2, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + force n2 = 1'bx; + multi = $countdrivers(n2, forced, countD, count0, count1, countX); + check_results(0, 1, 1, 0, 1, 0); + + // test net driven to X + multi = $countdrivers(n3); + check_results(0, -1, -1, -1, -1, -1); + multi = $countdrivers(n3, forced); + check_results(0, 0, -1, -1, -1, -1); + multi = $countdrivers(n3, forced, countD); + check_results(0, 0, 1, -1, -1, -1); + multi = $countdrivers(n3, forced, countD, count0); + check_results(0, 0, 1, 0, -1, -1); + multi = $countdrivers(n3, forced, countD, count0, count1); + check_results(0, 0, 1, 0, 0, -1); + multi = $countdrivers(n3, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 0, 1); + force n3 = 1'bx; + multi = $countdrivers(n3, forced, countD, count0, count1, countX); + check_results(0, 1, 1, 0, 0, 1); + + // test multi-driven net + multi = $countdrivers(n4); + check_results(1, -1, -1, -1, -1, -1); + multi = $countdrivers(n4, forced); + check_results(1, 0, -1, -1, -1, -1); + multi = $countdrivers(n4, forced, countD); + check_results(1, 0, 6, -1, -1, -1); + multi = $countdrivers(n4, forced, countD, count0); + check_results(1, 0, 6, 2, -1, -1); + multi = $countdrivers(n4, forced, countD, count0, count1); + check_results(1, 0, 6, 2, 3, -1); + multi = $countdrivers(n4, forced, countD, count0, count1, countX); + check_results(1, 0, 6, 2, 3, 1); + force n4 = 1'bx; + multi = $countdrivers(n4, forced, countD, count0, count1, countX); + check_results(1, 1, 6, 2, 3, 1); + + // test wire and + multi = $countdrivers(n5); + check_results(1, -1, -1, -1, -1, -1); + multi = $countdrivers(n5, forced); + check_results(1, 0, -1, -1, -1, -1); + multi = $countdrivers(n5, forced, countD); + check_results(1, 0, 6, -1, -1, -1); + multi = $countdrivers(n5, forced, countD, count0); + check_results(1, 0, 6, 3, -1, -1); + multi = $countdrivers(n5, forced, countD, count0, count1); + check_results(1, 0, 6, 3, 2, -1); + multi = $countdrivers(n5, forced, countD, count0, count1, countX); + check_results(1, 0, 6, 3, 2, 1); + force n5 = 1'bx; + multi = $countdrivers(n5, forced, countD, count0, count1, countX); + check_results(1, 1, 6, 3, 2, 1); + + // test wire or + multi = $countdrivers(n6); + check_results(1, -1, -1, -1, -1, -1); + multi = $countdrivers(n6, forced); + check_results(1, 0, -1, -1, -1, -1); + multi = $countdrivers(n6, forced, countD); + check_results(1, 0, 6, -1, -1, -1); + multi = $countdrivers(n6, forced, countD, count0); + check_results(1, 0, 6, 1, -1, -1); + multi = $countdrivers(n6, forced, countD, count0, count1); + check_results(1, 0, 6, 1, 2, -1); + multi = $countdrivers(n6, forced, countD, count0, count1, countX); + check_results(1, 0, 6, 1, 2, 3); + force n6 = 1'bx; + multi = $countdrivers(n6, forced, countD, count0, count1, countX); + check_results(1, 1, 6, 1, 2, 3); + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/countdrivers2.v b/ivtest/ivltests/countdrivers2.v new file mode 100644 index 000000000..bebca505e --- /dev/null +++ b/ivtest/ivltests/countdrivers2.v @@ -0,0 +1,203 @@ +module test(); + +wire [1:0] n0 = 2'bzx; +wire [1:0] n1 = 2'b0x; +wire [1:0] n2 = 2'b1x; +wire [1:0] n3 = 2'bxx; +wire [1:0] n4 = 2'bxx; +wand [1:0] n5 = 2'bxx; +wor [1:0] n6 = 2'bxx; + +assign n4 = 2'b0x; +assign n4 = 2'b0x; +assign n4 = 2'b1x; +assign n4 = 2'b1x; +assign n4 = 2'b1x; + +assign n5 = 2'b0x; +assign n5 = 2'b0x; +assign n5 = 2'b0x; +assign n5 = 2'b1x; +assign n5 = 2'b1x; + +assign n6 = 2'b0x; +assign n6 = 2'b1x; +assign n6 = 2'b1x; +assign n6 = 2'bxx; +assign n6 = 2'bxx; + +reg [15:0] multi; +reg [15:0] forced; +reg [15:0] countD; +reg [15:0] count0; +reg [15:0] count1; +reg [15:0] countX; + +reg failed = 0; + +task check_results; + +input integer expected_multi; +input integer expected_forced; +input integer expected_countD; +input integer expected_count0; +input integer expected_count1; +input integer expected_countX; + +begin + $write("multi = %0d ", multi); + if (multi !== expected_multi) failed = 1; + if (expected_forced != -1) begin + $write("forced = %0d ", forced); + if (forced !== expected_forced) failed = 1; + end + if (expected_countD != -1) begin + $write("countD = %0d ", countD); + if (countD !== expected_countD) failed = 1; + end + if (expected_count0 != -1) begin + $write("count0 = %0d ", count0); + if (count0 !== expected_count0) failed = 1; + end + if (expected_count1 != -1) begin + $write("count1 = %0d ", count1); + if (count1 !== expected_count1) failed = 1; + end + if (expected_countX != -1) begin + $write("countX = %0d ", countX); + if (countX !== expected_countX) failed = 1; + end + $write("\n"); +end + +endtask + +initial begin + #0; // wait for initial values to propagate + + // test undriven net + multi = $countdrivers(n0[1]); + check_results(0, -1, -1, -1, -1, -1); + multi = $countdrivers(n0[1], forced); + check_results(0, 0, -1, -1, -1, -1); + multi = $countdrivers(n0[1], forced, countD); + check_results(0, 0, 0, -1, -1, -1); + multi = $countdrivers(n0[1], forced, countD, count0); + check_results(0, 0, 0, 0, -1, -1); + multi = $countdrivers(n0[1], forced, countD, count0, count1); + check_results(0, 0, 0, 0, 0, -1); + multi = $countdrivers(n0[1], forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + force n0 = 2'bxx; + multi = $countdrivers(n0[1], forced, countD, count0, count1, countX); + check_results(0, 1, 0, 0, 0, 0); + + // test net driven to 0 + multi = $countdrivers(n1[1]); + check_results(0, -1, -1, -1, -1, -1); + multi = $countdrivers(n1[1], forced); + check_results(0, 0, -1, -1, -1, -1); + multi = $countdrivers(n1[1], forced, countD); + check_results(0, 0, 1, -1, -1, -1); + multi = $countdrivers(n1[1], forced, countD, count0); + check_results(0, 0, 1, 1, -1, -1); + multi = $countdrivers(n1[1], forced, countD, count0, count1); + check_results(0, 0, 1, 1, 0, -1); + multi = $countdrivers(n1[1], forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + force n1 = 2'bxx; + multi = $countdrivers(n1[1], forced, countD, count0, count1, countX); + check_results(0, 1, 1, 1, 0, 0); + + // test net driven to 1 + multi = $countdrivers(n2[1]); + check_results(0, -1, -1, -1, -1, -1); + multi = $countdrivers(n2[1], forced); + check_results(0, 0, -1, -1, -1, -1); + multi = $countdrivers(n2[1], forced, countD); + check_results(0, 0, 1, -1, -1, -1); + multi = $countdrivers(n2[1], forced, countD, count0); + check_results(0, 0, 1, 0, -1, -1); + multi = $countdrivers(n2[1], forced, countD, count0, count1); + check_results(0, 0, 1, 0, 1, -1); + multi = $countdrivers(n2[1], forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + force n2 = 2'bxx; + multi = $countdrivers(n2[1], forced, countD, count0, count1, countX); + check_results(0, 1, 1, 0, 1, 0); + + // test net driven to X + multi = $countdrivers(n3[1]); + check_results(0, -1, -1, -1, -1, -1); + multi = $countdrivers(n3[1], forced); + check_results(0, 0, -1, -1, -1, -1); + multi = $countdrivers(n3[1], forced, countD); + check_results(0, 0, 1, -1, -1, -1); + multi = $countdrivers(n3[1], forced, countD, count0); + check_results(0, 0, 1, 0, -1, -1); + multi = $countdrivers(n3[1], forced, countD, count0, count1); + check_results(0, 0, 1, 0, 0, -1); + multi = $countdrivers(n3[1], forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 0, 1); + force n3 = 2'bxx; + multi = $countdrivers(n3[1], forced, countD, count0, count1, countX); + check_results(0, 1, 1, 0, 0, 1); + + // test multi-driven net + multi = $countdrivers(n4[1]); + check_results(1, -1, -1, -1, -1, -1); + multi = $countdrivers(n4[1], forced); + check_results(1, 0, -1, -1, -1, -1); + multi = $countdrivers(n4[1], forced, countD); + check_results(1, 0, 6, -1, -1, -1); + multi = $countdrivers(n4[1], forced, countD, count0); + check_results(1, 0, 6, 2, -1, -1); + multi = $countdrivers(n4[1], forced, countD, count0, count1); + check_results(1, 0, 6, 2, 3, -1); + multi = $countdrivers(n4[1], forced, countD, count0, count1, countX); + check_results(1, 0, 6, 2, 3, 1); + force n4 = 2'bxx; + multi = $countdrivers(n4[1], forced, countD, count0, count1, countX); + check_results(1, 1, 6, 2, 3, 1); + + // test wire and + multi = $countdrivers(n5[1]); + check_results(1, -1, -1, -1, -1, -1); + multi = $countdrivers(n5[1], forced); + check_results(1, 0, -1, -1, -1, -1); + multi = $countdrivers(n5[1], forced, countD); + check_results(1, 0, 6, -1, -1, -1); + multi = $countdrivers(n5[1], forced, countD, count0); + check_results(1, 0, 6, 3, -1, -1); + multi = $countdrivers(n5[1], forced, countD, count0, count1); + check_results(1, 0, 6, 3, 2, -1); + multi = $countdrivers(n5[1], forced, countD, count0, count1, countX); + check_results(1, 0, 6, 3, 2, 1); + force n5 = 2'bxx; + multi = $countdrivers(n5[1], forced, countD, count0, count1, countX); + check_results(1, 1, 6, 3, 2, 1); + + // test wire or + multi = $countdrivers(n6[1]); + check_results(1, -1, -1, -1, -1, -1); + multi = $countdrivers(n6[1], forced); + check_results(1, 0, -1, -1, -1, -1); + multi = $countdrivers(n6[1], forced, countD); + check_results(1, 0, 6, -1, -1, -1); + multi = $countdrivers(n6[1], forced, countD, count0); + check_results(1, 0, 6, 1, -1, -1); + multi = $countdrivers(n6[1], forced, countD, count0, count1); + check_results(1, 0, 6, 1, 2, -1); + multi = $countdrivers(n6[1], forced, countD, count0, count1, countX); + check_results(1, 0, 6, 1, 2, 3); + force n6 = 2'bxx; + multi = $countdrivers(n6[1], forced, countD, count0, count1, countX); + check_results(1, 1, 6, 1, 2, 3); + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/countdrivers3.v b/ivtest/ivltests/countdrivers3.v new file mode 100644 index 000000000..f731b40a7 --- /dev/null +++ b/ivtest/ivltests/countdrivers3.v @@ -0,0 +1,174 @@ +module ts_pad ( + inout wire pad, + input wire oe, + input wire op +); + +assign pad = oe ? op : 1'bz; + +endmodule + +module test(); + +wire [1:0] bus; + +reg oe1 = 1'b0; +reg oe2 = 1'b0; +reg oe3 = 1'b0; +reg oe4 = 1'b0; +reg oe5 = 1'b0; +reg oe6 = 1'b0; + +wire op1 = 1'b0; +wire op2 = 1'b1; +wire op3 = 1'b1; +wire op4 = 1'b0; +wire op5 = 1'bx; +wire op6 = 1'bx; + +ts_pad pad1(bus[0], oe1, op1); +ts_pad pad2(bus[1], oe2, op2); + +ts_pad pad3(bus[0], oe3, op3); +ts_pad pad4(bus[1], oe4, op4); + +bufif1(bus[0], op5, oe5); +bufif1(bus[1], op6, oe6); + +integer multi; +integer forced; +integer countD; +integer count0; +integer count1; +integer countX; + +reg failed = 0; + +task check_results; + +input integer expected_multi; +input integer expected_forced; +input integer expected_countD; +input integer expected_count0; +input integer expected_count1; +input integer expected_countX; + +begin + $write("multi = %0d ", multi); + if (multi !== expected_multi) failed = 1; + if (expected_forced != -1) begin + $write("forced = %0d ", forced); + if (forced !== expected_forced) failed = 1; + end + if (expected_countD != -1) begin + $write("countD = %0d ", countD); + if (countD !== expected_countD) failed = 1; + end + if (expected_count0 != -1) begin + $write("count0 = %0d ", count0); + if (count0 !== expected_count0) failed = 1; + end + if (expected_count1 != -1) begin + $write("count1 = %0d ", count1); + if (count1 !== expected_count1) failed = 1; + end + if (expected_countX != -1) begin + $write("countX = %0d ", countX); + if (countX !== expected_countX) failed = 1; + end + $write("\n"); +end + +endtask + +initial begin + #1; + multi = $countdrivers(bus[0], forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(bus[1], forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + $display(""); + + oe1 = 1'b1; + #1; + multi = $countdrivers(bus[0], forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(bus[1], forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + $display(""); + + oe2 = 1'b1; + #1; + multi = $countdrivers(bus[0], forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(bus[1], forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + $display(""); + + oe3 = 1'b1; + #1; + multi = $countdrivers(bus[0], forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(bus[1], forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + $display(""); + + oe4 = 1'b1; + #1; + multi = $countdrivers(bus[0], forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(bus[1], forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + $display(""); + + oe5 = 1'b1; + #1; + multi = $countdrivers(bus[0], forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(bus[1], forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + $display(""); + + oe6 = 1'b1; + #1; + multi = $countdrivers(bus[0], forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(bus[1], forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + $display(""); + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/countdrivers4.v b/ivtest/ivltests/countdrivers4.v new file mode 100644 index 000000000..9b2c21561 --- /dev/null +++ b/ivtest/ivltests/countdrivers4.v @@ -0,0 +1,175 @@ +module ts_pad ( + inout wire pad, + input wire oe, + input wire op +); + +assign pad = oe ? op : 1'bz; + +endmodule + +module test(); + +wire bus0; +wire bus1; + +reg oe1 = 1'b0; +reg oe2 = 1'b0; +reg oe3 = 1'b0; +reg oe4 = 1'b0; +reg oe5 = 1'b0; +reg oe6 = 1'b0; + +wire op1 = 1'b0; +wire op2 = 1'b1; +wire op3 = 1'b1; +wire op4 = 1'b0; +wire op5 = 1'bx; +wire op6 = 1'bx; + +ts_pad pad1(bus0, oe1, op1); +ts_pad pad2(bus1, oe2, op2); + +ts_pad pad3(bus0, oe3, op3); +ts_pad pad4(bus1, oe4, op4); + +bufif1(bus0, op5, oe5); +bufif1(bus1, op6, oe6); + +integer multi; +integer forced; +integer countD; +integer count0; +integer count1; +integer countX; + +reg failed = 0; + +task check_results; + +input integer expected_multi; +input integer expected_forced; +input integer expected_countD; +input integer expected_count0; +input integer expected_count1; +input integer expected_countX; + +begin + $write("multi = %0d ", multi); + if (multi !== expected_multi) failed = 1; + if (expected_forced != -1) begin + $write("forced = %0d ", forced); + if (forced !== expected_forced) failed = 1; + end + if (expected_countD != -1) begin + $write("countD = %0d ", countD); + if (countD !== expected_countD) failed = 1; + end + if (expected_count0 != -1) begin + $write("count0 = %0d ", count0); + if (count0 !== expected_count0) failed = 1; + end + if (expected_count1 != -1) begin + $write("count1 = %0d ", count1); + if (count1 !== expected_count1) failed = 1; + end + if (expected_countX != -1) begin + $write("countX = %0d ", countX); + if (countX !== expected_countX) failed = 1; + end + $write("\n"); +end + +endtask + +initial begin + #1; + multi = $countdrivers(bus0, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(bus1, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + $display(""); + + oe1 = 1'b1; + #1; + multi = $countdrivers(bus0, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(bus1, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 0, 0, 0, 0); + $display(""); + + oe2 = 1'b1; + #1; + multi = $countdrivers(bus0, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(bus1, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + $display(""); + + oe3 = 1'b1; + #1; + multi = $countdrivers(bus0, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(bus1, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + $display(""); + + oe4 = 1'b1; + #1; + multi = $countdrivers(bus0, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(bus1, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + $display(""); + + oe5 = 1'b1; + #1; + multi = $countdrivers(bus0, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(bus1, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 1, 0); + $display(""); + + oe6 = 1'b1; + #1; + multi = $countdrivers(bus0, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(bus1, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 1, 1, 1); + $display(""); + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/countdrivers5.v b/ivtest/ivltests/countdrivers5.v new file mode 100644 index 000000000..2c760809a --- /dev/null +++ b/ivtest/ivltests/countdrivers5.v @@ -0,0 +1,173 @@ +module test(); + +wire net1; +wire net2; +wire net3; +wire net4; +wire net5; + +reg src1; +reg src2; +reg src3; + +assign net1 = src1; +assign net2 = src2; +assign net3 = src3; + +tran(net4, net1); +tran(net4, net2); +tran(net5, net3); +tran(net5, net4); + +integer multi; +integer forced; +integer countD; +integer count0; +integer count1; +integer countX; + +reg failed = 0; + +task check_results; + +input integer expected_multi; +input integer expected_forced; +input integer expected_countD; +input integer expected_count0; +input integer expected_count1; +input integer expected_countX; + +begin + $write("multi = %0d ", multi); + if (multi !== expected_multi) failed = 1; + if (expected_forced != -1) begin + $write("forced = %0d ", forced); + if (forced !== expected_forced) failed = 1; + end + if (expected_countD != -1) begin + $write("countD = %0d ", countD); + if (countD !== expected_countD) failed = 1; + end + if (expected_count0 != -1) begin + $write("count0 = %0d ", count0); + if (count0 !== expected_count0) failed = 1; + end + if (expected_count1 != -1) begin + $write("count1 = %0d ", count1); + if (count1 !== expected_count1) failed = 1; + end + if (expected_countX != -1) begin + $write("countX = %0d ", countX); + if (countX !== expected_countX) failed = 1; + end + $write("\n"); +end + +endtask + +initial begin + src1 = 1'b0; src2 = 1'b0; src3 = 1'b0; + #1; + multi = $countdrivers(net1, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 2, 0, 0); + multi = $countdrivers(net2, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 2, 0, 0); + multi = $countdrivers(net3, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 2, 0, 0); + multi = $countdrivers(net4, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 3, 0, 0); + multi = $countdrivers(net5, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 2, 0, 0); + $display(""); + + src1 = 1'b1; src2 = 1'b0; src3 = 1'b0; + #1; + multi = $countdrivers(net1, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 0, 1, 1); + multi = $countdrivers(net2, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 0, 1); + multi = $countdrivers(net3, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 0, 1); + multi = $countdrivers(net4, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 0, 0, 3); + multi = $countdrivers(net5, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 0, 0, 2); + $display(""); + + src1 = 1'b1; src2 = 1'b1; src3 = 1'b0; + #1; + multi = $countdrivers(net1, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 0, 1, 1); + multi = $countdrivers(net2, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 0, 1, 1); + multi = $countdrivers(net3, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 1, 0, 1); + multi = $countdrivers(net4, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 0, 0, 3); + multi = $countdrivers(net5, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 0, 0, 2); + $display(""); + + src1 = 1'b1; src2 = 1'b1; src3 = 1'b1; + #1; + multi = $countdrivers(net1, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 0, 2, 0); + multi = $countdrivers(net2, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 0, 2, 0); + multi = $countdrivers(net3, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 0, 2, 0); + multi = $countdrivers(net4, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 0, 3, 0); + multi = $countdrivers(net5, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 0, 2, 0); + $display(""); + + src1 = 1'b1; src2 = 1'bz; src3 = 1'bz; + #1; + multi = $countdrivers(net1, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 0, 2, 0); + multi = $countdrivers(net2, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + multi = $countdrivers(net3, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + multi = $countdrivers(net4, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 0, 3, 0); + multi = $countdrivers(net5, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 0, 2, 0); + $display(""); + + src1 = 1'bz; src2 = 1'b0; src3 = 1'bz; + #1; + multi = $countdrivers(net1, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(net2, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 2, 0, 0); + multi = $countdrivers(net3, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 1, 0, 0); + multi = $countdrivers(net4, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 3, 0, 0); + multi = $countdrivers(net5, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 2, 0, 0); + $display(""); + + src1 = 1'bz; src2 = 1'bz; src3 = 1'b1; + #1; + multi = $countdrivers(net1, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + multi = $countdrivers(net2, forced, countD, count0, count1, countX); + check_results(0, 0, 1, 0, 1, 0); + multi = $countdrivers(net3, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 0, 2, 0); + multi = $countdrivers(net4, forced, countD, count0, count1, countX); + check_results(1, 0, 3, 0, 3, 0); + multi = $countdrivers(net5, forced, countD, count0, count1, countX); + check_results(1, 0, 2, 0, 2, 0); + $display(""); + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/cprop.v b/ivtest/ivltests/cprop.v new file mode 100644 index 000000000..a04ca33d3 --- /dev/null +++ b/ivtest/ivltests/cprop.v @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test triggers constant propagation through AND gates. + */ +module main; + + wire a = 1'b0; + wire b = 1'b1; + wire c = 1'b1; + wire d = 1'bx; + + wire out0, out1, out2, out3; + + and (out0, a, b); // Should be 0 + and (out1, b, c); // Should be 1 + and (out2, a, d); // Should be 0 because of a + and (out3, b, d); // Should be x + + initial begin + #0 if (out0 !== 1'b0) begin + $display("FAILED -- out0 = %b", out0); + $finish; + end + + if (out1 !== 1'b1) begin + $display("FAILED -- out1 = %b", out1); + $finish; + end + + if (out2 !== 1'b0) begin + $display("FAILED -- out2 = %b", out2); + $finish; + end + + if (out3 !== 1'bx) begin + $display("FAILED -- outx = %b", out3); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/credence20041209.v b/ivtest/ivltests/credence20041209.v new file mode 100644 index 000000000..86f430fec --- /dev/null +++ b/ivtest/ivltests/credence20041209.v @@ -0,0 +1,82 @@ +// Copyright C(O) 2004 Burnell G West +// The following text may be utilized and / or reproduced by anybody for +// any reason. +// +// verr.v +// + +module verr (clk, vout); + +input clk; +output vout; + +reg vout; +real start_edge; +real end_edge; + +wire trigger_en; +wire [9:0] v_value; + +initial vout = 1'b0; + +always @( posedge clk) + begin + if (trigger_en) + begin + start_edge = ( v_value[0] * 1.95) + + ( v_value[1] * 3.9 ) + + ( v_value[2] * 7.8 ) + + ( v_value[3] * 15.6 ) + + ( v_value[4] * 31.2 ) + + ( v_value[5] * 62.5 ) + + ( v_value[6] * 125 ) + + ( v_value[7] * 250 ) + + ( v_value[8] * 0 ) + + ( v_value[9] * 0 ) + + 0; + end_edge = start_edge + 100; // make pulse width = 1ns + end + else + begin + start_edge <= start_edge; + end_edge <= end_edge; + end + end + +endmodule + +module vtest; + +wire vout0, vout1, vout2, vout3, vout4, vout5, vout6, vout7, vout8, vout9; +wire vout10, vout11, vout12, vout13, vout14, vout15, vout16, vout17, +vout18, vout19; + +reg clk, bit0; + +verr v0 (clk, vout0); +verr v1 (clk, vout1); +verr v2 (clk, vout2); +verr v3 (clk, vout3); +verr v4 (clk, vout4); +verr v5 (clk, vout5); +verr v6 (clk, vout6); +verr v7 (clk, vout7); +verr v8 (clk, vout8); +verr v9 (clk, vout9); +verr v10 (clk, vout10); +verr v11 (clk, vout11); +verr v12 (clk, vout12); +verr v13 (clk, vout13); +verr v14 (clk, vout14); +verr v15 (clk, vout15); +verr v16 (clk, vout16); +verr v17 (clk, vout17); +verr v18 (clk, vout18); +verr v19 (clk, vout19); + +initial begin + #10000 $display("This test doesn't check itself."); + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/dangling_port.v b/ivtest/ivltests/dangling_port.v new file mode 100644 index 000000000..6e4cf9b66 --- /dev/null +++ b/ivtest/ivltests/dangling_port.v @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// $Id: dangling_port.v,v 1.1 2001/07/08 03:22:08 sib4 Exp $ +// $Log: dangling_port.v,v $ +// Revision 1.1 2001/07/08 03:22:08 sib4 +// Test for PR#209 +// +// +// Test for PR#209, VVP wrong nodangle of dangling port. + +module main; + + reg retval; + reg a, b; + + function f; + input dangle; + begin + f = retval; + end + endfunction + + initial + begin + #1 retval <= 1; + #1 a <= f(0); + #1 b <= f(1); + #1 $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/dcomp1.v b/ivtest/ivltests/dcomp1.v new file mode 100644 index 000000000..9995a3b26 --- /dev/null +++ b/ivtest/ivltests/dcomp1.v @@ -0,0 +1,42 @@ +/* dcomp1.v - this is a fragment of a larger program, which would + * dynamicly compute a more interesting value for the phdelay variable. + * + * It illustrates a problem in verilog-20010721 when computing + * time values for use in behavioral delays. + */ +`timescale 1ps / 1ps +module dcomp; + time phdelay; + parameter clk_period = 400; + parameter phoffset = 4; + time compdelay; + reg internal_Clk, Clk; + + initial begin + $monitor("%b %b %t %t %t", internal_Clk, Clk, phdelay, compdelay, $time); + phdelay = 0; + #2000; + phdelay = 13; + #2001; + $finish(0); + end // initial begin + + initial internal_Clk <= 0; + always #(clk_period/2) internal_Clk = ~internal_Clk; + + always @(internal_Clk) begin +// uncoment only one of the next four lines: +// #(phdelay); // works +// #(phdelay + phoffset); // fails + compdelay = phdelay + phoffset; #(compdelay); // fails +// compdelay = phdelay + 4; #(compdelay); // fails + + $display("got here"); + + Clk <= internal_Clk; + + // of course, this is what I really want... (but that's PR#105) + // Clk <= #(phdelay + phoffset + clk_period/2) internal_Clk; + end // always @ (internal_Clk) + +endmodule // dcomp diff --git a/ivtest/ivltests/deassign3.4A.v b/ivtest/ivltests/deassign3.4A.v new file mode 100644 index 000000000..2bcb1bda8 --- /dev/null +++ b/ivtest/ivltests/deassign3.4A.v @@ -0,0 +1,88 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate deassign reg_ident; + +module main ; + + +reg [31:0] value; +reg [1:0] control; +reg clock; +reg error; + +always @(posedge clock) + value = 3; + +always @(control) + if(control == 1) + assign value = 1; + else + if(control == 2) + assign value = 2; + else + deassign value ; + + +// Setup a clock generator. +always begin + #2; + clock = ~clock; + end + +initial + begin + clock = 0; + error = 0; + # 3; + if(value != 3) + begin + $display("FAILED - deassign3.4A - procedural assignment(1)"); + error = 1; + end + # 2; + control = 1; + # 1; + if(value != 1) + begin + $display("FAILED - deassign3.4A - procedural assignment(2)"); + error = 1; + end + # 1 ; + control = 2; + # 1 ; + if(value != 2) + begin + $display("FAILED - deassign3.4A - procedural assignment(3)"); + error = 1; + end + #1 ; + control = 0; + # 10; + if(value != 3) + begin + $display("FAILED - deassign3.4A - procedural assignment(4)"); + error = 1; + end + + if(error == 0) $display ("PASSED"); + $finish ; + + end + +endmodule diff --git a/ivtest/ivltests/dec2to4.vhd b/ivtest/ivltests/dec2to4.vhd new file mode 100644 index 000000000..d2e47368e --- /dev/null +++ b/ivtest/ivltests/dec2to4.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dec2to4 is + port (sel: in std_logic_vector (1 downto 0); + en: in std_logic; + y: out std_logic_vector (0 to 3) ); +end dec2to4; + +architecture dec2to4_rtl of dec2to4 is + begin + process (sel, en) + begin + if (en = '1') then + case sel is + when "00" => y <= "1000"; + when "01" => y <= "0100"; + when "10" => y <= "0010"; + when "11" => y <= "0001"; + when others => y <= "0000"; + end case; + else + y <= "0000"; + end if; + end process; +end dec2to4_rtl; diff --git a/ivtest/ivltests/decl_assign1.v b/ivtest/ivltests/decl_assign1.v new file mode 100644 index 000000000..2111f7e0b --- /dev/null +++ b/ivtest/ivltests/decl_assign1.v @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This module checks integer initialization syntax. + */ +module main; + + integer i = 8; + time t = 0; + + + initial begin + #1 if (i !== 8) begin + $display("FAILED -- i == %b", i); + $finish; + end + + if (t !== 0) begin + $display("FAILED -- t == %b", t); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/def_nettype.v b/ivtest/ivltests/def_nettype.v new file mode 100644 index 000000000..808440c65 --- /dev/null +++ b/ivtest/ivltests/def_nettype.v @@ -0,0 +1,397 @@ +module all; + reg pass; + + task automatic check; + input sig; + input val; + input [32*8:1] name; + begin + if (sig !== val) begin + $display("FAILED \"%0s\", expected %b, got %b", name, val, sig); + pass = 1'b0; + end + end + endtask + + initial begin + pass = 1'b1; + #100; + if (pass) $display("PASSED"); + end +endmodule + +/* Check the wire net type. */ +`default_nettype wire +module top_wire; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1'b0; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "wire(0,0)"); + in0 = 1'b0; in1 = 1'b1; + #1 all.check(tmp, 1'bx, "wire(0,1)"); + in0 = 1'b0; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "wire(0,x)"); + in0 = 1'b0; in1 = 1'bz; + #1 all.check(tmp, 1'b0, "wire(0,z)"); + + in0 = 1'b1; in1 = 1'b0; + #1 all.check(tmp, 1'bx, "wire(1,0)"); + in0 = 1'b1; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "wire(1,1)"); + in0 = 1'b1; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "wire(1,x)"); + in0 = 1'b1; in1 = 1'bz; + #1 all.check(tmp, 1'b1, "wire(1,z)"); + + in0 = 1'bx; in1 = 1'b0; + #1 all.check(tmp, 1'bx, "wire(x,0)"); + in0 = 1'bx; in1 = 1'b1; + #1 all.check(tmp, 1'bx, "wire(x,1)"); + in0 = 1'bx; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "wire(x,x)"); + in0 = 1'bx; in1 = 1'bz; + #1 all.check(tmp, 1'bx, "wire(x,z)"); + + in0 = 1'bz; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "wire(z,0)"); + in0 = 1'bz; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "wire(z,1)"); + in0 = 1'bz; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "wire(z,x)"); + in0 = 1'bz; in1 = 1'bz; + #1 all.check(tmp, 1'bz, "wire(z,z)"); + end +endmodule + +/* Check the tri net type (should be identical to wire). */ +`default_nettype tri +module top_tri; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1'b0; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "tri(0,0)"); + in0 = 1'b0; in1 = 1'b1; + #1 all.check(tmp, 1'bx, "tri(0,1)"); + in0 = 1'b0; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "tri(0,x)"); + in0 = 1'b0; in1 = 1'bz; + #1 all.check(tmp, 1'b0, "tri(0,z)"); + + in0 = 1'b1; in1 = 1'b0; + #1 all.check(tmp, 1'bx, "tri(1,0)"); + in0 = 1'b1; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "tri(1,1)"); + in0 = 1'b1; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "tri(1,x)"); + in0 = 1'b1; in1 = 1'bz; + #1 all.check(tmp, 1'b1, "tri(1,z)"); + + in0 = 1'bx; in1 = 1'b0; + #1 all.check(tmp, 1'bx, "tri(x,0)"); + in0 = 1'bx; in1 = 1'b1; + #1 all.check(tmp, 1'bx, "tri(x,1)"); + in0 = 1'bx; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "tri(x,x)"); + in0 = 1'bx; in1 = 1'bz; + #1 all.check(tmp, 1'bx, "tri(x,z)"); + + in0 = 1'bz; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "tri(z,0)"); + in0 = 1'bz; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "tri(z,1)"); + in0 = 1'bz; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "tri(z,x)"); + in0 = 1'bz; in1 = 1'bz; + #1 all.check(tmp, 1'bz, "tri(z,z)"); + end +endmodule + +/* Check the tri0 net type (should be the same as tri except z,z is 0). */ +`default_nettype tri0 +module top_tri0; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1'b0; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "tri0(0,0)"); + in0 = 1'b0; in1 = 1'b1; + #1 all.check(tmp, 1'bx, "tri0(0,1)"); + in0 = 1'b0; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "tri0(0,x)"); + in0 = 1'b0; in1 = 1'bz; + #1 all.check(tmp, 1'b0, "tri0(0,z)"); + + in0 = 1'b1; in1 = 1'b0; + #1 all.check(tmp, 1'bx, "tri0(1,0)"); + in0 = 1'b1; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "tri0(1,1)"); + in0 = 1'b1; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "tri0(1,x)"); + in0 = 1'b1; in1 = 1'bz; + #1 all.check(tmp, 1'b1, "tri0(1,z)"); + + in0 = 1'bx; in1 = 1'b0; + #1 all.check(tmp, 1'bx, "tri0(x,0)"); + in0 = 1'bx; in1 = 1'b1; + #1 all.check(tmp, 1'bx, "tri0(x,1)"); + in0 = 1'bx; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "tri0(x,x)"); + in0 = 1'bx; in1 = 1'bz; + #1 all.check(tmp, 1'bx, "tri0(x,z)"); + + in0 = 1'bz; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "tri0(z,0)"); + in0 = 1'bz; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "tri0(z,1)"); + in0 = 1'bz; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "tri0(z,x)"); + in0 = 1'bz; in1 = 1'bz; + #1 all.check(tmp, 1'b0, "tri0(z,z)"); + end +endmodule + +/* Check the tri1 net type (should be the same as tri except z,z is 1). */ +`default_nettype tri1 +module top_tri1; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1'b0; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "tri1(0,0)"); + in0 = 1'b0; in1 = 1'b1; + #1 all.check(tmp, 1'bx, "tri1(0,1)"); + in0 = 1'b0; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "tri1(0,x)"); + in0 = 1'b0; in1 = 1'bz; + #1 all.check(tmp, 1'b0, "tri1(0,z)"); + + in0 = 1'b1; in1 = 1'b0; + #1 all.check(tmp, 1'bx, "tri1(1,0)"); + in0 = 1'b1; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "tri1(1,1)"); + in0 = 1'b1; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "tri1(1,x)"); + in0 = 1'b1; in1 = 1'bz; + #1 all.check(tmp, 1'b1, "tri1(1,z)"); + + in0 = 1'bx; in1 = 1'b0; + #1 all.check(tmp, 1'bx, "tri1(x,0)"); + in0 = 1'bx; in1 = 1'b1; + #1 all.check(tmp, 1'bx, "tri1(x,1)"); + in0 = 1'bx; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "tri1(x,x)"); + in0 = 1'bx; in1 = 1'bz; + #1 all.check(tmp, 1'bx, "tri1(x,z)"); + + in0 = 1'bz; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "tri1(z,0)"); + in0 = 1'bz; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "tri1(z,1)"); + in0 = 1'bz; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "tri1(z,x)"); + in0 = 1'bz; in1 = 1'bz; + #1 all.check(tmp, 1'b1, "tri1(z,z)"); + end +endmodule + +/* Check the wand net type. */ +`default_nettype wand +module top_wand; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1'b0; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "wand(0,0)"); + in0 = 1'b0; in1 = 1'b1; + #1 all.check(tmp, 1'b0, "wand(0,1)"); + in0 = 1'b0; in1 = 1'bx; + #1 all.check(tmp, 1'b0, "wand(0,x)"); + in0 = 1'b0; in1 = 1'bz; + #1 all.check(tmp, 1'b0, "wand(0,z)"); + + in0 = 1'b1; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "wand(1,0)"); + in0 = 1'b1; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "wand(1,1)"); + in0 = 1'b1; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "wand(1,x)"); + in0 = 1'b1; in1 = 1'bz; + #1 all.check(tmp, 1'b1, "wand(1,z)"); + + in0 = 1'bx; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "wand(x,0)"); + in0 = 1'bx; in1 = 1'b1; + #1 all.check(tmp, 1'bx, "wand(x,1)"); + in0 = 1'bx; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "wand(x,x)"); + in0 = 1'bx; in1 = 1'bz; + #1 all.check(tmp, 1'bx, "wand(x,z)"); + + in0 = 1'bz; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "wand(z,0)"); + in0 = 1'bz; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "wand(z,1)"); + in0 = 1'bz; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "wand(z,x)"); + in0 = 1'bz; in1 = 1'bz; + #1 all.check(tmp, 1'bz, "wand(z,z)"); + end +endmodule + +/* Check the triand net type (should be the same as wand). */ +`default_nettype triand +module top_triand; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1'b0; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "triand(0,0)"); + in0 = 1'b0; in1 = 1'b1; + #1 all.check(tmp, 1'b0, "triand(0,1)"); + in0 = 1'b0; in1 = 1'bx; + #1 all.check(tmp, 1'b0, "triand(0,x)"); + in0 = 1'b0; in1 = 1'bz; + #1 all.check(tmp, 1'b0, "triand(0,z)"); + + in0 = 1'b1; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "triand(1,0)"); + in0 = 1'b1; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "triand(1,1)"); + in0 = 1'b1; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "triand(1,x)"); + in0 = 1'b1; in1 = 1'bz; + #1 all.check(tmp, 1'b1, "triand(1,z)"); + + in0 = 1'bx; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "triand(x,0)"); + in0 = 1'bx; in1 = 1'b1; + #1 all.check(tmp, 1'bx, "triand(x,1)"); + in0 = 1'bx; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "triand(x,x)"); + in0 = 1'bx; in1 = 1'bz; + #1 all.check(tmp, 1'bx, "triand(x,z)"); + + in0 = 1'bz; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "triand(z,0)"); + in0 = 1'bz; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "triand(z,1)"); + in0 = 1'bz; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "triand(z,x)"); + in0 = 1'bz; in1 = 1'bz; + #1 all.check(tmp, 1'bz, "triand(z,z)"); + end +endmodule + +/* Check the wor net type. */ +`default_nettype wor +module top_wor; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1'b0; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "wor(0,0)"); + in0 = 1'b0; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "wor(0,1)"); + in0 = 1'b0; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "wor(0,x)"); + in0 = 1'b0; in1 = 1'bz; + #1 all.check(tmp, 1'b0, "wor(0,z)"); + + in0 = 1'b1; in1 = 1'b0; + #1 all.check(tmp, 1'b1, "wor(1,0)"); + in0 = 1'b1; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "wor(1,1)"); + in0 = 1'b1; in1 = 1'bx; + #1 all.check(tmp, 1'b1, "wor(1,x)"); + in0 = 1'b1; in1 = 1'bz; + #1 all.check(tmp, 1'b1, "wor(1,z)"); + + in0 = 1'bx; in1 = 1'b0; + #1 all.check(tmp, 1'bx, "wor(x,0)"); + in0 = 1'bx; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "wor(x,1)"); + in0 = 1'bx; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "wor(x,x)"); + in0 = 1'bx; in1 = 1'bz; + #1 all.check(tmp, 1'bx, "wor(x,z)"); + + in0 = 1'bz; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "wor(z,0)"); + in0 = 1'bz; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "wor(z,1)"); + in0 = 1'bz; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "wor(z,x)"); + in0 = 1'bz; in1 = 1'bz; + #1 all.check(tmp, 1'bz, "wor(z,z)"); + end +endmodule + +/* Check the trior net type (should be the same as wor). */ +`default_nettype trior +module top_trior; + reg in0, in1; + + assign tmp = in0; + assign tmp = in1; + + initial begin + in0 = 1'b0; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "trior(0,0)"); + in0 = 1'b0; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "trior(0,1)"); + in0 = 1'b0; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "trior(0,x)"); + in0 = 1'b0; in1 = 1'bz; + #1 all.check(tmp, 1'b0, "trior(0,z)"); + + in0 = 1'b1; in1 = 1'b0; + #1 all.check(tmp, 1'b1, "trior(1,0)"); + in0 = 1'b1; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "trior(1,1)"); + in0 = 1'b1; in1 = 1'bx; + #1 all.check(tmp, 1'b1, "trior(1,x)"); + in0 = 1'b1; in1 = 1'bz; + #1 all.check(tmp, 1'b1, "trior(1,z)"); + + in0 = 1'bx; in1 = 1'b0; + #1 all.check(tmp, 1'bx, "trior(x,0)"); + in0 = 1'bx; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "trior(x,1)"); + in0 = 1'bx; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "trior(x,x)"); + in0 = 1'bx; in1 = 1'bz; + #1 all.check(tmp, 1'bx, "trior(x,z)"); + + in0 = 1'bz; in1 = 1'b0; + #1 all.check(tmp, 1'b0, "trior(z,0)"); + in0 = 1'bz; in1 = 1'b1; + #1 all.check(tmp, 1'b1, "trior(z,1)"); + in0 = 1'bz; in1 = 1'bx; + #1 all.check(tmp, 1'bx, "trior(z,x)"); + in0 = 1'bz; in1 = 1'bz; + #1 all.check(tmp, 1'bz, "trior(z,z)"); + end +endmodule diff --git a/ivtest/ivltests/def_nettype_none.v b/ivtest/ivltests/def_nettype_none.v new file mode 100644 index 000000000..60926712d --- /dev/null +++ b/ivtest/ivltests/def_nettype_none.v @@ -0,0 +1,17 @@ +/* + * 1364-2001 19.2 "When the `default_nettype is set to none, all nets must be + * explicitly declared. If a net is not explicitly declared, an error is + * generated." + */ + +module ok; +reg a; +assign b=a; +endmodule + +`default_nettype none + +module bad; +reg a; +assign b=a; +endmodule diff --git a/ivtest/ivltests/define1.v b/ivtest/ivltests/define1.v new file mode 100644 index 000000000..81705af27 --- /dev/null +++ b/ivtest/ivltests/define1.v @@ -0,0 +1,58 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Play with defines a bit +// + +`define NUM1 10 +`define NUM2 4'b0001 +`define NUM3 4'h4 +`define WIDTH 4 + +module define1 ; + +reg [`WIDTH-1:0] val ; +reg error; + +initial + begin + error = 0; + val = `NUM1 ; + if(val !== 10) + begin + error = 1; + $display("FAILED - define NUM1 10 didn't"); + end + + val = `NUM2 ; + if(val !== 4'h1) + begin + error = 1; + $display("FAILED - define NUM1 10 didn't"); + end + val = `NUM3 ; + if(val !== 4'b0100) + begin + error = 1; + $display("FAILED - define NUM1 10 didn't"); + end + if(error == 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/defparam.v b/ivtest/ivltests/defparam.v new file mode 100644 index 000000000..d82f0c5e4 --- /dev/null +++ b/ivtest/ivltests/defparam.v @@ -0,0 +1,76 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate defparam with list +// + +module NameA (); + +parameter ident0 = 12; +parameter ident1 = 20 ; + +wire [31:0] value0 = ident0; +wire [31:0] value1 = ident1; + +endmodule + +module main (); + +defparam main.testmodA.ident0 = 15; // Validate single val +defparam main.testmodB.ident1 = 16, // Validate list of vals + main.testmodB.ident0 = 17; // Validate single val + +reg error; + +NameA testmodA (); +NameA testmodB (); + +initial + begin + error = 0; + # 1; + if(main.testmodA.value0 !== 15) + begin + error = 1; + $display("FAILED - defparam.v main.testmodA.value0 != 15"); + end + # 1; + if(main.testmodA.value1 !== 20) + begin + error = 1; + $display("FAILED - defparam.v main.testmodA.value1 != 20"); + end + # 1; + if(main.testmodB.value0 !== 17) + begin + error = 1; + $display("FAILED - defparam.v main.testmodB.value0 != 17"); + end + # 1; + if(main.testmodB.value1 !== 16) + begin + error = 1; + $display("FAILED - defparam.v main.testmodB.value1 != 16"); + end + # 1; + if(error == 0) + $display("PASSED"); + end + + +endmodule diff --git a/ivtest/ivltests/defparam2.v b/ivtest/ivltests/defparam2.v new file mode 100644 index 000000000..badc26196 --- /dev/null +++ b/ivtest/ivltests/defparam2.v @@ -0,0 +1,43 @@ +/* + * This module demonstrates the ability to use a defparam to control + * the instantation of an instance array, and to also control + * parameter values within the instance array. + */ + +module main; + + localparam wid = 5; + reg [wid-1:0] clk; + + dut xx (.clk(clk)); + + // This defparam sets the desired with of the U instance vector. + defparam main.xx.wid = wid; + // These defparams set parameters within U instances. + defparam main.xx.U[0].number = 0; + defparam main.xx.U[1].number = 1; + defparam main.xx.U[2].number = 2; + defparam main.xx.U[3].number = 3; + defparam main.xx.U[4].number = 4; + + initial begin + clk = 0; + #1 clk = 1; + while (clk != 0) + #1 clk = clk << 1; + $finish(0); + end + +endmodule // main + +module dut #(parameter wid = 1) (input [wid-1:0] clk); + target U [wid-1:0] (.clk(clk)); +endmodule // + +module target(input wire clk); + + parameter number = 999; + always @(posedge clk) + $display("%m: number=%0d", number); + +endmodule // target diff --git a/ivtest/ivltests/defparam3.5.v b/ivtest/ivltests/defparam3.5.v new file mode 100644 index 000000000..1a856ddde --- /dev/null +++ b/ivtest/ivltests/defparam3.5.v @@ -0,0 +1,114 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate defparam + +module module_a (out0,in0); + +input in0; +output [5:0] out0; + +parameter [5:0] ident0 = 0; +parameter [5:0] ident1 = 5'h11; + +reg [5:0] out0; + +// Basic MUX switches on in0 +always @ (in0) + begin + if(in0) + out0 = ident0; + else + out0 = ident1; + end + +endmodule // module_a + +module module_b (out0,out1,in0,in1); + +input in0; +input in1; +output [5:0] out0; +output [5:0] out1; + +module_a testmodA (.out0(out0),.in0(in0)); +module_a testmodB (.out0(out1),.in0(in1)); + +endmodule // module_b + +module main (); + +reg in0,in1; +reg error; +wire [5:0] out0,out1; + +defparam NameB.testmodA.ident0 = 5'h4; +defparam NameB.testmodB.ident0 = 5'h5; +defparam NameB.testmodB.ident1 = 5'h6; + +module_b NameB (.out0(out0),.out1(out1), + .in0(in0),.in1(in1)); + + +initial + begin + error = 0; + #1 ; + in0 = 0; + #1 ; + if(out0 != 5'h11) + begin + $display("FAILED - defparam3.5A - Defparam testmodA.ident0"); + $display("out0 = %h",out0); + error = 1; + end + #1 ; + in0 = 1; + #1 ; + if(out0 != 5'h4) + begin + $display("FAILED - defparam3.5A - Defparam testmodA.ident0"); + error = 1; + end + #1; + in1 = 0; + #1; + if(out0 != 5'h4) // Validate the 0 side didn't change! + begin + $display("FAILED - defparam3.5A - Defparam testmodA.ident0"); + error = 1; + end + if(out1 != 5'h6) + begin + $display("FAILED - defparam3.5A - Defparam testmodB.ident1"); + error = 1; + end + #1; + in1 = 1; + #1; + if(out1 != 5'h5) + begin + $display("FAILED - defparam3.5A - Defparam testmodB.ident0"); + error = 1; + end + + + if(error == 0) + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/defparam3.v b/ivtest/ivltests/defparam3.v new file mode 100644 index 000000000..8342d1100 --- /dev/null +++ b/ivtest/ivltests/defparam3.v @@ -0,0 +1,46 @@ +/* + * This module demonstrates the ability to use a defparam to control + * the instantation of an instance array, and to also control + * parameter values within the instance array. + */ + +module main; + + localparam wid = 5; + reg [wid-1:0] clk; + + dut xx (.clk(clk)); + + // This defparam sets the desired with of the U instance vector. + defparam main.xx.wid = wid; + // These defparams set parameters within U instances. + defparam main.xx.sub[0].U.number = 0; + defparam main.xx.sub[1].U.number = 1; + defparam main.xx.sub[2].U.number = 2; + defparam main.xx.sub[3].U.number = 3; + defparam main.xx.sub[4].U.number = 4; + + initial begin + clk = 0; + #1 clk = 1; + while (clk != 0) + #1 clk = clk << 1; + $finish(0); + end + +endmodule // main + +module dut #(parameter wid = 1) (input [wid-1:0] clk); + genvar i; + for (i = 0 ; i < wid ; i = i+1) begin : sub + target U (.clk(clk[i])); + end +endmodule // + +module target(input wire clk); + + parameter number = 999; + always @(posedge clk) + $display("%m: number=%0d", number); + +endmodule // target diff --git a/ivtest/ivltests/defparam4.v b/ivtest/ivltests/defparam4.v new file mode 100644 index 000000000..a761dd0c4 --- /dev/null +++ b/ivtest/ivltests/defparam4.v @@ -0,0 +1,48 @@ +/* + * This module demonstrates the ability to use a defparam to control + * the instantation of an instance array, and to also control + * parameter values within the instance array. + */ + +module main; + + localparam wid = 5; + reg [wid-1:0] clk; + + if (wid > 0) begin : D + dut xx (.clk(clk)); + end + + // This defparam sets the desired with of the U instance vector. + defparam main.D.xx.wid = wid; + // These defparams set parameters within U instances. + defparam main.D.xx.sub[0].U.number = 0; + defparam main.D.xx.sub[1].U.number = 1; + defparam main.D.xx.sub[2].U.number = 2; + defparam main.D.xx.sub[3].U.number = 3; + defparam main.D.xx.sub[4].U.number = 4; + + initial begin + clk = 0; + #1 clk = 1; + while (clk != 0) + #1 clk = clk << 1; + $finish(0); + end + +endmodule // main + +module dut #(parameter wid = 1) (input [wid-1:0] clk); + genvar i; + for (i = 0 ; i < wid ; i = i+1) begin : sub + target U (.clk(clk[i])); + end +endmodule // + +module target(input wire clk); + + parameter number = 999; + always @(posedge clk) + $display("%m: number=%0d", number); + +endmodule // target diff --git a/ivtest/ivltests/delay.v b/ivtest/ivltests/delay.v new file mode 100644 index 000000000..f55a2ed43 --- /dev/null +++ b/ivtest/ivltests/delay.v @@ -0,0 +1,77 @@ +`timescale 1ns/100ps + +module assign_test; + + +reg clk; +reg cat1; +reg cat2; +reg cat3; +reg cat4; +reg foo1; +reg foo2; +reg foo3; +reg foo4; +reg bar1; +reg bar2; +reg bar3; +reg bar4; + + +initial begin + clk = 0; + #100 $finish(0); +end + + +always begin + clk = 0; + #50; + clk = 1; + #50; +end + + +always @(posedge clk) begin + cat1 = #1 1; + cat2 = #1 1; + cat3 = #1 1; + cat4 = #1 1; + foo1 = #1 1; + foo2 = #1 1; + foo3 = #1 1; + foo4 = #1 1; + bar1 <= #1 1; + bar2 <= #1 1; + bar3 <= #1 1; + bar4 <= #1 1; +end + + +always @(cat1) + $write("time=%0t, cat1=%0h\n", $time, cat1); + +always @(cat2) $write("time=%04d, cat2=%0h\n", $time, cat2); + +always @(cat3) $write("time=%04d, cat3=%0h\n", $time, cat3); + +always @(cat4) $write("time=%04d, cat4=%0h\n", $time, cat4); + +always @(foo1) $write("time=%04d, foo1=%0h\n", $time, foo1); + +always @(foo2) $write("time=%04d, foo2=%0h\n", $time, foo2); + +always @(foo3) $write("time=%04d, foo3=%0h\n", $time, foo3); + +always @(foo4) $write("time=%04d, foo4=%0h\n", $time, foo4); + +always @(bar1) $write("time=%04d, bar1=%0h\n", $time, bar1); + +always @(bar2) $write("time=%04d, bar2=%0h\n", $time, bar2); + +always @(bar3) $write("time=%04d, bar3=%0h\n", $time, bar3); + +always @(bar4) $write("time=%04d, bar4=%0h\n", $time, bar4); + + +endmodule diff --git a/ivtest/ivltests/delay2.v b/ivtest/ivltests/delay2.v new file mode 100644 index 000000000..9761cb460 --- /dev/null +++ b/ivtest/ivltests/delay2.v @@ -0,0 +1,73 @@ +/* + * This program is derived from iverilog issue # 1327436. + */ + +`timescale 1ns/1ns +module verilog_test (); + +reg [24:0] APAD; +wire [24:0] AIN; + +initial begin +// $dumpfile("dumpfile.vcd"); +// $dumpvars; + + APAD=25'h1ffffff; + #21 if (AIN !== APAD) begin + $display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time); + $finish; + end + + #79 + APAD=25'h1555555; + + #19 if (AIN !== 25'h1ffffff) begin + $display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time); + $finish; + end + #2 if (AIN !== 25'h1555555) begin + $display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time); + $finish; + end + + #79 + APAD=25'h0aaaaaa; + + #19 if (AIN !== 25'h1555555) begin + $display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time); + $finish; + end + #2 if (AIN !== 25'h0aaaaaa) begin + $display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time); + $finish; + end + + #79 + APAD=25'h1555555; + + #19 if (AIN !== 25'h0aaaaaa) begin + $display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time); + $finish; + end + #2 if (AIN !== 25'h1555555) begin + $display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time); + $finish; + end + + #79 + APAD=25'h0aaaaaa; + + #19 if (AIN !== 25'h1555555) begin + $display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time); + $finish; + end + #2 if (AIN !== 25'h0aaaaaa) begin + $display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time); + $finish; + end + + $display("PASSED"); +end + +assign #20 AIN= APAD; +endmodule diff --git a/ivtest/ivltests/delay3.v b/ivtest/ivltests/delay3.v new file mode 100644 index 000000000..614e5b10f --- /dev/null +++ b/ivtest/ivltests/delay3.v @@ -0,0 +1,59 @@ +module main; + + reg [7:0] period; + + reg drive; + wire trace; + + // This is the main point of the test. Non-constant delay expressions + // should work here. + assign #(period) trace = drive; + + initial begin + period = 8; + // Initially, set up a period=8 and get the trace to start + // following the drive. + #1 drive <= 1; + #9 if (trace !== drive) begin + $display("FAILED -- time=%0t, drive=%b, trace=%b", + $time, drive, trace); + $finish; + end + + // The drive should NOT change the trace before the period. + drive <= 0; + + #7 if (trace !== 1'b1) begin + $display("FAILED -- time=%0t, drive=%b, trace=%b", + $time, drive, trace); + $finish; + end + #2 if (trace !== drive) begin + $display("FAILED -- time=%0t, drive=%b, trace=%b", + $time, drive, trace); + $finish; + end + + // Change the period. + period = 6; + + // Now check that the new delay is taken. + #1 drive <= 1; + + #5 if (trace !== 1'b0) begin + $display("FAILED -- time=%0t, drive=%b, trace=%b", + $time, drive, trace); + $finish; + end + + #2 if (trace !== drive) begin + $display("FAILED -- time=%0t, drive=%b, trace=%b", + $time, drive, trace); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/delay4.v b/ivtest/ivltests/delay4.v new file mode 100644 index 000000000..6e96bbb7e --- /dev/null +++ b/ivtest/ivltests/delay4.v @@ -0,0 +1,59 @@ +module main; + + reg [7:0] period; + + reg drive; + wire trace; + + // This is the main point of the test. Non-constant delay expressions + // should work here. + assign #(period/3) trace = drive; + + initial begin + period = 8*3; + // Initially, set up a period=8 and get the trace to start + // following the drive. + #1 drive <= 1; + #9 if (trace !== drive) begin + $display("FAILED -- time=%0t, drive=%b, trace=%b", + $time, drive, trace); + $finish; + end + + // The drive should NOT change the trace before the period. + drive <= 0; + + #7 if (trace !== 1'b1) begin + $display("FAILED -- time=%0t, drive=%b, trace=%b", + $time, drive, trace); + $finish; + end + #2 if (trace !== drive) begin + $display("FAILED -- time=%0t, drive=%b, trace=%b", + $time, drive, trace); + $finish; + end + + // Change the period. + period = 6*3; + + // Now check that the new delay is taken. + #1 drive <= 1; + + #5 if (trace !== 1'b0) begin + $display("FAILED -- time=%0t, drive=%b, trace=%b", + $time, drive, trace); + $finish; + end + + #2 if (trace !== drive) begin + $display("FAILED -- time=%0t, drive=%b, trace=%b", + $time, drive, trace); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/delay5.v b/ivtest/ivltests/delay5.v new file mode 100644 index 000000000..ac2ede246 --- /dev/null +++ b/ivtest/ivltests/delay5.v @@ -0,0 +1,57 @@ +module main; + + time period; + reg drive; + + // This is the main point of the test. Non-constant delay expressions + // should work here. + wire #(period/3) trace = drive; + + initial begin + period = 8*3; + // Initially, set up a period=8 and get the trace to start + // following the drive. + #1 drive <= 1; + #9 if (trace !== drive) begin + $display("FAILED -- time=%0t, drive=%b, trace=%b", + $time, drive, trace); + $finish; + end + + // The drive should NOT change the trace before the period. + drive <= 0; + + #7 if (trace !== 1'b1) begin + $display("FAILED -- time=%0t, drive=%b, trace=%b", + $time, drive, trace); + $finish; + end + #2 if (trace !== drive) begin + $display("FAILED -- time=%0t, drive=%b, trace=%b", + $time, drive, trace); + $finish; + end + + // Change the period. + period = 6*3; + + // Now check that the new delay is taken. + #1 drive <= 1; + + #5 if (trace !== 1'b0) begin + $display("FAILED -- time=%0t, drive=%b, trace=%b", + $time, drive, trace); + $finish; + end + + #2 if (trace !== drive) begin + $display("FAILED -- time=%0t, drive=%b, trace=%b", + $time, drive, trace); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/delay_assign_nb.v b/ivtest/ivltests/delay_assign_nb.v new file mode 100644 index 000000000..57288560d --- /dev/null +++ b/ivtest/ivltests/delay_assign_nb.v @@ -0,0 +1,57 @@ +// +// Copyright (c) 2001 Stephen Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +/* + * This program tests the behavior of a simple non-blocking assignment + * with an internal delay. We can check that the value changes at the + * right time and not the wrong time. + */ + +module main ; + + reg a; + + initial begin + a = 0; + if (a !== 0) begin + $display("FAILED -- a at 0 is %b", a); + $finish; + end + + a <= #2 1; + + if (a !== 0) begin + $display("FAILED -- (0) a should still be 0 but is %b", a); + $finish; + end + + #1 if (a !== 0) begin + $display("FAILED -- (1) a should still be 0 but is %b", a); + $finish; + end + + #2 if (a !== 1'b1) begin + $display("FAILED -- a should now be 1, but is %b", a); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/delay_assign_nb2.v b/ivtest/ivltests/delay_assign_nb2.v new file mode 100644 index 000000000..473e23da9 --- /dev/null +++ b/ivtest/ivltests/delay_assign_nb2.v @@ -0,0 +1,48 @@ +// +// Copyright (c) 2002 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +/* + * This function captures the correctness of a non-constant delay + * that is internal to a non-blocking assignment. + */ + +module main; + + reg [7:0] delay = 0; + reg step; + + initial begin + delay = 2; + step = 0; + step <= #(delay) 1; + + #1 if (step !== 0) begin + $display("FAILED -- step=%b at time=1", step); + $finish; + end + + #2 if (step !== 1) begin + $display("FAILED == step=%b at time=3", step); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/delay_var.v b/ivtest/ivltests/delay_var.v new file mode 100644 index 000000000..02dd6adba --- /dev/null +++ b/ivtest/ivltests/delay_var.v @@ -0,0 +1,47 @@ +`begin_keywords "1364-2005" +`timescale 1ns/100ps + +module top; + parameter pdly = 1.2; + real rdly = 1.3; + integer idly = 1; + reg in = 1'b0; + wire gi, gf, gs, gt; + + wire #idly int = in; + wire #1.1 first = in; + wire #pdly second = in; + wire #rdly third = in; + + buf #idly (gi, in); + buf #1.1 (gf, in); + buf #pdly (gs, in); + buf #rdly (gt, in); + + initial begin + $monitor($realtime,, int,, first,, second,, third,, gi,, gf,, gs,, gt); + #0 in = 1'b1; + #2 in = 1'b0; + #4; + rdly = -6.1; // Since we are at 6 this will not wrap. + in = 1'b1; + @(third or gt) $display("Large delay: ", $realtime); + end + + initial #1.1 $display("Should be 1.1: ", $realtime); // This should be 1.1 + initial #pdly $display("Should be 1.2: ", $realtime); // This should be 1.2 + initial begin + #0; // We need this so that rdly has a defined value. + #rdly $display("Should be 1.3: ", $realtime); // This should be 1.3 + end + initial begin + #0; // We need this so that rdly has a defined value. + #idly $display("Should be 1.0: ", $realtime); // This should be 1.0 + end +endmodule + +`timescale 1ns/1ps +module top2; + initial #1.001 $display("Should be 1.001: ", $realtime); +endmodule +`end_keywords diff --git a/ivtest/ivltests/delayed_comp_reduct.v b/ivtest/ivltests/delayed_comp_reduct.v new file mode 100644 index 000000000..ec349fa0e --- /dev/null +++ b/ivtest/ivltests/delayed_comp_reduct.v @@ -0,0 +1,13 @@ +module top; + reg [4:0]cntr; + wire done; + wire allone; + + // A delayed comparison is only 1 bit wide. If this does not crash + // the run time then the compiler is producing correct code. + assign #1 done = cntr == 'd7; + // The same for a reduction. + assign #1 allone = &cntr; + + initial $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/delayed_sfunc.v b/ivtest/ivltests/delayed_sfunc.v new file mode 100644 index 000000000..fbc9df307 --- /dev/null +++ b/ivtest/ivltests/delayed_sfunc.v @@ -0,0 +1,29 @@ +// This test is mostly to make sure valgrind cleans up correctly. +`timescale 1ns/1ns +module top; + wire real rtm; + wire [31:0] res1, res2; + integer a = 10; + + assign #1 rtm = $realtime; + assign #1 res1 = $clog2(a); + lwr dut(res2, a); + + initial begin + $monitor($realtime,, rtm, res1,, res2,, a); + #5 a = 20; + end + +endmodule + +module lwr(out, in); + output [31:0] out; + input [31:0] in; + wire [31:0] out, in; + + assign out = $clog2(in); + + specify + (in => out) = (1, 1); + endspecify +endmodule diff --git a/ivtest/ivltests/deposit.v b/ivtest/ivltests/deposit.v new file mode 100644 index 000000000..3db98b9f8 --- /dev/null +++ b/ivtest/ivltests/deposit.v @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: deposit.v,v 1.4 2001/11/22 04:36:33 sib4 Exp $ + +// Test for vpi_put_value() to properly propagate in structural context. + +module deposit_test; + + reg ck; + + reg start; + initial start = 0; + +`ifdef RTL + + reg [3:0] cnt; + wire cnt_tc = &cnt; + + always @(posedge ck) + if (start | ~cnt_tc) + cnt <= cnt + 1; + +`else // !ifdef RTL + + wire [3:0] cnt; + wire [3:0] cnt_1; + wire [3:0] cnt_c; + wire cnt_tc; + wire ne, e; + + and (cnt_tc, cnt[0], cnt[1], cnt[2], cnt[3]); + not (ne, cnt_tc); + or (e, ne, start); + + had A0 (cnt[0], 1'b1, cnt_c[0], cnt_1[0]); + had A1 (cnt[1], cnt_c[0], cnt_c[1], cnt_1[1]); + had A2 (cnt[2], cnt_c[1], cnt_c[2], cnt_1[2]); + had A3 (cnt[3], cnt_c[2], cnt_c[3], cnt_1[3]); + + dffe C0 (ck, e, cnt_1[0], cnt[0]); + dffe C1 (ck, e, cnt_1[1], cnt[1]); + dffe C2 (ck, e, cnt_1[2], cnt[2]); + dffe C3 (ck, e, cnt_1[3], cnt[3]); + +`endif // !ifdef RTL + + integer r0; initial r0 = 0; + integer r1; initial r1 = 0; + + always + begin + #5 ck <= 0; + #4; + $display("%b %b %d %d", cnt, cnt_tc, r0, r1); + if (cnt_tc === 1'b0) r0 = r0 + 1; + if (cnt_tc === 1'b1) r1 = r1 + 1; + #1 ck <= 1; + end + + initial + begin + // $dumpfile("deposit.vcd"); + // $dumpvars(0, deposit_test); + #22; +`ifdef RTL + cnt <= 4'b 1010; +`else + $deposit(C0.Q, 1'b0); + $deposit(C1.Q, 1'b1); + $deposit(C2.Q, 1'b0); + $deposit(C3.Q, 1'b1); +`endif + #1 if (cnt !== 4'b1010) + $display("FAILED"); + #99; + $display("%d/%d", r0, r1); + if (r0===5 && r1===5) + $display("PASSED"); + else + $display("FAILED"); + $finish; + end + +endmodule + +`ifdef RTL +`else + +module dffe (CK, E, D, Q); + input CK, E, D; + output Q; + wire qq; + UDP_dffe ff (qq, CK, E, D); + buf #1 (Q, qq); +endmodule + +primitive UDP_dffe (q, cp, e, d); + output q; + reg q; + input cp, e, d; + table + (01) 1 1 : ? : 1 ; + (01) 1 0 : ? : 0 ; + * 0 ? : ? : - ; + * ? 1 : 1 : - ; + * ? 0 : 0 : - ; + (1x) ? ? : ? : - ; + (?0) ? ? : ? : - ; + ? ? * : ? : - ; + ? * ? : ? : - ; + endtable +endprimitive + +module had (A, B, C, S); + input A, B; + output C, S; + xor s (S, A, B); + and c (C, A, B); +endmodule + +`endif // !ifdef RTL diff --git a/ivtest/ivltests/deposit_wire.v b/ivtest/ivltests/deposit_wire.v new file mode 100644 index 000000000..0831ac02e --- /dev/null +++ b/ivtest/ivltests/deposit_wire.v @@ -0,0 +1,58 @@ +// +// Copyright (c) 2001 Steve Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +/* + * The $depost system task takes the inputs a depositible object and a + * value to deposit. The $deposit works like a blocking assignment, so + * the target takes the value right away. + * + * This example tests the $deposit on a wire object. What that means is + * that the wire takes on the deposited value, but that value doesn't + * stick if its normal input changes. + */ +module main ; + + reg in; + wire test = in; + + initial begin + in = 1'b0; + #1 if (test !== 1'b0) begin + $display("FAILED -- test starts out as %b", test); + //$finish; + end + + $deposit(test, 1'b1); + + #1 if (test !== 1'b1) begin + $display("FAILED -- test after deposit is %b", test); + $finish; + end + + in = 1'bz; + + #1 if (test !== 1'bz) begin + $display("FAILED -- test after input is %b", test); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/dff1.v b/ivtest/ivltests/dff1.v new file mode 100644 index 000000000..188e1a031 --- /dev/null +++ b/ivtest/ivltests/dff1.v @@ -0,0 +1,70 @@ +// Copyright (c) 2000 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + + // This tests DFF-like behavior. The clocked always block acts like a + // DFF, and if the -Fsynth flag to ivl is used, actually generates an + // LPM_FF device. + +module main () ; + + reg clk; + reg D, Q; + + always #10 clk = ~clk; + always @(posedge clk) Q = D; + + initial begin + clk = 0; + D = 0; + @(negedge clk) + if (Q !== 1'b0) + begin + $display("FAILED: %b !== %b", Q, D); + $finish; + end + + D = 1; + @(negedge clk) + if (Q !== 1'b1) + begin + $display("FAILED: %b !== %b", Q, D); + $finish; + end + + D = 'bx; + + @(negedge clk) + if (Q !== 1'bx) + begin + $display("FAILED: %b !== %b", Q, D); + $finish; + end + + D = 'bz; + @(negedge clk) + if (Q !== 1'bz) + begin + $display("FAILED: %b !== %b", Q, D); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin + +endmodule diff --git a/ivtest/ivltests/dffsynth.v b/ivtest/ivltests/dffsynth.v new file mode 100644 index 000000000..55d20de51 --- /dev/null +++ b/ivtest/ivltests/dffsynth.v @@ -0,0 +1,72 @@ +module main; + + reg [3:0] count; + reg CLOCK; + reg RSTn, SETn; + + (* ivl_synthesis_off *) + initial begin + CLOCK = 0; + RSTn = 0; + SETn = 1; + + #1 CLOCK = 1; + #1 CLOCK = 0; + + if (count !== 4'b0000) begin + $display("FAILED -- initial reset doesn't"); + $finish; + end + + RSTn = 1; + #1 CLOCK = 1; + #1 CLOCK = 0; + #1 CLOCK = 1; + #1 CLOCK = 0; + + if (count !== 4'b0010) begin + $display("FAILED -- count up is %b", count); + $finish; + end + + SETn = 0; + #1 ; + + if (count !== 4'b1101) begin + $display("FAILED -- Aset failed: count=%b", count); + $finish; + end + + SETn = 1; + #1 CLOCK = 1; + #1 CLOCK = 0; + + if (count !== 4'b1110) begin + $display("FAILED -- Aset didn't release: count=%b", count); + $finish; + end + + RSTn = 0; + #1 ; + if (count !== 4'b0000) begin + $display("FAILED -- Aclr failed: count=%b", count); + $finish; + end + + $display("PASSED"); + $finish; + end + + (* ivl_synthesis_on *) + always @(posedge CLOCK or negedge RSTn or negedge SETn) + begin + if (!RSTn) + count =0; //async clear + else + if (!SETn) + count = 4'b1101; //async set + else + count = count + 1; + end + +endmodule diff --git a/ivtest/ivltests/dffsynth10.v b/ivtest/ivltests/dffsynth10.v new file mode 100644 index 000000000..970663713 --- /dev/null +++ b/ivtest/ivltests/dffsynth10.v @@ -0,0 +1,48 @@ +module top(); + +reg CLK; +reg [3:0] D; +reg EN; +reg [3:0] Q; + +always @(posedge CLK) begin + if (EN) begin + Q[1] <= D[1]; + Q[2] <= ~D[2]; + Q[3] <= D[3]; + end +end + +reg failed; + +(* ivl_synthesis_off *) +initial begin + failed = 0; + $monitor("%b %b %b %b", CLK, EN, D, Q); + CLK = 0; + EN = 0; + D = 4'b0000; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 4'bxxxx) failed = 1; + EN = 1; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 4'b010x) failed = 1; + EN = 0; + D = 4'b1111; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 4'b010x) failed = 1; + EN = 1; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 4'b101x) failed = 1; + #1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/dffsynth11.v b/ivtest/ivltests/dffsynth11.v new file mode 100644 index 000000000..b5ff754bc --- /dev/null +++ b/ivtest/ivltests/dffsynth11.v @@ -0,0 +1,55 @@ +module top(); + +reg CLK; +reg RST; +reg [3:1] D; +reg EN; +reg [3:1] Q; + +always @(posedge CLK or posedge RST) begin + if (RST) begin + Q[1] <= 1'b0; + Q[2] <= 1'b1; + Q[3] <= 1'b0; + end + else if (EN) begin + Q[1] <= D[1]; + Q[2] <= ~D[2]; + Q[3] <= D[3]; + end +end + +reg failed; + +(* ivl_synthesis_off *) +initial begin + failed = 0; + $monitor("%b %b %b %b", CLK, EN, D, Q); + CLK = 0; + RST = 1; + EN = 0; + D = 3'b111; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 3'b010) failed = 1; + EN = 1; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 3'b010) failed = 1; + RST = 0; + EN = 0; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 3'b010) failed = 1; + EN = 1; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 3'b101) failed = 1; + #1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/dffsynth2.v b/ivtest/ivltests/dffsynth2.v new file mode 100644 index 000000000..1b1936746 --- /dev/null +++ b/ivtest/ivltests/dffsynth2.v @@ -0,0 +1,44 @@ +/* + * This program tests the synthesis of small memories, including + * aysnchronous read w/ synchronous write. + */ +module main; + + reg clk; + + reg Q, D; + (* ivl_synthesys_on *) + always @(negedge clk) + Q <= D; + + (* ivl_synthesys_off *) + initial begin + clk = 1; + D = 0; + #2 clk = 0; + #2 clk = 1; + #2 if (Q !== 0) begin + $display("FAILED -- initial setup D=%b, Q=%b", D, Q); + $finish; + end + + D = 1; + #2 clk = 0; + + #2 if (Q !== 1) begin + $display("FAILED -- negedge clk failed D=%b, Q=%b", D, Q); + $finish; + end + + D = 0; + #2 clk = 1; + #2 if (Q !== 1) begin + $display("FAILED -- posedge clk tripped FF. D=%b, Q=%b", D, Q); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/dffsynth3.v b/ivtest/ivltests/dffsynth3.v new file mode 100644 index 000000000..727d58cf6 --- /dev/null +++ b/ivtest/ivltests/dffsynth3.v @@ -0,0 +1,63 @@ +module main; + + reg a, b, c; + + reg clk, rst, rnd; + + (* ivl_sinthesis_on *) + always @(posedge clk or posedge rst) + if (rst) begin + a <= 0; + b <= 0; + c <= 0; + end else if (rnd) begin + a <= 0; + b <= 0; + end else begin + {c, b, a} <= {c, b, a} + 3'b001; + end + + (* ivl_synthesis_off *) + initial begin + clk = 0; + rst = 0; + rnd = 0; + #1 rst = 1; + #1 rst = 0; + if ({c,b,a} !== 3'b000) begin + $display("FAILED - no async reset"); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + if ({c,b,a} !== 3'b001) begin + $display("FAILED - First clock failed. {%b,%b,%b}", c, b, a); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + #1 clk = 1; + #1 clk = 0; + #1 clk = 1; + #1 clk = 0; + #1 clk = 1; + #1 clk = 0; + if ({c,b,a} !== 3'b101) begin + $display("FAILED - Fifth clock failed. {%b,%b,%b}", c, b, a); + $finish; + end + + rnd = 1; + #1 clk = 1; + #1 clk = 0; + if ({c,b,a} !== 3'b100) begin + $display("FAILED - rnd failed. {%b,%b,%b}", c, b, a); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/dffsynth4.v b/ivtest/ivltests/dffsynth4.v new file mode 100644 index 000000000..55bf715d9 --- /dev/null +++ b/ivtest/ivltests/dffsynth4.v @@ -0,0 +1,52 @@ +module main; + + reg clk; + reg Q, D, ce; + + (* ivl_synthesis_on *) + always @(posedge clk) + if (ce) + begin + end + else + Q <= D; + + (* ivl_synthesis_off *) + initial begin + clk = 0; + ce = 0; + D = 0; + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1'b0) begin + $display("FAILED --- initial setup failed: Q=%b, D=%b, ce=%b", + Q, D, ce); + $finish; + end + + ce = 1; + D = 1; + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1'b0) begin + $display("FAILED --- disable didnot work: Q=%b, D=%b, ce=%b", + Q, D, ce); + $finish; + end + + ce = 0; + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1'b1) begin + $display("FAILED --- disabled disable not OK: Q=%b, D=%b, ce=%b", + Q, D, ce); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/dffsynth5.v b/ivtest/ivltests/dffsynth5.v new file mode 100644 index 000000000..ace49a990 --- /dev/null +++ b/ivtest/ivltests/dffsynth5.v @@ -0,0 +1,50 @@ + +module DFF + (output reg Q, + input wire D, + input wire CLK, + input wire RST + /* */); + + always @(posedge CLK or posedge RST) + if (RST) + Q <= 0; + else + Q <= D; + +endmodule // dut + +module main; + + wire q; + reg d, clk, rst; + DFF dut (.Q(q), .D(d), .CLK(clk), .RST(rst)); + + initial begin + clk <= 1; + d <= 1; + + #1 rst <= 1; + #1 if (q !== 1'b0) begin + $display("FAILED -- RST=%b, Q=%b", rst, q); + $finish; + end + + #1 rst <= 0; + #1 if (q !== 1'b0) begin + $display("FAILED -- RST=%b, Q=%b", rst, q); + $finish; + end + + #1 clk <= 0; + #1 clk <= 1; + #1 if (q !== d) begin + $display("FAILED -- Q=%b, D=%b", q, d); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/dffsynth6.v b/ivtest/ivltests/dffsynth6.v new file mode 100644 index 000000000..dfcd88d83 --- /dev/null +++ b/ivtest/ivltests/dffsynth6.v @@ -0,0 +1,59 @@ + +module DFF + (output reg Q0, + output reg [1:0] Q1, + input wire D0, + input wire [1:0] D1, + input wire CLK, + input wire RST + /* */); + + always @(posedge CLK or posedge RST) + if (RST) begin + Q0 <= 0; + Q1 <= 0; + end else begin + Q0 <= D0; + Q1 <= D1; + end + +endmodule // dut + +module main; + + wire q0; + wire [1:0] q1; + reg d0, clk, rst; + reg [1:0] d1; + + DFF dut (.Q0(q0), .Q1(q1), .D0(d0), .D1(d1), .CLK(clk), .RST(rst)); + + initial begin + clk <= 1; + d0 <= 0; + d1 <= 2; + + #1 rst <= 1; + #1 if (q0 !== 1'b0 || q1 !== 1'b0) begin + $display("FAILED -- RST=%b, Q0=%b, Q1=%b", rst, q0, q1); + $finish; + end + + #1 rst <= 0; + #1 if (q0 !== 1'b0 || q1 !== 1'b0) begin + $display("FAILED -- RST=%b, Q0=%b, Q1=%b", rst, q0, q1); + $finish; + end + + #1 clk <= 0; + #1 clk <= 1; + #1 if (q0 !== d0 || q1 !== d1) begin + $display("FAILED -- Q0=%b Q1=%b, D0=%b D1=%b", q0, q1, d0, d1); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/dffsynth7.v b/ivtest/ivltests/dffsynth7.v new file mode 100644 index 000000000..6425fb927 --- /dev/null +++ b/ivtest/ivltests/dffsynth7.v @@ -0,0 +1,60 @@ +module dff(); + +reg clk; +reg rst; +reg ce; +reg [3:0] d; +reg [3:0] q; + +always @(negedge clk or posedge rst) begin + if (rst) + q <= 4'b1001; + else if (ce) + q <= d; +end + +(* ivl_synthesis_off *) +reg failed = 0; + +initial begin + $monitor("%b %b %b %b", rst, clk, d, q); + clk = 1'b0; + ce = 1'b0; + rst = 1'b0; + d = 4'b0110; + #1; + if (q !== 4'bxxxx) failed = 1; + rst = 1'b1; + #1; + if (q !== 4'b1001) failed = 1; + clk = 1'b1; + #1; + if (q !== 4'b1001) failed = 1; + clk = 1'b0; + #1; + if (q !== 4'b1001) failed = 1; + rst = 1'b0; + #1; + if (q !== 4'b1001) failed = 1; + clk = 1'b1; + #1; + if (q !== 4'b1001) failed = 1; + clk = 1'b0; + #1; + if (q !== 4'b1001) failed = 1; + ce = 1'b1; + #1; + if (q !== 4'b1001) failed = 1; + clk = 1'b1; + #1; + if (q !== 4'b1001) failed = 1; + clk = 1'b0; + #1; + if (q !== 4'b0110) failed = 1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule // dff diff --git a/ivtest/ivltests/dffsynth8.v b/ivtest/ivltests/dffsynth8.v new file mode 100644 index 000000000..a2e01e644 --- /dev/null +++ b/ivtest/ivltests/dffsynth8.v @@ -0,0 +1,62 @@ +module dff(); + +reg clk; +reg rst; +reg ce; +reg [3:0] s; +reg [3:0] d; +reg [3:0] q; + +always @(negedge clk or posedge rst) begin + if (rst) + q <= s; + else if (ce) + q <= d; +end + +(* ivl_synthesis_off *) +reg failed = 0; + +initial begin + $monitor("%b %b %b %b", rst, clk, d, q); + clk = 1'b0; + ce = 1'b0; + rst = 1'b0; + s = 4'b1001; + d = 4'b0110; + #1; + if (q !== 4'bxxxx) failed = 1; + rst = 1'b1; + #1; + if (q !== 4'b1001) failed = 1; + clk = 1'b1; + #1; + if (q !== 4'b1001) failed = 1; + clk = 1'b0; + #1; + if (q !== 4'b1001) failed = 1; + rst = 1'b0; + #1; + if (q !== 4'b1001) failed = 1; + clk = 1'b1; + #1; + if (q !== 4'b1001) failed = 1; + clk = 1'b0; + #1; + if (q !== 4'b1001) failed = 1; + ce = 1'b1; + #1; + if (q !== 4'b1001) failed = 1; + clk = 1'b1; + #1; + if (q !== 4'b1001) failed = 1; + clk = 1'b0; + #1; + if (q !== 4'b0110) failed = 1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule // dff diff --git a/ivtest/ivltests/dffsynth9.v b/ivtest/ivltests/dffsynth9.v new file mode 100644 index 000000000..113fb51a2 --- /dev/null +++ b/ivtest/ivltests/dffsynth9.v @@ -0,0 +1,54 @@ +module top(); + +reg CLK; +reg [3:0] D; +reg EN1; +reg EN2; +reg EN3; +reg [3:0] Q; + +always @(posedge CLK) begin + if (EN1) Q[1] <= D[1]; + if (EN2) Q[2] <= D[2]; + if (EN3) Q[3] <= D[3]; +end + +reg failed; + +(* ivl_synthesis_off *) +initial begin + failed = 0; + $monitor("%b %b %b %b %b %b", CLK, EN1, EN2, EN3, D, Q); + CLK = 0; + EN1 = 0; + EN2 = 0; + EN3 = 0; + D = 4'b0000; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 4'bxxxx) failed = 1; + EN1 = 1; + D = 4'b0000; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 4'bxx0x) failed = 1; + EN1 = 0; + EN2 = 1; + D = 4'b1111; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 4'bx10x) failed = 1; + EN2 = 0; + EN3 = 1; + D = 4'b0000; + #1 CLK = 1; + #1 CLK = 0; + if (Q !== 4'b010x) failed = 1; + #1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/disable3.6A.v b/ivtest/ivltests/disable3.6A.v new file mode 100644 index 000000000..4b87e2c9e --- /dev/null +++ b/ivtest/ivltests/disable3.6A.v @@ -0,0 +1,77 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate defparam + +module main (); + +reg clock; +reg q; +reg reset; +reg error; + +always @(posedge clock or posedge reset) + begin : FF + # 2; + if(reset) + q <= 0; + else + q <= ~q; + end + +initial + begin + + // Set reset to init f/f. + error = 0; + clock = 0; + reset = 1; + + #4 ; + if(q != 1'b0) + begin + $display("FAILED - disable3.6A - Flop didn't clear on clock & reset"); + error = 1; + end + reset = 1'b0; + + clock = 1'b1; + # 3; + if(q != 1'b1) + begin + $display("FAILED - disable3.6A - Flop didn't set on clock"); + error = 1; + end + + clock = 1'b0; + # 3; + clock = 1'b1; // Now cause the toggle edge + # 1; + disable FF; // And disable the toggle event + # 2; + if(q != 1'b1) + begin + $display("FAILED - disable3.6A - Disable didn't stop FF toggle"); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/disable3.6B.v b/ivtest/ivltests/disable3.6B.v new file mode 100644 index 000000000..29a2fcf8a --- /dev/null +++ b/ivtest/ivltests/disable3.6B.v @@ -0,0 +1,83 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate defparam + +module main (); + +reg clock; +reg q; +reg reset; +reg error; + +task task_a ; + begin + # 2; + if(reset) + q = 0; + else + q = ~q ; + end +endtask + +initial + begin + + // Set reset to init f/f. + error = 0; + reset = 1; + task_a ; // Same as posedge reset in previous test + + #4 ; + if(q != 1'b0) + begin + $display("FAILED - disable3.6B - Flop didn't clear on clock & reset"); + error = 1; + end + reset = 1'b0; + + task_a ; // First clock edge from orig test + # 3; + if(q != 1'b1) + begin + $display("FAILED - disable3.6B - Flop didn't set on clock"); + error = 1; + end + + # 3; + + fork + task_a ; // Toggle f/f clock edge + + begin + # 1; + disable task_a; // And disable the toggle event + end + join + + if(q != 1'b1) + begin + $display("FAILED - disable3.6B - Disable task didn't stop toggle"); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/disable_cleanup.v b/ivtest/ivltests/disable_cleanup.v new file mode 100644 index 000000000..e45b0091c --- /dev/null +++ b/ivtest/ivltests/disable_cleanup.v @@ -0,0 +1,31 @@ +module bug(); + +reg clock = 0; + +always begin + #1 clock = 1; + #1 clock = 0; +end + +integer count = 0; + +initial begin:counter + forever begin + repeat (2) @(posedge clock); + count = count + 1; + $display(count); + end +end + +initial begin + repeat (5) @(posedge clock); + disable counter; + repeat (4) @(posedge clock); + if (count === 2) + $display("PASSED"); + else + $display("FAILED"); + $finish; +end + +endmodule diff --git a/ivtest/ivltests/disable_fork.v b/ivtest/ivltests/disable_fork.v new file mode 100644 index 000000000..26dee1c90 --- /dev/null +++ b/ivtest/ivltests/disable_fork.v @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +module main; + + initial begin + fork :fork_label + #100 disable fork_label; + #200 begin + $display("FAILED -- shouldn't get here"); + $finish; + end + join + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/disable_fork_cmd.v b/ivtest/ivltests/disable_fork_cmd.v new file mode 100644 index 000000000..65cf5da23 --- /dev/null +++ b/ivtest/ivltests/disable_fork_cmd.v @@ -0,0 +1,35 @@ +module top; + reg passed; + reg [4:1] result; + + initial begin + passed = 1'b1; + result = 4'b0000; + // Fork some processes and wait for the one with the least delay to finish. + fork + #3 result[3] = 1'b1; + #4 result[4] = 1'b1; + join_none + fork + #1 result[1] = 1'b1; + #2 result[2] = 1'b1; + join_any + // Disable the rest of the forked processes. + disable fork; + // Only the 1st bit should be set. + if (result !== 4'b0001) begin + $display("More than one process ran before the disable fork: %b", result); + passed = 1'b0; + result = 4'b0001; + end + // Wait to make sure the disabled processes do not run at a later time. + #10; + // Only the 1st bit should still be set. + if (result !== 4'b0001) begin + $display("Processes ran to completion after being disabled: %b", result); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/disblock.v b/ivtest/ivltests/disblock.v new file mode 100644 index 000000000..25884a15f --- /dev/null +++ b/ivtest/ivltests/disblock.v @@ -0,0 +1,49 @@ +// +// Copyright (c) 2002 Philip Blundell +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Disable within named block. +// + +module m(); + +initial + begin + #10; + $display("FAILED"); + $finish; + end + +task t; + begin + begin:wait_loop + #1; + while(1) begin + #1; + disable wait_loop; + end // while(1) + end // wait_loop + end +endtask + +initial begin + t; + $display("PASSED"); + $finish; +end + +endmodule diff --git a/ivtest/ivltests/disblock2.v b/ivtest/ivltests/disblock2.v new file mode 100644 index 000000000..a848a554e --- /dev/null +++ b/ivtest/ivltests/disblock2.v @@ -0,0 +1,27 @@ +module test; +reg [1:0] result; +initial begin + $display("hello world, 'b%b", 1'b1); + result = get_bytes(4'b0111); + +end + +function [1:0] get_bytes; +input [3:0] in_byte_enable; +reg my_byte; + +begin + my_byte = 3; + begin: while_block + while (in_byte_enable[my_byte] == 1) + begin + $display("Byte enable is 'h%h", my_byte); + if(my_byte == 0) + disable while_block; + my_byte = my_byte - 1; + end + end + get_bytes = 2'b11; +end +endfunction +endmodule diff --git a/ivtest/ivltests/disp_dec.v b/ivtest/ivltests/disp_dec.v new file mode 100644 index 000000000..6012c6eae --- /dev/null +++ b/ivtest/ivltests/disp_dec.v @@ -0,0 +1,36 @@ +/* + * Copyright (c) 1998 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This demonstrates proper handling of unknown values in decimal output. + */ +module main(); + +initial + begin + $display("4'bxxxx = %d", 4'bxxxx); + $display("4'bzzxx = %d", 4'bzzxx); + $display("4'bzzzz = %d", 4'bzzzz); + $display("4'b00zz = %d", 4'b00zz); + $display("4'b0000 = %d", 4'b0000); + $display("4'b0011 = %d", 4'b0011); + $finish(0); + end + +endmodule diff --git a/ivtest/ivltests/disp_dec2.v b/ivtest/ivltests/disp_dec2.v new file mode 100644 index 000000000..5a4cf44d6 --- /dev/null +++ b/ivtest/ivltests/disp_dec2.v @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main (); + + initial + begin + $display("%0d (should be -1)", -1); + end + +endmodule diff --git a/ivtest/ivltests/disp_leading_z.v b/ivtest/ivltests/disp_leading_z.v new file mode 100644 index 000000000..617ddc2bf --- /dev/null +++ b/ivtest/ivltests/disp_leading_z.v @@ -0,0 +1,34 @@ +/* + * Copyright (c) 1998 Purdea Andrei (purdeaandrei@yahoo.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This demonstrates proper handling of leading zeroes, and the %0b format. + */ +module main(); + +initial + begin + $display("|%b|", 10'b11); + $display("|%0b|", 10'b11); + $display("|%b|", 10'b0); + $display("|%0b|", 10'b0); + $finish(0); + end + +endmodule diff --git a/ivtest/ivltests/disp_parm.v b/ivtest/ivltests/disp_parm.v new file mode 100644 index 000000000..db812a433 --- /dev/null +++ b/ivtest/ivltests/disp_parm.v @@ -0,0 +1,14 @@ +/* From PR#516 */ +module top (); + + parameter GEORGE = 8'd5; + parameter HARRY = 10; + + initial begin + #1; + $display("decimal GEORGE: %0d, HARRY: %0d",GEORGE, HARRY); + $display("binary GEORGE: 'b%0b, HARRY: 'b%0b",GEORGE, HARRY); + $finish(0); + end + +endmodule diff --git a/ivtest/ivltests/disp_part.v b/ivtest/ivltests/disp_part.v new file mode 100644 index 000000000..597658dd5 --- /dev/null +++ b/ivtest/ivltests/disp_part.v @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * The output from this program should be: + * 1001 + * 0100 + * 0010 + * 1001 + * 1100 + */ + +module main; + + reg [7:0] foo; + + initial begin + foo = 8'b11001001; + $display("%b", foo[3:0]); + $display("%b", foo[4:1]); + $display("%b", foo[5:2]); + $display("%b", foo[6:3]); + $display("%b", foo[7:4]); + end + +endmodule // main diff --git a/ivtest/ivltests/display_bug.v b/ivtest/ivltests/display_bug.v new file mode 100644 index 000000000..724ecddbc --- /dev/null +++ b/ivtest/ivltests/display_bug.v @@ -0,0 +1,29 @@ +module main; + + typedef struct packed { + logic [7:0] high; + logic [7:0] low; + } word; + + word [2] array; // word[0:1] exposes the bug as well + word single; + + initial begin + array[0].high = "a"; + array[0].low = "b"; + array[1].high = "c"; + array[1].low = "d"; + + $display("%s", array[0]); // good + $display("%s %s", array[0].high, array[0].low); + + $display("%s", array[1]); // good + // the line below displays contents of array[0] instead of array[1] + $display("%s %s", array[1].high, array[1].low); + + // below everything is fine + single = array[0]; + $display("%s", single); + $display("%s %s", single.high, single.low); + end +endmodule diff --git a/ivtest/ivltests/dotinid.v b/ivtest/ivltests/dotinid.v new file mode 100644 index 000000000..5bcc07a1e --- /dev/null +++ b/ivtest/ivltests/dotinid.v @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// $Id: dotinid.v,v 1.1 2001/06/26 00:32:18 sib4 Exp $ +// $Log: dotinid.v,v $ +// Revision 1.1 2001/06/26 00:32:18 sib4 +// Two new tests for identifier parsing/elaboration +// +// +// IVL parser/elaboration test for escaped names with . + +module a; + wire \a.b ; + m \c.d (\a.b ); + initial + begin + \c.d . \y.z <= 1'b1; + #1; + if (\a.b === 1'b1) + $display("PASSED"); + else + $display("FAILED"); + end +endmodule +module m(x); + output x; + reg \y.z ; + assign x = \y.z ; +endmodule diff --git a/ivtest/ivltests/drive_strength.v b/ivtest/ivltests/drive_strength.v new file mode 100644 index 000000000..76e1be1a6 --- /dev/null +++ b/ivtest/ivltests/drive_strength.v @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2000 Guy Hutchison (ghutchis@pacbell.net) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +//`define DEBUG + +`define BUG_FIX + +module drive_strength; + + // strength values (append 1/0 to each): + // supply -> strong -> pull -> weak -> highz + +/* + * Strength Value Table + * 1--> supply | strong | pull | weak | highz + * supply x | 0 | 0 | 0 | 0 + * strong 1 | x | 0 | 0 | 0 + * pull 1 | 1 | x | 0 | 0 + * weak 1 | 1 | 1 | x | 0 + * highz 1 | 1 | 1 | 1 | z + */ + + wire su1su0, su1st0, su1pu0, su1we0, su1hz0; + wire st1su0, st1st0, st1pu0, st1we0, st1hz0; + wire pu1su0, pu1st0, pu1pu0, pu1we0, pu1hz0; + wire we1su0, we1st0, we1pu0, we1we0, we1hz0; + wire hz1su0, hz1st0, hz1pu0, hz1we0, hz1hz0; + + /* supply assignments */ + assign (supply1, supply0) su1su0 = 1'b1; + assign (supply1, supply0) su1st0 = 1'b1; + assign (supply1, supply0) su1pu0 = 1'b1; + assign (supply1, supply0) su1we0 = 1'b1; + assign (supply1, supply0) su1hz0 = 1'b1; + + /* strong assignments */ + assign (strong1, strong0) st1su0 = 1'b1; + assign (strong1, strong0) st1st0 = 1'b1; + assign (strong1, strong0) st1pu0 = 1'b1; + assign (strong1, strong0) st1we0 = 1'b1; + assign (strong1, strong0) st1hz0 = 1'b1; + + /* pull assignments */ + assign (pull1, pull0) pu1su0 = 1'b1; + assign (pull1, pull0) pu1st0 = 1'b1; + assign (pull1, pull0) pu1pu0 = 1'b1; + assign (pull1, pull0) pu1we0 = 1'b1; + assign (pull1, pull0) pu1hz0 = 1'b1; + + /* weak assignments */ + assign (weak1, weak0) we1su0 = 1'b1; + assign (weak1, weak0) we1st0 = 1'b1; + assign (weak1, weak0) we1pu0 = 1'b1; + assign (weak1, weak0) we1we0 = 1'b1; + assign (weak1, weak0) we1hz0 = 1'b1; + + /* highz assignments */ + assign (highz1, strong0) hz1su0 = 1'b1; + assign (highz1, strong0) hz1st0 = 1'b1; + assign (highz1, strong0) hz1pu0 = 1'b1; + assign (highz1, strong0) hz1we0 = 1'b1; + assign (highz1, strong0) hz1hz0 = 1'b1; + + /* supply assignments */ + assign (supply1, supply0) su1su0 = 1'b0; + assign (supply1, supply0) st1su0 = 1'b0; + assign (supply1, supply0) pu1su0 = 1'b0; + assign (supply1, supply0) we1su0 = 1'b0; + assign (supply1, supply0) hz1su0 = 1'b0; + + /* strong assignments */ + assign (strong1, strong0) su1st0 = 1'b0; + assign (strong1, strong0) st1st0 = 1'b0; + assign (strong1, strong0) pu1st0 = 1'b0; + assign (strong1, strong0) we1st0 = 1'b0; + assign (strong1, strong0) hz1st0 = 1'b0; + + /* pull assignments */ + assign (pull1, pull0) su1pu0 = 1'b0; + assign (pull1, pull0) st1pu0 = 1'b0; + assign (pull1, pull0) pu1pu0 = 1'b0; + assign (pull1, pull0) we1pu0 = 1'b0; + assign (pull1, pull0) hz1pu0 = 1'b0; + + /* weak assignments */ + assign (weak1, weak0) su1we0 = 1'b0; + assign (weak1, weak0) st1we0 = 1'b0; + assign (weak1, weak0) pu1we0 = 1'b0; + assign (weak1, weak0) we1we0 = 1'b0; + assign (weak1, weak0) hz1we0 = 1'b0; + + /* highz assignments */ + assign (strong1, highz0) su1hz0 = 1'b0; + assign (strong1, highz0) st1hz0 = 1'b0; + assign (strong1, highz0) pu1hz0 = 1'b0; + assign (strong1, highz0) we1hz0 = 1'b0; + assign (strong1, highz0) hz1hz0 = 1'b0; + + initial + begin +`ifdef DEBUG + $dumpfile ("verilog.dump"); + $dumpvars (0, drive_strength); +`endif + + /* check all values for 1/x/0 */ + #1; // Give things a chance to evaluate!!! + if ((su1su0 !== 1'bx) || + (su1st0 !== 1'b1) || + (su1pu0 !== 1'b1) || + (su1we0 !== 1'b1) || + (su1hz0 !== 1'b1) || + (st1su0 !== 1'b0) || + (st1st0 !== 1'bx) || + (st1pu0 !== 1'b1) || + (st1we0 !== 1'b1) || + (st1hz0 !== 1'b1) || + (pu1su0 !== 1'b0) || + (pu1st0 !== 1'b0) || + (pu1pu0 !== 1'bx) || + (pu1we0 !== 1'b1) || + (pu1hz0 !== 1'b1) || + (we1su0 !== 1'b0) || + (we1st0 !== 1'b0) || + (we1pu0 !== 1'b0) || + (we1we0 !== 1'bx) || + (we1hz0 !== 1'b1) || + (hz1su0 !== 1'b0) || + (hz1st0 !== 1'b0) || + (hz1pu0 !== 1'b0) || + (hz1we0 !== 1'b0) || + (hz1hz0 !== 1'bz)) + $display ("FAILED - drive_strength"); + else + $display ("PASSED"); + + #10; + $finish; + end // initial begin + +`ifdef BUG_FIX + reg bug_fix; + + initial + begin + bug_fix = 0; + #2; + bug_fix = 1; + #2; + bug_fix = 0; + end +`endif // ifdef BUG_FIX + +endmodule diff --git a/ivtest/ivltests/drive_strength1.v b/ivtest/ivltests/drive_strength1.v new file mode 100644 index 000000000..2de359aa1 --- /dev/null +++ b/ivtest/ivltests/drive_strength1.v @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program tests some tricky-to-compile strength syntax. Show that + * gates can drive a wire with various strengths and be properly resolved. + */ +module main(); + + reg pullval; + wire (weak0, weak1) value = pullval; + + reg en0, en1; + + /* This buffer will drive a strong 1 to value if en0 is 1, otherwise + it will go HiZ. */ + buf (highz0, strong1) drive0(value, en0); + + /* This inverter will drive a strong 0 to value if en1 is 1, otherwise + is will go HiZ. */ + not (strong0, highz1) drive1(value, en1); + + + initial begin + en0 = 0; + en1 = 0; + + /* Make sure when the other drivers are disabled, the pullval + can pull the value up or down. The gates should be HiZ. */ + pullval = 1; + #1 if (value !== 1'b1) begin + $display("FAILED -- value is %b", value); + $finish; + end + + pullval = 0; + #1 if (value !== 1'b0) begin + $display("FAILED -- value is %b", value); + $finish; + end + + /* When en0 is 1, drive0 puts a strong 1 onto value so the + pullval should not matter. */ + en0 = 1; + pullval = 1; + #1 if (value !== 1'b1) begin + $display("FAILED -- en0==%b en1==%b pull==%b value==%b", + en0, en1, pullval, value); + $finish; + end + + pullval = 0; + #1 if (value !== 1'b1) begin + $display("FAILED -- en0==%b en1==%b pull=0%b value==%b", + en0, en1, pullval, value); + $finish; + end + + /* When en1 is 1, drive1 puts a strong 0 onto value so the + pullval should not matter. */ + en0 = 0; + en1 = 1; + pullval = 1; + #1 if (value !== 1'b0) begin + $display("FAILED -- en0==%b en1==%b pull=0%b value==%b", + en0, en1, pullval, value); + $finish; + end + + pullval = 0; + #1 if (value !== 1'b0) begin + $display("FAILED -- en0==%b en1==%b pull=0%b value==%b", + en0, en1, pullval, value); + $finish; + end + + /* When both enables are 1, we have a double driven signal + and the value should be x. */ + en0 = 1; + en1 = 1; + pullval = 1; + #1 if (value !== 1'bx) begin + $display("FAILED -- en0==%b en1==%b pull=0%b value==%b", + en0, en1, pullval, value); + $finish; + end + + pullval = 0; + #1 if (value !== 1'bx) begin + $display("FAILED -- en0==%b en1==%b pull=0%b value==%b", + en0, en1, pullval, value); + $finish; + end + + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/drive_strength2.v b/ivtest/ivltests/drive_strength2.v new file mode 100644 index 000000000..9295edbfe --- /dev/null +++ b/ivtest/ivltests/drive_strength2.v @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2000 Yasuhisa Kato + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module drvz( clk, iA, iC, ioS ); + input clk, iA, iC ; + inout ioS ; + + assign ioS = (iC) ? iA : 'bz ; + +endmodule + +module main; + + reg clk, c ; + initial begin clk = 0 ; forever #5 clk = ~clk ; end + initial begin c = 0 ; #40 $finish(0); end + + wire a, b, s ; + + assign a = 'b0 ; + assign b = 'b1 ; + + always @(posedge clk) c <= ~c ; + + drvz M ( clk, a, c, s ) ; + drvz N ( clk, b, ~c, s ) ; // line(A) + + always @(posedge clk) + $display("%b %b %b", s, a, b ); + +endmodule + +// expected output +// 1 0 1 +// 0 0 1 +// 1 0 1 +// 0 0 1 + +// ivl 0.3 result +// x 0 1 +// 0 0 1 +// x 0 1 +// 0 0 1 diff --git a/ivtest/ivltests/drive_strength3.v b/ivtest/ivltests/drive_strength3.v new file mode 100644 index 000000000..f2b11b4bf --- /dev/null +++ b/ivtest/ivltests/drive_strength3.v @@ -0,0 +1,63 @@ +`begin_keywords "1364-2005" +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This tests the behavior of drive strength attached to a buf device. + * The assign of a reg to the bit should override the value and give a + * well defined result. + */ +module main; + + wire bit; + PULLDOWN pd(bit); + + reg drv; + assign bit = drv; + + initial begin + drv = 0; + #100 if (bit !== 1'b0) begin + $display("FAILED -- 0 bit = %b", bit); + $finish; + end + + drv = 1; + #100 if (bit !== 1'b1) begin + $display("FAILED -- 1 bit = %b", bit); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin + +endmodule // main + + +module PULLDOWN (O); + + output O; + wire A; + + pulldown (A); + buf (weak0,weak1) #(1,1) (O,A); + +endmodule +`end_keywords diff --git a/ivtest/ivltests/dummy7.v b/ivtest/ivltests/dummy7.v new file mode 100644 index 000000000..8ca119819 --- /dev/null +++ b/ivtest/ivltests/dummy7.v @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2002 Stephen Rowland + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module dummy7; + +`define ADDR1 16'h0011 +`define ADDR2 16'h0022 + +`define ADDR81 8'h11 +`define ADDR82 8'h22 + +reg [7:0] data1; +reg [7:0] data2; +reg [7:0] data3; +reg [7:0] data4; +reg [7:0] addr; +reg [15:0] addr16; + +// use mod operator to convert literal to 8 bits - this works in verilogXL +always @ (addr) +case (addr) +`ADDR1 %256 : data1 = 8'h11; +`ADDR2 %256 : data1 = 8'h22; +default : data1 = 8'h00; +endcase + +// icarus like this +always @ (addr) +case (addr) +`ADDR1 : data2 = 8'h11; +`ADDR2 : data2 = 8'h22; +default : data2 = 8'h00; +endcase + + +always @ (addr16) +case (addr16) +`ADDR1 : data3 = 8'h11; +`ADDR2 : data3 = 8'h22; +default : data3 = 8'h00; +endcase + +always @ (addr) +case (addr) +`ADDR81 : data4 = 8'h11; +`ADDR82 : data4 = 8'h22; +default : data4 = 8'h00; +endcase + + +initial +begin +addr = 8'h00; +addr16 = 16'h0000; +#10; +$display("should be 00 -- data1=%h data2=%h data3=%h data4=%h\n",data1,data2,data3,data4); + +addr = 8'h11; +addr16 = 16'h0011; +#10; +$display("should be 11 -- data1=%h data2=%h data3=%h data4=%h\n",data1,data2,data3,data4); + +addr = 8'h22; +addr16 = 16'h0022; +#10; +$display("should be 22 -- data1=%h data2=%h data3=%h data4=%h\n",data1,data2,data3,data4); + + +$finish(0); +end +endmodule diff --git a/ivtest/ivltests/dump_memword.v b/ivtest/ivltests/dump_memword.v new file mode 100644 index 000000000..5f65646e3 --- /dev/null +++ b/ivtest/ivltests/dump_memword.v @@ -0,0 +1,10 @@ +module top; + reg [7:0] arr [4:-2]; + + initial begin + $dumpfile("work/test.vcd"); + $dumpvars(1, arr[4]); + arr[4] = 8'h00; + #1 arr[4] = 8'hff; + end +endmodule diff --git a/ivtest/ivltests/dumpvars.v b/ivtest/ivltests/dumpvars.v new file mode 100644 index 000000000..f4b0535e7 --- /dev/null +++ b/ivtest/ivltests/dumpvars.v @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// $Id: dumpvars.v,v 1.2 2007/12/06 02:31:10 stevewilliams Exp $ +// $Log: dumpvars.v,v $ +// Revision 1.2 2007/12/06 02:31:10 stevewilliams +// Clean up work files (caryr) +// +// Revision 1.1 2001/07/08 02:56:25 sib4 +// Test for PR#174 +// +// +// Test if $dumpvars() accepts non-hierachical names + +module dumptest; + + submod u1(0); + submod u2(1); + + initial + begin + $dumpfile("work/dumptest.vcd"); + $dumpvars(0, dumptest.u1); + $dumpvars(0, u2); + $display("PASSED"); + $finish; + end + +endmodule + +module submod (b); + input b; + reg a; + initial a = b; +endmodule diff --git a/ivtest/ivltests/edge.v b/ivtest/ivltests/edge.v new file mode 100644 index 000000000..2e2eaa433 --- /dev/null +++ b/ivtest/ivltests/edge.v @@ -0,0 +1,108 @@ +module top; + reg passed; + reg pevt; + reg evt; + reg pedge; + reg nedge; + + initial begin + passed = 1'b1; + + #1; // Check X to 0 + {pedge, nedge} = 2'b01; + evt = 1'b0; + + #1; // Check 0 to X + pevt = evt; + {pedge, nedge} = 2'b10; + evt = 1'bx; + + #1; // Check X to 1 + pevt = evt; + {pedge, nedge} = 2'b10; + evt = 1'b1; + + #1; // Check 1 to X + pevt = evt; + {pedge, nedge} = 2'b01; + evt = 1'bx; + + #1; // Check X to Z + pevt = evt; + {pedge, nedge} = 2'b00; + evt = 1'bz; + + #1; // Check Z to X + pevt = evt; + {pedge, nedge} = 2'b00; + evt = 1'bx; + + #1; // Check X to Z (again) + pevt = evt; + {pedge, nedge} = 2'b00; + evt = 1'bz; + + #1; // Check Z to 0 + pevt = evt; + {pedge, nedge} = 2'b01; + evt = 1'b0; + + #1; // Check 0 to Z + pevt = evt; + {pedge, nedge} = 2'b10; + evt = 1'bz; + + #1; // Check Z to 1 + pevt = evt; + {pedge, nedge} = 2'b10; + evt = 1'b1; + + #1; // Check 1 to Z + pevt = evt; + {pedge, nedge} = 2'b01; + evt = 1'bz; + + #1; // Check Z to 1 (again) + pevt = evt; + {pedge, nedge} = 2'b10; + evt = 1'b1; + + #1; // Check 1 to 0 + pevt = evt; + {pedge, nedge} = 2'b01; + evt = 1'b0; + + #1; // Check 0 to 1 + pevt = evt; + {pedge, nedge} = 2'b10; + evt = 1'b1; + + #1; + + if (passed) $display("PASSED"); + end + + always @(posedge evt) begin + if (!pedge) begin + $display("Error: posedge detected for %b -> %b", pevt, evt); + passed = 1'b0; + end + end + + always @(negedge evt) begin + if (!nedge) begin + $display("Error: negedge detected for %b -> %b", pevt, evt); + passed = 1'b0; + end + end + + always @(edge evt) begin + if (!nedge && !pedge) begin + $display("Error: edge detected for %b -> %b", pevt, evt); + passed = 1'b0; + end + end + + always @(evt) + $display("Checking the %b -> %b event", pevt, evt); +endmodule diff --git a/ivtest/ivltests/eeq.v b/ivtest/ivltests/eeq.v new file mode 100644 index 000000000..47bd1ac52 --- /dev/null +++ b/ivtest/ivltests/eeq.v @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// $Id: eeq.v,v 1.1 2001/06/26 01:07:15 sib4 Exp $ +// $Log: eeq.v,v $ +// Revision 1.1 2001/06/26 01:07:15 sib4 +// new test for === and !== +// +// +// Test for === amd !== in structural context. + +module eeq; + + reg [3:0] a, b; + + wire eeq = a === b; +`ifdef DONT_TEST_NEE + wire nee = ~(a === b); +`else + wire nee = a !== b; +`endif + + reg err; + + always + begin + #2; + $display("%b %b ===%b !==%b", a, b, eeq, nee); + if (((a === b) !== eeq) || ((a !== b) !== nee)) err = 1; + end + + initial + begin + err = 0; + #1 a = 4'b zx10; b = 4'b zx10; #1; + #1 a = 4'b 1x10; b = 4'b zx10; #1; + #1 a = 4'b xz10; b = 4'b zx10; #1; + #1 a = 4'b xz01; b = 4'b zx10; #1; + #1 a = 4'b 0000; b = 4'b 0000; #1; + #1 a = 4'b 1111; b = 4'b 1111; #1; + #1 a = 4'b xxxx; b = 4'b xxxx; #1; + #1 a = 4'b zzzz; b = 4'b zzzz; #1; + #1; + if (err) + $display("FAILED"); + else + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/else1.v b/ivtest/ivltests/else1.v new file mode 100644 index 000000000..d72754726 --- /dev/null +++ b/ivtest/ivltests/else1.v @@ -0,0 +1,55 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Basic ifdef test with else, no define +// + + +module ifdef1; + +reg error ; + + +`ifdef NOCODE +initial + begin + #20; + error = 1; + #20; + end +`else +initial + begin + #20; + error = 0; + #20; + end +`endif + +initial + begin + #1; + error = 1; + #40; + if(error == 0) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule // main diff --git a/ivtest/ivltests/else2.v b/ivtest/ivltests/else2.v new file mode 100644 index 000000000..4904fa12a --- /dev/null +++ b/ivtest/ivltests/else2.v @@ -0,0 +1,57 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Compound ifdef test with else, exterior define +// + +`define DOUBLE + +module ifdef1; + +reg error ; + + +`ifdef DOUBLE +`ifdef NOCODE +initial + begin + #20; + error = 1; + #20; + end +`else +initial + begin + #20; + error = 0; + #20; + end +`endif +`endif +initial + begin + #1; + error = 1; + #40; + if(error == 0) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule // main diff --git a/ivtest/ivltests/else3.v b/ivtest/ivltests/else3.v new file mode 100644 index 000000000..a5deb23d8 --- /dev/null +++ b/ivtest/ivltests/else3.v @@ -0,0 +1,64 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Compound ifdef test with else, exterior define +// + + +module ifdef1; + +reg error ; + + +`ifdef DOUBLE +initial + begin + #20; + error = 1; + #20; + end +`else +`ifdef NOCODE +initial + begin + #20; + error = 1; + #20; + end +`else +initial + begin + #20; + error = 0; + #20; + end +`endif +`endif + +initial + begin + #1; + error = 1; + #40; + if(error == 0) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule // main diff --git a/ivtest/ivltests/elsif_test.v b/ivtest/ivltests/elsif_test.v new file mode 100644 index 000000000..05e3f87d5 --- /dev/null +++ b/ivtest/ivltests/elsif_test.v @@ -0,0 +1,94 @@ +module elsif_test(); + +`define DEFINED + +integer i; + +initial begin + i = 0; + +`ifdef DEFINED + `ifdef DEFINED + i = i + 1; + `elsif DEFINED + i = 100; + `else + i = 110; + `endif +`elsif DEFINED + `ifdef DEFINED + i = 120; + `elsif DEFINED + i = 130; + `else + i = 140; + `endif +`else + `ifdef DEFINED + i = 150; + `elsif DEFINED + i = 160; + `else + i = 170; + `endif +`endif + +`ifdef UNDEFINED + `ifdef DEFINED + i = 200; + `elsif DEFINED + i = 210; + `else + i = 220; + `endif +`elsif DEFINED + `ifdef UNDEFINED + i = 230; + `elsif DEFINED + i = i + 1; + `else + i = 240; + `endif +`else + `ifdef UNDEFINED + i = 250; + `elsif DEFINED + i = 260; + `else + i = 270; + `endif +`endif + +`ifdef UNDEFINED + `ifdef UNDEFINED + i = 300; + `elsif UNDEFINED + i = 310; + `else + i = 320; + `endif +`elsif UNDEFINED + `ifdef UNDEFINED + i = 330; + `elsif UNDEFINED + i = 340; + `else + i = 350; + `endif +`else + `ifdef UNDEFINED + i = 360; + `elsif UNDEFINED + i = 370; + `else + i = i + 1; + `endif +`endif + + if (i == 3) + $display("PASSED"); + else + $display("Test FAILED: %d", i); +end + +endmodule diff --git a/ivtest/ivltests/enum_base_range.v b/ivtest/ivltests/enum_base_range.v new file mode 100644 index 000000000..62d241f5a --- /dev/null +++ b/ivtest/ivltests/enum_base_range.v @@ -0,0 +1,52 @@ +module test; + + // Test declaring the enum as a 3-bit logic. + enum reg [2:0] { rstate[8] } reg_enum; + enum bit [2:0] { bstate[8] } bit_enum; + enum logic [2:0] { lstate[8] } log_enum; + + initial begin + if ($bits(reg_enum) != 3) begin + $display("FAILED -- $bits(reg_enum) == %0d", $bits(reg_enum)); + $finish; + end + if ($bits(bit_enum) != 3) begin + $display("FAILED -- $bits(bit_enum) == %0d", $bits(bit_enum)); + $finish; + end + if ($bits(log_enum) != 3) begin + $display("FAILED -- $bits(log_enum) == %0d", $bits(log_enum)); + $finish; + end + + if ($bits(rstate0) != 3) begin + $display("FAILED -- $bits(rstate0) == %0d", $bits(rstate0)); + $finish; + end + if ($bits(bstate0) != 3) begin + $display("FAILED -- $bits(bstate0) == %0d", $bits(bstate0)); + $finish; + end + if ($bits(lstate0) != 3) begin + $display("FAILED -- $bits(lstate0) == %0d", $bits(lstate0)); + $finish; + end + + if (rstate0 !== 3'b000 || bstate0 !== 3'b000 || lstate0 !== 3'b000) begin + $display("FAILED -- rstate0 == %b", rstate0); + $finish; + end + + if (rstate4 !== 3'b100 || bstate4 !== 3'b100 || lstate4 !== 3'b100) begin + $display("FAILED -- rstate4 == %b", rstate4); + $finish; + end + + if (rstate7 !== 3'b111 || bstate7 !== 3'b111 || lstate7 !== 3'b111) begin + $display("FAILED -- rstate7 == %b", rstate7); + $finish; + end + + $display ("PASSED"); + end +endmodule // test diff --git a/ivtest/ivltests/enum_dims_invalid.v b/ivtest/ivltests/enum_dims_invalid.v new file mode 100644 index 000000000..e9a67e403 --- /dev/null +++ b/ivtest/ivltests/enum_dims_invalid.v @@ -0,0 +1,50 @@ +// Check that all sorts of enum dimension declarations are handled correctly and +// do not cause an assert or segfault. + +module test; + +// These are invalid + +enum logic [$] { + A +} a; + +enum logic [] { + B +} b; + +enum logic [-1] { + C +} c; + +enum logic [0] { + D +} d; + +enum logic [1:0][3:0] { + E +} e; + +// These are valid + +enum logic [0:2] { + F +} f; + +enum logic [2:0] { + G +} g; + +enum logic [-1:-2] { + H +} h; + +// These are valid as an extension in iverilog + +enum logic [16] { + I +} i; + +int x; + +endmodule diff --git a/ivtest/ivltests/enum_elem_ranges.v b/ivtest/ivltests/enum_elem_ranges.v new file mode 100644 index 000000000..3abb7f569 --- /dev/null +++ b/ivtest/ivltests/enum_elem_ranges.v @@ -0,0 +1,96 @@ +module test; + parameter SIZE = 3; + + parameter PVALUE = 12; + localparam LVALUE = 88; + + enum byte unsigned { UVAL[256] } unsignedbyte_enum; + enum byte { SVAL[100] } signedbyte_enum; + enum { ADD = 10, SUB[5], JMP[6:8]} E1; // page 28 LRM + enum { REGISTER[2] = 1, REGISTER[2:4] = 10 } vr; // page 28 LRM + enum { P[5] = 12 /*PVALUE*/, Q, S[3] = 88/*LVALUE*/} par_enum; + + initial begin + // 1. Default anonymous enum data type should be int + // don't know yet how to quickly check this + // + // 1. Checking initialisations + // + // a. If the first name is not assigned it should be zero + if (UVAL0 !== 8'h0 || SVAL0 !== 8'h0) + begin + $display ("FAILED - First un-assigned element of enum type was not zero"); + $finish; + end + // b. Checking initials E1 and vr + if (ADD != 10 || REGISTER0 != 1) + begin + $display ("FAILED - First initialised elements of enums E1 and vr were not elaborated properly"); + $finish; + end + // A name without a value is automatically assigned and increment of the value of the + // previous name (Section 4.10 LRM) + // c. checking initial values for SUB (0-4) in E1 + if (SUB0 != 11 || SUB1 != 12 || SUB2 != 13 || SUB3 != 14 || SUB4 != 15) + begin + $display ("FAILED - Initialised elements SUB (0-4) in enum E1 were not elaborated properly"); + $finish; + end + // c. checking initial values for JMP (6-8) in E1 + if (JMP6 != 16 || JMP7 != 17 || JMP8 != 18) + begin + $display ("FAILED - Initialised elements (6-8) JMP in enum E1 were not elaborated properly"); + $finish; + end + // c. checking initial values in vr + if (REGISTER1 != 2 || REGISTER2 != 10 || REGISTER3 != 11 || REGISTER4 != 12) + begin + $display ("FAILED - Initialised elements REGISTER (1-4) in enum vr were not elaborated properly"); + $finish; + end + // c. checking hand-picked values in unsignedbyte_enum + if (UVAL23 != 23 || UVAL91 != 91 || UVAL138 != 138 || UVAL207 != 207) + begin + $display ("FAILED - Initialised some UVAL in enum unsignedbyte_enum were not elaborated properly"); + $display ("UVAL23 = %0d, UVAL91 = %0d, UVAL138 = %0d, UVAL207 = %0d", UVAL23, UVAL91, UVAL138, UVAL207); + $finish; + end + // c. checking hand-picked values in signedbyte_enum + if (SVAL7 != 7 || SVAL19 != 19 || SVAL87 != 87) + begin + $display ("FAILED - Initialised some SVAL in enum signedbyte_enum were not elaborated properly"); + $display ("SVAL7 = %0d, SVAL19 = %0d, SVAL87 = %0d", SVAL7, UVAL91, SVAL19, SVAL87); + $finish; + end + // c. checking final values in unsignedbyte_enum and signedbyte_enum + if (UVAL255 != 255 || SVAL99 != 99) + begin + $display ("FAILED - Initialised final values UVAL and SVAL did not elaborate properly"); + $display ("UVAL255 = %0d, SVAL99 = %0d", UVAL255, SVAL99); + $finish; + end + // constants elaborated from parameter + if (P0 != PVALUE+0 || P1 != PVALUE+1 || P2 != PVALUE+2 || P3 != PVALUE+3 || P4 != PVALUE + 4 || Q != PVALUE+5) + begin + $display ("FAILED - Initialised values P in par_enum were not elaborated properly"); + $finish; + end + // constants elaborated from localparam + if (S0 != LVALUE+0 || S1 != LVALUE+1 || S2 != LVALUE+2) + begin + $display ("FAILED - Initialised values S in par_enum were not elaborated properly"); + $finish; + end + #1; + // checking num method + if (unsignedbyte_enum.num != 256 || signedbyte_enum.num != 100 || + E1.num != 9 || vr.num != 5 || par_enum.num != 9) + begin + $display ("FAILED - The num method does not report as expected"); + $finish; + end + $display ("PASSED"); + end + + +endmodule diff --git a/ivtest/ivltests/enum_next.v b/ivtest/ivltests/enum_next.v new file mode 100644 index 000000000..b148fe9bc --- /dev/null +++ b/ivtest/ivltests/enum_next.v @@ -0,0 +1,44 @@ +/* + * This program tests that enumeration value first/last/next + * methods work properly. The .next method requires some run-time + * support for enumeration. + */ +module main; + + enum { RED, GREEN = 2, BLUE } color1; + + initial begin + color1 = RED; + $display("color1.first == %0d", color1.first); + $display("color1.last == %0d", color1.last); + $display("color1.num == %0d", color1.num); + $display("color1.next == %0d", color1.next); + + color1 = color1.next; + if (color1 != GREEN || color1 !== 2) begin + $display("FAILED -- should be %0d, got %0d", GREEN, color1); + $finish; + end + + color1 = color1.next; + if (color1 != BLUE || color1 !== 3 || color1 != color1.last) begin + $display("FAILED -- should be %0d, got %0d", BLUE, color1); + $finish; + end + + color1 = color1.prev; + if (color1 != GREEN || color1 !== 2) begin + $display("FAILED -- should be %0d, got %0d", GREEN, color1); + $finish; + end + + color1 = color1.prev; + if (color1 != RED || color1 !== 0 || color1 != color1.first) begin + $display("FAILED -- should be %0d, got %0d", RED, color1); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/enum_ports.v b/ivtest/ivltests/enum_ports.v new file mode 100644 index 000000000..c234e383e --- /dev/null +++ b/ivtest/ivltests/enum_ports.v @@ -0,0 +1,70 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Tests enum as a port type. + +typedef enum integer { var_presence, var_identif, var_1, var_2, var_3, var_rst, var_4, var_5, var_whatever } t_var; + +module enum_ports(input wire t_var var_i, output t_var var_o, output reg is_var_rst); + +initial begin + var_o = var_presence; +end + +always @(var_i) +begin + if(var_i == var_rst) + is_var_rst = 1'b1; + else + is_var_rst = 1'b0; +end +endmodule + +module test_unit(); +t_var var_in, var_out; +reg result; + +enum_ports dut(var_in, var_out, result); + +initial begin + #1; + + if(var_out !== var_presence) begin + $display("FAILED 1"); + $finish(); + end + + var_in = var_1; + #1; + if(result !== 1'b0) begin + $display("FAILED 2"); + $finish(); + end + + var_in = var_rst; + #1 + if(result !== 1'b1) begin + $display("FAILED 3"); + $finish(); + end + + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/enum_test1.v b/ivtest/ivltests/enum_test1.v new file mode 100644 index 000000000..503f03d87 --- /dev/null +++ b/ivtest/ivltests/enum_test1.v @@ -0,0 +1,205 @@ +module test; + + parameter PVALUE = 12; + localparam LVALUE = 88; + + enum byte unsigned { UVAL[256] } unsignedbyte_enum; + enum byte { SVAL[100] } signedbyte_enum; + enum { ADD = 10, SUB[5], JMP[6:8]} E1; // page 28 LRM + enum { REGISTER[2] = 1, REGISTER[2:4] = 10 } vr; // page 28 LRM + enum { P[5] = PVALUE, Q, S[3] = LVALUE} par_enum; + enum reg [2:0] { state[8] } bin_enum; + enum integer {IDLE, XX='bx, XY='b01, YY='b10, XZ = 32'h1x2z3xxz} next_state; + + int i; + + initial begin + // 1. Default anonymous enum data type should be int + // don't know yet how to quickly check this + // + // 1. Checking initialisations + // + // a. If the first name is not assigned it should be zero + if (UVAL0 !== 8'h0 || SVAL0 !== 8'h0) + begin + $display ("FAILED - First un-assigned element of enum type was not zero"); + $finish; + end + // b. Checking initials E1 and vr + if (ADD != 10 || REGISTER0 != 1) + begin + $display ("FAILED - First initialised elements of enums E1 and vr were not elaborated properly"); + $finish; + end + // A name without a value is automatically assigned and increment of the value of the + // previous name (Section 4.10 LRM) + // c. checking initial values for SUB (0-4) in E1 + if (SUB0 != 11 || SUB1 != 12 || SUB2 != 13 || SUB3 != 14 || SUB4 != 15) + begin + $display ("FAILED - Initialised elements SUB (0-4) in enum E1 were not elaborated properly"); + $finish; + end + // c. checking initial values for JMP (6-8) in E1 + if (JMP6 != 16 || JMP7 != 17 || JMP8 != 18) + begin + $display ("FAILED - Initialised elements (6-8) JMP in enum E1 were not elaborated properly"); + $finish; + end + // c. checking initial values in vr + if (REGISTER1 != 2 || REGISTER2 != 10 || REGISTER3 != 11 || REGISTER4 != 12) + begin + $display ("FAILED - Initialised elements REGISTER (1-4) in enum vr were not elaborated properly"); + $finish; + end + // c. checking hand-picked values in unsignedbyte_enum + if (UVAL23 != 23 || UVAL91 != 91 || UVAL138 != 138 || UVAL207 != 207) + begin + $display ("FAILED - Initialised some UVAL in enum unsignedbyte_enum were not elaborated properly"); + $display ("UVAL23 = %0d, UVAL91 = %0d, UVAL138 = %0d, UVAL207 = %0d", UVAL23, UVAL91, UVAL138, UVAL207); + $finish; + end + // c. checking hand-picked values in signedbyte_enum + if (SVAL7 != 7 || SVAL19 != 19 || SVAL87 != 87) + begin + $display ("FAILED - Initialised some SVAL in enum signedbyte_enum were not elaborated properly"); + $display ("SVAL7 = %0d, SVAL19 = %0d, SVAL87 = %0d", SVAL7, UVAL91, SVAL19, SVAL87); + $finish; + end + // c. checking final values in unsignedbyte_enum and signedbyte_enum + if (UVAL255 != 255 || SVAL99 != 99) + begin + $display ("FAILED - Initialised final values UVAL and SVAL did not elaborate properly"); + $display ("UVAL255 = %0d, SVAL99 = %0d", UVAL255, SVAL99); + $finish; + end + // d. checking xz values in next_state + if (XX !== 'bx || XZ !== 32'h1x2z3xxz) + begin + $display ("FAILED - Initialised x,z values in next_state did not elaborate properly"); + $finish; + end + // e. constants elaborated from parameter + if (P0 != PVALUE+0 || P1 != PVALUE+1 || P2 != PVALUE+2 || P3 != PVALUE+3 || P4 != PVALUE + 4 || Q != PVALUE+5) + begin + $display ("FAILED - Initialised values P in par_enum were not elaborated properly"); + $finish; + end + // f. constants elaborated from localparam + if (S0 != LVALUE+0 || S1 != LVALUE+1 || S2 != LVALUE+2) + begin + $display ("FAILED - Initialised values S in par_enum were not elaborated properly"); + $finish; + end + #1; + // g. checking num method + if (unsignedbyte_enum.num != 256 || signedbyte_enum.num != 100 || + E1.num != 9 || vr.num != 5 || par_enum.num != 9 ) + begin + $display ("FAILED - The num method does not report as expected"); + $finish; + end + // h. checking first method + if (unsignedbyte_enum.first != 0 || signedbyte_enum.first != 0 || + E1.first != 10 || vr.first != 1 || par_enum.first != PVALUE ) + begin + $display ("FAILED - The first method does not report as expected"); + $finish; + end + // i. checking last method + if (unsignedbyte_enum.last != 255 || signedbyte_enum.last != 99 || + E1.last != 18 || vr.last != 12 || par_enum.last != LVALUE+2 ) + begin + $display ("FAILED - The last method does not report as expected"); + $finish; + end + // checking the next method on unsignedbyte_enum + unsignedbyte_enum = unsignedbyte_enum.first; + for (i=1; i<=255; i=i+1) begin + unsignedbyte_enum = unsignedbyte_enum.next; + if (unsignedbyte_enum != i) begin + $display ("FAILED - The next method does not report as expected for unsignedbyte_enum"); + $finish; + end + end + unsignedbyte_enum = unsignedbyte_enum.next; + // checking wrap to the first element for signedbyte_enum + if (unsignedbyte_enum != unsignedbyte_enum.first) begin + $display ("FAILED - The next method did not wrap to the first element for unsignedbyte_enum"); + $finish; + end + // checking the next method on signedbyte_enum + signedbyte_enum = signedbyte_enum.first; + for (i=1; i<100; i=i+1) begin + signedbyte_enum = signedbyte_enum.next; + if (signedbyte_enum != i) begin + $display ("FAILED - The next method does not report as expected for signedbyte_enum"); + $finish; + end + end + signedbyte_enum = signedbyte_enum.next; + // checking wrap to the first element for signedbyte_enum + if (signedbyte_enum != signedbyte_enum.first) begin + $display ("FAILED - The next method did not wrap to the first element for signedbyte_enum"); + $finish; + end + // checking the next method on E1 + E1 = E1.first; + for (i=E1.first; i<= E1.last; i=i+1) begin + if (E1 != i) begin + $display ("FAILED - The next method does not report as expected for E1"); + $finish; + end + E1 = E1.next; + end + // checking wrap to the first element in E1 + if (E1 != E1.first) begin + $display ("FAILED - The next method did not wrap to the first element for E1"); + $finish; + end + // checking the next method on vr, manual walk + vr = vr.first; + vr = vr.next; + if (vr != 2) begin + $display ("FAILED - The next method does not report as expected for vr in element REGISTER1"); + $finish; + end + vr = vr.next; + if (vr != 10) begin + $display ("FAILED - The next method does not report as expected for vr in element REGISTER2"); + $finish; + end + vr = vr.next; + if (vr != 11) begin + $display ("FAILED - The next method does not report as expected for vr in element REGISTER3"); + $finish; + end + vr = vr.next; + if (vr != 12) begin + $display ("FAILED - The next method does not report as expected for vr in element REGISTER4"); + $finish; + end + // checking wrap to the first element in vr + vr = vr.next; + if (vr != vr.first) begin + $display ("FAILED - The next method did not wrap to the first element for vr"); + $finish; + end + // checking the next method for bin_enum + bin_enum = bin_enum.first; + for (i=bin_enum.first; i<= bin_enum.last; i = i+1) begin + if (bin_enum != i) begin + $display ("FAILED - The next method does not report as expected for bin_enum"); + $finish; + end + bin_enum = bin_enum.next; + end + // checking wrap to the first element in bin_enum + if (bin_enum != bin_enum.first) begin + $display ("FAILED - The next method did not wrap to the first element for bin_enum"); + $finish; + end + $display ("PASSED"); + end + + +endmodule diff --git a/ivtest/ivltests/enum_test2.v b/ivtest/ivltests/enum_test2.v new file mode 100644 index 000000000..913c97704 --- /dev/null +++ b/ivtest/ivltests/enum_test2.v @@ -0,0 +1,8 @@ +module top; + // This will compile. + enum integer {IDLE, UNKNOWN='bx} en1; + // This is failing to compile. + enum integer {VAL, XX=32'bx} en2; + + initial $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/enum_test3.v b/ivtest/ivltests/enum_test3.v new file mode 100644 index 000000000..6c18906b8 --- /dev/null +++ b/ivtest/ivltests/enum_test3.v @@ -0,0 +1,9 @@ +module top; + // This should be okay (the trimmed bits match the enum MSB). + enum reg[3:0] {VAL1, XX1='bxxxxx} en1; + // But these should fail because the trimmed bits do not match the enum MSB. + enum reg[3:0] {VAL2, XX2='b0xxxx} en2; + enum reg[3:0] {VAL3, XX3='b0xxxxx} en3; + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/enum_test4.v b/ivtest/ivltests/enum_test4.v new file mode 100644 index 000000000..e14b0adfc --- /dev/null +++ b/ivtest/ivltests/enum_test4.v @@ -0,0 +1,4 @@ +module top; + enum bit [3:0] {first, second, third, fourth, last = -4'sd1} my_type; + initial $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/enum_test5.v b/ivtest/ivltests/enum_test5.v new file mode 100644 index 000000000..95dddfd62 --- /dev/null +++ b/ivtest/ivltests/enum_test5.v @@ -0,0 +1,9 @@ +module top; + // This should be okay because the size matches. + enum reg[3:0] {VAL1, XX1=4'bxxxx} en1; + // But these should fail because the size is wrong. + enum reg[3:0] {VAL2, XX2=3'bxxx} en2; + enum reg[3:0] {VAL3, XX3=5'bxxxxx} en3; + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/enum_test6.v b/ivtest/ivltests/enum_test6.v new file mode 100644 index 000000000..f7133fff9 --- /dev/null +++ b/ivtest/ivltests/enum_test6.v @@ -0,0 +1,6 @@ +module top; + // This should fail because XX4 is not given a constant. + enum {VAL4, XX4 = $time} en4; + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/enum_test7.v b/ivtest/ivltests/enum_test7.v new file mode 100644 index 000000000..5fe5c2eb4 --- /dev/null +++ b/ivtest/ivltests/enum_test7.v @@ -0,0 +1,6 @@ +module top; + // This should fail because XX5 is given an undefined constant (2-state). + enum {VAL5, XX5 = 'bx} en5; + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/enum_test8.v b/ivtest/ivltests/enum_test8.v new file mode 100644 index 000000000..a24a75973 --- /dev/null +++ b/ivtest/ivltests/enum_test8.v @@ -0,0 +1,10 @@ +module top; + localparam enum_start = 2'd1; + + // This is an expression so the value just has to fit. + enum logic [3:0] { first = enum_start + 2'd0, + second = enum_start + 2'd1} my_enum; + + initial $display("PASSED"); + +endmodule diff --git a/ivtest/ivltests/enum_value_expr.v b/ivtest/ivltests/enum_value_expr.v new file mode 100644 index 000000000..03bbeb6e5 --- /dev/null +++ b/ivtest/ivltests/enum_value_expr.v @@ -0,0 +1,29 @@ +module test; + parameter PVALUE = 12; + localparam LVALUE = 88; + enum { P[5] = PVALUE, Q, S[3] = LVALUE } par_enum; + + initial begin + // constants elaborated from parameter + if (P0 != PVALUE+0 || P1 != PVALUE+1 || P2 != PVALUE+2 || P3 != PVALUE+3 || P4 != PVALUE + 4 || Q != PVALUE+5) + begin + $display ("FAILED - Initialised values P in par_enum were not elaborated properly"); + $finish; + end + // constants elaborated from localparam + if (S0 != LVALUE+0 || S1 != LVALUE+1 || S2 != LVALUE+2) + begin + $display ("FAILED - Initialised values S in par_enum were not elaborated properly"); + $finish; + end + #1; + // checking num method + if ( par_enum.num != 9) + begin + $display ("FAILED - The num method does not report as expected"); + $finish; + end + $display ("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/enum_values.v b/ivtest/ivltests/enum_values.v new file mode 100644 index 000000000..504d5e10c --- /dev/null +++ b/ivtest/ivltests/enum_values.v @@ -0,0 +1,41 @@ +/* + * This program tests that enumeration values work and are + * implicitly translated to integer values. + */ +module main; + + enum { RED, ORANGE, YELLOW, GREEN, BLUE, VIOLET, + BLACK = 10, WHITE = 'd11 + } color1; + + int var1; + + initial begin + color1 = RED; + var1 = RED; + $display("color1 = %0d, var1 = %0d", color1, var1); + if (color1 !== 0) begin + $display("FAILED"); + $finish; + end + if (var1 !== 0) begin + $display("FAILED"); + $finish; + end + + color1 = GREEN; + var1 = GREEN; + $display("color1 = %0d, var1 = %0d", color1, var1); + if (color1 !== 3) begin + $display("FAILED"); + $finish; + end + if (var1 !== 3) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/enumsystem.vhd b/ivtest/ivltests/enumsystem.vhd new file mode 100644 index 000000000..def0f6c4a --- /dev/null +++ b/ivtest/ivltests/enumsystem.vhd @@ -0,0 +1,77 @@ +------------------------------------------------------------------------------ +-- Author: Oswaldo Cadenas +-- Date: September 27 2011 +-- +-- Summary: This system runs an internal counter 0,1,2, ..., 7, 0, 1, +-- and also accepts an enable signal +-- it generates an output y (4 bits) as: +-- if (e = 0) y = 0000 +-- if (e = 1) then +-- y = 1000 when counter is 0 +-- y = 0100 when counter is 1 +-- y = 0010 when counter is 2 +-- y = 0001 when counter is 3 +-- y = 1111 other count +-- internaly the design uses some enumartion arguments for decoding and encoding +--------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity enumsystem is + port (clk, reset: in std_logic; + en: in std_logic; -- enable + y: out std_logic_vector (0 to 3) ); -- decoded output +end enumsystem; + +architecture enumsystem_rtl of enumsystem is + + type States is (zero, one, two, three, other); + signal mystate: States; + + signal Counter: std_logic_vector (2 downto 0); + + begin + + SmallCounter : process (clk, reset) + begin + if ( clk'event and clk = '1') then + if (reset = '1') then + Counter <= (others => '0'); + else + Counter <= Counter + 1; + end if; + end if; + end process; + + + encoding_process: process (Counter) + begin + case Counter is + when "000" => mystate <= zero; + when "001" => mystate <= one; + when "010" => mystate <= two; + when "011" => mystate <= three; + when others => mystate <= other; + end case; + end process; + + + decoding_process: process (mystate, en) + begin + if (en = '1') then + case mystate is + when zero => y <= "1000"; + when one => y <= "0100"; + when two => y <= "0010"; + when three => y <= "0001"; + when others => y <= "1111"; + end case; + else + y <= "0000"; + end if; + end process; + +end enumsystem_rtl; diff --git a/ivtest/ivltests/eofmt_percent.v b/ivtest/ivltests/eofmt_percent.v new file mode 100644 index 000000000..3115286a2 --- /dev/null +++ b/ivtest/ivltests/eofmt_percent.v @@ -0,0 +1,3 @@ +module top; + initial $display("The following should be a single percent: %"); +endmodule diff --git a/ivtest/ivltests/eq.v b/ivtest/ivltests/eq.v new file mode 100644 index 000000000..06a4df780 --- /dev/null +++ b/ivtest/ivltests/eq.v @@ -0,0 +1,33 @@ +// Trigger breakage of Icarus Verilog CVS 2004-06-18 +// $ iverilog netnet.v +// netnet.v:7: internal error: pin(3) out of bounds(3) +// netnet.v:7: : typeid=6NetNet +// ivl: netlist.cc:208: Link &NetObj::pin (unsigned int): Assertion `idx < npins_' failed. +// $ +// Larry Doolittle + +`timescale 1ns / 1ns + +module netnet(); + +reg [2:0] s; +wire s_ones; +assign s_ones = (s==7); + +initial begin + s = 3'b111; + + #1 if (s_ones !== 1) begin + $display("FAILED -- %b==7 returns %b", s, s_ones); + $finish; + end + s = 3'b011; + + #1 if (s_ones !== 0) begin + $display("FAILED -- %b==7 returns %b", s, s_ones); + $finish; + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/escape1.v b/ivtest/ivltests/escape1.v new file mode 100644 index 000000000..64bc71e03 --- /dev/null +++ b/ivtest/ivltests/escape1.v @@ -0,0 +1,71 @@ +// +// Copyright (c) 2001 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Tests defparam \$ in module name and if() + +module test (); + +parameter init = 16'h1234; +reg [15:0] rcv; + +initial + begin + #10; + rcv = init ; + $display("Init value is %h",rcv); + end + +endmodule + +module \$I178 (); + +defparam \$I178 .a.init = 16'h0040; +defparam \$I178 .b.init = 16'h0041; +defparam \$I178 .c.init = 16'h0042; + + +test a (); +test b (); +test c (); + +reg error; + +initial + begin + error = 0; + #20; + if(\$I178 .a.rcv !== 16'h0040) + begin + $display("FAILED"); + error = 1; + end + if(\$I178 .b.rcv !== 16'h0041) + begin + $display("FAILED"); + error = 1; + end + if(\$I178 .c.rcv !== 16'h0042) + begin + $display("FAILED"); + error = 1; + end + if(error === 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/escape2a.v b/ivtest/ivltests/escape2a.v new file mode 100644 index 000000000..e9484e87c --- /dev/null +++ b/ivtest/ivltests/escape2a.v @@ -0,0 +1,36 @@ +module part1 ( +\6A_A , +\6Y_A , +VCC , +GND , +\6A_B , +\6Y_B , +\6A_C , +\6Y_C , +\6A_D , +\6Y_D , +\6A_E , +// note: there is not a space character before the nl below +\6Y_E + ) ; + +input \6A_A ; +output \6Y_A ; +input VCC ; +input GND ; +input \6A_B ; +output \6Y_B ; +input \6A_C ; +output \6Y_C ; +input \6A_D ; +output \6Y_D ; +input \6A_E ; +output \6Y_E ; + +assign \6Y_A = ~\6A_A ; +assign \6Y_B = ~\6A_B ; +assign \6Y_C = ~\6A_C ; +assign \6Y_D = ~\6A_D ; +assign \6Y_E = ~\6A_E ; + +endmodule diff --git a/ivtest/ivltests/escape2b.v b/ivtest/ivltests/escape2b.v new file mode 100644 index 000000000..14538a786 --- /dev/null +++ b/ivtest/ivltests/escape2b.v @@ -0,0 +1,37 @@ +module part2 ( +\6A_A , +\6Y_A , +VCC , +GND , +\6A_B , +\6Y_B , +\6A_C , +\6Y_C , +\6A_D , +\6Y_D , +\6A_E , +// note: there is not a space character before the nl below +// no space character after nl also +\6Y_E +) ; + +input \6A_A ; +output \6Y_A ; +input VCC ; +input GND ; +input \6A_B ; +output \6Y_B ; +input \6A_C ; +output \6Y_C ; +input \6A_D ; +output \6Y_D ; +input \6A_E ; +output \6Y_E ; + +assign \6Y_A = ~\6A_A ; +assign \6Y_B = ~\6A_B ; +assign \6Y_C = ~\6A_C ; +assign \6Y_D = ~\6A_D ; +assign \6Y_E = ~\6A_E ; + +endmodule diff --git a/ivtest/ivltests/escape2c.v b/ivtest/ivltests/escape2c.v new file mode 100644 index 000000000..1e88a32e8 --- /dev/null +++ b/ivtest/ivltests/escape2c.v @@ -0,0 +1,36 @@ +module part3 ( +\6A_A , +\6Y_A , +VCC , +GND , +\6A_B , +\6Y_B , +\6A_C , +\6Y_C , +\6A_D , +\6Y_D , +\6A_E , +// note: with space before the nl below +\6Y_E +) ; + +input \6A_A ; +output \6Y_A ; +input VCC ; +input GND ; +input \6A_B ; +output \6Y_B ; +input \6A_C ; +output \6Y_C ; +input \6A_D ; +output \6Y_D ; +input \6A_E ; +output \6Y_E ; + +assign \6Y_A = ~\6A_A ; +assign \6Y_B = ~\6A_B ; +assign \6Y_C = ~\6A_C ; +assign \6Y_D = ~\6A_D ; +assign \6Y_E = ~\6A_E ; + +endmodule diff --git a/ivtest/ivltests/escape3.v b/ivtest/ivltests/escape3.v new file mode 100644 index 000000000..436209847 --- /dev/null +++ b/ivtest/ivltests/escape3.v @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This tests the rule in section 2.7.1: + * "Neither the leading backslash character nor the terminating + * white space is considered to be part of the identifier. There- + * fore, an escaped identifier \cpu3 is treated the same as a + * non escaped identifier cpu3." + * + * The cpu3 and \cpu3 notations are for the same object. + */ + +module top; + + reg \cpu3 ; + + initial begin + cpu3 = 1; + $display("cpu3 == %b", \cpu3 ); + if (top.\cpu3 !== cpu3) begin + $display("FAILED -- top.\\cpu3 !== cpu3"); + $finish; + end + + if (\top .cpu3 !== \cpu3 ) begin + $display("FAILED -- \\top .cpu3 !== cpu3"); + $finish; + end + + if (top.\cpu3 !== 1) begin + $display("FAILED -- top.\\cpu3 !== 1"); + $finish; + end + + $display("PASSED"); + end +endmodule // top diff --git a/ivtest/ivltests/escape4.v b/ivtest/ivltests/escape4.v new file mode 100644 index 000000000..060ee78c6 --- /dev/null +++ b/ivtest/ivltests/escape4.v @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2002 Michael Ruff (mruff @chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module top; + + reg \bot.r ; + + bot bot(); + + initial begin + #1; + \bot.r = 1; + #1; + $display("\\bot.r == %b", \bot.r ); + $display("bot.r == %b", bot.r ); + + if (\bot.r !== 1) begin + $display("FAILED -- \\bot.r !== 1"); + $finish; + end + + if (bot.r !== 0) begin + $display("FAILED -- bot.r !== 0"); + $finish; + end + + $display("PASSED"); + end +endmodule // top + +module bot; + + reg r; + + initial begin + r = 0; + end +endmodule diff --git a/ivtest/ivltests/escape4b.v b/ivtest/ivltests/escape4b.v new file mode 100644 index 000000000..bd1ba3d54 --- /dev/null +++ b/ivtest/ivltests/escape4b.v @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2002 Michael Ruff (mruff @chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module top; + + reg [1:0] \bot.m [1:0]; + + bot bot(); + + initial begin + #1; + \bot.m [0] = 2'b11; + #1; + $display("\\bot.m [0] == %b", \bot.m [0]); + $display("bot.m[0] == %b", bot.m[0] ); + + if (\bot.m [0] !== 2'b11) begin + $display("FAILED -- \\bot.m [0] !== 2'b11"); + $finish; + end + + if (bot.m[0] !== 2'b00) begin + $display("FAILED -- bot.m[0] !== 2'b00"); + $finish; + end + + $display("PASSED"); + end +endmodule // top + +module bot; + + reg [1:0] m[1:0]; + + initial begin + m[0] = 2'b00; + end +endmodule diff --git a/ivtest/ivltests/escaped_macro_name.v b/ivtest/ivltests/escaped_macro_name.v new file mode 100644 index 000000000..8890d063f --- /dev/null +++ b/ivtest/ivltests/escaped_macro_name.v @@ -0,0 +1,22 @@ +`define simple "simple name" +`define \escaped "escaped name" +`define \`name "backtick name" +`define \` "backtick" +`define \quote (x) `"`\`"x`\`"`" +`define \`\`" "escaped quote" + +module test(); + +initial begin + $display(`simple); + $display(`\simple ); + $display(`escaped); + $display(`\escaped ); + $display(`\`name ); + $display(`\` ); + $display(`quote(text)); + $display(`\quote (text)); + $display(`\`\`" ); +end + +endmodule diff --git a/ivtest/ivltests/event2.v b/ivtest/ivltests/event2.v new file mode 100644 index 000000000..d9a3b4132 --- /dev/null +++ b/ivtest/ivltests/event2.v @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This checks that event name scope is searched properly. + */ + +module a; + + event FOO; + + task b; + ->FOO; + endtask // b + + initial @FOO $display("PASSED"); + + initial #1 b; + +endmodule // a diff --git a/ivtest/ivltests/event3.15.v b/ivtest/ivltests/event3.15.v new file mode 100644 index 000000000..ded78d6a7 --- /dev/null +++ b/ivtest/ivltests/event3.15.v @@ -0,0 +1,80 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Event list_of_event_identifiers, -> event_identifier. +// + +module main (); + +reg [31:0] v1,v2,v3; +reg error; +event event_1, event_2; + +always @ event_1 + begin + v1 = v1 + 1; + end + +always @ event_2 + begin + v2 = 1; + end + +initial + begin + error = 0; + v1 = 0; + v2 = 0; + v3 = 0; +// $dumpfile("test.vcd"); +// $dumpvars(0,main); + + #(5); + -> event_1; + v3 = 1; + #1 ; // Need delay here or race with always schedule + if(v1 !== 1) + begin + $display("FAILED - event3.15 event1 trigger didn't occur"); + error = 1; + end + + #5 -> event_2; + #1 ; + if(v2 !== 1) + begin + $display("FAILED - event3.15 event2 trigger didn't occur"); + error = 1; + end + v3 = 2; + + #5 -> event_1; + #1 ; + if(v1 !== 2) + begin + $display("FAILED - event3.15 event1 trigger didn't occur"); + error = 1; + end + v3 = 3; + #5 ; + + if(error === 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/event3.v b/ivtest/ivltests/event3.v new file mode 100644 index 000000000..599c005dc --- /dev/null +++ b/ivtest/ivltests/event3.v @@ -0,0 +1,61 @@ +module et1; +reg [31:0] a; +reg [31:0] b; + +wire [31:0] x; +reg [31:0] y; + +event e1; + +initial begin +// $dumpvars; + $monitor ("T=", $time, ", a=", a, ", b=", b, ", x=", +x, ", y=", y); + #200 + $finish(0); +end + +initial begin + a = 10; + b = 20; + #10 + a = 30; + #10 + b = 40; + #10 + a = 50; + -> et1.m1.e2; + #10 + b = 60; + -> et1.m1.e2; + #10 + a = 70; + -> et1.m1.e2; + b = 80; + #10 + a = 90; +end + +always @e1 begin + y <= b; +end + + +m m1 (a,x); + +endmodule + +module m (a,x); +input [31:0] a; +output [31:0] x; +reg [31:0] x; + +event e2; + +always @e2 begin + #1 + x <= a; + #2 + -> et1.e1; +end +endmodule diff --git a/ivtest/ivltests/event_array.v b/ivtest/ivltests/event_array.v new file mode 100644 index 000000000..d08ae7777 --- /dev/null +++ b/ivtest/ivltests/event_array.v @@ -0,0 +1,43 @@ +module event_array_test(); + +event my_event[3:0]; + +integer event_count[3:0]; + +generate + genvar i; + + for (i = 0; i < 4; i = i + 1) begin + always @(my_event[i]) begin + $display("Got event %d", i); + event_count[i] = event_count[i] + 1; + end + end +endgenerate + +initial begin + event_count[0] = 0; + event_count[1] = 0; + event_count[2] = 0; + event_count[3] = 0; + #1 ->my_event[0]; + #1 ->my_event[1]; + #1 ->my_event[2]; + #1 ->my_event[3]; + #1 ->my_event[1]; + #1 ->my_event[2]; + #1 ->my_event[3]; + #1 ->my_event[2]; + #1 ->my_event[3]; + #1 ->my_event[3]; + #1; + if ((event_count[0] === 1) + && (event_count[1] === 2) + && (event_count[2] === 3) + && (event_count[3] === 4)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/event_list.v b/ivtest/ivltests/event_list.v new file mode 100644 index 000000000..fe3fe37b9 --- /dev/null +++ b/ivtest/ivltests/event_list.v @@ -0,0 +1,82 @@ +// +// Copyright (c) 2000 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// Check support for event lists with named events. +// + +module main (); + + reg flag1, flag2, flag12; + event event_1, event_2; + + always @ event_1 flag1 = ~flag1; + + always @ event_2 flag2 = ~flag2; + + always @(event_1 or event_2) flag12 = ~flag12; + + initial begin + flag1 = 0; + flag2 = 0; + flag12 = 0; + + #1 -> event_1; + + #1 + if (flag1 !== 1) begin + $display("FAILED -- event_1 didn't trigger flag1"); + $finish; + end + + if (flag2 !== 0) begin + $display("FAILED -- event_1 DID trigger flag2"); + $finish; + end + + if (flag12 !== 1) begin + $display("FAILED -- event_1 didn't trigger flag12"); + $finish; + end + + flag1 = 0; + flag2 = 0; + flag12 = 0; + + #1 -> event_2; + + #1 + if (flag1 !== 0) begin + $display("FAILED -- event_2 DID trigger flag1"); + $finish; + end + + if (flag2 !== 1) begin + $display("FAILED -- event_2 didn't trigger flag2"); + $finish; + end + + if (flag12 !== 1) begin + $display("FAILED -- event_1 didn't trigger flag12"); + $finish; + end + + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/event_list2.v b/ivtest/ivltests/event_list2.v new file mode 100644 index 000000000..9d0ded396 --- /dev/null +++ b/ivtest/ivltests/event_list2.v @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program combines two events with an event or. The tricky part + * for the vvp target is that there is a mix of posedge and negedge + * events. + */ + +module ndFF ( nset, reset, Q ); + + input nset; // clk negedge set Q=1 + input reset; // reset posedge set Q=0 + output Q ; // Q output + reg Q ; + + always @(negedge nset or posedge reset) + begin + if (nset ==1'b0) Q = 1'b1; + else if (reset==1'b1) Q = 1'b0; + end + +endmodule + +module main; + + reg nset, reset; + wire Q; + + ndFF dut(nset, reset, Q); + + initial begin + #0 nset = 1; + reset = 1; + #1 nset = 0; + #1 if (Q !== 1'b1) begin + $display("FAILED (a) nset=%b, reset=%b, Q=%b", nset, reset, Q); + $finish; + end + nset = 1; + #1 if (Q !== 1'b1) begin + $display("FAILED (b) nset=%b, reset=%b, Q=%b", nset, reset, Q); + $finish; + end + reset = 0; + #1 if (Q !== 1'b1) begin + $display("FAILED (c) nset=%b, reset=%b, Q=%b", nset, reset, Q); + $finish; + end + reset = 1; + #1 if (Q !== 1'b0) begin + $display("FAILED (d) nset=%b, reset=%b, Q=%b", nset, reset, Q); + $finish; + end + $display("PASSED"); + + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/event_list3.v b/ivtest/ivltests/event_list3.v new file mode 100644 index 000000000..f71d814b3 --- /dev/null +++ b/ivtest/ivltests/event_list3.v @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2001 Juergen Urban + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module sensitivity_list (); +parameter ii = 4; +reg CLK; +reg A; +reg [ii-1:0] B,C; +initial +begin + #30; + C <= {ii{1'b0}}; + #60; + $finish(0); +end + +always +begin + CLK = 1'b0; + #10; + CLK = 1'b1; + #10; + $display ($time); +end + +always @(A or C) begin + A = 1'b0; + $display ("combinatorial process ", A, " time:",$time); + A = 1'b1; + $display ("combinatorial process ", A, " time:",$time); + B = A+C; + end +endmodule diff --git a/ivtest/ivltests/extend.v b/ivtest/ivltests/extend.v new file mode 100644 index 000000000..c6b737e1a --- /dev/null +++ b/ivtest/ivltests/extend.v @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test tests simple zero-extend of small r-values into large + * l-values. + * + * Correction and extensions by EML; 2007-11-15 + */ +module main; + + reg [3:0] y; + reg signed xs; + reg x; + reg fail; + + initial begin + fail = 0; + x = 1'b0; + y = x; + if (y !== 4'b0000) begin + $display("FAILED 1 -- x=%b, y=%b", x, y); + fail = 1; + end + + x = 1'b1; + y = x; + if (y !== 4'b0001) begin + $display("FAILED 2 -- x=%b, y=%b", x, y); + fail = 1; + end + + // x is a 1-bit unsigned reg; it zero-extends when assigned to y + x = 1'bx; + y = x; + if (y !== 4'b000x) begin + $display("FAILED 3 -- x=%b, y=%b", x, y); + fail = 1; + end + + // x is a 1-bit unsigned reg; it zero-extends when assigned to y + x = 1'bz; + y = x; + if (y !== 4'b000z) begin + $display("FAILED 4 -- x=%b, y=%b", x, y); + fail = 1; + end + + // xs is a 1-bit signed reg; it top-bit-extends when assigned to y + xs = 1'bx; + y = xs; + if (y !== 4'bxxxx) begin + $display("FAILED 5 -- xs=%b, y=%b", xs, y); + fail = 1; + end + + // xs is a 1-bit signed reg; it top-bit-extends when assigned to y + xs = 1'bz; + y = xs; + if (y !== 4'bzzzz) begin + $display("FAILED 6 -- xs=%b, y=%b", xs, y); + fail = 1; + end + + // 'bx is an unsized unsigned constant; it X-extends to the size of + // the expression it is in + y = 'bx; + if (y !== 4'bxxxx) begin + $display("FAILED 7 -- y=%b", y); + fail = 1; + end + + // 'bz is an unsized unsigned constant; it Z-extends to the size of + // the expression it is in + y = 'bz; + if (y !== 4'bzzzz) begin + $display("FAILED 8 -- y=%b", y); + fail = 1; + end + + // this is the only case in which a constant pads to the left with + // X's. 4'bx is 4-bit unsigned, but it is specified with fewer than 4 + // bits + y = 4'bx; + if (y !== 4'bxxxx) begin + $display("FAILED 9 -- y=%b", y); + fail = 1; + end + + // this is the only case in which a constant pads to the left with + // Z's. 4'bz is 4-bit unsigned, but it is specified with fewer than 4 + // bits + y = 4'bz; + if (y !== 4'bzzzz) begin + $display("FAILED 10 -- y=%b", y); + fail = 1; + end + + if (!fail) $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/extra_semicolon.v b/ivtest/ivltests/extra_semicolon.v new file mode 100644 index 000000000..09d615186 --- /dev/null +++ b/ivtest/ivltests/extra_semicolon.v @@ -0,0 +1,5 @@ +module top; + initial begin + $display("PASSED"); + end; +endmodule; diff --git a/ivtest/ivltests/fatal_et_al.v b/ivtest/ivltests/fatal_et_al.v new file mode 100644 index 000000000..f868aa46c --- /dev/null +++ b/ivtest/ivltests/fatal_et_al.v @@ -0,0 +1,8 @@ +module top; + initial begin + #1 $info("This is the $info message."); + #1 $warning("This is the $warning message."); + #1 $error("This is the $error message."); + #1 $display("Check that the messages are correct."); + end +endmodule diff --git a/ivtest/ivltests/fatal_et_al2.v b/ivtest/ivltests/fatal_et_al2.v new file mode 100644 index 000000000..a46c4df0b --- /dev/null +++ b/ivtest/ivltests/fatal_et_al2.v @@ -0,0 +1,9 @@ +module top; + initial begin + #1 $info("This is the $info message."); + #1 $warning("This is the $warning message."); + #1 $error("This is the $error message."); + #1 $fatal(0, "This is the $fatal message."); + #1 $display("FAILED: This should not print."); + end +endmodule diff --git a/ivtest/ivltests/fdisplay1.v b/ivtest/ivltests/fdisplay1.v new file mode 100644 index 000000000..8003a98f6 --- /dev/null +++ b/ivtest/ivltests/fdisplay1.v @@ -0,0 +1,44 @@ +/* Copyright (C) 2000 Stephen G. Tell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ +/* fdisplay1 - test $fwrite and $fdisplay system tasks without using $fopen + * + * NB: this may need a little tweaking, as I'm not sure that all verilogs + * have the predefined $fdisplay descriptors 2 and 3 matching what + * vpi_mcd_printf provides. + */ + +module fdisplay1; + + integer fp; + reg [7:0] a; + + initial begin + + $display("message to stdout (from $display)\n"); + $fwrite(1, "another message (via fwrite) "); + $fdisplay(1,"to stdout\n (via fdisplay)"); + #5 + + a = 8'h5a; + $fwrite(1, "a = %b at %0t\n", a, $time); + + $finish(0); + + end // initial begin + +endmodule diff --git a/ivtest/ivltests/fdisplay2.v b/ivtest/ivltests/fdisplay2.v new file mode 100644 index 000000000..8211bf0b9 --- /dev/null +++ b/ivtest/ivltests/fdisplay2.v @@ -0,0 +1,43 @@ +/* Copyright (C) 2000 Stephen G. Tell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ +/* fdisplay2 - test $fopen and $fdisplay system tasks */ + +module fdisplay2; + + integer fp, dfp; + reg [7:0] a; + + initial begin + fp = $fopen("work/fdisplay2.out"); + if(fp != 2 && fp != 4 && fp != 8 && fp != 16 && fp != 32 && fp != 64) + begin + $display("FAILED fopen fp=%d", fp); + $finish; + end + + $fwrite(fp, "hello, world\n"); + a = 8'hac; + + //$fdisplay(1|fp, "a = %h; x: %b\n", a, a^8'h0f); + dfp = 1|fp; + $fdisplay(dfp, "a = 'h%h = 'b%b", a, a); + + $finish; + end // initial begin + +endmodule diff --git a/ivtest/ivltests/fdisplay3.v b/ivtest/ivltests/fdisplay3.v new file mode 100644 index 000000000..3c7b3c0fc --- /dev/null +++ b/ivtest/ivltests/fdisplay3.v @@ -0,0 +1,33 @@ +/* Copyright (C) 2000 Stephen G. Tell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ +/* fdisplay3 - check that $fdisplay rejects bogus first arguments */ + +module fdisplay3; + + initial begin + +// This error is now caught at compile time so this message will not +// be printed. +// +// $display("expect compile or runtime error from bad $fdisplay args:"); + $fdisplay(fdisplay3, "bogus message"); + $finish; + + end // initial begin + +endmodule diff --git a/ivtest/ivltests/fdisplay_fail_fd.v b/ivtest/ivltests/fdisplay_fail_fd.v new file mode 100644 index 000000000..6a6e6af5b --- /dev/null +++ b/ivtest/ivltests/fdisplay_fail_fd.v @@ -0,0 +1,6 @@ +module top; + initial begin + // This will fail at run time. + $fdisplay(32'h8000_000f, "write to invalid FD"); + end +endmodule diff --git a/ivtest/ivltests/fdisplay_fail_mcd.v b/ivtest/ivltests/fdisplay_fail_mcd.v new file mode 100644 index 000000000..5d30d40ab --- /dev/null +++ b/ivtest/ivltests/fdisplay_fail_mcd.v @@ -0,0 +1,6 @@ +module top; + initial begin + // This will fail at run time. + $fdisplay(32'h4000_0000, "write to invalid MCD"); + end +endmodule diff --git a/ivtest/ivltests/ff_dual_enable.v b/ivtest/ivltests/ff_dual_enable.v new file mode 100644 index 000000000..3e0dd0dc7 --- /dev/null +++ b/ivtest/ivltests/ff_dual_enable.v @@ -0,0 +1,71 @@ + +module test + (input wire clk, + output reg foo, bar, + input wire foo_valid, foo_in, + input wire bar_valid, bar_in + /* */); + + always @(posedge clk) + begin + if (foo_valid) foo <= foo_in; + if (bar_valid) bar <= bar_in; + end + +endmodule // test + + +module main; + reg clk; + wire foo, bar; + reg foo_valid, foo_in; + reg bar_valid, bar_in; + + test dut (.clk(clk), + .foo(foo), .bar(bar), + .foo_valid(foo_valid), .bar_valid(bar_valid), + .foo_in(foo_in), .bar_in(bar_in)); + task fail; + begin + $display("FAILED -- foo/bar=%b/%b, foo/bar_valid=%b/%b, foo/bar_in=%b/%b", + foo, bar, foo_valid, bar_valid, foo_in, bar_in); + $finish; + end + endtask // fail + + initial begin + clk = 0; + foo_valid = 1; + bar_valid = 1; + foo_in = 0; + bar_in = 0; + + #1 clk = 1; + #1 clk = 0; + + if (foo !== 0 || bar !== 0) + fail; + + bar_in = 1; + + #1 clk = 1; + #1 clk = 0; + + if (foo !== 0 || bar !== 1) + fail; + + foo_in = 1; + bar_in = 0; + foo_valid = 1; + bar_valid = 0; + + #1 clk = 1; + #1 clk = 0; + + if (foo !== 1 || bar !== 1) + fail; + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/fileio.v b/ivtest/ivltests/fileio.v new file mode 100644 index 000000000..8ef481712 --- /dev/null +++ b/ivtest/ivltests/fileio.v @@ -0,0 +1,25 @@ +`begin_keywords "1364-2005" +module top; + reg [20*8-1:0] var; + integer fp, code; + initial begin + fp = $fopenr("read"); + if (fp != 0) $display("Read of empty file failed."); + + fp = $fopenw("work/test.txt"); + $fdisplay(fp, "From the write."); + $fclose(fp); + + fp = $fopena("work/test.txt"); + $fdisplay(fp, "From the append."); + $fclose(fp); + + fp = $fopenr("work/test.txt"); + code = $fgets(var, fp); + $display("%0s", var[20*8-1:8]); + code = $fgets(var, fp); + $display("%0s", var[20*8-1:8]); + $fclose(fp); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/fileline.v b/ivtest/ivltests/fileline.v new file mode 100644 index 000000000..8b02c37df --- /dev/null +++ b/ivtest/ivltests/fileline.v @@ -0,0 +1,27 @@ +/* + * P1800/D8 22.13 + * "`__FILE__ expands to the name of the current input file, in the form of a + * string literal." + */ +module aaa; +initial begin + #1; + $display(`__FILE__); +end +endmodule + +/* + * P1800/D8 22.13 + * "`__LINE__ expands to the current input line number, in the form of + * a simple decimal number." + */ +module bbb; +initial begin + #2; + if(`__LINE__ !== 21 || + `__LINE__ !== 22) begin + $display("FAIL"); $finish; + end + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/fileline2.v b/ivtest/ivltests/fileline2.v new file mode 100644 index 000000000..acf72e729 --- /dev/null +++ b/ivtest/ivltests/fileline2.v @@ -0,0 +1,33 @@ +/* + * P1800/D8 22.13 + * "A `line directive changes `__LINE__, and may change `__FILE__ as well." + */ +module aaa; +reg pass; + +`define printfl(x) $display("%0d -> %s:%0d", x, `__FILE__, `__LINE__) +initial begin #0 + pass = 1; + +`line 1000 "./ivltests/fileline2.v" 0 + if(`__LINE__ !== 1000) begin + $display("FAIL"); pass = 0; + end + `printfl(1); + +`line 2000 "imaginary-include-file" 1 + if(`__LINE__ !== 2000) begin + $display("FAIL"); pass = 0; + end + `printfl(2); + +`line 3000 "./ivltests/fileline2.v" 2 + if(`__LINE__ !== 3000) begin + $display("FAIL"); pass = 0; + end + `printfl(3); + + + if(pass) $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/final.v b/ivtest/ivltests/final.v new file mode 100644 index 000000000..28db4a4e6 --- /dev/null +++ b/ivtest/ivltests/final.v @@ -0,0 +1,16 @@ +module t; +reg [7:0] x = 1; + +initial #5 x = 2; +always @(x) #5 x = 3; + +final begin + if (x == 3) $display("x =%d, PASSED", x); + $finish(0); + $display("FAILED! Executed past $finish in final block!"); +end +endmodule + +module t2; +final $display("t2 final"); +endmodule diff --git a/ivtest/ivltests/final2.v b/ivtest/ivltests/final2.v new file mode 100644 index 000000000..c3d810a96 --- /dev/null +++ b/ivtest/ivltests/final2.v @@ -0,0 +1,7 @@ +module t; + final $display("Final in %m"); +endmodule + +module t2; + final $display("Final in %m"); +endmodule diff --git a/ivtest/ivltests/first_last_num.v b/ivtest/ivltests/first_last_num.v new file mode 100644 index 000000000..921f72287 --- /dev/null +++ b/ivtest/ivltests/first_last_num.v @@ -0,0 +1,36 @@ +/* + * This program tests that enumeration value first/last/num + * methods work properly. + */ +module main; + + enum byte { RED, ORANGE, YELLOW, GREEN, BLUE, VIOLET, + BLACK = 10, WHITE = 'd11 + } color1; + + + initial begin + color1 = RED; + $display("color1.first == %0d", color1.first); + $display("color1.last == %0d", color1.last); + $display("color1.num == %0d", color1.num); + + if (color1.first !== RED) begin + $display("FAILED"); + $finish; + end + + if (color1.last !== WHITE) begin + $display("FAILED"); + $finish; + end + + if (color1.num !== 8) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/fopen1.v b/ivtest/ivltests/fopen1.v new file mode 100644 index 000000000..8dbf1db2f --- /dev/null +++ b/ivtest/ivltests/fopen1.v @@ -0,0 +1,75 @@ +/* Copyright (C) 2000 Stephen G. Tell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ +// SDW - reworked a bit to account for the fact that it HAS to be + +/* fopen1 - test $fopen system task */ + +module fopen1; + reg [31:0] fp; + reg error ; + + initial begin + + fp = $fopen("work/fopen1.out"); + case(fp) + 32'h0000_0001: error = 1; + 32'h0000_0002: error = 0; + 32'h0000_0004: error = 1; + 32'h0000_0008: error = 1; + 32'h0000_0010: error = 1; + 32'h0000_0020: error = 1; + 32'h0000_0040: error = 1; + 32'h0000_0080: error = 1; + 32'h0000_0100: error = 1; + 32'h0000_0200: error = 1; + 32'h0000_0400: error = 1; + 32'h0000_0800: error = 1; + 32'h0000_1000: error = 1; + 32'h0000_2000: error = 1; + 32'h0000_4000: error = 1; + 32'h0000_8000: error = 1; + 32'h0001_0000: error = 1; + 32'h0002_0000: error = 1; + 32'h0004_0000: error = 1; + 32'h0008_0000: error = 1; + 32'h0010_0000: error = 1; + 32'h0020_0000: error = 1; + 32'h0040_0000: error = 1; + 32'h0080_0000: error = 1; + 32'h0100_0000: error = 1; + 32'h0200_0000: error = 1; + 32'h0400_0000: error = 1; + 32'h0800_0000: error = 1; + 32'h1000_0000: error = 1; + 32'h2000_0000: error = 1; + 32'h4000_0000: error = 1; + 32'h8000_0000: error = 1; + default: error = 1; // std_io! + endcase + + $display("fp = %b",fp); + + if(error == 0) + $display("PASSED"); + else + $display("FAILED"); + $fclose(fp); + + $finish; + end +endmodule diff --git a/ivtest/ivltests/fopen2.v b/ivtest/ivltests/fopen2.v new file mode 100644 index 000000000..ce895424f --- /dev/null +++ b/ivtest/ivltests/fopen2.v @@ -0,0 +1,53 @@ +/* fopen2 - test $fopen and $fclose system tasks */ + +module fopen2; + integer fp1, fp2, fp3, fp4; + integer dfp; + + reg error; + reg [31:0] foo; + + initial begin + error = 0; + fp1 = $fopen("work/fopen2.out1"); + checkfp(fp1); + dfp = fp1|1; + $fdisplay(dfp, "fp1=%d", fp1); + + fp2 = $fopen("work/fopen2.out2"); + checkfp(fp2); + dfp = fp2|1; + $fdisplay(dfp, "fp2=%d", fp2); + + fp3 = $fopen("work/fopen2.out3"); + checkfp(fp3); + dfp = fp3|1; + $fdisplay(dfp, "fp3=%d", fp3); + + $fclose(fp2); + + fp4 = $fopen("work/fopen2.out4"); + checkfp(fp4); + dfp = fp4|1; + $fdisplay(dfp, "fp4=%d", fp4); + + $fclose(fp1); + $fclose(fp2); + $fclose(fp3); + $fclose(fp4); + if(error == 0) + $display("PASSED"); + + end // initial begin + + task checkfp; + input [31:0] fp; + begin + if(fp != 2 && fp != 4 && fp != 8 && fp != 16 && fp != 32 && fp != 64) begin + $display("FAILED fopen fp=%d", fp); + error = 1; + end + end + endtask // checkfp + +endmodule diff --git a/ivtest/ivltests/for3.16A.v b/ivtest/ivltests/for3.16A.v new file mode 100644 index 000000000..3ccfb0382 --- /dev/null +++ b/ivtest/ivltests/for3.16A.v @@ -0,0 +1,43 @@ +// +// Copyright (c) 2000 Steve Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// for3.16A - Template 1 - for(val1=0; val1 <= expr ; val1 = val1 + 1) some_action +// + +module test ; + +reg [3:0] val1; +reg [3:0] val2; + +initial + begin + val2 = 0; + for(val1 = 0; val1 <= 4'ha; val1 = val1+1) + begin + val2 = val2 + 1; + end + if(val2 === 4'hb) + $display("PASSED"); + else + begin + $display("FAILED val2 s/b 4'ha, but is %h",val2); + end + + end + +endmodule diff --git a/ivtest/ivltests/for_loop_synth.v b/ivtest/ivltests/for_loop_synth.v new file mode 100644 index 000000000..1999ea2a6 --- /dev/null +++ b/ivtest/ivltests/for_loop_synth.v @@ -0,0 +1,54 @@ + +module test + #(parameter inputs = 8) + (output reg [inputs-1:0] Q, + input wire [inputs-1:0] D, + input wire [inputs-1:0] I); + + // This should synthesize to an unrolled version of the + // for loop. + integer j; + always @* begin + for (j = 0 ; j < inputs ; j = j+1) begin + if (I[j]) Q[j] = ~D[j]; + else Q[j] = D[j]; + end + end + +endmodule // test + +module main; + + wire [7:0] Q; + reg [7:0] D, I; + + test dut (.Q(Q), .D(D), .I(I)); + + (* ivl_synthesis_off *) + initial begin + D = 0; + I = 0; + #1 if (Q !== 8'h00) begin + $display("FAILED -- Q=%b, D=%b, I=%b", Q, D, I); + $finish; + end + + D = 'h55; + I = 'h55; + #1 if (Q !== 8'h00) begin + $display("FAILED -- Q=%b, D=%b, I=%b", Q, D, I); + $finish; + end + + D = 'h55; + I = 'haa; + #1 if (Q !== 8'hff) begin + $display("FAILED -- Q=%b, D=%b, I=%b", Q, D, I); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/for_loop_synth2.v b/ivtest/ivltests/for_loop_synth2.v new file mode 100644 index 000000000..1ddc4efec --- /dev/null +++ b/ivtest/ivltests/for_loop_synth2.v @@ -0,0 +1,54 @@ + +module test + #(parameter inputs = 8) + (output reg [inputs-1:0] Q, + input wire [inputs-1:0] D, + input wire [inputs-1:0] I); + + // This should synthesize to an unrolled version of the + // for loop. + integer j; + always @* begin + for (j = 0 ; j < inputs ; j += 1) begin + if (I[j]) Q[j] = ~D[j]; + else Q[j] = D[j]; + end + end + +endmodule // test + +module main; + + wire [7:0] Q; + reg [7:0] D, I; + + test dut (.Q(Q), .D(D), .I(I)); + + (* ivl_synthesis_off *) + initial begin + D = 0; + I = 0; + #1 if (Q !== 8'h00) begin + $display("FAILED -- Q=%h, D=%h, I=%h", Q, D, I); + $finish; + end + + D = 'h55; + I = 'h55; + #1 if (Q !== 8'h00) begin + $display("FAILED -- Q=%h, D=%h, I=%h", Q, D, I); + $finish; + end + + D = 'h55; + I = 'haa; + #1 if (Q !== 8'hff) begin + $display("FAILED -- Q=%h, D=%h, I=%h", Q, D, I); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/force1.v b/ivtest/ivltests/force1.v new file mode 100644 index 000000000..326afe941 --- /dev/null +++ b/ivtest/ivltests/force1.v @@ -0,0 +1,60 @@ +// +// Copyright (c) 2002 Stephen Williams (steve at icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +module main; + + reg [3:0] val_drv = 4'b0101; + wire [3:0] val; + + buf val_buf[3:0] (val, val_drv); + + initial begin + #50 if (val !== val_drv) begin + $display("FAILED -- initial val %b !== %b", val, val_drv); + $finish; + end + + force val = 4'b1010; + #1 if (val !== 4'b1010) begin + $display("FAILED -- force 1010 failed, val=%b", val); + $finish; + end + + // Use force to "lift" the driver. + force val = 4'bzzzz; + + if (val !== 4'bzzzz) begin + $display("FAILED -- force z failed, val=%b", val); + $finish; + end + + release val; + #1 if (val !== 4'b0101) begin + $display("FAILED -- unforced val = %b", val); + $finish; + end + + val_drv = 4'b1010; + #1 if (val !== 4'b1010) begin + $display("FAILED -- val_drv=%b, val=%b", val_drv, val); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/force2.v b/ivtest/ivltests/force2.v new file mode 100644 index 000000000..70cab3cb7 --- /dev/null +++ b/ivtest/ivltests/force2.v @@ -0,0 +1,58 @@ +// +// Copyright (c) 2002 Stephen Williams (steve at icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +module main; + + reg [3:0] val_drv = 4'b0101; + wire [3:0] val = val_drv; + + initial begin + #50 if (val !== val_drv) begin + $display("FAILED -- initial val %b !== %b", val, val_drv); + $finish; + end + + force val = 4'b1010; + #1 if (val !== 4'b1010) begin + $display("FAILED -- force 1010 failed, val=%b", val); + $finish; + end + + // Use force to "lift" the driver. + force val = 4'bzzzz; + + if (val !== 4'bzzzz) begin + $display("FAILED -- force z failed, val=%b", val); + $finish; + end + + release val; + #1 if (val !== 4'b0101) begin + $display("FAILED -- unforced val = %b", val); + $finish; + end + + val_drv = 4'b1010; + #1 if (val !== 4'b1010) begin + $display("FAILED -- val_drv=%b, val=%b", val_drv, val); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/force3.17A.v b/ivtest/ivltests/force3.17A.v new file mode 100644 index 000000000..946d6cd9e --- /dev/null +++ b/ivtest/ivltests/force3.17A.v @@ -0,0 +1,42 @@ +// +// Copyright (c) 2000 Steve Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// force3.17A - Template 1 - force reg_lvalue = constant. +// + +module test ; + +reg [3:0] val1; +reg [3:0] val2; + +initial + begin + val2 = 0; + #50 ; + if(val2 !== 4'b1010) + $display("FAILED"); + else + $display("PASSED"); + end + +initial + begin + #20; + force val2 = 4'b1010; + end +endmodule diff --git a/ivtest/ivltests/force3.17B.v b/ivtest/ivltests/force3.17B.v new file mode 100644 index 000000000..7c8684cad --- /dev/null +++ b/ivtest/ivltests/force3.17B.v @@ -0,0 +1,43 @@ +// +// Copyright (c) 2000 Steve Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// force3.17A - Template 1 - force reg_lvalue = constant. +// + +module test ; + +reg [3:0] val1; +reg [3:0] val2; + +initial + begin + val2 = 0; + val1 = 2; + #50 ; + if(val2 !== 4'b0001) + $display("FAILED"); + else + $display("PASSED"); + end + +initial + begin + #20; + force val2 = (val1 == 2); + end +endmodule diff --git a/ivtest/ivltests/force3.17C.v b/ivtest/ivltests/force3.17C.v new file mode 100644 index 000000000..074eee7dc --- /dev/null +++ b/ivtest/ivltests/force3.17C.v @@ -0,0 +1,42 @@ +// +// Copyright (c) 2000 Steve Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// force3.17A - Template 1 - force net_lvalue = constant. +// + +module test ; + +reg [3:0] val1; +reg [3:0] val2; +wire [3:0] val3; + +initial + begin + #50 ; + if(val3 !== 4'b1010) + $display("FAILED"); + else + $display("PASSED"); + end + +initial + begin + #20; + force val3 = 4'b1010; + end +endmodule diff --git a/ivtest/ivltests/force_lval_part.v b/ivtest/ivltests/force_lval_part.v new file mode 100644 index 000000000..b9e9908a2 --- /dev/null +++ b/ivtest/ivltests/force_lval_part.v @@ -0,0 +1,24 @@ +module top; + reg pass; + reg [3:0] value; + reg [3:0] in; + + initial begin + pass = 1'b1; + value = 4'b1001; + if (value !== 4'b1001) begin + $display("Failed: initial value, expected 4'b1001, got %b", value); + pass = 1'b0; + end + + in = 4'bzx10; + // This should work since it is really the whole value. + force value[0 +: 4] = in; + if (value !== 4'bzx10) begin + $display("Failed: force value, expected 4'bzx10, got %b", value); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/force_release_reg_pv.v b/ivtest/ivltests/force_release_reg_pv.v new file mode 100644 index 000000000..67eb918bc --- /dev/null +++ b/ivtest/ivltests/force_release_reg_pv.v @@ -0,0 +1,61 @@ +module test; + reg fail = 1'b0; + reg [3:0] bus = 4'b0; + wire [3:0] val = bus; // to check the propagated value is correct + + initial begin + // Check the initial value. + #1 if (val !== 4'b0) begin + $display("FAILED: initial value, got %b, expected 0000.", val); + fail = 1; + end + + // Check a bit force and verify a normal bit assign does nothing. + #1 force bus[0] = 1'b1; + bus[0] = 1'bz; + #1 if (val !== 4'b0001) begin + $display("FAILED: force of bus[0], got %b, expected 0001.", val); + fail = 1'b1; + end + + // Check a part force + #1 force bus[3:2] = 2'b11; + #1 if (val !== 4'b1101) begin + $display("FAILED: force of bus[3:2], got %b, expected 1101.", val); + fail = 1'b1; + end + + // Check that we can change an unforced bit. + #1 bus[1] = 1'bz; + #1 if (val !== 4'b11z1) begin + $display("FAILED: assignment of bus[1], got %b, expected 11z1.", val); + fail = 1'b1; + end + #1 bus[1] = 1'b0; + + // Check a bit release. + #1 release bus[0]; + bus = 4'b000z; + #1 if (val !== 4'b110z) begin + $display("FAILED: release of bus[0], got %b, expected 110z.", val); + fail = 1'b1; + end + + // Check a part release. + #1 release bus[3:2]; + bus[3] = 1'b0; + #1 if (val !== 4'b010z) begin + $display("FAILED: release of bus[3:2], got %b, expected 010z.", val); + fail = 1'b1; + end + + // Check a force from the upper thread bits (>=8). + #1 force bus[2:1] = 2'bx1; + #1 if (val !== 4'b0x1z) begin + $display("FAILED: force of bus[2:1], got %b, expected 0x1z.", val); + fail = 1'b1; + end + + if (!fail) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/force_release_wire8_pv.v b/ivtest/ivltests/force_release_wire8_pv.v new file mode 100644 index 000000000..963bff52e --- /dev/null +++ b/ivtest/ivltests/force_release_wire8_pv.v @@ -0,0 +1,62 @@ +module test; + reg fail = 1'b0; + reg [3:0] in = 4'b0; + wire [3:0] bus; + wire [3:0] val; + assign (pull1, pull0) bus = in; + assign val = bus; + + initial begin + // Check the initial value. + #1 if (val !== 4'b0) begin + $display("FAILED: initial value, got %b, expected 0000.", val); + fail = 1'b1; + end + + // Check a bit force and verify a normal bit assign does nothing. + #1 force bus[0] = 1'b1; + #1 in[0] = 1'bz; + #1 if (val !== 4'b0001) begin + $display("FAILED: force of bus[0], got %b, expected 0001.", val); + fail = 1'b1; + end + + // Check a part force. + #1 force bus[3:2] = 2'b11; + #1 if (val !== 4'b1101) begin + $display("FAILED: force of bus[3:2], got %b, expected 1101.", val); + fail = 1'b1; + end + + // Check that we can change an unforced bit. + #1 in[1] = 1'bz; + #1 if (val !== 4'b11z1) begin + $display("FAILED: assignment of bus[1], got %b, expected 11z1.", val); + fail = 1'b1; + end + #1 in[1] = 1'b0; + + // Check a bit release. + #1 release bus[0]; + #1 if (val !== 4'b110z) begin + $display("FAILED: release of bus[0], got %b, expected 110z.", val); + fail = 1'b1; + end + + // Check a part release. + #1 release bus[3:2]; + #1 if (val !== 4'b000z) begin + $display("FAILED: release of bus[3:2], got %b, expected 000z.", val); + fail = 1'b1; + end + + // Check a force from the upper thread bits (>= 8). + #1 force bus[2:1] = 2'bx1; + #1 if (val !== 4'b0x1z) begin + $display("FAILED: force of bus[2:1], got %b, expected 0x1z.", val); + fail = 1'b1; + end + + if (!fail) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/force_release_wire_pv.v b/ivtest/ivltests/force_release_wire_pv.v new file mode 100644 index 000000000..de81cbb19 --- /dev/null +++ b/ivtest/ivltests/force_release_wire_pv.v @@ -0,0 +1,60 @@ +module test; + reg fail = 1'b0; + reg [3:0] in = 4'b0; + wire [3:0] bus = in; + wire [3:0] val = bus; // to check the propagated value is correct + + initial begin + // Check the initial value. + #1 if (val !== 4'b0) begin + $display("FAILED: initial value, got %b, expected 0000.", val); + fail = 1'b1; + end + + // Check a bit froce and verify a normal bit assign does nothing. + #1 force bus[0] = 1'b1; + #1 in[0] = 1'bz; + #1 if (val !== 4'b0001) begin + $display("FAILED: force of bus[0], got %b, expected 0001.", val); + fail = 1'b1; + end + + // Check a part force. + #1 force bus[3:2] = 2'b11; + #1 if (val !== 4'b1101) begin + $display("FAILED: force of bus[3:2], got %b, expected 1101.", val); + fail = 1'b1; + end + + // Check that we can change an unforced bit. + #1 in[1] = 1'bz; + #1 if (val !== 4'b11z1) begin + $display("FAILED: assignment of bus[1], got %b, expected 11z1.", val); + fail = 1'b1; + end + #1 in[1] = 1'b0; + + // Check a bit release. + #1 release bus[0]; + #1 if (val !== 4'b110z) begin + $display("FAILED: release of bus[0], got %b, expected 110z.", val); + fail = 1'b1; + end + + // Check a part release. + #1 release bus[3:2]; + #1 if (val !== 4'b000z) begin + $display("FAILED: release of bus[3:2], got %b, expected 000z.", val); + fail = 1'b1; + end + + // Check a force from the upper thread bits (>= 8). + #1 force bus[2:1] = 2'bx1; + #1 if (val !== 4'b0x1z) begin + $display("FAILED: force of bus[2:1], got %b, expected 0x1z.", val); + fail = 1'b1; + end + + if (!fail) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/forgen.vhd b/ivtest/ivltests/forgen.vhd new file mode 100644 index 000000000..9bcc35ee8 --- /dev/null +++ b/ivtest/ivltests/forgen.vhd @@ -0,0 +1,51 @@ +library ieee; +use ieee.std_logic_1164.all; + +-- This is a simple test of the initialization assignment for +-- signals. We also let a generic into the test. + +entity test is + + generic (width : integer := 4); + + port (clk : in std_logic; + src0, src1 : in std_logic_vector (width-1 downto 0); + dst : out std_logic_vector (width-1 downto 0)); + +end test; + +library ieee; +use ieee.std_logic_1164.all; + +entity reg_xor is + port (clk : in std_logic; + src0, src1 : in std_logic; + dst : out std_logic); +end reg_xor; + +architecture operation of test is + component reg_xor + port (clk : in std_logic; + src0, src1 : in std_logic; + dst : out std_logic); + end component; +begin + vec: for idx in width-1 downto 0 generate + slice: reg_xor port map (clk => clk, + src0 => src0(idx), + src1 => src1(idx), + dst => dst(idx)); + end generate vec; +end operation; + +architecture operation of reg_xor is + signal tmp : std_logic; +begin + tmp <= src0 xor src1; + step: process (clk) + begin -- process step + if clk'event and clk = '1' then -- rising clock edge + dst <= tmp; + end if; + end process step; +end operation; diff --git a/ivtest/ivltests/fork1.v b/ivtest/ivltests/fork1.v new file mode 100644 index 000000000..b8364f6a8 --- /dev/null +++ b/ivtest/ivltests/fork1.v @@ -0,0 +1,56 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate 3 way fork. Bug report 228. + +module test; + +reg a,b,c; +reg error; + + +initial + begin + error = 0; + fork + a = 1; + b = 0; + c = 1; + join + + if(a !== 1) + begin + $display("FAILED - a not set to 1"); + error = 1; + end + if(b !== 0) + begin + $display("FAILED - b not set to 0"); + error = 1; + end + if(c !== 1) + begin + $display("FAILED - c not set to 1"); + error = 1; + end + if(error == 0) + $display("PASSED"); + + end + +endmodule diff --git a/ivtest/ivltests/fork3.19A.v b/ivtest/ivltests/fork3.19A.v new file mode 100644 index 000000000..c1a084c41 --- /dev/null +++ b/ivtest/ivltests/fork3.19A.v @@ -0,0 +1,71 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate fork template 1 + +module main ; + +reg [3:0] value1,value2 ; +reg [3:0] ret1,ret2 ; +reg error; + +always @(value1 or value2) + begin + fork + #10 ret1 = value1; + #22 ret2 = value2; + join + end + +initial + begin + error = 0; + #1 ; + value1 = 1; + value2 = 2; + ret1 = 0; + ret2 = 0; + #12; + if(ret1 !== 1) + begin + $display("FAILED - force3.19A first statement didn't execute(1)"); + error = 1; + end + if(ret2 !== 0) + begin + $display("FAILED - force3.19A second stmt executed? is %d sb %d", + 1'b0,ret2); + error = 1; + end + #10; + if(ret1 !== 1) + begin + $display("FAILED -fork3.19A First statement problem sb 1, is %d",ret1); + error = 1; + end + if(ret2 !== 2) + begin + $display("FAILED -fork3.19A First statement problem sb 2, is %d",ret1); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/fork3.19B.v b/ivtest/ivltests/fork3.19B.v new file mode 100644 index 000000000..de66578c0 --- /dev/null +++ b/ivtest/ivltests/fork3.19B.v @@ -0,0 +1,71 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate fork template 2 + +module main ; + +reg [3:0] value1,value2 ; +reg [3:0] ret1,ret2 ; +reg error; + +always @(value1 or value2) + begin + fork + #10 ret1 = value1; + @(ret1) #12 ret2 = value2; + join + end + +initial + begin + error = 0; + #1; + value1 = 1; + value2 = 2; + ret1 = 0; + ret2 = 0; + #12; + if(ret1 !== 1) + begin + $display("FAILED - force3.19B first statement didn't execute(1)"); + error = 1; + end + if(ret2 !== 0) + begin + $display("FAILED - force3.19B second stmt executed? is %d sb %d", + 1'b0,ret2); + error = 1; + end + #10; + if(ret1 !== 1) + begin + $display("FAILED -fork3.19B First statement problem sb 1, is %d",ret1); + error = 1; + end + if(ret2 !== 2) + begin + $display("FAILED -fork3.19B First statement problem sb 2, is %d",ret1); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/fork_join_any.v b/ivtest/ivltests/fork_join_any.v new file mode 100644 index 000000000..70fcae23d --- /dev/null +++ b/ivtest/ivltests/fork_join_any.v @@ -0,0 +1,35 @@ +/* + * This is a simple test for the for...join_any syntax. There is a + * fork statement to start a bunch of threads. We wait for none of + * them and instead watch them progress with the master thread. + */ +module main; + + int flag; + initial begin + flag = 0; + fork + # 10 flag = 10; + # 20 flag = 20; + # 30 flag = 30; + join_any + + #5 if (flag != 10) begin + $display("FAILED -- flag=%d (s.b. 10)", flag); + $finish; + end + + #10 if (flag != 20) begin + $display("FAILED -- flag=%d (s.b. 20)", flag); + $finish; + end + + #10 if (flag != 30) begin + $display("FAILED -- flag=%d (s.b. 30)", flag); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/fork_join_dis.v b/ivtest/ivltests/fork_join_dis.v new file mode 100644 index 000000000..e01d5bc1e --- /dev/null +++ b/ivtest/ivltests/fork_join_dis.v @@ -0,0 +1,108 @@ +module top; + reg [1:0] a, b, c, d, e; + reg passed; + + initial begin + a = 2'b00; + b = 2'b00; + c = 2'b00; + d = 2'b00; + e = 2'b00; + passed =1'b1; + #2; + // Check that only the first process has run so far. + if (a !== 2'b01) begin + $display("First process in named fork has not run: %b", a); + passed = 1'b0; + end + if (b !== 2'b01) begin + $display("First process in named block has not run: %b", b); + passed = 1'b0; + end + if (c !== 2'b01) begin + $display("First process in parent ending has not run: %b", c); + passed = 1'b0; + end + if (d !== 2'b01) begin + $display("First process in parent alive has not run: %b", d); + passed = 1'b0; + end + if (e !== 2'b01) begin + $display("First process in parent ending (disable) has not run: %b", e); + passed = 1'b0; + end + // This external lexical disable should disable the second process even + // though the parent has already ended. + disable top.be_name; + #2; + // Check that the second process only runs for the parent ending + // and alive cases. + if (a !== 2'b01) begin + $display("Second process in named fork ran: %b", a); + passed = 1'b0; + end + if (b !== 2'b01) begin + $display("Second process in named block ran: %b", b); + passed = 1'b0; + end + if (c !== 2'b11) begin + $display("Second process in parent ending has not run: %b", c); + passed = 1'b0; + end + if (d !== 2'b11) begin + $display("Second process in parent alive has not run: %b", d); + passed = 1'b0; + end + if (e !== 2'b01) begin + $display("Second process in parent ending (disable) ran: %b", e); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end + + // Verify that disabling a named fork kills any detached processes. + initial begin + fork: fa_name + #1 a[0] = 1'b1; + #3 a[1] = 1'b1; + join_any + disable fa_name; + end + + // Verify that disabling a named block kills any detached processes. + initial begin: bb_name + fork + #1 b[0] = 1'b1; + #3 b[1] = 1'b1; + join_any + disable bb_name; + end + + // Verify that a detached process survives the parent ending. + initial begin + fork + #1 c[0] = 1'b1; + #3 c[1] = 1'b1; + join_any + end + + // Verify that a detached process runs if the parent is still alive. + initial begin + fork + #1 d[0] = 1'b1; + #3 d[1] = 1'b1; + join_any + #4; + end + + // Verify that a detached process survives the parent ending, but can + // still be disabled lexically by disabling the block that started it. + initial begin: be_name + fork + #1 e[0] = 1'b1; + #3 e[1] = 1'b1; + join_any + end + +endmodule diff --git a/ivtest/ivltests/fork_join_none.v b/ivtest/ivltests/fork_join_none.v new file mode 100644 index 000000000..4f0a6490d --- /dev/null +++ b/ivtest/ivltests/fork_join_none.v @@ -0,0 +1,40 @@ +/* + * This is a simple test for the for...join_none syntax. There is a + * fork statement to start a bunch of threads. We wait for none of + * them and instead watch them progress with the master thread. + */ +module main; + + int flag; + initial begin + flag = 0; + fork + # 10 flag = 10; + # 20 flag = 20; + # 30 flag = 30; + join_none + + #5 if (flag != 0) begin + $display("FAILED -- flag=%d (s.b. 0)", flag); + $finish; + end + + #10 if (flag != 10) begin + $display("FAILED -- flag=%d (s.b. 10)", flag); + $finish; + end + + #10 if (flag != 20) begin + $display("FAILED -- flag=%d (s.b. 20)", flag); + $finish; + end + + #10 if (flag != 30) begin + $display("FAILED -- flag=%d (s.b. 30)", flag); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/format.v b/ivtest/ivltests/format.v new file mode 100644 index 000000000..5fe4b3013 --- /dev/null +++ b/ivtest/ivltests/format.v @@ -0,0 +1,15 @@ +module test; + + wire [10:0] a = 7'd 16; + + initial + begin + #1; + $display(">%0d<", a); + $display(">%4d<", a); + $display(">%h<", a); + $display(">%4h<", a); + $display("%d, %d", a); + end + +endmodule diff --git a/ivtest/ivltests/fr47.v b/ivtest/ivltests/fr47.v new file mode 100644 index 000000000..365d008a7 --- /dev/null +++ b/ivtest/ivltests/fr47.v @@ -0,0 +1,26 @@ +// Regression test for feature request #47 +module test(); + +function [15:0] add; + +input [15:0] a; +input [15:0] b; + +begin + add = a + b; +end + +endfunction + +reg [15:0] result; + +initial begin + result = add(1, add(4, 2)); + $display("(1+(4+2)) = %d", result); + if (result === 7) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/fr49.v b/ivtest/ivltests/fr49.v new file mode 100644 index 000000000..0b76993c8 --- /dev/null +++ b/ivtest/ivltests/fr49.v @@ -0,0 +1,13 @@ +// Check that a SystemVerilog do/while loop works correctly. +module top; + int i; + + initial begin + i = 0; + do begin + i += 1; + $display("The value of i is %0d", i); + end while (i < 2); + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/fread-error.v b/ivtest/ivltests/fread-error.v new file mode 100644 index 000000000..0aa132b5a --- /dev/null +++ b/ivtest/ivltests/fread-error.v @@ -0,0 +1,14 @@ +module top; + integer res, ival; + reg [7:0] rg; + reg [7:0] mem [3:0]; + + initial begin + res = $fread(ival, 1); // 1st arg. must be a reg. or memory. + res = $fread(rg); // Too few argument. + res = $fread(mem, "a"); // Not a valid fd. + res = $fread(mem, 1, "a"); // Not a valid start. + res = $fread(mem, 1, 0, "a"); // Not a valid count. + res = $fread(mem, 1, 0, 2, 3); // Too many argument. + end +endmodule diff --git a/ivtest/ivltests/fread.txt b/ivtest/ivltests/fread.txt new file mode 100644 index 000000000..c3946fb73 --- /dev/null +++ b/ivtest/ivltests/fread.txt @@ -0,0 +1 @@ +ab01zy01234567890123456789012345678901 diff --git a/ivtest/ivltests/fread.v b/ivtest/ivltests/fread.v new file mode 100644 index 000000000..8a54bbc60 --- /dev/null +++ b/ivtest/ivltests/fread.v @@ -0,0 +1,164 @@ +`begin_keywords "1364-2005" +module top; + localparam string = "ab"; + localparam rg_res = string & 9'h1ff; + + reg passed; + integer fd, res; + reg [8:0] rg; + reg [7:0] mem [31:0]; + + initial begin + passed = 1'b1; + + fd = $fopen("ThisFileDoesNotExist.txt", "r"); + + res = $fread(rg, fd); // Try to read from an invalid fd. + if (res != 0) begin + $display("$fread (register fd) count is wrong, expected 0, got %0d", res); + passed = 1'b0; + end + if (rg !== 9'bx) begin + $display("$fread (register fd) value is wrong, expected 9'bx, got %b", + rg); + passed = 1'b0; + end + + fd = $fopen("ivltests/fread.txt", "r"); + + res = $fread(mem, fd, -1); // Try an invalid start + if (res != 0) begin + $display("$fread (mem. start) count is wrong, expected 0, got %0d", res); + passed = 1'b0; + end + if (mem[0] !== 8'bx) begin + $display("$fread (mem. start[0]) value is wrong, expected 8'bx, got %b", + mem[0]); + passed = 1'b0; + end + if (mem[15] !== 8'bx) begin + $display("$fread (mem. start[15]) value is wrong, expected 8'bx, got %b", + mem[15]); + passed = 1'b0; + end + if (mem[31] !== 8'bx) begin + $display("$fread (mem. start[31]) value is wrong, expected 8'bx, got %b", + mem[31]); + passed = 1'b0; + end + + // Check $fread with a register value. + res = $fread(rg, fd); // Load with the lower nine bits of "ab". + if (res != 2) begin + $display("$fread (register) count is wrong, expected 2, got %0d", res); + passed = 1'b0; + end + if (rg !== rg_res) begin + $display("$fread (register) value is wrong, expected %b, got %b", + rg_res, rg); + passed = 1'b0; + end + + // Check $fread with a memory. + res = $fread(mem, fd, 0, 2); // Load 0 with "0" and 1 with "1". + if (res != 2) begin + $display("$fread (mem. 1) count is wrong, expected 2, got %0d", res); + passed = 1'b0; + end + if (mem[0] !== "0") begin + $display("$fread (mem. 1[0]) value is wrong, expected %b, got %b", + "0", mem[0]); + passed = 1'b0; + end + if (mem[1] !== "1") begin + $display("$fread (mem. 1[1]) value is wrong, expected %b, got %b", + "1", mem[1]); + passed = 1'b0; + end + + res = $fread(mem, fd, 31); // Load 31 with "z". + if (res != 1) begin + $display("$fread (mem. 2) count is wrong, expected 1, got %0d", res); + passed = 1'b0; + end + if (mem[31] !== "z") begin + $display("$fread (mem. 2[31]) value is wrong, expected %b, got %b", + "z", mem[31]); + passed = 1'b0; + end + + res = $fread(mem, fd, 31, 2); // Load 31 with "y" and warns. + if (res != 1) begin + $display("$fread (mem. 3) count is wrong, expected 1, got %0d", res); + passed = 1'b0; + end + if (mem[31] !== "y") begin + $display("$fread (mem. 3[31]) value is wrong, expected %b, got %b", + "y", mem[31]); + passed = 1'b0; + end + + res = $fread(mem, fd); // Load with repeated "0" .. "9" pattern. + if (res != 32) begin + $display("$fread (mem. 4) count is wrong, expected 32, got %0d", res); + passed = 1'b0; + end + // Just check the end values and a value in the middle (15). + if (mem[0] !== "0") begin + $display("$fread (mem. 4[0]) value is wrong, expected %b, got %b", + "0", mem[0]); + passed = 1'b0; + end + if (mem[15] !== "5") begin + $display("$fread (mem. 4[15]) value is wrong, expected %b, got %b", + "5", mem[15]); + passed = 1'b0; + end + if (mem[31] !== "1") begin + $display("$fread (mem. 4[31]) value is wrong, expected %b, got %b", + "1", mem[31]); + passed = 1'b0; + end + + // This only gets the trailing new line. + rg = 9'bx; + res = $fread(rg, fd); + if (res != 1) begin + $display("$fread (EOL) count is wrong, expected 1, got %0d", res); + passed = 1'b0; + end + if (rg !== 9'h0xx) begin + $display("$fread (EOL value is wrong, expected 9'b0xx, got %b", rg); + passed = 1'b0; + end + + // There are no bits left so this array should be the same. + res = $fread(mem, fd); + if (res != 0) begin + $display("$fread (mem. EOL) count is wrong, expected 0, got %0d", res); + passed = 1'b0; + end + // Just check the end values and a value in the middle (15). + if (mem[0] !== "0") begin + $display("$fread (mem. EOL[0]) value is wrong, expected %b, got %b", + "0", mem[0]); + passed = 1'b0; + end + if (mem[15] !== "5") begin + $display("$fread (mem. EOL[15]) value is wrong, expected %b, got %b", + "5", mem[15]); + passed = 1'b0; + end + if (mem[31] !== "1") begin + $display("$fread (mem. EOL[31]) value is wrong, expected %b, got %b", + "1", mem[31]); + passed = 1'b0; + end + + $fclose(fd); + + if (passed) $display("PASSED"); + else $display("FAILED"); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/fscanf_u.v b/ivtest/ivltests/fscanf_u.v new file mode 100644 index 000000000..10dbbb0ae --- /dev/null +++ b/ivtest/ivltests/fscanf_u.v @@ -0,0 +1,242 @@ +module top; + reg [15:0] out_16; + reg [31:0] in_32, in_32x, ck_32, ck_32x, out_32, out_32x; + reg [63:0] out_64; + integer res, fd; + reg passed; + + initial begin + passed = 1'b1; + + // Check that a normal 32 bit %u works as expected. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32'b00001000_00100000_10100000_10001110; + $fwrite(fd, "%u", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%u", out_32); + if (res !== 1) begin + $display("FAILED: $fscanf() #1 returned %d", res); + passed = 1'b0; + end else if (ck_32 !== out_32) begin + $display("FAILED: #1 %b !== %b", ck_32, out_32); + passed = 1'b0; + end + res = $fscanf(fd, "%u", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #1 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a normal 32/64 bit %u works as expected. Do the write as + // two 32 bit values to make sure the word order is correct. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32'b00001000_00100000_10100000_10001110; + $fwrite(fd, "%u", in_32); + in_32x = 32'b0001000x_0010000x_0011000x_0100000x; + ck_32x = 32'b00010000_00100000_00110000_01000000; + $fwrite(fd, "%u", in_32x); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%u", out_64); + if (res !== 1) $display("FAILED: $fscanf() #2a returned %d", res); + else if ({ck_32x,ck_32} !== out_64) begin + $display("FAILED: #2a %b !== %b", {ck_32x,ck_32}, out_64); + passed = 1'b0; + end + res = $fscanf(fd, "%u", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #2a EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a normal 64/64 bit %u works as expected. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32'b00001000_00100000_10100000_10001110; + in_32x = 32'b0001000x_0010000x_0011000x_0100000x; + ck_32x = 32'b00010000_00100000_00110000_01000000; + $fwrite(fd, "%u", {in_32x,in_32}); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%u", out_64); + if (res !== 1) $display("FAILED: $fscanf() #2b returned %d", res); + else if ({ck_32x,ck_32} !== out_64) begin + $display("FAILED: #2b %b !== %b", {ck_32x,ck_32}, out_64); + passed = 1'b0; + end + res = $fscanf(fd, "%u", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #2b EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a normal 64/32 bit %u works as expected. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32'b00001000_00100000_10100000_10001110; + in_32x = 32'b0001000x_0010000x_0011000x_0100000x; + ck_32x = 32'b00010000_00100000_00110000_01000000; + $fwrite(fd, "%u", {in_32x,in_32}); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%u%u", out_32,out_32x); + if (res !== 2) $display("FAILED: $fscanf() #2c returned %d", res); + else if ({ck_32x,ck_32} !== {out_32x, out_32}) begin + $display("FAILED: #2c %b !== %b", {ck_32x,ck_32}, {out_32x,out_32}); + passed = 1'b0; + end + res = $fscanf(fd, "%u", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #2c EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a 16 bit %u works as expected. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32'b00001000_00100000_10100000_10001110; + $fwrite(fd, "%u", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%u", out_16); + if (res !== 1) begin + $display("FAILED: $fscanf() #3 returned %d", res); + passed = 1'b0; + end else if (ck_32[15:0] !== out_16) begin + $display("FAILED: #3 %b !== %b", ck_32[15:0], out_16); + passed = 1'b0; + end + res = $fscanf(fd, "%u", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #3 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a 16 bit %u works as expected even with a 32 bit variable. + // All 32 bits are read but we truncate and zero fill the result. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32'b00001000_00100000_10100000_10001110; + $fwrite(fd, "%u", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%16u", out_32); + if (res !== 1) begin + $display("FAILED: $fscanf() #4 returned %d", res); + passed = 1'b0; + end else if (ck_32[15:0] !== out_32) begin + $display("FAILED: #4 %b !== %b", ck_32[15:0], out_32); + passed = 1'b0; + end + res = $fscanf(fd, "%u", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #4 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a 32 bit %u works with a 64 bit variable when sized. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32'b00001000_00100000_10100000_10001110; + $fwrite(fd, "%u", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%32u", out_64); + if (res !== 1) begin + $display("FAILED: $fscanf() #5 returned %d", res); + passed = 1'b0; + end else if (ck_32 !== out_64) begin + $display("FAILED: #5 %b !== %b", ck_32, out_64); + passed = 1'b0; + end + res = $fscanf(fd, "%u", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #5 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that by default one element is suppressed. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32x = 32'b0001000x_0010000x_0011000x_0100000x; + $fwrite(fd, "%u", in_32x); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32'b00001000_00100000_10100000_10001110; + $fwrite(fd, "%u", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%*u%u", out_32); + if (res !== 1) begin + $display("FAILED: $fscanf() #6 returned %d", res); + passed = 1'b0; + end else if (ck_32 !== out_32) begin + $display("FAILED: #6 %b !== %b", ck_32, out_32); + passed = 1'b0; + end + res = $fscanf(fd, "%u", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #6 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that multiple elements can be suppressed (exact count). + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32x = 32'b0001000x_0010000x_0011000x_0100000x; + $fwrite(fd, "%u%u", in_32x, in_32x); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32'b00001000_00100000_10100000_10001110; + $fwrite(fd, "%u", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%*64u%u", out_32); + if (res !== 1) begin + $display("FAILED: $fscanf() #7 returned %d", res); + passed = 1'b0; + end else if (ck_32 !== out_32) begin + $display("FAILED: #7 %b !== %b", ck_32, out_32); + passed = 1'b0; + end + res = $fscanf(fd, "%u", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #7 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that multiple elements can be suppressed (minimum count). + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32x = 32'b0001000x_0010000x_0011000x_0100000x; + $fwrite(fd, "%u%u", in_32x, in_32x); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32'b00001000_00100000_10100000_10001110; + $fwrite(fd, "%u", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%*33u%u", out_32); + if (res !== 1) begin + $display("FAILED: $fscanf() #8 returned %d", res); + passed = 1'b0; + end else if (ck_32 !== out_32) begin + $display("FAILED: #8 %b !== %b", ck_32, out_32); + passed = 1'b0; + end + res = $fscanf(fd, "%u", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #8 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/fscanf_u_warn.v b/ivtest/ivltests/fscanf_u_warn.v new file mode 100644 index 000000000..84b104c2e --- /dev/null +++ b/ivtest/ivltests/fscanf_u_warn.v @@ -0,0 +1,122 @@ +module top; + reg [31:0] in_32, ck_32, out_32, out_32x; + reg [63:0] out_64; + integer res, fd; + reg passed; + + initial begin + passed = 1'b1; + + // Check that a normal 32 bit %u catches missing bytes. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%c%c", in_32[15:8], in_32[7:0]); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%u", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #1 returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a normal 64 bit %u catches missing bytes (1/4). + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%c%c", in_32[15:8], in_32[7:0]); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%u", out_64); + if (res !== -1) begin + $display("FAILED: $fscanf() #2a returned %d (%b)", res, out_64); + passed = 1'b0; + end + $fclose(fd); + + // Check that a normal 64 bit %u catches missing bytes (1/2). + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%u", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%u", out_64); + if (res !== -1) begin + $display("FAILED: $fscanf() #2b returned %d (%b)", res, out_64); + passed = 1'b0; + end + $fclose(fd); + + // Check that a normal 64 bit %u catches missing bytes (3/4). + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%u%c%c", in_32, in_32[15:8], in_32[7:0]); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%u", out_64); + if (res !== -1) begin + $display("FAILED: $fscanf() #2c returned %d (%b)", res, out_64); + passed = 1'b0; + end + $fclose(fd); + + // Check that a normal 32 bit %u suppression catches missing bytes. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%c%c", in_32[15:8], in_32[7:0]); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%*u", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #3 returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a multiple read %u catches missing bytes (1/2). + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + ck_32 = 32'b00001000_00100000_10100000_10001110; + $fwrite(fd, "%u%c%c", in_32, in_32[15:8], in_32[7:0]); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%u%u", out_32, out_32x); + if (res !== 1) begin + $display("FAILED: $fscanf() #4 returned %d (%b)", res, out_32x); + passed = 1'b0; + end else begin + if (ck_32 !== out_32) begin + $display("FAILED: $fscanf() #4 %b !== %b", ck_32, out_32); + passed = 1'b0; + end + if (out_32x !== 32'bx) begin + $display("FAILED: $fscanf() #4 %b !== 32'bx", out_32x); + passed = 1'b0; + end + end + res = $fscanf(fd, "%u", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #4 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a suppression/read %u catches missing bytes (1/2). + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%u%c%c", in_32, in_32[15:8], in_32[7:0]); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + out_32 = 32'bx; + res = $fscanf(fd, "%*u%u", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #5 returned %d (%b)", res, out_32); + passed = 1'b0; + end else if (out_32 !== 32'bx) begin + $display("FAILED: $fscanf() #5 %b !== 32'bx", out_32); + passed = 1'b0; + end + $fclose(fd); + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/fscanf_z.v b/ivtest/ivltests/fscanf_z.v new file mode 100644 index 000000000..b240370e1 --- /dev/null +++ b/ivtest/ivltests/fscanf_z.v @@ -0,0 +1,229 @@ +module top; + reg [15:0] out_16; + reg [31:0] in_32, in_32x, out_32, out_32x; + reg [63:0] out_64; + integer res, fd; + reg passed; + + initial begin + passed = 1'b1; + + // Check that a normal 32 bit %z works as expected. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%z", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%z", out_32); + if (res !== 1) begin + $display("FAILED: $fscanf() #1 returned %d", res); + passed = 1'b0; + end else if (in_32 !== out_32) begin + $display("FAILED: #1 %b !== %b", in_32, out_32); + passed = 1'b0; + end + res = $fscanf(fd, "%z", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #1 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a normal 32/64 bit %z works as expected. Do the write as + // two 32 bit values to make sure the word order is correct. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%z", in_32); + in_32x = 32'b0001000x_0010000x_0011000x_0100000x; + $fwrite(fd, "%z", in_32x); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%z", out_64); + if (res !== 1) $display("FAILED: $fscanf() #2a returned %d", res); + else if ({in_32x,in_32} !== out_64) begin + $display("FAILED: #2a %b !== %b", {in_32x,in_32}, out_64); + passed = 1'b0; + end + res = $fscanf(fd, "%z", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #2a EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a normal 64/64 bit %z works as expected. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + in_32x = 32'b0001000x_0010000x_0011000x_0100000x; + $fwrite(fd, "%z", {in_32x,in_32}); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%z", out_64); + if (res !== 1) $display("FAILED: $fscanf() #2b returned %d", res); + else if ({in_32x,in_32} !== out_64) begin + $display("FAILED: #2b %b !== %b", {in_32x,in_32}, out_64); + passed = 1'b0; + end + res = $fscanf(fd, "%z", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #2b EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a normal 64/32 bit %z works as expected. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + in_32x = 32'b0001000x_0010000x_0011000x_0100000x; + $fwrite(fd, "%z", {in_32x,in_32}); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%z%z", out_32,out_32x); + if (res !== 2) $display("FAILED: $fscanf() #2c returned %d", res); + else if ({in_32x,in_32} !== {out_32x, out_32}) begin + $display("FAILED: #2c %b !== %b", {in_32x,in_32}, {out_32x,out_32}); + passed = 1'b0; + end + res = $fscanf(fd, "%z", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #2c EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a 16 bit %z works as expected. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%z", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%z", out_16); + if (res !== 1) begin + $display("FAILED: $fscanf() #3 returned %d", res); + passed = 1'b0; + end else if (in_32[15:0] !== out_16) begin + $display("FAILED: #3 %b !== %b", in_32[15:0], out_16); + passed = 1'b0; + end + res = $fscanf(fd, "%z", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #3 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a 16 bit %z works as expected even with a 32 bit variable. + // All 32 bits are read but we truncate and zero fill the result. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%z", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%16z", out_32); + if (res !== 1) begin + $display("FAILED: $fscanf() #4 returned %d", res); + passed = 1'b0; + end else if (in_32[15:0] !== out_32) begin + $display("FAILED: #4 %b !== %b", in_32[15:0], out_32); + passed = 1'b0; + end + res = $fscanf(fd, "%z", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #4 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a 32 bit %z works with a 64 bit variable when sized. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%z", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%32z", out_64); + if (res !== 1) begin + $display("FAILED: $fscanf() #5 returned %d", res); + passed = 1'b0; + end else if (in_32 !== out_64) begin + $display("FAILED: #5 %b !== %b", in_32, out_64); + passed = 1'b0; + end + res = $fscanf(fd, "%z", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #5 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that by default one element is suppressed. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32x = 32'b0001000x_0010000x_0011000x_0100000x; + $fwrite(fd, "%z", in_32x); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%z", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%*z%z", out_32); + if (res !== 1) begin + $display("FAILED: $fscanf() #6 returned %d", res); + passed = 1'b0; + end else if (in_32 !== out_32) begin + $display("FAILED: #6 %b !== %b", in_32, out_32); + passed = 1'b0; + end + res = $fscanf(fd, "%z", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #6 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that multiple elements can be suppressed (exact count). + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32x = 32'b0001000x_0010000x_0011000x_0100000x; + $fwrite(fd, "%z%z", in_32x, in_32x); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%z", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%*64z%z", out_32); + if (res !== 1) begin + $display("FAILED: $fscanf() #7 returned %d", res); + passed = 1'b0; + end else if (in_32 !== out_32) begin + $display("FAILED: #7 %b !== %b", in_32, out_32); + passed = 1'b0; + end + res = $fscanf(fd, "%z", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #7 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that multiple elements can be suppressed (minimum count). + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32x = 32'b0001000x_0010000x_0011000x_0100000x; + $fwrite(fd, "%z%z", in_32x, in_32x); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%z", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%*33z%z", out_32); + if (res !== 1) begin + $display("FAILED: $fscanf() #8 returned %d", res); + passed = 1'b0; + end else if (in_32 !== out_32) begin + $display("FAILED: #8 %b !== %b", in_32, out_32); + passed = 1'b0; + end + res = $fscanf(fd, "%z", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #8 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/fscanf_z_warn.v b/ivtest/ivltests/fscanf_z_warn.v new file mode 100644 index 000000000..3851a9f15 --- /dev/null +++ b/ivtest/ivltests/fscanf_z_warn.v @@ -0,0 +1,121 @@ +module top; + reg [31:0] in_32, out_32, out_32x; + reg [63:0] out_64; + integer res, fd; + reg passed; + + initial begin + passed = 1'b1; + + // Check that a normal 32 bit %z catches missing bytes. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%u", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%z", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #1 returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a normal 64 bit %z catches missing bytes (1/4). + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%u", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%z", out_64); + if (res !== -1) begin + $display("FAILED: $fscanf() #2a returned %d (%b)", res, out_64); + passed = 1'b0; + end + $fclose(fd); + + // Check that a normal 64 bit %z catches missing bytes (1/2). + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%z", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%z", out_64); + if (res !== -1) begin + $display("FAILED: $fscanf() #2b returned %d (%b)", res, out_64); + passed = 1'b0; + end + $fclose(fd); + + // Check that a normal 64 bit %z catches missing bytes (3/4). + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%z%u", in_32, in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%z", out_64); + if (res !== -1) begin + $display("FAILED: $fscanf() #2c returned %d (%b)", res, out_64); + passed = 1'b0; + end + $fclose(fd); + + // Check that a normal 32 bit %z suppression catches missing bytes. + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%u", in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%*z", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #3 returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a multiple read %z catches missing bytes (1/2). + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%z%u", in_32, in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + res = $fscanf(fd, "%z%z", out_32, out_32x); + if (res !== 1) begin + $display("FAILED: $fscanf() #4 returned %d (%b)", res, out_32x); + passed = 1'b0; + end else begin + if (in_32 !== out_32) begin + $display("FAILED: $fscanf() #4 %b !== %b", in_32, out_32); + passed = 1'b0; + end + if (out_32x !== 32'bx) begin + $display("FAILED: $fscanf() #4 %b !== 32'bx", out_32x); + passed = 1'b0; + end + end + res = $fscanf(fd, "%z", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #4 EOF returned %d (%b)", res, out_32); + passed = 1'b0; + end + $fclose(fd); + + // Check that a suppression/read %z catches missing bytes (1/2). + fd = $fopen("work/test_fscanf.bin", "wb"); + in_32 = 32'b000x100z_001z000x_101xxxzz_100z111x; + $fwrite(fd, "%z%u", in_32, in_32); + $fclose(fd); + fd = $fopen("work/test_fscanf.bin", "rb"); + out_32 = 32'bx; + res = $fscanf(fd, "%*z%z", out_32); + if (res !== -1) begin + $display("FAILED: $fscanf() #5 returned %d (%b)", res, out_32); + passed = 1'b0; + end else if (out_32 !== 32'bx) begin + $display("FAILED: $fscanf() #5 %b !== 32'bx", out_32); + passed = 1'b0; + end + $fclose(fd); + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/full_case.v b/ivtest/ivltests/full_case.v new file mode 100644 index 000000000..ecf91feb8 --- /dev/null +++ b/ivtest/ivltests/full_case.v @@ -0,0 +1,40 @@ +/* + */ +module main; + + reg [1:0] sel, in; + reg [1:0] out; + + (* ivl_combinational *) + always @* + (* ivl_full_case *) case (sel) + 2'b01: out = 2'b10; + 2'b10: out = in[0]; + 2'b11: out = in[1]; + endcase // casex(sel) + + (* ivl_synthesis_off *) + initial begin + in = 2'b10; + + sel = 1; + #1 if (out !== 2'b10) begin + $display("FAILED -- sel=%b, out=%b", sel, out); + $finish; + end + + sel = 2; + #1 if (out !== 2'b00) begin + $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out); + $finish; + end + + sel = 3; + #1 if (out !== 2'b01) begin + $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/full_case2.v b/ivtest/ivltests/full_case2.v new file mode 100644 index 000000000..875dffe44 --- /dev/null +++ b/ivtest/ivltests/full_case2.v @@ -0,0 +1,40 @@ +/* + */ +module main; + + reg [1:0] sel, in; + reg [1:0] out; + + (* ivl_combinational *) + always @* begin + (* ivl_full_case *) case (sel) + 2'b01: out = 2'b10; + 2'b10: out = in[0]; + 2'b11: out = in[1]; + endcase // casex(sel) + end + (* ivl_synthesis_off *) + initial begin + in = 2'b10; + + sel = 1; + #1 if (out !== 2'b10) begin + $display("FAILED -- sel=%b, out=%b", sel, out); + $finish; + end + + sel = 2; + #1 if (out !== 2'b00) begin + $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out); + $finish; + end + + sel = 3; + #1 if (out !== 2'b01) begin + $display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/func_init_var1.v b/ivtest/ivltests/func_init_var1.v new file mode 100644 index 000000000..507c8d5af --- /dev/null +++ b/ivtest/ivltests/func_init_var1.v @@ -0,0 +1,59 @@ +module test(); + +function integer accumulate1(input integer value); + static int acc = 1; + acc = acc + value; + return acc; +endfunction + +function automatic integer accumulate2(input integer value); + int acc = 1; + acc = acc + value; + return acc; +endfunction + +localparam value1 = accumulate1(2); +localparam value2 = accumulate1(3); +localparam value3 = accumulate2(2); +localparam value4 = accumulate2(3); + +integer value; + +reg failed = 0; + +initial begin + $display("%d", value1); + if (value1 !== 3) failed = 1; + + $display("%d", value2); + if (value2 !== 4) failed = 1; + + $display("%d", value3); + if (value3 !== 3) failed = 1; + + $display("%d", value4); + if (value4 !== 4) failed = 1; + + value = accumulate1(2); + $display("%d", value); + if (value !== 3) failed = 1; + + value = accumulate1(3); + $display("%d", value); + if (value !== 6) failed = 1; + + value = accumulate2(2); + $display("%d", value); + if (value !== 3) failed = 1; + + value = accumulate2(3); + $display("%d", value); + if (value !== 4) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/func_init_var2.v b/ivtest/ivltests/func_init_var2.v new file mode 100644 index 000000000..22685dda4 --- /dev/null +++ b/ivtest/ivltests/func_init_var2.v @@ -0,0 +1,63 @@ +module static test(); + +function integer accumulate1(input integer value); +begin:blk + static int acc = 1; + acc = acc + value; + return acc; +end +endfunction + +function automatic integer accumulate2(input integer value); +begin:blk + automatic int acc = 1; + acc = acc + value; + return acc; +end +endfunction + +localparam value1 = accumulate1(2); +localparam value2 = accumulate1(3); +localparam value3 = accumulate2(2); +localparam value4 = accumulate2(3); + +integer value; + +initial begin + static reg failed = 0; + + $display("%d", value1); + if (value1 !== 3) failed = 1; + + $display("%d", value2); + if (value2 !== 4) failed = 1; + + $display("%d", value3); + if (value3 !== 3) failed = 1; + + $display("%d", value4); + if (value4 !== 4) failed = 1; + + value = accumulate1(2); + $display("%d", value); + if (value !== 3) failed = 1; + + value = accumulate1(3); + $display("%d", value); + if (value !== 6) failed = 1; + + value = accumulate2(2); + $display("%d", value); + if (value !== 3) failed = 1; + + value = accumulate2(3); + $display("%d", value); + if (value !== 4) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/func_init_var3.v b/ivtest/ivltests/func_init_var3.v new file mode 100644 index 000000000..6fbe4ec27 --- /dev/null +++ b/ivtest/ivltests/func_init_var3.v @@ -0,0 +1,59 @@ +module automatic test(); + +function static integer accumulate1(input integer value); + static int acc = 1; + acc = acc + value; + return acc; +endfunction + +function integer accumulate2(input integer value); + int acc = 1; + acc = acc + value; + return acc; +endfunction + +localparam value1 = accumulate1(2); +localparam value2 = accumulate1(3); +localparam value3 = accumulate2(2); +localparam value4 = accumulate2(3); + +integer value; + +reg failed = 0; + +initial begin + $display("%d", value1); + if (value1 !== 3) failed = 1; + + $display("%d", value2); + if (value2 !== 4) failed = 1; + + $display("%d", value3); + if (value3 !== 3) failed = 1; + + $display("%d", value4); + if (value4 !== 4) failed = 1; + + value = accumulate1(2); + $display("%d", value); + if (value !== 3) failed = 1; + + value = accumulate1(3); + $display("%d", value); + if (value !== 6) failed = 1; + + value = accumulate2(2); + $display("%d", value); + if (value !== 3) failed = 1; + + value = accumulate2(3); + $display("%d", value); + if (value !== 4) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/function1.v b/ivtest/ivltests/function1.v new file mode 100644 index 000000000..c4cfde092 --- /dev/null +++ b/ivtest/ivltests/function1.v @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This example catches the case of a unser defined function that is + * a parameter to a system task. + */ + +module main; + + function [15:0] sum; + input [15:0] a; + input [15:0] b; + + sum = a + b; + endfunction // sum + + initial begin + $display("%h = sum(%h, %h)", sum(3,5), 16'd3, 16'd5); + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/function10.v b/ivtest/ivltests/function10.v new file mode 100644 index 000000000..47a64243b --- /dev/null +++ b/ivtest/ivltests/function10.v @@ -0,0 +1,30 @@ +/* + * Copyright (c) 1998-2000 Andrei Purdea (andrei@purdea.ro) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + // Test that functions without parantheses for port-list, + // and without any declarations compile successfully. + // Valid according to IEEE1800-2005. + // IEEE1364-2005 requires at least one declaration. + function void empty_function; + endfunction + initial begin + empty_function(); + end +endmodule diff --git a/ivtest/ivltests/function11.v b/ivtest/ivltests/function11.v new file mode 100644 index 000000000..659a0265f --- /dev/null +++ b/ivtest/ivltests/function11.v @@ -0,0 +1,25 @@ +/* + * Copyright (c) 1998-2000 Andrei Purdea (andrei@purdea.ro) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// The below test is expected to fail with a combilation error. +module main; + function void bla(); + return 10; + endfunction +endmodule diff --git a/ivtest/ivltests/function12.v b/ivtest/ivltests/function12.v new file mode 100644 index 000000000..2a851cb73 --- /dev/null +++ b/ivtest/ivltests/function12.v @@ -0,0 +1,42 @@ +/* + * Copyright (c) 1998-2000 Andrei Purdea (andrei@purdea.ro) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// This test checks that returning from a void function works correctly. +module main; + int res = 123; + function void bla(); + int i; + for (i=0;i<10;i=i+1) begin + res = i; + $display("loop %d", i); + if (i == 5) + begin + return; + end + end + endfunction + initial begin + bla(); + if (res == 5) begin + $display("PASS"); + end else begin + $display("FAIL"); + end + end +endmodule diff --git a/ivtest/ivltests/function2.v b/ivtest/ivltests/function2.v new file mode 100644 index 000000000..ae1a9c3d7 --- /dev/null +++ b/ivtest/ivltests/function2.v @@ -0,0 +1,24 @@ +/* + * This program handles the case of a system task within a user + * defined function. + */ +module main; + + reg [31:0] tmp1; + reg [31:0] tmp2; + + function [31:0] test; + input [31:0] op1; + + $write("op1 = %h\n", op1); + + endfunction + + initial + begin + tmp1 = 'hdeadbeef; + tmp2 = test(tmp1); + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/function3.11B.v b/ivtest/ivltests/function3.11B.v new file mode 100644 index 000000000..5539626e7 --- /dev/null +++ b/ivtest/ivltests/function3.11B.v @@ -0,0 +1,59 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate function w/ single input + +module main (); + +reg [31:0] val1,val2 ; +reg error; + +function [31:0] myfunc ; + input [31:0] in1 ; + myfunc = in1 ; +endfunction + +initial + begin + error = 0; + val1 = myfunc(32'h0) ; + if(val1 != 32'h0) + begin + $display("FAILED - function3.11B - func(lit) != lit "); + error = 1; + end + + val2 = 32'h12345678 ; + val1 = myfunc(val2); + if(val1 != val2) + begin + $display("FAILED - function3.11B - func(reg var) != reg var "); + error = 1; + end + + if(myfunc(32'h10101010) != 32'h10101010) + begin + $display("FAILED - function3.11B - if(func(reg var) != reg var) "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/function3.11C.v b/ivtest/ivltests/function3.11C.v new file mode 100644 index 000000000..fe5bb4468 --- /dev/null +++ b/ivtest/ivltests/function3.11C.v @@ -0,0 +1,64 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate function called from within function + +module main (); + +reg [31:0] val1,val2 ; +reg error; + +function [31:0] myfunc2 ; + input [31:0] in2 ; + myfunc2 = in2; +endfunction + +function [31:0] myfunc1 ; + input [31:0] in1 ; + myfunc1 = myfunc2(in1) ; +endfunction + +initial + begin + error = 0; + val1 = myfunc1(32'h0) ; + if(val1 != 32'h0) + begin + $display("FAILED - function3.11C - function called from funct(1)"); + error = 1; + end + + val2 = 32'h12345678 ; + val1 = myfunc1(val2); + if(val1 != val2) + begin + $display("FAILED - function3.11C - function called from funct(2)"); + error = 1; + end + + if(myfunc1(32'h10101010) != 32'h10101010) + begin + $display("FAILED - function3.11C - function called from funct(3)"); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/function3.11D.v b/ivtest/ivltests/function3.11D.v new file mode 100644 index 000000000..8fe1dba40 --- /dev/null +++ b/ivtest/ivltests/function3.11D.v @@ -0,0 +1,58 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate function within a continuous assignment + +module main (); + +reg error; +reg [3:0] val2; + + +function [3:0] myfunc ; + input [31:0] in1 ; + myfunc = in1; +endfunction + +wire [3:0] val1; +assign val1 = myfunc(val2); + +initial + begin + error = 0; + val2 = 4'h0; + # 1 ; + if(val1 !== 4'b0) + begin + $display("FAILED - function3.11D - function within continuous assign(1)"); + error = 1; + end + + val2 = 32'h8; + # 1 ; + if(val1 !== val2) + begin + $display("FAILED - function3.11D - function within continuous assign(2)"); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/function3.11E.v b/ivtest/ivltests/function3.11E.v new file mode 100644 index 000000000..16079638f --- /dev/null +++ b/ivtest/ivltests/function3.11E.v @@ -0,0 +1,40 @@ +// +// Copyright (c) 2000 Steve Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// function3.11E - Validate calling a task in a function causes an error. +// +module test ; + +task foo2; +$display("insided foo2"); +endtask + +function [31:0] foo; +input [31:0] a; +foo = a; +foo2; +endfunction + +reg [31:0] b; +initial + begin + $display("hi"); + b = foo(123); + end + +endmodule diff --git a/ivtest/ivltests/function3.11F.v b/ivtest/ivltests/function3.11F.v new file mode 100644 index 000000000..3be30a2f0 --- /dev/null +++ b/ivtest/ivltests/function3.11F.v @@ -0,0 +1,66 @@ +// +// Copyright (c) 1999 Peter Monta (pmonta@imedia.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// 9/7/99 - SDW - Modified by instantiating Peter's module into a +// self-checking structure. Moved bar=result inside +// begin clause in function. +// +// SDW - Validate function contains a register + +module main (); + +reg [1:0] val1; +reg val2; +reg error; + +function bar; + input [1:0] arg; + reg result; + begin + result = |arg; + bar = result; + end +endfunction + +initial + begin + error = 0; + val2 = bar(2'b01); + if(val2 != 1) + begin + $display("FAILED function 3.11F - register within a function(1)"); + error = 1; + end + val1 = 2'b11 ; + val2 = bar(val1) ; + if(val2 != 1) + begin + $display("FAILED function 3.11F - register within a function(2)"); + error = 1; + end + val2 = bar(2'b00); + if(val2 != 0) + begin + $display("FAILED function 3.11F - register within a function(2)"); + error = 1; + end + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/function3.v b/ivtest/ivltests/function3.v new file mode 100644 index 000000000..dc598a9f7 --- /dev/null +++ b/ivtest/ivltests/function3.v @@ -0,0 +1,64 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program checks that a function execution that includes part + * selects properly evaluates expressions. This is inspired by PR#95. + */ +module main; + + wire [3:0] a = 4'h1; + wire [3:0] b = 4'h3; + reg [1:0] got1, got2; + reg [7:0] line; + + initial + begin + line = 8'h30; + + #1; // Need some delay for the assignments to run. + got1 = { (b[3:0] == line[7:4]), (a[3:0] == line[3:0]) }; + got2 = test(a, b, line); + + $display("a=%b, b=%b, line=%b, got1=%b, got2=%b", + a, b, line, got1, got2); + + if (got1 !== 2'b10) begin + $display("FAILED -- got1 is wrong: %b !== 2'b10", got1); + $finish; + end + + if (got1 !== got2) begin + $display("FAILED -- got2 is incorrect: %b !== %b", got1, got2); + $finish; + end + + $display("PASSED"); + $finish; + end + + function [1:0] test; + input [3:0] a, b; + input [7:0] line; + test = { (b == line[7:4]), (a[3:0] == line[3:0]) }; + + endfunction // test + + +endmodule // main diff --git a/ivtest/ivltests/function4.v b/ivtest/ivltests/function4.v new file mode 100644 index 000000000..945ddc61c --- /dev/null +++ b/ivtest/ivltests/function4.v @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This problem shows the case of a function with no input ports, + * and also a function with a parameter (not a port). + * + * A function without an argument is an error, so this should fail. + */ + +module main; + + function [3:0] test; + + parameter a = 3; + reg [a:0] out; + + begin + out = a; + test[3:0] = out[3:0]; + end + + endfunction + + reg [3:0] tmp; + initial begin + tmp = test(); + if (tmp !== 4'b0011) begin + $display("FAILED -- tmp == %b", tmp); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/function5.v b/ivtest/ivltests/function5.v new file mode 100644 index 000000000..16772031a --- /dev/null +++ b/ivtest/ivltests/function5.v @@ -0,0 +1,25 @@ +// Submitted as PR184 by Matt Welland +module test; + + wire foo; + reg [1:49] bar; + + function foobar; + input [1:49] a; + begin + foobar = a[1] & a[2] & a[3] & a[4] & a[5] & + a[6] & a[7] & a[8] & a[9] & a[10] & + a[11] & a[12] & a[13] & a[14] & a[15] & + a[16] & a[17] & a[18] & a[19] & a[20] & + a[21] & a[22] & a[23] & a[24] & a[25] & + a[26] & a[27] & a[28] & a[29] & a[30] & + a[31] & a[32] & a[33] & a[34] & a[35] & + a[36] & a[37] & a[38] & a[39] & a[40] & + a[41] & a[42] & a[43] & a[44] & a[45] & + a[46] & a[47] & a[48] & a[49] ; + end + endfunction + + assign foo = foobar( bar ); + +endmodule diff --git a/ivtest/ivltests/function6.v b/ivtest/ivltests/function6.v new file mode 100644 index 000000000..a2983a50d --- /dev/null +++ b/ivtest/ivltests/function6.v @@ -0,0 +1,26 @@ +module test; + + function f_0; + input i; + begin + f_0 = f_1(i); + end + endfunction + + function f_1; + input i; + begin + f_1 = !i; + end + endfunction + + wire w = f_0(1'b0); + + initial begin + #1; + if ( w !== 1'b1) + $display ("FAILED w (%b) !== 1'b1", w); + else + $display ("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/function7.v b/ivtest/ivltests/function7.v new file mode 100644 index 000000000..008212d31 --- /dev/null +++ b/ivtest/ivltests/function7.v @@ -0,0 +1,28 @@ +module test; + parameter BYTES = 2; + localparam mxbit = BYTES*8-1; + + function integer clog2; + input value; + integer value; + for (clog2=0; value>0; clog2=clog2+1) value = value >> 1; + endfunction + + // This is not recognized as a constant function call! + localparam cntrw = clog2(mxbit); + + integer tmp; + initial begin + tmp = mxbit; + $display("The maximum bit is %0d and uses a %0d bit counter", mxbit, cntrw); + $display("clog2 does works here! Got %0d, should be %0d.", clog2(mxbit), clog2(tmp)); + + if (cntrw !== clog2(tmp)) begin + $display("FAILED -- cntrw=%0d", cntrw); + $finish; + end + + $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/function8.v b/ivtest/ivltests/function8.v new file mode 100644 index 000000000..23c38d7b2 --- /dev/null +++ b/ivtest/ivltests/function8.v @@ -0,0 +1,55 @@ +// Test constant functions. +module main; + + localparam BYTESIZE = 8; + localparam STRLEN = 4; + + function [STRLEN*BYTESIZE - 1 : 0] bits2text; + input [STRLEN-1:0] use_map; + + integer idx; + begin + bits2text = 0; + for (idx = 0 ; idx < STRLEN ; idx = idx+1) begin + bits2text[(idx*BYTESIZE) +: BYTESIZE] = (use_map[idx] == 1'b0)? "1" : "0"; + end + end + endfunction + + + localparam [STRLEN*BYTESIZE - 1 : 0] str0010 = bits2text(4'b0010); + localparam [STRLEN*BYTESIZE - 1 : 0] str0100 = bits2text(4'b0100); + localparam [STRLEN*BYTESIZE - 1 : 0] str0011 = bits2text(4'b0011); + localparam [STRLEN*BYTESIZE - 1 : 0] str1100 = bits2text(4'b1100); + + reg [STRLEN*BYTESIZE - 1 : 0] tmp; + initial begin + tmp = bits2text(4'b0010); + if (tmp !== str0010) begin + $display("FAILED -- str0010=%h, expect %h", str0010, tmp); + $finish; + end + + tmp = bits2text(4'b0100); + if (tmp !== str0100) begin + $display("FAILED -- str0100=%h, expect %h", str0100, tmp); + $finish; + end + + tmp = bits2text(4'b0011); + if (tmp !== str0011) begin + $display("FAILED -- str0011=%h, expect %h", str0011, tmp); + $finish; + end + + tmp = bits2text(4'b1100); + if (tmp !== str1100) begin + $display("FAILED -- str1100=%h, expect %h", str1100, tmp); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/function9.v b/ivtest/ivltests/function9.v new file mode 100644 index 000000000..3ff9b486b --- /dev/null +++ b/ivtest/ivltests/function9.v @@ -0,0 +1,55 @@ +module main; + + localparam BYTESIZE = 8; + localparam STRLEN = 4; + localparam [15:0] CHAR = "10"; + + function [STRLEN*BYTESIZE - 1 : 0] bits2text; + input [STRLEN-1:0] use_map; + + integer idx; + begin + bits2text = 0; + for (idx = 0 ; idx < STRLEN ; idx = idx+1) begin + bits2text[(idx*BYTESIZE) +: BYTESIZE] = CHAR[BYTESIZE*use_map[idx] +: BYTESIZE]; + end + end + endfunction + + + localparam [STRLEN*BYTESIZE - 1 : 0] str0010 = bits2text(4'b0010); + localparam [STRLEN*BYTESIZE - 1 : 0] str0100 = bits2text(4'b0100); + localparam [STRLEN*BYTESIZE - 1 : 0] str0011 = bits2text(4'b0011); + localparam [STRLEN*BYTESIZE - 1 : 0] str1100 = bits2text(4'b1100); + + reg [STRLEN*BYTESIZE - 1 : 0] tmp; + initial begin + tmp = bits2text(4'b0010); + if (tmp !== str0010) begin + $display("FAILED -- str0010=%h, expect %h", str0010, tmp); + $finish; + end + + tmp = bits2text(4'b0100); + if (tmp !== str0100) begin + $display("FAILED -- str0100=%h, expect %h", str0100, tmp); + $finish; + end + + tmp = bits2text(4'b0011); + if (tmp !== str0011) begin + $display("FAILED -- str0011=%h, expect %h", str0011, tmp); + $finish; + end + + tmp = bits2text(4'b1100); + if (tmp !== str1100) begin + $display("FAILED -- str1100=%h, expect %h", str1100, tmp); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/function_exp.v b/ivtest/ivltests/function_exp.v new file mode 100644 index 000000000..872f1910c --- /dev/null +++ b/ivtest/ivltests/function_exp.v @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2000 Peter monta (pmonta@pacbell.net) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module main; + + function [3:0] foo; + input [3:0] x; + begin + foo = ~x + 1; + end + endfunction + + reg [3:0] x; + wire [3:0] y; + + assign y = foo(x); + + initial begin + x = 4'b0110; + #1; + if (y==4'b1010) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/ga_and.v b/ivtest/ivltests/ga_and.v new file mode 100644 index 000000000..87a2a717b --- /dev/null +++ b/ivtest/ivltests/ga_and.v @@ -0,0 +1,58 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate and gate vector +// + + +module main; + +reg globvar; + +wire [15:0] out; +reg [15:0] a,b, rslt; +reg error; + +// The test gate goes HERE! + +and foo [15:0] (out,a,b); + +always @(a or b) + rslt = a & b; + +initial + begin // { + error = 0; + # 1; + for(a = 16'h1; a != 16'hffff; a = (a << 1) | 1) + begin // { + for(b = 16'hffff; b !== 16'h0; b = b >> 1) + begin // { + #1 ; + if(out !== rslt) + begin // { + $display("FAILED - GA And a=%h,b=%h,expct=%h - rcvd=%h", + a,b,rslt,out); + error = 1; + end // } + end // } + end // } + if( error == 0) + $display("PASSED"); + end // } +endmodule // main diff --git a/ivtest/ivltests/ga_mod.v b/ivtest/ivltests/ga_mod.v new file mode 100644 index 000000000..485b7e5be --- /dev/null +++ b/ivtest/ivltests/ga_mod.v @@ -0,0 +1,69 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate that arrays spread across the input range of an arrayed +// module instantiation are supported. +// + +module my_and (out,a,b); +input [3:0] a,b; +output [3:0] out; + +and u0 (out[0],a[0],b[0]); +and u1 (out[1],a[1],b[1]); +and u2 (out[2],a[2],b[2]); +and u3 (out[3],a[3],b[3]); + +endmodule + +module main; + +reg globvar; + +wire [15:0] out; +reg [15:0] a,b, rslt; +reg error; + +// The test gate goes HERE! + +my_and foo [0:3] (out,a,b); + +always @(a or b) + rslt = a & b; + +initial + begin // { + error = 0; + # 1; + for(a = 16'h1; a != 16'hffff; a = (a << 1) | 1) + begin // { + for(b = 16'hffff; b !== 16'h0; b = b >> 1) + begin // { + #1 ; + if(out !== rslt) + begin // { + $display("FAILED - GA And a=%h,b=%h,expct=%h - rcvd=%h", + a,b,rslt,out); + error = 1; + end // } + end // } + end // } + if( error == 0) + $display("PASSED"); + end // } +endmodule // main diff --git a/ivtest/ivltests/ga_mod1.v b/ivtest/ivltests/ga_mod1.v new file mode 100644 index 000000000..e8a812bc0 --- /dev/null +++ b/ivtest/ivltests/ga_mod1.v @@ -0,0 +1,65 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate that an array of modules in supported. +// + +module my_and (out,a,b); +input a,b; +output out; + +and u0 (out,a,b); + +endmodule + +module main; + +reg globvar; + +wire [15:0] out; +reg [15:0] a,b, rslt; +reg error; + +// The test gate goes HERE! + +my_and foo [0:15] (out,a,b); + +always @(a or b) + rslt = a & b; + +initial + begin // { + error = 0; + # 1; + for(a = 16'h1; a != 16'hffff; a = (a << 1) | 1) + begin // { + for(b = 16'hffff; b !== 16'h0; b = b >> 1) + begin // { + #1 ; + if(out !== rslt) + begin // { + $display("FAILED - GA And a=%h,b=%h,expct=%h - rcvd=%h", + a,b,rslt,out); + error = 1; + end // } + end // } + end // } + if( error == 0) + $display("PASSED"); + end // } +endmodule // main diff --git a/ivtest/ivltests/ga_mod2.v b/ivtest/ivltests/ga_mod2.v new file mode 100644 index 000000000..11cb40f13 --- /dev/null +++ b/ivtest/ivltests/ga_mod2.v @@ -0,0 +1,64 @@ +// +// Copyright (c) 2004 Stephen Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + + reg C; + reg [1:0] in; + wire [1:0] out; + + DFF u [1:0] (out, in, C); + + initial begin + C <= 0; + in <= 2'b00; + + #10 C <= 1; + #10 if (out !== 2'b00) begin + $display("FAILED -- out=%b, in=%b", out, in); + $finish; + end + + C <= 0; + in <= 2'b10; + #10 C <= 1; + #10 if (out !== 2'b10) begin + $display("FAILED -- out=%b, in=%b", out, in); + $finish; + end + + C <= 0; + in <= 2'b01; + #10 C <= 1; + #10 if (out !== 2'b01) begin + $display("FAILED -- out=%b, in=%b", out, in); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main + +module DFF(output reg Q, input D, input C); + + always @(posedge C) + Q <= D; + +endmodule // DFF diff --git a/ivtest/ivltests/ga_nand.v b/ivtest/ivltests/ga_nand.v new file mode 100644 index 000000000..2be48640e --- /dev/null +++ b/ivtest/ivltests/ga_nand.v @@ -0,0 +1,58 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate NAND gate vector +// + + +module main; + +reg globvar; + +wire [15:0] out; +reg [15:0] a,b, rslt; +reg error; + +// The test gate goes HERE! + +nand foo [15:0] (out,a,b); + +always @(a or b) + rslt = ~(a & b); + +initial + begin // { + error = 0; + # 1; + for(a = 16'h1; a != 16'hffff; a = (a << 1) | 1) + begin // { + for(b = 16'hffff; b !== 16'h0; b = b >> 1) + begin // { + #1 ; + if(out !== rslt) + begin // { + $display("FAILED - GA NAND a=%h,b=%h,expct=%h - rcvd=%h", + a,b,rslt,out); + error = 1; + end // } + end // } + end // } + if( error == 0) + $display("PASSED"); + end // } +endmodule // main diff --git a/ivtest/ivltests/ga_nor.v b/ivtest/ivltests/ga_nor.v new file mode 100644 index 000000000..57d7a729e --- /dev/null +++ b/ivtest/ivltests/ga_nor.v @@ -0,0 +1,58 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate NOR gate vector +// + + +module main; + +reg globvar; + +wire [15:0] out; +reg [15:0] a,b, rslt; +reg error; + +// The test gate goes HERE! + +nor foo [15:0] (out,a,b); + +always @(a or b) + rslt = ~(a | b); + +initial + begin // { + error = 0; + # 1; + for(a = 16'h1; a != 16'h8000; a = (a << 1) ) + begin // { + for(b = 16'h8000; b !== 16'h0; b = b >> 1) + begin // { + #1 ; + if(out !== rslt) + begin // { + $display("FAILED - GA NOR a=%h,b=%h,expct=%h - rcvd=%h", + a,b,rslt,out); + error = 1; + end // } + end // } + end // } + if( error == 0) + $display("PASSED"); + end // } +endmodule // main diff --git a/ivtest/ivltests/ga_or.v b/ivtest/ivltests/ga_or.v new file mode 100644 index 000000000..104074902 --- /dev/null +++ b/ivtest/ivltests/ga_or.v @@ -0,0 +1,58 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate OR gate vector +// + + +module main; + +reg globvar; + +wire [15:0] out; +reg [15:0] a,b, rslt; +reg error; + +// The test gate goes HERE! + +or foo [15:0] (out,a,b); + +always @(a or b) + rslt = a | b; + +initial + begin // { + error = 0; + # 1; + for(a = 16'h1; a != 16'h8000; a = (a << 1) ) + begin // { + for(b = 16'h8000; b !== 16'h0; b = b >> 1) + begin // { + #1 ; + if(out !== rslt) + begin // { + $display("FAILED - GA OR a=%h,b=%h,expct=%h - rcvd=%h", + a,b,rslt,out); + error = 1; + end // } + end // } + end // } + if( error == 0) + $display("PASSED"); + end // } +endmodule // main diff --git a/ivtest/ivltests/ga_xnor.v b/ivtest/ivltests/ga_xnor.v new file mode 100644 index 000000000..e247397f7 --- /dev/null +++ b/ivtest/ivltests/ga_xnor.v @@ -0,0 +1,59 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate XNOR gate vector +// + + +module main; + +reg globvar; + +wire [15:0] out; +reg [15:0] a,b, rslt; +reg error; + +// The test gate goes HERE! + +xnor foo [15:0] (out,a,b); + +// This is the computed value used to determine if the gate is sane. +always @(a or b) + rslt = ~(a ^ b); + +initial + begin // { + error = 0; + # 1; + for(a = 16'h1; a != 16'hffff; a = (a << 1) | 1) + begin // { + for(b = 16'hffff; b !== 16'h0; b = b >> 1) + begin // { + #1 ; + if(out !== rslt) + begin // { + $display("FAILED - GA XNOR a=%h,b=%h,expct=%h - rcvd=%h", + a,b,rslt,out); + error = 1; + end // } + end // } + end // } + if( error == 0) + $display("PASSED"); + end // } +endmodule // main diff --git a/ivtest/ivltests/ga_xor.v b/ivtest/ivltests/ga_xor.v new file mode 100644 index 000000000..f9f38996a --- /dev/null +++ b/ivtest/ivltests/ga_xor.v @@ -0,0 +1,59 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate XOR gate vector +// + + +module main; + +reg globvar; + +wire [15:0] out; +reg [15:0] a,b, rslt; +reg error; + +// The test gate goes HERE! + +xor foo [15:0] (out,a,b); + +// This is the computed value used to determine if the gate is sane. +always @(a or b) + rslt = a ^ b; + +initial + begin // { + error = 0; + # 1; + for(a = 16'h1; a != 16'hffff; a = (a << 1) | 1) + begin // { + for(b = 16'hffff; b !== 16'h0; b = b >> 1) + begin // { + #1 ; + if(out !== rslt) + begin // { + $display("FAILED - GA XOR a=%h,b=%h,expct=%h - rcvd=%h", + a,b,rslt,out); + error = 1; + end // } + end // } + end // } + if( error == 0) + $display("PASSED"); + end // } +endmodule // main diff --git a/ivtest/ivltests/galan.v b/ivtest/ivltests/galan.v new file mode 100644 index 000000000..fd60bbec2 --- /dev/null +++ b/ivtest/ivltests/galan.v @@ -0,0 +1,58 @@ +/* +Steve, + I have small 8bit CPU working in Iverilog, it works if I + change a line similar to the one below in the test case to + + assign result = (data[0] | data[1]) ? 1:0; + + using the test case below I get, + + elab_net.cc:1368: failed assertion `expr_sig->pin_count() == 1' + + when compiling using the standard "verilog bug.v" (verilog-20000519) + + This works fine in XL. + + Regards + + Gerard. + + PS thanks for fixing the $monitor function. It works as XL, + as long as I pipe the output through uniq (./stimexe | uniq) + + + */ + + +module stim; + wire [1:0] data; + wire result; + + + assign result = data ? 1:0; + + initial + $display("PASSED"); + + +endmodule // stim + + +/* + * Copyright (c) 2000 Gerard A. Allan (gaa@ee.ed.ac.uk) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ diff --git a/ivtest/ivltests/gate_connect1.v b/ivtest/ivltests/gate_connect1.v new file mode 100644 index 000000000..61e177bd8 --- /dev/null +++ b/ivtest/ivltests/gate_connect1.v @@ -0,0 +1,24 @@ +// Test behaviour when a multi-bit expression is used as the input of +// a single instance of a primitive gate. The standard is quiet about +// this, but the consensus among other simulators is that the LSB of +// the expression is used. + +module top; + +reg [1:0] in; +wire [2:0] out; + +buf buf1(out[0], 1); +buf buf2(out[1], 2'b01); +buf buf3(out[2], in[1:0]); + +initial begin + in = 1; + #1 $display("out = %b", out); + if (out === 3'b111) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/gate_connect2.v b/ivtest/ivltests/gate_connect2.v new file mode 100644 index 000000000..dc68bcaff --- /dev/null +++ b/ivtest/ivltests/gate_connect2.v @@ -0,0 +1,21 @@ +// Test behaviour when a multi-bit expression is used as the input of +// a singleton array of a primitive gate. The standard is explicit +// that this should be treated as an error. + +module top; + +reg [1:0] in; +wire [2:0] out; + +buf buf1[0:0](out[0], 1); +buf buf2[0:0](out[1], 2'b01); +buf buf3[0:0](out[2], in[1:0]); + +initial begin + in = 1; + #1 $display("out = %b", out); + // this should have failed at compile time + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/gen_case_opt1.v b/ivtest/ivltests/gen_case_opt1.v new file mode 100644 index 000000000..0f57d4faa --- /dev/null +++ b/ivtest/ivltests/gen_case_opt1.v @@ -0,0 +1,16 @@ +module top; + parameter NAME = "test"; + wire i = 0; + + generate + case(NAME) + "test" : assign i = 1'b1; + default : ; + endcase + endgenerate + + initial begin + #1 if (i !== 1'bx) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/gen_case_opt2.v b/ivtest/ivltests/gen_case_opt2.v new file mode 100644 index 000000000..b5d188d4b --- /dev/null +++ b/ivtest/ivltests/gen_case_opt2.v @@ -0,0 +1,16 @@ +module top; + parameter NAME = "def"; + wire i = 0; + + generate + case(NAME) + "test" : assign i = 1'b1; + default : ; + endcase + endgenerate + + initial begin + #1 if (i !== 1'b0) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/gen_case_opt3.v b/ivtest/ivltests/gen_case_opt3.v new file mode 100644 index 000000000..ce93d4fb9 --- /dev/null +++ b/ivtest/ivltests/gen_case_opt3.v @@ -0,0 +1,17 @@ +module top; + parameter NAME = "skip"; + wire i = 0; + + generate + case(NAME) + "test" : assign i = 1'b1; + "skip" : ; + default : ; + endcase + endgenerate + + initial begin + #1 if (i !== 1'b0) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/generate_case.v b/ivtest/ivltests/generate_case.v new file mode 100644 index 000000000..a8024b52a --- /dev/null +++ b/ivtest/ivltests/generate_case.v @@ -0,0 +1,52 @@ +module main; + + wire [2:0] value1, value2, value3, value4; + + dut #( .select(1) ) dut1(value1); + dut #( .select(2) ) dut2(value2); + dut #( .select(3) ) dut3(value3); + dut #( .select(4) ) dut4(value4); + + initial begin + #1 $display("value1=%d, value2=%d, value3=%d, value4=%d", + value1, value2, value3, value4); + + if (value1 !== 1) begin + $display("FAILED -- value1=%b", value1); + $finish; + end + + if (value2 !== 2) begin + $display("FAILED -- value2=%b", value2); + $finish; + end + + if (value3 !== 3) begin + $display("FAILED -- value3=%b", value3); + $finish; + end + + if (value4 !== 7) begin + $display("FAILED -- value4=%b", value4); + $finish; + end + + $display("PASSED"); + end + +endmodule // main + +module dut(output wire [2:0] value); + + parameter select = 0; + + case (select) + 0: assign value = 0; + 1: assign value = 1; + 2: assign value = 2; + 3: assign value = 3; + default: + assign value = 7; + endcase // case endcase + +endmodule // dut diff --git a/ivtest/ivltests/generate_case2.v b/ivtest/ivltests/generate_case2.v new file mode 100644 index 000000000..9815b152e --- /dev/null +++ b/ivtest/ivltests/generate_case2.v @@ -0,0 +1,66 @@ +module main; + + wire [2:0] value1, value2, value3, value4; + + dut #( .select(1) ) dut1(value1); + dut #( .select(2) ) dut2(value2); + dut #( .select(3) ) dut3(value3); + dut #( .select(4) ) dut4(value4); + + initial begin + #1 $display("value1=%d, value2=%d, value3=%d, value4=%d", + value1, value2, value3, value4); + + if (value1 !== 1) begin + $display("FAILED -- value1=%b", value1); + $finish; + end + + if (value2 !== 2) begin + $display("FAILED -- value2=%b", value2); + $finish; + end + + if (value3 !== 3) begin + $display("FAILED -- value3=%b", value3); + $finish; + end + + if (value4 !== 7) begin + $display("FAILED -- value4=%b", value4); + $finish; + end + + $display("PASSED"); + end + +endmodule // main + +module dut(output wire [2:0] value); + + parameter select = 0; + + case (select) + 0: begin + function [2:0] funfun; + input integer in; + funfun = in; + endfunction // funfun + + assign value = funfun(select); + end + 1: begin + function [2:0] funfun; + input integer in; + funfun = in; + endfunction // funfun + + assign value = funfun(1); + end + 2: assign value = 2; + 3: assign value = 3; + default: + assign value = 7; + endcase // case endcase + +endmodule // dut diff --git a/ivtest/ivltests/generate_case3.v b/ivtest/ivltests/generate_case3.v new file mode 100644 index 000000000..2af8d2284 --- /dev/null +++ b/ivtest/ivltests/generate_case3.v @@ -0,0 +1,30 @@ +module main; + + parameter COND = 1; + parameter SEL = 0; + parameter VAL0 = 0; + parameter VAL1 = 1; + parameter VAL2 = 2; + + wire [3:0] foo; + if (COND) begin + case (SEL) + 0: assign foo = VAL0; + 1: assign foo = VAL1; + 2: assign foo = VAL2; + endcase // case (SEL) + end else begin + assign foo = 'bx; + end + + initial begin + #1 $display("foo = %b", foo); + if (foo !== VAL0) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/generate_multi_loop.v b/ivtest/ivltests/generate_multi_loop.v new file mode 100644 index 000000000..d01e380e0 --- /dev/null +++ b/ivtest/ivltests/generate_multi_loop.v @@ -0,0 +1,80 @@ +`begin_keywords "1364-2005" +module generate_multi_loop(); + +reg [31:0] input_value; + +wire [31:0] output_value; + +generate + genvar i; + genvar j; + + for (i = 0; i < 4; i = i + 1) begin:byte + wire [7:0] byte_value; + + for (j = 0; j < 8; j = j + 1) begin:bit + wire bit_value; + + buf buffer(bit_value, input_value[i*8+j]); + + assign byte_value[j] = bit_value; + end + + assign output_value[i*8+7:i*8] = byte_value; + end +endgenerate + +initial begin + input_value = 32'h12345678; + #1; + $write("byte_value ="); + $write(" %b", byte[3].byte_value); + $write(" %b", byte[2].byte_value); + $write(" %b", byte[1].byte_value); + $write(" %b", byte[0].byte_value); + $write("\n"); + $write("bit_value = "); + $write("%b", byte[3].bit[7].bit_value); + $write("%b", byte[3].bit[6].bit_value); + $write("%b", byte[3].bit[5].bit_value); + $write("%b", byte[3].bit[4].bit_value); + $write("%b", byte[3].bit[3].bit_value); + $write("%b", byte[3].bit[2].bit_value); + $write("%b", byte[3].bit[1].bit_value); + $write("%b", byte[3].bit[0].bit_value); + $write(" "); + $write("%b", byte[2].bit[7].bit_value); + $write("%b", byte[2].bit[6].bit_value); + $write("%b", byte[2].bit[5].bit_value); + $write("%b", byte[2].bit[4].bit_value); + $write("%b", byte[2].bit[3].bit_value); + $write("%b", byte[2].bit[2].bit_value); + $write("%b", byte[2].bit[1].bit_value); + $write("%b", byte[2].bit[0].bit_value); + $write(" "); + $write("%b", byte[1].bit[7].bit_value); + $write("%b", byte[1].bit[6].bit_value); + $write("%b", byte[1].bit[5].bit_value); + $write("%b", byte[1].bit[4].bit_value); + $write("%b", byte[1].bit[3].bit_value); + $write("%b", byte[1].bit[2].bit_value); + $write("%b", byte[1].bit[1].bit_value); + $write("%b", byte[1].bit[0].bit_value); + $write(" "); + $write("%b", byte[0].bit[7].bit_value); + $write("%b", byte[0].bit[6].bit_value); + $write("%b", byte[0].bit[5].bit_value); + $write("%b", byte[0].bit[4].bit_value); + $write("%b", byte[0].bit[3].bit_value); + $write("%b", byte[0].bit[2].bit_value); + $write("%b", byte[0].bit[1].bit_value); + $write("%b", byte[0].bit[0].bit_value); + $write("\n"); + if (output_value == input_value) + $display("Test passed"); + else + $display("Test FAILED"); +end + +endmodule +`end_keywords diff --git a/ivtest/ivltests/genloop.v b/ivtest/ivltests/genloop.v new file mode 100644 index 000000000..1857babb9 --- /dev/null +++ b/ivtest/ivltests/genloop.v @@ -0,0 +1,40 @@ +/* + * This is a simple test of a generate loop. + */ +module main; + + parameter SIZE = 4; + wire [SIZE:0] cin; + reg [SIZE-1:0] a, b; + wire [SIZE-1:0] q; + + // This generates a ripple adder by using a generate loop to + // instantiate an array of half-adders. + + genvar i; + + assign cin[0] = 0; + for (i=0 ; i 0; --i) begin + initial array2[i] = i; +end + +for (genvar i = 0; i < 4; i++) begin + initial array3[i] = i; +end + +for (genvar i = 4; i > 0; i--) begin + initial array4[i] = i; +end + +initial begin + #1 failed = 0; + + for (i = 0; i < 4; ++i) begin + $display(array1[i]); + if (array1[i] !== i) failed = 1; + end + + for (i = 1; i < 5; ++i) begin + $display(array2[i]); + if (array2[i] !== i) failed = 1; + end + + for (i = 0; i < 4; ++i) begin + $display(array3[i]); + if (array3[i] !== i) failed = 1; + end + + for (i = 1; i < 5; ++i) begin + $display(array4[i]); + if (array4[i] !== i) failed = 1; + end + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/genvar_scopes.v b/ivtest/ivltests/genvar_scopes.v new file mode 100644 index 000000000..aa1972201 --- /dev/null +++ b/ivtest/ivltests/genvar_scopes.v @@ -0,0 +1,50 @@ +module genvar_scopes(); + +// This test is designed to check that genvars can be declared +// within a generate block and do not collide with genvars of +// the same name declared in the enclosing scope. + +genvar i; +genvar j; + +reg [1:0] a[1:0]; +wire [1:0] b[1:0]; +wire [1:0] c[1:0]; +wire [1:0] d[1:0]; + +for (i = 0; i < 2; i = i + 1) begin + for (j = 0; j < 2; j = j + 1) begin + assign b[i][j] = a[i][j]; + end +end + +for (i = 0; i < 2; i = i + 1) begin + genvar j; + for (j = 0; j < 2; j = j + 1) begin + assign c[i][j] = a[i][j]; + end +end + +for (j = 0; j < 2; j = j + 1) begin + genvar k; + for (k = 0; k < 2; k = k + 1) begin + assign d[j][k] = a[j][k]; + end +end + +initial begin + a[0] = 2'b01; + a[1] = 2'b10; + #1; + $display("%b %b", b[0], b[1]); + $display("%b %b", c[0], c[1]); + $display("%b %b", d[0], d[1]); + if ((b[0] === 2'b01) && (b[1] === 2'b10) + && (c[0] === 2'b01) && (c[1] === 2'b10) + && (d[0] === 2'b01) && (d[1] === 2'b10)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/gh161a.v b/ivtest/ivltests/gh161a.v new file mode 100644 index 000000000..e161bda49 --- /dev/null +++ b/ivtest/ivltests/gh161a.v @@ -0,0 +1,34 @@ + + +module test(); + typedef struct packed { + logic [31:0] sub_local; + } row_entry_t; + + typedef struct packed { + logic [31:0] row_local; + row_entry_t sub; + row_entry_t [1:0] sub_list; + } row_t; + + row_t main; + + initial begin + main.row_local = 32'hCAFE; + main.sub.sub_local = 32'h00000001; + main.sub_list[0].sub_local = 32'hACE; + main.sub_list[1].sub_local = 32'hECA; + $display("main=0x%08X", main); + if (main !== 128'h0000cafe0000000100000eca00000ace) begin + $display("FAILED -- main != 128'h0000cafe0000000100000eca00000ace"); + $finish; + end + $display("main.row_local=0x%08X", main.row_local); + $display("main.sub=0x%08X", main.sub); + //$display("0x%08X", main.sub.sub_local); + //$display("0x%08X", main.sub_list[0].sub_local); + $display("PASSED"); + $finish(); + end + +endmodule diff --git a/ivtest/ivltests/gh161b.v b/ivtest/ivltests/gh161b.v new file mode 100644 index 000000000..4e1a79bb6 --- /dev/null +++ b/ivtest/ivltests/gh161b.v @@ -0,0 +1,47 @@ + + +module test(); + typedef struct packed { + logic [31:0] sub_local; + } row_entry_t; + + typedef struct packed { + logic [31:0] row_local; + row_entry_t sub; + row_entry_t [1:0] sub_list; + } row_t; + + row_t main; + + initial begin + main.row_local = 32'hCAFE; + main.sub.sub_local = 32'h00000001; + main.sub_list[0].sub_local = 32'hACE; + main.sub_list[1].sub_local = 32'hECA; + $display("main=0x%08X", main); + if (main !== 128'h0000cafe0000000100000eca00000ace) begin + $display("FAILED -- main != 128'h0000cafe0000000100000eca00000ace"); + $finish; + end + $display("main.row_local=0x%08X", main.row_local); + $display("main.sub=0x%08X", main.sub); + $display("main.sub.sub_local=0x%08X", main.sub.sub_local); + if (main.sub.sub_local !== 32'h00000001) begin + $display("FAILED -- main.sub.sub_local != 32'h00000001"); + $finish; + end + $display("main.sub_list[0].sub_local=0x%08X", main.sub_list[0].sub_local); + if (main.sub_list[0].sub_local !== 32'hACE) begin + $display("FAILED -- main.sub.sub_local != 32'h00000ace"); + $finish; + end + $display("main.sub_list[1].sub_local=0x%08X", main.sub_list[1].sub_local); + if (main.sub_list[1].sub_local !== 32'hECA) begin + $display("FAILED -- main.sub.sub_local != 32'h00000eca"); + $finish; + end + $display("PASSED"); + $finish(); + end + +endmodule diff --git a/ivtest/ivltests/gxor.vhd b/ivtest/ivltests/gxor.vhd new file mode 100644 index 000000000..3499b53c6 --- /dev/null +++ b/ivtest/ivltests/gxor.vhd @@ -0,0 +1,43 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity gxor is +port (a, b: in std_logic; + z : out std_logic); +end gxor; + +architecture gxor_rtl of gxor is +begin + z <= a xor b; + +end architecture gxor_rtl; + +library ieee; +use ieee.std_logic_1164.all; + +entity gxor_reduce is + generic (half_width: integer := 4); + port (a: in std_logic_vector (2*half_width-1 downto 0); + ar: out std_logic); + +end gxor_reduce; + +architecture gxor_reduce_rtl of gxor_reduce is + +component gxor is + port (a, b: in std_logic; + z : out std_logic); +end component; + +--type path is array (0 to size/2) of std_logic; +signal x_int: std_logic_vector (2*half_width downto 0); + +begin + x_int(2*half_width) <= '0'; -- MSB +gen_xor: for i in 2*half_width downto 1 generate + each_gate: gxor port map (a => x_int(i), b => a(i-1), z => x_int(i-1) ); +end generate; + +ar <= x_int(0); + +end architecture gxor_reduce_rtl; diff --git a/ivtest/ivltests/hello1.v b/ivtest/ivltests/hello1.v new file mode 100644 index 000000000..74e930a43 --- /dev/null +++ b/ivtest/ivltests/hello1.v @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This trivial test has triggered problems with the empty parameter + * is encountered. The output should be: "Hello, World." + */ +module main; + initial begin + $display("Hello,",,"World."); + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/hier_ref_error.v b/ivtest/ivltests/hier_ref_error.v new file mode 100644 index 000000000..441ee5452 --- /dev/null +++ b/ivtest/ivltests/hier_ref_error.v @@ -0,0 +1,12 @@ +module hier_ref_error(); + +task my_task; + +begin:block +end + +endtask + +initial my_task.missing = 0; + +endmodule diff --git a/ivtest/ivltests/hierspace.v b/ivtest/ivltests/hierspace.v new file mode 100644 index 000000000..afad66cb0 --- /dev/null +++ b/ivtest/ivltests/hierspace.v @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// $Id: hierspace.v,v 1.1 2001/06/26 00:32:18 sib4 Exp $ +// $Log: hierspace.v,v $ +// Revision 1.1 2001/06/26 00:32:18 sib4 +// Two new tests for identifier parsing/elaboration +// +// +// IVL parser test for hierarchical names. + +module a; + wire b ; + m inst (b); + initial + begin + #1 inst.x <= 1'b0; + #1 inst .x <= 1'bx; + #1 inst. x <= 1'bz; + #1 inst . x <= 1'b1; + #1; + if (b === 1'b1) + $display("PASSED"); + else + $display("FAILED"); + end +endmodule +module m (x); + output x; + reg x; +endmodule diff --git a/ivtest/ivltests/ibit_test.v b/ivtest/ivltests/ibit_test.v new file mode 100644 index 000000000..f5ac060b6 --- /dev/null +++ b/ivtest/ivltests/ibit_test.v @@ -0,0 +1,95 @@ +// Three basic tests in here: +// 1. bit must be initialised before any initial or always block +// 2. assignments to (unsigned) bits with random numbers +// 3. assignments to (unsigned) bits with random values including X and Z + + +module ibit_test; + parameter TRIALS = 100; + parameter MAX = 32768; + + reg unsigned [14:0] ar; // should it be "reg unsigned [7:0] aw"? + reg unsigned [14:0] ar_xz; // same as above here? + reg unsigned [14:0] ar_expected; // and here + bit unsigned [14:0] bu; + bit unsigned [14:0] bu_xz; + + integer i; + + assign bu = ar; + assign bu_xz = ar_xz; + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 15'b0 | bu_xz != 15'b0) + begin + $display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz); + $finish; + end + // random numbers + for (i = 0; i< TRIALS; i = i+1) + begin + #1; + ar = {$random} % MAX; + #1; + if (bu !== ar) + begin + $display ("FAILED - incorrect assigment to bits: %b", bu); + $finish; + end + end + # 1; + // with 'x injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< TRIALS; i = i+1) + begin + #1; + ar = {$random} % MAX; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect assigment to bits (when 'x): %b", bu); + $finish; + end + end + # 1; + $display("PASSED"); + end + + // this returns X and Z states into bit random positions for a value + function [15:0] xz_inject (input reg unsigned [15:0] value); // should it be "input unsigned [15:0]" instead? + integer i, temp; + begin + temp = {$random} % MAX; + for (i=0; i<15; i=i+1) + begin + if (temp[i] == 1'b1) + begin + temp = $random % MAX; + if (temp <= 0) + value[i] = 1'bx; // 'x noise + else + value[i] = 1'bz; // 'z noise + end + end + xz_inject = value; + end + endfunction + + // this function returns bit positions with either X or Z to 0 for an input value + function [15:0] xz_expected (input reg unsigned [15:0] value_xz); // should it be "input unsigned [15:0] instead? + integer i; + begin + for (i=0; i<15; i=i+1) + begin + if (value_xz[i] === 1'bx || value_xz[i] === 1'bz ) + value_xz[i] = 1'b0; // forced to zero + end + xz_expected = value_xz; + end + endfunction + + +endmodule diff --git a/ivtest/ivltests/ibyte_test.v b/ivtest/ivltests/ibyte_test.v new file mode 100644 index 000000000..00b3ff06b --- /dev/null +++ b/ivtest/ivltests/ibyte_test.v @@ -0,0 +1,94 @@ +// Three basic tests in here: +// 1. byte must be initialised before any initial or always block +// 2. assignments to (unsigned) bytes with random numbers +// 3. assignments to (unsigned) bytes with random values including X and Z + + +module ibyte_test; + parameter TRIALS = 100; + parameter MAX = 256; + reg [7:0] ar; // should it be "reg unsigned [7:0] aw"? + reg [7:0] ar_xz; // same as above here? + reg [7:0] ar_expected; // and here + byte unsigned bu; + byte unsigned bu_xz; + + integer i; + + assign bu = ar; + assign bu_xz = ar_xz; + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 8'b0 | bu_xz != 8'b0) + begin + $display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz); + $finish; + end + // random numbers + for (i = 0; i< TRIALS; i = i+1) + begin + #1; + ar = {$random} % MAX; + #1; + if (bu !== ar) + begin + $display ("FAILED - incorrect assigment to byte: %b", bu); + $finish; + end + end + # 1; + // with 'x injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< TRIALS; i = i+1) + begin + #1; + ar = {$random} % MAX; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect assigment to byte (when 'x): %b", bu); + $finish; + end + end + # 1; + $display("PASSED"); + end + + // this returns X and Z states into bit random positions for a value + function [7:0] xz_inject (input [7:0] value); // should it be "input unsigned [7:0]" instead? + integer i, temp; + begin + temp = {$random} % MAX; + for (i=0; i<8; i=i+1) + begin + if (temp[i] == 1'b1) + begin + temp = $random % MAX; + if (temp <= 0) + value[i] = 1'bx; // 'x noise + else + value[i] = 1'bz; // 'z noise + end + end + xz_inject = value; + end + endfunction + + // this function returns bit positions with either X or Z to 0 for an input value + function [7:0] xz_expected (input [7:0] value_xz); // should it be "input unsigned [7:0] instead? + integer i; + begin + for (i=0; i<8; i=i+1) + begin + if (value_xz[i] === 1'bx || value_xz[i] === 1'bz ) + value_xz[i] = 1'b0; // forced to zero + end + xz_expected = value_xz; + end + endfunction + + +endmodule diff --git a/ivtest/ivltests/idiv1.v b/ivtest/ivltests/idiv1.v new file mode 100644 index 000000000..e32840498 --- /dev/null +++ b/ivtest/ivltests/idiv1.v @@ -0,0 +1,99 @@ +// +// Copyright (c) 1999 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// Test the divide (/) operator + +module top () ; + + reg [7:0] a, b, result; + wire [7:0] wa, wb, wresult; + + assign wa = a; + assign wb = b; + assign wresult = wa / wb; + +always @(a or b) + result = a / b; + +initial begin + #1 a = 0; b = 1; + # 1; + if( result !== 8'b0) + begin + $display("FAILED - Divide 0/1 reg assign failed - is %b",result); + $finish; + end + if( wresult !== 8'b0) + begin + $display("FAILED - Divide 0/1 wire assign failed - is %b",wresult); + $finish; + end + + #1 a = 1; + #1 if( result !== 8'b1) + begin + $display("FAILED - Divide 1/1 reg assign failed - is %b",result); + $finish; + end + if( wresult !== 8'b1) + begin + $display("FAILED - Divide 1/1 wire assign failed - is %b",wresult); + $finish; + end + + #1 a = 5; b = 2; + #1 if( result !== 8'd2) + begin + $display("FAILED - Divide 5/2 reg assign failed - is %b",result); + $finish; + end + if( wresult !== 8'd2) + begin + $display("FAILED - Divide 5/2 wire assign failed - is %b",wresult); + $finish; + end + + #1 a = 8'd255; b = 5; + #1 if( result !== 51) + begin + $display("FAILED - Divide 255/5 reg assign failed - is %b",result); + $finish; + end + if( wresult !== 51) + begin + $display("FAILED - Divide 255/5 wire assign failed - is %b",wresult); + $finish; + end + + #1 a = 1'bx; b = 3; + #1 if( result !== 8'bxxxx_xxxx) + begin + $display("FAILED - Divide x/3 reg assign failed - is %b",result); + $finish; + end + if( wresult !== 8'bxxxx_xxxx) + begin + $display("FAILED - Divide x/3 wire assign failed - is %b",wresult); + $finish; + end + + $display("PASSED"); + +end + +endmodule diff --git a/ivtest/ivltests/idiv2.v b/ivtest/ivltests/idiv2.v new file mode 100644 index 000000000..3e099da00 --- /dev/null +++ b/ivtest/ivltests/idiv2.v @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This is a check of the implementation of division and multiplication + * within more complex expressions. + */ +module test; + task mod; + input [31:0] a; + input [15:0] b; + output [31:0] out; + begin + out = a-(a/b)*b; + end + endtask + + reg [31:0] result,c, nl; + initial begin + c = 13; nl = 3; + mod(c, nl, result); + $display("13 %% 3 = %d", result); + if (result !== 32'h00_00_00_01) begin + $display("FAILED -- result is %b", result); + $finish; + end + + $display("PASSED"); + + end +endmodule diff --git a/ivtest/ivltests/idiv3.v b/ivtest/ivltests/idiv3.v new file mode 100644 index 000000000..528f1a55a --- /dev/null +++ b/ivtest/ivltests/idiv3.v @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2002 Simon Denman + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// +// File: DivBug.v +// Author: Simon Denman +// Created: 28/3/02 +// Description: integer division bug test + +module DivBug ; + + integer intX, intY; + + initial + begin + intX = -8; + intY = intX / 8; + $display("%5d %5d", intX, intY); + end + +endmodule diff --git a/ivtest/ivltests/if_part_no_else.v b/ivtest/ivltests/if_part_no_else.v new file mode 100644 index 000000000..485f8677e --- /dev/null +++ b/ivtest/ivltests/if_part_no_else.v @@ -0,0 +1,62 @@ + + +module test + (output reg [1:0] foo, + input wire in0, en0, + input wire in1, en1 + /* */); + + localparam foo_default = 2'b00; + always @* + begin + foo = foo_default; + if (en0) foo[0] = in0; + if (en1) foo[1] = in1; + end + +endmodule // test + +module main; + + wire [1:0] foo; + reg in0, en0; + reg in1, en1; + + test dut (.foo(foo), .in0(in0), .in1(in1), .en0(en0), .en1(en1)); + + initial begin + in0 = 1; + in1 = 1; + + en0 = 0; + en1 = 0; + + #1 if (foo !== 2'b00) begin + $display("FAILED -- foo=%b, in=%b%b, en=%b%b", foo, in1, in0, en1, en0); + $finish; + end + + en0 = 1; + #1 if (foo !== 2'b01) begin + $display("FAILED -- foo=%b, in=%b%b, en=%b%b", foo, in1, in0, en1, en0); + $finish; + end + + en0 = 0; + en1 = 1; + #1 if (foo !== 2'b10) begin + $display("FAILED -- foo=%b, in=%b%b, en=%b%b", foo, in1, in0, en1, en0); + $finish; + end + + en0 = 1; + en1 = 1; + #1 if (foo !== 2'b11) begin + $display("FAILED -- foo=%b, in=%b%b, en=%b%b", foo, in1, in0, en1, en0); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/if_part_no_else2.v b/ivtest/ivltests/if_part_no_else2.v new file mode 100644 index 000000000..3cc39eaf0 --- /dev/null +++ b/ivtest/ivltests/if_part_no_else2.v @@ -0,0 +1,97 @@ + + +module test + (output reg [1:0] foo, + input wire [1:0] addr, + input wire in0, in1, + input wire en0, en1 + /* */); + + localparam foo_default = 2'b00; + always @* + begin + foo = foo_default; + case (addr) + 0: if (en0) foo[0] = in0; + 1: if (en1) foo[1] = in1; + 2: foo = {in1, in0}; + default: foo = 0; + endcase + end + +endmodule // test + +module main; + + wire [1:0] foo; + reg [1:0] addr; + reg in0, in1; + reg en0, en1; + + test dut(.foo(foo), .addr(addr), .in0(in0), .in1(in1), .en0(en0), .en1(en1)); + + initial begin + in0 = 1; + in1 = 1; + en0 = 1; + en1 = 1; + + addr = 3; + #1 if (foo !== 2'b00) begin + $display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b", + foo, in1, in0, en1, en0, addr); + $finish; + end + + addr = 0; + #1 if (foo !== 2'b01) begin + $display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr); + $finish; + end + + addr = 1; + #1 if (foo !== 2'b10) begin + $display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr); + $finish; + end + + addr = 2; + #1 if (foo !== 2'b11) begin + $display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr); + $finish; + end + + en0 = 0; + en1 = 0; + + addr = 3; + #1 if (foo !== 2'b00) begin + $display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b", + foo, in1, in0, en1, en0, addr); + $finish; + end + + addr = 0; + #1 if (foo !== 2'b00) begin + $display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b", + foo, in1, in0, en1, en0, addr); + $finish; + end + + addr = 1; + #1 if (foo !== 2'b00) begin + $display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr); + $finish; + end + + addr = 2; + #1 if (foo !== 2'b11) begin + $display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b", + foo, in1, in0, en1, en0, addr); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/ifdef1.v b/ivtest/ivltests/ifdef1.v new file mode 100644 index 000000000..135a2dd68 --- /dev/null +++ b/ivtest/ivltests/ifdef1.v @@ -0,0 +1,47 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Basic ifdef test +// + + +module ifdef1; + +reg error ; + +`ifdef NOCODE +initial + begin + #20; + error = 1; + #20; + end +`endif + +initial + begin + #1; + error = 0; + #40; + if(error == 0) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule // main diff --git a/ivtest/ivltests/ifdef2.v b/ivtest/ivltests/ifdef2.v new file mode 100644 index 000000000..73aa2dd34 --- /dev/null +++ b/ivtest/ivltests/ifdef2.v @@ -0,0 +1,49 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Basic ifdef test with define +// + + +`define NOCODE +module ifdef2; + +reg error ; + + +`ifdef NOCODE +initial + begin + #20; + error = 0; + #20; + end +`endif + +initial + begin + #1; + error = 1; + #40; + if(error == 0) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule // main diff --git a/ivtest/ivltests/ifdef3.v b/ivtest/ivltests/ifdef3.v new file mode 100644 index 000000000..f9096665f --- /dev/null +++ b/ivtest/ivltests/ifdef3.v @@ -0,0 +1,50 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Compound ifdef (two) with interior not defined +// + + +`define DOUBLE +module ifdef1; + +reg error ; + +`ifdef DOUBLE +`ifdef NOCODE +initial + begin + #20; + error = 1; + #20; + end +`endif // NOCODE +`endif // DOUBLE + +initial + begin + #1; + error = 0; + #40; + if(error == 0) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule // main diff --git a/ivtest/ivltests/ifdef4.v b/ivtest/ivltests/ifdef4.v new file mode 100644 index 000000000..ef2c4d8f5 --- /dev/null +++ b/ivtest/ivltests/ifdef4.v @@ -0,0 +1,51 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Compount ifdef test with 2 defines +// + + +`define DOUBLE +`define NOCODE +module ifdef2; + +reg error ; + + +`ifdef DOUBLE +`ifdef NOCODE +initial + begin + #20; + error = 0; + #20; + end +`endif // NOCODE +`endif // DOUBLE +initial + begin + #1; + error = 1; + #40; + if(error == 0) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule // main diff --git a/ivtest/ivltests/ifdef_fail.v b/ivtest/ivltests/ifdef_fail.v new file mode 100644 index 000000000..5ea2701b5 --- /dev/null +++ b/ivtest/ivltests/ifdef_fail.v @@ -0,0 +1,11 @@ +module if_fail_test(); + +`ifdef +`ifndef +`elsif +`else +`endif + + initial $display("FAILED"); + +endmodule diff --git a/ivtest/ivltests/iint_test.v b/ivtest/ivltests/iint_test.v new file mode 100644 index 000000000..ee5c02d55 --- /dev/null +++ b/ivtest/ivltests/iint_test.v @@ -0,0 +1,94 @@ +// Three basic tests in here: +// 1. byte must be initialised before any initial or always block +// 2. assignments to (unsigned) bytes with random numbers +// 3. assignments to (unsigned) bytes with random values including X and Z + + +module ibyte_test; + parameter TRIALS = 100; + parameter MAX = 'h7fffffff; + reg [31:0] ar; // should it be "reg unsigned [7:0] aw"? + reg [31:0] ar_xz; // same as above here? + reg [31:0] ar_expected; // and here + int unsigned bu; + int unsigned bu_xz; + + integer i; + + assign bu = ar; + assign bu_xz = ar_xz; + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 32'b0 | bu_xz != 32'b0) + begin + $display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz); + $finish; + end + // random numbers + for (i = 0; i< TRIALS; i = i+1) + begin + #1; + ar = {$random} % MAX; + #1; + if (bu !== ar) + begin + $display ("FAILED - incorrect assigment to byte: %b", bu); + $finish; + end + end + # 1; + // with 'x injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< TRIALS; i = i+1) + begin + #1; + ar = {$random} % MAX; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect assigment to byte (when 'x): %b", bu); + $finish; + end + end + # 1; + $display("PASSED"); + end + + // this returns X and Z states into bit random positions for a value + function [31:0] xz_inject (input [31:0] value); // should it be "input unsigned [7:0]" instead? + integer i, temp; + begin + temp = {$random} % MAX; + for (i=0; i<32; i=i+1) + begin + if (temp[i] == 1'b1) + begin + temp = $random % MAX; + if (temp <= 0) + value[i] = 1'bx; // 'x noise + else + value[i] = 1'bz; // 'z noise + end + end + xz_inject = value; + end + endfunction + + // this function returns bit positions with either X or Z to 0 for an input value + function [31:0] xz_expected (input [31:0] value_xz); // should it be "input unsigned [7:0] instead? + integer i; + begin + for (i=0; i<32; i=i+1) + begin + if (value_xz[i] === 1'bx || value_xz[i] === 1'bz ) + value_xz[i] = 1'b0; // forced to zero + end + xz_expected = value_xz; + end + endfunction + + +endmodule diff --git a/ivtest/ivltests/ilongint_test.v b/ivtest/ivltests/ilongint_test.v new file mode 100644 index 000000000..f1d64c9aa --- /dev/null +++ b/ivtest/ivltests/ilongint_test.v @@ -0,0 +1,94 @@ +// Three basic tests in here: +// 1. byte must be initialised before any initial or always block +// 2. assignments to (unsigned) bytes with random numbers +// 3. assignments to (unsigned) bytes with random values including X and Z + + +module ibyte_test; + parameter TRIALS = 100; + parameter MAX = 'h7fffffff_ffffffff; + reg [63:0] ar; // should it be "reg unsigned [7:0] aw"? + reg [63:0] ar_xz; // same as above here? + reg [63:0] ar_expected; // and here + longint unsigned bu; + longint unsigned bu_xz; + + integer i; + + assign bu = ar; + assign bu_xz = ar_xz; + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 64'b0 | bu_xz != 64'b0) + begin + $display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz); + $finish; + end + // random numbers + for (i = 0; i< TRIALS; i = i+1) + begin + #1; + ar = {$random} % MAX; + #1; + if (bu !== ar) + begin + $display ("FAILED - incorrect assigment to byte: %b", bu); + $finish; + end + end + # 1; + // with 'x injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< TRIALS; i = i+1) + begin + #1; + ar = {$random} % MAX; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect assigment to byte (when 'x): %b", bu); + $finish; + end + end + # 1; + $display("PASSED"); + end + + // this returns X and Z states into bit random positions for a value + function [63:0] xz_inject (input [63:0] value); // should it be "input unsigned [7:0]" instead? + integer i, temp; + begin + temp = {$random} % MAX; + for (i=0; i<64; i=i+1) + begin + if (temp[i] == 1'b1) + begin + temp = $random % MAX; + if (temp <= 0) + value[i] = 1'bx; // 'x noise + else + value[i] = 1'bz; // 'z noise + end + end + xz_inject = value; + end + endfunction + + // this function returns bit positions with either X or Z to 0 for an input value + function [63:0] xz_expected (input [63:0] value_xz); // should it be "input unsigned [7:0] instead? + integer i; + begin + for (i=0; i<64; i=i+1) + begin + if (value_xz[i] === 1'bx || value_xz[i] === 1'bz ) + value_xz[i] = 1'b0; // forced to zero + end + xz_expected = value_xz; + end + endfunction + + +endmodule diff --git a/ivtest/ivltests/implicit-port1.v b/ivtest/ivltests/implicit-port1.v new file mode 100644 index 000000000..f1312e93b --- /dev/null +++ b/ivtest/ivltests/implicit-port1.v @@ -0,0 +1,23 @@ +// test basic implicit ports work +module m(input a, output b, output c); +assign b = a; +assign c = ~a; +endmodule + +module top; +reg a; +wire b, d; +m foo(.a, .b, .c(d)); + +initial begin + a = 0; + #1 if (b !== a || d !== ~a) begin + $display("FAILED -- a=%b, b=%b, d=%b", a, b, d); + end + #1 a = 1; + #1 if (b !== a || d !== ~a) begin + $display("FAILED -- a=%b, b=%b, d=%b", a, b, d); + end + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/implicit-port2.v b/ivtest/ivltests/implicit-port2.v new file mode 100644 index 000000000..c209964d3 --- /dev/null +++ b/ivtest/ivltests/implicit-port2.v @@ -0,0 +1,10 @@ +// test that if the signal doesn't exist, an error is thrown +module m(input a, output b); +assign b = a; +endmodule + +module top; +reg a; +// wire b; +m foo(.a, .b); +endmodule diff --git a/ivtest/ivltests/implicit-port3.v b/ivtest/ivltests/implicit-port3.v new file mode 100644 index 000000000..082d4da5b --- /dev/null +++ b/ivtest/ivltests/implicit-port3.v @@ -0,0 +1,11 @@ +// test that if the port doesn't exist, an error is thrown +module m(input a, output b); +assign b = a; +endmodule + +module top; +reg a; +wire b; +wire c; +m foo(.a, .b, .c); +endmodule diff --git a/ivtest/ivltests/implicit-port4.v b/ivtest/ivltests/implicit-port4.v new file mode 100644 index 000000000..5ae8b2e39 --- /dev/null +++ b/ivtest/ivltests/implicit-port4.v @@ -0,0 +1,23 @@ +// test that .* implicit ports work +module m(input a, output b, output c); +assign b = a; +assign c = ~a; +endmodule + +module top; +reg a; +wire b, d; +m foo(.*, .c(d)); + +initial begin + a = 0; + #1 if (b !== a || d !== ~a) begin + $display("FAILED -- a=%b, b=%b, d=%b", a, b, d); + end + #1 a = 1; + #1 if (b !== a || d !== ~a) begin + $display("FAILED -- a=%b, b=%b, d=%b", a, b, d); + end + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/implicit-port5.v b/ivtest/ivltests/implicit-port5.v new file mode 100644 index 000000000..8ca635679 --- /dev/null +++ b/ivtest/ivltests/implicit-port5.v @@ -0,0 +1,25 @@ +// test that .* implicit ports work with override +module m(input a, output b, output c); +assign b = a; +assign c = ~a; +endmodule + +module top; +reg a; +reg x; +wire b, d; +m foo(.a(x), .*, .c(d)); + +initial begin + a = 0; + x = 1; + #1 if (b !== x || d !== ~x) begin + $display("FAILED -- a=%b, x=%b, b=%b, d=%b", a, x, b, d); + end + #1 a = 1; + #1 if (b !== x || d !== ~x) begin + $display("FAILED -- a=%b, x=%b, b=%b, d=%b", a, x, b, d); + end + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/implicit-port6.v b/ivtest/ivltests/implicit-port6.v new file mode 100644 index 000000000..1881f8e03 --- /dev/null +++ b/ivtest/ivltests/implicit-port6.v @@ -0,0 +1,10 @@ +// test that if the signal doesn't exist, an error is thrown +module m(input a, output b); +assign b = a; +endmodule + +module top; +reg a; +// wire b; +m foo(.*); +endmodule diff --git a/ivtest/ivltests/implicit-port7.v b/ivtest/ivltests/implicit-port7.v new file mode 100644 index 000000000..a90563666 --- /dev/null +++ b/ivtest/ivltests/implicit-port7.v @@ -0,0 +1,32 @@ +// test that .* implicit ports work with override +module m(input a, output b, output c, output d, output e); +assign b = a; +assign c = ~a; +assign d = ~a; +assign e = ~a; +endmodule + +module top; +reg a; +reg x; +wire b, d; +m foo(.a(x), .e(), .*, .c(d), .d()); +m foo2(.a(x), .d(), .*, .c(), .e()); +m foo3(.a(x), .*, .d(), .c(), .e()); +m foo4(.*, .a(x), .d(), .c(), .e()); +m foo5(.a(x), .d(), .c(), .*, .e()); +m foo6(.a(x), .d(), .c(), .e(), .*); + +initial begin + a = 0; + x = 1; + #1 if (b !== x || d !== ~x) begin + $display("FAILED -- a=%b, x=%b, b=%b, d=%b", a, x, b, d); + end + #1 a = 1; + #1 if (b !== x || d !== ~x) begin + $display("FAILED -- a=%b, x=%b, b=%b, d=%b", a, x, b, d); + end + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/implicit1.v b/ivtest/ivltests/implicit1.v new file mode 100644 index 000000000..ea04ca965 --- /dev/null +++ b/ivtest/ivltests/implicit1.v @@ -0,0 +1,40 @@ +/* + * From PR#379 + */ +`define IDLE 2'b00 +`define COUNT 2'b01 +`define DONE 2'b10 + +module Counter56 (POR, CLK, VoltageOK, ChargeDone ); +input POR; +input CLK; +input VoltageOK; +output ChargeDone; + +reg [1:0] CounterState, nextCounterState; + +wire [8:0] nextMinuteCounter; + +always @(posedge CLK or negedge POR) + if (!POR) + CounterState = 2'b00; + else + CounterState = nextCounterState; + +always @(VoltageOK or CounterReset) // CounterReset should make an error + casez (CounterState) + `IDLE: begin + nextCounterState = (VoltageOK) ? `COUNT : `IDLE; + end + `COUNT: begin + nextCounterState = (VoltageOK) ? `COUNT : `IDLE; + end + `DONE: begin + nextCounterState = `DONE; + end + default: begin + nextCounterState = 2'bxx; + end + endcase + +endmodule diff --git a/ivtest/ivltests/implicit_cast1.v b/ivtest/ivltests/implicit_cast1.v new file mode 100644 index 000000000..183e6b676 --- /dev/null +++ b/ivtest/ivltests/implicit_cast1.v @@ -0,0 +1,130 @@ +// Test implicit casts during procedural blocking assignments. + +module implicit_cast(); + +real src_r; + +bit unsigned [7:0] src_u2; +bit signed [7:0] src_s2; + +logic unsigned [7:0] src_u4; +logic signed [7:0] src_s4; + +logic unsigned [7:0] src_ux; +logic signed [7:0] src_sx; + +real dst_r; + +bit unsigned [3:0] dst_u2s; +bit signed [3:0] dst_s2s; + +bit unsigned [11:0] dst_u2l; +bit signed [11:0] dst_s2l; + +logic unsigned [3:0] dst_u4s; +logic signed [3:0] dst_s4s; + +logic unsigned [11:0] dst_u4l; +logic signed [11:0] dst_s4l; + +bit failed; + +initial begin + failed = 0; + + src_r = -7; + src_u2 = 7; + src_s2 = -7; + src_u4 = 7; + src_s4 = -7; + src_ux = 8'bx0z00111; + src_sx = 8'bx0z00111; + + $display("cast to real"); + dst_r = src_r; $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + dst_r = src_u2; $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + dst_r = src_s2; $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + dst_r = src_u4; $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + dst_r = src_s4; $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + dst_r = src_ux; $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + dst_r = src_sx; $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + + $display("cast to small unsigned bit"); + dst_u2s = src_r; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + dst_u2s = src_u2; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + dst_u2s = src_s2; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + dst_u2s = src_u4; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + dst_u2s = src_s4; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + dst_u2s = src_ux; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + dst_u2s = src_sx; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + + $display("cast to small signed bit"); + dst_s2s = src_r; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + dst_s2s = src_u2; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + dst_s2s = src_s2; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + dst_s2s = src_u4; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + dst_s2s = src_s4; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + dst_s2s = src_ux; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + dst_s2s = src_sx; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + + $display("cast to large unsigned bit"); + dst_u2l = src_r; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + dst_u2l = src_u2; $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1; + dst_u2l = src_s2; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + dst_u2l = src_u4; $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1; + dst_u2l = src_s4; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + dst_u2l = src_ux; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1; + dst_u2l = src_sx; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1; + + $display("cast to large signed bit"); + dst_s2l = src_r; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + dst_s2l = src_u2; $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1; + dst_s2l = src_s2; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + dst_s2l = src_u4; $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1; + dst_s2l = src_s4; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + dst_s2l = src_ux; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1; + dst_s2l = src_sx; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1; + + $display("cast to small unsigned logic"); + dst_u4s = src_r; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + dst_u4s = src_u2; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + dst_u4s = src_s2; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + dst_u4s = src_u4; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + dst_u4s = src_s4; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + dst_u4s = src_ux; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + dst_u4s = src_sx; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + + $display("cast to small signed logic"); + dst_s4s = src_r; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + dst_s4s = src_u2; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + dst_s4s = src_s2; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + dst_s4s = src_u4; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + dst_s4s = src_s4; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + dst_s4s = src_ux; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + dst_s4s = src_sx; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + + $display("cast to large unsigned logic"); + dst_u4l = src_r; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + dst_u4l = src_u2; $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1; + dst_u4l = src_s2; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + dst_u4l = src_u4; $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1; + dst_u4l = src_s4; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + dst_u4l = src_ux; $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1; + dst_u4l = src_sx; $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1; + + $display("cast to large signed logic"); + dst_s4l = src_r; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + dst_s4l = src_u2; $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1; + dst_s4l = src_s2; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + dst_s4l = src_u4; $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1; + dst_s4l = src_s4; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + dst_s4l = src_ux; $display("%b", dst_s4l); if (dst_s4l !== 12'b0000x0z00111) failed = 1; + dst_s4l = src_sx; $display("%b", dst_s4l); if (dst_s4l !== 12'bxxxxx0z00111) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/implicit_cast10.v b/ivtest/ivltests/implicit_cast10.v new file mode 100644 index 000000000..e2389e56c --- /dev/null +++ b/ivtest/ivltests/implicit_cast10.v @@ -0,0 +1,175 @@ +// Test implicit casts during task input assignments. + +module implicit_cast(); + +real src_r; + +bit unsigned [7:0] src_u2; +bit signed [7:0] src_s2; + +logic unsigned [7:0] src_u4; +logic signed [7:0] src_s4; + +logic unsigned [7:0] src_ux; +logic signed [7:0] src_sx; + +real dst_r; + +bit unsigned [3:0] dst_u2s; +bit signed [3:0] dst_s2s; + +bit unsigned [11:0] dst_u2l; +bit signed [11:0] dst_s2l; + +logic unsigned [3:0] dst_u4s; +logic signed [3:0] dst_s4s; + +logic unsigned [11:0] dst_u4l; +logic signed [11:0] dst_s4l; + +task cp_r(output real dst, + input real src); + dst = src; +endtask + +task cp_u2s(output bit unsigned [3:0] dst, + input bit unsigned [3:0] src); + dst = src; +endtask + +task cp_s2s(output bit signed [3:0] dst, + input bit signed [3:0] src); + dst = src; +endtask + +task cp_u2l(output bit unsigned [11:0] dst, + input bit unsigned [11:0] src); + dst = src; +endtask + +task cp_s2l(output bit signed [11:0] dst, + input bit signed [11:0] src); + dst = src; +endtask + +task cp_u4s(output logic unsigned [3:0] dst, + input logic unsigned [3:0] src); + dst = src; +endtask + +task cp_s4s(output logic signed [3:0] dst, + input logic signed [3:0] src); + dst = src; +endtask + +task cp_u4l(output logic unsigned [11:0] dst, + input logic unsigned [11:0] src); + dst = src; +endtask + +task cp_s4l(output logic signed [11:0] dst, + input logic signed [11:0] src); + dst = src; +endtask + +bit failed; + +initial begin + failed = 0; + + src_r = -7; + src_u2 = 7; + src_s2 = -7; + src_u4 = 7; + src_s4 = -7; + src_ux = 8'bx0z00111; + src_sx = 8'bx0z00111; + + $display("cast to real"); + cp_r(dst_r, src_r); $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + cp_r(dst_r, src_u2); $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + cp_r(dst_r, src_s2); $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + cp_r(dst_r, src_u4); $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + cp_r(dst_r, src_s4); $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + cp_r(dst_r, src_ux); $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + cp_r(dst_r, src_sx); $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + + $display("cast to small unsigned bit"); + cp_u2s(dst_u2s, src_r); $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + cp_u2s(dst_u2s, src_u2); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + cp_u2s(dst_u2s, src_s2); $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + cp_u2s(dst_u2s, src_u4); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + cp_u2s(dst_u2s, src_s4); $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + cp_u2s(dst_u2s, src_ux); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + cp_u2s(dst_u2s, src_sx); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + + $display("cast to small signed bit"); + cp_s2s(dst_s2s, src_r); $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + cp_s2s(dst_s2s, src_u2); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + cp_s2s(dst_s2s, src_s2); $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + cp_s2s(dst_s2s, src_u4); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + cp_s2s(dst_s2s, src_s4); $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + cp_s2s(dst_s2s, src_ux); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + cp_s2s(dst_s2s, src_sx); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + + $display("cast to large unsigned bit"); + cp_u2l(dst_u2l, src_r); $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + cp_u2l(dst_u2l, src_u2); $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1; + cp_u2l(dst_u2l, src_s2); $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + cp_u2l(dst_u2l, src_u4); $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1; + cp_u2l(dst_u2l, src_s4); $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + cp_u2l(dst_u2l, src_ux); $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1; + cp_u2l(dst_u2l, src_sx); $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1; + + $display("cast to large signed bit"); + cp_s2l(dst_s2l, src_r); $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + cp_s2l(dst_s2l, src_u2); $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1; + cp_s2l(dst_s2l, src_s2); $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + cp_s2l(dst_s2l, src_u4); $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1; + cp_s2l(dst_s2l, src_s4); $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + cp_s2l(dst_s2l, src_ux); $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1; + cp_s2l(dst_s2l, src_sx); $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1; + + $display("cast to small unsigned logic"); + cp_u4s(dst_u4s, src_r); $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + cp_u4s(dst_u4s, src_u2); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + cp_u4s(dst_u4s, src_s2); $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + cp_u4s(dst_u4s, src_u4); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + cp_u4s(dst_u4s, src_s4); $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + cp_u4s(dst_u4s, src_ux); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + cp_u4s(dst_u4s, src_sx); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + + $display("cast to small signed logic"); + cp_s4s(dst_s4s, src_r); $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + cp_s4s(dst_s4s, src_u2); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + cp_s4s(dst_s4s, src_s2); $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + cp_s4s(dst_s4s, src_u4); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + cp_s4s(dst_s4s, src_s4); $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + cp_s4s(dst_s4s, src_ux); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + cp_s4s(dst_s4s, src_sx); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + + $display("cast to large unsigned logic"); + cp_u4l(dst_u4l, src_r); $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + cp_u4l(dst_u4l, src_u2); $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1; + cp_u4l(dst_u4l, src_s2); $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + cp_u4l(dst_u4l, src_u4); $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1; + cp_u4l(dst_u4l, src_s4); $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + cp_u4l(dst_u4l, src_ux); $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1; + cp_u4l(dst_u4l, src_sx); $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1; + + $display("cast to large signed logic"); + cp_s4l(dst_s4l, src_r); $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + cp_s4l(dst_s4l, src_u2); $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1; + cp_s4l(dst_s4l, src_s2); $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + cp_s4l(dst_s4l, src_u4); $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1; + cp_s4l(dst_s4l, src_s4); $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + cp_s4l(dst_s4l, src_ux); $display("%b", dst_s4l); if (dst_s4l !== 12'b0000x0z00111) failed = 1; + cp_s4l(dst_s4l, src_sx); $display("%b", dst_s4l); if (dst_s4l !== 12'bxxxxx0z00111) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/implicit_cast11.v b/ivtest/ivltests/implicit_cast11.v new file mode 100644 index 000000000..9acb7a675 --- /dev/null +++ b/ivtest/ivltests/implicit_cast11.v @@ -0,0 +1,155 @@ +// Test implicit casts during task output assignments. + +module implicit_cast(); + +real src_r; + +bit unsigned [7:0] src_u2; +bit signed [7:0] src_s2; + +logic unsigned [7:0] src_u4; +logic signed [7:0] src_s4; + +logic unsigned [7:0] src_ux; +logic signed [7:0] src_sx; + +real dst_r; + +bit unsigned [3:0] dst_u2s; +bit signed [3:0] dst_s2s; + +bit unsigned [11:0] dst_u2l; +bit signed [11:0] dst_s2l; + +logic unsigned [3:0] dst_u4s; +logic signed [3:0] dst_s4s; + +logic unsigned [11:0] dst_u4l; +logic signed [11:0] dst_s4l; + +task cp_r(output real dst, + input real src); + dst = src; +endtask + +task cp_u2(output bit unsigned [7:0] dst, + input bit unsigned [7:0] src); + dst = src; +endtask + +task cp_s2(output bit signed [7:0] dst, + input bit signed [7:0] src); + dst = src; +endtask + +task cp_u4(output logic unsigned [7:0] dst, + input logic unsigned [7:0] src); + dst = src; +endtask + +task cp_s4(output logic signed [7:0] dst, + input logic signed [7:0] src); + dst = src; +endtask + +bit failed; + +initial begin + failed = 0; + + src_r = -7; + src_u2 = 7; + src_s2 = -7; + src_u4 = 7; + src_s4 = -7; + src_ux = 8'bx0z00111; + src_sx = 8'bx0z00111; + + $display("cast to real"); + cp_r (dst_r, src_r); $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + cp_u2(dst_r, src_u2); $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + cp_s2(dst_r, src_s2); $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + cp_u4(dst_r, src_u4); $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + cp_s4(dst_r, src_s4); $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + cp_u4(dst_r, src_ux); $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + cp_s4(dst_r, src_sx); $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + + $display("cast to small unsigned bit"); + cp_r (dst_u2s, src_r); $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + cp_u2(dst_u2s, src_u2); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + cp_s2(dst_u2s, src_s2); $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + cp_u4(dst_u2s, src_u4); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + cp_s4(dst_u2s, src_s4); $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + cp_u4(dst_u2s, src_ux); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + cp_s4(dst_u2s, src_sx); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + + $display("cast to small signed bit"); + cp_r (dst_s2s, src_r); $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + cp_u2(dst_s2s, src_u2); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + cp_s2(dst_s2s, src_s2); $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + cp_u4(dst_s2s, src_u4); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + cp_s4(dst_s2s, src_s4); $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + cp_u4(dst_s2s, src_ux); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + cp_s4(dst_s2s, src_sx); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + + $display("cast to large unsigned bit"); + cp_r (dst_u2l, src_r); $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + cp_u2(dst_u2l, src_u2); $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1; + cp_s2(dst_u2l, src_s2); $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + cp_u4(dst_u2l, src_u4); $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1; + cp_s4(dst_u2l, src_s4); $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + cp_u4(dst_u2l, src_ux); $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1; + cp_s4(dst_u2l, src_sx); $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1; + + $display("cast to large signed bit"); + cp_r (dst_s2l, src_r); $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + cp_u2(dst_s2l, src_u2); $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1; + cp_s2(dst_s2l, src_s2); $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + cp_u4(dst_s2l, src_u4); $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1; + cp_s4(dst_s2l, src_s4); $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + cp_u4(dst_s2l, src_ux); $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1; + cp_s4(dst_s2l, src_sx); $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1; + + $display("cast to small unsigned logic"); + cp_r (dst_u4s, src_r); $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + cp_u2(dst_u4s, src_u2); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + cp_s2(dst_u4s, src_s2); $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + cp_u4(dst_u4s, src_u4); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + cp_s4(dst_u4s, src_s4); $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + cp_u4(dst_u4s, src_ux); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + cp_s4(dst_u4s, src_sx); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + + $display("cast to small signed logic"); + cp_r (dst_s4s, src_r); $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + cp_u2(dst_s4s, src_u2); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + cp_s2(dst_s4s, src_s2); $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + cp_u4(dst_s4s, src_u4); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + cp_s4(dst_s4s, src_s4); $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + cp_u4(dst_s4s, src_ux); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + cp_s4(dst_s4s, src_sx); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + + $display("cast to large unsigned logic"); + cp_r (dst_u4l, src_r); $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + cp_u2(dst_u4l, src_u2); $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1; + cp_s2(dst_u4l, src_s2); $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + cp_u4(dst_u4l, src_u4); $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1; + cp_s4(dst_u4l, src_s4); $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + cp_u4(dst_u4l, src_ux); $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1; + cp_s4(dst_u4l, src_sx); $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1; + + $display("cast to large signed logic"); + cp_r (dst_s4l, src_r); $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + cp_u2(dst_s4l, src_u2); $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1; + cp_s2(dst_s4l, src_s2); $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + cp_u4(dst_s4l, src_u4); $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1; + cp_s4(dst_s4l, src_s4); $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + cp_u4(dst_s4l, src_ux); $display("%b", dst_s4l); if (dst_s4l !== 12'b0000x0z00111) failed = 1; + cp_s4(dst_s4l, src_sx); $display("%b", dst_s4l); if (dst_s4l !== 12'bxxxxx0z00111) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/implicit_cast12.v b/ivtest/ivltests/implicit_cast12.v new file mode 100644 index 000000000..0299bfb1f --- /dev/null +++ b/ivtest/ivltests/implicit_cast12.v @@ -0,0 +1,328 @@ +// Test implicit casts during module input assignments. + +`ifdef __ICARUS__ + `define SUPPORT_REAL_NETS_IN_IVTEST + `define SUPPORT_TWO_STATE_NETS_IN_IVTEST +`endif + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +module cp_r(output wire real dst, + input wire real src); + assign dst = src; +endmodule +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +module cp_u2s(output wire bit unsigned [3:0] dst, + input wire bit unsigned [3:0] src); + assign dst = src; +endmodule + +module cp_s2s(output wire bit signed [3:0] dst, + input wire bit signed [3:0] src); + assign dst = src; +endmodule + +module cp_u2l(output wire bit unsigned [11:0] dst, + input wire bit unsigned [11:0] src); + assign dst = src; +endmodule + +module cp_s2l(output wire bit signed [11:0] dst, + input wire bit signed [11:0] src); + assign dst = src; +endmodule +`endif + +module cp_u4s(output wire logic unsigned [3:0] dst, + input wire logic unsigned [3:0] src); + assign dst = src; +endmodule + +module cp_s4s(output wire logic signed [3:0] dst, + input wire logic signed [3:0] src); + assign dst = src; +endmodule + +module cp_u4l(output wire logic unsigned [11:0] dst, + input wire logic unsigned [11:0] src); + assign dst = src; +endmodule + +module cp_s4l(output wire logic signed [11:0] dst, + input wire logic signed [11:0] src); + assign dst = src; +endmodule + +module implicit_cast(); + +real src_r; + +bit unsigned [7:0] src_u2; +bit signed [7:0] src_s2; + +logic unsigned [7:0] src_u4; +logic signed [7:0] src_s4; + +logic unsigned [7:0] src_ux; +logic signed [7:0] src_sx; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +wire real dst1_r; +wire real dst2_r; +wire real dst3_r; +wire real dst4_r; +wire real dst5_r; +wire real dst6_r; +wire real dst7_r; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +wire bit unsigned [3:0] dst1_u2s; +wire bit unsigned [3:0] dst2_u2s; +wire bit unsigned [3:0] dst3_u2s; +wire bit unsigned [3:0] dst4_u2s; +wire bit unsigned [3:0] dst5_u2s; +wire bit unsigned [3:0] dst6_u2s; +wire bit unsigned [3:0] dst7_u2s; + +wire bit signed [3:0] dst1_s2s; +wire bit signed [3:0] dst2_s2s; +wire bit signed [3:0] dst3_s2s; +wire bit signed [3:0] dst4_s2s; +wire bit signed [3:0] dst5_s2s; +wire bit signed [3:0] dst6_s2s; +wire bit signed [3:0] dst7_s2s; + +wire bit unsigned [11:0] dst1_u2l; +wire bit unsigned [11:0] dst2_u2l; +wire bit unsigned [11:0] dst3_u2l; +wire bit unsigned [11:0] dst4_u2l; +wire bit unsigned [11:0] dst5_u2l; +wire bit unsigned [11:0] dst6_u2l; +wire bit unsigned [11:0] dst7_u2l; + +wire bit signed [11:0] dst1_s2l; +wire bit signed [11:0] dst2_s2l; +wire bit signed [11:0] dst3_s2l; +wire bit signed [11:0] dst4_s2l; +wire bit signed [11:0] dst5_s2l; +wire bit signed [11:0] dst6_s2l; +wire bit signed [11:0] dst7_s2l; +`endif + +wire logic unsigned [3:0] dst1_u4s; +wire logic unsigned [3:0] dst2_u4s; +wire logic unsigned [3:0] dst3_u4s; +wire logic unsigned [3:0] dst4_u4s; +wire logic unsigned [3:0] dst5_u4s; +wire logic unsigned [3:0] dst6_u4s; +wire logic unsigned [3:0] dst7_u4s; + +wire logic signed [3:0] dst1_s4s; +wire logic signed [3:0] dst2_s4s; +wire logic signed [3:0] dst3_s4s; +wire logic signed [3:0] dst4_s4s; +wire logic signed [3:0] dst5_s4s; +wire logic signed [3:0] dst6_s4s; +wire logic signed [3:0] dst7_s4s; + +wire logic unsigned [11:0] dst1_u4l; +wire logic unsigned [11:0] dst2_u4l; +wire logic unsigned [11:0] dst3_u4l; +wire logic unsigned [11:0] dst4_u4l; +wire logic unsigned [11:0] dst5_u4l; +wire logic unsigned [11:0] dst6_u4l; +wire logic unsigned [11:0] dst7_u4l; + +wire logic signed [11:0] dst1_s4l; +wire logic signed [11:0] dst2_s4l; +wire logic signed [11:0] dst3_s4l; +wire logic signed [11:0] dst4_s4l; +wire logic signed [11:0] dst5_s4l; +wire logic signed [11:0] dst6_s4l; +wire logic signed [11:0] dst7_s4l; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +cp_r cp1_r(dst1_r, src_r); +cp_r cp2_r(dst2_r, src_u2); +cp_r cp3_r(dst3_r, src_s2); +cp_r cp4_r(dst4_r, src_u4); +cp_r cp5_r(dst5_r, src_s4); +cp_r cp6_r(dst6_r, src_ux); +cp_r cp7_r(dst7_r, src_sx); +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +cp_u2s cp1_u2s(dst1_u2s, src_r); +cp_u2s cp2_u2s(dst2_u2s, src_u2); +cp_u2s cp3_u2s(dst3_u2s, src_s2); +cp_u2s cp4_u2s(dst4_u2s, src_u4); +cp_u2s cp5_u2s(dst5_u2s, src_s4); +cp_u2s cp6_u2s(dst6_u2s, src_ux); +cp_u2s cp7_u2s(dst7_u2s, src_sx); + +cp_s2s cp1_s2s(dst1_s2s, src_r); +cp_s2s cp2_s2s(dst2_s2s, src_u2); +cp_s2s cp3_s2s(dst3_s2s, src_s2); +cp_s2s cp4_s2s(dst4_s2s, src_u4); +cp_s2s cp5_s2s(dst5_s2s, src_s4); +cp_s2s cp6_s2s(dst6_s2s, src_ux); +cp_s2s cp7_s2s(dst7_s2s, src_sx); + +cp_u2l cp1_u2l(dst1_u2l, src_r); +cp_u2l cp2_u2l(dst2_u2l, src_u2); +cp_u2l cp3_u2l(dst3_u2l, src_s2); +cp_u2l cp4_u2l(dst4_u2l, src_u4); +cp_u2l cp5_u2l(dst5_u2l, src_s4); +cp_u2l cp6_u2l(dst6_u2l, src_ux); +cp_u2l cp7_u2l(dst7_u2l, src_sx); + +cp_s2l cp1_s2l(dst1_s2l, src_r); +cp_s2l cp2_s2l(dst2_s2l, src_u2); +cp_s2l cp3_s2l(dst3_s2l, src_s2); +cp_s2l cp4_s2l(dst4_s2l, src_u4); +cp_s2l cp5_s2l(dst5_s2l, src_s4); +cp_s2l cp6_s2l(dst6_s2l, src_ux); +cp_s2l cp7_s2l(dst7_s2l, src_sx); +`endif + +cp_u4s cp1_u4s(dst1_u4s, src_r); +cp_u4s cp2_u4s(dst2_u4s, src_u2); +cp_u4s cp3_u4s(dst3_u4s, src_s2); +cp_u4s cp4_u4s(dst4_u4s, src_u4); +cp_u4s cp5_u4s(dst5_u4s, src_s4); +cp_u4s cp6_u4s(dst6_u4s, src_ux); +cp_u4s cp7_u4s(dst7_u4s, src_sx); + +cp_s4s cp1_s4s(dst1_s4s, src_r); +cp_s4s cp2_s4s(dst2_s4s, src_u2); +cp_s4s cp3_s4s(dst3_s4s, src_s2); +cp_s4s cp4_s4s(dst4_s4s, src_u4); +cp_s4s cp5_s4s(dst5_s4s, src_s4); +cp_s4s cp6_s4s(dst6_s4s, src_ux); +cp_s4s cp7_s4s(dst7_s4s, src_sx); + +cp_u4l cp1_u4l(dst1_u4l, src_r); +cp_u4l cp2_u4l(dst2_u4l, src_u2); +cp_u4l cp3_u4l(dst3_u4l, src_s2); +cp_u4l cp4_u4l(dst4_u4l, src_u4); +cp_u4l cp5_u4l(dst5_u4l, src_s4); +cp_u4l cp6_u4l(dst6_u4l, src_ux); +cp_u4l cp7_u4l(dst7_u4l, src_sx); + +cp_s4l cp1_s4l(dst1_s4l, src_r); +cp_s4l cp2_s4l(dst2_s4l, src_u2); +cp_s4l cp3_s4l(dst3_s4l, src_s2); +cp_s4l cp4_s4l(dst4_s4l, src_u4); +cp_s4l cp5_s4l(dst5_s4l, src_s4); +cp_s4l cp6_s4l(dst6_s4l, src_ux); +cp_s4l cp7_s4l(dst7_s4l, src_sx); + +bit failed; + +initial begin + failed = 0; + + src_r = -7; + src_u2 = 7; + src_s2 = -7; + src_u4 = 7; + src_s4 = -7; + src_ux = 8'bx0z00111; + src_sx = 8'bx0z00111; + + #1; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST + $display("cast to real"); + $display("%g", dst1_r); if (dst1_r != -7.0) failed = 1; + $display("%g", dst2_r); if (dst2_r != 7.0) failed = 1; + $display("%g", dst3_r); if (dst3_r != -7.0) failed = 1; + $display("%g", dst4_r); if (dst4_r != 7.0) failed = 1; + $display("%g", dst5_r); if (dst5_r != -7.0) failed = 1; + $display("%g", dst6_r); if (dst6_r != 7.0) failed = 1; + $display("%g", dst7_r); if (dst7_r != 7.0) failed = 1; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST + $display("cast to small unsigned bit"); + $display("%d", dst1_u2s); if (dst1_u2s !== 4'd9) failed = 1; + $display("%d", dst2_u2s); if (dst2_u2s !== 4'd7) failed = 1; + $display("%d", dst3_u2s); if (dst3_u2s !== 4'd9) failed = 1; + $display("%d", dst4_u2s); if (dst4_u2s !== 4'd7) failed = 1; + $display("%d", dst5_u2s); if (dst5_u2s !== 4'd9) failed = 1; + $display("%d", dst6_u2s); if (dst6_u2s !== 4'd7) failed = 1; + $display("%d", dst7_u2s); if (dst7_u2s !== 4'd7) failed = 1; + + $display("cast to small signed bit"); + $display("%d", dst1_s2s); if (dst1_s2s !== -4'sd7) failed = 1; + $display("%d", dst2_s2s); if (dst2_s2s !== 4'sd7) failed = 1; + $display("%d", dst3_s2s); if (dst3_s2s !== -4'sd7) failed = 1; + $display("%d", dst4_s2s); if (dst4_s2s !== 4'sd7) failed = 1; + $display("%d", dst5_s2s); if (dst5_s2s !== -4'sd7) failed = 1; + $display("%d", dst6_s2s); if (dst6_s2s !== 4'sd7) failed = 1; + $display("%d", dst7_s2s); if (dst7_s2s !== 4'sd7) failed = 1; + + $display("cast to large unsigned bit"); + $display("%d", dst1_u2l); if (dst1_u2l !== 12'd4089) failed = 1; + $display("%d", dst2_u2l); if (dst2_u2l !== 12'd7) failed = 1; + $display("%d", dst3_u2l); if (dst3_u2l !== 12'd4089) failed = 1; + $display("%d", dst4_u2l); if (dst4_u2l !== 12'd7) failed = 1; + $display("%d", dst5_u2l); if (dst5_u2l !== 12'd4089) failed = 1; + $display("%b", dst6_u2l); if (dst6_u2l !== 12'b000000000111) failed = 1; + $display("%b", dst7_u2l); if (dst7_u2l !== 12'b000000000111) failed = 1; + + $display("cast to large signed bit"); + $display("%d", dst1_s2l); if (dst1_s2l !== -12'sd7) failed = 1; + $display("%d", dst2_s2l); if (dst2_s2l !== 12'sd7) failed = 1; + $display("%d", dst3_s2l); if (dst3_s2l !== -12'sd7) failed = 1; + $display("%d", dst4_s2l); if (dst4_s2l !== 12'sd7) failed = 1; + $display("%d", dst5_s2l); if (dst5_s2l !== -12'sd7) failed = 1; + $display("%b", dst6_s2l); if (dst6_s2l !== 12'b000000000111) failed = 1; + $display("%b", dst7_s2l); if (dst7_s2l !== 12'b000000000111) failed = 1; +`endif + + $display("cast to small unsigned logic"); + $display("%d", dst1_u4s); if (dst1_u4s !== 4'd9) failed = 1; + $display("%d", dst2_u4s); if (dst2_u4s !== 4'd7) failed = 1; + $display("%d", dst3_u4s); if (dst3_u4s !== 4'd9) failed = 1; + $display("%d", dst4_u4s); if (dst4_u4s !== 4'd7) failed = 1; + $display("%d", dst5_u4s); if (dst5_u4s !== 4'd9) failed = 1; + $display("%d", dst6_u4s); if (dst6_u4s !== 4'd7) failed = 1; + $display("%d", dst7_u4s); if (dst7_u4s !== 4'd7) failed = 1; + + $display("cast to small signed logic"); + $display("%d", dst1_s4s); if (dst1_s4s !== -4'sd7) failed = 1; + $display("%d", dst2_s4s); if (dst2_s4s !== 4'sd7) failed = 1; + $display("%d", dst3_s4s); if (dst3_s4s !== -4'sd7) failed = 1; + $display("%d", dst4_s4s); if (dst4_s4s !== 4'sd7) failed = 1; + $display("%d", dst5_s4s); if (dst5_s4s !== -4'sd7) failed = 1; + $display("%d", dst6_s4s); if (dst6_s4s !== 4'sd7) failed = 1; + $display("%d", dst7_s4s); if (dst7_s4s !== 4'sd7) failed = 1; + + $display("cast to large unsigned logic"); + $display("%d", dst1_u4l); if (dst1_u4l !== 12'd4089) failed = 1; + $display("%d", dst2_u4l); if (dst2_u4l !== 12'd7) failed = 1; + $display("%d", dst3_u4l); if (dst3_u4l !== 12'd4089) failed = 1; + $display("%d", dst4_u4l); if (dst4_u4l !== 12'd7) failed = 1; + $display("%d", dst5_u4l); if (dst5_u4l !== 12'd4089) failed = 1; + $display("%b", dst6_u4l); if (dst6_u4l !== 12'b0000x0z00111) failed = 1; + $display("%b", dst7_u4l); if (dst7_u4l !== 12'bxxxxx0z00111) failed = 1; + + $display("cast to large signed logic"); + $display("%d", dst1_s4l); if (dst1_s4l !== -12'sd7) failed = 1; + $display("%d", dst2_s4l); if (dst2_s4l !== 12'sd7) failed = 1; + $display("%d", dst3_s4l); if (dst3_s4l !== -12'sd7) failed = 1; + $display("%d", dst4_s4l); if (dst4_s4l !== 12'sd7) failed = 1; + $display("%d", dst5_s4l); if (dst5_s4l !== -12'sd7) failed = 1; + $display("%b", dst6_s4l); if (dst6_s4l !== 12'b0000x0z00111) failed = 1; + $display("%b", dst7_s4l); if (dst7_s4l !== 12'bxxxxx0z00111) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/implicit_cast13.v b/ivtest/ivltests/implicit_cast13.v new file mode 100644 index 000000000..3fa2752d4 --- /dev/null +++ b/ivtest/ivltests/implicit_cast13.v @@ -0,0 +1,340 @@ +// Test implicit casts during module output assignments. + +`ifdef __ICARUS__ + `define SUPPORT_REAL_NETS_IN_IVTEST + `define SUPPORT_TWO_STATE_NETS_IN_IVTEST +`endif + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +module cp_r(output wire real dst, + input wire real src); + assign dst = src; +endmodule +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +module cp_u2(output wire bit unsigned [7:0] dst, + input wire bit unsigned [7:0] src); + assign dst = src; +endmodule + +module cp_s2(output wire bit signed [7:0] dst, + input wire bit signed [7:0] src); + assign dst = src; +endmodule +`endif + +module cp_u4(output wire logic unsigned [7:0] dst, + input wire logic unsigned [7:0] src); + assign dst = src; +endmodule + +module cp_s4(output wire logic signed [7:0] dst, + input wire logic signed [7:0] src); + assign dst = src; +endmodule + +module implicit_cast(); + +real src_r; + +bit unsigned [7:0] src_u2; +bit signed [7:0] src_s2; + +logic unsigned [7:0] src_u4; +logic signed [7:0] src_s4; + +logic unsigned [7:0] src_ux; +logic signed [7:0] src_sx; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +wire real dst1_r; +wire real dst2_r; +wire real dst3_r; +wire real dst4_r; +wire real dst5_r; +wire real dst6_r; +wire real dst7_r; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +wire bit unsigned [3:0] dst1_u2s; +wire bit unsigned [3:0] dst2_u2s; +wire bit unsigned [3:0] dst3_u2s; +wire bit unsigned [3:0] dst4_u2s; +wire bit unsigned [3:0] dst5_u2s; +wire bit unsigned [3:0] dst6_u2s; +wire bit unsigned [3:0] dst7_u2s; + +wire bit signed [3:0] dst1_s2s; +wire bit signed [3:0] dst2_s2s; +wire bit signed [3:0] dst3_s2s; +wire bit signed [3:0] dst4_s2s; +wire bit signed [3:0] dst5_s2s; +wire bit signed [3:0] dst6_s2s; +wire bit signed [3:0] dst7_s2s; + +wire bit unsigned [11:0] dst1_u2l; +wire bit unsigned [11:0] dst2_u2l; +wire bit unsigned [11:0] dst3_u2l; +wire bit unsigned [11:0] dst4_u2l; +wire bit unsigned [11:0] dst5_u2l; +wire bit unsigned [11:0] dst6_u2l; +wire bit unsigned [11:0] dst7_u2l; + +wire bit signed [11:0] dst1_s2l; +wire bit signed [11:0] dst2_s2l; +wire bit signed [11:0] dst3_s2l; +wire bit signed [11:0] dst4_s2l; +wire bit signed [11:0] dst5_s2l; +wire bit signed [11:0] dst6_s2l; +wire bit signed [11:0] dst7_s2l; +`endif + +wire logic unsigned [3:0] dst1_u4s; +wire logic unsigned [3:0] dst2_u4s; +wire logic unsigned [3:0] dst3_u4s; +wire logic unsigned [3:0] dst4_u4s; +wire logic unsigned [3:0] dst5_u4s; +wire logic unsigned [3:0] dst6_u4s; +wire logic unsigned [3:0] dst7_u4s; + +wire logic signed [3:0] dst1_s4s; +wire logic signed [3:0] dst2_s4s; +wire logic signed [3:0] dst3_s4s; +wire logic signed [3:0] dst4_s4s; +wire logic signed [3:0] dst5_s4s; +wire logic signed [3:0] dst6_s4s; +wire logic signed [3:0] dst7_s4s; + +wire logic unsigned [11:0] dst1_u4l; +wire logic unsigned [11:0] dst2_u4l; +wire logic unsigned [11:0] dst3_u4l; +wire logic unsigned [11:0] dst4_u4l; +wire logic unsigned [11:0] dst5_u4l; +wire logic unsigned [11:0] dst6_u4l; +wire logic unsigned [11:0] dst7_u4l; + +wire logic signed [11:0] dst1_s4l; +wire logic signed [11:0] dst2_s4l; +wire logic signed [11:0] dst3_s4l; +wire logic signed [11:0] dst4_s4l; +wire logic signed [11:0] dst5_s4l; +wire logic signed [11:0] dst6_s4l; +wire logic signed [11:0] dst7_s4l; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +cp_r cp1_r(dst1_r, src_r); +`endif +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +cp_u2 cp2_r(dst2_r, src_u2); +cp_s2 cp3_r(dst3_r, src_s2); +`endif +cp_u4 cp4_r(dst4_r, src_u4); +cp_s4 cp5_r(dst5_r, src_s4); +cp_u4 cp6_r(dst6_r, src_ux); +cp_s4 cp7_r(dst7_r, src_sx); + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +cp_r cp1_u2s(dst1_u2s, src_r); +`endif +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +cp_u2 cp2_u2s(dst2_u2s, src_u2); +cp_s2 cp3_u2s(dst3_u2s, src_s2); +`endif +cp_u4 cp4_u2s(dst4_u2s, src_u4); +cp_s4 cp5_u2s(dst5_u2s, src_s4); +cp_u4 cp6_u2s(dst6_u2s, src_ux); +cp_s4 cp7_u2s(dst7_u2s, src_sx); + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +cp_r cp1_s2s(dst1_s2s, src_r); +`endif +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +cp_u2 cp2_s2s(dst2_s2s, src_u2); +cp_s2 cp3_s2s(dst3_s2s, src_s2); +`endif +cp_u4 cp4_s2s(dst4_s2s, src_u4); +cp_s4 cp5_s2s(dst5_s2s, src_s4); +cp_u4 cp6_s2s(dst6_s2s, src_ux); +cp_s4 cp7_s2s(dst7_s2s, src_sx); + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +cp_r cp1_u2l(dst1_u2l, src_r); +`endif +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +cp_u2 cp2_u2l(dst2_u2l, src_u2); +cp_s2 cp3_u2l(dst3_u2l, src_s2); +`endif +cp_u4 cp4_u2l(dst4_u2l, src_u4); +cp_s4 cp5_u2l(dst5_u2l, src_s4); +cp_u4 cp6_u2l(dst6_u2l, src_ux); +cp_s4 cp7_u2l(dst7_u2l, src_sx); + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +cp_r cp1_s2l(dst1_s2l, src_r); +`endif +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +cp_u2 cp2_s2l(dst2_s2l, src_u2); +cp_s2 cp3_s2l(dst3_s2l, src_s2); +`endif +cp_u4 cp4_s2l(dst4_s2l, src_u4); +cp_s4 cp5_s2l(dst5_s2l, src_s4); +cp_u4 cp6_s2l(dst6_s2l, src_ux); +cp_s4 cp7_s2l(dst7_s2l, src_sx); + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +cp_r cp1_u4s(dst1_u4s, src_r); +`endif +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +cp_u2 cp2_u4s(dst2_u4s, src_u2); +cp_s2 cp3_u4s(dst3_u4s, src_s2); +`endif +cp_u4 cp4_u4s(dst4_u4s, src_u4); +cp_s4 cp5_u4s(dst5_u4s, src_s4); +cp_u4 cp6_u4s(dst6_u4s, src_ux); +cp_s4 cp7_u4s(dst7_u4s, src_sx); + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +cp_r cp1_s4s(dst1_s4s, src_r); +`endif +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +cp_u2 cp2_s4s(dst2_s4s, src_u2); +cp_s2 cp3_s4s(dst3_s4s, src_s2); +`endif +cp_u4 cp4_s4s(dst4_s4s, src_u4); +cp_s4 cp5_s4s(dst5_s4s, src_s4); +cp_u4 cp6_s4s(dst6_s4s, src_ux); +cp_s4 cp7_s4s(dst7_s4s, src_sx); + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +cp_r cp1_u4l(dst1_u4l, src_r); +`endif +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +cp_u2 cp2_u4l(dst2_u4l, src_u2); +cp_s2 cp3_u4l(dst3_u4l, src_s2); +`endif +cp_u4 cp4_u4l(dst4_u4l, src_u4); +cp_s4 cp5_u4l(dst5_u4l, src_s4); +cp_u4 cp6_u4l(dst6_u4l, src_ux); +cp_s4 cp7_u4l(dst7_u4l, src_sx); + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +cp_r cp1_s4l(dst1_s4l, src_r); +`endif +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +cp_u2 cp2_s4l(dst2_s4l, src_u2); +cp_s2 cp3_s4l(dst3_s4l, src_s2); +`endif +cp_u4 cp4_s4l(dst4_s4l, src_u4); +cp_s4 cp5_s4l(dst5_s4l, src_s4); +cp_u4 cp6_s4l(dst6_s4l, src_ux); +cp_s4 cp7_s4l(dst7_s4l, src_sx); + +bit failed; + +initial begin + failed = 0; + + src_r = -7; + src_u2 = 7; + src_s2 = -7; + src_u4 = 7; + src_s4 = -7; + src_ux = 8'bx0z00111; + src_sx = 8'bx0z00111; + + #1; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST + $display("cast to real"); + $display("%g", dst1_r); if (dst1_r != -7.0) failed = 1; + $display("%g", dst2_r); if (dst2_r != 7.0) failed = 1; + $display("%g", dst3_r); if (dst3_r != -7.0) failed = 1; + $display("%g", dst4_r); if (dst4_r != 7.0) failed = 1; + $display("%g", dst5_r); if (dst5_r != -7.0) failed = 1; + $display("%g", dst6_r); if (dst6_r != 7.0) failed = 1; + $display("%g", dst7_r); if (dst7_r != 7.0) failed = 1; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST + $display("cast to small unsigned bit"); + $display("%d", dst1_u2s); if (dst1_u2s !== 4'd9) failed = 1; + $display("%d", dst2_u2s); if (dst2_u2s !== 4'd7) failed = 1; + $display("%d", dst3_u2s); if (dst3_u2s !== 4'd9) failed = 1; + $display("%d", dst4_u2s); if (dst4_u2s !== 4'd7) failed = 1; + $display("%d", dst5_u2s); if (dst5_u2s !== 4'd9) failed = 1; + $display("%d", dst6_u2s); if (dst6_u2s !== 4'd7) failed = 1; + $display("%d", dst7_u2s); if (dst7_u2s !== 4'd7) failed = 1; + + $display("cast to small signed bit"); + $display("%d", dst1_s2s); if (dst1_s2s !== -4'sd7) failed = 1; + $display("%d", dst2_s2s); if (dst2_s2s !== 4'sd7) failed = 1; + $display("%d", dst3_s2s); if (dst3_s2s !== -4'sd7) failed = 1; + $display("%d", dst4_s2s); if (dst4_s2s !== 4'sd7) failed = 1; + $display("%d", dst5_s2s); if (dst5_s2s !== -4'sd7) failed = 1; + $display("%d", dst6_s2s); if (dst6_s2s !== 4'sd7) failed = 1; + $display("%d", dst7_s2s); if (dst7_s2s !== 4'sd7) failed = 1; + + $display("cast to large unsigned bit"); + $display("%d", dst1_u2l); if (dst1_u2l !== 12'd4089) failed = 1; + $display("%d", dst2_u2l); if (dst2_u2l !== 12'd7) failed = 1; + $display("%d", dst3_u2l); if (dst3_u2l !== 12'd4089) failed = 1; + $display("%d", dst4_u2l); if (dst4_u2l !== 12'd7) failed = 1; + $display("%d", dst5_u2l); if (dst5_u2l !== 12'd4089) failed = 1; + $display("%b", dst6_u2l); if (dst6_u2l !== 12'b000000000111) failed = 1; + $display("%b", dst7_u2l); if (dst7_u2l !== 12'b000000000111) failed = 1; + + $display("cast to large signed bit"); + $display("%d", dst1_s2l); if (dst1_s2l !== -12'sd7) failed = 1; + $display("%d", dst2_s2l); if (dst2_s2l !== 12'sd7) failed = 1; + $display("%d", dst3_s2l); if (dst3_s2l !== -12'sd7) failed = 1; + $display("%d", dst4_s2l); if (dst4_s2l !== 12'sd7) failed = 1; + $display("%d", dst5_s2l); if (dst5_s2l !== -12'sd7) failed = 1; + $display("%b", dst6_s2l); if (dst6_s2l !== 12'b000000000111) failed = 1; + $display("%b", dst7_s2l); if (dst7_s2l !== 12'b000000000111) failed = 1; +`endif + + $display("cast to small unsigned logic"); + $display("%d", dst1_u4s); if (dst1_u4s !== 4'd9) failed = 1; + $display("%d", dst2_u4s); if (dst2_u4s !== 4'd7) failed = 1; + $display("%d", dst3_u4s); if (dst3_u4s !== 4'd9) failed = 1; + $display("%d", dst4_u4s); if (dst4_u4s !== 4'd7) failed = 1; + $display("%d", dst5_u4s); if (dst5_u4s !== 4'd9) failed = 1; + $display("%d", dst6_u4s); if (dst6_u4s !== 4'd7) failed = 1; + $display("%d", dst7_u4s); if (dst7_u4s !== 4'd7) failed = 1; + + $display("cast to small signed logic"); + $display("%d", dst1_s4s); if (dst1_s4s !== -4'sd7) failed = 1; + $display("%d", dst2_s4s); if (dst2_s4s !== 4'sd7) failed = 1; + $display("%d", dst3_s4s); if (dst3_s4s !== -4'sd7) failed = 1; + $display("%d", dst4_s4s); if (dst4_s4s !== 4'sd7) failed = 1; + $display("%d", dst5_s4s); if (dst5_s4s !== -4'sd7) failed = 1; + $display("%d", dst6_s4s); if (dst6_s4s !== 4'sd7) failed = 1; + $display("%d", dst7_s4s); if (dst7_s4s !== 4'sd7) failed = 1; + + $display("cast to large unsigned logic"); + $display("%d", dst1_u4l); if (dst1_u4l !== 12'd4089) failed = 1; + $display("%d", dst2_u4l); if (dst2_u4l !== 12'd7) failed = 1; + $display("%d", dst3_u4l); if (dst3_u4l !== 12'd4089) failed = 1; + $display("%d", dst4_u4l); if (dst4_u4l !== 12'd7) failed = 1; + $display("%d", dst5_u4l); if (dst5_u4l !== 12'd4089) failed = 1; + $display("%b", dst6_u4l); if (dst6_u4l !== 12'b0000x0z00111) failed = 1; + $display("%b", dst7_u4l); if (dst7_u4l !== 12'bxxxxx0z00111) failed = 1; + + $display("cast to large signed logic"); + $display("%d", dst1_s4l); if (dst1_s4l !== -12'sd7) failed = 1; + $display("%d", dst2_s4l); if (dst2_s4l !== 12'sd7) failed = 1; + $display("%d", dst3_s4l); if (dst3_s4l !== -12'sd7) failed = 1; + $display("%d", dst4_s4l); if (dst4_s4l !== 12'sd7) failed = 1; + $display("%d", dst5_s4l); if (dst5_s4l !== -12'sd7) failed = 1; + $display("%b", dst6_s4l); if (dst6_s4l !== 12'b0000x0z00111) failed = 1; + $display("%b", dst7_s4l); if (dst7_s4l !== 12'bxxxxx0z00111) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/implicit_cast2.v b/ivtest/ivltests/implicit_cast2.v new file mode 100644 index 000000000..fa80c4c08 --- /dev/null +++ b/ivtest/ivltests/implicit_cast2.v @@ -0,0 +1,130 @@ +// Test implicit casts during procedural non-blocking assignments. + +module implicit_cast(); + +real src_r; + +bit unsigned [7:0] src_u2; +bit signed [7:0] src_s2; + +logic unsigned [7:0] src_u4; +logic signed [7:0] src_s4; + +logic unsigned [7:0] src_ux; +logic signed [7:0] src_sx; + +real dst_r; + +bit unsigned [3:0] dst_u2s; +bit signed [3:0] dst_s2s; + +bit unsigned [11:0] dst_u2l; +bit signed [11:0] dst_s2l; + +logic unsigned [3:0] dst_u4s; +logic signed [3:0] dst_s4s; + +logic unsigned [11:0] dst_u4l; +logic signed [11:0] dst_s4l; + +bit failed; + +initial begin + failed = 0; + + src_r = -7; + src_u2 = 7; + src_s2 = -7; + src_u4 = 7; + src_s4 = -7; + src_ux = 8'bx0z00111; + src_sx = 8'bx0z00111; + + $display("cast to real"); + dst_r <= src_r; #1 $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + dst_r <= src_u2; #1 $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + dst_r <= src_s2; #1 $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + dst_r <= src_u4; #1 $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + dst_r <= src_s4; #1 $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + dst_r <= src_ux; #1 $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + dst_r <= src_sx; #1 $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + + $display("cast to small unsigned bit"); + dst_u2s <= src_r; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + dst_u2s <= src_u2; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + dst_u2s <= src_s2; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + dst_u2s <= src_u4; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + dst_u2s <= src_s4; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + dst_u2s <= src_ux; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + dst_u2s <= src_sx; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + + $display("cast to small signed bit"); + dst_s2s <= src_r; #1 $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + dst_s2s <= src_u2; #1 $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + dst_s2s <= src_s2; #1 $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + dst_s2s <= src_u4; #1 $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + dst_s2s <= src_s4; #1 $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + dst_s2s <= src_ux; #1 $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + dst_s2s <= src_sx; #1 $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + + $display("cast to large unsigned bit"); + dst_u2l <= src_r; #1 $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + dst_u2l <= src_u2; #1 $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1; + dst_u2l <= src_s2; #1 $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + dst_u2l <= src_u4; #1 $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1; + dst_u2l <= src_s4; #1 $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + dst_u2l <= src_ux; #1 $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1; + dst_u2l <= src_sx; #1 $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1; + + $display("cast to large signed bit"); + dst_s2l <= src_r; #1 $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + dst_s2l <= src_u2; #1 $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1; + dst_s2l <= src_s2; #1 $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + dst_s2l <= src_u4; #1 $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1; + dst_s2l <= src_s4; #1 $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + dst_s2l <= src_ux; #1 $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1; + dst_s2l <= src_sx; #1 $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1; + + $display("cast to small unsigned logic"); + dst_u4s <= src_r; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + dst_u4s <= src_u2; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + dst_u4s <= src_s2; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + dst_u4s <= src_u4; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + dst_u4s <= src_s4; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + dst_u4s <= src_ux; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + dst_u4s <= src_sx; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + + $display("cast to small signed logic"); + dst_s4s <= src_r; #1 $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + dst_s4s <= src_u2; #1 $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + dst_s4s <= src_s2; #1 $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + dst_s4s <= src_u4; #1 $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + dst_s4s <= src_s4; #1 $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + dst_s4s <= src_ux; #1 $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + dst_s4s <= src_sx; #1 $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + + $display("cast to large unsigned logic"); + dst_u4l <= src_r; #1 $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + dst_u4l <= src_u2; #1 $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1; + dst_u4l <= src_s2; #1 $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + dst_u4l <= src_u4; #1 $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1; + dst_u4l <= src_s4; #1 $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + dst_u4l <= src_ux; #1 $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1; + dst_u4l <= src_sx; #1 $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1; + + $display("cast to large signed logic"); + dst_s4l <= src_r; #1 $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + dst_s4l <= src_u2; #1 $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1; + dst_s4l <= src_s2; #1 $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + dst_s4l <= src_u4; #1 $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1; + dst_s4l <= src_s4; #1 $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + dst_s4l <= src_ux; #1 $display("%b", dst_s4l); if (dst_s4l !== 12'b0000x0z00111) failed = 1; + dst_s4l <= src_sx; #1 $display("%b", dst_s4l); if (dst_s4l !== 12'bxxxxx0z00111) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/implicit_cast3.v b/ivtest/ivltests/implicit_cast3.v new file mode 100644 index 000000000..e8103d630 --- /dev/null +++ b/ivtest/ivltests/implicit_cast3.v @@ -0,0 +1,130 @@ +// Test implicit casts during procedural continuous (reg) assignments. + +module implicit_cast(); + +real src_r; + +bit unsigned [7:0] src_u2; +bit signed [7:0] src_s2; + +logic unsigned [7:0] src_u4; +logic signed [7:0] src_s4; + +logic unsigned [7:0] src_ux; +logic signed [7:0] src_sx; + +real dst_r; + +bit unsigned [3:0] dst_u2s; +bit signed [3:0] dst_s2s; + +bit unsigned [11:0] dst_u2l; +bit signed [11:0] dst_s2l; + +logic unsigned [3:0] dst_u4s; +logic signed [3:0] dst_s4s; + +logic unsigned [11:0] dst_u4l; +logic signed [11:0] dst_s4l; + +bit failed; + +initial begin + failed = 0; + + src_r = -7; + src_u2 = 7; + src_s2 = -7; + src_u4 = 7; + src_s4 = -7; + src_ux = 8'bx0z00111; + src_sx = 8'bx0z00111; + + $display("cast to real"); + assign dst_r = src_r; $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + assign dst_r = src_u2; $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + assign dst_r = src_s2; $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + assign dst_r = src_u4; $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + assign dst_r = src_s4; $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + assign dst_r = src_ux; $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + assign dst_r = src_sx; $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + + $display("cast to small unsigned bit"); + assign dst_u2s = src_r; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + assign dst_u2s = src_u2; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + assign dst_u2s = src_s2; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + assign dst_u2s = src_u4; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + assign dst_u2s = src_s4; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + assign dst_u2s = src_ux; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + assign dst_u2s = src_sx; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + + $display("cast to small signed bit"); + assign dst_s2s = src_r; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + assign dst_s2s = src_u2; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + assign dst_s2s = src_s2; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + assign dst_s2s = src_u4; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + assign dst_s2s = src_s4; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + assign dst_s2s = src_ux; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + assign dst_s2s = src_sx; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + + $display("cast to large unsigned bit"); + assign dst_u2l = src_r; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + assign dst_u2l = src_u2; $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1; + assign dst_u2l = src_s2; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + assign dst_u2l = src_u4; $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1; + assign dst_u2l = src_s4; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + assign dst_u2l = src_ux; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1; + assign dst_u2l = src_sx; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1; + + $display("cast to large signed bit"); + assign dst_s2l = src_r; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + assign dst_s2l = src_u2; $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1; + assign dst_s2l = src_s2; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + assign dst_s2l = src_u4; $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1; + assign dst_s2l = src_s4; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + assign dst_s2l = src_ux; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1; + assign dst_s2l = src_sx; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1; + + $display("cast to small unsigned logic"); + assign dst_u4s = src_r; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + assign dst_u4s = src_u2; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + assign dst_u4s = src_s2; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + assign dst_u4s = src_u4; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + assign dst_u4s = src_s4; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + assign dst_u4s = src_ux; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + assign dst_u4s = src_sx; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + + $display("cast to small signed logic"); + assign dst_s4s = src_r; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + assign dst_s4s = src_u2; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + assign dst_s4s = src_s2; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + assign dst_s4s = src_u4; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + assign dst_s4s = src_s4; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + assign dst_s4s = src_ux; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + assign dst_s4s = src_sx; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + + $display("cast to large unsigned logic"); + assign dst_u4l = src_r; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + assign dst_u4l = src_u2; $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1; + assign dst_u4l = src_s2; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + assign dst_u4l = src_u4; $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1; + assign dst_u4l = src_s4; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + assign dst_u4l = src_ux; $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1; + assign dst_u4l = src_sx; $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1; + + $display("cast to large signed logic"); + assign dst_s4l = src_r; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + assign dst_s4l = src_u2; $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1; + assign dst_s4l = src_s2; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + assign dst_s4l = src_u4; $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1; + assign dst_s4l = src_s4; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + assign dst_s4l = src_ux; $display("%b", dst_s4l); if (dst_s4l !== 12'b0000x0z00111) failed = 1; + assign dst_s4l = src_sx; $display("%b", dst_s4l); if (dst_s4l !== 12'bxxxxx0z00111) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/implicit_cast4.v b/ivtest/ivltests/implicit_cast4.v new file mode 100644 index 000000000..4be18fcf8 --- /dev/null +++ b/ivtest/ivltests/implicit_cast4.v @@ -0,0 +1,142 @@ +// Test implicit casts during procedural continuous (net) assignments. + +`ifdef __ICARUS__ + `define SUPPORT_REAL_NETS_IN_IVTEST + `define SUPPORT_TWO_STATE_NETS_IN_IVTEST +`endif + +module implicit_cast(); + +real src_r; + +bit unsigned [7:0] src_u2; +bit signed [7:0] src_s2; + +logic unsigned [7:0] src_u4; +logic signed [7:0] src_s4; + +logic unsigned [7:0] src_ux; +logic signed [7:0] src_sx; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +wire real dst_r; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +wire bit unsigned [3:0] dst_u2s; +wire bit signed [3:0] dst_s2s; + +wire bit unsigned [11:0] dst_u2l; +wire bit signed [11:0] dst_s2l; +`endif +wire logic unsigned [3:0] dst_u4s; +wire logic signed [3:0] dst_s4s; + +wire logic unsigned [11:0] dst_u4l; +wire logic signed [11:0] dst_s4l; + +bit failed; + +initial begin + failed = 0; + + src_r = -7; + src_u2 = 7; + src_s2 = -7; + src_u4 = 7; + src_s4 = -7; + src_ux = 8'bx0z00111; + src_sx = 8'bx0z00111; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST + $display("cast to real"); + force dst_r = src_r; $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + force dst_r = src_u2; $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + force dst_r = src_s2; $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + force dst_r = src_u4; $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + force dst_r = src_s4; $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + force dst_r = src_ux; $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + force dst_r = src_sx; $display("%g", dst_r); if (dst_r != 7.0) failed = 1; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST + $display("cast to small unsigned bit"); + force dst_u2s = src_r; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + force dst_u2s = src_u2; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + force dst_u2s = src_s2; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + force dst_u2s = src_u4; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + force dst_u2s = src_s4; $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + force dst_u2s = src_ux; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + force dst_u2s = src_sx; $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + + $display("cast to small signed bit"); + force dst_s2s = src_r; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + force dst_s2s = src_u2; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + force dst_s2s = src_s2; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + force dst_s2s = src_u4; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + force dst_s2s = src_s4; $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + force dst_s2s = src_ux; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + force dst_s2s = src_sx; $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + + $display("cast to large unsigned bit"); + force dst_u2l = src_r; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + force dst_u2l = src_u2; $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1; + force dst_u2l = src_s2; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + force dst_u2l = src_u4; $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1; + force dst_u2l = src_s4; $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + force dst_u2l = src_ux; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1; + force dst_u2l = src_sx; $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1; + + $display("cast to large signed bit"); + force dst_s2l = src_r; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + force dst_s2l = src_u2; $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1; + force dst_s2l = src_s2; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + force dst_s2l = src_u4; $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1; + force dst_s2l = src_s4; $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + force dst_s2l = src_ux; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1; + force dst_s2l = src_sx; $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1; +`endif + + $display("cast to small unsigned logic"); + force dst_u4s = src_r; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + force dst_u4s = src_u2; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + force dst_u4s = src_s2; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + force dst_u4s = src_u4; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + force dst_u4s = src_s4; $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + force dst_u4s = src_ux; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + force dst_u4s = src_sx; $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + + $display("cast to small signed logic"); + force dst_s4s = src_r; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + force dst_s4s = src_u2; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + force dst_s4s = src_s2; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + force dst_s4s = src_u4; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + force dst_s4s = src_s4; $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + force dst_s4s = src_ux; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + force dst_s4s = src_sx; $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + + $display("cast to large unsigned logic"); + force dst_u4l = src_r; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + force dst_u4l = src_u2; $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1; + force dst_u4l = src_s2; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + force dst_u4l = src_u4; $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1; + force dst_u4l = src_s4; $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + force dst_u4l = src_ux; $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1; + force dst_u4l = src_sx; $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1; + + $display("cast to large signed logic"); + force dst_s4l = src_r; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + force dst_s4l = src_u2; $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1; + force dst_s4l = src_s2; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + force dst_s4l = src_u4; $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1; + force dst_s4l = src_s4; $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + force dst_s4l = src_ux; $display("%b", dst_s4l); if (dst_s4l !== 12'b0000x0z00111) failed = 1; + force dst_s4l = src_sx; $display("%b", dst_s4l); if (dst_s4l !== 12'bxxxxx0z00111) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/implicit_cast5.v b/ivtest/ivltests/implicit_cast5.v new file mode 100644 index 000000000..6e0abd9b7 --- /dev/null +++ b/ivtest/ivltests/implicit_cast5.v @@ -0,0 +1,203 @@ +// Test implicit casts during net declaration assignments. + +`ifdef __ICARUS__ + `define SUPPORT_REAL_NETS_IN_IVTEST + `define SUPPORT_TWO_STATE_NETS_IN_IVTEST +`endif + +module implicit_cast(); + +real src_r; + +bit unsigned [7:0] src_u2; +bit signed [7:0] src_s2; + +logic unsigned [7:0] src_u4; +logic signed [7:0] src_s4; + +logic unsigned [7:0] src_ux; +logic signed [7:0] src_sx; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +wire real dst1_r = src_r; +wire real dst2_r = src_u2; +wire real dst3_r = src_s2; +wire real dst4_r = src_u4; +wire real dst5_r = src_s4; +wire real dst6_r = src_ux; +wire real dst7_r = src_sx; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +wire bit unsigned [3:0] dst1_u2s = src_r; +wire bit unsigned [3:0] dst2_u2s = src_u2; +wire bit unsigned [3:0] dst3_u2s = src_s2; +wire bit unsigned [3:0] dst4_u2s = src_u4; +wire bit unsigned [3:0] dst5_u2s = src_s4; +wire bit unsigned [3:0] dst6_u2s = src_ux; +wire bit unsigned [3:0] dst7_u2s = src_sx; + +wire bit signed [3:0] dst1_s2s = src_r; +wire bit signed [3:0] dst2_s2s = src_u2; +wire bit signed [3:0] dst3_s2s = src_s2; +wire bit signed [3:0] dst4_s2s = src_u4; +wire bit signed [3:0] dst5_s2s = src_s4; +wire bit signed [3:0] dst6_s2s = src_ux; +wire bit signed [3:0] dst7_s2s = src_sx; + +wire bit unsigned [11:0] dst1_u2l = src_r; +wire bit unsigned [11:0] dst2_u2l = src_u2; +wire bit unsigned [11:0] dst3_u2l = src_s2; +wire bit unsigned [11:0] dst4_u2l = src_u4; +wire bit unsigned [11:0] dst5_u2l = src_s4; +wire bit unsigned [11:0] dst6_u2l = src_ux; +wire bit unsigned [11:0] dst7_u2l = src_sx; + +wire bit signed [11:0] dst1_s2l = src_r; +wire bit signed [11:0] dst2_s2l = src_u2; +wire bit signed [11:0] dst3_s2l = src_s2; +wire bit signed [11:0] dst4_s2l = src_u4; +wire bit signed [11:0] dst5_s2l = src_s4; +wire bit signed [11:0] dst6_s2l = src_ux; +wire bit signed [11:0] dst7_s2l = src_sx; +`endif + +wire logic unsigned [3:0] dst1_u4s = src_r; +wire logic unsigned [3:0] dst2_u4s = src_u2; +wire logic unsigned [3:0] dst3_u4s = src_s2; +wire logic unsigned [3:0] dst4_u4s = src_u4; +wire logic unsigned [3:0] dst5_u4s = src_s4; +wire logic unsigned [3:0] dst6_u4s = src_ux; +wire logic unsigned [3:0] dst7_u4s = src_sx; + +wire logic signed [3:0] dst1_s4s = src_r; +wire logic signed [3:0] dst2_s4s = src_u2; +wire logic signed [3:0] dst3_s4s = src_s2; +wire logic signed [3:0] dst4_s4s = src_u4; +wire logic signed [3:0] dst5_s4s = src_s4; +wire logic signed [3:0] dst6_s4s = src_ux; +wire logic signed [3:0] dst7_s4s = src_sx; + +wire logic unsigned [11:0] dst1_u4l = src_r; +wire logic unsigned [11:0] dst2_u4l = src_u2; +wire logic unsigned [11:0] dst3_u4l = src_s2; +wire logic unsigned [11:0] dst4_u4l = src_u4; +wire logic unsigned [11:0] dst5_u4l = src_s4; +wire logic unsigned [11:0] dst6_u4l = src_ux; +wire logic unsigned [11:0] dst7_u4l = src_sx; + +wire logic signed [11:0] dst1_s4l = src_r; +wire logic signed [11:0] dst2_s4l = src_u2; +wire logic signed [11:0] dst3_s4l = src_s2; +wire logic signed [11:0] dst4_s4l = src_u4; +wire logic signed [11:0] dst5_s4l = src_s4; +wire logic signed [11:0] dst6_s4l = src_ux; +wire logic signed [11:0] dst7_s4l = src_sx; + +bit failed; + +initial begin + failed = 0; + + src_r = -7; + src_u2 = 7; + src_s2 = -7; + src_u4 = 7; + src_s4 = -7; + src_ux = 8'bx0z00111; + src_sx = 8'bx0z00111; + + #1; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST + $display("cast to real"); + $display("%g", dst1_r); if (dst1_r != -7.0) failed = 1; + $display("%g", dst2_r); if (dst4_r != 7.0) failed = 1; + $display("%g", dst3_r); if (dst5_r != -7.0) failed = 1; + $display("%g", dst4_r); if (dst2_r != 7.0) failed = 1; + $display("%g", dst5_r); if (dst3_r != -7.0) failed = 1; + $display("%g", dst6_r); if (dst6_r != 7.0) failed = 1; + $display("%g", dst7_r); if (dst7_r != 7.0) failed = 1; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST + $display("cast to small unsigned bit"); + $display("%d", dst1_u2s); if (dst1_u2s !== 4'd9) failed = 1; + $display("%d", dst2_u2s); if (dst4_u2s !== 4'd7) failed = 1; + $display("%d", dst3_u2s); if (dst5_u2s !== 4'd9) failed = 1; + $display("%d", dst4_u2s); if (dst2_u2s !== 4'd7) failed = 1; + $display("%d", dst5_u2s); if (dst3_u2s !== 4'd9) failed = 1; + $display("%d", dst6_u2s); if (dst6_u2s !== 4'd7) failed = 1; + $display("%d", dst7_u2s); if (dst7_u2s !== 4'd7) failed = 1; + + $display("cast to small signed bit"); + $display("%d", dst1_s2s); if (dst1_s2s !== -4'sd7) failed = 1; + $display("%d", dst2_s2s); if (dst4_s2s !== 4'sd7) failed = 1; + $display("%d", dst3_s2s); if (dst5_s2s !== -4'sd7) failed = 1; + $display("%d", dst4_s2s); if (dst2_s2s !== 4'sd7) failed = 1; + $display("%d", dst5_s2s); if (dst3_s2s !== -4'sd7) failed = 1; + $display("%d", dst6_s2s); if (dst6_s2s !== 4'sd7) failed = 1; + $display("%d", dst7_s2s); if (dst7_s2s !== 4'sd7) failed = 1; + + $display("cast to large unsigned bit"); + $display("%d", dst1_u2l); if (dst1_u2l !== 12'd4089) failed = 1; + $display("%d", dst2_u2l); if (dst4_u2l !== 12'd7) failed = 1; + $display("%d", dst3_u2l); if (dst5_u2l !== 12'd4089) failed = 1; + $display("%d", dst4_u2l); if (dst2_u2l !== 12'd7) failed = 1; + $display("%d", dst5_u2l); if (dst3_u2l !== 12'd4089) failed = 1; + $display("%b", dst6_u2l); if (dst6_u2l !== 12'b000000000111) failed = 1; + $display("%b", dst7_u2l); if (dst7_u2l !== 12'b000000000111) failed = 1; + + $display("cast to large signed bit"); + $display("%d", dst1_s2l); if (dst1_s2l !== -12'sd7) failed = 1; + $display("%d", dst2_s2l); if (dst4_s2l !== 12'sd7) failed = 1; + $display("%d", dst3_s2l); if (dst5_s2l !== -12'sd7) failed = 1; + $display("%d", dst4_s2l); if (dst2_s2l !== 12'sd7) failed = 1; + $display("%d", dst5_s2l); if (dst3_s2l !== -12'sd7) failed = 1; + $display("%b", dst6_s2l); if (dst6_s2l !== 12'b000000000111) failed = 1; + $display("%b", dst7_s2l); if (dst7_s2l !== 12'b000000000111) failed = 1; +`endif + + $display("cast to small unsigned logic"); + $display("%d", dst1_u4s); if (dst1_u4s !== 4'd9) failed = 1; + $display("%d", dst2_u4s); if (dst4_u4s !== 4'd7) failed = 1; + $display("%d", dst3_u4s); if (dst5_u4s !== 4'd9) failed = 1; + $display("%d", dst4_u4s); if (dst2_u4s !== 4'd7) failed = 1; + $display("%d", dst5_u4s); if (dst3_u4s !== 4'd9) failed = 1; + $display("%d", dst6_u4s); if (dst6_u4s !== 4'd7) failed = 1; + $display("%d", dst7_u4s); if (dst7_u4s !== 4'd7) failed = 1; + + $display("cast to small signed logic"); + $display("%d", dst1_s4s); if (dst1_s4s !== -4'sd7) failed = 1; + $display("%d", dst2_s4s); if (dst4_s4s !== 4'sd7) failed = 1; + $display("%d", dst3_s4s); if (dst5_s4s !== -4'sd7) failed = 1; + $display("%d", dst4_s4s); if (dst2_s4s !== 4'sd7) failed = 1; + $display("%d", dst5_s4s); if (dst3_s4s !== -4'sd7) failed = 1; + $display("%d", dst6_s4s); if (dst6_s4s !== 4'sd7) failed = 1; + $display("%d", dst7_s4s); if (dst7_s4s !== 4'sd7) failed = 1; + + $display("cast to large unsigned logic"); + $display("%d", dst1_u4l); if (dst1_u4l !== 12'd4089) failed = 1; + $display("%d", dst2_u4l); if (dst4_u4l !== 12'd7) failed = 1; + $display("%d", dst3_u4l); if (dst5_u4l !== 12'd4089) failed = 1; + $display("%d", dst4_u4l); if (dst2_u4l !== 12'd7) failed = 1; + $display("%d", dst5_u4l); if (dst3_u4l !== 12'd4089) failed = 1; + $display("%b", dst6_u4l); if (dst6_u4l !== 12'b0000x0z00111) failed = 1; + $display("%b", dst7_u4l); if (dst7_u4l !== 12'bxxxxx0z00111) failed = 1; + + $display("cast to large signed logic"); + $display("%d", dst1_s4l); if (dst1_s4l !== -12'sd7) failed = 1; + $display("%d", dst2_s4l); if (dst4_s4l !== 12'sd7) failed = 1; + $display("%d", dst3_s4l); if (dst5_s4l !== -12'sd7) failed = 1; + $display("%d", dst4_s4l); if (dst2_s4l !== 12'sd7) failed = 1; + $display("%d", dst5_s4l); if (dst3_s4l !== -12'sd7) failed = 1; + $display("%b", dst6_s4l); if (dst6_s4l !== 12'b0000x0z00111) failed = 1; + $display("%b", dst7_s4l); if (dst7_s4l !== 12'bxxxxx0z00111) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/implicit_cast6.v b/ivtest/ivltests/implicit_cast6.v new file mode 100644 index 000000000..faf8e6e55 --- /dev/null +++ b/ivtest/ivltests/implicit_cast6.v @@ -0,0 +1,279 @@ +// Test implicit casts during continuous assignments. + +`ifdef __ICARUS__ + `define SUPPORT_REAL_NETS_IN_IVTEST + `define SUPPORT_TWO_STATE_NETS_IN_IVTEST +`endif + +module implicit_cast(); + +real src_r; + +bit unsigned [7:0] src_u2; +bit signed [7:0] src_s2; + +logic unsigned [7:0] src_u4; +logic signed [7:0] src_s4; + +logic unsigned [7:0] src_ux; +logic signed [7:0] src_sx; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +wire real dst1_r; +wire real dst2_r; +wire real dst3_r; +wire real dst4_r; +wire real dst5_r; +wire real dst6_r; +wire real dst7_r; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +wire bit unsigned [3:0] dst1_u2s; +wire bit unsigned [3:0] dst2_u2s; +wire bit unsigned [3:0] dst3_u2s; +wire bit unsigned [3:0] dst4_u2s; +wire bit unsigned [3:0] dst5_u2s; +wire bit unsigned [3:0] dst6_u2s; +wire bit unsigned [3:0] dst7_u2s; + +wire bit signed [3:0] dst1_s2s; +wire bit signed [3:0] dst2_s2s; +wire bit signed [3:0] dst3_s2s; +wire bit signed [3:0] dst4_s2s; +wire bit signed [3:0] dst5_s2s; +wire bit signed [3:0] dst6_s2s; +wire bit signed [3:0] dst7_s2s; + +wire bit unsigned [11:0] dst1_u2l; +wire bit unsigned [11:0] dst2_u2l; +wire bit unsigned [11:0] dst3_u2l; +wire bit unsigned [11:0] dst4_u2l; +wire bit unsigned [11:0] dst5_u2l; +wire bit unsigned [11:0] dst6_u2l; +wire bit unsigned [11:0] dst7_u2l; + +wire bit signed [11:0] dst1_s2l; +wire bit signed [11:0] dst2_s2l; +wire bit signed [11:0] dst3_s2l; +wire bit signed [11:0] dst4_s2l; +wire bit signed [11:0] dst5_s2l; +wire bit signed [11:0] dst6_s2l; +wire bit signed [11:0] dst7_s2l; +`endif + +wire logic unsigned [3:0] dst1_u4s; +wire logic unsigned [3:0] dst2_u4s; +wire logic unsigned [3:0] dst3_u4s; +wire logic unsigned [3:0] dst4_u4s; +wire logic unsigned [3:0] dst5_u4s; +wire logic unsigned [3:0] dst6_u4s; +wire logic unsigned [3:0] dst7_u4s; + +wire logic signed [3:0] dst1_s4s; +wire logic signed [3:0] dst2_s4s; +wire logic signed [3:0] dst3_s4s; +wire logic signed [3:0] dst4_s4s; +wire logic signed [3:0] dst5_s4s; +wire logic signed [3:0] dst6_s4s; +wire logic signed [3:0] dst7_s4s; + +wire logic unsigned [11:0] dst1_u4l; +wire logic unsigned [11:0] dst2_u4l; +wire logic unsigned [11:0] dst3_u4l; +wire logic unsigned [11:0] dst4_u4l; +wire logic unsigned [11:0] dst5_u4l; +wire logic unsigned [11:0] dst6_u4l; +wire logic unsigned [11:0] dst7_u4l; + +wire logic signed [11:0] dst1_s4l; +wire logic signed [11:0] dst2_s4l; +wire logic signed [11:0] dst3_s4l; +wire logic signed [11:0] dst4_s4l; +wire logic signed [11:0] dst5_s4l; +wire logic signed [11:0] dst6_s4l; +wire logic signed [11:0] dst7_s4l; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST +assign dst1_r = src_r; +assign dst2_r = src_u4; +assign dst3_r = src_s4; +assign dst4_r = src_u2; +assign dst5_r = src_s2; +assign dst6_r = src_ux; +assign dst7_r = src_sx; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST +assign dst1_u2s = src_r; +assign dst2_u2s = src_u4; +assign dst3_u2s = src_s4; +assign dst4_u2s = src_u2; +assign dst5_u2s = src_s2; +assign dst6_u2s = src_ux; +assign dst7_u2s = src_sx; + +assign dst1_s2s = src_r; +assign dst2_s2s = src_u4; +assign dst3_s2s = src_s4; +assign dst4_s2s = src_u2; +assign dst5_s2s = src_s2; +assign dst6_s2s = src_ux; +assign dst7_s2s = src_sx; + +assign dst1_u2l = src_r; +assign dst2_u2l = src_u4; +assign dst3_u2l = src_s4; +assign dst4_u2l = src_u2; +assign dst5_u2l = src_s2; +assign dst6_u2l = src_ux; +assign dst7_u2l = src_sx; + +assign dst1_s2l = src_r; +assign dst2_s2l = src_u4; +assign dst3_s2l = src_s4; +assign dst4_s2l = src_u2; +assign dst5_s2l = src_s2; +assign dst6_s2l = src_ux; +assign dst7_s2l = src_sx; +`endif + +assign dst1_u4s = src_r; +assign dst2_u4s = src_u4; +assign dst3_u4s = src_s4; +assign dst4_u4s = src_u2; +assign dst5_u4s = src_s2; +assign dst6_u4s = src_ux; +assign dst7_u4s = src_sx; + +assign dst1_s4s = src_r; +assign dst2_s4s = src_u4; +assign dst3_s4s = src_s4; +assign dst4_s4s = src_u2; +assign dst5_s4s = src_s2; +assign dst6_s4s = src_ux; +assign dst7_s4s = src_sx; + +assign dst1_u4l = src_r; +assign dst2_u4l = src_u4; +assign dst3_u4l = src_s4; +assign dst4_u4l = src_u2; +assign dst5_u4l = src_s2; +assign dst6_u4l = src_ux; +assign dst7_u4l = src_sx; + +assign dst1_s4l = src_r; +assign dst2_s4l = src_u4; +assign dst3_s4l = src_s4; +assign dst4_s4l = src_u2; +assign dst5_s4l = src_s2; +assign dst6_s4l = src_ux; +assign dst7_s4l = src_sx; + +bit failed; + +initial begin + failed = 0; + + src_r = -7; + src_u2 = 7; + src_s2 = -7; + src_u4 = 7; + src_s4 = -7; + src_ux = 8'bx0z00111; + src_sx = 8'bx0z00111; + + #1; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST + $display("cast to real"); + $display("%g", dst1_r); if (dst1_r != -7.0) failed = 1; + $display("%g", dst2_r); if (dst2_r != 7.0) failed = 1; + $display("%g", dst3_r); if (dst3_r != -7.0) failed = 1; + $display("%g", dst4_r); if (dst4_r != 7.0) failed = 1; + $display("%g", dst5_r); if (dst5_r != -7.0) failed = 1; + $display("%g", dst6_r); if (dst6_r != 7.0) failed = 1; + $display("%g", dst7_r); if (dst7_r != 7.0) failed = 1; +`endif + +`ifdef SUPPORT_TWO_STATE_NETS_IN_IVTEST + $display("cast to small unsigned bit"); + $display("%d", dst1_u2s); if (dst1_u2s !== 4'd9) failed = 1; + $display("%d", dst2_u2s); if (dst2_u2s !== 4'd7) failed = 1; + $display("%d", dst3_u2s); if (dst3_u2s !== 4'd9) failed = 1; + $display("%d", dst4_u2s); if (dst4_u2s !== 4'd7) failed = 1; + $display("%d", dst5_u2s); if (dst5_u2s !== 4'd9) failed = 1; + $display("%d", dst6_u2s); if (dst6_u2s !== 4'd7) failed = 1; + $display("%d", dst7_u2s); if (dst7_u2s !== 4'd7) failed = 1; + + $display("cast to small signed bit"); + $display("%d", dst1_s2s); if (dst1_s2s !== -4'sd7) failed = 1; + $display("%d", dst2_s2s); if (dst2_s2s !== 4'sd7) failed = 1; + $display("%d", dst3_s2s); if (dst3_s2s !== -4'sd7) failed = 1; + $display("%d", dst4_s2s); if (dst4_s2s !== 4'sd7) failed = 1; + $display("%d", dst5_s2s); if (dst5_s2s !== -4'sd7) failed = 1; + $display("%d", dst6_s2s); if (dst6_s2s !== 4'sd7) failed = 1; + $display("%d", dst7_s2s); if (dst7_s2s !== 4'sd7) failed = 1; + + $display("cast to large unsigned bit"); + $display("%d", dst1_u2l); if (dst1_u2l !== 12'd4089) failed = 1; + $display("%d", dst2_u2l); if (dst2_u2l !== 12'd7) failed = 1; + $display("%d", dst3_u2l); if (dst3_u2l !== 12'd4089) failed = 1; + $display("%d", dst4_u2l); if (dst4_u2l !== 12'd7) failed = 1; + $display("%d", dst5_u2l); if (dst5_u2l !== 12'd4089) failed = 1; + $display("%b", dst6_u2l); if (dst6_u2l !== 12'b000000000111) failed = 1; + $display("%b", dst7_u2l); if (dst7_u2l !== 12'b000000000111) failed = 1; + + $display("cast to large signed bit"); + $display("%d", dst1_s2l); if (dst1_s2l !== -12'sd7) failed = 1; + $display("%d", dst2_s2l); if (dst2_s2l !== 12'sd7) failed = 1; + $display("%d", dst3_s2l); if (dst3_s2l !== -12'sd7) failed = 1; + $display("%d", dst4_s2l); if (dst4_s2l !== 12'sd7) failed = 1; + $display("%d", dst5_s2l); if (dst5_s2l !== -12'sd7) failed = 1; + $display("%b", dst6_s2l); if (dst6_s2l !== 12'b000000000111) failed = 1; + $display("%b", dst7_s2l); if (dst7_s2l !== 12'b000000000111) failed = 1; +`endif + + $display("cast to small unsigned logic"); + $display("%d", dst1_u4s); if (dst1_u4s !== 4'd9) failed = 1; + $display("%d", dst2_u4s); if (dst2_u4s !== 4'd7) failed = 1; + $display("%d", dst3_u4s); if (dst3_u4s !== 4'd9) failed = 1; + $display("%d", dst4_u4s); if (dst4_u4s !== 4'd7) failed = 1; + $display("%d", dst5_u4s); if (dst5_u4s !== 4'd9) failed = 1; + $display("%d", dst6_u4s); if (dst6_u4s !== 4'd7) failed = 1; + $display("%d", dst7_u4s); if (dst7_u4s !== 4'd7) failed = 1; + + $display("cast to small signed logic"); + $display("%d", dst1_s4s); if (dst1_s4s !== -4'sd7) failed = 1; + $display("%d", dst2_s4s); if (dst2_s4s !== 4'sd7) failed = 1; + $display("%d", dst3_s4s); if (dst3_s4s !== -4'sd7) failed = 1; + $display("%d", dst4_s4s); if (dst4_s4s !== 4'sd7) failed = 1; + $display("%d", dst5_s4s); if (dst5_s4s !== -4'sd7) failed = 1; + $display("%d", dst6_s4s); if (dst6_s4s !== 4'sd7) failed = 1; + $display("%d", dst7_s4s); if (dst7_s4s !== 4'sd7) failed = 1; + + $display("cast to large unsigned logic"); + $display("%d", dst1_u4l); if (dst1_u4l !== 12'd4089) failed = 1; + $display("%d", dst2_u4l); if (dst2_u4l !== 12'd7) failed = 1; + $display("%d", dst3_u4l); if (dst3_u4l !== 12'd4089) failed = 1; + $display("%d", dst4_u4l); if (dst4_u4l !== 12'd7) failed = 1; + $display("%d", dst5_u4l); if (dst5_u4l !== 12'd4089) failed = 1; + $display("%b", dst6_u4l); if (dst6_u4l !== 12'b0000x0z00111) failed = 1; + $display("%b", dst7_u4l); if (dst7_u4l !== 12'bxxxxx0z00111) failed = 1; + + $display("cast to large signed logic"); + $display("%d", dst1_s4l); if (dst1_s4l !== -12'sd7) failed = 1; + $display("%d", dst2_s4l); if (dst2_s4l !== 12'sd7) failed = 1; + $display("%d", dst3_s4l); if (dst3_s4l !== -12'sd7) failed = 1; + $display("%d", dst4_s4l); if (dst4_s4l !== 12'sd7) failed = 1; + $display("%d", dst5_s4l); if (dst5_s4l !== -12'sd7) failed = 1; + $display("%b", dst6_s4l); if (dst6_s4l !== 12'b0000x0z00111) failed = 1; + $display("%b", dst7_s4l); if (dst7_s4l !== 12'bxxxxx0z00111) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/implicit_cast7.v b/ivtest/ivltests/implicit_cast7.v new file mode 100644 index 000000000..220c785e0 --- /dev/null +++ b/ivtest/ivltests/implicit_cast7.v @@ -0,0 +1,180 @@ +// Test implicit casts during parameter declarations. + +module implicit_cast(); + +localparam real src_r = -7; + +localparam bit unsigned [7:0] src_u2 = 7; +localparam bit signed [7:0] src_s2 = -7; + +localparam logic unsigned [7:0] src_u4 = 7; +localparam logic signed [7:0] src_s4 = -7; + +localparam logic unsigned [7:0] src_ux = 8'bx0z00111; +localparam logic signed [7:0] src_sx = 8'bx0z00111; + +localparam real dst1_r = src_r; +localparam real dst2_r = src_u4; +localparam real dst3_r = src_s4; +localparam real dst4_r = src_u2; +localparam real dst5_r = src_s2; +localparam real dst6_r = src_ux; +localparam real dst7_r = src_sx; + +localparam bit unsigned [3:0] dst1_u2s = src_r; +localparam bit unsigned [3:0] dst2_u2s = src_u4; +localparam bit unsigned [3:0] dst3_u2s = src_s4; +localparam bit unsigned [3:0] dst4_u2s = src_u2; +localparam bit unsigned [3:0] dst5_u2s = src_s2; +localparam bit unsigned [3:0] dst6_u2s = src_ux; +localparam bit unsigned [3:0] dst7_u2s = src_sx; + +localparam bit signed [3:0] dst1_s2s = src_r; +localparam bit signed [3:0] dst2_s2s = src_u4; +localparam bit signed [3:0] dst3_s2s = src_s4; +localparam bit signed [3:0] dst4_s2s = src_u2; +localparam bit signed [3:0] dst5_s2s = src_s2; +localparam bit signed [3:0] dst6_s2s = src_ux; +localparam bit signed [3:0] dst7_s2s = src_sx; + +localparam bit unsigned [11:0] dst1_u2l = src_r; +localparam bit unsigned [11:0] dst2_u2l = src_u4; +localparam bit unsigned [11:0] dst3_u2l = src_s4; +localparam bit unsigned [11:0] dst4_u2l = src_u2; +localparam bit unsigned [11:0] dst5_u2l = src_s2; +localparam bit unsigned [11:0] dst6_u2l = src_ux; +localparam bit unsigned [11:0] dst7_u2l = src_sx; + +localparam bit signed [11:0] dst1_s2l = src_r; +localparam bit signed [11:0] dst2_s2l = src_u4; +localparam bit signed [11:0] dst3_s2l = src_s4; +localparam bit signed [11:0] dst4_s2l = src_u2; +localparam bit signed [11:0] dst5_s2l = src_s2; +localparam bit signed [11:0] dst6_s2l = src_ux; +localparam bit signed [11:0] dst7_s2l = src_sx; + +localparam logic unsigned [3:0] dst1_u4s = src_r; +localparam logic unsigned [3:0] dst2_u4s = src_u4; +localparam logic unsigned [3:0] dst3_u4s = src_s4; +localparam logic unsigned [3:0] dst4_u4s = src_u2; +localparam logic unsigned [3:0] dst5_u4s = src_s2; +localparam logic unsigned [3:0] dst6_u4s = src_ux; +localparam logic unsigned [3:0] dst7_u4s = src_sx; + +localparam logic signed [3:0] dst1_s4s = src_r; +localparam logic signed [3:0] dst2_s4s = src_u4; +localparam logic signed [3:0] dst3_s4s = src_s4; +localparam logic signed [3:0] dst4_s4s = src_u2; +localparam logic signed [3:0] dst5_s4s = src_s2; +localparam logic signed [3:0] dst6_s4s = src_ux; +localparam logic signed [3:0] dst7_s4s = src_sx; + +localparam logic unsigned [11:0] dst1_u4l = src_r; +localparam logic unsigned [11:0] dst2_u4l = src_u4; +localparam logic unsigned [11:0] dst3_u4l = src_s4; +localparam logic unsigned [11:0] dst4_u4l = src_u2; +localparam logic unsigned [11:0] dst5_u4l = src_s2; +localparam logic unsigned [11:0] dst6_u4l = src_ux; +localparam logic unsigned [11:0] dst7_u4l = src_sx; + +localparam logic signed [11:0] dst1_s4l = src_r; +localparam logic signed [11:0] dst2_s4l = src_u4; +localparam logic signed [11:0] dst3_s4l = src_s4; +localparam logic signed [11:0] dst4_s4l = src_u2; +localparam logic signed [11:0] dst5_s4l = src_s2; +localparam logic signed [11:0] dst6_s4l = src_ux; +localparam logic signed [11:0] dst7_s4l = src_sx; + +bit failed; + +initial begin + failed = 0; + + $display("cast to real"); + $display("%g", dst1_r); if (dst1_r != -7.0) failed = 1; + $display("%g", dst2_r); if (dst2_r != 7.0) failed = 1; + $display("%g", dst3_r); if (dst3_r != -7.0) failed = 1; + $display("%g", dst4_r); if (dst4_r != 7.0) failed = 1; + $display("%g", dst5_r); if (dst5_r != -7.0) failed = 1; + $display("%g", dst6_r); if (dst6_r != 7.0) failed = 1; + $display("%g", dst7_r); if (dst7_r != 7.0) failed = 1; + + $display("cast to small unsigned bit"); + $display("%d", dst1_u2s); if (dst1_u2s !== 4'd9) failed = 1; + $display("%d", dst2_u2s); if (dst2_u2s !== 4'd7) failed = 1; + $display("%d", dst3_u2s); if (dst3_u2s !== 4'd9) failed = 1; + $display("%d", dst4_u2s); if (dst4_u2s !== 4'd7) failed = 1; + $display("%d", dst5_u2s); if (dst5_u2s !== 4'd9) failed = 1; + $display("%d", dst6_u2s); if (dst6_u2s !== 4'd7) failed = 1; + $display("%d", dst7_u2s); if (dst7_u2s !== 4'd7) failed = 1; + + $display("cast to small signed bit"); + $display("%d", dst1_s2s); if (dst1_s2s !== -4'sd7) failed = 1; + $display("%d", dst2_s2s); if (dst2_s2s !== 4'sd7) failed = 1; + $display("%d", dst3_s2s); if (dst3_s2s !== -4'sd7) failed = 1; + $display("%d", dst4_s2s); if (dst4_s2s !== 4'sd7) failed = 1; + $display("%d", dst5_s2s); if (dst5_s2s !== -4'sd7) failed = 1; + $display("%d", dst6_s2s); if (dst6_s2s !== 4'sd7) failed = 1; + $display("%d", dst7_s2s); if (dst7_s2s !== 4'sd7) failed = 1; + + $display("cast to large unsigned bit"); + $display("%d", dst1_u2l); if (dst1_u2l !== 12'd4089) failed = 1; + $display("%d", dst2_u2l); if (dst2_u2l !== 12'd7) failed = 1; + $display("%d", dst3_u2l); if (dst3_u2l !== 12'd4089) failed = 1; + $display("%d", dst4_u2l); if (dst4_u2l !== 12'd7) failed = 1; + $display("%d", dst5_u2l); if (dst5_u2l !== 12'd4089) failed = 1; + $display("%b", dst6_u2l); if (dst6_u2l !== 12'b000000000111) failed = 1; + $display("%b", dst7_u2l); if (dst7_u2l !== 12'b000000000111) failed = 1; + + $display("cast to large signed bit"); + $display("%d", dst1_s2l); if (dst1_s2l !== -12'sd7) failed = 1; + $display("%d", dst2_s2l); if (dst2_s2l !== 12'sd7) failed = 1; + $display("%d", dst3_s2l); if (dst3_s2l !== -12'sd7) failed = 1; + $display("%d", dst4_s2l); if (dst4_s2l !== 12'sd7) failed = 1; + $display("%d", dst5_s2l); if (dst5_s2l !== -12'sd7) failed = 1; + $display("%b", dst6_s2l); if (dst6_s2l !== 12'b000000000111) failed = 1; + $display("%b", dst7_s2l); if (dst7_s2l !== 12'b000000000111) failed = 1; + + $display("cast to small unsigned logic"); + $display("%d", dst1_u4s); if (dst1_u4s !== 4'd9) failed = 1; + $display("%d", dst2_u4s); if (dst2_u4s !== 4'd7) failed = 1; + $display("%d", dst3_u4s); if (dst3_u4s !== 4'd9) failed = 1; + $display("%d", dst4_u4s); if (dst4_u4s !== 4'd7) failed = 1; + $display("%d", dst5_u4s); if (dst5_u4s !== 4'd9) failed = 1; + $display("%d", dst6_u4s); if (dst6_u4s !== 4'd7) failed = 1; + $display("%d", dst7_u4s); if (dst7_u4s !== 4'd7) failed = 1; + + $display("cast to small signed logic"); + $display("%d", dst1_s4s); if (dst1_s4s !== -4'sd7) failed = 1; + $display("%d", dst2_s4s); if (dst2_s4s !== 4'sd7) failed = 1; + $display("%d", dst3_s4s); if (dst3_s4s !== -4'sd7) failed = 1; + $display("%d", dst4_s4s); if (dst4_s4s !== 4'sd7) failed = 1; + $display("%d", dst5_s4s); if (dst5_s4s !== -4'sd7) failed = 1; + $display("%d", dst6_s4s); if (dst6_s4s !== 4'sd7) failed = 1; + $display("%d", dst7_s4s); if (dst7_s4s !== 4'sd7) failed = 1; + + $display("cast to large unsigned logic"); + $display("%d", dst1_u4l); if (dst1_u4l !== 12'd4089) failed = 1; + $display("%d", dst2_u4l); if (dst2_u4l !== 12'd7) failed = 1; + $display("%d", dst3_u4l); if (dst3_u4l !== 12'd4089) failed = 1; + $display("%d", dst4_u4l); if (dst4_u4l !== 12'd7) failed = 1; + $display("%d", dst5_u4l); if (dst5_u4l !== 12'd4089) failed = 1; + $display("%b", dst6_u4l); if (dst6_u4l !== 12'b0000x0z00111) failed = 1; + $display("%b", dst7_u4l); if (dst7_u4l !== 12'bxxxxx0z00111) failed = 1; + + $display("cast to large signed logic"); + $display("%d", dst1_s4l); if (dst1_s4l !== -12'sd7) failed = 1; + $display("%d", dst2_s4l); if (dst2_s4l !== 12'sd7) failed = 1; + $display("%d", dst3_s4l); if (dst3_s4l !== -12'sd7) failed = 1; + $display("%d", dst4_s4l); if (dst4_s4l !== 12'sd7) failed = 1; + $display("%d", dst5_s4l); if (dst5_s4l !== -12'sd7) failed = 1; + $display("%b", dst6_s4l); if (dst6_s4l !== 12'b0000x0z00111) failed = 1; + $display("%b", dst7_s4l); if (dst7_s4l !== 12'bxxxxx0z00111) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/implicit_cast8.v b/ivtest/ivltests/implicit_cast8.v new file mode 100644 index 000000000..09471e863 --- /dev/null +++ b/ivtest/ivltests/implicit_cast8.v @@ -0,0 +1,166 @@ +// Test implicit casts during function input assignments. + +module implicit_cast(); + +real src_r; + +bit unsigned [7:0] src_u2; +bit signed [7:0] src_s2; + +logic unsigned [7:0] src_u4; +logic signed [7:0] src_s4; + +logic unsigned [7:0] src_ux; +logic signed [7:0] src_sx; + +real dst_r; + +bit unsigned [3:0] dst_u2s; +bit signed [3:0] dst_s2s; + +bit unsigned [11:0] dst_u2l; +bit signed [11:0] dst_s2l; + +logic unsigned [3:0] dst_u4s; +logic signed [3:0] dst_s4s; + +logic unsigned [11:0] dst_u4l; +logic signed [11:0] dst_s4l; + +function real cp_r(input real val); + cp_r = val; +endfunction + +function bit unsigned [3:0] cp_u2s(input bit unsigned [3:0] val); + cp_u2s = val; +endfunction + +function bit signed [3:0] cp_s2s(input bit signed [3:0] val); + cp_s2s = val; +endfunction + +function bit unsigned [11:0] cp_u2l(input bit unsigned [11:0] val); + cp_u2l = val; +endfunction + +function bit signed [11:0] cp_s2l(input bit signed [11:0] val); + cp_s2l = val; +endfunction + +function logic unsigned [3:0] cp_u4s(input logic unsigned [3:0] val); + cp_u4s = val; +endfunction + +function logic signed [3:0] cp_s4s(input logic signed [3:0] val); + cp_s4s = val; +endfunction + +function logic unsigned [11:0] cp_u4l(input logic unsigned [11:0] val); + cp_u4l = val; +endfunction + +function logic signed [11:0] cp_s4l(input logic signed [11:0] val); + cp_s4l = val; +endfunction + +bit failed; + +initial begin + failed = 0; + + src_r = -7; + src_u2 = 7; + src_s2 = -7; + src_u4 = 7; + src_s4 = -7; + src_ux = 8'bx0z00111; + src_sx = 8'bx0z00111; + + $display("cast to real"); + dst_r = cp_r(src_r); $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + dst_r = cp_r(src_u2); $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + dst_r = cp_r(src_s2); $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + dst_r = cp_r(src_u4); $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + dst_r = cp_r(src_s4); $display("%g", dst_r); if (dst_r != -7.0) failed = 1; + dst_r = cp_r(src_ux); $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + dst_r = cp_r(src_sx); $display("%g", dst_r); if (dst_r != 7.0) failed = 1; + + $display("cast to small unsigned bit"); + dst_u2s = cp_u2s(src_r); $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + dst_u2s = cp_u2s(src_u2); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + dst_u2s = cp_u2s(src_s2); $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + dst_u2s = cp_u2s(src_u4); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + dst_u2s = cp_u2s(src_s4); $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1; + dst_u2s = cp_u2s(src_ux); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + dst_u2s = cp_u2s(src_sx); $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1; + + $display("cast to small signed bit"); + dst_s2s = cp_s2s(src_r); $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + dst_s2s = cp_s2s(src_u2); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + dst_s2s = cp_s2s(src_s2); $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + dst_s2s = cp_s2s(src_u4); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + dst_s2s = cp_s2s(src_s4); $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1; + dst_s2s = cp_s2s(src_ux); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + dst_s2s = cp_s2s(src_sx); $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1; + + $display("cast to large unsigned bit"); + dst_u2l = cp_u2l(src_r); $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + dst_u2l = cp_u2l(src_u2); $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1; + dst_u2l = cp_u2l(src_s2); $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + dst_u2l = cp_u2l(src_u4); $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1; + dst_u2l = cp_u2l(src_s4); $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1; + dst_u2l = cp_u2l(src_ux); $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1; + dst_u2l = cp_u2l(src_sx); $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1; + + $display("cast to large signed bit"); + dst_s2l = cp_s2l(src_r); $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + dst_s2l = cp_s2l(src_u2); $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1; + dst_s2l = cp_s2l(src_s2); $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + dst_s2l = cp_s2l(src_u4); $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1; + dst_s2l = cp_s2l(src_s4); $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1; + dst_s2l = cp_s2l(src_ux); $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1; + dst_s2l = cp_s2l(src_sx); $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1; + + $display("cast to small unsigned logic"); + dst_u4s = cp_u4s(src_r); $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + dst_u4s = cp_u4s(src_u2); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + dst_u4s = cp_u4s(src_s2); $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + dst_u4s = cp_u4s(src_u4); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + dst_u4s = cp_u4s(src_s4); $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1; + dst_u4s = cp_u4s(src_ux); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + dst_u4s = cp_u4s(src_sx); $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1; + + $display("cast to small signed logic"); + dst_s4s = cp_s4s(src_r); $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + dst_s4s = cp_s4s(src_u2); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + dst_s4s = cp_s4s(src_s2); $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + dst_s4s = cp_s4s(src_u4); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + dst_s4s = cp_s4s(src_s4); $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1; + dst_s4s = cp_s4s(src_ux); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + dst_s4s = cp_s4s(src_sx); $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1; + + $display("cast to large unsigned logic"); + dst_u4l = cp_u4l(src_r); $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + dst_u4l = cp_u4l(src_u2); $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1; + dst_u4l = cp_u4l(src_s2); $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + dst_u4l = cp_u4l(src_u4); $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1; + dst_u4l = cp_u4l(src_s4); $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1; + dst_u4l = cp_u4l(src_ux); $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1; + dst_u4l = cp_u4l(src_sx); $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1; + + $display("cast to large signed logic"); + dst_s4l = cp_s4l(src_r); $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + dst_s4l = cp_s4l(src_u2); $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1; + dst_s4l = cp_s4l(src_s2); $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + dst_s4l = cp_s4l(src_u4); $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1; + dst_s4l = cp_s4l(src_s4); $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1; + dst_s4l = cp_s4l(src_ux); $display("%b", dst_s4l); if (dst_s4l !== 12'b0000x0z00111) failed = 1; + dst_s4l = cp_s4l(src_sx); $display("%b", dst_s4l); if (dst_s4l !== 12'bxxxxx0z00111) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/implicit_cast9.v b/ivtest/ivltests/implicit_cast9.v new file mode 100644 index 000000000..b6b22b732 --- /dev/null +++ b/ivtest/ivltests/implicit_cast9.v @@ -0,0 +1,216 @@ +// Test implicit casts during constant function input assignments. + +module implicit_cast(); + +localparam real src_r = -7; + +localparam bit unsigned [7:0] src_u2 = 7; +localparam bit signed [7:0] src_s2 = -7; + +localparam logic unsigned [7:0] src_u4 = 7; +localparam logic signed [7:0] src_s4 = -7; + +localparam logic unsigned [7:0] src_ux = 8'bx0z00111; +localparam logic signed [7:0] src_sx = 8'bx0z00111; + +function real cp_r(input real val); + cp_r = val; +endfunction + +function bit unsigned [3:0] cp_u2s(input bit unsigned [3:0] val); + cp_u2s = val; +endfunction + +function bit signed [3:0] cp_s2s(input bit signed [3:0] val); + cp_s2s = val; +endfunction + +function bit unsigned [11:0] cp_u2l(input bit unsigned [11:0] val); + cp_u2l = val; +endfunction + +function bit signed [11:0] cp_s2l(input bit signed [11:0] val); + cp_s2l = val; +endfunction + +function logic unsigned [3:0] cp_u4s(input logic unsigned [3:0] val); + cp_u4s = val; +endfunction + +function logic signed [3:0] cp_s4s(input logic signed [3:0] val); + cp_s4s = val; +endfunction + +function logic unsigned [11:0] cp_u4l(input logic unsigned [11:0] val); + cp_u4l = val; +endfunction + +function logic signed [11:0] cp_s4l(input logic signed [11:0] val); + cp_s4l = val; +endfunction + +localparam dst1_r = cp_r(src_r); +localparam dst2_r = cp_r(src_u4); +localparam dst3_r = cp_r(src_s4); +localparam dst4_r = cp_r(src_u2); +localparam dst5_r = cp_r(src_s2); +localparam dst6_r = cp_r(src_ux); +localparam dst7_r = cp_r(src_sx); + +localparam dst1_u2s = cp_u2s(src_r); +localparam dst2_u2s = cp_u2s(src_u4); +localparam dst3_u2s = cp_u2s(src_s4); +localparam dst4_u2s = cp_u2s(src_u2); +localparam dst5_u2s = cp_u2s(src_s2); +localparam dst6_u2s = cp_u2s(src_ux); +localparam dst7_u2s = cp_u2s(src_sx); + +localparam dst1_s2s = cp_s2s(src_r); +localparam dst2_s2s = cp_s2s(src_u4); +localparam dst3_s2s = cp_s2s(src_s4); +localparam dst4_s2s = cp_s2s(src_u2); +localparam dst5_s2s = cp_s2s(src_s2); +localparam dst6_s2s = cp_s2s(src_ux); +localparam dst7_s2s = cp_s2s(src_sx); + +localparam dst1_u2l = cp_u2l(src_r); +localparam dst2_u2l = cp_u2l(src_u4); +localparam dst3_u2l = cp_u2l(src_s4); +localparam dst4_u2l = cp_u2l(src_u2); +localparam dst5_u2l = cp_u2l(src_s2); +localparam dst6_u2l = cp_u2l(src_ux); +localparam dst7_u2l = cp_u2l(src_sx); + +localparam dst1_s2l = cp_s2l(src_r); +localparam dst2_s2l = cp_s2l(src_u4); +localparam dst3_s2l = cp_s2l(src_s4); +localparam dst4_s2l = cp_s2l(src_u2); +localparam dst5_s2l = cp_s2l(src_s2); +localparam dst6_s2l = cp_s2l(src_ux); +localparam dst7_s2l = cp_s2l(src_sx); + +localparam dst1_u4s = cp_u4s(src_r); +localparam dst2_u4s = cp_u4s(src_u4); +localparam dst3_u4s = cp_u4s(src_s4); +localparam dst4_u4s = cp_u4s(src_u2); +localparam dst5_u4s = cp_u4s(src_s2); +localparam dst6_u4s = cp_u4s(src_ux); +localparam dst7_u4s = cp_u4s(src_sx); + +localparam dst1_s4s = cp_s4s(src_r); +localparam dst2_s4s = cp_s4s(src_u4); +localparam dst3_s4s = cp_s4s(src_s4); +localparam dst4_s4s = cp_s4s(src_u2); +localparam dst5_s4s = cp_s4s(src_s2); +localparam dst6_s4s = cp_s4s(src_ux); +localparam dst7_s4s = cp_s4s(src_sx); + +localparam dst1_u4l = cp_u4l(src_r); +localparam dst2_u4l = cp_u4l(src_u4); +localparam dst3_u4l = cp_u4l(src_s4); +localparam dst4_u4l = cp_u4l(src_u2); +localparam dst5_u4l = cp_u4l(src_s2); +localparam dst6_u4l = cp_u4l(src_ux); +localparam dst7_u4l = cp_u4l(src_sx); + +localparam dst1_s4l = cp_s4l(src_r); +localparam dst2_s4l = cp_s4l(src_u4); +localparam dst3_s4l = cp_s4l(src_s4); +localparam dst4_s4l = cp_s4l(src_u2); +localparam dst5_s4l = cp_s4l(src_s2); +localparam dst6_s4l = cp_s4l(src_ux); +localparam dst7_s4l = cp_s4l(src_sx); + +bit failed; + +initial begin + failed = 0; + + $display("cast to real"); + $display("%g", dst1_r); if (dst1_r != -7.0) failed = 1; + $display("%g", dst2_r); if (dst2_r != 7.0) failed = 1; + $display("%g", dst3_r); if (dst3_r != -7.0) failed = 1; + $display("%g", dst4_r); if (dst4_r != 7.0) failed = 1; + $display("%g", dst5_r); if (dst5_r != -7.0) failed = 1; + $display("%g", dst6_r); if (dst6_r != 7.0) failed = 1; + $display("%g", dst7_r); if (dst7_r != 7.0) failed = 1; + + $display("cast to small unsigned bit"); + $display("%d", dst1_u2s); if (dst1_u2s !== 4'd9) failed = 1; + $display("%d", dst2_u2s); if (dst2_u2s !== 4'd7) failed = 1; + $display("%d", dst3_u2s); if (dst3_u2s !== 4'd9) failed = 1; + $display("%d", dst4_u2s); if (dst4_u2s !== 4'd7) failed = 1; + $display("%d", dst5_u2s); if (dst5_u2s !== 4'd9) failed = 1; + $display("%d", dst6_u2s); if (dst6_u2s !== 4'd7) failed = 1; + $display("%d", dst7_u2s); if (dst7_u2s !== 4'd7) failed = 1; + + $display("cast to small signed bit"); + $display("%d", dst1_s2s); if (dst1_s2s !== -4'sd7) failed = 1; + $display("%d", dst2_s2s); if (dst2_s2s !== 4'sd7) failed = 1; + $display("%d", dst3_s2s); if (dst3_s2s !== -4'sd7) failed = 1; + $display("%d", dst4_s2s); if (dst4_s2s !== 4'sd7) failed = 1; + $display("%d", dst5_s2s); if (dst5_s2s !== -4'sd7) failed = 1; + $display("%d", dst6_s2s); if (dst6_s2s !== 4'sd7) failed = 1; + $display("%d", dst7_s2s); if (dst7_s2s !== 4'sd7) failed = 1; + + $display("cast to large unsigned bit"); + $display("%d", dst1_u2l); if (dst1_u2l !== 12'd4089) failed = 1; + $display("%d", dst2_u2l); if (dst2_u2l !== 12'd7) failed = 1; + $display("%d", dst3_u2l); if (dst3_u2l !== 12'd4089) failed = 1; + $display("%d", dst4_u2l); if (dst4_u2l !== 12'd7) failed = 1; + $display("%d", dst5_u2l); if (dst5_u2l !== 12'd4089) failed = 1; + $display("%b", dst6_u2l); if (dst6_u2l !== 12'b000000000111) failed = 1; + $display("%b", dst7_u2l); if (dst7_u2l !== 12'b000000000111) failed = 1; + + $display("cast to large signed bit"); + $display("%d", dst1_s2l); if (dst1_s2l !== -12'sd7) failed = 1; + $display("%d", dst2_s2l); if (dst2_s2l !== 12'sd7) failed = 1; + $display("%d", dst3_s2l); if (dst3_s2l !== -12'sd7) failed = 1; + $display("%d", dst4_s2l); if (dst4_s2l !== 12'sd7) failed = 1; + $display("%d", dst5_s2l); if (dst5_s2l !== -12'sd7) failed = 1; + $display("%b", dst6_s2l); if (dst6_s2l !== 12'b000000000111) failed = 1; + $display("%b", dst7_s2l); if (dst7_s2l !== 12'b000000000111) failed = 1; + + $display("cast to small unsigned logic"); + $display("%d", dst1_u4s); if (dst1_u4s !== 4'd9) failed = 1; + $display("%d", dst2_u4s); if (dst2_u4s !== 4'd7) failed = 1; + $display("%d", dst3_u4s); if (dst3_u4s !== 4'd9) failed = 1; + $display("%d", dst4_u4s); if (dst4_u4s !== 4'd7) failed = 1; + $display("%d", dst5_u4s); if (dst5_u4s !== 4'd9) failed = 1; + $display("%d", dst6_u4s); if (dst6_u4s !== 4'd7) failed = 1; + $display("%d", dst7_u4s); if (dst7_u4s !== 4'd7) failed = 1; + + $display("cast to small signed logic"); + $display("%d", dst1_s4s); if (dst1_s4s !== -4'sd7) failed = 1; + $display("%d", dst2_s4s); if (dst2_s4s !== 4'sd7) failed = 1; + $display("%d", dst3_s4s); if (dst3_s4s !== -4'sd7) failed = 1; + $display("%d", dst4_s4s); if (dst4_s4s !== 4'sd7) failed = 1; + $display("%d", dst5_s4s); if (dst5_s4s !== -4'sd7) failed = 1; + $display("%d", dst6_s4s); if (dst6_s4s !== 4'sd7) failed = 1; + $display("%d", dst7_s4s); if (dst7_s4s !== 4'sd7) failed = 1; + + $display("cast to large unsigned logic"); + $display("%d", dst1_u4l); if (dst1_u4l !== 12'd4089) failed = 1; + $display("%d", dst2_u4l); if (dst2_u4l !== 12'd7) failed = 1; + $display("%d", dst3_u4l); if (dst3_u4l !== 12'd4089) failed = 1; + $display("%d", dst4_u4l); if (dst4_u4l !== 12'd7) failed = 1; + $display("%d", dst5_u4l); if (dst5_u4l !== 12'd4089) failed = 1; + $display("%b", dst6_u4l); if (dst6_u4l !== 12'b0000x0z00111) failed = 1; + $display("%b", dst7_u4l); if (dst7_u4l !== 12'bxxxxx0z00111) failed = 1; + + $display("cast to large signed logic"); + $display("%d", dst1_s4l); if (dst1_s4l !== -12'sd7) failed = 1; + $display("%d", dst2_s4l); if (dst2_s4l !== 12'sd7) failed = 1; + $display("%d", dst3_s4l); if (dst3_s4l !== -12'sd7) failed = 1; + $display("%d", dst4_s4l); if (dst4_s4l !== 12'sd7) failed = 1; + $display("%d", dst5_s4l); if (dst5_s4l !== -12'sd7) failed = 1; + $display("%b", dst6_s4l); if (dst6_s4l !== 12'b0000x0z00111) failed = 1; + $display("%b", dst7_s4l); if (dst7_s4l !== 12'bxxxxx0z00111) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/inc_dec_stmt.v b/ivtest/ivltests/inc_dec_stmt.v new file mode 100644 index 000000000..12ec55849 --- /dev/null +++ b/ivtest/ivltests/inc_dec_stmt.v @@ -0,0 +1,25 @@ +module main; + + int foo; + + initial begin + foo = 1; + foo ++; + ++ foo; + if (foo !== 3) begin + $display("FAILED -- foo=%0d", foo); + $finish; + end + + foo --; + -- foo; + if (foo !== 1) begin + $display("FAILED -- foo=%0d", foo); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/include1.v b/ivtest/ivltests/include1.v new file mode 100644 index 000000000..53bea1ec9 --- /dev/null +++ b/ivtest/ivltests/include1.v @@ -0,0 +1,22 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - include a single file +// + +`include "ivltests/else3.v" diff --git a/ivtest/ivltests/include2.v b/ivtest/ivltests/include2.v new file mode 100644 index 000000000..dd1dff9f6 --- /dev/null +++ b/ivtest/ivltests/include2.v @@ -0,0 +1,22 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - include a two levels deep +// + +`include "ivltests/include1.v" diff --git a/ivtest/ivltests/include3.v b/ivtest/ivltests/include3.v new file mode 100644 index 000000000..3ef8ff881 --- /dev/null +++ b/ivtest/ivltests/include3.v @@ -0,0 +1,22 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - include is three levels deep +// + +`include "ivltests/include2.v" diff --git a/ivtest/ivltests/indef_width_concat.v b/ivtest/ivltests/indef_width_concat.v new file mode 100644 index 000000000..810dd3a01 --- /dev/null +++ b/ivtest/ivltests/indef_width_concat.v @@ -0,0 +1,5 @@ +module top; + parameter pval = 1; + + initial $display("Concat: %d", {pval, 2}); +endmodule diff --git a/ivtest/ivltests/initmod.v b/ivtest/ivltests/initmod.v new file mode 100644 index 000000000..6b77c720d --- /dev/null +++ b/ivtest/ivltests/initmod.v @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2000 Yasuhisa Kato + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module busm ( clk, iB, oB ); + input clk ; + input [3:0] iB ; + output [3:0] oB ; + reg [3:0] r ; + + assign oB = r ; + always @(posedge clk) r <= iB ; + +endmodule + +module main; + reg a, b, c, d ; + + reg clk ; + initial begin clk = 0 ; forever #5 clk = ~clk ; end + initial begin a = 0 ; c = 0 ; #100 $finish(0); end + + wire e0, f0, g0, h0 ; + wire e, f, g, h ; + wire [3:0] ii, oo ; + + always @(posedge clk) a <= ~a ; + always @(posedge clk) b <= a ; + always @(posedge clk) c <= c ^ a ; + always @(posedge clk) d <= ~c ; + + assign ii = {a, b, c, d} ; + assign {e0, f0, g0, h0} = oo ; + + busm M0 ( clk, ii, oo ); + busm M1 ( clk, {a,b,c,d}, {e,f,g,h} ); + + always @(posedge clk) + $display("%h %h %h %h : %b : %h %h %h %h : %b : %h %h %h %h", + a, b, c, d, M0.r, e0, f0, g0, h0, + M1.r, e, f, g, h + + ); + +endmodule + +// expecting result +// 0 x 0 x : xxxx : z z z z : xxxx : z z z z +// 1 0 0 1 : 0z0z : 0 z 0 z : 0z0z : 0 z 0 z +// 0 1 1 1 : 1001 : 1 0 0 1 : 1001 : 1 0 0 1 +// 1 0 1 0 : 0111 : 0 1 1 1 : 0111 : 0 1 1 1 +// 0 1 0 0 : 1010 : 1 0 1 0 : 1010 : 1 0 1 0 +// 1 0 0 1 : 0100 : 0 1 0 0 : 0100 : 0 1 0 0 +// 0 1 1 1 : 1001 : 1 0 0 1 : 1001 : 1 0 0 1 +// 1 0 1 0 : 0111 : 0 1 1 1 : 0111 : 0 1 1 1 +// 0 1 0 0 : 1010 : 1 0 1 0 : 1010 : 1 0 1 0 +// 1 0 0 1 : 0100 : 0 1 0 0 : 0100 : 0 1 0 0 diff --git a/ivtest/ivltests/initmod2.v b/ivtest/ivltests/initmod2.v new file mode 100644 index 000000000..de0d1b993 --- /dev/null +++ b/ivtest/ivltests/initmod2.v @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2000 Yasuhisa Kato + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// Modified my stevew@home.com to be self-checking per the comments. + +module main; + + reg clk ; + initial begin clk = 0 ; forever #5 clk = ~clk ; end + initial #20 $finish; + + wire w, ww, wr, w1, wwr, ww1, wr1, wwro, ww1o, wr1o ; + reg r, rw ; + reg error; + + // z <- (z) = z + assign ww = w ; // z <- (z) = z + assign wr = r ; // x <- (z) = x + assign w1 = 'b1 ; // 1 <- (z) = 1 + assign wwr = w & r ; // x <- z & x + assign ww1 = w & 'b1 ; // x <- z & 1 + assign wr1 = r & 'b1 ; // x <- x & 1 + + assign wwro= w | r ; // x <- z | x + assign ww1o= w | 'b1 ; // 1 <- z | 1 + assign wr1o= r | 'b1 ; // 1 <- x | 1 + + always @(posedge clk) + rw <= w ; // x <- (x) = z + + always @(posedge clk) + begin + #1; + $display("%b %b %b %b %b %b %b : %b %b %b : %b %b", + w, ww, wr, w1, wwr, ww1, wr1, wwro, ww1o, wr1o, r, rw ); + end + +initial + begin + error = 0; + #19; + if(ww !== 1'bz) begin + error = 1; + $display("FAILED - ww s/b z, is %h",ww); + end + if(wr !== 1'bx) begin + error = 1; + $display("FAILED - wr s/b x, is %h",wr); + end + if(w1 !== 1'b1) begin + error = 1; + $display("FAILED - wr s/b 1, is %h",wr); + end + if(wwr !== 1'bx) begin + error = 1; + $display("FAILED - wwr s/b x, is %h",wwr); + end + if(ww1 !== 1'bx) begin + error = 1; + $display("FAILED - ww1 s/b x, is %h",ww1); + end + if(wr1 !== 1'bx) begin + error = 1; + $display("FAILED - wr1 s/b x, is %h",wr1); + end + if(wwro !== 1'bx) begin + error = 1; + $display("FAILED - wwro s/b 1, is %h",wwro); + end + if(wr1o !== 1'b1) begin + error = 1; + $display("FAILED - wr1o s/b 1, is %h",wr1o); + end + if(r !== 1'bx) begin + error = 1; + $display("FAILED - r s/b x, is %h",r); + end + if(r !== 1'bx) begin + error = 1; + $display("FAILED - r s/b x, is %h",r); + end + if(rw !== 1'bz) begin + error = 1; + $display("FAILED - rw s/b z, is %h",r); + end + if(error === 0) + $display("PASSED"); + $finish(0); + end + +endmodule + +// *Initial Value Test* + +// expected output - This according to XL +// z z x 1 x x x : x 1 1 : x x +// z z x 1 x x x : x 1 1 : x z + +// ivl current result +// z z x 1 x z x : x 1 1 : x x +// z z x 1 x z x : x 1 1 : x z diff --git a/ivtest/ivltests/inout.v b/ivtest/ivltests/inout.v new file mode 100644 index 000000000..387158d9b --- /dev/null +++ b/ivtest/ivltests/inout.v @@ -0,0 +1,105 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate inout with id(a,a) inout a; definition. + +module id(a,a); +inout a; +endmodule + +module top (); + +wire b,c; + +id i1(b,c); + +reg a, error, ena_a,ena_b; + +assign c = ena_a ? a : 1'bz; +assign b = ena_b ? a : 1'bz; + +initial + begin + error = 0; + ena_a = 1'b0; + ena_b = 1'b0; + #1 ; + ena_a = 1'b1; + #1 ; + a= 0; + #1; + if(b !== 1'b0) + begin + error = 1; + $display("FAILED - b init value not 1'b0 a=%b,b=%b,c=%b",a,b,c); + end + if(c !== 1'b0) + begin + error = 1; + $display("FAILED - c init value not 1'b0 a=%b,b=%b,c=%b",a,b,c); + end + #1 ; + a= 1; + #1; + if(b !== 1'b1) + begin + error = 1; + $display("FAILED - b init value not 1'b1 a=%b,b=%b,c=%b",a,b,c); + end + if(c !== 1'b1) + begin + error = 1; + $display("FAILED - c init value not 1'b1 a=%b,b=%b,c=%b",a,b,c); + end + #1 ; + ena_a = 1'b0; + #1 ; + ena_b = 1'b1; + #1 ; + a= 0; + #1; + if(b !== 1'b0) + begin + error = 1; + $display("FAILED - b init value not 1'b0 a=%b,b=%b,c=%b",a,b,c); + end + if(c !== 1'b0) + begin + error = 1; + $display("FAILED - c init value not 1'b0 a=%b,b=%b,c=%b",a,b,c); + end + #1 ; + a= 1; + #1; + if(b !== 1'b1) + begin + error = 1; + $display("FAILED - b init value not 1'b1 a=%b,b=%b,c=%b",a,b,c); + end + if(c !== 1'b1) + begin + error = 1; + $display("FAILED - c init value not 1'b1 a=%b,b=%b,c=%b",a,b,c); + end + + + if(error == 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/inout2.v b/ivtest/ivltests/inout2.v new file mode 100644 index 000000000..23ef950d2 --- /dev/null +++ b/ivtest/ivltests/inout2.v @@ -0,0 +1,44 @@ +/* + * This test deminstrates a complication in the handling of a vector + * as a unit, instead of breaking it out. The problem is with the + * legal inout expression that takes one bit of the vector. That + * leads to a driver to the input of a part select, and also the + * other way around. Yikes. + */ +module main; + + reg [1:0] drv = 2'b0z; + wire [1:0] a = drv; + reg en; + + bi dut0(a[0], en); + + initial begin + en <= 0; + + #1 $display("drv=%b en=%b, a=%b (should be 0z)", drv, en, a); + if (a !== 2'b0z) begin + $display("FAILED"); + $finish; + end + + en <= 1; + + #1 $display("drv=%b en=%b, a=%b (should be 01)", drv, en, a); + if (a !== 2'b01) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main + +module bi (inout a, input en); + + reg val = 1; + assign a = en? val : 1'bz; + +endmodule // bi diff --git a/ivtest/ivltests/inout3.v b/ivtest/ivltests/inout3.v new file mode 100644 index 000000000..be85be17f --- /dev/null +++ b/ivtest/ivltests/inout3.v @@ -0,0 +1,36 @@ +module main; + + wire qh = 1'bz; + wire [1:0] Q; + reg [2:0] D; + + buft a({qh,Q}, D); + + reg x; + //assign D[0] = x; + + initial begin + D = 3'bzz0; + #1 $display("Q=%b, D=%b", Q, D); + if (Q !== 2'bz0) begin + $display("FAILED"); + $finish; + end + + D[0] = 1; + #1 $display("Q=%b, D=%b", Q, D); + if (Q !== 2'bz1) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main + +module buft(inout [2:0] T, input [2:0] D); + + assign T = D; + +endmodule // buft diff --git a/ivtest/ivltests/inout4.v b/ivtest/ivltests/inout4.v new file mode 100644 index 000000000..a0e39020f --- /dev/null +++ b/ivtest/ivltests/inout4.v @@ -0,0 +1,45 @@ +module main; + + wire [31:0] DB; + reg E; + + X2 U (.DB(DB[31:8]), .E(E)); + Y1 V (.DB(DB[7:0]), .E(E)); + + initial begin + E = 0; + #1 if (DB !== 32'hzzzzzzzz) begin + $display("FAILED -- DB=%b", DB); + $finish; + end + + E = 1; + #1 if (DB !== 32'h9zzzzz87) begin + $display("FAILED -- DB=%b", DB); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main + +module X2(inout wire [31:8] DB, input wire E); + + X1 uu (.DB(DB[31:28]), .E(E)); + +endmodule // X2 + +module X1(inout wire [31:28] DB, input wire E); + + wire foo = DB[31:28]; + assign DB[31:28] = E? 4'b1001 : 4'bzzzz; + +endmodule // sub + +module Y1(inout wire [7:0] DB, input wire E); + + wire foo = DB[7:0]; + assign DB[7:0] = E? 8'h87 : 8'hzz; + +endmodule // sub diff --git a/ivtest/ivltests/inside_synth.v b/ivtest/ivltests/inside_synth.v new file mode 100644 index 000000000..3fd308b6f --- /dev/null +++ b/ivtest/ivltests/inside_synth.v @@ -0,0 +1,52 @@ +/* + * This tests the latching of an output that isn't really an output, + * but an intermediate symbol that is only used in some clauses. + */ +module main; + + reg [15:0] out, a; + reg [7:0] b; + reg cy; + reg with_carry; + + (* ivl_combinational *) + always @(with_carry, a, b, cy) + if (with_carry) begin + {cy, out[7:0]} = {1'b0, a[7:0]} + {1'b0, b[7:0]}; + out[15:8] = a[15:8] + {7'b0, cy}; + end else begin + out = a + {8'h00, b}; + end + + (* ivl_synthesis_off *) + initial begin + a = 16'h00fe; + b = 8'h00; + with_carry = 0; + #1 if (out !== 16'h00fe) begin + $display("FAILED -- a=%h, b=%h, out=%h", a, b, out); + $finish; + end + + with_carry = 1; + #1 if (out !== 16'h00fe) begin + $display("FAILED -- a=%h, b=%h, out=%h", a, b, out); + $finish; + end + + b = 2; + #1 if (out !== 16'h0100) begin + $display("FAILED -- a=%h, b=%h, out=%h", a, b, out); + $finish; + end + + with_carry = 0; + #1 if (out !== 16'h0100) begin + $display("FAILED -- a=%h, b=%h, out=%h", a, b, out); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/inside_synth2.v b/ivtest/ivltests/inside_synth2.v new file mode 100644 index 000000000..ad7e09e02 --- /dev/null +++ b/ivtest/ivltests/inside_synth2.v @@ -0,0 +1,69 @@ +module main; + + reg [7:0] th2, init; + reg carry, clk, rst, foo; + + (* ivl_synthesis_on *) + always @(posedge clk) begin + + if (rst) begin + th2 <= 0; + carry <= 1; + foo <= 0; // This causes foo to be an output to the block. + end else begin + if (carry) + {carry, th2} <= {1'b0, init}; + else + {carry, th2} <= {1'b0, th2} + 9'h1; + end + + end + + (* ivl_synthesis_off *) + initial begin + rst = 1; + clk = 0; + init = 8'hfe; + $monitor("clk=%b: rst=%b, th2=%h, carry=%b", clk, rst, th2, carry); + + #1 clk = 1; + #1 clk = 0; + if (foo !== 0) begin + $display("FAILED -- foo=%b", foo); + $finish; + end + + rst = 0; + + #1 clk = 1; + #1 clk = 0; + + #1 clk = 1; + #1 clk = 0; + if (th2 !== 8'hff) begin + $display("FAILED -- th2=%h (1)", th2); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + if (th2 !== 8'h00) begin + $display("FAILED == th2=%h", th2); + $finish; + end + if (carry !== 1) begin + $display("FAILED -- carry=%b, th2=%h", carry, th2); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + if (th2 !== 8'hfe) begin + $display("FAILED -- th2=%h", th2); + $finish; + end + + #1 $strobe("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/inside_synth3.v b/ivtest/ivltests/inside_synth3.v new file mode 100644 index 000000000..75b17e403 --- /dev/null +++ b/ivtest/ivltests/inside_synth3.v @@ -0,0 +1,57 @@ +/* + * This tests the latching of an output that isn't really an output, + * but an intermediate symbol that is only used in some clauses. + */ +module main; + + reg [15:0] out, a; + reg [7:0] b; + reg cy; + reg with_carry; + + (* ivl_combinational *) + always @(with_carry, a, b, cy) + case (with_carry) + 1'b1: + begin + {cy, out[7:0]} = {1'b0, a[7:0]} + {1'b0, b[7:0]}; + out[15:8] = a[15:8] + {7'b0, cy}; + end + 1'b0: + begin + out = a + {8'h00, b}; + end + endcase + + (* ivl_synthesis_off *) + initial begin + a = 16'h00fe; + b = 8'h00; + with_carry = 0; + #1 if (out !== 16'h00fe) begin + $display("FAILED -- a=%h, b=%h, out=%h", a, b, out); + $finish; + end + + with_carry = 1; + #1 if (out !== 16'h00fe) begin + $display("FAILED -- a=%h, b=%h, out=%h", a, b, out); + $finish; + end + + b = 2; + #1 if (out !== 16'h0100) begin + $display("FAILED -- a=%h, b=%h, out=%h", a, b, out); + $finish; + end + + with_carry = 0; + #1 if (out !== 16'h0100) begin + $display("FAILED -- a=%h, b=%h, out=%h", a, b, out); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/int_not_signext.v b/ivtest/ivltests/int_not_signext.v new file mode 100644 index 000000000..2438214a5 --- /dev/null +++ b/ivtest/ivltests/int_not_signext.v @@ -0,0 +1,19 @@ +module top; + reg [47:0] out1, out2, out3, out4, out5; + integer i; + + initial begin + for (i=-1 ; i<2; i=i+1) begin + // i is signed so should it be sign extended? + out1 = 48'd16 + i; + // I would have expected this to be the same as (i+0) below! + out2 = 48'd16 + (i); + // All the rest of these are sign extended? + out3 = 48'd16 + (i+0); + out4 = 48'sd16 + i; + out5 = 48'd16 + (i-1); + $display("16 + %2d = %10d, %10d, %2d, %2d, -1 = %2d", + i, out1, out2, out3, out4, out5); + end + end +endmodule diff --git a/ivtest/ivltests/int_param.v b/ivtest/ivltests/int_param.v new file mode 100644 index 000000000..9427fe133 --- /dev/null +++ b/ivtest/ivltests/int_param.v @@ -0,0 +1,37 @@ +module main; + + localparam int int_lparm = 11; + parameter int int_param = 10; + int int_var; + + initial begin + if (int_lparm != 11) begin + $display("FAILED: int_lparm=%b", int_lparm); + $finish; + end + + if ($bits(int_lparm) != 32) begin + $display("FAILED: $bits(int_lparm) = %d", $bits(int_lparm)); + $finish; + end + + if (int_param != 10) begin + $display("FAILED: int_param=%b", int_param); + $finish; + end + + if ($bits(int_param) != 32) begin + $display("FAILED: $bits(int_param) = %d", $bits(int_param)); + $finish; + end + + int_var = int_param; + if (int_var != 10) begin + $display("FAILED: int_var=%b", int_var); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/integer1lt.v b/ivtest/ivltests/integer1lt.v new file mode 100644 index 000000000..27bc3048c --- /dev/null +++ b/ivtest/ivltests/integer1lt.v @@ -0,0 +1,68 @@ +/* + * integer1 - a verilog test for integer conditionals + * + * Copyright (C) 1999 Stephen G. Tell + * Portions inspired by qmark.v by Steven Wilson (stevew@home.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ + +module integer1lt; + + integer a; + integer b; + reg error; + + initial begin + error = 0; + + a = 2; + if(a < 2) begin + $display("FAILED 2 < 2"); + error = 1; + end + + a = 3; + if(a < 2) begin + $display("FAILED 3 < 2"); + error = 1; + end + + a = 1; + if(a < 2) begin + b = 1; + end else begin + $display("FAILED 1 < 2"); + error = 1; + end + + b = 0; + for(a = 0; a < 5; a = a + 1) begin + b = b + a; + end // for (a = 0; a < 5; a = a + 1) + + if(b != 10) begin + $display("FAILED forloop b=%d expected 10", b); + error = 1; + end + + if(error == 0) + $display("PASSED"); + $finish; + + end // initial begin + +endmodule diff --git a/ivtest/ivltests/integer2le.v b/ivtest/ivltests/integer2le.v new file mode 100644 index 000000000..96dddf973 --- /dev/null +++ b/ivtest/ivltests/integer2le.v @@ -0,0 +1,115 @@ +/* + * integer2le - a verilog test for integer less-or-equal conditional <= + * + * Copyright (C) 1999 Stephen G. Tell + * Portions inspired by qmark.v by Steven Wilson (stevew@home.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ + +module integer2le; + + integer a; + integer b; + integer c; + reg error; + +initial + begin + error = 0; + + a = 1; + if(a <= 2) + begin + b = 1; + end + else + begin + $display("FAILED 1 <= 2"); + error = 1; + end + + a = 2; + + if(a <= 2) + begin + b = 1; + end + else + begin + $display("FAILED 2 <= 2"); + error = 1; + end + + a = 3; + + if(a <= 2) + begin + $display("FAILED 3 <= 2"); + error = 1; + end + + c = 0; + a = 10; + for(b = 0; a <= 5; b = b + 1) + begin + b = b + a; + c = c + 1; + if(c > 10) + begin + $display("FAILED (infinite loop) a=%d b=%d", a, b); + error = 1; + $finish; + end + end + if(b != 0) + begin + $display("FAILED forloop a=%d b=%d", a, b); + error = 1; + end + if(a != 10) + begin + $display("FAILED forloop a=%d b=%d", a, b); + error = 1; + end + + b = 0; + c = 0; + for(a = 0; a <= 5; a = a + 1) + begin + b = b + a; + c = c + 1; + if(c > 10) + begin + $display("FAILED (infinite loop) a=%d b=%d", a, b); + error = 1; + $finish; + end + end + + if(b != 15) + begin + $display("FAILED forloop b=%d expected 15", b); + error = 1; + end + + if(error == 0) + $display("PASSED"); + + $finish; + end // initial begin + +endmodule diff --git a/ivtest/ivltests/integer3gt.v b/ivtest/ivltests/integer3gt.v new file mode 100644 index 000000000..0456816b3 --- /dev/null +++ b/ivtest/ivltests/integer3gt.v @@ -0,0 +1,69 @@ +/* + * integer3gt - a verilog test for integer greater-than conditional > + * + * Copyright (C) 1999 Stephen G. Tell + * Portions inspired by qmark.v by Steven Wilson (stevew@home.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ + +module integer3gt; + + integer a; + integer b; + reg error; + + initial begin + error = 0; + + a = 1; + if(a > 2) begin + $display("FAILED 1 > 2"); + error = 1; + end // if (a < 2) + + a = 2; + if(a > 2) begin + $display("FAILED 2 > 2"); + error = 1; + end + + a = 3; + if(a > 2) begin + b = 1; + end else begin + $display("FAILED 3 > 2"); + error = 1; + end + + + b = 0; + for(a = 10; a > 5; a = a - 1) begin + b = b + a; + end + + if(b != 40) begin + $display("FAILED forloop b=%d expected 40", b); + error = 1; + end + + if(error == 0) + $display("PASSED"); + $finish; + + end // initial begin + +endmodule diff --git a/ivtest/ivltests/integer4ge.v b/ivtest/ivltests/integer4ge.v new file mode 100644 index 000000000..2cd46f1a3 --- /dev/null +++ b/ivtest/ivltests/integer4ge.v @@ -0,0 +1,71 @@ +/* + * integer4ge - a verilog test for integer greater-or-equal conditional >= + * + * Copyright (C) 1999 Stephen G. Tell + * Portions inspired by qmark.v by Steven Wilson (stevew@home.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ + +module integer4ge; + + integer a; + integer b; + reg error; + + initial begin + error = 0; + + a = 1; + if(a >= 2) begin + $display("FAILED 1 >= 2"); + error = 1; + end + + a = 2; + if(a >= 2) begin + b = 1; + end else begin + $display("FAILED 2 >= 2"); + error = 1; + end + + a = 3; + if(a >= 2) begin + b = 1; + end else begin + $display("FAILED 3 >= 2"); + error = 1; + end + + + b = 0; + for(a = 10; a >= 5; a = a - 1) begin + b = b + a; + end + + if(b != 45) begin + $display("FAILED forloop b=%d expected 45", b); + error = 1; + end + + if(error == 0) + $display("PASSED"); + $finish; + + end // initial begin + +endmodule diff --git a/ivtest/ivltests/integer5.v b/ivtest/ivltests/integer5.v new file mode 100644 index 000000000..a1354f652 --- /dev/null +++ b/ivtest/ivltests/integer5.v @@ -0,0 +1,51 @@ +/* + * integer4ge - a verilog test for integer greater-or-equal conditional >= + * + * Copyright (C) 2000 Steve Wilson stevew@home.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ +`timescale 100s/1s +module test; + +reg [3:0] result; +reg error; +integer num1; +wire [3:0] result1; + +assign result1 = 1 + (num1 /4); + +initial + begin + error = 0; + num1 = 32'h24 ; + result = 1 + (num1 / 4); + #1; + if(result !== 4'ha) + begin + $display("FAILED - division didn't work s/b A, is %h",result); + error = 1; + end + if(result1 !== 4'ha) + begin + $display("FAILED - assign division didn't work s/b A, is %h",result1); + error = 1; + end + if(error == 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/ishortint_test.v b/ivtest/ivltests/ishortint_test.v new file mode 100644 index 000000000..528460009 --- /dev/null +++ b/ivtest/ivltests/ishortint_test.v @@ -0,0 +1,94 @@ +// Three basic tests in here: +// 1. byte must be initialised before any initial or always block +// 2. assignments to (unsigned) bytes with random numbers +// 3. assignments to (unsigned) bytes with random values including X and Z + + +module ibyte_test; + parameter TRIALS = 100; + parameter MAX = 'h7fff; + reg [15:0] ar; // should it be "reg unsigned [7:0] aw"? + reg [15:0] ar_xz; // same as above here? + reg [15:0] ar_expected; // and here + shortint unsigned bu; + shortint unsigned bu_xz; + + integer i; + + assign bu = ar; + assign bu_xz = ar_xz; + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 16'b0 | bu_xz != 16'b0) + begin + $display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz); + $finish; + end + // random numbers + for (i = 0; i< TRIALS; i = i+1) + begin + #1; + ar = {$random} % MAX; + #1; + if (bu !== ar) + begin + $display ("FAILED - incorrect assigment to byte: %b", bu); + $finish; + end + end + # 1; + // with 'x injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< TRIALS; i = i+1) + begin + #1; + ar = {$random} % MAX; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect assigment to byte (when 'x): %b", bu); + $finish; + end + end + # 1; + $display("PASSED"); + end + + // this returns X and Z states into bit random positions for a value + function [7:0] xz_inject (input [7:0] value); // should it be "input unsigned [7:0]" instead? + integer i, temp; + begin + temp = {$random} % MAX; + for (i=0; i<16; i=i+1) + begin + if (temp[i] == 1'b1) + begin + temp = $random % MAX; + if (temp <= 0) + value[i] = 1'bx; // 'x noise + else + value[i] = 1'bz; // 'z noise + end + end + xz_inject = value; + end + endfunction + + // this function returns bit positions with either X or Z to 0 for an input value + function [15:0] xz_expected (input [15:0] value_xz); // should it be "input unsigned [7:0] instead? + integer i; + begin + for (i=0; i<16; i=i+1) + begin + if (value_xz[i] === 1'bx || value_xz[i] === 1'bz ) + value_xz[i] = 1'b0; // forced to zero + end + xz_expected = value_xz; + end + endfunction + + +endmodule diff --git a/ivtest/ivltests/itor_rtoi.v b/ivtest/ivltests/itor_rtoi.v new file mode 100644 index 000000000..5f00bbb55 --- /dev/null +++ b/ivtest/ivltests/itor_rtoi.v @@ -0,0 +1,84 @@ +/* + * This does not check that $itor() and $rtoi() can actually be called in + * a constant context (e.g. a parameter assignment). This was done so that + * older version of Icarus Verilog will still run this code to verify that + * the values are converted correctly. Also some of the results are not + * defined in the standard so we use a gold file instead of pass/fail test + * to make it easier to check other simulators. + */ +module top; + integer ival; + real rval; + + initial begin + $display("Testing $itor() in a constant context."); + // Check various integer values. + rval = $itor(10); $display(" $itor(10) = %g", rval); + rval = $itor(1'bx); $display(" $itor(1'bx) = %g", rval); + rval = $itor(1'bz); $display(" $itor(1'bx) = %g", rval); + // Check various real values. + rval = $itor(10.4); $display(" $itor(10.4) = %g", rval); + rval = $itor(10.5); $display(" $itor(10.5) = %g", rval); + rval = $itor(-1.4); $display(" $itor(-1.4) = %g", rval); + rval = $itor(-1.5); $display(" $itor(-1.5) = %g", rval); + rval = $itor(0.0/0.0); $display(" $itor(NaN) = %g", rval); + rval = $itor(1.0/0.0); $display(" $itor(+inf) = %g", rval); + rval = $itor(-1.0/0.0); $display(" $itor(-inf) = %g", rval); + + $display(""); + $display("Testing $itor() in a variable context."); + // Check various integer values. + ival = 10; rval = $itor(ival); $display(" $itor(10) = %g", rval); + ival = 1'bx; rval = $itor(ival); $display(" $itor(1'bx) = %g", rval); + ival = 1'bx; rval = $itor(ival); $display(" $itor(1'bx) = %g", rval); + // Check various real values. + rval = 10.4; rval = $itor(rval); $display(" $itor(10.4) = %g", rval); + rval = 10.5; rval = $itor(rval); $display(" $itor(10.5) = %g", rval); + rval = -1.4; rval = $itor(rval); $display(" $itor(-1.4) = %g", rval); + rval = -1.5; rval = $itor(rval); $display(" $itor(-1.5) = %g", rval); + rval = 0.0/0.0; rval = $itor(rval); $display(" $itor(NaN) = %g", rval); + rval = 1.0/0.0; rval = $itor(rval); $display(" $itor(+inf) = %g", rval); + rval = -1.0/0.0; rval = $itor(rval); $display(" $itor(-inf) = %g", rval); + + $display(""); + $display("Testing $rtoi() in a constant context."); + // Check for truncation of a positive value. + ival = $rtoi(1.1); $display(" $rtoi(1.1) = %0d", ival); + ival = $rtoi(1.9); $display(" $rtoi(1.9) = %0d", ival); + // Check for truncation of a negative value. + ival = $rtoi(-1.1); $display(" $rtoi(-1.1) = %0d", ival); + ival = $rtoi(-1.9); $display(" $rtoi(-1.9) = %0d", ival); + // Check a value larger than an integer is truncated. + ival = $rtoi((33'b1<<32)+0.0); $display(" Overflow(0) = %0d", ival); + ival = $rtoi((33'b1<<32)+1.0); $display(" Overflow(1) = %0d", ival); + // Check NaN, +/- infinity. + ival = $rtoi(0.0/0.0); $display(" $rtoi(NaN) = %0d", ival); + ival = $rtoi(1.0/0.0); $display(" $rtoi(+inf) = %0d", ival); + ival = $rtoi(-1.0/0.0); $display(" $rtoi(-inf) = %0d", ival); + // Check various integer values. + ival = $rtoi(1); $display(" $rtoi(1) = %0d", ival); + ival = $rtoi(1'bx); $display(" $rtoi(1'bx) = %0d", ival); + ival = $rtoi(1'bz); $display(" $rtoi(1'bz) = %0d", ival); + + $display(""); + $display("Testing $rtoi() in a variable context."); + // Check for truncation of a positive value. + rval = 1.1; ival = $rtoi(rval); $display(" $rtoi(1.1) = %0d", ival); + rval = 1.9; ival = $rtoi(rval); $display(" $rtoi(1.9) = %0d", ival); + // Check for truncation of a negative value. + rval = -1.1; ival = $rtoi(rval); $display(" $rtoi(-1.1) = %0d", ival); + rval = -1.9; ival = $rtoi(rval); $display(" $rtoi(-1.9) = %0d", ival); + // Check a value larger than an integer is truncated. + rval = (33'b1<<32)+0.0; ival = $rtoi(rval); $display(" Overflow(0) = %0d", ival); + rval = (33'b1<<32)+1.0; ival = $rtoi(rval); $display(" Overflow(1) = %0d", ival); + // Check NaN, +/- infinity. + rval = 0.0/0.0; ival = $rtoi(rval); $display(" $rtoi(NaN) = %0d", ival); + rval = 1.0/0.0; ival = $rtoi(rval); $display(" $rtoi(+inf) = %0d", ival); + rval = -1.0/0.0; ival = $rtoi(rval); $display(" $rtoi(-inf) = %0d", ival); + // Check various integer values. + ival = 1; ival = $rtoi(ival); $display(" $rtoi(1) = %0d", ival); + ival = 1'bx; ival = $rtoi(ival); $display(" $rtoi(1'bx) = %0d", ival); + ival = 1'bz; ival = $rtoi(ival); $display(" $rtoi(1'bz) = %0d", ival); + + end +endmodule diff --git a/ivtest/ivltests/iuint1.v b/ivtest/ivltests/iuint1.v new file mode 100644 index 000000000..4baa226fd --- /dev/null +++ b/ivtest/ivltests/iuint1.v @@ -0,0 +1,76 @@ +module main; + + int unsigned foo, bar = 10; + int signed foos, bars = 10; + + int unsigned wire_sum; + int wire_sums; + + assign wire_sum = foo + bar; + assign wire_sums = foos + bars; + + function int unsigned sum(input int unsigned a, b); + sum = a + b; + endfunction + + function int unsigned sums(input int signed a, b); + sums = a + b; + endfunction + + initial begin + foo = 9; + $display("%0d * %0d = %0d", foo, bar, foo * bar); + $display("sum(%0d,%0d) = %0d", foo, bar, sum(foo,bar)); + + if (foo !== 9 || bar !== 10) begin + $display("FAILED"); + $finish; + end + + if (foo*bar !== 90) begin + $display("FAILED"); + $finish; + end + + if (sum(foo,bar) !== 19) begin + $display("FAILED"); + $finish; + end + + foos = -7; + $display("%0d * %0d = %0d", foos, bars, foos * bars); + $display("sums(%0d,%0d) = %0d", foos, bars, sums(foos,bars)); + + if (foos !== -7 || bars !== 10) begin + $display("FAILED"); + $finish; + end + + if (foos*bars !== -70) begin + $display("FAILED"); + $finish; + end + + if (sums(foos,bars) !== 3) begin + $display("FAILED"); + $finish; + end + + #0; // allow CAs to propagate + $display("wire_sum = %0d", wire_sum); + $display("wire_sums = %0d", wire_sums); + + if (wire_sum !== 19) begin + $display("FAILED"); + $finish; + end + + if (wire_sums !== 3) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/ivlh_event.v b/ivtest/ivltests/ivlh_event.v new file mode 100644 index 000000000..b96976ae1 --- /dev/null +++ b/ivtest/ivltests/ivlh_event.v @@ -0,0 +1,20 @@ +module main; + + reg a, b; + + always @(a or b) begin + if ($ivlh_attribute_event(a)) + $display("%0t: EVENT on a", $time); + if ($ivlh_attribute_event(b)) + $display("%0t: EVENT on b", $time); + end + + initial begin + #1 a <= 1; + #1 b <= 1; + #1 a <= 0; + #1 b <= 0; + #1 $finish(0); + end + +endmodule // main diff --git a/ivtest/ivltests/ivlh_rising_falling.v b/ivtest/ivltests/ivlh_rising_falling.v new file mode 100644 index 000000000..ac412fdec --- /dev/null +++ b/ivtest/ivltests/ivlh_rising_falling.v @@ -0,0 +1,60 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for $ivlh_{rising,falling}_edge VPI functions +// (mostly used by the VHDL frontend). + +module main; + + reg a, b; + + always @(a or b) begin + if ($ivlh_rising_edge(a)) + $display("%0t: rising_edge(a)", $time); + if ($ivlh_falling_edge(a)) + $display("%0t: falling_edge(a)", $time); + + if ($ivlh_rising_edge(b)) + $display("%0t: rising_edge(b)", $time); + if ($ivlh_falling_edge(b)) + $display("%0t: falling_edge(b)", $time); + end + + initial begin + #1 a <= 1; + #1 b <= 1; + + #1 a <= 0; + #1 b <= 0; + + #1 a <= 0; // nothing should be detected + #1 b <= 0; + + #1 a <= 1; + #1 b <= 1; + + #1 a <= 1; // nothing should be detected + #1 b <= 1; + + #1 a <= 0; + #1 b <= 0; + #1 $finish(0); + end + +endmodule // main diff --git a/ivtest/ivltests/ivlh_textio.v b/ivtest/ivltests/ivlh_textio.v new file mode 100644 index 000000000..37bfc6a97 --- /dev/null +++ b/ivtest/ivltests/ivlh_textio.v @@ -0,0 +1,218 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for VHDL std.textio & ieee.std_logic_textio functions implemented using VPI. + +`timescale 1ns/1ns + +typedef enum integer { false, true } boolean; +typedef enum integer { read_mode , write_mode , append_mode } file_open_kind; + +module vhdl_textio_test; + +string line; +int file; + +string str; +bit [3:0][7:0] str_lim; +real r; +int in; +integer i; +byte by; +time t; +boolean boo; + +logic l; +logic [7:0] lv; +bit bi; +bit [7:0] biv; + +initial begin + static string filename = "vpi_textio_text.tmp"; + + // values to be saved + str = "test_string"; + str_lim = "TEST"; + r = -2.5e3; + in = 120; + i = -12; + by = 8'h1f; + t = 100ns; + boo = true; + l = 1'bx; + lv = 8'b110101xz; + bi = 1'b0; + biv = 8'b10111001; + + // write test + $ivlh_file_open(file, filename, write_mode); + + $ivlh_write(line, str, 0); // standard format + $ivlh_write(line, " ", 0); + $ivlh_write(line, str_lim, 4); // string format + $ivlh_write(line, " ", 0); + $ivlh_write(line, r, 0); + $ivlh_write(line, " ", 0); + $ivlh_write(line, in, 0); + $ivlh_write(line, " ", 0); + $ivlh_write(line, i, 0); + $ivlh_write(line, " ", 0); + $ivlh_write(line, by, 0); + $ivlh_write(line, " ", 0); + $ivlh_write(line, t, 2); // time format + + // this will be intentionally skipped during the read test + $ivlh_write(line, " ", 0); + $ivlh_write(line, l, 0); + $ivlh_write(line, " ", 0); + $ivlh_write(line, lv, 0); + + if(line != "test_string TEST -2500.000000 120 -12 31 100 ns X 110101XZ") begin + $display("FAILED 1"); + $finish(); + end + + $ivlh_writeline(file, line); + + // writeline should clear the written string + if(line != "") begin + $display("FAILED 2"); + $finish(); + end + + $ivlh_write(line, boo, 1); // boolean format + $ivlh_write(line, " ", 0); + $ivlh_write(line, l, 0); + $ivlh_write(line, " ", 0); + $ivlh_write(line, lv, 0); + $ivlh_write(line, " ", 0); + $ivlh_write(line, bi, 0); + $ivlh_write(line, " ", 0); + $ivlh_write(line, biv, 0); + $ivlh_write(line, " ", 0); + $ivlh_write(line, biv, 3); // hex format + + if(line != "TRUE X 110101XZ 0 10111001 B9") begin + $display("FAILED 3"); + $finish(); + end + + $ivlh_writeline(file, line); + $fclose(file); + + // reset variables + str = ""; + r = 0; + in = 0; + i = 0; + by = 0; + t = 0s; + boo = false; + l = 0; + lv = 0; + bi = 0; + biv = 0; + + // read test + $ivlh_file_open(file, filename, read_mode ); + + $ivlh_readline(file, line); + $ivlh_read(line, str, 0); // standard format + $ivlh_read(line, str_lim, 4); // string format + $ivlh_read(line, r, 0); + $ivlh_read(line, in, 0); + $ivlh_read(line, i, 0); + $ivlh_read(line, by, 0); + $ivlh_read(line, t, 2); // time format + + $ivlh_readline(file, line); + $ivlh_read(line, boo, 1); // boolean format + $ivlh_read(line, l, 0); + $ivlh_read(line, lv, 0); + $ivlh_read(line, bi, 0); + $ivlh_read(line, biv, 0); + $ivlh_read(line, biv, 3); // hex format + + $fclose(file); + + // compare read and expected values + if(str != "test_string") begin + $display("FAILED 5"); + $finish(); + end + + if(str_lim != "TEST") begin + $display("FAILED 6"); + $finish(); + end + + if(r != -2.5e3) begin + $display("FAILED 7"); + $finish(); + end + + if(in !== 120) begin + $display("FAILED 8"); + $finish(); + end + + if(i !== -12) begin + $display("FAILED 9"); + $finish(); + end + + if(by !== 8'h1f) begin + $display("FAILED 10"); + $finish(); + end + + if(t != 100ns) begin + $display("FAILED 11"); + $finish(); + end + + if(boo !== true) begin + $display("FAILED 12"); + $finish(); + end + + if(l !== 1'bx) begin + $display("FAILED 13"); + $finish(); + end + + if(lv !== 8'b110101xz) begin + $display("FAILED 14"); + $finish(); + end + + if(bi !== 1'b0) begin + $display("FAILED 15"); + $finish(); + end + + if(biv !== 8'b10111001) begin + $display("FAILED 16"); + $finish(); + end + + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/l_equiv.v b/ivtest/ivltests/l_equiv.v new file mode 100644 index 000000000..79e01ab40 --- /dev/null +++ b/ivtest/ivltests/l_equiv.v @@ -0,0 +1,156 @@ +module top; + real rval1, rval2; + reg val1, val2; + reg [3:0] wval1, wval2; + reg [1:0] wres; + reg res; + reg pass; + + initial begin + pass = 1'b1; + + val1 = 1'b0; + val2 = 1'b0; + res = val1 <-> val2; + if (res !== 1'b1) begin + $display("FAILED: 1'b0 <-> 1'b0 returned %b not 1'b1", res); + pass = 1'b0; + end + val2 = 1'b1; + res = val1 <-> val2; + if (res !== 1'b0) begin + $display("FAILED: 1'b0 <-> 1'b1 returned %b not 1'b0", res); + pass = 1'b0; + end + val2 = 1'bx; + res = val1 <-> val2; + if (res !== 1'bx) begin + $display("FAILED: 1'b0 <-> 1'bx returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'bz; + res = val1 <-> val2; + if (res !== 1'bx) begin + $display("FAILED: 1'b0 <-> 1'bz returned %b not 1'bx", res); + pass = 1'b0; + end + val1 = 1'b1; + val2 = 1'b0; + res = val1 <-> val2; + if (res !== 1'b0) begin + $display("FAILED: 1'b1 <-> 1'b0 returned %b not 1'b0", res); + pass = 1'b0; + end + val2 = 1'b1; + res = val1 <-> val2; + if (res !== 1'b1) begin + $display("FAILED: 1'b1 <-> 1'b1 returned %b not 1'b1", res); + pass = 1'b0; + end + val2 = 1'bx; + res = val1 <-> val2; + if (res !== 1'bx) begin + $display("FAILED: 1'b1 <-> 1'bx returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'bz; + res = val1 <-> val2; + if (res !== 1'bx) begin + $display("FAILED: 1'b1 <-> 1'bz returned %b not 1'bx", res); + pass = 1'b0; + end + val1 = 1'bx; + val2 = 1'b0; + res = val1 <-> val2; + if (res !== 1'bx) begin + $display("FAILED: 1'bx <-> 1'b0 returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'b1; + res = val1 <-> val2; + if (res !== 1'bx) begin + $display("FAILED: 1'bx <-> 1'b1 returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'bx; + res = val1 <-> val2; + if (res !== 1'bx) begin + $display("FAILED: 1'bx <-> 1'bx returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'bz; + res = val1 <-> val2; + if (res !== 1'bx) begin + $display("FAILED: 1'bx <-> 1'bz returned %b not 1'bx", res); + pass = 1'b0; + end + val1 = 1'bz; + val2 = 1'b0; + res = val1 <-> val2; + if (res !== 1'bx) begin + $display("FAILED: 1'bz <-> 1'b0 returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'b1; + res = val1 <-> val2; + if (res !== 1'bx) begin + $display("FAILED: 1'bz <-> 1'b1 returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'bx; + res = val1 <-> val2; + if (res !== 1'bx) begin + $display("FAILED: 1'bz <-> 1'bx returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'bz; + res = val1 <-> val2; + if (res !== 1'bx) begin + $display("FAILED: 1'bz <-> 1'bz returned %b not 1'bx", res); + pass = 1'b0; + end + + rval1 = 0.0; + val2 = 1'b0; + res = rval1 <-> val2; + if (res !== 1'b1) begin + $display("FAILED: 0.0 <-> 1'b0 returned %b not 1'b1", res); + pass = 1'b0; + end + val1 = 1'b0; + rval2 = 2.0; + res = val1 <-> rval2; + if (res !== 1'b0) begin + $display("FAILED: 1'b0 <-> 2.0 returned %b not 1'b0", res); + pass = 1'b0; + end + rval1 = 2.0; + val2 = 1'bx; + res = rval1 <-> val2; + if (res !== 1'bx) begin + $display("FAILED: 2.0 <-> 1'bx returned %b not 1'bx", res); + pass = 1'b0; + end + rval1 = -5.0; + rval2 = 2.0; + res = rval1 <-> rval2; + if (res !== 1'b1) begin + $display("FAILED: -5.0 <-> -2.0 returned %b not 1'b1", res); + pass = 1'b0; + end + wval1 = 4'b0110; + wval2 = 4'b1001; + wres = wval1 <-> wval2; + if (wres !== 2'b01) begin + $display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b01", wres); + pass = 1'b0; + end + wres = $signed(wval1 <-> wval2); + if (wres !== 2'b11) begin + $display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b11", wres); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/l_equiv_ca.v b/ivtest/ivltests/l_equiv_ca.v new file mode 100644 index 000000000..89983a9dc --- /dev/null +++ b/ivtest/ivltests/l_equiv_ca.v @@ -0,0 +1,163 @@ +module top; + wire res, ler0, ler1, ler2, ler3; + wire [1:0] lew, lews; + real rval1, rval2; + reg val1, val2; + reg [3:0] wval1, wval2; + reg pass; + + assign res = val1 <-> val2; + assign lew = wval1 <-> wval2; + assign lews = $signed(wval1 <-> wval2); + assign ler0 = rval1 <-> val2; + assign ler1 = val1 <-> rval2; + assign ler2 = rval1 <-> val2; + assign ler3 = rval1 <-> rval2; + + initial begin + pass = 1'b1; + + val1 = 1'b0; + val2 = 1'b0; + #1; + if (res !== 1'b1) begin + $display("FAILED: 1'b0 <-> 1'b0 returned %b not 1'b1", res); + pass = 1'b0; + end + val2 = 1'b1; + #1; + if (res !== 1'b0) begin + $display("FAILED: 1'b0 <-> 1'b1 returned %b not 1'b0", res); + pass = 1'b0; + end + val2 = 1'bx; + #1; + if (res !== 1'bx) begin + $display("FAILED: 1'b0 <-> 1'bx returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'bz; + #1; + if (res !== 1'bx) begin + $display("FAILED: 1'b0 <-> 1'bz returned %b not 1'bx", res); + pass = 1'b0; + end + val1 = 1'b1; + val2 = 1'b0; + #1; + if (res !== 1'b0) begin + $display("FAILED: 1'b1 <-> 1'b0 returned %b not 1'b0", res); + pass = 1'b0; + end + val2 = 1'b1; + #1; + if (res !== 1'b1) begin + $display("FAILED: 1'b1 <-> 1'b1 returned %b not 1'b1", res); + pass = 1'b0; + end + val2 = 1'bx; + #1; + if (res !== 1'bx) begin + $display("FAILED: 1'b1 <-> 1'bx returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'bz; + #1; + if (res !== 1'bx) begin + $display("FAILED: 1'b1 <-> 1'bz returned %b not 1'bx", res); + pass = 1'b0; + end + val1 = 1'bx; + val2 = 1'b0; + #1; + if (res !== 1'bx) begin + $display("FAILED: 1'bx <-> 1'b0 returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'b1; + #1; + if (res !== 1'bx) begin + $display("FAILED: 1'bx <-> 1'b1 returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'bx; + #1; + if (res !== 1'bx) begin + $display("FAILED: 1'bx <-> 1'bx returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'bz; + #1; + if (res !== 1'bx) begin + $display("FAILED: 1'bx <-> 1'bz returned %b not 1'bx", res); + pass = 1'b0; + end + val1 = 1'bz; + val2 = 1'b0; + #1; + if (res !== 1'bx) begin + $display("FAILED: 1'bz <-> 1'b0 returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'b1; + #1; + if (res !== 1'bx) begin + $display("FAILED: 1'bz <-> 1'b1 returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'bx; + #1; + if (res !== 1'bx) begin + $display("FAILED: 1'bz <-> 1'bx returned %b not 1'bx", res); + pass = 1'b0; + end + val2 = 1'bz; + #1; + if (res !== 1'bx) begin + $display("FAILED: 1'bz <-> 1'bz returned %b not 1'bx", res); + pass = 1'b0; + end + + rval1 = 0.0; + val2 = 1'b0; + #1; + if (ler0 !== 1'b1) begin + $display("FAILED: 0.0 <-> 1'b0 returned %b not 1'b1", ler0); + pass = 1'b0; + end + val1 = 1'b0; + rval2 = 2.0; + #1; + if (ler1 !== 1'b0) begin + $display("FAILED: 1'b0 <-> 2.0 returned %b not 1'b0", ler1); + pass = 1'b0; + end + rval1 = 2.0; + val2 = 1'bx; + #1; + if (ler2 !== 1'bx) begin + $display("FAILED: 2.0 <-> 1'bx returned %b not 1'bx", ler2); + pass = 1'b0; + end + rval1 = -5.0; + rval2 = 2.0; + #1; + if (ler3 !== 1'b1) begin + $display("FAILED: -5.0 <-> -2.0 returned %b not 1'b1", ler3); + pass = 1'b0; + end + wval1 = 4'b0110; + wval2 = 4'b1001; + #1; + if (lew !== 2'b01) begin + $display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b01", lew); + pass = 1'b0; + end + if (lews !== 2'b11) begin + $display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b11", lews); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/l_equiv_const.v b/ivtest/ivltests/l_equiv_const.v new file mode 100644 index 000000000..135ec2462 --- /dev/null +++ b/ivtest/ivltests/l_equiv_const.v @@ -0,0 +1,123 @@ +module top; + parameter le0 = 1'b0 <-> 1'b0; // 1'b1 + parameter le1 = 1'b0 <-> 1'b1; // 1'b0 + parameter le2 = 1'b0 <-> 1'bz; // 1'bx + parameter le3 = 1'b0 <-> 1'bx; // 1'bx + parameter le4 = 1'b1 <-> 1'b0; // 1'b0 + parameter le5 = 1'b1 <-> 1'b1; // 1'b1 + parameter le6 = 1'b1 <-> 1'bz; // 1'bx + parameter le7 = 1'b1 <-> 1'bx; // 1'bx + parameter le8 = 1'bz <-> 1'b0; // 1'bx + parameter le9 = 1'bz <-> 1'b1; // 1'bx + parameter lea = 1'bz <-> 1'bz; // 1'bx + parameter leb = 1'bz <-> 1'bx; // 1'bx + parameter lec = 1'bx <-> 1'b0; // 1'bx + parameter led = 1'bx <-> 1'b1; // 1'bx + parameter lee = 1'bx <-> 1'bz; // 1'bx + parameter lef = 1'bx <-> 1'bx; // 1'bx + + parameter [1:0] lew = 4'b0110 <-> 4'b1001; // 2'b01 + parameter [1:0] lews = $signed(4'b0110 <-> 4'b1001); // 2'b11 + parameter ler0 = 0.0 <-> 1'b0; // 1'b1 + parameter ler1 = 1'b0 <-> 2.0; // 1'b0 + parameter ler2 = 2.0 <-> 1'bx; // 1'bx + parameter ler3 = -5.0 <-> 2.0; // 1'b1 + + reg pass; + + initial begin + pass = 1'b1; + + if (le0 !== 1'b1) begin + $display("FAILED: 1'b0 <-> 1'b0 returned %b not 1'b1", le0); + pass = 1'b0; + end + if (le1 !== 1'b0) begin + $display("FAILED: 1'b0 <-> 1'b1 returned %b not 1'b0", le1); + pass = 1'b0; + end + if (le2 !== 1'bx) begin + $display("FAILED: 1'b0 <-> 1'bz returned %b not 1'bx", le2); + pass = 1'b0; + end + if (le3 !== 1'bx) begin + $display("FAILED: 1'b0 <-> 1'bx returned %b not 1'bx", le3); + pass = 1'b0; + end + if (le4 !== 1'b0) begin + $display("FAILED: 1'b1 <-> 1'b0 returned %b not 1'b0", le4); + pass = 1'b0; + end + if (le5 !== 1'b1) begin + $display("FAILED: 1'b1 <-> 1'b1 returned %b not 1'b1", le5); + pass = 1'b0; + end + if (le6 !== 1'bx) begin + $display("FAILED: 1'b1 <-> 1'bz returned %b not 1'bx", le6); + pass = 1'b0; + end + if (le7 !== 1'bx) begin + $display("FAILED: 1'b1 <-> 1'bx returned %b not 1'bx", le7); + pass = 1'b0; + end + if (le8 !== 1'bx) begin + $display("FAILED: 1'bz <-> 1'b0 returned %b not 1'bx", le8); + pass = 1'b0; + end + if (le9 !== 1'bx) begin + $display("FAILED: 1'bz <-> 1'b1 returned %b not 1'bx", le9); + pass = 1'b0; + end + if (lea !== 1'bx) begin + $display("FAILED: 1'bz <-> 1'bz returned %b not 1'bx", lea); + pass = 1'b0; + end + if (leb !== 1'bx) begin + $display("FAILED: 1'bz <-> 1'bx returned %b not 1'bx", leb); + pass = 1'b0; + end + if (lec !== 1'bx) begin + $display("FAILED: 1'bx <-> 1'b0 returned %b not 1'bx", lec); + pass = 1'b0; + end + if (led !== 1'bx) begin + $display("FAILED: 1'bx <-> 1'b0 returned %b not 1'bx", led); + pass = 1'b0; + end + if (lee !== 1'bx) begin + $display("FAILED: 1'bx <-> 1'bz returned %b not 1'bx", lee); + pass = 1'b0; + end + if (lef !== 1'bx) begin + $display("FAILED: 1'bx <-> 1'bx returned %b not 1'bx", lef); + pass = 1'b0; + end + + if (ler0 !== 1'b1) begin + $display("FAILED: 0.0 <-> 1'b0 returned %b not 1'b1", ler0); + pass = 1'b0; + end + if (ler1 !== 1'b0) begin + $display("FAILED: 1'b0 <-> 2.0 returned %b not 1'b1", ler1); + pass = 1'b0; + end + if (ler2 !== 1'bx) begin + $display("FAILED: 2.0 <-> 1'bx returned %b not 1'b1", ler2); + pass = 1'b0; + end + if (ler3 !== 1'b1) begin + $display("FAILED: -5.0 <-> 2.0 returned %b not 1'b1", ler3); + pass = 1'b0; + end + if (lew !== 2'b01) begin + $display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b01", lew); + pass = 1'b0; + end + if (lews !== 2'b11) begin + $display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b11", lews); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/land2.v b/ivtest/ivltests/land2.v new file mode 100644 index 000000000..bb21740e3 --- /dev/null +++ b/ivtest/ivltests/land2.v @@ -0,0 +1,97 @@ +/* + * land2 - a verilog test for logical and operator && in boolean context + * + * + * Copyright (C) 1999 Stephen G. Tell + * Portions inspired by qmark.v by Steven Wilson (stevew@home.com) + * Modified by SDW to self test. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ + +module land2; + + reg Clk; + reg a; + reg b; + reg c; + reg error; + + wire q; + wire q_calc; + + tand tand_m(q, q_calc, a, b, c); + + initial Clk = 0; + always #10 Clk = ~Clk; + + always @(posedge Clk) + begin + #1; + if(q != q_calc) + begin + $display("FAILED - expr && using %b%b%b is %b s/b %b", + a, b, c, q,q_calc); + error = 1; + end + end + + reg [3:0] bvec; + integer xa; + integer xb; + integer xc; + initial begin + bvec = 4'bzx10 ; + error = 0; + for(xa = 0; xa <= 3; xa = xa + 1) + for(xb = 0; xb <= 3; xb = xb + 1) + for(xc = 0; xc <= 3; xc = xc + 1) + begin + @(posedge Clk) + a = bvec[xa]; + b = bvec[xb]; + c = bvec[xc]; + end // for (var3 = 0; var3 <= 3; var3 = var3 + 1) + if(error == 0 ) $display("PASSED"); + $finish; + end + +endmodule + +module tand(q, q_calc, a, b, c); + output q; + output q_calc; + input a; + input b; + input c; + + wire q = ( (a===b) && (b===c) ); + reg q_calc; + + always @(a or b or c) + begin + if(a === b) + begin + if( b === c) + q_calc = 1'b1; + else + q_calc = 1'b0; + end + else + q_calc = 1'b0; + end + +endmodule // foo diff --git a/ivtest/ivltests/land3.v b/ivtest/ivltests/land3.v new file mode 100644 index 000000000..a7faedbbe --- /dev/null +++ b/ivtest/ivltests/land3.v @@ -0,0 +1,107 @@ +/* + * land3 - a verilog test for logical and operator && in a conditional. + * + * Copyright (C) 1999 Stephen G. Tell + * Portions inspired by qmark.v by Steven Wilson (stevew@home.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ + +module land3; + + reg Clk; + reg a; + reg b; + reg c; + reg error; + + wire q; + wire q_calc; + + tand tand_m(q,q_calc, a, b, c); + + initial Clk = 0; + always #10 Clk = ~Clk; + + always @(posedge Clk) + begin + #1 ; + if(q != q_calc) + begin + $display("FAILED - Cond && failed for vect %b%b%b - was %b, s/b %b", + a,b,c,q,q_calc); + error = 1; + end + end + + + reg [3:0] bvec; + integer xa, xb, xc; + initial begin + error = 0; + bvec = 4'bzx10 ; + for(xa = 0; xa < 4; xa = xa + 1) + for(xb = 0; xb < 4; xb = xb + 1) + for(xc = 0; xc < 4; xc = xc + 1) + begin + @(posedge Clk) + a = bvec[xa]; + b = bvec[xb]; + c = bvec[xc]; + end // for (var3 = 0; var3 <= 3; var3 = var3 + 1) + @(posedge Clk) ; + @(posedge Clk) ; + if(error == 0) + $display("PASSED"); + $finish; + end + +endmodule + +module tand(q, q_calc, a, b, c); + output q; + output q_calc; + input a; + input b; + input c; + + reg q; + reg q_calc; + + always @(a or b or c) begin + if(a===b && b===c) + q <= 1; + else + q <= 0; + end // always @ (a or b or c) + + // Added to allow 2nd calculation + // We use the if (a === b) formulation - it's part + // of the base set that is need to do ANY tests.. + always @(a or b or c) + begin + if( a===b) + begin + if(b === c) + q_calc = 1'b1; + else + q_calc = 1'b0; + end + else + q_calc = 1'b0; + end + +endmodule // foo diff --git a/ivtest/ivltests/land4.v b/ivtest/ivltests/land4.v new file mode 100644 index 000000000..f2b4ba741 --- /dev/null +++ b/ivtest/ivltests/land4.v @@ -0,0 +1,60 @@ +// +// Copyright (c) 2002 Stephen Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + + reg ena, wea; + reg enb, web; + + reg clk; + reg out = 0; + + always @(posedge clk) begin + if ((ena == 1) && (wea == 1) && + (enb == 1) && (web == 1)) + out <= 1; + end + + initial begin + clk = 0; + ena = 0; + enb = 0; + wea = 0; + web = 0; + + $monitor("clk=%b: ena=%b, enb=%b, wea=%b, web=%b --> out=%b", + clk, ena, enb, wea, web, out); + + #1 clk = 1; + #1 clk = 0; + + ena = 1; + enb = 1; + + #1 clk = 1; + #1 clk = 0; + + wea = 1; + web = 1; + + #1 clk = 1; + #1 clk = 0; + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/land5.v b/ivtest/ivltests/land5.v new file mode 100644 index 000000000..db3b5b131 --- /dev/null +++ b/ivtest/ivltests/land5.v @@ -0,0 +1,29 @@ +module main; + + reg [1:0] a, b; + reg flag; + + (* ivl_combinational *) + always @(a, b) + flag = a && b; + + (* ivl_synthesis_off *) + initial begin + a = 1; + b = 0; + #1 if (flag !== 0) begin + $display("FAILED -- a=%b, b=%b, flag=%b", a, b, flag); + $finish; + end + + b = 2; + #1 if (flag !== 1) begin + $display("FAILED -- a=%b, b=%b, flag=%b", a, b, flag); + $finish; + end + + $display("PASSED"); + + end + +endmodule // main diff --git a/ivtest/ivltests/landor1.v b/ivtest/ivltests/landor1.v new file mode 100644 index 000000000..2219315a7 --- /dev/null +++ b/ivtest/ivltests/landor1.v @@ -0,0 +1,21 @@ +module test; + reg [1:0] r1, r2; + + initial begin + r1 = 2'd2; + r2 = 2'd0; + + if (r1 || r2) + $display("PASSED"); + else + $display("FAILED"); + + r1 = 2'd2; + r2 = 2'd1; + if (r1 && r2) + $display("PASSED"); + else + $display("FAILED"); + + end +endmodule diff --git a/ivtest/ivltests/lcatsynth.v b/ivtest/ivltests/lcatsynth.v new file mode 100644 index 000000000..dfebb79ed --- /dev/null +++ b/ivtest/ivltests/lcatsynth.v @@ -0,0 +1,47 @@ +module main; + + reg q0, q1, clk, clr; + + (* ivl_synthesis_on *) + always @(posedge clk, posedge clr) + if (clr) begin + //q0 <= 0; + //q1 <= 0; + {q0, q1} <= 2'b00; + end else begin + {q1, q0} <= {q1, q0} + 1; + end + + (* ivl_synthesis_off *) + initial begin + clk = 0; + clr = 1; + #1 clk = 1; + #1 clk = 0; + if ({q1,q0} !== 2'b00) begin + $display("FAILED"); + $finish; + end + + clr = 0; + + #1 clk = 1; + #1 clk = 0; + + if ({q1,q0} !== 2'b01) begin + $display("FAILED"); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if ({q1,q0} !== 2'b10) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/ldelay1.v b/ivtest/ivltests/ldelay1.v new file mode 100644 index 000000000..d6a719786 --- /dev/null +++ b/ivtest/ivltests/ldelay1.v @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: ldelay1.v,v 1.2 2007/12/06 02:31:10 stevewilliams Exp $ + +// Test for delays in structural logic. Inertial delays + +module test; + + wire q; + reg a, b; + and #6 (q, a, b); + + task ok; + input qq; + reg error; + begin + if (q !== qq) + begin + error = 1; + $display("%0d: FAILED: q=%b, expect %b", $time, q, qq); + end + end + endtask + + initial + begin + ok.error = 0; +// $dumpvars; + a <= 0; + b <= 1; + #5 ok(1'b x); + #2 ok(1'b 0); + a <= 1; + #5 ok(1'b 0); + #2 ok(1'b 1); + a <= 0; + #3 ok(1'b 1); + a <= 1; + #1 ok(1'b 1); + #1 ok(1'b 1); + #1 ok(1'b 1); + #1 ok(1'b 1); + #1 ok(1'b 1); + #1 ok(1'b 1); + #1 ok(1'b 1); + if (!ok.error) + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/ldelay2.v b/ivtest/ivltests/ldelay2.v new file mode 100644 index 000000000..cad3576f5 --- /dev/null +++ b/ivtest/ivltests/ldelay2.v @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: ldelay2.v,v 1.2 2007/12/06 02:31:10 stevewilliams Exp $ + +// Test for delays in structural logic. Inertial delays suppress event. + +module test; + + wire q; + reg a, b; + xor #1 (q, a, b); + + reg error; + initial + begin + error = 0; + #2; + @(q); + error = 1; + $display("%0d: FAILED: q=%b", $time, q); + end + + initial + begin +// $dumpvars; + a = 0; + b = 1; + #3; + a = 1; + b = 0; + #2; + a = 0; + b = 1; + #3; + if (!error) + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/ldelay3.v b/ivtest/ivltests/ldelay3.v new file mode 100644 index 000000000..ac458a0fa --- /dev/null +++ b/ivtest/ivltests/ldelay3.v @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: ldelay3.v,v 1.2 2007/12/06 02:31:10 stevewilliams Exp $ + +// Test for delays in structural logic. timescale + +`timescale 1ns/100ps + +module test; + + wire q; + reg a, b; + gate gg (q, a, b); + + task ok; + input qq; + reg error; + begin + if (q !== qq) + begin + error = 1; + $display("%0d: FAILED: q=%b, expect %b", $time, q, qq); + end + end + endtask + + initial + begin + ok.error = 0; +// $dumpvars; + a <= 0; + b <= 1; + #5.5 ok(1'b x); + #0.1 ok(1'b 0); + a <= 1; + #5.5 ok(1'b 0); + #0.1 ok(1'b 1); + a <= 0; + #3 ok(1'b 1); + a <= 1; + #1 ok(1'b 1); + #1 ok(1'b 1); + #1 ok(1'b 1); + #1 ok(1'b 1); + #1 ok(1'b 1); + #1 ok(1'b 1); + #1 ok(1'b 1); + if (!ok.error) + $display("PASSED"); + end + +endmodule + +`timescale 1ps/1ps + +module gate(q, a, b); + output q; + input a, b; + + and #5555 (q, a, b); +endmodule diff --git a/ivtest/ivltests/ldelay4.v b/ivtest/ivltests/ldelay4.v new file mode 100644 index 000000000..67f49bb87 --- /dev/null +++ b/ivtest/ivltests/ldelay4.v @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: ldelay4.v,v 1.3 2007/12/06 02:31:10 stevewilliams Exp $ + +// Test for delays in structural logic. Differential clock receiver UDP. + +module test; + + wire q, e; + reg a, b; + drec #1 rec(q, a, b); + edet det (e, q); + + reg error; + initial + begin + error = 0; + #2; + forever @(e) + if (e !== 1'bx) begin // Fail on anything other then x. + error = 1; + $display("%0d: FAILED: e=%b", $time, e); + end + end + + always @(q) + $display("%d: q=%b", $time, q); + + initial + begin +// $dumpvars; + a = 0; + b = 1; + #3; + a = 1; + b = 0; + #2; + a = 0; + b = 1; + #3; + if (!error) + $display("PASSED"); + end +endmodule + +// differential receiver + +primitive drec (q, a, b); + output q; + input a, b; + table + 1 0 : 1 ; + 0 1 : 0 ; + endtable +endprimitive + +// flag any edges to or from 'bx + +primitive edet (q, i); + output q; + input i; + reg q; + table + (?x) : ? : 1; + (x?) : ? : 0; + endtable +endprimitive diff --git a/ivtest/ivltests/ldelay5.v b/ivtest/ivltests/ldelay5.v new file mode 100644 index 000000000..abe0a06f7 --- /dev/null +++ b/ivtest/ivltests/ldelay5.v @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: ldelay5.v,v 1.1 2001/12/26 23:45:57 sib4 Exp $ + +// Test for delays in structural logic. Multiple UDP instances. + +module test; + + wire [1:2] q, a, b; + drec U1(q[1], a[1], b[1]); + drec U2(q[2], a[2], b[2]); + + initial $display("PASSED"); + +endmodule + +module drec (q, a, b); + output q; + input a, b; + U_drec #1 U(q, a, b); +endmodule + +primitive U_drec (q, a, b); + output q; + input a, b; + table + 1 0 : 1 ; + 0 1 : 0 ; + endtable +endprimitive diff --git a/ivtest/ivltests/lh_catadd.v b/ivtest/ivltests/lh_catadd.v new file mode 100644 index 000000000..38a0dfa77 --- /dev/null +++ b/ivtest/ivltests/lh_catadd.v @@ -0,0 +1,42 @@ +/* + * Copyright (c) 1998-1999 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module test; + + wire [3:0] a = 7, b = 13 ; + wire [3:0] sum ; + wire carry ; + assign {carry,sum} = a + b ; + + initial begin + #1 + if (carry !== 1'b1) begin + $display("FAILED: carry === %b", carry); + $finish; + end + + if (sum !== 4'b0100) begin + $display("FAILED: sum === %b", sum); + $finish; + end + + $display("Correct results {carry,sum} === %b,%b", carry, sum); + $display("PASSED"); + end +endmodule /* test */ diff --git a/ivtest/ivltests/lh_memcat.v b/ivtest/ivltests/lh_memcat.v new file mode 100644 index 000000000..e71712cc4 --- /dev/null +++ b/ivtest/ivltests/lh_memcat.v @@ -0,0 +1,58 @@ +module main; + + reg clk, rst, done; + wire [31:0] x; + reg [3:0] a; + reg [23:0] in, out; + reg [2:0] a_fifo_cam_indices[3:0], lt_fifo_cam_indices[3:0]; + + // Debug signals to see 'em under signalscan + // -- iverilog generates a warning here + wire [2:0] db0_a_fifo_cam_indices = a_fifo_cam_indices[0]; + + // generate a clock + always + #10 clk = ~clk; + + // -- iverilog generates a warning here + assign x[31:0] = { 28'hfffffff, (~a[3:0] + 4'd1) }; + + initial + begin + $display ("\n<< BEGIN >>"); + rst = 1'b0; + a[3:0] = 4'b0101; + + // -- iverilog internal value is not dealt with correctly (see value + out[23:0] = ( rst ? 24'o7654_3210 : in[23:0] ); + + casex ( done ) + // -- iverilog generate errors - "could not match signal" + 1'b1: { a_fifo_cam_indices[3], + a_fifo_cam_indices[2], + a_fifo_cam_indices[1], + a_fifo_cam_indices[0] } = {3'b000, + lt_fifo_cam_indices[3], + lt_fifo_cam_indices[2], + lt_fifo_cam_indices[1]}; + 1'b0: { a_fifo_cam_indices[3], + a_fifo_cam_indices[2], + a_fifo_cam_indices[1], + a_fifo_cam_indices[0] } = { lt_fifo_cam_indices[3], + lt_fifo_cam_indices[2], + lt_fifo_cam_indices[1], + lt_fifo_cam_indices[0]}; + endcase + + $display ("\n<< END >>"); + $finish(0); + end + + // Waves definition +// initial +// begin +// $dumpfile("out.dump"); +// $dumpvars(0, main); +// end + +endmodule // main diff --git a/ivtest/ivltests/lh_memcat2.v b/ivtest/ivltests/lh_memcat2.v new file mode 100644 index 000000000..9d99cf878 --- /dev/null +++ b/ivtest/ivltests/lh_memcat2.v @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version.will need a Picture Elements Binary Software + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program demonstrates the mixing of reg and memories in l-value + * contatenations. + */ +module main; + + reg [3:0] mem [2:0]; + reg a, b; + + initial begin + mem[0] = 0; + mem[1] = 0; + mem[2] = 0; + + {b, mem[1], a} = 6'b0_0000_1; + if (a !== 1'b1) begin + $display("FAILED -- a = %b", a); + $finish; + end + if (mem[1] !== 4'b0000) begin + $display("FAILED -- mem[1] = %b", mem[1]); + $finish; + end + if (b !== 1'b0) begin + $display("FAILED -- b = %b", b); + $finish; + end + + {b, mem[1], a} = 6'b0_1111_0; + if (a !== 1'b0) begin + $display("FAILED -- a = %b", a); + $finish; + end + if (mem[0] !== 4'b0000) begin + $display("FAILED -- mem[0] - %b", mem[0]); + $finish; + end + if (mem[1] !== 4'b1111) begin + $display("FAILED -- mem[1] = %b", mem[1]); + $finish; + end + if (b !== 1'b0) begin + $display("FAILED -- b = %b", b); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/lh_memcat3.v b/ivtest/ivltests/lh_memcat3.v new file mode 100644 index 000000000..df6e6bd6d --- /dev/null +++ b/ivtest/ivltests/lh_memcat3.v @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version.will need a Picture Elements Binary Software + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program demonstrates the mixing of reg and memories in l-value + * contatenations. + */ +module main; + + reg [3:0] mem [2:0]; + reg a, b; + + initial begin + mem[0] = 0; + mem[1] = 0; + mem[2] = 0; + + {b, mem[1], a} <= 6'b0_0000_1; + #1 + if (a !== 1'b1) begin + $display("FAILED -- a = %b", a); + $finish; + end + if (mem[1] !== 4'b0000) begin + $display("FAILED -- mem[1] = %b", mem[1]); + $finish; + end + if (b !== 1'b0) begin + $display("FAILED -- b = %b", b); + $finish; + end + + {b, mem[1], a} <= 6'b0_1111_0; + #1 + if (a !== 1'b0) begin + $display("FAILED -- a = %b", a); + $finish; + end + if (mem[0] !== 4'b0000) begin + $display("FAILED -- mem[0] - %b", mem[0]); + $finish; + end + if (mem[1] !== 4'b1111) begin + $display("FAILED -- mem[1] = %b", mem[1]); + $finish; + end + if (b !== 1'b0) begin + $display("FAILED -- b = %b", b); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/lh_varindx.v b/ivtest/ivltests/lh_varindx.v new file mode 100644 index 000000000..de69c1531 --- /dev/null +++ b/ivtest/ivltests/lh_varindx.v @@ -0,0 +1,56 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate left hand variable index + +module main ; + +reg [3:0] a,b; +reg c; +reg error; + +always @(c or b) + a[b] = c; + +initial + begin + #1 ; + a = 4'b1111; + error = 0; + b = 1'b0; + c = 1'b0; + #1 ; + if(a != 4'b1110) + begin + $display("FAILED - var index - a = %b, [b] = %d, c=%b",a,b,c); + error = 1; + end + #1 ; + b = 1; + #1 ; + if(a != 4'b1100) + begin + $display("FAILED - var index - a = %b, [b] = %d, c=%b",a,b,c); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/lh_varindx2.v b/ivtest/ivltests/lh_varindx2.v new file mode 100644 index 000000000..9815b62f4 --- /dev/null +++ b/ivtest/ivltests/lh_varindx2.v @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program is designed to test non-constant bit selects in the + * concatenated l-value of procedural assignment. + */ +module main; + + reg [3:0] vec; + reg a; + integer i; + + initial begin + vec = 4'b0000; + a = 0; + + if (vec !== 4'b0000) begin + $display("FAILED -- initialized vec to %b", vec); + $finish; + end + + for (i = 0 ; i < 4 ; i = i + 1) begin + { a, vec[i] } = i; + end + + if (vec !== 4'b1010) begin + $display("FAILED == vec (%b) is not 1010", vec); + $finish; + end + + if (a !== 1'b1) begin + $display("FAILED -- a (%b) is not 1", a); + $finish; + end + + $display("PASSED"); + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/lh_varindx3.v b/ivtest/ivltests/lh_varindx3.v new file mode 100644 index 000000000..7c5763833 --- /dev/null +++ b/ivtest/ivltests/lh_varindx3.v @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program is designed to test non-constant bit selects in the + * concatenated l-value of procedural assignment. + */ +module main; + + reg [3:0] vec; + reg a; + integer i; + + initial begin + vec = 4'b0000; + a = 0; + + if (vec !== 4'b0000) begin + $display("FAILED -- initialized vec to %b", vec); + $finish; + end + + for (i = 0 ; i < 4 ; i = i + 1) begin + { a, vec[i] } = 2'b11; + end + + if (vec !== 4'b1111) begin + $display("FAILED == vec (%b) is not 1111", vec); + $finish; + end + + if (a !== 1'b1) begin + $display("FAILED -- a (%b) is not 1", a); + $finish; + end + + $display("PASSED"); + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/lh_varindx4.v b/ivtest/ivltests/lh_varindx4.v new file mode 100644 index 000000000..0c56aa5a3 --- /dev/null +++ b/ivtest/ivltests/lh_varindx4.v @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program is designed to test non-constant bit selects in the + * concatenated l-value of procedural assignment. + */ +module main; + + reg [3:0] vec; + reg a; + integer i; + + initial begin + vec = 4'b0000; + a = 0; + + if (vec !== 4'b0000) begin + $display("FAILED -- initialized vec to %b", vec); + $finish; + end + + for (i = 0 ; i < 4 ; i = i + 1) begin + #1 { a, vec[i] } <= i; + end + + #1 if (vec !== 4'b1010) begin + $display("FAILED == vec (%b) is not 1010", vec); + $finish; + end + + if (a !== 1'b1) begin + $display("FAILED -- a (%b) is not 1", a); + $finish; + end + + $display("PASSED"); + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/lh_varindx5.v b/ivtest/ivltests/lh_varindx5.v new file mode 100644 index 000000000..fa11d47a1 --- /dev/null +++ b/ivtest/ivltests/lh_varindx5.v @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program is designed to test non-constant bit selects in the + * concatenated l-value of procedural assignment. + */ +module main; + + reg [3:0] vec; + reg a; + integer i; + + initial begin + vec = 4'b0000; + a = 0; + + if (vec !== 4'b0000) begin + $display("FAILED -- initialized vec to %b", vec); + $finish; + end + + for (i = 0 ; i < 4 ; i = i + 1) begin + #1 { a, vec[i] } <= 2'b11; + end + + #1 if (vec !== 4'b1111) begin + $display("FAILED == vec (%b) is not 1111", vec); + $finish; + end + + if (a !== 1'b1) begin + $display("FAILED -- a (%b) is not 1", a); + $finish; + end + + $display("PASSED"); + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/line_directive.v b/ivtest/ivltests/line_directive.v new file mode 100644 index 000000000..813cf651b --- /dev/null +++ b/ivtest/ivltests/line_directive.v @@ -0,0 +1,17 @@ +module test(); + +`define MACRO \ + $display("file %s line %0d", \ + `__FILE__, `__LINE__); + +initial begin + $display("file %s line %0d", `__FILE__, `__LINE__); +`line 1 "real_source.v" 0 + $display("file %s line %0d", `__FILE__, `__LINE__); +`include "line_directive_inc.v" + $display("file %s line %0d", `__FILE__, `__LINE__); + `MACRO + $display("file %s line %0d", `__FILE__, `__LINE__); +end + +endmodule diff --git a/ivtest/ivltests/line_directive_inc.v b/ivtest/ivltests/line_directive_inc.v new file mode 100644 index 000000000..8ed8e06fc --- /dev/null +++ b/ivtest/ivltests/line_directive_inc.v @@ -0,0 +1 @@ + $display("file %s line %0d", `__FILE__, `__LINE__); diff --git a/ivtest/ivltests/localparam_query.v b/ivtest/ivltests/localparam_query.v new file mode 100644 index 000000000..68f090a0d --- /dev/null +++ b/ivtest/ivltests/localparam_query.v @@ -0,0 +1,58 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for array query functions applied to localparams. + +module lparam_query; +localparam const_param = 16'b0001110111001111; + +initial begin + if($left(const_param) !== 15) begin + $display("FAILED 1"); + $finish(); + end + + if($right(const_param) !== 0) begin + $display("FAILED 2"); + $finish(); + end + + if($high(const_param) !== 15) begin + $display("FAILED 3"); + $finish(); + end + + if($low(const_param) !== 0) begin + $display("FAILED 4"); + $finish(); + end + + if($increment(const_param) !== 1) begin + $display("FAILED 5"); + $finish(); + end + + if($size(const_param) !== 16) begin + $display("FAILED 6"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/localparam_type.v b/ivtest/ivltests/localparam_type.v new file mode 100644 index 000000000..27d44dab8 --- /dev/null +++ b/ivtest/ivltests/localparam_type.v @@ -0,0 +1,21 @@ +module top; + localparam irparam = -1.0; + localparam iiparam = -1; + localparam [7:0] uparam = -1.0; + localparam signed [7:0] sparam = -1.0; + localparam real rparam = -1; + localparam realtime rtparam = -1; + localparam integer iparam = -1.0; + localparam time tparam = -1.0; + + initial begin + $display("Implicit real: ", irparam); + $display("Implicit integer: ", iiparam); + $display("Unsigned: ", uparam); + $display("Signed: ", sparam); + $display("Real: ", rparam); + $display("Real time: ", rtparam); + $display("Integer: ", iparam); + $display("Time: ", tparam); + end +endmodule diff --git a/ivtest/ivltests/localparam_type2.v b/ivtest/ivltests/localparam_type2.v new file mode 100644 index 000000000..941353938 --- /dev/null +++ b/ivtest/ivltests/localparam_type2.v @@ -0,0 +1,158 @@ +module test(); + +localparam signed snv1 = 4'd1; +localparam signed [2:0] s3v1 = 4'd1; +localparam signed [3:0] s4v1 = 4'd1; +localparam signed [4:0] s5v1 = 4'd1; + +localparam signed snv15 = 4'd15; +localparam signed [2:0] s3v15 = 4'd15; +localparam signed [3:0] s4v15 = 4'd15; +localparam signed [4:0] s5v15 = 4'd15; + +localparam signed snvm1 = -4'sd1; +localparam signed [2:0] s3vm1 = -4'sd1; +localparam signed [3:0] s4vm1 = -4'sd1; +localparam signed [4:0] s5vm1 = -4'sd1; + +localparam signed snrm1 = -1.0; +localparam signed [2:0] s3rm1 = -1.0; +localparam signed [3:0] s4rm1 = -1.0; +localparam signed [4:0] s5rm1 = -1.0; + +localparam nnv1 = 4'd1; +localparam [2:0] u3v1 = 4'd1; +localparam [3:0] u4v1 = 4'd1; +localparam [4:0] u5v1 = 4'd1; + +localparam nnv15 = 4'd15; +localparam [2:0] u3v15 = 4'd15; +localparam [3:0] u4v15 = 4'd15; +localparam [4:0] u5v15 = 4'd15; + +localparam nnvm1 = -4'sd1; +localparam [2:0] u3vm1 = -4'sd1; +localparam [3:0] u4vm1 = -4'sd1; +localparam [4:0] u5vm1 = -4'sd1; + +localparam nnrm1 = -1.0; +localparam [2:0] u3rm1 = -1.0; +localparam [3:0] u4rm1 = -1.0; +localparam [4:0] u5rm1 = -1.0; + +reg fail = 0; + +reg match; + +initial begin + match = ($bits(snv1) == 4) && (snv1 === 1); + $display("snv1 : %2d (%0d`b%b) %c", snv1, $bits(snv1), snv1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s3v1) == 3) && (s3v1 === 1); + $display("s3v1 : %2d (%0d`b%b) %c", s3v1 , $bits(s3v1), s3v1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s4v1) == 4) && (s4v1 === 1); + $display("s4v1 : %2d (%0d`b%b) %c", s4v1 , $bits(s4v1), s4v1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s5v1) == 5) && (s5v1 === 1); + $display("s5v1 : %2d (%0d`b%b) %c", s5v1 , $bits(s5v1), s5v1, match ? " " : "*"); + fail = fail || !match; + + match = ($bits(snv15) == 4) && (snv15 === -1); + $display("snv15 : %2d (%0d`b%b) %c", snv15, $bits(snv15), snv15, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s3v15) == 3) && (s3v15 === -1); + $display("s3v15 : %2d (%0d`b%b) %c", s3v15, $bits(s3v15), s3v15, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s4v15) == 4) && (s4v15 === -1); + $display("s4v15 : %2d (%0d`b%b) %c", s4v15, $bits(s4v15), s4v15, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s5v15) == 5) && (s5v15 === 15); + $display("s5v15 : %2d (%0d`b%b) %c", s5v15, $bits(s5v15), s5v15, match ? " " : "*"); + fail = fail || !match; + + match = ($bits(snvm1) == 4) && (snvm1 === -1); + $display("snvm1 : %2d (%0d`b%b) %c", snvm1, $bits(snvm1), snvm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s3vm1) == 3) && (s3vm1 === -1); + $display("s3vm1 : %2d (%0d`b%b) %c", s3vm1, $bits(s3vm1), s3vm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s4vm1) == 4) && (s4vm1 === -1); + $display("s4vm1 : %2d (%0d`b%b) %c", s4vm1, $bits(s4vm1), s4vm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s5vm1) == 5) && (s5vm1 === -1); + $display("s5vm1 : %2d (%0d`b%b) %c", s5vm1, $bits(s5vm1), s5vm1, match ? " " : "*"); + fail = fail || !match; + + match = (snrm1 == -1); + $display("snrm1 : %4.1f %c", snrm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s3rm1) == 3) && (s3rm1 === -1); + $display("s3rm1 : %2d (%0d`b%b) %c", s3rm1, $bits(s3rm1), s3rm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s4rm1) == 4) && (s4rm1 === -1); + $display("s4rm1 : %2d (%0d`b%b) %c", s4rm1, $bits(s4rm1), s4rm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s5rm1) == 5) && (s5rm1 === -1); + $display("s5rm1 : %2d (%0d`b%b) %c", s5rm1, $bits(s5rm1), s5rm1, match ? " " : "*"); + fail = fail || !match; + + match = ($bits(nnv1) == 4) && (nnv1 === 1); + $display("nnv1 : %2d (%0d`b%b) %c", nnv1, $bits(nnv1), nnv1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u3v1) == 3) && (u3v1 === 1); + $display("u3v1 : %2d (%0d`b%b) %c", u3v1 , $bits(u3v1), u3v1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u4v1) == 4) && (u4v1 === 1); + $display("u4v1 : %2d (%0d`b%b) %c", u4v1 , $bits(u4v1), u4v1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u5v1) == 5) && (u5v1 === 1); + $display("u5v1 : %2d (%0d`b%b) %c", u5v1 , $bits(u5v1), u5v1, match ? " " : "*"); + fail = fail || !match; + + match = ($bits(nnv15) == 4) && (nnv15 === 15); + $display("nnv15 : %2d (%0d`b%b) %c", nnv15, $bits(nnv15), nnv15, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u3v15) == 3) && (u3v15 === 7); + $display("u3v15 : %2d (%0d`b%b) %c", u3v15, $bits(u3v15), u3v15, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u4v15) == 4) && (u4v15 === 15); + $display("u4v15 : %2d (%0d`b%b) %c", u4v15, $bits(u4v15), u4v15, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u5v15) == 5) && (u5v15 === 15); + $display("u5v15 : %2d (%0d`b%b) %c", u5v15, $bits(u5v15), u5v15, match ? " " : "*"); + fail = fail || !match; + + match = ($bits(nnvm1) == 4) && (nnvm1 === -1); + $display("nnvm1 : %2d (%0d`b%b) %c", nnvm1, $bits(nnvm1), nnvm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u3vm1) == 3) && (u3vm1 === 7); + $display("u3vm1 : %2d (%0d`b%b) %c", u3vm1, $bits(u3vm1), u3vm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u4vm1) == 4) && (u4vm1 === 15); + $display("u4vm1 : %2d (%0d`b%b) %c", u4vm1, $bits(u4vm1), u4vm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u5vm1) == 5) && (u5vm1 === 31); + $display("u5vm1 : %2d (%0d`b%b) %c", u5vm1, $bits(u5vm1), u5vm1, match ? " " : "*"); + fail = fail || !match; + + match = (nnrm1 == -1.0); + $display("nnrm1 : %4.1f %c", nnrm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u3rm1) == 3) && (u3rm1 === 7); + $display("u3rm1 : %2d (%0d`b%b) %c", u3rm1, $bits(u3rm1), u3rm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u4rm1) == 4) && (u4rm1 === 15); + $display("u4rm1 : %2d (%0d`b%b) %c", u4rm1, $bits(u4rm1), u4rm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u5rm1) == 5) && (u5rm1 === 31); + $display("u5rm1 : %2d (%0d`b%b) %c", u5rm1, $bits(u5rm1), u5rm1, match ? " " : "*"); + fail = fail || !match; + + if (fail) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/logical_short_circuit.v b/ivtest/ivltests/logical_short_circuit.v new file mode 100644 index 000000000..9a5570e6c --- /dev/null +++ b/ivtest/ivltests/logical_short_circuit.v @@ -0,0 +1,147 @@ +module test; + +// The SystemVerilog standard requires that the right side of a logical operator +// is not evaluated under certain conditions. +// For && if the left hand side is false the right hand side is not evalualted +// For || if the left hand side is true the right hand side is not evalualted + +wire a0 = 1'b0; +wire a1 = 1'b1; +wire ax = 1'bx; +wire az = 1'bz; + +integer b; +logic [1:0] c; + +bit failed = 1'b0; + +initial begin + // AND with first parameter 1'b0 + b = 0; + c = 2'b00; + + if (a0 && b++ && ++b) + c = 2'b01; + + failed |= b !== 0; + failed |= c !== 2'b00; + + c = a0 && b++ && ++b; + + failed |= b !== 0; + failed |= c !== 2'b00; + + // AND with first parameter 1'b1 + b = 0; + c = 2'b00; + + if (a1 && b++ && ++b) + c = 2'b01; + + failed |= b !== 1; + failed |= c !== 2'b00; + + c = a1 && b++ && ++b; + + failed |= b !== 3; + failed |= c !== 2'b01; + + // AND with first parameter 1'bz + b = 0; + c = 2'b00; + + if (az && b++ && ++b) + c = 2'b01; + + failed |= b !== 1; + failed |= c !== 2'b00; + + c = az && b++ && ++b; + + failed |= b !== 3; + failed |= c !== 2'b0x; + + // AND with first parameter 1'bz + b = 0; + c = 0; + + if (ax && b++ && ++b) + c = 2'b01; + + failed |= b !== 1; + failed |= c !== 2'b00; + + c = ax && b++ && ++b; + + failed |= b !== 3; + failed |= c !== 2'b0x; + + // OR with first parameter 1'b0 + b = 0; + c = 0; + + if (a0 || b++ || ++b) + c = 2'b01; + + failed |= b !== 2; + failed |= c !== 2'b01; + + c = a0 || b++ || ++b; + + failed |= b !== 3; + failed |= c !== 2'b01; + + // OR with first parameter 1'b1 + b = 0; + c = 2'b00; + + if (a1 || b++ || ++b) + c = 2'b01; + + failed |= b !== 0; + failed |= c !== 2'b01; + + c = a1 || b++ || ++b; + + failed |= b !== 0; + failed |= c !== 2'b01; + + // OR with first parameter 1'bz + b = 0; + c = 2'b00; + + if (az || b++ || ++b) + c = 2'b01; + + failed |= b !== 2; + failed |= c !== 2'b01; + + b = 0; + c = az || b++; + + failed |= b !== 1; + failed |= c !== 2'b0x; + + // OR with first parameter 1'bz + b = 0; + c = 0; + + if (ax || b++ || ++b) + c = 2'b01; + + failed |= b !== 2; + failed |= c !== 2'b01; + + b = 0; + c = ax || b++; + + failed |= b !== 1; + failed |= c !== 2'b0x; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/logp2.v b/ivtest/ivltests/logp2.v new file mode 100644 index 000000000..42e61f6ca --- /dev/null +++ b/ivtest/ivltests/logp2.v @@ -0,0 +1,48 @@ +module test; + + logic b; + logic [9:0] b10; + logic signed bs; + logic unsigned bu; + logic signed [6:0] bs7; + logic unsigned [5:0] bu6; + + initial + begin + b = 1; + b10 = 100; + bs = 0; + bu = 1; + bs7 = -17; + bu6 = 21; + #1; + if (b * b10 !== 100) begin + $display ("FAILED 1"); + $finish; + end + if (bs * b10 !== 0) begin + $display ("FAILED 2" ); + $finish; + end + if (bu * b10 !== 100) begin + $display ("FAILED 3"); + $finish; + end + if (bs7 * 1 !== -17) begin + $display ("FAILED 4"); + $finish; + end + if (bu6 * b !== 21) begin + $display ("FAILED 5"); + $finish; + end + #1; + bu6 = 6'bx1100z; + if (bu6 * 1'b1 !== 6'bxxxxxx) begin + $display ("FAILED 6"); + $finish; + end + $display ("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/long_div.v b/ivtest/ivltests/long_div.v new file mode 100644 index 000000000..e5ece03e0 --- /dev/null +++ b/ivtest/ivltests/long_div.v @@ -0,0 +1,24 @@ +module test(); + + reg [31:0] a, b; + reg [65:0] a_l, b_l; + + wire [31:0] result = a / b; + wire [31:0] mod = a % b; + wire [65:0] result_l = a_l / b_l; + wire [65:0] mod_l = a_l % b_l; + + initial begin + a = 'h1; + b = 'h1; + a_l = 'h1; + b_l = 'h1; + #1; // Need some delay for the calculations to run. +// b_l = 'h0; // This will now fail with an error. + $display("Using normal math routines."); + $display("Result: %0d\nModulus: %h", result, mod); + $display("\nUsing wide math routines."); + $display("Result: %0d\nModulus: %h", result_l, mod_l); + end + +endmodule diff --git a/ivtest/ivltests/macro2.v b/ivtest/ivltests/macro2.v new file mode 100644 index 000000000..fb0efe002 --- /dev/null +++ b/ivtest/ivltests/macro2.v @@ -0,0 +1,11 @@ +`define TBMESS(str) $display("PAS%s", str ); + + // 1364-2001 S19.3 "The text macro facility is not affected by the compiler + // directive `resetall." +`resetall + +module main; + +initial `TBMESS("SED") + +endmodule diff --git a/ivtest/ivltests/macro_redefinition.v b/ivtest/ivltests/macro_redefinition.v new file mode 100644 index 000000000..a1277bbf1 --- /dev/null +++ b/ivtest/ivltests/macro_redefinition.v @@ -0,0 +1,9 @@ +module test(); + +`define MACRO 1 +`define MACRO 1 +`define MACRO 2 +`undef MACRO +`define MACRO 1 + +endmodule diff --git a/ivtest/ivltests/macro_replacement.v b/ivtest/ivltests/macro_replacement.v new file mode 100644 index 000000000..a1277bbf1 --- /dev/null +++ b/ivtest/ivltests/macro_replacement.v @@ -0,0 +1,9 @@ +module test(); + +`define MACRO 1 +`define MACRO 1 +`define MACRO 2 +`undef MACRO +`define MACRO 1 + +endmodule diff --git a/ivtest/ivltests/macro_str_esc.v b/ivtest/ivltests/macro_str_esc.v new file mode 100644 index 000000000..2bda8434f --- /dev/null +++ b/ivtest/ivltests/macro_str_esc.v @@ -0,0 +1,24 @@ +`define DEF1 "string1" +`define DEF2 "string2\"" +`define DEF3 a\b +`define DEF4(a) a + +module top; + initial begin + $display("Using ``celldefine gives: %s", ``celldefine); + $display("Plain ``celldefine gives: ", ``celldefine); + $display("Using `DEF1 gives: %s", `DEF1); + $display("Using ``DEF1 gives: %s", ``DEF1); + $display("Plain ``DEF1 gives: ", ``DEF1); + + $display("Using `DEF2 gives: %s", `DEF2); + $display("Using ``DEF2 gives: %s", ``DEF2); + $display("Plain ``DEF2 gives: ", ``DEF2); + + $display("Using ``DEF3 gives: %s", ``DEF3); + $display("Plain ``DEF3 gives: ", ``DEF3); + + $display("Using ``DEF4(\"tmp\") gives: %s", ``DEF4("tmp")); + $display("Plain ``DEF4(\"tmp\") gives: ", ``DEF4("tmp")); + end +endmodule diff --git a/ivtest/ivltests/macro_with_args.v b/ivtest/ivltests/macro_with_args.v new file mode 100644 index 000000000..f98ef60d6 --- /dev/null +++ b/ivtest/ivltests/macro_with_args.v @@ -0,0 +1,69 @@ +// Copyright 2007, Martin Whitaker +// This file may be freely copied for any purpose. +module macro_with_args(); + +`define forward_and_reverse(str1,str2,str3) /* comment */ \ + $write("%0s", str1); /* comment */ \ + $write(".."); /* comment */ \ + $write("%0s", str3); /* comment */ \ + $write("%0s", str2); /* comment */ \ + $write("%0s", str3); /* comment */ \ + $write(".."); /* comment */ \ + $write("%0s", str1); /* comment */ \ + $write("\n") + +`define sqr( x ) (x * x) // comment + +`define sum( a /* comment */ , b /* comment */ ) /* comment */ \ + (a + b) + +`define sumsqr( + a // comment + , + b // comment + ) \ + `sum ( \ + `sqr(a) \ + , \ + `sqr(b) \ + ) + +`define no_args (a,b,c) + +`define null1 // null +`define null2 + +integer value; + +reg [79:0] astr, bstr, cstr; + +initial begin + `forward_and_reverse("first"," first,last ","last"); + + $sformat(astr, "(a%s)", ``null1); + $sformat(bstr, " %s ", ``no_args); + $sformat(cstr, "(c%s)", ``null2); + `forward_and_reverse // comment + ( // comment + astr // comment + , // comment + bstr // comment + , // comment + cstr // comment + ); // comment + + value = `sumsqr(3,4); + $display("sumsqr(3,4) = %1d", value); + if (value != `sqr(5)) $display("sumsqr expansion failed"); + + value = `sumsqr + ( + (2 + 3) /* 5 */ + , + (4 + 8) /* 12 */ + ); + $display("sumsqr(5,12) = %1d", value); + if (value != `sqr(13)) $display("sumsqr expansion failed"); +end + +endmodule diff --git a/ivtest/ivltests/macsub.v b/ivtest/ivltests/macsub.v new file mode 100644 index 000000000..24f833a96 --- /dev/null +++ b/ivtest/ivltests/macsub.v @@ -0,0 +1,25 @@ +module test(); + +integer j; +integer jel; +integer x; +integer xel; + +`define A(j) (jel == 1 && j == 2) +`define B(j) (jel \ + == 1 && \ + j == 2) + +initial +begin + j = 0; + jel = 1; + x = 2; + xel = 3; + + if(`A(x) && `B(x)) + $display("PASSED"); + else + $display("FAILED"); +end +endmodule diff --git a/ivtest/ivltests/mangle.v b/ivtest/ivltests/mangle.v new file mode 100644 index 000000000..601c99651 --- /dev/null +++ b/ivtest/ivltests/mangle.v @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// $Id: mangle.v,v 1.1 2001/06/19 13:52:13 ka6s Exp $ +// $Log: mangle.v,v $ +// Revision 1.1 2001/06/19 13:52:13 ka6s +// Added 4 tests from Stephan Boettcher +// +// +// Test of \escaped identifiers + +module mangle; + + reg \abc ; + reg \`~!-_=+\|[]{};:'"",./<>? ; + reg cde ; + + initial + begin + abc <= 1; + \`~!-_=+\|[]{};:'"",./<>? <= 1; + \cde <= 1; + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/mangle_1.v b/ivtest/ivltests/mangle_1.v new file mode 100644 index 000000000..f8984f6eb --- /dev/null +++ b/ivtest/ivltests/mangle_1.v @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// $Id: mangle_1.v,v 1.1 2001/06/19 13:52:13 ka6s Exp $ +// $Log: mangle_1.v,v $ +// Revision 1.1 2001/06/19 13:52:13 ka6s +// Added 4 tests from Stephan Boettcher +// +// Test of \escaped identifiers +module a; + wire \a.b ; + m \c.d (\a.b ); + initial + begin + \c.d . \y.z <= 1'b1; + #1; + if (\a.b === 1'b1) + $display("PASSED"); + else + $display("FAILED"); + end +endmodule + +module m(x); + output x; + reg \y.z ; + assign x = \y.z ; +endmodule diff --git a/ivtest/ivltests/many_drivers.v b/ivtest/ivltests/many_drivers.v new file mode 100644 index 000000000..bcfebab88 --- /dev/null +++ b/ivtest/ivltests/many_drivers.v @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: many_drivers.v,v 1.2 2001/07/21 02:30:44 stevewilliams Exp $ +// $Log: many_drivers.v,v $ +// Revision 1.2 2001/07/21 02:30:44 stevewilliams +// Get the expected blended values right. +// +// Revision 1.1 2001/07/18 01:22:26 sib4 +// test for nets with many drivers +// + +module test; + + reg [66:0] in; + wire out; + buf (out, in[ 0]); + buf (out, in[ 1]); + buf (out, in[ 2]); + buf (out, in[ 3]); + buf (out, in[ 4]); + buf (out, in[ 5]); + buf (out, in[ 6]); + buf (out, in[ 7]); + buf (out, in[ 8]); + buf (out, in[ 9]); + buf (out, in[10]); + buf (out, in[11]); + buf (out, in[12]); + buf (out, in[13]); + buf (out, in[14]); + buf (out, in[15]); + buf (out, in[16]); + buf (out, in[17]); + buf (out, in[18]); + buf (out, in[19]); + buf (out, in[20]); + buf (out, in[21]); + buf (out, in[22]); + buf (out, in[23]); + buf (out, in[24]); + buf (out, in[25]); + buf (out, in[26]); + buf (out, in[27]); + buf (out, in[28]); + buf (out, in[29]); + buf (out, in[30]); + buf (out, in[31]); + buf (out, in[32]); + buf (out, in[33]); + buf (out, in[34]); + buf (out, in[35]); + buf (out, in[36]); + buf (out, in[37]); + buf (out, in[38]); + buf (out, in[39]); + buf (out, in[40]); + buf (out, in[41]); + buf (out, in[42]); + buf (out, in[43]); + buf (out, in[44]); + buf (out, in[45]); + buf (out, in[46]); + buf (out, in[47]); + buf (out, in[48]); + buf (out, in[49]); + buf (out, in[50]); + buf (out, in[51]); + buf (out, in[52]); + buf (out, in[53]); + buf (out, in[54]); + buf (out, in[55]); + buf (out, in[56]); + buf (out, in[57]); + buf (out, in[58]); + buf (out, in[59]); + buf (out, in[60]); + buf (out, in[61]); + buf (out, in[62]); + buf (out, in[63]); + buf (out, in[64]); + buf (out, in[65]); + buf (out, in[66]); + + reg err; + + // Verilog-XL yields out=x for all but the first two + + initial + begin + err = 0; + + in = 67'b0; + #1 $display("in=%b out=%b", in, out); + if (out!==1'b0) err = 1; + + in = ~67'b0; + #1 $display("in=%b out=%b", in, out); + if (out!==1'b1) err = 1; + + in = 67'bz; + #1 $display("in=%b out=%b", in, out); + if (out!==1'bx) err = 1; + + in = 67'bx; + #1 $display("in=%b out=%b", in, out); + if (out!==1'bx) err = 1; + + in = 67'h 5_55555555_55555555; + #1 $display("in=%b out=%b", in, out); + if (out!==1'bx) err = 1; + + in = ~67'h 5_55555555_55555555; + #1 $display("in=%b out=%b", in, out); + if (out!==1'bx) err = 1; + + in = 67'h 0_xxxxxxxx_00000000; + #1 $display("in=%b out=%b", in, out); + if (out!==1'bx) err = 1; + + in = ~67'h 0_xxxxxxxx_00000000; + #1 $display("in=%b out=%b", in, out); + if (out!==1'bx) err = 1; + + in = 67'h x_xxxxxxxx_00000000; + #1 $display("in=%b out=%b", in, out); + if (out!==1'bx) err = 1; + + in = ~67'h x_xxxxxxxx_00000000; + #1 $display("in=%b out=%b", in, out); + if (out!==1'bx) err = 1; + + in = 67'h x_55555555_55555555; + #1 $display("in=%b out=%b", in, out); + if (out!==1'bx) err = 1; + + in = ~67'h x_55555555_55555555; + #1 $display("in=%b out=%b", in, out); + if (out!==1'bx) err = 1; + + in = 67'h 1_ffffxxxx_00000000; + #1 $display("in=%b out=%b", in, out); + if (out!==1'bx) err = 1; + + in = ~67'h 1_ffffxxxx_00000000; + #1 $display("in=%b out=%b", in, out); + if (out!==1'bx) err = 1; + + if (err) + $display("FAILED"); + else + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/mcl1.v b/ivtest/ivltests/mcl1.v new file mode 100644 index 000000000..029929242 --- /dev/null +++ b/ivtest/ivltests/mcl1.v @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2001 Eric Brombaugh + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// test_simple.v - testbench for simple.mcl behavioral output +// 01-22-01 E. Brombaugh + +/* + * The ``simple'' module was generated by the synopsis module compiler + * and is typical of the modules it generates. The testbench was hand + * coded. This file was merged into a single file using the Verilog + * preprocessor. + */ + +`timescale 1ns / 10 ps +module simple( y, a, b, c ); +input [3:0] a; +input [3:0] b; +input [7:0] c; +output [8:0] y; +wire dpa_zero, dpa_one; +wire [8:0] y_1_; +assign dpa_zero= 1024'h0; +assign dpa_one= 1024'h1; + +/* simple.mcl:4 module simple (y, a, b, c); */ + +/* simple.mcl:6 input signed [3:0] a, b; */ + +/* simple.mcl:7 input signed [7:0] c; */ + +/* simple.mcl:9 y = a*b+c; */ + +assign y_1_= ((a[2:0]-(a[3]<<3))*(b[2:0]-(b[3]<<3))+(c[6:0]-(c[7]<<7))); + +/* simple.mcl:5 output signed [8:0] y; */ + +assign y = y_1_[8:0]; + +/* simple.mcl:4 module simple (y, a, b, c); */ + +/* simple.mcl:9 y = a*b+c; */ + +/*User Defined Aliases */ +endmodule + +module test_simple; + + reg [15:0] count; + + reg clk; + reg [3:0] a, b; + reg [7:0] c; + + wire [8:0] y; + + simple u1(y, a, b, c); + + initial + begin + count = 0; + clk = 0; + a = 0; + b = 0; + c = 0; + end + + always + #10 clk = ~clk; + + always @(posedge clk) + begin + a = count[3:0]; + b = count[7:4]; + c = count[15:8]; + + #10 + $display("%h %h %h %h", a, b, c, y); + + count = count + 1; + if(count == 0) + $finish(0); + end +endmodule diff --git a/ivtest/ivltests/mcl2.v b/ivtest/ivltests/mcl2.v new file mode 100644 index 000000000..c5f500eae --- /dev/null +++ b/ivtest/ivltests/mcl2.v @@ -0,0 +1,107 @@ +// test_mis.v - Testbench for mis.bvrl +// 01-22-01 E. Brombaugh + +/* + * Copyright (c) 2001 Eric Brombaugh + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * The mis'' module was generated by the synopsis module compiler + * and is typical of the modules it generates. The testbench was hand + * coded. This file was merged into a single file using the Verilog + * preprocessor. + */ + +`timescale 1ns / 10 ps +module mis( y, a, b ); +input [3:0] a; +input [3:0] b; +output [12:0] y; +wire dpa_zero, dpa_one; +wire [5:0] const__1_24_; +wire [7:0] C0; +wire [6:0] const__2_33_; +wire [7:0] C1; +wire [12:0] y_1_; +assign dpa_zero= 1024'h0; +assign dpa_one= 1024'h1; +assign const__1_24_=- 1024'h18; +assign const__2_33_=- 1024'h21; + +/* mis.mcl:4 module mis (y, a, b); */ + +/* mis.mcl:5 input signed [3:0] a, b; */ + +/* mis.mcl:10 C0 = -24; */ + +assign C0= ((const__1_24_[4:0]-(const__1_24_[5]<<5))); + +/* mis.mcl:11 C1 = -33; */ + +assign C1= ((const__2_33_[5:0]-(const__2_33_[6]<<6))); + +/* mis.mcl:13 y = C0*a + C1*b; */ + +assign y_1_= ((C0[6:0]-(C0[7]<<7))*(a[2:0]-(a[3]<<3))+ + (C1[6:0]-(C1[7]<<7))*(b[2:0]-(b[3]<<3))); + +/* mis.mcl:6 output signed [12:0] y; */ + +assign y = y_1_[12:0]; + +/* mis.mcl:4 module mis (y, a, b); */ + +/* mis.mcl:13 y = C0*a + C1*b; */ + +/*User Defined Aliases */ +endmodule + +module test_mis; + reg [10:0] count; + + reg clk; + reg [3:0] a, b; + + wire [12:0] y; + + mis u1(y, a, b); + + initial + begin + count = 0; + clk = 0; + a = 0; + b = 0; + end + + always + #10 clk = ~clk; + + always @(posedge clk) + begin + a = count[3:0]; + b = count[7:4]; + + #10 + $display("%h %h %h", a, b, y); + + count = count + 1; + if(count == 0) + $finish(0); + end +endmodule diff --git a/ivtest/ivltests/mem1.dat b/ivtest/ivltests/mem1.dat new file mode 100644 index 000000000..0d04581f2 --- /dev/null +++ b/ivtest/ivltests/mem1.dat @@ -0,0 +1,16 @@ +00000000_00000001_00000000 +00000000_00000010_00000000 +00000000_00000100_00000000 +00000000_00001000_00000001 +00000000_00010000_00000000 +00000000_00100000_00000000 +00000000_01000000_00000000 +00000000_10000000_00000000 +00000001_00000000_00000000 +00000010_00000000_00000000 +00000100_00000000_00000000 +00001000_00000000_00000000 +00010000_00000000_00000000 +00100000_00000000_00000010 +01000000_00000000_00000000 +10000000_00000000_00000000 diff --git a/ivtest/ivltests/mem1.v b/ivtest/ivltests/mem1.v new file mode 100644 index 000000000..4ce3d6484 --- /dev/null +++ b/ivtest/ivltests/mem1.v @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + * $Log: mem1.v,v $ + * Revision 1.2 2001/01/29 17:26:06 ka6s + * Check in fixes contributed by Paul Campbell (Thanks Paul) + * + */ + +`define CLK 10 + +module main; + reg [31:0] counter; + integer i; + reg [23:0] testvec [15:0]; + reg clk; + wire [23:0] data; + reg write; + + + initial + begin + write = 0; + counter = 0; + clk = 0; + + $readmemb("ivltests/mem1.dat", testvec, 0); + + for (i = 0; i < 16; i = i + 1) + begin + $write("mem[%d] = %x\n", i, testvec[i]); + end + end + + always + begin + #`CLK clk = ~clk; + end + + assign data = (write) ? testvec[counter] : 24'bz; + + always @ (posedge clk) + begin + begin + write = 1; + #1 ; + $write("%d %x\n", counter, data); + write = 0; + counter = counter + 1; + if (counter == 16) + $finish(0); + end + end + +endmodule diff --git a/ivtest/ivltests/mem2port.v b/ivtest/ivltests/mem2port.v new file mode 100644 index 000000000..6e32091ff --- /dev/null +++ b/ivtest/ivltests/mem2port.v @@ -0,0 +1,50 @@ +/* + * Bug report: + * + * From: Hendrik + * Subject: gEDA: Pass array element into module in iverilog 0.5 + * To: geda-dev@seul.org + * Date: Mon, 10 Sep 2001 11:53:04 +0800 + */ + +module top; + reg [6:0] x[2:0]; + + speak i0 (x[0], x[1], x[2]); + + initial + begin + #10 x[0] = 0; + x[1] = 0; + x[2] = 0; + #100 x[0] = 1; + #100 x[0] = 0; + x[1] = 1; + #100 x[1] = 0; + x[2] = 1; + #100 $finish; + end +endmodule + +module speak(x1, x2, x3); + input [6:0] x1, x2, x3; + always #100 + $display ("%d: x1=%d, x2=%d, x3=%d", $time, x1, x2, x3); + + integer errors; + initial + begin + errors = 0; + #100 if (x1 !== 7'b0 || x2 !== 7'b0 || x3 !== 7'b0) + begin errors = errors + 1; $display("FAILED"); end + #100 if (x1 !== 7'b1 || x2 !== 7'b0 || x3 !== 7'b0) + begin errors = errors + 1; $display("FAILED"); end + #100 if (x1 !== 7'b0 || x2 !== 7'b1 || x3 !== 7'b0) + begin errors = errors + 1; $display("FAILED"); end + #100 if (x1 !== 7'b0 || x2 !== 7'b0 || x3 !== 7'b1) + begin errors = errors + 1; $display("FAILED"); end + if (errors === 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/memassign.v b/ivtest/ivltests/memassign.v new file mode 100644 index 000000000..3663f71e9 --- /dev/null +++ b/ivtest/ivltests/memassign.v @@ -0,0 +1,105 @@ +// +// Copyright (c) 1999 David Leask (david.leask@ctam.com.au) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Modified to be self checking + +/* +** The problem: +** Reading in a series of bytes, one per clock, to create a +** large vector which holds the bytes in a parallel form. +*/ + + +module demo_assign_problem; + +reg [7:0] mem_buffer [0:3]; +wire [31:0] big_word; +reg error; +reg [31:0] myconst; + +integer i; + +assign big_word[ 31: 24] = mem_buffer[0]; +assign big_word[ 23: 16] = mem_buffer[1]; +assign big_word[ 15: 8] = mem_buffer[2]; +assign big_word[ 7: 0] = mem_buffer[3]; + +initial + begin + error = 0; + + for (i = 0; i < 4; i = i+1) + mem_buffer[i] = 0; + #50; + mem_buffer[0] = 8'h12; + #50; + myconst = 32'h12_00_00_00; + if(big_word !== 32'h12_00_00_00) + begin + $display("FAILED -Memory assign - expect %h, but have %h", + myconst,big_word); + error = 1; + end + #100 ; + mem_buffer[1] = 8'h34; + #50; + myconst = 32'h12_34_00_00; + if(big_word !== 32'h12_34_00_00) + begin + $display("FAILED -Memory assign - expect %h, but have %h", + myconst,big_word); + error = 1; + end + #100 ; + mem_buffer[2] = 8'h56; + #50; + myconst = 32'h12_34_56_00; + if(big_word !== 32'h12_34_56_00) + begin + $display("FAILED -Memory assign - expect %h, but have %h", + myconst,big_word); + error = 1; + end + #100; + mem_buffer[3] = 8'h78; + #50; + myconst = 32'h12_34_56_00; + if(big_word !== 32'h12_34_56_78) + begin + $display("FAILED - Memory assign - expect %h, but have %h", + myconst,big_word); + error = 1; + end + #100; + mem_buffer[0] = 8'hab; + #50; + myconst = 32'hab_34_56_00; + if(big_word !== 32'hab_34_56_78) + begin + $display("FAILED - Memory assign - expect %h, but have %h", + myconst,big_word); + error = 1; + end + + #100; + if (error ===0) + $display("PASSED"); + + +end +endmodule diff --git a/ivtest/ivltests/memidx.v b/ivtest/ivltests/memidx.v new file mode 100644 index 000000000..3a963ac2e --- /dev/null +++ b/ivtest/ivltests/memidx.v @@ -0,0 +1,117 @@ +/*********************************************************************** + + Array access test cases + Copyright (C) 2001 Eric LaForest, ecl@pet.dhs.org + Licenced under GPL + +***********************************************************************/ + +module wire_test_case (array_out, clock, reset); + output [15:0] array_out; + input clock, reset; + + reg [3:0] readptr; + reg [15:0] body [15:0]; + + wire [15:0] array_out; + assign array_out = body[readptr]; + +// reg [15:0] array_out; +// always @(readptr or body[readptr]) begin +// array_out <= body[readptr]; +// end + + always @(posedge clock) begin + if (reset == 0) begin + readptr <= 16'h0000; + body[0] <= 16'h0001; // Fibonnacci + body[1] <= 16'h0002; + body[2] <= 16'h0003; + body[3] <= 16'h0005; + body[4] <= 16'h0008; + body[5] <= 16'h000D; + body[6] <= 16'h0015; + end + else begin + readptr <= readptr + 16'h0001; + end + end +endmodule + +module always_test_case (array_out, clock, reset); + output [15:0] array_out; + input clock, reset; + + reg [3:0] readptr; + reg [15:0] body [15:0]; + +// wire [15:0] array_out; +// assign array_out = body[readptr]; + + reg [15:0] array_out; + always @(readptr or body[readptr]) begin + array_out <= body[readptr]; + end + + always @(posedge clock) begin + if (reset == 0) begin + readptr <= 16'h0000; + body[0] <= 16'h0001; // Fibonnacci + body[1] <= 16'h0002; + body[2] <= 16'h0003; + body[3] <= 16'h0005; + body[4] <= 16'h0008; + body[5] <= 16'h000D; + body[6] <= 16'h0015; + end + else begin + readptr <= readptr + 16'h0001; + end + end +endmodule + +module BENCH (); + wire [15:0] array_out1, array_out2; + reg clock, reset; + + integer count; + integer errors; + + wire_test_case usingwire (array_out1, clock, reset); + always_test_case usingalways (array_out2, clock, reset); + + initial begin +// $dumpfile("waves.vcd"); +// $dumpvars(0, BENCH); + clock <= 0; + reset <= 0; + count <= 0; + #1000; + if (errors == 0) + $display("PASSED"); + $finish; + end + + always begin + # 10 clock <= ~clock; + end + + always @(posedge clock) begin + count <= count + 1; + case (count) + 10: begin + reset <= 1; + end + endcase + end + + initial errors = 0; + + always @(negedge clock) + if (array_out1 !== array_out2) + begin + $display("FAILED: %b !== %b", array_out1, array_out2); + errors = errors + 1; + end + +endmodule diff --git a/ivtest/ivltests/memidx2.v b/ivtest/ivltests/memidx2.v new file mode 100644 index 000000000..6d0a3e50b --- /dev/null +++ b/ivtest/ivltests/memidx2.v @@ -0,0 +1,19 @@ +// Memory test for index bug +module main (); +reg [7:0] mem [0:64]; +reg [7:0] val_reg; +wire [7:0] val_wire; + +// Works ok +assign val_wire = mem[67]; + +initial + begin + + // This should generate an error. + val_reg = mem; + + end + + +endmodule diff --git a/ivtest/ivltests/memidxrng.v b/ivtest/ivltests/memidxrng.v new file mode 100644 index 000000000..ec94bf265 --- /dev/null +++ b/ivtest/ivltests/memidxrng.v @@ -0,0 +1,59 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// $Id: memidxrng.v,v 1.1 2001/09/29 05:03:41 sib4 Exp $ +// $Log: memidxrng.v,v $ +// Revision 1.1 2001/09/29 05:03:41 sib4 +// add memidxrng.v: memory address range check +// + +module memidxrng; + + reg mem[12:2]; + + reg [7:0] i; + integer errs = 0; + + initial + begin + for (i=0; i<255; i=i+1) mem[i] <= ^i; + #1; + for (i=0; i<17; i=i+1) + $display("mem[%d] = %b \%b", i, mem[i], ^i); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + if (mem[13] !== 1'bx) + begin + $display("FAILED: mem[13] = %b, expect x", mem[14]); + errs = errs + 1; + end + if (mem[1] !== 1'bx) + begin + $display("FAILED: mem[1] = %b, expect x", mem[1]); + errs = errs + 1; + end +`endif + if (errs===0) + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/meminit.v b/ivtest/ivltests/meminit.v new file mode 100644 index 000000000..7810c9951 --- /dev/null +++ b/ivtest/ivltests/meminit.v @@ -0,0 +1,43 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program checks that the initial value of a memory is x. The + * verilog standard clearly states that reg values must start as x + * values, and implies that memories are the same. + */ +module main; + + reg [3:0] mem [0:1] ; + + initial begin + if (mem[0] !== 4'bxxxx) begin + $display("FAILED -- mem[0] == %b", mem[0]); + $finish; + end + + if (mem[1] !== 4'bxxxx) begin + $display("FAILED -- mem[1] == %b", mem[1]); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/meminit2.v b/ivtest/ivltests/meminit2.v new file mode 100644 index 000000000..89d52db98 --- /dev/null +++ b/ivtest/ivltests/meminit2.v @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program checks that the initial value of a memory is x. The + * verilog standard clearly states that reg values must start as x + * values, and implies that memories are the same. + */ +module main; + + integer mem [0:1] ; + + initial begin + if (mem[0] !== 32'hxxxx) begin + $display("FAILED -- mem[0] == %b", mem[0]); + $finish; + end + + if (mem[1] !== 32'hxxxx) begin + $display("FAILED -- mem[1] == %b", mem[1]); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/memport_bs.v b/ivtest/ivltests/memport_bs.v new file mode 100644 index 000000000..13052dc2b --- /dev/null +++ b/ivtest/ivltests/memport_bs.v @@ -0,0 +1,74 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// $Id: memport_bs.v,v 1.1 2001/10/13 03:35:01 sib4 Exp $ +// $Log: memport_bs.v,v $ +// Revision 1.1 2001/10/13 03:35:01 sib4 +// PR#303 memport_bs.v +// + +module pr303; + + reg [3:0] mem [2:5]; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + wire [3:0] m1 = mem[1]; +`else + wire [3:0] m1 = 4'bxxxx; +`endif + wire [3:0] m2 = mem[2]; + wire [3:0] m3 = mem[3]; + wire [3:0] m4 = mem[4]; + wire [3:0] m5 = mem[5]; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + wire [3:0] m6 = mem[6]; +`else + wire [3:0] m6 = 4'bxxxx; +`endif + + reg [2:0] a; + reg [3:0] e; + + initial + begin + e = 0; + for (a=0; a<7; a=a+1) mem[a] <= a; + #1; + if ( m1 !== 4'hx) begin e=e+1; $display("FAILED m1=%b", m1 ); end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + if (mem[1] !== 4'hx) begin e=e+1; $display("FAILED mem[1]=%b", mem[1]); end +`endif + if ( m2 !== 4'h2) begin e=e+1; $display("FAILED m2=%b", m2 ); end + if (mem[2] !== 4'h2) begin e=e+1; $display("FAILED mem[2]=%b", mem[2]); end + if ( m3 !== 4'h3) begin e=e+1; $display("FAILED m3=%b", m3 ); end + if (mem[3] !== 4'h3) begin e=e+1; $display("FAILED mem[3]=%b", mem[3]); end + if ( m4 !== 4'h4) begin e=e+1; $display("FAILED m4=%b", m4 ); end + if (mem[4] !== 4'h4) begin e=e+1; $display("FAILED mem[4]=%b", mem[4]); end + if ( m5 !== 4'h5) begin e=e+1; $display("FAILED m5=%b", m5 ); end + if (mem[5] !== 4'h5) begin e=e+1; $display("FAILED mem[5]=%b", mem[5]); end + if ( m6 !== 4'hx) begin e=e+1; $display("FAILED m6=%b", m6 ); end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + if (mem[6] !== 4'hx) begin e=e+1; $display("FAILED mem[6]=%b", mem[6]); end +`endif + if (e===0) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/memref.v b/ivtest/ivltests/memref.v new file mode 100644 index 000000000..c296056c9 --- /dev/null +++ b/ivtest/ivltests/memref.v @@ -0,0 +1,27 @@ +/* + * Check simple scope up-reference of memories. + */ +module main; + + reg [7:0] foo [0:5]; + + integer idx; + task showstring; + begin + for (idx = 0 ; idx < 6 ; idx = idx+1) begin + $write("%c", foo[idx]); + end + $display; + end + endtask // showstring + + initial begin + foo[0] = "P"; + foo[1] = "A"; + foo[2] = "S"; + foo[3] = "S"; + foo[4] = "E"; + foo[5] = "D"; + showstring; + end +endmodule // main diff --git a/ivtest/ivltests/memsynth1.v b/ivtest/ivltests/memsynth1.v new file mode 100644 index 000000000..7dfec0792 --- /dev/null +++ b/ivtest/ivltests/memsynth1.v @@ -0,0 +1,113 @@ +/* + * This program tests the synthesis of small memories, including + * aysnchronous read w/ synchronous write. + */ +module main; + + reg [3:0] mem [1:0], D; + reg rst, clk, wr, wadr, radr; + + /* + * This implements the synchronous write port to the memory. + */ + (* ivl_synthesis_on *) + always @(posedge clk) + if (rst) begin + mem[0] <= 0; + mem[1] <= 0; + end else if (wr) begin + mem[wadr] <= D; + end + + /* This is the asynchronous read port from the memory. */ + wire [3:0] Q = mem[radr]; + + (* ivl_synthesis_off *) + initial begin + rst = 0; + clk = 0; + wadr = 0; + radr = 0; + wr = 0; + + #1 clk = 1; + #1 clk = 0; + + // Make sure reset works. + rst = 1; + + #1 clk = 1; + #1 clk = 0; + + #1 if (mem[0] !== 0 || mem[1] !== 0) begin + $display("FAILED -- Reset 1: mem[0]=%b, mem[1]=%b", mem[0], mem[1]); + $finish; + end + + radr = 0; + #1 if (Q !== mem[radr]) begin + $display("FAILED -- mem[%b] = %b, Q=%b", radr, mem[radr], Q); + $finish; + end + + radr = 1; + #1 if (Q !== mem[radr]) begin + $display("FAILED -- mem[%b] = %b, Q=%b", radr, mem[radr], Q); + $finish; + end + + rst = 0; + #1 clk = 1; + #1 clk = 0; + + // Make sure memory remembers value. + if (mem[0] !== 0 || mem[1] !== 0) begin + $display("FAILED -- Reset 2: mem[0]=%b, mem[1]=%b", mem[0], mem[1]); + $finish; + end + + D = 7; + wr = 1; + #1 clk = 1; + #1 clk = 0; + + // Make sure write works. + if (mem[0] !== 7 || mem[1] !== 0) begin + $display("FAILED -- write D=%b: mem[0]=%b, mem[1]=%b", + D, mem[0], mem[1]); + $finish; + end + + D = 2; + wadr = 1; + #1 clk = 1; + #1 clk = 0; + + // Make sure write works. + if (mem[0] !== 7 || mem[1] !== 2) begin + $display("FAILED -- write D=%b: mem[0]=%b, mem[1]=%b", + D, mem[0], mem[1]); + $finish; + end + + radr = 0; + #1 if (Q !== mem[radr]) begin + $display("FAILED -- mem[%b] = %b, Q=%b", radr, mem[radr], Q); + $finish; + end + + wr = 0; + D = 5; + + // Make sure memory remembers written values. + if (mem[0] !== 7 || mem[1] !== 2) begin + $display("FAILED -- write D=%b: mem[0]=%b, mem[1]=%b", + D, mem[0], mem[1]); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/memsynth2.v b/ivtest/ivltests/memsynth2.v new file mode 100644 index 000000000..b84f98b2a --- /dev/null +++ b/ivtest/ivltests/memsynth2.v @@ -0,0 +1,115 @@ +/* + * This program tests the synthesis of small memories, including + * aysnchronous read w/ synchronous write. + */ +module main; + + reg [1:0] mem; + reg D; + reg rst, clk, wr, wadr, radr; + + /* + * This implements the synchronous write port to the memory. + * Asynchronous reset? In this case, yes, even though that is + * not normally the case for RAM devices. + */ + (* ivl_synthesis_on *) + always @(posedge clk or posedge rst) + if (rst) begin + mem[0] <= 0; + mem[1] <= 0; + end else if (wr) begin + mem[wadr] <= D; + + end else begin + end + + /* This is the asynchronous read port from the memory. */ + wire Q = mem[radr]; + + (* ivl_synthesis_off *) + initial begin + rst = 0; + clk = 0; + wadr = 0; + radr = 0; + wr = 0; + + #1 clk = 1; + #1 clk = 0; + + // Make sure reset works. + rst = 1; + + #1 if (mem[0] !== 0 || mem[1] !== 0) begin + $display("FAILED -- Reset: mem[0]=%b, mem[1]=%b", mem[0], mem[1]); + $finish; + end + + radr = 0; + #1 if (Q !== mem[radr]) begin + $display("FAILED -- mem[%b] = %b, Q=%b", radr, mem[radr], Q); + $finish; + end + + radr = 1; + #1 if (Q !== mem[radr]) begin + $display("FAILED -- mem[%b] = %b, Q=%b", radr, mem[radr], Q); + $finish; + end + + rst = 0; + #1 clk = 1; + #1 clk = 0; + + // Make sure memory remembers value. + if (mem[0] !== 0 || mem[1] !== 0) begin + $display("FAILED -- Reset: mem[0]=%b, mem[1]=%b", mem[0], mem[1]); + $finish; + end + + D = 1; + wr = 1; + #1 clk = 1; + #1 clk = 0; + + // Make sure write works. + if (mem[0] !== 1 || mem[1] !== 0) begin + $display("FAILED -- write D=%b: mem[0]=%b, mem[1]=%b", + D, mem[0], mem[1]); + $finish; + end + + D = 0; + wadr = 1; + #1 clk = 1; + #1 clk = 0; + + // Make sure write works. + if (mem[0] !== 1 || mem[1] !== 0) begin + $display("FAILED -- write D=%b: mem[0]=%b, mem[1]=%b", + D, mem[0], mem[1]); + $finish; + end + + radr = 0; + #1 if (Q !== mem[radr]) begin + $display("FAILED -- mem[%b] = %b, Q=%b", radr, mem[radr], Q); + $finish; + end + + wr = 0; + D = 1; + + // Make sure memory remembers written values. + if (mem[0] !== 1 || mem[1] !== 0) begin + $display("FAILED -- write D=%b: mem[0]=%b, mem[1]=%b", + D, mem[0], mem[1]); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/memsynth3.v b/ivtest/ivltests/memsynth3.v new file mode 100644 index 000000000..3dc93cf64 --- /dev/null +++ b/ivtest/ivltests/memsynth3.v @@ -0,0 +1,80 @@ +`begin_keywords "1364-2005" +module main; + + reg [3:0] foo, bar; + reg [1:0] adr; + + reg bit, rst, clk; + reg load_enable, write_enable; + + (* ivl_synthesis_on *) + always @(posedge clk or posedge rst) + if (rst) begin + foo <= 0; + + end else if (load_enable) begin + foo <= bar; + + end else if (write_enable) begin + foo[adr] <= bit; + + end + + (* ivl_synthesis_off *) + initial begin + rst = 1; + clk = 0; + bar = 4'bzzzz; + load_enable = 0; + write_enable = 0; + + #1 clk = 1; + #1 clk = 0; + + if (foo !== 4'b0000) begin + $display("FAILED -- reset foo=%b", foo); + $finish; + end + + rst = 0; + bar = 4'b1001; + load_enable = 1; + write_enable = 0; + + #1 clk = 1; + #1 clk = 0; + + if (foo !== bar) begin + $display("FAILED -- load foo=%b, bar=%b", foo, bar); + $finish; + end + + load_enable = 0; + write_enable = 0; + + #1 clk = 1; + #1 clk = 0; + if (foo !== 4'b1001) begin + $display("FAILED -- foo=%b after clk", foo); + $finish; + end + + adr = 1; + bit = 1; + load_enable = 0; + write_enable = 1; + + #1 clk = 1; + #1 clk = 0; + + if (foo !== 4'b1011) begin + $display("FAILED -- foo=%b, adr=%b, bit=%b", foo, adr, bit); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main +`end_keywords diff --git a/ivtest/ivltests/memsynth4.v b/ivtest/ivltests/memsynth4.v new file mode 100644 index 000000000..ac5f63814 --- /dev/null +++ b/ivtest/ivltests/memsynth4.v @@ -0,0 +1,41 @@ +module main; + + reg clk; + reg mem[1:0]; + reg clr; + + (* ivl_synthesis_on *) + always @(posedge clk) + if (clr) begin + mem[1] <= 1; + mem[0] <= 0; + end else begin + mem[1] <= ~mem[1]; + mem[0] <= ~mem[0]; + end + + (* ivl_synthesis_off *) + initial begin + clk = 0; + clr = 1; + #1 clk = 1; + #1 clk = 0; + + if (mem[0] !== 0 || mem[1] !== 1) begin + $display("FAILED -- clr"); + $finish; + end + + clr = 0; + #1 clk = 1; + #1 clk = 0; + + if (mem[0] !== 1 || mem[1] !== 0) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/memsynth5.v b/ivtest/ivltests/memsynth5.v new file mode 100644 index 000000000..d3715cb91 --- /dev/null +++ b/ivtest/ivltests/memsynth5.v @@ -0,0 +1,62 @@ +module main; + + reg [7:0] mem [7:0], D; + reg [2:0] radr, wadr; + reg wr, rst, clk; + + /* + * This implements the synchronous write port to the memory. + */ + always @(posedge clk) + + if (rst) begin + mem[0] <= 0; + mem[1] <= 0; + mem[2] <= 0; + mem[3] <= 8'h33; + mem[5] <= 8'h55; + mem[6] <= 0; + mem[7] <= 0; + end else + if (wr) begin + mem[wadr] <= D; + end + + // This is the asynchronous read port from the memory. + wire[7:0] Q = mem[radr]; + + initial begin + wr = 0; + rst = 1; + clk = 0; + #1 clk = 1; + #1 clk = 0; + + radr = 3; + #1 if (Q !== 8'h33) begin + $display("FAILED -- mem[3] == 'b%b", Q); + $finish; + end + + radr = 5; + #1 if (Q !== 8'h55) begin + $display("FAILED == mem[5] == 'b%b", Q); + $finish; + end + + wadr = 4; + wr = 1; + rst = 0; + D = 'h44; + #1 clk = 1; + #1 clk = 0; + + radr = 4; + #1 if (Q !== 8'h44) begin + $display("FAILED -- mem[4] == 'b%b", Q); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/memsynth6.v b/ivtest/ivltests/memsynth6.v new file mode 100644 index 000000000..b39f1c971 --- /dev/null +++ b/ivtest/ivltests/memsynth6.v @@ -0,0 +1,40 @@ +module main; + + reg [7:0] mem [7:0], D; + reg [3:0] radr, wadr; + reg wr, clk; + + /* + * This implements the synchronous write port to the memory. + */ + always @(posedge clk) + if (wr) mem[wadr] <= D; + + // This is the asynchronous read port from the memory. + wire[7:0] Q = mem[radr]; + + (* ivl_synthesis_off *) + initial begin + wr = 0; + clk = 0; + #1 clk = 1; + #1 clk = 0; + + for (wadr = 0 ; wadr < 8 ; wadr = wadr+1) begin + wr = 1; + D = { 2{wadr} }; + #1 clk = 1; + #1 clk = 0; + end + + wr = 0; + for (radr = 0 ; radr < 8 ; radr = radr+1) begin + #1 if (Q !== {2{radr}}) begin + $display("FAILED -- mem[%d] == 'b%b", radr, Q); + $finish; + end + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/memsynth7.v b/ivtest/ivltests/memsynth7.v new file mode 100644 index 000000000..f6c53f909 --- /dev/null +++ b/ivtest/ivltests/memsynth7.v @@ -0,0 +1,77 @@ +module main; + + reg [7:0] a; + reg [2:0] adr, w_adr; + reg rst, clk, ae, wr; + + (* ivl_synthesis_on *) + always @(posedge clk) + if (rst) begin + a <= 8'b00000000; + adr <= 3'b000; + end else if (ae) begin + adr <= w_adr; + end else if (wr) begin + adr <= adr + 1; + a[adr] <= 1; + end + + (* ivl_synthesis_off *) + initial begin + + clk = 0; + wr = 0; + ae = 0; + rst = 1; + #1 clk = 1; + #1 clk = 0; + if (a !== 8'b0000_0000 || adr !== 3'b000) begin + $display("FAILED - reset - a=%b, adr=%b", a, adr); + $finish; + end + + rst = 0; + #1 clk = 1; + #1 clk = 0; + if (a !== 8'b0000_0000 || adr !== 3'b000) begin + $display("FAILED - pause - a=%b, adr=%b", a, adr); + $finish; + end + + wr = 1; + #1 clk = 1; + #1 clk = 0; + if (a !== 8'b0000_0001 || adr !== 3'b001) begin + $display("FAILED - wr 1 - a=%b, adr=%b", a, adr); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + if (a !== 8'b0000_0011 || adr !== 3'b010) begin + $display("FAILED - wr 2 - a=%b, adr=%b", a, adr); + $finish; + end + + ae = 1; + w_adr = 4; + #1 clk = 1; + #1 clk = 0; + if (a !== 8'b0000_0011 || adr !== 3'b100) begin + $display("FAILED - ae - a=%b, adr=%b", a, adr); + $finish; + end + + ae = 0; + #1 clk = 1; + #1 clk = 0; + if (a !== 8'b0001_0011 || adr !== 3'b101) begin + $display("FAILED - ae - a=%b, adr=%b", a, adr); + $finish; + end + + $display("PASSED"); + + end + +endmodule // main diff --git a/ivtest/ivltests/memsynth8.v b/ivtest/ivltests/memsynth8.v new file mode 100644 index 000000000..9ce49715e --- /dev/null +++ b/ivtest/ivltests/memsynth8.v @@ -0,0 +1,31 @@ +module main; + + reg [7:0] mem; + reg [2:0] addr; + reg out; + reg clk; + + (* ivl_synthesis_on *) + always @(posedge clk) out <= mem[addr]; + + integer idx; + (* ivl_synthesis_off *) + initial begin + mem = 8'hca; + addr = 0; + clk = 0; + + for (idx = 0 ; idx < 8 ; idx = idx+1) begin + addr = idx[2:0]; + #1 clk = 1; + #1 clk = 0; + if (out !== mem[idx]) begin + $display("FAILED -- mem[%d] = %b", idx, out); + $finish; + end + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/memsynth9.v b/ivtest/ivltests/memsynth9.v new file mode 100644 index 000000000..f717f6d07 --- /dev/null +++ b/ivtest/ivltests/memsynth9.v @@ -0,0 +1,55 @@ +module main; + + parameter CACHE_RAM = 128; + parameter ADR_WIDTH = 7; + + reg [31:0] buff[0:CACHE_RAM], data_o, data_i; + + reg [ADR_WIDTH-1:0] addr; + reg clk, rst, wr; + + (* ivl_synthesis_on *) + always @(posedge clk) + if (wr) buff[addr] <= data_i; + + (* ivl_synthesis_on *) + always @(posedge clk or posedge rst) + begin + if (rst) + data_o <= 32'h0; + else if (wr) + data_o <= data_i; + else + data_o <= buff[addr]; + end + + (* ivl_synthesis_off *) + initial begin + clk = 0; + rst = 0; + wr = 1; + for (addr = 0 ; addr < 64 ; addr = addr+1) begin + data_i <= addr; + #1 clk = 1; + #1 clk = 0; + if (data_o !== data_i) begin + $display("FAILED -- write addr=0x%h, data_o=%h", addr, data_o); + $finish; + end + end + + wr = 0; + data_i = 32'hx; + for (addr = 0 ; addr < 64 ; addr = addr+1) begin + #1 clk = 1; + #1 clk = 0; + if (data_o !== addr) begin + $display("FAILED -- read addr=0x%h, data_o=%h", addr, data_o); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/mhead_task.v b/ivtest/ivltests/mhead_task.v new file mode 100644 index 000000000..41260b2c0 --- /dev/null +++ b/ivtest/ivltests/mhead_task.v @@ -0,0 +1,35 @@ +// +// Copyright (c) 1999 Steve Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate fork template 2 + +module main; + + initial begin + other_main.passed; + end + +endmodule // main + +module other_main; + + task passed; + $display("PASSED"); + endtask // passed + +endmodule diff --git a/ivtest/ivltests/mix_reset.v b/ivtest/ivltests/mix_reset.v new file mode 100644 index 000000000..413648644 --- /dev/null +++ b/ivtest/ivltests/mix_reset.v @@ -0,0 +1,64 @@ +module main; + + reg [7:0] data_i; + reg [2:0] addr; + reg clk, rst, wr; + + reg [7:0] data_o, buff[0:7]; + + (* ivl_synthesis_on *) + always @(posedge clk or posedge rst) + begin + if (rst) + data_o <= 8'h0; + else if (wr) begin + buff[addr] <= data_i; + data_o <= data_i; + end else + data_o <= buff[addr]; + end + + (* ivl_synthesis_off *) + initial begin + clk = 0; + rst = 1; + wr = 1; + addr = 0; + data_i = 8'hff; + + #1 clk = 1; + #1 clk = 0; + if (data_o !== 8'h00) begin + $display("FAILED -- reset data_o=%b", data_o); + $finish; + end + + rst = 0; + wr = 1; + + for (addr = 0; addr < 7; addr = addr+1) begin + data_i = addr; + #1 clk = 1; + #1 clk = 0; + if (data_o !== data_i) begin + $display("FAILED -- write data_i=%h, data_o=%h", data_i, data_o); + $finish; + end + end + + wr = 0; + data_i = 8'hff; + + for (addr = 0 ; addr < 7; addr = addr+1) begin + #1 clk = 1; + #1 clk = 0; + if (data_o !== {5'b00000, addr}) begin + $display("FAILED -- read addr=%h, data_o=%h", addr, data_o); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/mixed_type_div_mod.v b/ivtest/ivltests/mixed_type_div_mod.v new file mode 100644 index 000000000..6ca69007a --- /dev/null +++ b/ivtest/ivltests/mixed_type_div_mod.v @@ -0,0 +1,43 @@ +`ifdef __ICARUS__ + `define SUPPORT_REAL_MODULUS_IN_IVTEST +`endif + +module top; + reg pass; + real result; + initial begin + pass = 1'b1; + + // This should turn into a just a load of 0.5. + result = 1/2.0; + if (result != 0.5) begin + $display("Failed: int/real, expected 0.5, got %g", result); + pass = 1'b0; + end + + // This should turn into a just a load of 0.5. + result = 1.0/2; + if (result != 0.5) begin + $display("Failed: real/int, expected 0.5, got %g", result); + pass = 1'b0; + end + +`ifdef SUPPORT_REAL_MODULUS_IN_IVTEST + // This should turn into a just a load of 1.0. + result = 1%2.0; + if (result != 1.0) begin + $display("Failed: int%%real, expected 1.0, got %g", result); + pass = 1'b0; + end + + // This should turn into a just a load of 1.0. + result = 1.0%2; + if (result != 1.0) begin + $display("Failed: real%%int, expected 1.0, got %g", result); + pass = 1'b0; + end +`endif + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/mixed_width_case.v b/ivtest/ivltests/mixed_width_case.v new file mode 100644 index 000000000..1b9e08595 --- /dev/null +++ b/ivtest/ivltests/mixed_width_case.v @@ -0,0 +1,87 @@ +module mixed_width_case(); + +function [2:0] lookup1(input signed [2:0] value); + +begin + case (value) + 4'sb0100 : lookup1 = 1; + 3'sb100 : lookup1 = 2; + 2'sb10 : lookup1 = 3; + default : lookup1 = 4; + endcase + $display("case = %d", lookup1); +end + +endfunction + +function [2:0] lookup2(input signed [2:0] value); + +begin + case (value) + 4'b1100 : lookup2 = 1; + 3'sb100 : lookup2 = 2; + 2'sb10 : lookup2 = 3; + default : lookup2 = 4; + endcase + $display("case = %d", lookup2); +end + +endfunction + +function [2:0] lookup3(input real value); + +begin + case (value) + 4'b0001 : lookup3 = 1; + 3'sb010 : lookup3 = 2; + 2'sb11 : lookup3 = 3; + default : lookup3 = 4; + endcase + $display("case = %d", lookup3); +end + +endfunction + +function [2:0] lookup4(input signed [2:0] value); + +begin + case (value) + 4'b0110 : lookup4 = 1; + 3'sb110 : lookup4 = 2; + -1.0 : lookup4 = 3; + default : lookup4 = 4; + endcase + $display("case = %d", lookup4); +end + +endfunction + +reg [2:0] result; + +reg failed = 0; + +initial begin + result = lookup1(3'sb100); if ( result != 2) failed = 1; + result = lookup1(3'sb110); if ( result != 3) failed = 1; + result = lookup1(3'sb010); if ( result != 4) failed = 1; + $display(""); + result = lookup2(3'sb100); if ( result != 2) failed = 1; + result = lookup2(3'sb010); if ( result != 3) failed = 1; + result = lookup2(3'sb110); if ( result != 4) failed = 1; + $display(""); + result = lookup3( 1.0); if ( result != 1) failed = 1; + result = lookup3( 2.0); if ( result != 2) failed = 1; + result = lookup3(-1.0); if ( result != 3) failed = 1; + result = lookup3( 1.5); if ( result != 4) failed = 1; + $display(""); + result = lookup4(3'sb110); if ( result != 2) failed = 1; + result = lookup4(3'sb111); if ( result != 3) failed = 1; + result = lookup4(3'sb011); if ( result != 4) failed = 1; + $display(""); + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/mod_inst_pkg.v b/ivtest/ivltests/mod_inst_pkg.v new file mode 100644 index 000000000..d9563ae23 --- /dev/null +++ b/ivtest/ivltests/mod_inst_pkg.v @@ -0,0 +1,67 @@ +package fooPkg; + localparam FOO = 5; +endpackage + +package barPkg; + function int get_size ( + input int x + ); + return x + 3; + endfunction +endpackage + +package bazPkg; + typedef int baz; +endpackage + +/* +IEEE 1800-2012 A.1.2 says: + +module_nonansi_header ::= + { attribute_instance } module_keyword [ lifetime ] module_identifier + { package_import_declaration } [ parameter_port_list ] list_of_ports ; +module_ansi_header ::= + { attribute_instance } module_keyword [ lifetime ] module_identifier + { package_import_declaration } [ parameter_port_list ] [ list_of_port_declarations ] ; + +This allows for the importing of packages during module definition which can be used in the + parameter and port lists. +*/ + +module foo +// Testing comman separated imports +import + fooPkg::*, + barPkg::*; +// Testing multiple import statements +import bazPkg::*; +#( + parameter FOO_PARAM = FOO +) +( + input [get_size(7)-1:0] inport +); + + baz value = 11; + + initial begin + if ($bits(inport) != 10) begin + $display("FAILED -- function import in module declaration failed (%d)", $bits(inport)); + $finish; + end + + if (value != 11) begin + $display("FAILED -- Something is wrong with typedef import (%d)", value); + $finish; + end + + if (FOO_PARAM != 5) begin + $display("FAILED -- Something is wrong with paramater imports (%d)", FOO_PARAM); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/modparam.v b/ivtest/ivltests/modparam.v new file mode 100644 index 000000000..a449940a0 --- /dev/null +++ b/ivtest/ivltests/modparam.v @@ -0,0 +1,159 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate parameter passing override in module declaration. +// +// Build a single line of storage - Note it's +// + +module reg32 (clk,we, din, dout); + +parameter WIDTH=32; + +input we; +input clk; +input [WIDTH-1:0] din; + +output [WIDTH-1:0] dout; + +reg [WIDTH-1:0] store; + +always @(posedge clk) + if(we) + store <= din; + +assign dout = store ; + +endmodule + +module memory(clk, we, addr, din, dout); + +parameter WIDTH=8; + +input clk; +input we; +input [1:0] addr; +input [WIDTH-1:0] din; + +output [WIDTH-1:0] dout; +reg [WIDTH-1:0] dout; + +wire [WIDTH-1:0] dout0,dout1,dout2,dout3; +reg we0,we1,we2,we3; + +reg32 #(WIDTH) reg0 (.clk(clk),.we(we0),.din(din[WIDTH-1:0]), + .dout(dout0[WIDTH-1:0])); +reg32 #(WIDTH) reg1 (.clk(clk),.we(we1),.din(din[WIDTH-1:0]), + .dout(dout1[WIDTH-1:0])); +reg32 #(WIDTH) reg2 (.clk(clk),.we(we2),.din(din[WIDTH-1:0]), + .dout(dout2[WIDTH-1:0])); +reg32 #(WIDTH) reg3 (.clk(clk),.we(we3),.din(din[WIDTH-1:0]), + .dout(dout3[WIDTH-1:0])); + +// +// Build we decode +// +always @(addr or we) + case (addr) + 2'b00: begin + we0 = we; + we1 = 0; + we2 = 0; + we3 = 0; + end + 2'b01: begin + we0 = 0; + we1 = we; + we2 = 0; + we3 = 0; + end + 2'b10: begin + we0 = 0; + we1 = 0; + we2 = we; + we3 = 0; + end + 2'b11: begin + we0 = 0; + we1 = 0; + we2 = 0; + we3 = we; + end + endcase + +// +// Connect dout to register output +// +always @(addr or dout0 or dout1 or dout2 or dout3) + case (addr) + 2'b00: dout = dout0; + 2'b01: dout = dout1; + 2'b10: dout = dout2; + 2'b11: dout = dout3; + endcase + +endmodule + +module top; + +parameter WIDTH=8; +reg clk; +reg we; +reg [1:0] addr; +reg [WIDTH-1:0] din; +reg error; +wire [WIDTH-1:0] dout; + +memory mem (clk, we, addr, din, dout); + +initial + begin +// $dumpfile("test.vcd"); +// $dumpvars(0,top.mem.reg0); + + clk = 0; + error =0; + #3; + we = 1; + addr = 0; + din = 32'b0_00; + #10; + addr = 1; + din = 32'h1; + #10; + addr = 2; + din = 32'h2; + #10; + addr = 3; + din = 32'h3; + #10; + we = 0; + addr = 0; + #1; + if(dout[7:0] !== 8'h00) + begin + $display("FAILED - Ram[0] not 0, is %h",dout[7:0]); + error = 1; + end + if(error == 0) + $display("PASSED"); + $finish ; + end + +always #(5) clk = ~clk; +endmodule diff --git a/ivtest/ivltests/module3.12A.v b/ivtest/ivltests/module3.12A.v new file mode 100644 index 000000000..3b7ad94c3 --- /dev/null +++ b/ivtest/ivltests/module3.12A.v @@ -0,0 +1,74 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate various module formats + + +// Template 1 + +module mod1 ; +endmodule + +// Template 2 +module mod2 (); +endmodule + +// Template 3 +module mod3 (a,b); +input a; +input b; +endmodule + +//Template 4 - +module mod4 (ident1,out1); +input [31:0] ident1; +output [31:0] out1; + +wire [31:0] out1 = ident1; +endmodule + +module main (); + +wire [31:0] out1,out2; +reg [31:0] val1,val2; +reg error; + +mod4 inst1 (val1,out1); // Ordered port list +mod4 inst2 (.ident1(val2),.out1(out2)); // List by portname + +initial + begin + error = 0; + val1 = 32'h11223344; + #1 if(out1 != 32'h11223344) + begin + $display("FAILED - module 3.12A - Ordered module port list failed"); + error = 1; + end + val2 = 32'h44332211; + #1 if(out2 != 32'h44332211) + begin + $display("FAILED -module 3.12A -named module port list (.x(a)) failed"); + error = 1; + end + if(error == 0) + $display("PASSED"); + end + + +endmodule // main diff --git a/ivtest/ivltests/module3.12B.v b/ivtest/ivltests/module3.12B.v new file mode 100644 index 000000000..dc066538f --- /dev/null +++ b/ivtest/ivltests/module3.12B.v @@ -0,0 +1,37 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate various module formats + + +module foo(a); + output a; + wire a = 1'b1 ; +endmodule + +module main; + wire b; + foo foo1 (.a()); + foo foo2 (.a(b)); + + initial + if(!b) + $display("FAILED - 3.12B - Module with output only failed"); + else + $display("PASSED"); +endmodule // main diff --git a/ivtest/ivltests/module3.12C.v b/ivtest/ivltests/module3.12C.v new file mode 100644 index 000000000..6f73dc2ff --- /dev/null +++ b/ivtest/ivltests/module3.12C.v @@ -0,0 +1,37 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate module a(),b(); + + +module foo(a); + output a; + wire a = 1'b1 ; +endmodule + +module main; + wire b; + foo foo1 (.a()), + foo2 (.a(b)); + + initial + if(!b) + $display("FAILED - 3.12C - Module with output only failed"); + else + $display("PASSED"); +endmodule // main diff --git a/ivtest/ivltests/modulus.v b/ivtest/ivltests/modulus.v new file mode 100644 index 000000000..e48fd07ec --- /dev/null +++ b/ivtest/ivltests/modulus.v @@ -0,0 +1,88 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate Modulus operator + +module top; + +reg [7:0] a,b; +wire [7:0] wa,wb; +reg [7:0] result; +wire [7:0] wresult; +reg [15:0] work; +reg error; + +assign wa = a; +assign wresult = work % a; + +always @ (work or wa) + result = work % a; + +initial + begin + error = 0; + /* Try mod div by 0 */ + #1; + a = 0; + work = 16'd1235; + #1; + if(wresult !== 8'hxx) + begin + $display("FAILED - wire 1235 mod 0: wresult = %h",wresult); + error =1; + end + if(result !== 8'hxx) + begin + $display("FAILED - reg 1235 mod 0: result = %h",result); + error =1; + end + #1; + a = 8'd10; + #1; + if(wresult !== 8'h05) + begin + $display("FAILED - wire 1235 mod 10: wresult = %h",wresult); + error =1; + end + if(result !== 8'h05) + begin + $display("FAILED - reg 1235 mod 10: result = %h",result); + error =1; + end + + #1; + a = 8'b0000_x001; + #1; + if(wresult !== 8'bxxxx_xxxx) + begin + $display("FAILED - wire 1235 mod 10: wresult = %h",wresult); + error =1; + end + if(result !== 8'bxxxx_xxxx) + begin + $display("FAILED - reg 1235 mod 10: result = %h",result); + error =1; + end + + + if(error == 0) + $display("PASSED"); + + end + +endmodule diff --git a/ivtest/ivltests/modulus2.v b/ivtest/ivltests/modulus2.v new file mode 100644 index 000000000..6c449f932 --- /dev/null +++ b/ivtest/ivltests/modulus2.v @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program tests the behavioral modulus operator, to make sure it + * works at least minimally. + */ + +module main; + + reg [15:0] a, b, c; + + initial begin + a = 1; + b = 1; + c = a % b; + + if (c !== 16'd0) begin + $display("FAILED -- 1 %% 1 == 'b%b", c); + $finish; + end + + a = 9; + b = 8; + c = a % b; + + if (c !== 16'd1) begin + $display("FAILED -- 9 %% 8 == 'b%b", c); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/monitor.v b/ivtest/ivltests/monitor.v new file mode 100644 index 000000000..ed86f692d --- /dev/null +++ b/ivtest/ivltests/monitor.v @@ -0,0 +1,32 @@ +// Copyright (c) 2001 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +// This trivial program shows that the $monitor system task really does +// seem to work. + +module main; + reg clk = 0; + + always #5 clk = ~clk; + + initial begin + $monitor($time,, "clk=%b", clk); + #61 $finish(0); + end + +endmodule diff --git a/ivtest/ivltests/monitor2.v b/ivtest/ivltests/monitor2.v new file mode 100644 index 000000000..36e0b6fcd --- /dev/null +++ b/ivtest/ivltests/monitor2.v @@ -0,0 +1,51 @@ +/* + I seem to have found a problem with the $monitor task/events. + (this is probably related to bug 399) + The problem only seems to arise in vvp mode and not in vvm. + Problem: $monitor seems to lose both the first and last time steps. + + A complete copy of the run follows with source appended at the end. + (The correct output from vvm is shown in the last run) + This file compiles and produces the problem. + + jungle_geo@hotmail.com + +*/ + +/* + +bubba> uname -a +Linux bubba 2.2.15-4mdk #1 Wed May 10 15:31:30 CEST 2000 i686 unknown + +bubba> iverilog -V +Icarus Verilog version 0.6 +Copyright 1998-2002 Stephen Williams +$Name: $ + +bubba> iverilog -Wall -tvvp stim.v +bubba> a.out +Time = 1 a = 1 + +bubba> iverilog -Wall -tvvm stim.v +bubba> a.out +Time = 0 a = 0 +Time = 1 a = 1 +Time = 2 a = 0 + +*/ + +// -------------------------------------------------------------------------stim +module stim; + reg a; + + initial begin + a = 0; + #1 a = 1; + #1 a = 0; + end + + initial begin + $monitor("Time = %0d a = %b", $time, a); + end + +endmodule diff --git a/ivtest/ivltests/monitor3.v b/ivtest/ivltests/monitor3.v new file mode 100644 index 000000000..33141a5f0 --- /dev/null +++ b/ivtest/ivltests/monitor3.v @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + real x, y; + + initial begin + $monitor("%t: x=%f, y=%f", $time, x, y); + #1 x = 1.0; + #1 y = 2.0; + #1 x = 1.5; + #1 y = 5.1; + #1 $finish(0); + end + +endmodule // main diff --git a/ivtest/ivltests/mult1.v b/ivtest/ivltests/mult1.v new file mode 100644 index 000000000..7a22c6d94 --- /dev/null +++ b/ivtest/ivltests/mult1.v @@ -0,0 +1,128 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - multiply operator + +module top () ; + +reg [3:0] a,b; +wire [3:0] wa,wb; +reg [7:0] result; +wire [8:0] wresult; + +assign wa = a; +assign wb = b; +assign wresult = wa * wb; + +always @(a or b) + result = a * b; + +initial + begin + #1; + a = 0; + b = 0; + # 1; + if( result !== 8'b0) + begin + $display("FAILED - Mult 0*0 reg assign failed - is %b",result); + $finish; + end + if( wresult !== 9'b0) + begin + $display("FAILED - Mult 0*0 wire assign failed - is %b",result); + $finish; + end + + #1; + a = 1; + #1; + if( result !== 8'b0) + begin + $display("FAILED - Mult 0*1 reg assign failed - is %b",result); + $finish; + end + if( wresult !== 9'b0) + begin + $display("FAILED - Mult 0*1 wire assign failed - is %b",result); + $finish; + end + + #1; + b = 1; + #1; + if( result !== 8'b1) + begin + $display("FAILED - Mult 1*1 reg assign failed - is %b",result); + $finish; + end + if( wresult !== 9'b1) + begin + $display("FAILED - Mult 1*1 wire assign failed - is %b",result); + $finish; + end + + #1; + a = 2; + #1; + if( result !== 8'h2) + begin + $display("FAILED - Mult 2*1 reg assign failed - is %b",result); + $finish; + end + if( wresult !== 9'h2) + begin + $display("FAILED - Mult 2*1 wire assign failed - is %b",result); + $finish; + end + + #1; + a = 2; + b = 3; + #1; + if( result !== 8'h6) + begin + $display("FAILED - Mult 2*3 reg assign failed - is %b",result); + $finish; + end + if( wresult !== 9'h6) + begin + $display("FAILED - Mult 2*3 wire assign failed - is %b",result); + $finish; + end + + #1; + a = 1'bx; + b = 3; + #1; + if( result !== 8'bxxxx_xxxx) + begin + $display("FAILED - Mult 2*x reg assign failed - is %b",result); + $finish; + end + if( wresult !== 9'bx_xxxx_xxxx) + begin + $display("FAILED - Mult 2*x wire assign failed - is %b",wresult); + $finish; + end + + $display("PASSED"); + + end + +endmodule diff --git a/ivtest/ivltests/mult16.v b/ivtest/ivltests/mult16.v new file mode 100644 index 000000000..47750c23d --- /dev/null +++ b/ivtest/ivltests/mult16.v @@ -0,0 +1,171 @@ +// +// Copyright (c) 1999 Thomas Coonan (tcoonan@mindspring.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// **** Here's a simple, sequential multiplier. Very simple, unsigned.. +// Not very well tested, play with testbench, use at your own risk, blah blah blah.. +// + +// +// Unsigned 16-bit multiply (multiply two 16-bit inputs to get a 32-bit output) +// +// Present data and assert start synchronous with clk. +// Assert start for ONLY one cycle. +// Wait N cycles for answer (at most). Answer will remain stable until next start. +// You may use DONE signal as handshake. +// +// Written by tom coonan +// +module mult16 (clk, resetb, start, done, ain, bin, yout); +parameter N = 16; +input clk; +input resetb; +input start; // Register the ain and bin inputs (they can change afterwards) +//input [N-1:0] ain; +//input [N-1:0] bin; +//output [2*N-1:0] yout; +input [15:0] ain; +input [15:0] bin; +output [31:0] yout; + +output done; + +//reg [2*N-1:0] a; +//reg [N-1:0] b; +//reg [2*N-1:0] yout; +reg [31:0] a; +reg [15:0] b; +reg [31:0] yout; + +reg done; + +always @(posedge clk or negedge resetb) begin + if (~resetb) begin + a <= 0; + b <= 0; + yout <= 0; + done <= 1'b1; + end + else begin + // Load will register the input and clear the counter. + if (start) begin + a <= ain; + b <= bin; + yout <= 0; + done <= 0; + end + else begin + // Go until b is zero + if (~done) begin + if (b != 0) begin + // If '1' then add a to sum + if (b[0]) begin + yout <= yout + a; + end + b <= b >> 1; + a <= a << 1; + $display ("a = %h, b = %h, yout = %h", a,b,yout); + end + else begin + done <= 1'b1; + end + end + end + end +end +endmodule + + +module mul16; +reg clk, resetb, start; +reg [15:0] a; +reg [15:0] b; +wire [31:0] y; +wire done; + +mult16 mult16inst (clk, resetb, start, done, a, b, y); + +initial begin + clk = 0; + forever begin + #10 clk = ~clk; + end +end + +initial begin + resetb = 0; + #30 resetb = 1; +end + +integer num_errors; +parameter MAX_TRIALS = 10; + +initial begin +// $dumpfile ("multdiv.vcd"); +// $dumpvars (0,a); +// $dumpvars (0,b); +// $dumpvars (0,y); +// $dumpvars (0,resetb); +// $dumpvars (0,done); + num_errors = 0; + + #100; + + // Do a bunch of random multiplies + repeat (MAX_TRIALS) begin + test_multiply ($random, $random); + end + + // Special cases + test_multiply ($random, 1); + test_multiply (1, $random); + test_multiply ($random, 0); + test_multiply (0, $random); + + $display ("Done. %0d Errors", num_errors); + #800; + $finish; +end + +task test_multiply; + input [15:0] aarg; + input [15:0] barg; + + integer expected_answer; + + begin + if (~done) begin + $display ("Multiplier is Busy!!"); + end + else begin + @(negedge clk); + start = 1; + a = aarg; + b = barg; + @(negedge clk) start = 0; + @(posedge done); + expected_answer = a*b; + $display ("%0d * %0d = %0h, Reality = %0h", a, b, y, expected_answer); + if (y !== expected_answer) begin + $display (" FAILURE!"); + num_errors = num_errors + 1; + end + end + end +endtask + +endmodule diff --git a/ivtest/ivltests/mult2.v b/ivtest/ivltests/mult2.v new file mode 100644 index 000000000..a7ec0d129 --- /dev/null +++ b/ivtest/ivltests/mult2.v @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test some multiply values for an 18*18-->36 multiply. + */ + +module main; + + wire [35:0] p; + reg [17:0] a, b; + reg clk, ce, reset; + + parameter MAX_TRIALS = 1000; + integer idx; + + MULT18X18S dut (p, a, b, clk, ce, reset); + + initial begin + clk <= 0; + ce <= 1; + reset <= 1; + a <= 0; + b <= 0; + #5 clk <= 1; + #5 clk <= 0; + + if (p !== 36'h0) begin + $display("FAILED -- reset p=%h", p); + $finish; + end + + reset <= 0; + + /* A magical value I know failed at one time. */ + a <= 18'h3ff82; + b <= 18'h04000; + + #5 clk <= 1; + #5 clk <= 0; + + if (p !== 36'hfffe08000) begin + $display("FAILED -- %h * %h --> %h", a, b, p); + $finish; + end + + for (idx = 0 ; idx < MAX_TRIALS ; idx = idx + 1) begin + a <= $random; + b <= $random; + + #5 clk <= 1; + #5 clk <= 0; + + if ($signed(p) !== ($signed(a) * $signed(b))) begin + $display("FAILED == %h * %h --> %h", a, b, p); + $finish; + end + end // for (idx = 0 ; idx < `MAX_TRIALS ; idx = idx + 1) + + $display("PASSED"); + end // initial begin + +endmodule // main + +module MULT18X18S (output reg [35:0] P, + input [17:0] A, + input [17:0] B, + input C, CE, R); + + wire [35:0] a_in = { {18{A[17]}}, A[17:0] }; + wire [35:0] b_in = { {18{B[17]}}, B[17:0] }; + wire [35:0] p_in; + reg [35:0] p_out; + + assign p_in = a_in * b_in; + + always @(posedge C) + if (R) + P <= 36'b0; + else if (CE) + P <= p_in; + + +endmodule diff --git a/ivtest/ivltests/multi_bit_strength.v b/ivtest/ivltests/multi_bit_strength.v new file mode 100644 index 000000000..8c5ad4b21 --- /dev/null +++ b/ivtest/ivltests/multi_bit_strength.v @@ -0,0 +1,18 @@ +`timescale 1ns/1ps + +module top; + parameter length = 17; + reg [length*8-1:0] result; + wire [3:0] net; + + assign (pull1, strong0) net = 4'b0110; + + initial begin + #1; + $swrite(result, "%v", net); + $display("All three lines should match:"); + $display("-----------------------------"); + $display("St0_Pu1_Pu1_St0 (reference)"); + $display("%v (display)\n%0s (swrite)", net, result); + end +endmodule diff --git a/ivtest/ivltests/multi_driver_delay.v b/ivtest/ivltests/multi_driver_delay.v new file mode 100644 index 000000000..483d7c402 --- /dev/null +++ b/ivtest/ivltests/multi_driver_delay.v @@ -0,0 +1,38 @@ +`timescale 1us/100ns + +module top; + reg pass = 1; + + reg [3:0] ia = 4'd1, ib = 4'd2; + wire [2:0] icon, irep; + + /* Integer concatenation. */ + assign #1 icon = {ib[1:0], ia[0]}; // 5 + + /* Integer replication. */ + assign #1 irep = {3{ia[0]}}; // 7 + + + initial begin + #0.9; + if (icon !== 3'bx) begin + pass = 1'b0; + $display("Failed: concatenation is not delayed, expected 3'bx got %b.", icon); + end + if (irep !== 3'bx) begin + pass = 1'b0; + $display("Failed: replication is not delayed, expected 3'bx got %b.", irep); + end + #0.1; + #0; + if (icon !== 3'd5) begin + pass = 1'b0; + $display("Failed: concatenation has incorrect value, expected 3'd5 got %b.", icon); + end + if (irep !== 3'd7) begin + pass = 1'b0; + $display("Failed: replication has incorrect value, expected 3'd7 got %b.", irep); + end + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/multiply_large.v b/ivtest/ivltests/multiply_large.v new file mode 100644 index 000000000..26ca43493 --- /dev/null +++ b/ivtest/ivltests/multiply_large.v @@ -0,0 +1,174 @@ +// +// multiply_large.v +// +// Copyright (c) 2001 ajb +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +`define W (65) // any value past 32 will suffice + +module multiplier(a,b,sum); +parameter N=1; + +input[N-1:0] a, b; +output[N-1:0] sum; + +reg [(N-1)*2:0] tmp; +integer i; + +always @(a or b) + begin + tmp = 0; + for(i=0;i y <= i0; + when others => y <= i1; + end case; + end process; +end mux2to1_rtl; diff --git a/ivtest/ivltests/muxtest.v b/ivtest/ivltests/muxtest.v new file mode 100644 index 000000000..ebc3e8b3f --- /dev/null +++ b/ivtest/ivltests/muxtest.v @@ -0,0 +1,92 @@ +module test ; + +wire a; +reg sel,in0, in1; +reg error; + +assign a = sel ? in1 : in0 ; + +initial + begin + error = 0; + #1; + sel = 0; + in0 = 0; + in1 = 0; + #1; + if(a !== 0) + begin + $display("FAILED - (1) Mux error sel=0, in0=in0=0 yet out != 0"); + $display("sel=%b,in0=%b,in1=%b,out=%b", + sel,in0,in1,a); + error = 1; + end + #1; + in0 = 1; + #1; + if(a !== 1) + begin + $display("FAILED - (2) Mux error sel=0, in0=1,in1=0 yet out != 1"); + $display("sel=%b,in0=%b,in1=%b,out=%b", + sel,in0,in1,a); + error = 1; + end + + #1; + sel = 1; + #1; + if(a !== 0) + begin + $display("FAILED - (3) Mux error sel=1, in0=1,in1=0 yet out != 0"); + $display("sel=%b,in0=%b,in1=%b,out=%b", + sel,in0,in1,a); + error = 1; + end + #1; + in1 = 1; + #1; + if(a !== 1) + begin + $display("FAILED - (5) Mux error sel=1, in0=1,in1=1 yet out != 1"); + $display("sel=%b,in0=%b,in1=%b,out=%b", + sel,in0,in1,a); + error = 1; + end + #1; + in0 = 0; + #1; + if(a !== 1) + begin + $display("FAILED - (6) Mux error sel=1, in0=0,in1=1 yet out != 1"); + $display("sel=%b,in0=%b,in1=%b,out=%b", + sel,in0,in1,a); + error = 1; + end + #1; + in1 = 0; + sel = 1'bx; + #1; + if(a !== 0) + begin + $display("FAILED - (8) Mux error sel=X, in0=0,in1=0 yet out != 0"); + $display("sel=%b,in0=%b,in1=%b,out=%b", + sel,in0,in1,a); + error = 1; + end + #1; + in0 = 1; + in1 = 1; + sel = 1'bx; + #1; + if(a !== 1) + begin + $display("FAILED - (9) Mux error sel=X, in0=1,in1=1 yet out != 1"); + $display("sel=%b,in0=%b,in1=%b,out=%b", + sel,in0,in1,a); + error = 1; + end + if(error === 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/named_begin.v b/ivtest/ivltests/named_begin.v new file mode 100644 index 000000000..7b1adba7c --- /dev/null +++ b/ivtest/ivltests/named_begin.v @@ -0,0 +1,5 @@ +module top; + initial begin : named_begin + $display("PASSED"); + end : named_begin +endmodule diff --git a/ivtest/ivltests/named_begin_fail.v b/ivtest/ivltests/named_begin_fail.v new file mode 100644 index 000000000..a9a098f82 --- /dev/null +++ b/ivtest/ivltests/named_begin_fail.v @@ -0,0 +1,5 @@ +module top; + initial begin : named_begin + $display("FAILED"); + end : wrong_name +endmodule diff --git a/ivtest/ivltests/named_event_no_edges.v b/ivtest/ivltests/named_event_no_edges.v new file mode 100644 index 000000000..4bbee0336 --- /dev/null +++ b/ivtest/ivltests/named_event_no_edges.v @@ -0,0 +1,15 @@ +module top; + event my_event; + + // The following two line should be an error + // You can not take the edge of a named event. + always @(posedge my_event) $display("Posedge event."); + always @(negedge my_event) $display("Negedge event."); + // This should work correctly. + always @(my_event) $display("Any event edge."); + + initial begin + #1 ->my_event; + #1 $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/named_fork.v b/ivtest/ivltests/named_fork.v new file mode 100644 index 000000000..e22f1c0fc --- /dev/null +++ b/ivtest/ivltests/named_fork.v @@ -0,0 +1,5 @@ +module top; + initial fork : named_fork + $display("PASSED"); + join : named_fork +endmodule diff --git a/ivtest/ivltests/named_fork_fail.v b/ivtest/ivltests/named_fork_fail.v new file mode 100644 index 000000000..347691944 --- /dev/null +++ b/ivtest/ivltests/named_fork_fail.v @@ -0,0 +1,5 @@ +module top; + initial fork : named_begin + $display("FAILED"); + join : wrong_name +endmodule diff --git a/ivtest/ivltests/nb_array_pv.v b/ivtest/ivltests/nb_array_pv.v new file mode 100644 index 000000000..a2a63bd03 --- /dev/null +++ b/ivtest/ivltests/nb_array_pv.v @@ -0,0 +1,71 @@ +module top; + reg pass = 1'b1; + + integer delay; + reg [3:0] in = 4'h0; + reg [7:0] result [1:0]; + + initial begin + result[0] <= #10 8'h00; + if ($simtime != 0 || result[0] !== 8'bx) begin + $display("Failed #10 blocked at %0t, expected 8'hxx, got %h", + $simtime, result[0]); + pass = 1'b0; + end + @(result[0]); + if ($simtime != 10 || result[0] !== 8'h00) begin + $display("Failed #10 at %0t, expected 8'h00, got %h", + $simtime, result[0]); + pass = 1'b0; + end + + result[0][8:5] <= #10 4'hb; + @(result[0]); + if ($simtime != 20 || result[0] !== 8'h60) begin + $display("Failed MSB #10 at %0t, expected 8'h60, got %h", + $simtime, result[0]); + pass = 1'b0; + end + + result[0][1:-2] <= #10 4'hb; + @(result[0]); + if ($simtime != 30 || result[0] !== 8'h62) begin + $display("Failed LSB #10 at %0t, expected 8'h62, got %h", + $simtime, result[0]); + pass = 1'b0; + end + + delay = 20; + result[1] <= #delay 8'h00; + if ($simtime != 30 || result[1] !== 8'bx) begin + $display("Failed #delay blocked at %0t, expected 8'hxx, got %h", + $simtime, result[1]); + pass = 1'b0; + end + @(result[1]); + if ($simtime != 50 || result[1] !== 8'h00) begin + $display("Failed #delay at %0t, expected 8'h00, got %h", + $simtime, result[1]); + pass = 1'b0; + end + + result[1][8:5] <= #delay 4'hb; + @(result[1]); + if ($simtime != 70 || result[1] !== 8'h60) begin + $display("Failed MSB #delay at %0t, expected 8'h60, got %h", + $simtime, result[1]); + pass = 1'b0; + end + + result[1][1:-2] <= #delay 4'hb; + @(result[1]); + if ($simtime != 90 || result[1] !== 8'h62) begin + $display("Failed LSB #delay at %0t, expected 8'h62, got %h", + $simtime, result[1]); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/nb_assign.v b/ivtest/ivltests/nb_assign.v new file mode 100644 index 000000000..e55cb830d --- /dev/null +++ b/ivtest/ivltests/nb_assign.v @@ -0,0 +1,36 @@ +`begin_keywords "1364-2005" +module top; + reg pass = 1'b1; + reg [1:0] var = 2'b0; + real rvar = 0.0; + integer delay = 3; + + initial begin + // These should both happen at time 2. + var <= #2 2'b01; + rvar <= #2 1.0; + #3 if (var !== 2'b01) begin + $display("FAILED: constant delay (bits)"); + pass = 1'b0; + end + if (rvar != 1.0) begin + $display("FAILED: constant delay (real)"); + pass = 1'b0; + end + + // These should both happen at time 6. + var <= #(delay) 2'b10; + rvar <= #(delay) 2.0; + #4 if (var !== 2'b10) begin + $display("FAILED: calculated delay (bits)"); + pass = 1'b0; + end + if (rvar != 2.0) begin + $display("FAILED: calculated delay (real)"); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/nb_delay.v b/ivtest/ivltests/nb_delay.v new file mode 100644 index 000000000..dc9e3c976 --- /dev/null +++ b/ivtest/ivltests/nb_delay.v @@ -0,0 +1,93 @@ +/* + * For a non-blocking delay the last NB assign in the same thread + * at the same time must set the final result, but you are allowed + * to have multiple assignments in the queue. + */ +module top; + reg passed = 1'b1; + reg out; + real rout; + integer delay; + + initial begin + out <= 1'b1; + out <= 1'b0; + rout <= 0.0; + rout <= 1.0; + #1; + if (out !== 1'b0) begin + $display("FAILED: zero delay, expected 1'b0, got %b", out); + passed = 1'b0; + end + if (rout != 1.0) begin + $display("FAILED: zero delay (real), expected 1.0, got %f", rout); + passed = 1'b0; + end + + out <= #1 1'b0; + out <= #1 1'b1; + rout <= #1 0.0; + rout <= #1 2.0; + #2; + if (out !== 1'b1) begin + $display("FAILED: constant delay, expected 1'b1, got %b", out); + passed = 1'b0; + end + if (rout != 2.0) begin + $display("FAILED: constant delay (real), expected 2.0, got %f", rout); + passed = 1'b0; + end + + delay = 2; + out <= #(delay) 1'b1; + out <= #(delay) 1'b0; + rout <= #(delay) 0.0; + rout <= #(delay) 3.0; + #(delay+1); + if (out !== 1'b0) begin + $display("FAILED: calculated delay, expected 1'b0, got %b", out); + passed = 1'b0; + end + if (rout != 3.0) begin + $display("FAILED: calculated delay (real), expected 3.0, got %f", rout); + passed = 1'b0; + end + + out <= #1 1'b1; + out <= #3 1'b0; + out <= #5 1'b1; + rout <= #1 1.0; + rout <= #3 3.0; + rout <= #5 5.0; + #2; + if (out !== 1'b1) begin + $display("FAILED: first delay, expected 1'b1, got %b", out); + passed = 1'b0; + end + if (rout != 1.0) begin + $display("FAILED: first delay (real), expected 1.0, got %f", rout); + passed = 1'b0; + end + #2; + if (out !== 1'b0) begin + $display("FAILED: second delay, expected 1'b0, got %b", out); + passed = 1'b0; + end + if (rout != 3.0) begin + $display("FAILED: second delay (real), expected 3.0, got %f", rout); + passed = 1'b0; + end + #2; + if (out !== 1'b1) begin + $display("FAILED: third delay, expected 1'b1, got %b", out); + passed = 1'b0; + end + if (rout != 5.0) begin + $display("FAILED: third delay (real), expected 5.0, got %f", rout); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + + end +endmodule diff --git a/ivtest/ivltests/nb_ec_array.v b/ivtest/ivltests/nb_ec_array.v new file mode 100644 index 000000000..eca60ee65 --- /dev/null +++ b/ivtest/ivltests/nb_ec_array.v @@ -0,0 +1,84 @@ +module top; + reg pass = 1'b1; + + integer count; + reg [2:0] icount; + reg clk = 0; + reg [3:0] in = 4'h0; + reg [3:0] result [1:0]; + + always #10 clk = ~clk; + always #20 in = in + 4'h1; + + initial begin + count = 3; + result[0] <= repeat(count) @(posedge clk) in; + if ($simtime != 0 || result[0] !== 4'bx) begin + $display("Failed repeat(3) blocked at %0t, expected 4'hx, got %h", + $simtime, result[0]); + pass = 1'b0; + end + @(result[0]); + if ($simtime != 50 || result[0] !== 4'h0) begin + $display("Failed repeat(3) at %0t, expected 4'h0, got %h", + $simtime, result[0]); + pass = 1'b0; + end + + #15; + count = 0; + result[0] <= repeat(count) @(posedge clk) in; + @(result[0]); // Reals happen faster they can use an #0, vectors are slower. + if ($simtime != 65 || result[0] !== 4'h3) begin + $display("Failed repeat(0) at %0t, expected 4'h3, got %h", + $simtime, result[0]); + pass = 1'b0; + end + + #20; + count = -1; + result[0] <= repeat(count) @(posedge clk) in; + @(result[0]); // Reals happen faster they can use an #0, vectors are slower. + if ($simtime != 85 || result[0] !== 4'h4) begin + $display("Failed repeat(-1) at %0t, expected 4'h4, got %h", + $simtime, result[0]); + pass = 1'b0; + end + + #20; + result[0] <= @(posedge clk) 4'h0; + result[0] <= @(posedge clk) in; // This one sets the final value. + @(result[0]); + if ($simtime != 110 || result[0] !== 4'h5) begin + $display("Failed @ at %0t, expected 4'h5, got %h", + $simtime, result[0]); + pass = 1'b0; + end + + icount = 3'd2; + result[0] <= @(posedge clk) 4'h1; + result[0] <= repeat(icount) @(posedge clk) 4'h2; + result[0] <= repeat(3) @(posedge clk) 4'h3; + @(result[0]); + if ($simtime != 130 || result[0] !== 4'h1) begin + $display("Failed first @ at %0t, expected 4'h1, got %h", + $simtime, result[0]); + pass = 1'b0; + end + @(result[0]); + if ($simtime != 150 || result[0] !== 4'h2) begin + $display("Failed second @ at %0t, expected 4'h2, got %h", + $simtime, result[0]); + pass = 1'b0; + end + @(result[0]); + if ($simtime != 170 || result[0] !== 4'h3) begin + $display("Failed third @ at %0t, expected 4'h3, got %h", + $simtime, result[0]); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/nb_ec_array_pv.v b/ivtest/ivltests/nb_ec_array_pv.v new file mode 100644 index 000000000..ad0b5ab8c --- /dev/null +++ b/ivtest/ivltests/nb_ec_array_pv.v @@ -0,0 +1,84 @@ +module top; + reg pass = 1'b1; + + integer count; + reg [2:0] icount; + reg clk = 0; + reg [3:0] in = 4'h0; + reg [7:0] result [1:0]; + + always #10 clk = ~clk; + always #20 in = in + 4'h1; + + initial begin + count = 3; + result[0][3:0] <= repeat(count) @(posedge clk) in; + if ($simtime != 0 || result[0] !== 8'bx) begin + $display("Failed repeat(3) blocked at %0t, expected 8'hxx, got %h", + $simtime, result[0]); + pass = 1'b0; + end + @(result[0]); + if ($simtime != 50 || result[0] !== 8'hx0) begin + $display("Failed repeat(3) at %0t, expected 8'hx0, got %h", + $simtime, result[0]); + pass = 1'b0; + end + + #15; + count = 0; + result[0][7:4] <= repeat(count) @(posedge clk) in; + @(result[0]); // Reals happen faster so they can use an #0, vectors are slower. + if ($simtime != 65 || result[0] !== 8'h30) begin + $display("Failed repeat(0) at %0t, expected 8'h30, got %h", + $simtime, result[0]); + pass = 1'b0; + end + + #20; + count = -1; + result[0][8:5] <= repeat(count) @(posedge clk) in; + @(result[0]); // Reals happen faster so they can use an #0, vectors are slower. + if ($simtime != 85 || result[0] !== 8'h90) begin + $display("Failed repeat(-1) at %0t, expected 8'h80, got %h", + $simtime, result[0]); + pass = 1'b0; + end + + #20; + result[0][7:4] <= @(posedge clk) 4'h0; + result[0][7:4] <= @(posedge clk) in; // This one sets the final value. + @(result[0]); + if ($simtime != 110 || result[0] !== 8'h50) begin + $display("Failed @ at %0t, expected 8'h50, got %h", + $simtime, result[0]); + pass = 1'b0; + end + + icount = 3'd2; + result[0][3:0] <= @(posedge clk) 4'h1; + result[0][7:4] <= repeat(icount) @(posedge clk) 4'h2; + result[0][1:-2] <= repeat(3) @(posedge clk) 4'h3; + @(result[0]); + if ($simtime != 130 || result[0] !== 8'h51) begin + $display("Failed first @ at %0t, expected 8'h51, got %h", + $simtime, result[0]); + pass = 1'b0; + end + @(result[0]); + if ($simtime != 150 || result[0] !== 8'h21) begin + $display("Failed second @ at %0t, expected 8'h21, got %h", + $simtime, result[0]); + pass = 1'b0; + end + @(result[0]); + if ($simtime != 170 || result[0] !== 8'h20) begin + $display("Failed third @ at %0t, expected 8'h20, got %h", + $simtime, result[0]); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/nb_ec_pv.v b/ivtest/ivltests/nb_ec_pv.v new file mode 100644 index 000000000..4d65f5fc0 --- /dev/null +++ b/ivtest/ivltests/nb_ec_pv.v @@ -0,0 +1,84 @@ +module top; + reg pass = 1'b1; + + integer count; + reg [2:0] icount; + reg clk = 0; + reg [3:0] in = 4'h0; + reg [7:0] result; + + always #10 clk = ~clk; + always #20 in = in + 4'h1; + + initial begin + count = 3; + result[3:0] <= repeat(count) @(posedge clk) in; + if ($simtime != 0 || result !== 8'bx) begin + $display("Failed repeat(3) blocked at %0t, expected 8'hxx, got %h", + $simtime, result); + pass = 1'b0; + end + @(result); + if ($simtime != 50 || result !== 8'hx0) begin + $display("Failed repeat(3) at %0t, expected 8'hx0, got %h", + $simtime, result); + pass = 1'b0; + end + + #15; + count = 0; + result[7:4] <= repeat(count) @(posedge clk) in; + @(result); // Reals happen faster so they can use an #0, vectors are slower. + if ($simtime != 65 || result !== 8'h30) begin + $display("Failed repeat(0) at %0t, expected 8'h30, got %h", + $simtime, result); + pass = 1'b0; + end + + #20; + count = -1; + result[8:5] <= repeat(count) @(posedge clk) in; + @(result); // Reals happen faster so they can use an #0, vectors are slower. + if ($simtime != 85 || result !== 8'h90) begin + $display("Failed repeat(-1) at %0t, expected 8'h80, got %h", + $simtime, result); + pass = 1'b0; + end + + #20; + result[7:4] <= @(posedge clk) 4'h0; + result[7:4] <= @(posedge clk) in; // This one sets the final value. + @(result); + if ($simtime != 110 || result !== 8'h50) begin + $display("Failed @ at %0t, expected 8'h50, got %h", + $simtime, result); + pass = 1'b0; + end + + icount = 3'd2; + result[3:0] <= @(posedge clk) 4'h1; + result[7:4] <= repeat(icount) @(posedge clk) 4'h2; + result[1:-2] <= repeat(3) @(posedge clk) 4'h3; + @(result); + if ($simtime != 130 || result !== 8'h51) begin + $display("Failed first @ at %0t, expected 8'h51, got %h", + $simtime, result); + pass = 1'b0; + end + @(result); + if ($simtime != 150 || result !== 8'h21) begin + $display("Failed second @ at %0t, expected 8'h21, got %h", + $simtime, result); + pass = 1'b0; + end + @(result); + if ($simtime != 170 || result !== 8'h20) begin + $display("Failed third @ at %0t, expected 8'h20, got %h", + $simtime, result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/nb_ec_pv2.v b/ivtest/ivltests/nb_ec_pv2.v new file mode 100644 index 000000000..80260b4a7 --- /dev/null +++ b/ivtest/ivltests/nb_ec_pv2.v @@ -0,0 +1,41 @@ +`begin_keywords "1364-2005" +module top; + reg pass = 1'b1; + + reg clk = 0; + reg [7:0] result; + reg [3:0] bit; + + always #10 clk = ~clk; + + initial begin + // Since the bit is not defined this assignment will not happen. + // We will check to verify this fact 1 time step after it should + // happen (50). + result[bit] <= repeat(3) @(posedge clk) 1'b0; + if ($simtime != 0 || result !== 8'bx) begin + $display("Failed repeat(3) blocked at %0t, expected 8'hxx, got %h", + $simtime, result); + pass = 1'b0; + end + #51; + if (result !== 8'hxx) begin + $display("Failed repeat(3) at %0t, expected 8'hxx, got %h", + $simtime, result); + pass = 1'b0; + end + + bit = 0; + result[bit] <= @(posedge clk) 4'h0; + @(result) + if ($simtime != 70 || result !== 8'bxxxxxxx0) begin + $display("Failed repeat(3) at %0t, expected 8'bxxxxxxx0, got %h", + $simtime, result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + $finish; + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/nb_ec_real.v b/ivtest/ivltests/nb_ec_real.v new file mode 100644 index 000000000..2ceba1a21 --- /dev/null +++ b/ivtest/ivltests/nb_ec_real.v @@ -0,0 +1,84 @@ +module top; + reg pass = 1'b1; + + integer count; + reg [2:0] icount; + reg clk = 0; + real in = 0.0; + real result = -1.0; + + always #10 clk = ~clk; + always #20 in = in + 1.0; + + initial begin + count = 3; + result <= repeat(count) @(posedge clk) in; + if ($simtime != 0 || result != -1.0) begin + $display("Failed repeat(3) blocked at %0t, expected -1.0, got %f", + $simtime, result); + pass = 1'b0; + end + @(result); + if ($simtime != 50 || result != 0.0) begin + $display("Failed repeat(3) at %0t, expected 0.0, got %f", + $simtime, result); + pass = 1'b0; + end + + #15; + count = 0; + result <= repeat(count) @(posedge clk) in; + #0; // This may not work since there is no delay. + if ($simtime != 65 || result != 3.0) begin + $display("Failed repeat(0) at %0t, expected 3.0, got %f", + $simtime, result); + pass = 1'b0; + end + + #20; + count = -1; + result <= repeat(count) @(posedge clk) in; + #0; // This may not work since there is no delay. + if ($simtime != 85 || result != 4.0) begin + $display("Failed repeat(-1) at %0t, expected 4.0, got %f", + $simtime, result); + pass = 1'b0; + end + + #20; + result <= @(posedge clk) 0.0; + result <= @(posedge clk) in; // This one sets the final value. + @(result); + if ($simtime != 110 || result != 5.0) begin + $display("Failed @ at %0t, expected 5.0, got %f", + $simtime, result); + pass = 1'b0; + end + + icount = 3'd2; + result <= @(posedge clk) 1.0; + result <= repeat(icount) @(posedge clk) 2.0; + result <= repeat(3) @(posedge clk) 3.0; + @(result); + if ($simtime != 130 || result != 1.0) begin + $display("Failed first @ at %0t, expected 1.0, got %f", + $simtime, result); + pass = 1'b0; + end + @(result); + if ($simtime != 150 || result != 2.0) begin + $display("Failed second @ at %0t, expected 2.0, got %f", + $simtime, result); + pass = 1'b0; + end + @(result); + if ($simtime != 170 || result != 3.0) begin + $display("Failed third @ at %0t, expected 3.0, got %f", + $simtime, result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/nb_ec_vector.v b/ivtest/ivltests/nb_ec_vector.v new file mode 100644 index 000000000..0c6238a37 --- /dev/null +++ b/ivtest/ivltests/nb_ec_vector.v @@ -0,0 +1,84 @@ +module top; + reg pass = 1'b1; + + integer count; + reg [2:0] icount; + reg clk = 0; + reg [3:0] in = 4'h0; + reg [3:0] result; + + always #10 clk = ~clk; + always #20 in = in + 4'h1; + + initial begin + count = 3; + result <= repeat(count) @(posedge clk) in; + if ($simtime != 0 || result !== 4'bx) begin + $display("Failed repeat(3) blocked at %0t, expected 4'hx, got %h", + $simtime, result); + pass = 1'b0; + end + @(result); + if ($simtime != 50 || result !== 4'h0) begin + $display("Failed repeat(3) at %0t, expected 4'h0, got %h", + $simtime, result); + pass = 1'b0; + end + + #15; + count = 0; + result <= repeat(count) @(posedge clk) in; + @(result); // Reals happen faster so they can use an #0, vectors are slower. + if ($simtime != 65 || result !== 4'h3) begin + $display("Failed repeat(0) at %0t, expected 4'h3, got %h", + $simtime, result); + pass = 1'b0; + end + + #20; + count = -1; + result <= repeat(count) @(posedge clk) in; + @(result); // Reals happen faster so they can use an #0, vectors are slower. + if ($simtime != 85 || result !== 4'h4) begin + $display("Failed repeat(-1) at %0t, expected 4'h4, got %h", + $simtime, result); + pass = 1'b0; + end + + #20; + result <= @(posedge clk) 4'h0; + result <= @(posedge clk) in; // This one sets the final value. + @(result); + if ($simtime != 110 || result !== 4'h5) begin + $display("Failed @ at %0t, expected 4'h5, got %h", + $simtime, result); + pass = 1'b0; + end + + icount = 3'd2; + result <= @(posedge clk) 4'h1; + result <= repeat(icount) @(posedge clk) 4'h2; + result <= repeat(3) @(posedge clk) 4'h3; + @(result); + if ($simtime != 130 || result !== 4'h1) begin + $display("Failed first @ at %0t, expected 4'h1, got %h", + $simtime, result); + pass = 1'b0; + end + @(result); + if ($simtime != 150 || result !== 4'h2) begin + $display("Failed second @ at %0t, expected 4'h2, got %h", + $simtime, result); + pass = 1'b0; + end + @(result); + if ($simtime != 170 || result !== 4'h3) begin + $display("Failed third @ at %0t, expected 4'h3, got %h", + $simtime, result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/nblkorder.v b/ivtest/ivltests/nblkorder.v new file mode 100644 index 000000000..25ef9d61e --- /dev/null +++ b/ivtest/ivltests/nblkorder.v @@ -0,0 +1,64 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validates Non-blocking order determinism IEEE1364-Draft, page 5-3, +// SDW - section 5.4.1. + +module main (); + +reg x,clock; +reg inval; +reg error; + +always @(posedge clock) + begin + x <= ~inval; + x <= inval; + end + +initial + begin + clock = 0; + error = 0; + #1; + inval = 0; + #5 ; + clock = 1; + #1 ; + if(x !== inval) + begin + $display("FAILED - parallel non-blocking assign s/b 0, is %b",x); + error = 1; + end + #6 + clock = 0; + #1 ; + inval = 1; + #5 ; + clock = 1; + #1 ; + if(x !== inval) + begin + $display("FAILED - parallel non-blocking assign s/b 1, is %b",x); + error = 1; + end + #1 ; + if(error == 0) + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/nblkpush.v b/ivtest/ivltests/nblkpush.v new file mode 100644 index 000000000..6f9617700 --- /dev/null +++ b/ivtest/ivltests/nblkpush.v @@ -0,0 +1,59 @@ +// +// Copyright (c) 2001 Stephan Boettcher +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// Validates Non-blocking assignment propagation +// $Id: nblkpush.v,v 1.2 2005/07/07 16:25:20 stevewilliams Exp $ + +// Update: This test has a race in it that makes it not valid. The +// assumption that a blocking assign will push through the continuous +// assignment before the thread doing the assign is allowed to advance +// is not valid. This test only passes Verilog XL. Every other tool, +// commercial or otherwise, seems to FAIL this test. Therefore, this +// test should not be relied on. + +module test; + + reg a, b, c, d; + + wire ab = a & b; + wire abc = ab | c; + wire abcd = abc & d; + + initial + begin + a = 0; + b = 1; + c = 0; + d = 1; + #1; + a = 1; + if (abcd === 1) + begin + $display("PASSED"); + $finish; + end + + $display("FAILED ab=%b, abc=%b, abcd=%b", ab, abc, abcd); + #1; + if (abcd === 1) + $display("abcd value changed late"); + else + $display("abcd value still wrong"); + end + +endmodule diff --git a/ivtest/ivltests/negative_genvar.v b/ivtest/ivltests/negative_genvar.v new file mode 100644 index 000000000..60a8b4206 --- /dev/null +++ b/ivtest/ivltests/negative_genvar.v @@ -0,0 +1,28 @@ +module negative_genvar; + +wire signed [3:0] value[-7:7]; + +genvar i; + +for (i = 7; i >= -7; i = i - 1) begin:genloop + assign value[i] = i; +end + +integer j; + +reg fail = 0; + +initial begin + #0; + for (j = -7; j <= 7; j = j + 1) begin + $display("%d", value[j]); + if (value[j] !== j) fail = 1; + end + + if (fail) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/negvalue.v b/ivtest/ivltests/negvalue.v new file mode 100644 index 000000000..c805445ee --- /dev/null +++ b/ivtest/ivltests/negvalue.v @@ -0,0 +1,15 @@ +module negvalue; + + reg[7:0]reg1; + + initial begin + reg1 <= -13 +21 ; + #1 + reg1 <= 0 -13 +21 ; + end + + always@(reg1)begin + $display("%d (should be 8)",reg1); + end + +endmodule diff --git a/ivtest/ivltests/neq1.v b/ivtest/ivltests/neq1.v new file mode 100644 index 000000000..a917bd418 --- /dev/null +++ b/ivtest/ivltests/neq1.v @@ -0,0 +1,28 @@ +module main; + +reg [2:0] a; + +wire e0 = a==3'h0; wire n0 = a!=3'h0; +wire e1 = a==3'h1; wire n1 = a!=3'h1; +wire e2 = a==3'h2; wire n2 = a!=3'h2; +wire e3 = a==3'h3; wire n3 = a!=3'h3; +wire e4 = a==3'h4; wire n4 = a!=3'h4; +wire e5 = a==3'h5; wire n5 = a!=3'h5; +wire e6 = a==3'h6; wire n6 = a!=3'h6; +wire e7 = a==3'h7; wire n7 = a!=3'h7; +initial begin + for (a=0; a<7; a=a+1) begin + #1; + $display("a=",a); + $display(" 0 %d %d", e0, n0); + $display(" 1 %d %d", e1, n1); + $display(" 2 %d %d", e2, n2); + $display(" 3 %d %d", e3, n3); + $display(" 4 %d %d", e4, n4); + $display(" 5 %d %d", e5, n5); + $display(" 6 %d %d", e6, n6); + $display(" 7 %d %d", e7, n7); + end +end + +endmodule diff --git a/ivtest/ivltests/nested_func.v b/ivtest/ivltests/nested_func.v new file mode 100644 index 000000000..b0b69103b --- /dev/null +++ b/ivtest/ivltests/nested_func.v @@ -0,0 +1,27 @@ +module nested_func(); + +function automatic real sum; + +input real a; +input real b; + +begin + sum = a + b; +end + +endfunction + +real r1; +real r2; +real r3; + +initial begin + r1 = sum(sum(2, 3), sum(4, 5)); + r2 = sum(3, sum(4, sum(5, 6))); + r3 = sum(sum(sum(4, 5), 6), 7); + $display("sum of 2 to 5 = %0d", r1); + $display("sum of 3 to 6 = %0d", r2); + $display("sum of 4 to 7 = %0d", r3); +end + +endmodule diff --git a/ivtest/ivltests/nested_impl_event1.v b/ivtest/ivltests/nested_impl_event1.v new file mode 100644 index 000000000..2fbd7ef97 --- /dev/null +++ b/ivtest/ivltests/nested_impl_event1.v @@ -0,0 +1,24 @@ +module test(); + +reg a, b, c; + +always @* begin // always @(b or c) + a = b; + $display("Triggered 1 at %0t", $time); + + @* a = c; // @(c) + $display("Triggered 2 at %0t", $time); +end + +initial begin + #10 a = 0; + #10 a = 1; + #10 b = 0; + #10 b = 1; + #10 c = 0; + #10 c = 1; + #10 c = 0; + #10 $finish(0); +end + +endmodule diff --git a/ivtest/ivltests/nested_impl_event2.v b/ivtest/ivltests/nested_impl_event2.v new file mode 100644 index 000000000..d197c43a8 --- /dev/null +++ b/ivtest/ivltests/nested_impl_event2.v @@ -0,0 +1,21 @@ +module test(); + +reg a, b; + +always @* begin // always @(b) + a = b; + $display("Triggered 1 at %0t", $time); + + @*; + $display("Triggered 2 at %0t", $time); +end + +initial begin + #10 a = 0; + #10 a = 1; + #10 b = 0; + #10 b = 1; + #10 $finish(0); +end + +endmodule diff --git a/ivtest/ivltests/no_if_statement.v b/ivtest/ivltests/no_if_statement.v new file mode 100644 index 000000000..f59e46384 --- /dev/null +++ b/ivtest/ivltests/no_if_statement.v @@ -0,0 +1,5 @@ +module top; + reg var; + + always if (var); +endmodule diff --git a/ivtest/ivltests/no_timescale_in_module.v b/ivtest/ivltests/no_timescale_in_module.v new file mode 100644 index 000000000..cad86c447 --- /dev/null +++ b/ivtest/ivltests/no_timescale_in_module.v @@ -0,0 +1,4 @@ +`timescale 1ns/1ps +module top; +`timescale 1us/1ns +endmodule diff --git a/ivtest/ivltests/non-polymorphic-abs.v b/ivtest/ivltests/non-polymorphic-abs.v new file mode 100644 index 000000000..714c0e5b6 --- /dev/null +++ b/ivtest/ivltests/non-polymorphic-abs.v @@ -0,0 +1,17 @@ +// $abs should take a real argument and return a real result. +module test(); + +localparam s = 0; +localparam a = 1.5; +localparam b = 1; +localparam r = $abs((s ? a : b) / 2); + +initial begin + $display("%g", r); + if (r == 0.5) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/not_a_latch1.v b/ivtest/ivltests/not_a_latch1.v new file mode 100644 index 000000000..3e6b8d4fd --- /dev/null +++ b/ivtest/ivltests/not_a_latch1.v @@ -0,0 +1,60 @@ + +module test(input wire load, in, + output reg out1, out2); + + (* ivl_combinational *) + always @* begin + out1 = 0; + if (load) begin + out1 = in; + out2 = in; + end else begin + out2 = ~in; + end + end + +endmodule // test + +module test_bench; + + reg load; + reg val; + wire out1, out2; + + test DUT(.load(load), .in(val), .out1(out1), .out2(out2)); + + (* ivl_synthesis_off *) + initial begin + val = 0; + load = 1; + #1 ; + if (out1 !== 0 || out2 !== 0) begin + $display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2); + $finish; + end + + val = 1; + #1 ; + if (out1 !== 1 || out2 !== 1) begin + $display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2); + $finish; + end + + load = 0; + #1 ; + if (out1 !== 0 || out2 !== 0) begin + $display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2); + $finish; + end + + val = 0; + #1 ; + if (out1 !== 0 || out2 !== 1) begin + $display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // test_bench diff --git a/ivtest/ivltests/not_a_latch2.v b/ivtest/ivltests/not_a_latch2.v new file mode 100644 index 000000000..491c0bfa8 --- /dev/null +++ b/ivtest/ivltests/not_a_latch2.v @@ -0,0 +1,75 @@ + +module test(input wire load, drain, + input wire clk, data, + output reg foo_nxt, bar_nxt); + + reg foo, bar; + + (* ivl_combinational *) + always @* begin + foo_nxt = foo; + bar_nxt = bar; + + if (load) begin + foo_nxt = data; + bar_nxt = 1; + end else if (drain) begin + bar_nxt = 0; + end + end + + always @(posedge clk) begin + foo <= foo_nxt; + bar <= bar_nxt; + end + +endmodule // test + +module main; + + reg clk, load, drain, data; + wire foo, bar; + + test dut (.clk(clk), .load(load), .drain(drain), .data(data), + .foo_nxt(foo), .bar_nxt(bar)); + + (* ivl_synthesis_off *) + initial begin + clk = 0; + load = 1; + drain = 0; + data = 1; + #1 clk = 1; + #1 clk = 0; + $display("%0t: load=%b, drain=%b, data=%b: foo=%b, bar=%b", + $time, load, drain, data, foo, bar); + if (foo !== 1 || bar !== 1) begin + $display("FAILED -- foo=%b, bar=%b (1)", foo, bar); + $finish; + end + data = 0; + #1 clk = 1; + #1 clk = 0; + $display("%0t: load=%b, drain=%b, data=%b: foo=%b, bar=%b", + $time, load, drain, data, foo, bar); + if (foo !== 0 || bar !== 1) begin + $display("FAILED -- foo=%b, bar=%b (2)", foo, bar); + $finish; + end + load = 0; + drain = 1; + #1 ; + if (foo !== 0 || bar !== 0) begin + $display("FAILED -- foo=%b, bar=%b (3)", foo, bar); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + $display("%0t: load=%b, drain=%b, data=%b: foo=%b, bar=%b", + $time, load, drain, data, foo, bar); + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/npmos.v b/ivtest/ivltests/npmos.v new file mode 100644 index 000000000..89d41c4d4 --- /dev/null +++ b/ivtest/ivltests/npmos.v @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + wire no, po; + reg d, c; + + nmos n (no, d, c); + pmos p (po, d, c); + + initial begin + c = 0; + d = 0; + + #1 if (no !== 1'bz) begin + $display("FAILED -- n (%b, %b, %b)", no, d, c); + $finish; + end + + if (po !== 1'b0) begin + $display("FAILED -- p (%b, %b, %b)", po, d, c); + $finish; + end + + d = 1; + + #1 if (no !== 1'bz) begin + $display("FAILED -- n (%b, %b, %b)", no, d, c); + $finish; + end + + if (po !== 1'b1) begin + $display("FAILED -- p (%b, %b, %b)", po, d, c); + $finish; + end + + c = 1; + + #1 if (no !== 1'b1) begin + $display("FAILED -- n (%b, %b, %b)", no, d, c); + $finish; + end + + if (po !== 1'bz) begin + $display("FAILED -- p (%b, %b, %b)", po, d, c); + $finish; + end + + d = 0; + + #1 if (no !== 1'b0) begin + $display("FAILED -- n (%b, %b, %b)", no, d, c); + $finish; + end + + if (po !== 1'bz) begin + $display("FAILED -- p (%b, %b, %b)", po, d, c); + $finish; + end + + $display("PASSED"); + + end + +endmodule // main diff --git a/ivtest/ivltests/npmos2.v b/ivtest/ivltests/npmos2.v new file mode 100644 index 000000000..62d3e5158 --- /dev/null +++ b/ivtest/ivltests/npmos2.v @@ -0,0 +1,91 @@ +// Copyright (c) 2001 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + + +/* + * This module implements what essentially amounts to an array of DFF + * devices with output enable. This test checks the operation of the + * pmos and nmos devices. + */ +module grayGap (ad, clk, read, write); + + output [31:0] ad; + input clk, read, write; + + reg [15:0] regff; + + pmos ad_drv [31:0] (ad, {16'b0, regff}, read); + + always @(posedge clk) + if (write) regff = ad[15:0]; + + +endmodule + + +module main; + + wire [31:0] ad; + reg clk, read, write; + + reg [31:0] ad_val; + reg ad_en; + + nmos ad_drv[31:0] (ad, ad_val, ad_en); + + grayGap test (ad, clk, read, write); + + always #10 clk = ~clk; + + initial begin + clk = 1; + read = 1; + write = 0; + $monitor($time, "ad=%b", ad); + + // Set up to write a value into the grayGap register. + @(negedge clk) + ad_val = 32'haaaa_aaaa; + read = 1; + write = 1; + ad_en = 1; + + // The posedge has passed, now set up to read that value + // out. Turn all the drivers off for a moment, to see that the + // line becomes tri-state... + @(negedge clk) + ad_en = 0; + write = 0; + + // Now read the value. + #1 read = 0; + + #1 $display("Wrote %h, got %h", ad_val, ad); + + if (ad !== 32'b0000_0000_0000_0000_1010_1010_1010_1010) begin + $display("FAILED -- ad is %b", ad); + $finish; + end + + #2 read = 1; + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/p_monta.v b/ivtest/ivltests/p_monta.v new file mode 100644 index 000000000..6476ec0e8 --- /dev/null +++ b/ivtest/ivltests/p_monta.v @@ -0,0 +1,39 @@ +// From: Peter Monta +// Subject: verilog: vvp bug, function or concat related? +// Message-Id: <20010726071414.1CEF41C5@www.pmonta.com> +// Date: Thu, 26 Jul 2001 00:14:14 -0700 (PDT) + +module main(); + +function [7:0] f; + input [7:0] r; + f = { + r[0]^r[1]^r[2]^r[3]^r[7], + r[3]^r[6]^r[7], + r[2]^r[5]^r[6], + r[1]^r[4]^r[5]^r[7], + r[0]^r[3]^r[4]^r[6]^r[7], + r[0]^r[1]^r[5]^r[6], + r[1]^r[2]^r[3]^r[4]^r[5], + r[0]^r[1]^r[2]^r[3]^r[4] }; +endfunction + + reg [7:0] data_in; + reg [7:0] r; + reg start_in; + + initial begin + data_in = 8'h23; + r = 0; + start_in = 0; + #2; + r <= #1 start_in ? 0 : f(data_in); + #2; + $display("%b",r); + if (r === 8'b00101100) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/packed_dims_invalid_class.v b/ivtest/ivltests/packed_dims_invalid_class.v new file mode 100644 index 000000000..6a91d515e --- /dev/null +++ b/ivtest/ivltests/packed_dims_invalid_class.v @@ -0,0 +1,28 @@ +// Invalid packed dimensions +// This should generate a error message and not crash during elaboration + +typedef logic [] T1; +typedef logic [0] T2; +typedef logic [-1] T3; +typedef logic [$] T4; + +class C; + logic [$] a; + T1 b; + T1 [$] c; + + logic [0] d; + T2 e; + T2 [0] f; + + logic [-1] g; + T3 h; + T3 [-1] i; + + logic [$] j; + T4 k; + T4 [$] l; +endclass + +module test; +endmodule diff --git a/ivtest/ivltests/packed_dims_invalid_module.v b/ivtest/ivltests/packed_dims_invalid_module.v new file mode 100644 index 000000000..55735aaa5 --- /dev/null +++ b/ivtest/ivltests/packed_dims_invalid_module.v @@ -0,0 +1,30 @@ +// Invalid packed dimensions +// This should generate a error message and not crash during elaboration + +typedef logic [] T1; +typedef logic [0] T2; +typedef logic [-1] T3; +typedef logic [$] T4; + +module test ( + input [] port_a, + input [0] port_b, + output [-1] port_c, + output [$] port_d +); + logic [$] a; + T1 b; + T1 [$] c; + + logic [0] d; + T2 e; + T2 [0] f; + + logic [-1] g; + T3 h; + T3 [-1] i; + + logic [$] j; + T4 k; + T4 [$] l; +endmodule diff --git a/ivtest/ivltests/packeda.v b/ivtest/ivltests/packeda.v new file mode 100644 index 000000000..ebfeb3719 --- /dev/null +++ b/ivtest/ivltests/packeda.v @@ -0,0 +1,95 @@ +module top; + + // packed 2D array, arranged as 4 bytes of 8 bits each. + logic [3:0][7:0] word32; + int idx; + int x; + + // Show a slice select in a continuous assignment + wire [7:0] word1 = word32[1]; + + initial begin + // Const slice select in l-values. + word32[0] = 'h00; + word32[1] = 'h11; + word32[2] = 'h22; + word32[3] = 'h33; + + if (word32 !== 'h33_22_11_00) begin + $display("FAILED -- word32 = %h (1)", word32); + $finish; + end + + #1 if (word1 !== 8'h11) begin + $display("FAILED -- word1 = %h", word1); + $finish; + end + + // Non-constant slice indices, l-value and r-value. + for (idx = 0 ; idx < 4 ; idx = idx+1) + word32[idx] = ~word32[idx]; + + if (word32 !== ~ 'h33_22_11_00) begin + $display("FAILED -- word32 = %h (2)", word32); + $finish; + end + + word32[0][3:0] = 'h0; + word32[1][3:0] = 'h1; + word32[2][3:0] = 'h2; + word32[3][3:0] = 'h3; + + word32[0][7:4] = 'h3; + word32[1][7:4] = 'h2; + word32[2][4 +: 4] = 'h1; + word32[3][4 +: 4] = 'h0; + + if (word32 !== 'h03_12_21_30) begin + $display("FAILED -- word32 = %h (3)", word32); + $finish; + end + + if (word32[1][7:4] !== word32[1][4 +: 4]) begin + $display("FAILED -- word32[1][7:4]=%h, word32[1][4 +: 4]=%h", + word32[1][7:4],word32[1][4 +: 4]); + $finish; + end + + x = 4; + word32[1][x +: 4] = 'h2; + if (word32[1][7:4] !== word32[1][x +: 4]) begin + $display("FAILED -- word32[1][7:4]=%h, word32[1][4 +: 4]=%h", + word32[1][7:4],word32[1][x +: 4]); + $finish; + end + + for (idx = 0 ; idx < 8 ; idx = idx+1) begin + word32[0][idx] = idx[0]; + word32[2][idx] = idx[0]; + word32[1][idx] = ~idx[0]; + word32[3][idx] = ~idx[0]; + end + + if (word32 !== 'h55_aa_55_aa) begin + $display("FAILED -- word32 = %h (4)", word32); + $finish; + end + + for (idx = 0 ; idx < 8 ; idx = idx+1) begin + if (word32[0][idx] !== word32[2][idx]) begin + $display("FAILED -- word32[0][%0d]=%b, word32[2][%0d]=%b", + idx, word32[0][idx], idx, word32[2][idx]); + $finish; + end + if (word32[1][idx] !== word32[3][idx]) begin + $display("FAILED -- word32[1][%0d]=%b, word32[3][%0d]=%b", + idx, word32[1][idx], idx, word32[3][idx]); + $display("FAILED"); + $finish; + end + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/packeda2.v b/ivtest/ivltests/packeda2.v new file mode 100644 index 000000000..7d8761468 --- /dev/null +++ b/ivtest/ivltests/packeda2.v @@ -0,0 +1,32 @@ +module main; + + wire logic [3:0][7:0] foo; + + genvar idx; + for (idx = 0 ; idx <= 3 ; idx = idx+1) begin: test + test dut (.sum(foo[idx]), .a(idx)); + end + + logic [7:0] tmp; + initial begin + #0; // avoid time-zero race + for (tmp = 0 ; tmp <= 3 ; tmp = tmp+1) begin + //if ($bits(foo[tmp]) !== 8) begin + // $display("FAILED -- $bits = %d", $bits(foo[tmp])); + // $finish; + //end + if (foo[tmp] !== (tmp+8'd5)) begin + $display("FAILED -- foo[%d] = %b", tmp, foo[tmp]); + $finish; + end + end + $display("PASSED"); + end + +endmodule // main + +module test (output logic[7:0] sum, input logic [7:0]a); + + assign sum = a + 8'd5; + +endmodule // test diff --git a/ivtest/ivltests/par_mismatch.v b/ivtest/ivltests/par_mismatch.v new file mode 100644 index 000000000..4c8726566 --- /dev/null +++ b/ivtest/ivltests/par_mismatch.v @@ -0,0 +1,23 @@ +module top; + reg in; + wire [7:0] out; + + lwr dut(out, in); + + initial begin + $display("FAILED"); + end +endmodule + +module lwr(out, in); + output [7:0] out; + input in; + + assign out = {8{in}}; + + specify + // It is an error to use a parallel connection here since the input + // and output (source/destination) do not have the same width. + (in => out) = 2; + endspecify +endmodule diff --git a/ivtest/ivltests/param-extend.v b/ivtest/ivltests/param-extend.v new file mode 100644 index 000000000..ab754aac8 --- /dev/null +++ b/ivtest/ivltests/param-extend.v @@ -0,0 +1,37 @@ +module top(); + +localparam signed [31:0] SizedValue = -1; +localparam UnsizedValue = -1; + +reg [35:0] Result; +reg Failed; + +initial begin + Failed = 0; + // check for sign extension + Result = SizedValue; + $display("%h", Result); + if (Result !== 36'hfffffffff) Failed = 1; + Result = UnsizedValue; + $display("%h", Result); + if (Result !== 36'hfffffffff) Failed = 1; + + // check for zero extension + Result = 'd0 + SizedValue; + $display("%h", Result); + if (Result !== 36'h0ffffffff) Failed = 1; + Result = 'd0 + UnsizedValue; + $display("%h", Result); +`ifdef OLD_UNSIZED + if (Result !== 36'hfffffffff) Failed = 1; +`else + if (Result !== 36'h0ffffffff) Failed = 1; +`endif + + if (Failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/param-width.v b/ivtest/ivltests/param-width.v new file mode 100644 index 000000000..812d4a7c7 --- /dev/null +++ b/ivtest/ivltests/param-width.v @@ -0,0 +1,23 @@ +module param_width(); + +parameter a = 3'd4; +parameter b = 3'd5; +parameter c = 3'd4; +parameter d = 3'd5; + +parameter [3:0] sum1 = a + b; +parameter sum2 = a + b; +parameter [3:0] sum3 = c + d; +parameter sum4 = c + d; + +defparam c = 2'd2; +defparam d = 2'd3; + +initial begin + $display("%b", sum1); + $display("%b", sum2); + $display("%b", sum3); + $display("%b", sum4); +end + +endmodule diff --git a/ivtest/ivltests/param_add.v b/ivtest/ivltests/param_add.v new file mode 100644 index 000000000..2cd9945eb --- /dev/null +++ b/ivtest/ivltests/param_add.v @@ -0,0 +1,35 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * SDW: Verify addition in a param declaration + */ +module test; + +parameter A0 = 4'b0011 + 4'b0001 ; + +initial + begin + if(A0 !== 4'b0100) + $display("FAILED - Addition in a param declaration."); + else + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/param_and.v b/ivtest/ivltests/param_and.v new file mode 100644 index 000000000..d2b3fdd58 --- /dev/null +++ b/ivtest/ivltests/param_and.v @@ -0,0 +1,35 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * SDW: This test is a first expression test inside a parameter declaration. + */ +module test; + +parameter A0 = 2'b10 & 2'b11 ; + +initial + begin + if(A0 !== 2'b10) + $display("FAILED - A0 expression AND doesn't work."); + else + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/param_and2.v b/ivtest/ivltests/param_and2.v new file mode 100644 index 000000000..3e389b579 --- /dev/null +++ b/ivtest/ivltests/param_and2.v @@ -0,0 +1,35 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * SDW: Verify expression using logical and in a parameter declaration + */ +module test; + +parameter A0 = 2'b10 && 2'b01 ; + +initial + begin + if(A0 !== 1'b1) + $display("FAILED - A0 expression && doesn't work."); + else + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/param_band.v b/ivtest/ivltests/param_band.v new file mode 100644 index 000000000..1fd5ec1bc --- /dev/null +++ b/ivtest/ivltests/param_band.v @@ -0,0 +1,35 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * SDW: Verify expression using bit-wise and in a parameter declaration + */ +module test; + +parameter A0 = & 4'b1111; + +initial + begin + if(A0 !== 1'b1) + $display("FAILED - bit-wise and in an expression ."); + else + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/param_binv.v b/ivtest/ivltests/param_binv.v new file mode 100644 index 000000000..b4585ffa4 --- /dev/null +++ b/ivtest/ivltests/param_binv.v @@ -0,0 +1,35 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * SDW: Verify bit vector inversion in a param declaration + */ +module test; + +parameter A0 = ~(4'b1010); + +initial + begin + if(A0 !== 4'b0101) + $display("FAILED - Bit vector inversion in a param declaration."); + else + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/param_bor.v b/ivtest/ivltests/param_bor.v new file mode 100644 index 000000000..1fd628cfd --- /dev/null +++ b/ivtest/ivltests/param_bor.v @@ -0,0 +1,35 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * SDW: Verify expression using bit-wise or in a parameter declaration + */ +module test; + +parameter A0 = | 4'b0001; + +initial + begin + if(A0 !== 1'b1) + $display("FAILED - bit-wise and in an expression ."); + else + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/param_concat.v b/ivtest/ivltests/param_concat.v new file mode 100644 index 000000000..246608acb --- /dev/null +++ b/ivtest/ivltests/param_concat.v @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2000 Peter Monta + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module main; + parameter foo = { 2'b01, 2'b10 }; + initial + if (foo==4'b0110) + $display("PASSED"); + else + $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/param_eq3.v b/ivtest/ivltests/param_eq3.v new file mode 100644 index 000000000..ede8eb3ca --- /dev/null +++ b/ivtest/ivltests/param_eq3.v @@ -0,0 +1,35 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * SDW: This verifies the bit equivalence expr in a parameter + */ +module test; + +parameter A0 = (3'b1zx === 3'b1zx); + +initial + begin + if(A0 !== 1'b1) + $display("FAILED - Expression equivalence fails in a parameter."); + else + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/param_expr.v b/ivtest/ivltests/param_expr.v new file mode 100644 index 000000000..aa82da230 --- /dev/null +++ b/ivtest/ivltests/param_expr.v @@ -0,0 +1,35 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * SDW: This test is a first expression test inside a parameter declaration. + */ +module test; + +parameter A0 = 2'b10 | 2'b01 ; + +initial + begin + if(A0 !== 2'b11) + $display("FAILED - A0 expression OR doesn't work."); + else + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/param_mod.v b/ivtest/ivltests/param_mod.v new file mode 100644 index 000000000..f3a4adfb1 --- /dev/null +++ b/ivtest/ivltests/param_mod.v @@ -0,0 +1,35 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * SDW: Verify addition in a param declaration + */ +module test; + +parameter A0 = 4'b0011 % 4'b0010 ; + +initial + begin + if(A0 !== 4'b0001) + $display("FAILED - Mod in a param declaration."); + else + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/param_select.v b/ivtest/ivltests/param_select.v new file mode 100644 index 000000000..dab95df76 --- /dev/null +++ b/ivtest/ivltests/param_select.v @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program tests the ability to take bit and part selects + * of parameters. This is actually not legal in Verilog, but + * Icarus Verilog supports it anyhow, as do many (most?) other + * Verilog compilers. + */ + +module main; + + parameter vec = 16'b0000_1001_0111_1010; + + initial begin + if (vec[0] !== 0) begin + $display("FAILED -- %b[0] !== 0", vec); + $finish; + end + + if (vec[1] !== 1) begin + $display("FAILED -- %b[1] !== 1", vec); + $finish; + end + + if (vec[3:1] !== 3'b101) begin + $display("FAILED -- %b[3:1] !== b101", vec); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/param_select2.v b/ivtest/ivltests/param_select2.v new file mode 100644 index 000000000..541a880ca --- /dev/null +++ b/ivtest/ivltests/param_select2.v @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This module checks that parameter bit select works + * in parameter assignment expressions. + */ +module main; + + parameter value = 2'b10; + parameter x = 0; + parameter y = 1; + parameter pa = value[0]; + parameter pb = value[1]; + parameter px = value[x]; + parameter py = value[y]; + + initial begin + + if (pa !== value[0]) begin + $display("FAILED -- pa == %b", pa); + $finish; + end + + if (pa !== 0) begin + $display("FAILED -- pa == %b", pa); + $finish; + end + + if (pb !== value[1]) begin + $display("FAILED -- pb == %b", pb); + $finish; + end + + if (pb !== 1) begin + $display("FAILED -- pb == %b", pb); + $finish; + end + + if (px !== value[0]) begin + $display("FAILED -- px == %b", px); + $finish; + end + + if (px !== 0) begin + $display("FAILED -- px == %b", px); + $finish; + end + + if (py !== value[1]) begin + $display("FAILED -- py == %b", py); + $finish; + end + + if (py !== 1) begin + $display("FAILED -- py == %b", py); + $finish; + end + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/param_select3.v b/ivtest/ivltests/param_select3.v new file mode 100644 index 000000000..53c9d58c0 --- /dev/null +++ b/ivtest/ivltests/param_select3.v @@ -0,0 +1,54 @@ +/* + * This program demonstrates non-constant part selects + * applied to a parameter value. + */ +module main; + + parameter foo = 32'h76543210; + + reg [3:0] tmp; + reg [3:0] idx; + + initial begin + if (foo[0 +: 4] !== 4'h0) begin + $display("FAILED -- %b !== 0", foo[0 +: 4]); + $finish; + end + + if (foo[4 +: 4] !== 4'h1) begin + $display("FAILED -- %b !== 1", foo[4 +: 4]); + $finish; + end + + if (foo[8 +: 4] !== 4'h2) begin + $display("FAILED -- %b !== 2", foo[8 +: 4]); + $finish; + end + + if (foo[12+: 4] !== 4'h3) begin + $display("FAILED -- %b !== 3", foo[12 +: 4]); + $finish; + end + + for (idx = 0 ; idx < 8 ; idx = idx + 1) begin + tmp = foo[(idx*4) +: 4]; + if (tmp !== idx) begin + $display("FAILED -- %b !== %b", idx, tmp); + $finish; + end + + end + + for (idx = 0 ; idx < 8 ; idx = idx + 1) begin + tmp = foo[(idx*4+3) -: 4]; + if (tmp !== idx) begin + $display("FAILED -- %b !== %b", idx, tmp); + $finish; + end + + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/param_string.v b/ivtest/ivltests/param_string.v new file mode 100644 index 000000000..1b7d5dec0 --- /dev/null +++ b/ivtest/ivltests/param_string.v @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + parameter passed = "PASSED"; + + initial $display(passed); + +endmodule // main diff --git a/ivtest/ivltests/param_tern.v b/ivtest/ivltests/param_tern.v new file mode 100644 index 000000000..4e7797de6 --- /dev/null +++ b/ivtest/ivltests/param_tern.v @@ -0,0 +1,66 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + parameter PARM08 = 8; + parameter PARM04 = PARM08 >> 1; + parameter PARM16 = PARM08 << 1; + + parameter PARM10 = ((PARM08 <=2) ? 1: + ((PARM08 <=4) ? 2: + ((PARM08 <=8) ? 3:4))); + + // this parameterized input compiles ok + wire [PARM04 : 0] in04; + wire [PARM16 : 0] in05; + + reg [PARM08 : 0] out00; + reg [PARM04 : 0] out04; + reg [PARM16 : 0] out05; + + // this parameterized doesn't compile, stack dump + wire [PARM10:0] in99; + + initial begin + if (PARM08 !== 8) begin + $display("FAILED -- PARM08 == %b", PARM08); + $finish; + end + + if (PARM04 !== 4) begin + $display("FAILED -- PARM04 == %b", PARM04); + $finish; + end + + if (PARM16 !== 16) begin + $display("FAILED -- PARM16 == %b", PARM16); + $finish; + end + + + if (PARM10 !== 3) begin + $display("FAILED -- PARM10 == %b", PARM10); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/param_tern2.v b/ivtest/ivltests/param_tern2.v new file mode 100644 index 000000000..b5598070f --- /dev/null +++ b/ivtest/ivltests/param_tern2.v @@ -0,0 +1,32 @@ +/* + * This example is a distillation of the essence of PR#993. + * Or at least the essence that led to a bug report. + */ + +module main; + + parameter [31:0] fifo_address = 32'hc0_00_00_00; + + reg [31:0] bar; + reg flag; + wire [31:0] foo = flag? fifo_address : bar; + + initial begin + bar = ~fifo_address; + + flag = 1; + #1 if (foo !== fifo_address) begin + $display("FAILED"); + $finish; + end + + flag = 0; + #1 if (foo !== bar) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/param_test1.v b/ivtest/ivltests/param_test1.v new file mode 100644 index 000000000..bfc47be8e --- /dev/null +++ b/ivtest/ivltests/param_test1.v @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2001 Peter Bain + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* This is based on PR#124. */ + +`timescale 1ns/1ns +module paramtest(clk, dat); + parameter dat_width = 32; + input clk; + output [dat_width-1:0] dat; + + reg [dat_width-1:0] dat; + reg [4-1:0] exp_dat; + parameter pay_init = 32'h01020304; + parameter pay_inc = 32'h01010101; + + parameter cell_size = (53 * 8); + parameter transfers = cell_size/dat_width + ((cell_size%dat_width)?1:0); + + initial begin + exp_dat = 0; + dat = 0; + end + + + initial begin + #10; + for (exp_dat = 0; exp_dat != 4'hf; exp_dat = exp_dat + 1) begin + dat <= exp_dat; + #1 + if (dat !== exp_dat) begin + $display("ERROR: dat = %h, exp_dat = %h", dat, exp_dat); + end else begin + $display("OKAY: dat = %h, exp_dat = %h", dat, exp_dat); + end + end + end +endmodule diff --git a/ivtest/ivltests/param_test2.v b/ivtest/ivltests/param_test2.v new file mode 100644 index 000000000..3e7b12b55 --- /dev/null +++ b/ivtest/ivltests/param_test2.v @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2001 Brendan J Simon + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +//**************************************************************************** +// +// MODULE : parameter_test +// +// DESCRIPTION : Test module to demonstrate parameter evaluation bug. +// +// AUTHOR : Brendan J Simon (brendan.simon@bigpond.com) +// +// DATE : Monday 5th January 2001. +// +// NOTES : It seems that Icarus Verilog 0.4 does not evaluate +// moderately complex parameter statements properly. +// +//**************************************************************************** + +module parameter_test; + + +parameter foo_size = 32 * 6; +parameter foo_lsb = 0; + +`ifdef GOOD_CODE + parameter foo_msb_temp = foo_lsb + foo_size; + parameter foo_msb = foo_msb_temp - 1; +`else + parameter foo_msb = foo_lsb + foo_size - 1; +`endif + + +// These complex statements work; +parameter temp0 = 1 + 2 + 3 + 4 + 5; +parameter temp1 = 1 + 2 + 3 + 4 + 5 - 1; + +reg [foo_msb:foo_lsb] foo; +integer i; + + +initial begin + for (i=0; i + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module m(a); +input a; +endmodule + +module n; +wire a; +m #(1,2,3) am(a); +initial $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/param_test4.v b/ivtest/ivltests/param_test4.v new file mode 100644 index 000000000..6771eeeb4 --- /dev/null +++ b/ivtest/ivltests/param_test4.v @@ -0,0 +1,14 @@ +module test; + + parameter parm1 = 0; + parameter parm2 = parm1 == 0; + + initial begin + // if got here then we compiled + if (parm2) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/param_times.v b/ivtest/ivltests/param_times.v new file mode 100644 index 000000000..44b9c6c2a --- /dev/null +++ b/ivtest/ivltests/param_times.v @@ -0,0 +1,48 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test is inspired by (and tests) PR#12. The interesting aspect of + * this is the multiply in the parameter passed to module foo instance yak. + */ +`define ONE 1 +`define TWO 2 + +module foo(in,out); + parameter blah = 2; + + input in; + output out; + + initial begin + if (blah != 4) begin + $display("FAILED -- parameter override of blah failed: %d", blah); + $finish; + end + + $display("PASSED"); + end + +endmodule + +module bar; + + foo #(`ONE * 2 + `TWO) yak (,); + +endmodule diff --git a/ivtest/ivltests/param_vec.v b/ivtest/ivltests/param_vec.v new file mode 100644 index 000000000..51b115c0c --- /dev/null +++ b/ivtest/ivltests/param_vec.v @@ -0,0 +1,14 @@ +module test; + + parameter [39:0] foo = 5; + + initial begin + if ($bits(foo) != 40) begin + $display("FAILED -- $bits(foo) == %d", $bits(foo)); + $finish; + end + + $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/param_vec2.v b/ivtest/ivltests/param_vec2.v new file mode 100644 index 000000000..2eaaf08a3 --- /dev/null +++ b/ivtest/ivltests/param_vec2.v @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* Based on PR#557. */ + +module test (); + + parameter s_ack = 3; + + parameter [s_ack-1:0] + Ack_Wait = 2'b 00, + Ack_Rdy = 2'b 11, + Ack_Err = 2'b 10; + + initial begin + if ($bits(Ack_Wait) != 3) begin + $display("FAILED -- $bits(Ack_Wait) == %0d (should be 3)", + $bits(Ack_Wait)); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/parameter_type.v b/ivtest/ivltests/parameter_type.v new file mode 100644 index 000000000..9294e7534 --- /dev/null +++ b/ivtest/ivltests/parameter_type.v @@ -0,0 +1,21 @@ +module top; + parameter irparam = -1.0; + parameter iiparam = -1; + parameter [7:0] uparam = -1.0; + parameter signed [7:0] sparam = -1.0; + parameter real rparam = -1; + parameter realtime rtparam = -1; + parameter integer iparam = -1.0; + parameter time tparam = -1.0; + + initial begin + $display("Implicit real: ", irparam); + $display("Implicit integer: ", iiparam); + $display("Unsigned: ", uparam); + $display("Signed: ", sparam); + $display("Real: ", rparam); + $display("Real time: ", rtparam); + $display("Integer: ", iparam); + $display("Time: ", tparam); + end +endmodule diff --git a/ivtest/ivltests/parameter_type2.v b/ivtest/ivltests/parameter_type2.v new file mode 100644 index 000000000..0cce62dc9 --- /dev/null +++ b/ivtest/ivltests/parameter_type2.v @@ -0,0 +1,158 @@ +module test(); + +parameter signed snv1 = 4'd1; +parameter signed [2:0] s3v1 = 4'd1; +parameter signed [3:0] s4v1 = 4'd1; +parameter signed [4:0] s5v1 = 4'd1; + +parameter signed snv15 = 4'd15; +parameter signed [2:0] s3v15 = 4'd15; +parameter signed [3:0] s4v15 = 4'd15; +parameter signed [4:0] s5v15 = 4'd15; + +parameter signed snvm1 = -4'sd1; +parameter signed [2:0] s3vm1 = -4'sd1; +parameter signed [3:0] s4vm1 = -4'sd1; +parameter signed [4:0] s5vm1 = -4'sd1; + +parameter signed snrm1 = -1.0; +parameter signed [2:0] s3rm1 = -1.0; +parameter signed [3:0] s4rm1 = -1.0; +parameter signed [4:0] s5rm1 = -1.0; + +parameter nnv1 = 4'd1; +parameter [2:0] u3v1 = 4'd1; +parameter [3:0] u4v1 = 4'd1; +parameter [4:0] u5v1 = 4'd1; + +parameter nnv15 = 4'd15; +parameter [2:0] u3v15 = 4'd15; +parameter [3:0] u4v15 = 4'd15; +parameter [4:0] u5v15 = 4'd15; + +parameter nnvm1 = -4'sd1; +parameter [2:0] u3vm1 = -4'sd1; +parameter [3:0] u4vm1 = -4'sd1; +parameter [4:0] u5vm1 = -4'sd1; + +parameter nnrm1 = -1.0; +parameter [2:0] u3rm1 = -1.0; +parameter [3:0] u4rm1 = -1.0; +parameter [4:0] u5rm1 = -1.0; + +reg fail = 0; + +reg match; + +initial begin + match = ($bits(snv1) == 4) && (snv1 === 1); + $display("snv1 : %2d (%0d`b%b) %c", snv1, $bits(snv1), snv1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s3v1) == 3) && (s3v1 === 1); + $display("s3v1 : %2d (%0d`b%b) %c", s3v1 , $bits(s3v1), s3v1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s4v1) == 4) && (s4v1 === 1); + $display("s4v1 : %2d (%0d`b%b) %c", s4v1 , $bits(s4v1), s4v1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s5v1) == 5) && (s5v1 === 1); + $display("s5v1 : %2d (%0d`b%b) %c", s5v1 , $bits(s5v1), s5v1, match ? " " : "*"); + fail = fail || !match; + + match = ($bits(snv15) == 4) && (snv15 === -1); + $display("snv15 : %2d (%0d`b%b) %c", snv15, $bits(snv15), snv15, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s3v15) == 3) && (s3v15 === -1); + $display("s3v15 : %2d (%0d`b%b) %c", s3v15, $bits(s3v15), s3v15, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s4v15) == 4) && (s4v15 === -1); + $display("s4v15 : %2d (%0d`b%b) %c", s4v15, $bits(s4v15), s4v15, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s5v15) == 5) && (s5v15 === 15); + $display("s5v15 : %2d (%0d`b%b) %c", s5v15, $bits(s5v15), s5v15, match ? " " : "*"); + fail = fail || !match; + + match = ($bits(snvm1) == 4) && (snvm1 === -1); + $display("snvm1 : %2d (%0d`b%b) %c", snvm1, $bits(snvm1), snvm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s3vm1) == 3) && (s3vm1 === -1); + $display("s3vm1 : %2d (%0d`b%b) %c", s3vm1, $bits(s3vm1), s3vm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s4vm1) == 4) && (s4vm1 === -1); + $display("s4vm1 : %2d (%0d`b%b) %c", s4vm1, $bits(s4vm1), s4vm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s5vm1) == 5) && (s5vm1 === -1); + $display("s5vm1 : %2d (%0d`b%b) %c", s5vm1, $bits(s5vm1), s5vm1, match ? " " : "*"); + fail = fail || !match; + + match = (snrm1 == -1); + $display("snrm1 : %4.1f %c", snrm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s3rm1) == 3) && (s3rm1 === -1); + $display("s3rm1 : %2d (%0d`b%b) %c", s3rm1, $bits(s3rm1), s3rm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s4rm1) == 4) && (s4rm1 === -1); + $display("s4rm1 : %2d (%0d`b%b) %c", s4rm1, $bits(s4rm1), s4rm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(s5rm1) == 5) && (s5rm1 === -1); + $display("s5rm1 : %2d (%0d`b%b) %c", s5rm1, $bits(s5rm1), s5rm1, match ? " " : "*"); + fail = fail || !match; + + match = ($bits(nnv1) == 4) && (nnv1 === 1); + $display("nnv1 : %2d (%0d`b%b) %c", nnv1, $bits(nnv1), nnv1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u3v1) == 3) && (u3v1 === 1); + $display("u3v1 : %2d (%0d`b%b) %c", u3v1 , $bits(u3v1), u3v1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u4v1) == 4) && (u4v1 === 1); + $display("u4v1 : %2d (%0d`b%b) %c", u4v1 , $bits(u4v1), u4v1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u5v1) == 5) && (u5v1 === 1); + $display("u5v1 : %2d (%0d`b%b) %c", u5v1 , $bits(u5v1), u5v1, match ? " " : "*"); + fail = fail || !match; + + match = ($bits(nnv15) == 4) && (nnv15 === 15); + $display("nnv15 : %2d (%0d`b%b) %c", nnv15, $bits(nnv15), nnv15, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u3v15) == 3) && (u3v15 === 7); + $display("u3v15 : %2d (%0d`b%b) %c", u3v15, $bits(u3v15), u3v15, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u4v15) == 4) && (u4v15 === 15); + $display("u4v15 : %2d (%0d`b%b) %c", u4v15, $bits(u4v15), u4v15, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u5v15) == 5) && (u5v15 === 15); + $display("u5v15 : %2d (%0d`b%b) %c", u5v15, $bits(u5v15), u5v15, match ? " " : "*"); + fail = fail || !match; + + match = ($bits(nnvm1) == 4) && (nnvm1 === -1); + $display("nnvm1 : %2d (%0d`b%b) %c", nnvm1, $bits(nnvm1), nnvm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u3vm1) == 3) && (u3vm1 === 7); + $display("u3vm1 : %2d (%0d`b%b) %c", u3vm1, $bits(u3vm1), u3vm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u4vm1) == 4) && (u4vm1 === 15); + $display("u4vm1 : %2d (%0d`b%b) %c", u4vm1, $bits(u4vm1), u4vm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u5vm1) == 5) && (u5vm1 === 31); + $display("u5vm1 : %2d (%0d`b%b) %c", u5vm1, $bits(u5vm1), u5vm1, match ? " " : "*"); + fail = fail || !match; + + match = (nnrm1 == -1.0); + $display("nnrm1 : %4.1f %c", nnrm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u3rm1) == 3) && (u3rm1 === 7); + $display("u3rm1 : %2d (%0d`b%b) %c", u3rm1, $bits(u3rm1), u3rm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u4rm1) == 4) && (u4rm1 === 15); + $display("u4rm1 : %2d (%0d`b%b) %c", u4rm1, $bits(u4rm1), u4rm1, match ? " " : "*"); + fail = fail || !match; + match = ($bits(u5rm1) == 5) && (u5rm1 === 31); + $display("u5rm1 : %2d (%0d`b%b) %c", u5rm1, $bits(u5rm1), u5rm1, match ? " " : "*"); + fail = fail || !match; + + if (fail) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/parpkg_test.v b/ivtest/ivltests/parpkg_test.v new file mode 100644 index 000000000..d1fb0275b --- /dev/null +++ b/ivtest/ivltests/parpkg_test.v @@ -0,0 +1,31 @@ +// This tests SystemVerilog packages +// +// This tests the elaboration infrastructure of packages in +// SystemVerilog. It actually covers a fair number of features, +// given the small size of the program: +// +// *) Parsing of package blocks and import statements +// *) Manage scope of names in package +// *) Actual references of imported names from packages. +// + +package pkg; + parameter int foo = 1; +endpackage + + +module test (); + + // import all from p1 + import pkg::*; + + initial begin + $display("pkg::foo = %0d", foo); + if (foo != 1) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/parpkg_test2.v b/ivtest/ivltests/parpkg_test2.v new file mode 100644 index 000000000..cb351c4a9 --- /dev/null +++ b/ivtest/ivltests/parpkg_test2.v @@ -0,0 +1,31 @@ +// This tests SystemVerilog packages +// +// This tests the elaboration infrastructure of packages in +// SystemVerilog. It actually covers a fair number of features, +// given the small size of the program: +// +// *) Parsing of package blocks and import statements +// *) Manage scope of names in package +// *) Actual references of imported names from packages. +// + +package pkg; + parameter int foo = 1; +endpackage + + +module test (); + + // import all from p1 + import pkg::foo; + + initial begin + $display("pkg::foo = %0d", foo); + if (foo != 1) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/parpkg_test3.v b/ivtest/ivltests/parpkg_test3.v new file mode 100644 index 000000000..b5676bbcb --- /dev/null +++ b/ivtest/ivltests/parpkg_test3.v @@ -0,0 +1,31 @@ +// This tests SystemVerilog packages +// +// This tests the elaboration infrastructure of packages in +// SystemVerilog. It actually covers a fair number of features, +// given the small size of the program: +// +// *) Parsing of package blocks and import statements +// *) Manage scope of names in package +// *) Actual references of imported names from packages. +// + +package pkg; + parameter int foo = 1; +endpackage + + +module test (); + + // import all from p1 + //import pkg::foo; + + initial begin + $display("pkg::foo = %0d", pkg::foo); + if (pkg::foo != 1) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/part_sel_port.v b/ivtest/ivltests/part_sel_port.v new file mode 100644 index 000000000..64e502b10 --- /dev/null +++ b/ivtest/ivltests/part_sel_port.v @@ -0,0 +1,44 @@ +// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test part selection in multidimensional packed ports assignment. + +module mod_test(output wire logic[1:8][7:0] out); + assign out = "testTEST"; +endmodule + +module mod_test2(output wire logic[1:8][7:0] out); + assign out = "abcdefgh"; +endmodule + +module mod_main; +logic[1:16][7:0] test_string; +mod_test dut(test_string[1:8]); +mod_test2 dut2(test_string[9:16]); + +initial begin + if(test_string !== "testTESTabcdefgh") begin + $display("FAILED"); + $finish(); + end + + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/partselsynth.v b/ivtest/ivltests/partselsynth.v new file mode 100644 index 000000000..268da37a4 --- /dev/null +++ b/ivtest/ivltests/partselsynth.v @@ -0,0 +1,62 @@ +module main; + + reg enable, bar_a, bar_b, val_in; + reg [7:0] scon; + + reg val; + //(* ivl_synthesis_on *) + always @(val_in or bar_a or bar_b or scon[7:6] or enable) + begin + if (scon[7:6]==2'b10) begin + val = 1'b1; + end else if (enable) begin + val = val_in; + end else begin + val = !bar_b & bar_a; + end + end + + (* ivl_synthesis_off *) + initial begin + val_in = 0; + enable = 0; + bar_b = 0; + bar_a = 0; + scon = 8'b10_000000; + + #1 if (val !== 1'b1) begin + $display("FAILED -- scon=%b, val=%b", scon, val); + $finish; + end + + scon = 0; + enable = 1; + #1 if (val !== 1'b0) begin + $display("FAILED -- scon=%b, enable=%b, val=%b", scon, enable, val); + $finish; + end + + val_in = 1; + #1 if (val !== 1'b1) begin + $display("FAILED -- scon=%b, enable=%b, val_in=%b, val=%b", + scon, enable, val_in, val); + $finish; + end + + enable = 0; + #1 if (val !== 1'b0) begin + $display("FAILED -- scon=%b, enable=%b, val=%b", scon, enable, val); + $finish; + end + + bar_a = 1; + #1 if (val !== 1'b1) begin + $display("FAILED -- scon=%b, enable=%b, bar_a==%b, bar_b=%b, val=%b", + scon, enable, bar_a, bar_b, val); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/patch1268.v b/ivtest/ivltests/patch1268.v new file mode 100644 index 000000000..ae463ce38 --- /dev/null +++ b/ivtest/ivltests/patch1268.v @@ -0,0 +1,28 @@ +// This is a regression test for the bug fixed in patch tracker #1268. +module test(); + +reg [19:0] a[15:0]; + +reg [3:0] idx[3:1]; + +initial begin + idx[1] = 2; + idx[2] = 3; + idx[3] = 4; + a[idx[1]][idx[2]*4 +: 4] <= #(idx[3]) 4'ha; + #4; + $display("%h", a[2]); + if (a[2] !== 20'hxxxxx) begin + $display("FAILED"); + $finish; + end + #1; + $display("%h", a[2]); + if (a[2] !== 20'hxaxxx) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pca1.v b/ivtest/ivltests/pca1.v new file mode 100644 index 000000000..badc0f08b --- /dev/null +++ b/ivtest/ivltests/pca1.v @@ -0,0 +1,63 @@ +// Copyright (c) 2000 Steve Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +// SDW: First test for Procedural continuous assignment + +module test; + + +// +// Define a procedural assignment based mux. +// +reg [1:0] sel; +reg [1:0] out, a,b,c,d; +reg error; + +always @ (sel) + case (sel) + 2'b00: assign out = a; + 2'b01: assign out = b; + 2'b10: assign out = c; + 2'b11: assign out = d; + endcase + +initial + begin + error = 0; + #1 ; + sel = 0; + a = 0; + #1; + if(out !== 2'b00) + begin + $display("FAILED - Procedural assignment out != 0 (1)"); + error =1; + end + #1; + a = 1; + #1; + if(out !== 2'b01) + begin + $display("FAILED - Procedural assignment out != 1 (2)"); + error =1; + end + if(error == 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/plus_5.v b/ivtest/ivltests/plus_5.v new file mode 100644 index 000000000..89fde48a4 --- /dev/null +++ b/ivtest/ivltests/plus_5.v @@ -0,0 +1,116 @@ +/* + * Verification test for increment/decrement operators + * + * Author: Prasad Joshi + */ + +module main; +logic la; +logic lb; + +int ia; +int ib; + +bit ba; +bit bb; + +real ra; +real rb; +real rc; + + initial begin + + /* logic tests */ + la = 0; + #1 + + lb = ++la; + #1 + if (la != lb) begin + $display("FAILED"); + $finish; + end + + ib = 15; + #1 + ia = ++ib; + #1 + if (ia != ib) begin + $display("FAILED"); + $finish; + end + + ia = 15; + #1 + ib = ia++; + #1 + if (ia != 16 || ib != 15) begin + $display("FAILED"); + $finish; + end + + ib = --ia; + if (ib != ia) begin + $display("FAILED"); + $finish; + end + + /* bit test */ + ba = 0; + #1 + for (ia = 0; ia < 10; ia = ia + 1) begin + bb = --ba; + #1 + if (bb != ba && !(bb == 1 || bb == 0)) begin + $display("FAILED"); + $finish; + end + end + + /* real decrement test */ + ia = 15; + ra = --ia; + if (ra != ia) begin + $display("FAILED"); + $finish; + end + + rb = 19.99; + rc = rb - 2; + ra = --rb; + if (ra != rb) begin + $display("FAILED"); + $finish; + end + + ra = rb--; + if (ra == rb || rc != rb) begin + $display("FAILED"); + $finish; + end + + /* real increment test */ + ia = 15; + ra = ++ia; + if (ra != ia) begin + $display("FAILED"); + $finish; + end + + rb = 19.99; + rc = rb + 2; + ra = ++rb; + if (ra != rb) begin + $display("FAILED"); + $finish; + end + + ra = rb++; + if (ra == rb || rc != rb) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/plus_arg_string.v b/ivtest/ivltests/plus_arg_string.v new file mode 100644 index 000000000..edff784ef --- /dev/null +++ b/ivtest/ivltests/plus_arg_string.v @@ -0,0 +1,13 @@ +module main; + string img; + + initial begin + if (!$value$plusargs("img=%s", img)) begin + $display("Specify image file with +img=."); + $finish_and_return(1); + end + $display("Using image: %s", img); + if (img != "test_image.file") $display("FAILED"); + else $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/port-test2.v b/ivtest/ivltests/port-test2.v new file mode 100644 index 000000000..b5c3f9350 --- /dev/null +++ b/ivtest/ivltests/port-test2.v @@ -0,0 +1,83 @@ +// This is a compile time test, +// for various port declaration syntax options + +`define TEST3 +// `define TEST3_X + +// unconnected ports + +`ifdef TEST3 +module port_3 + ( + dummy_1, + /* unconnected */, + in[7:0], + dummy_2, + out[7:0], + /* unconnected */ + ); + input [7:0] in; + output [7:0] out; + output dummy_1; + output dummy_2; + assign out = in; +endmodule +`endif // ifdef TEST_3 + + +module port_test; + + reg [7:0] data; + +`ifdef TEST3 + wire [7:0] out_3; + reg pass_3; + initial pass_3 = 1; + port_3 dut_3 + (, // unconnected dummy_1 +`ifdef TEST3_X +// This fails in verilog-XL with: +// Error! Expression given for a null module port [Verilog-EXPNMP] +// "port-test.v", 115: dut_3(, pass_3, data[7:0], , +// out_3[7:0], ) + pass_3, // dummy unconnected +`else + , // unconnected unconnected +`endif + data[7:0], + , // unconnected dummy_2 + out_3[7:0], + // unconnected unconnected + ); +`endif + + initial + begin + data <= 1; + #1; + + while (data != 0) + begin + $display ("%b", data); + +`ifdef TEST3 + if (out_3 != data) + begin + $display("data=%b, out_2=%b, FAILED", data, out_3); + pass_3 = 0; + end +`endif + + data <= data << 1; + #1; + end + +`ifdef TEST3 + if (pass_3) + $display("PASSED"); +`endif + + $finish; + end + +endmodule // port_test diff --git a/ivtest/ivltests/port-test3.v b/ivtest/ivltests/port-test3.v new file mode 100644 index 000000000..98a4ad03a --- /dev/null +++ b/ivtest/ivltests/port-test3.v @@ -0,0 +1,48 @@ +/*********************************************************************** + + Incorrect direction non-detection test case + Copyright (C) 2001 Eric LaForest, ecl@pet.dhs.org + Licenced under GPL + +***********************************************************************/ + +module CPU (data, address, rw, clock, reset); + inout [15:0] data; + output [15:0] address; + // This should be an output really.... + input rw; + input clock, reset; + + reg [15:0] data, address; // XXX error on data + reg rw; // error on rw + + // I presume these should not be allowed to occur.... + always @(posedge clock) begin + rw <= 1'b1; + end + + always @(negedge clock) begin + rw <= 1'b0; + end + +endmodule + +module BENCH (); + + reg [15:0] address, data; + reg rw, clock, reset; + + CPU fm (address, data, rw, clock, reset); + + initial begin + clock <= 0; + reset <= 1; + #1000; + $finish; + end + + always begin + # 10 clock <= ~clock; + end + +endmodule diff --git a/ivtest/ivltests/port-test4a.v b/ivtest/ivltests/port-test4a.v new file mode 100644 index 000000000..aefc27308 --- /dev/null +++ b/ivtest/ivltests/port-test4a.v @@ -0,0 +1,20 @@ +/*********************************************************************** + + Duplicate input declaration test case + Duplicate port declarations should generate an error + +***********************************************************************/ + +module port_test4 ( + a, // Input + b, // Output + ); + +input a; +input a; + +output b; + +assign b=a; + +endmodule diff --git a/ivtest/ivltests/port-test4b.v b/ivtest/ivltests/port-test4b.v new file mode 100644 index 000000000..658e4c5a3 --- /dev/null +++ b/ivtest/ivltests/port-test4b.v @@ -0,0 +1,20 @@ +/*********************************************************************** + + Duplicate output declaration test case + Duplicate port declarations should generate an error + +***********************************************************************/ + +module port_test4 ( + a, // Input + b, // Output + ); + +input a; + +output b; +output b; + +assign b=a; + +endmodule diff --git a/ivtest/ivltests/port-test5.v b/ivtest/ivltests/port-test5.v new file mode 100644 index 000000000..964d02823 --- /dev/null +++ b/ivtest/ivltests/port-test5.v @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg a, b; + wire res; + + has_ports test(res, a, b); + + initial begin + a = 0; + b = 0; + #1 $display("has_ports (%b, %b, %b)", res, a, b); + if (res !== (a & b)) begin + $display("FAILED"); + $finish; + end + + a = 1; + #1 $display("has_ports (%b, %b, %b)", res, a, b); + if (res !== (a & b)) begin + $display("FAILED"); + $finish; + end + + b = 1; + #1 $display("has_ports (%b, %b, %b)", res, a, b); + if (res !== (a & b)) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main + +module has_ports (output reg o, input wire a, input wire b); + + always @* o <= a & b; + +endmodule // has_ports diff --git a/ivtest/ivltests/port-test6.v b/ivtest/ivltests/port-test6.v new file mode 100644 index 000000000..b8a3d7a97 --- /dev/null +++ b/ivtest/ivltests/port-test6.v @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg [7:0] a, b; + wire [8:0] res; + + has_ports test(res, a, b); + + initial begin + a = 0; + b = 0; + #1 $display("has_ports (%b, %b, %b)", res, a, b); + if (res !== (a + b)) begin + $display("FAILED"); + $finish; + end + + a = 10; + #1 $display("has_ports (%b, %b, %b)", res, a, b); + if (res !== (a + b)) begin + $display("FAILED"); + $finish; + end + + b = 11; + #1 $display("has_ports (%b, %b, %b)", res, a, b); + if (res !== (a + b)) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main + +module has_ports (output reg [8:0] o, + input wire [7:0] a, + input wire [7:0] b); + + always @* o <= a + b; + +endmodule // has_ports diff --git a/ivtest/ivltests/port-test7.v b/ivtest/ivltests/port-test7.v new file mode 100644 index 000000000..929481f5c --- /dev/null +++ b/ivtest/ivltests/port-test7.v @@ -0,0 +1,39 @@ +`define REG_DELAY 1 + +module ansireg(input clk, reset, input [7:0] d, output reg [7:0] q ); +always @(posedge clk or posedge reset) + if(reset) + q <= #(`REG_DELAY) 8'h00; + else + q <= #(`REG_DELAY) d; + +endmodule + +module main; + + reg clk, reset; + reg [7:0] d; + wire [7:0] q; + + ansireg U(clk, reset, d, q); + + initial begin + clk = 0; + reset = 0; + d = 'hff; + + #(2*`REG_DELAY) clk <= 1; + #(2*`REG_DELAY) if (q !== d) begin + $display("FAILED -- clk=%b, reset=%b, d=%b, q=%b", clk, reset, d, q); + $finish; + end + + reset <= 1; + #(1 + `REG_DELAY) if (q !== 8'h00) begin + $display("FAILED -- clk=%b, reset=%b, d=%b, q=%b", clk, reset, d, q); + $finish; + end + + $display("PASSED"); + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/posedge.v b/ivtest/ivltests/posedge.v new file mode 100644 index 000000000..f8f975deb --- /dev/null +++ b/ivtest/ivltests/posedge.v @@ -0,0 +1,52 @@ +// +// Copyright (c) 2000 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// single bit positive events +// + +module main (); + + reg flag1; + reg event_1; + + always @ (posedge event_1) flag1 = ~flag1; + + initial begin + event_1 = 1'b0; + #1 flag1 = 0; + + #1 event_1 = 1'b1; + + #1 + if (flag1 !== 1'b1) begin + $display("FAILED -- 0->1 didn't trigger flag1"); + $finish; + end + + event_1 = 1'b0; + + #1 + if (flag1 !== 1'b1) begin + $display("FAILED -- 1->0 DID trigger flag1"); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pow-ca.v b/ivtest/ivltests/pow-ca.v new file mode 100644 index 000000000..582aef2b7 --- /dev/null +++ b/ivtest/ivltests/pow-ca.v @@ -0,0 +1,119 @@ +module top; + reg signed [7:0] neg = -2; + reg signed [7:0] m1 = -1; + reg signed [7:0] zero = 0; + reg signed [7:0] one = 1; + reg signed [7:0] pos = 2; + reg signed [7:0] pose = 2; + reg signed [7:0] poso = 3; + reg signed [7:0] res; + + wire signed [7:0] neg_pose = neg**pose; + wire signed [7:0] neg_poso = neg**poso; + wire signed [7:0] m1_pose = m1**pose; + wire signed [7:0] m1_poso = m1**poso; + wire signed [7:0] zero_pos = zero**pos; + wire signed [7:0] one_pos = one**pos; + wire signed [7:0] pos_pos = pos**pos; + + wire signed [7:0] neg_zero = neg**zero; + wire signed [7:0] m1_zero = m1**zero; + wire signed [7:0] zero_zero = zero**zero; + wire signed [7:0] one_zero = one**zero; + wire signed [7:0] pos_zero = pos**zero; + + wire signed [7:0] neg_neg = neg**m1; + wire signed [7:0] m1_nege = m1**neg; + wire signed [7:0] m1_nego = m1**m1; + wire signed [7:0] zero_neg = zero**m1; + wire signed [7:0] one_neg = one**m1; + wire signed [7:0] pos_neg = pos**m1; + + reg pass; + + initial begin + pass = 1'b1; + + #1; + + /* Positive exponent. */ + if (neg_pose !== 4) begin + $display("Failed neg**pos even, got %d", neg_pose); + pass = 1'b0; + end + if (neg_poso !== -8) begin + $display("Failed neg**pos odd, got %d", neg_poso); + pass = 1'b0; + end + if (m1_pose !== 1) begin + $display("Failed -1**pos even, got %d", m1_pose); + pass = 1'b0; + end + if (m1_poso !== -1) begin + $display("Failed -1**pos odd, got %d", m1_poso); + pass = 1'b0; + end + if (zero_pos !== 0) begin + $display("Failed 0**pos, got %d", zero_pos); + pass = 1'b0; + end + if (one_pos !== 1) begin + $display("Failed 1**pos, got %d", one_pos); + pass = 1'b0; + end + if (pos_pos !== 4) begin + $display("Failed 1**pos, got %d", pos_pos); + pass = 1'b0; + end + + /* Zero exponent. */ + if (neg_zero !== 1) begin + $display("Failed neg**0, got %d", neg_zero); + pass = 1'b0; + end + if (m1_zero !== 1) begin + $display("Failed -1**0, got %d", m1_zero); + pass = 1'b0; + end + if (zero_zero !== 1) begin + $display("Failed 0**0, got %d", zero_zero); + pass = 1'b0; + end + if (one_zero !== 1) begin + $display("Failed 1**0, got %d", one_zero); + pass = 1'b0; + end + if (pos_zero !== 1) begin + $display("Failed pos**0, got %d", pos_zero); + pass = 1'b0; + end + + /* Negative exponent. */ + if (neg_neg !== 0) begin + $display("Failed neg**neg got %d", neg_neg); + pass = 1'b0; + end + if (m1_nege !== 1) begin + $display("Failed -1**neg (even) got %d", m1_nege); + pass = 1'b0; + end + if (m1_nego !== -1) begin + $display("Failed -1**neg (odd) got %d", m1_nego); + pass = 1'b0; + end + if (zero_neg !== 'sbx) begin + $display("Failed 0**neg (odd) got %d", zero_neg); + pass = 1'b0; + end + if (one_neg !== 1) begin + $display("Failed 1**neg got %d", one_neg); + pass = 1'b0; + end + if (pos_neg !== 0) begin + $display("Failed pos**neg got %d", pos_neg); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pow-const.v b/ivtest/ivltests/pow-const.v new file mode 100644 index 000000000..ac52fe41a --- /dev/null +++ b/ivtest/ivltests/pow-const.v @@ -0,0 +1,108 @@ +module top; + parameter neg_pose = -2**2; + parameter neg_poso = -2**3; + parameter m1_pose = -1**2; + parameter m1_poso = -1**3; + parameter zero_pos = 0**2; + parameter one_pos = 1**2; + parameter pos_pos = 2**2; + + parameter neg_zero = -2**0; + parameter m1_zero = -1**0; + parameter zero_zero = 0**0; + parameter one_zero = 1**0; + parameter pos_zero = 2**0; + + parameter neg_neg = -2**-1; + parameter m1_nege = -1**-2; + parameter m1_nego = -1**-1; + parameter zero_neg = 0**-1; + parameter one_neg = 1**-1; + parameter pos_neg = 2**-1; + + reg pass; + + initial begin + pass = 1'b1; + + /* Positive exponent. */ + if (neg_pose !== 4) begin + $display("Failed neg**pos even, got %d", neg_pose); + pass = 1'b0; + end + if (neg_poso !== -8) begin + $display("Failed neg**pos odd, got %d", neg_poso); + pass = 1'b0; + end + if (m1_pose !== 1) begin + $display("Failed -1**pos even, got %d", m1_pose); + pass = 1'b0; + end + if (m1_poso !== -1) begin + $display("Failed -1**pos odd, got %d", m1_poso); + pass = 1'b0; + end + if (zero_pos !== 0) begin + $display("Failed 0**pos, got %d", zero_pos); + pass = 1'b0; + end + if (one_pos !== 1) begin + $display("Failed 1**pos, got %d", one_pos); + pass = 1'b0; + end + if (pos_pos !== 4) begin + $display("Failed 1**pos, got %d", pos_pos); + pass = 1'b0; + end + + /* Zero exponent. */ + if (neg_zero !== 1) begin + $display("Failed neg**0, got %d", neg_zero); + pass = 1'b0; + end + if (m1_zero !== 1) begin + $display("Failed -1**0, got %d", m1_zero); + pass = 1'b0; + end + if (zero_zero !== 1) begin + $display("Failed 0**0, got %d", zero_zero); + pass = 1'b0; + end + if (one_zero !== 1) begin + $display("Failed 1**0, got %d", one_zero); + pass = 1'b0; + end + if (pos_zero !== 1) begin + $display("Failed pos**0, got %d", pos_zero); + pass = 1'b0; + end + + /* Negative exponent. */ + if (neg_neg !== 0) begin + $display("Failed neg**neg got %d", neg_neg); + pass = 1'b0; + end + if (m1_nege !== 1) begin + $display("Failed -1**neg (even) got %d", m1_nege); + pass = 1'b0; + end + if (m1_nego !== -1) begin + $display("Failed -1**neg (odd) got %d", m1_nego); + pass = 1'b0; + end + if (zero_neg !== 'sbx) begin + $display("Failed 0**neg (odd) got %d", zero_neg); + pass = 1'b0; + end + if (one_neg !== 1) begin + $display("Failed 1**neg got %d", one_neg); + pass = 1'b0; + end + if (pos_neg !== 0) begin + $display("Failed pos**neg got %d", pos_neg); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pow-proc.v b/ivtest/ivltests/pow-proc.v new file mode 100644 index 000000000..9c547386c --- /dev/null +++ b/ivtest/ivltests/pow-proc.v @@ -0,0 +1,116 @@ +module top; + reg pass; + + reg signed [7:0] neg = -2; + reg signed [7:0] m1 = -1; + reg signed [7:0] zero = 0; + reg signed [7:0] one = 1; + reg signed [7:0] pos = 2; + reg signed [7:0] pose = 2; + reg signed [7:0] poso = 3; + reg signed [7:0] res; + + initial begin + pass = 1'b1; + + #1; + + /* Positive exponent. */ + res = neg**pose; + if (res !== 4) begin + $display("Failed neg**pos even, got %d", res); + pass = 1'b0; + end + res = neg**poso; + if (res !== -8) begin + $display("Failed neg**pos odd, got %d", res); + pass = 1'b0; + end + res = m1**pose; + if (res !== 1) begin + $display("Failed -1**pos even, got %d", res); + pass = 1'b0; + end + res = m1**poso; + if (res !== -1) begin + $display("Failed -1**pos odd, got %d", res); + pass = 1'b0; + end + res = zero**pos; + if (res !== 0) begin + $display("Failed 0**pos, got %d", res); + pass = 1'b0; + end + res = one**pos; + if (res !== 1) begin + $display("Failed 1**pos, got %d", res); + pass = 1'b0; + end + res = pos**pos; + if (res !== 4) begin + $display("Failed 1**pos, got %d", res); + pass = 1'b0; + end + + /* Zero exponent. */ + res = neg**zero; + if (res !== 1) begin + $display("Failed neg**0, got %d", res); + pass = 1'b0; + end + res = m1**zero; + if (res !== 1) begin + $display("Failed -1**0, got %d", res); + pass = 1'b0; + end + res = zero**zero; + if (res !== 1) begin + $display("Failed 0**0, got %d", res); + pass = 1'b0; + end + res = one**zero; + if (res !== 1) begin + $display("Failed 1**0, got %d", res); + pass = 1'b0; + end + res = pos**zero; + if (res !== 1) begin + $display("Failed pos**0, got %d", res); + pass = 1'b0; + end + + /* Negative exponent. */ + res = neg**m1; + if (res !== 0) begin + $display("Failed neg**neg got %d", res); + pass = 1'b0; + end + res = m1**neg; + if (res !== 1) begin + $display("Failed -1**neg (even) got %d", res); + pass = 1'b0; + end + res = m1**m1; + if (res !== -1) begin + $display("Failed -1**neg (odd) got %d", res); + pass = 1'b0; + end + res = zero**m1; + if (res !== 'sbx) begin + $display("Failed 0**neg got %d", res); + pass = 1'b0; + end + res = one**m1; + if (res !== 1) begin + $display("Failed 1**neg got %d", res); + pass = 1'b0; + end + res = pos**m1; + if (res !== 0) begin + $display("Failed pos**neg got %d", res); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pow_ca_signed.v b/ivtest/ivltests/pow_ca_signed.v new file mode 100644 index 000000000..519dccc4c --- /dev/null +++ b/ivtest/ivltests/pow_ca_signed.v @@ -0,0 +1,34 @@ +`begin_keywords "1364-2005" +module test(); + +reg signed [15:0] a; +reg signed [7:0] b; +reg signed [31:0] expect; +wire signed [31:0] actual; + +reg signed [127:0] long_x; +real real_x; + +assign actual = a ** b; + +initial begin + for (a = -32768; a < 32767; a = a + 1) begin:outer_loop + long_x = 1; + for (b = 0; b < 127; b = b + 1) begin:inner_loop + real_x = $itor(a) ** $itor(b); + if (real_x < 0.0) real_x = -real_x; + if (real_x >= 2.0**128.0) disable outer_loop; + expect = long_x; + #0; // wait for net propagation + if (actual !== expect) begin + $display("FAILED : %0d ** %0d = %0d not %0d", a, b, expect, actual); + $finish; + end + long_x = long_x * a; + end + end + $display("PASSED"); +end + +endmodule +`end_keywords diff --git a/ivtest/ivltests/pow_ca_unsigned.v b/ivtest/ivltests/pow_ca_unsigned.v new file mode 100644 index 000000000..e1901eb25 --- /dev/null +++ b/ivtest/ivltests/pow_ca_unsigned.v @@ -0,0 +1,33 @@ +`begin_keywords "1364-2005" +module test(); + +reg [15:0] a; +reg [7:0] b; +reg [31:0] expect; +wire [31:0] actual; + +reg [127:0] long_x; +real real_x; + +assign actual = a ** b; + +initial begin + for (a = 0; a < 65535; a = a + 1) begin:outer_loop + long_x = 1; + for (b = 0; b < 127; b = b + 1) begin:inner_loop + real_x = $itor(a) ** $itor(b); + if (real_x >= 2.0**128.0) disable outer_loop; + expect = long_x; + #0; // wait for net propagation + if (actual !== expect) begin + $display("FAILED : %0d ** %0d = %0d not %0d", a, b, expect, actual); + $finish; + end + long_x = long_x * a; + end + end + $display("PASSED"); +end + +endmodule +`end_keywords diff --git a/ivtest/ivltests/pow_reg_signed.v b/ivtest/ivltests/pow_reg_signed.v new file mode 100644 index 000000000..42a0f2ce7 --- /dev/null +++ b/ivtest/ivltests/pow_reg_signed.v @@ -0,0 +1,32 @@ +`begin_keywords "1364-2005" +module test(); + +reg signed [15:0] a; +reg signed [7:0] b; +reg signed [31:0] expect; +reg signed [31:0] actual; + +reg signed [127:0] long_x; +real real_x; + +initial begin + for (a = -32768; a < 32767; a = a + 1) begin:outer_loop + long_x = 1; + for (b = 0; b < 127; b = b + 1) begin:inner_loop + real_x = $itor(a) ** $itor(b); + if (real_x < 0.0) real_x = -real_x; + if (real_x >= 2.0**128.0) disable outer_loop; + expect = long_x; + actual = a ** b; + if (actual !== expect) begin + $display("FAILED : %0d ** %0d = %0d not %0d", a, b, expect, actual); + $finish; + end + long_x = long_x * a; + end + end + $display("PASSED"); +end + +endmodule +`end_keywords diff --git a/ivtest/ivltests/pow_reg_unsigned.v b/ivtest/ivltests/pow_reg_unsigned.v new file mode 100644 index 000000000..c278c0094 --- /dev/null +++ b/ivtest/ivltests/pow_reg_unsigned.v @@ -0,0 +1,33 @@ +`begin_keywords "1364-2005" +module test(); + +reg [15:0] a; +reg [7:0] b; +reg [31:0] expect; +reg [31:0] actual; + +reg [127:0] long_x; +real real_x; + +initial begin + for (a = 0; a < 65535; a = a + 1) begin:outer_loop + long_x = 1; + for (b = 0; b < 127; b = b + 1) begin:inner_loop + real_x = $itor(a) ** $itor(b); + if (real_x >= 2.0**128.0) disable outer_loop; + expect = long_x; + actual = a ** b; + actual = a ** b; + actual = a ** b; + if (actual !== expect) begin + $display("FAILED : %0d ** %0d = %0d not %0d", a, b, expect, actual); + $finish; + end + long_x = long_x * a; + end + end + $display("PASSED"); +end + +endmodule +`end_keywords diff --git a/ivtest/ivltests/pow_signed.v b/ivtest/ivltests/pow_signed.v new file mode 100644 index 000000000..98fcfde69 --- /dev/null +++ b/ivtest/ivltests/pow_signed.v @@ -0,0 +1,45 @@ +module top; + reg pass; + integer in1, in2, res; + + initial begin + pass = 1'b1; + + in1 = 1; in2 = 2; + res = in1 ** in2; + if (res != 1) begin + $display("Failed: 1 ** 2, expected 1, got %0d", res); + pass = 1'b0; + end + + in1 = 2; in2 = 3; + res = in1 ** in2; + if (res != 8) begin + $display("Failed: 2 ** 3, expected 8, got %0d", res); + pass = 1'b0; + end + + in1 = -2; in2 = 2; + res = in1 ** in2; + if (res != 4) begin + $display("Failed: -2 ** 2, expected 4, got %0d", res); + pass = 1'b0; + end + + in1 = -2; in2 = 3; + res = in1 ** in2; + if (res != -8) begin + $display("Failed: -2 ** 3, expected -8, got %0d", res); + pass = 1'b0; + end + + in1 = 1; in2 = -1; + res = in1 ** in2; + if (res != 1) begin + $display("Failed: 1 ** -1, expected 1, got %0d", res); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pow_unsigned.v b/ivtest/ivltests/pow_unsigned.v new file mode 100644 index 000000000..94a82e0f1 --- /dev/null +++ b/ivtest/ivltests/pow_unsigned.v @@ -0,0 +1,38 @@ +module top; + reg passed = 1'b1; + + reg [199:0] r, a, b; + + initial begin + a = 'd5; + + b = 'd2; // A simple test. + r = a ** b; + if (r != 'd25) begin + $display("Failed: 5 ** 2 gave %d, expected 25", r); + passed = 1'b0; + end + + b = 'd55; // A 128 bit value. + r = a ** b; + if (r != 200'd277555756156289135105907917022705078125) begin + $display("Failed: 5 ** 55\n gave %0d", r); + $display(" expected 277555756156289135105907917022705078125"); + passed = 1'b0; + end + + b = 'd86; // A 200 bit value. + r = a ** b; + if (r != 200'd1292469707114105741986576081359316958696581423282623291015625) begin + $display("Failed: 5 ** 55\n gave %0d", r); + $display(" expected 1292469707114105741986576081359316958696581423282623291015625"); + passed = 1'b0; + end + if (r != 'd5**'d86) begin + $display("Failed: compile-time/run-time value mismatch."); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1000.v b/ivtest/ivltests/pr1000.v new file mode 100644 index 000000000..a5ab8f334 --- /dev/null +++ b/ivtest/ivltests/pr1000.v @@ -0,0 +1,21 @@ +/* + * Based on PR#1000. + */ + +module foo20 (); + /* This is reported to return the warning: + warning: Ranges in localparam definition are not supported. + The value is OK, and the compiler chooses a width that holds + whatever value is there. */ + localparam [65:0] foo = 0; + + initial begin + if ($bits(foo) != 66) begin + $display("FAILED -- $bits(foo) --> %0d", $bits(foo)); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1002.v b/ivtest/ivltests/pr1002.v new file mode 100644 index 000000000..ce11d5a97 --- /dev/null +++ b/ivtest/ivltests/pr1002.v @@ -0,0 +1,42 @@ +module top ( + ); + +reg signed [13:0] datain; +wire signed [15:0] dataout; + +assign dataout = datain >>> 2; + +reg test_failed; + +initial + begin + test_failed = 0; + #1 datain = 14'h0FFF; + #1 datain = 14'h0000; + #1 datain = 14'h1FFF; + #1 datain = 14'h1000; + #1 datain = 14'h2FFF; + #1 datain = 14'h2000; + #1 datain = 14'h3FFF; + #1 datain = 14'h3000; + #2; + if (test_failed) + $display("TEST FAILED :-("); + else + $display("TEST PASSED :-)"); + end + +wire signed [15:0] expected_dataout; + +assign expected_dataout = ($signed({datain[13:2], 2'b0}) / 4) ; + +always @(dataout) + if (expected_dataout != dataout) + begin + $display("datain = %d dataout = %h expected = %h ... CHECK FAILED", datain, dataout, expected_dataout); + test_failed = 1; + end + else + $display("datain = %d dataout = %d expected = %d ... CHECK PASSED", datain, dataout, expected_dataout); + +endmodule // top diff --git a/ivtest/ivltests/pr1002a.v b/ivtest/ivltests/pr1002a.v new file mode 100644 index 000000000..471bfe8fa --- /dev/null +++ b/ivtest/ivltests/pr1002a.v @@ -0,0 +1,42 @@ +module top ( + ); + +reg signed [13:0] datain; +wire signed [15:0] dataout; + +assign dataout = datain <<< 2; + +reg test_failed; + +initial + begin + test_failed = 0; + #1 datain = 14'h0FFF; + #1 datain = 14'h0000; + #1 datain = 14'h1FFF; + #1 datain = 14'h1000; + #1 datain = 14'h2FFF; + #1 datain = 14'h2000; + #1 datain = 14'h3FFF; + #1 datain = 14'h3000; + #2; + if (test_failed) + $display("TEST FAILED :-("); + else + $display("TEST PASSED :-)"); + end + +wire signed [15:0] expected_dataout; + +assign expected_dataout = $signed({datain[13:0], 2'b0}); + +always @(dataout) + if (expected_dataout != dataout) + begin + $display("datain = %d dataout = %d expected = %d ... CHECK FAILED", datain, dataout, expected_dataout); + test_failed = 1; + end + else + $display("datain = %d dataout = %d expected = %d ... CHECK PASSED", datain, dataout, expected_dataout); + +endmodule // top diff --git a/ivtest/ivltests/pr1007.v b/ivtest/ivltests/pr1007.v new file mode 100644 index 000000000..8818b0227 --- /dev/null +++ b/ivtest/ivltests/pr1007.v @@ -0,0 +1,20 @@ +`timescale 1 ps / 1 ps + +module main; + +initial begin + #1; + if ($realtime == 0) begin + $display ("FAILED -- time == 0"); + $finish; + end + + if ($realtime != 1) begin + $display ("FAILED -- time != 0"); + $finish; + end + + $display("PASSED"); +end + +endmodule // main diff --git a/ivtest/ivltests/pr1008.v b/ivtest/ivltests/pr1008.v new file mode 100644 index 000000000..e75aed6c0 --- /dev/null +++ b/ivtest/ivltests/pr1008.v @@ -0,0 +1,29 @@ +/* + * Based on PR#1008 + */ + +`timescale 1 ps / 1 ps + +module star; + +reg a; +reg b; + +initial begin + $monitor("b = %b", b); + #1; + a = 1; + #2; + a = 0; + #2; + a = 1; +end + +/* This generated the error: + :0: internal error: NetProc::nex_output not implemented + Before CVS 20040630 */ +always @* begin + b = #1 ~a; +end + +endmodule // star diff --git a/ivtest/ivltests/pr1022.v b/ivtest/ivltests/pr1022.v new file mode 100644 index 000000000..66728211b --- /dev/null +++ b/ivtest/ivltests/pr1022.v @@ -0,0 +1,21 @@ +// based on PR#1022 + +module foo; + wire [-1:0] fred; + assign fred = 1; + + initial begin + #1 if (fred[0] !== 1) begin + $display("FAILED -- fred[0] = %b", fred[0]); + $finish; + end + + if (fred[-1] !== 0) begin + $display("FAILED -- fred[-1] = %b", fred[-1]); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/pr1024.v b/ivtest/ivltests/pr1024.v new file mode 100644 index 000000000..317951c65 --- /dev/null +++ b/ivtest/ivltests/pr1024.v @@ -0,0 +1,11 @@ +/* + * Based on PR#1024 + */ + +module test; + + initial begin + wait(1) ; /* This is weird, but legal. */ + $display("PASSED"); + end +endmodule // test diff --git a/ivtest/ivltests/pr1026.v b/ivtest/ivltests/pr1026.v new file mode 100644 index 000000000..2d6465ff4 --- /dev/null +++ b/ivtest/ivltests/pr1026.v @@ -0,0 +1,21 @@ +/* + * This is based on PR#1026. + */ +module main; + + reg [4:0] index; + reg [31:0] foo; + + initial begin + for (index = 0 ; index < 31 ; index = index + 1) begin + #1 $display("index=%d, foo=%b", index, foo); + end + $finish(0); + end + + always @(*) + begin + foo = 32'b0; + foo[index]=1'b1; + end +endmodule diff --git a/ivtest/ivltests/pr1029.v b/ivtest/ivltests/pr1029.v new file mode 100644 index 000000000..aaa949701 --- /dev/null +++ b/ivtest/ivltests/pr1029.v @@ -0,0 +1,17 @@ +/* + * This is based on PR#1029 + */ +module main(); + +`define none +`define fred eric +`define bill main`none.eric +reg [8*8:0] eric; +initial + begin + eric = "PASSED"; + $display("%0s",`bill); + $finish ; + end + +endmodule diff --git a/ivtest/ivltests/pr1032.v b/ivtest/ivltests/pr1032.v new file mode 100644 index 000000000..a0efb73a6 --- /dev/null +++ b/ivtest/ivltests/pr1032.v @@ -0,0 +1,53 @@ +module test; + + reg d; + wire bar; + + // Assign some value to bar with weak drive. + assign (weak0, weak1) bar = d; + + // Whatever value is on bar, give that *strong* drive onto foo. + // The strength of an assignment is its own, and does not come + // from the strength contained in the r-value. + tri0 foo = bar; + + initial begin + d = 0; + #1 if (d !== bar) begin + $display("FAILED -- d=%b, bar=%b", d, bar); + $finish; + end + + if (d !== foo) begin + $display("FAILED -- d=%b, foo=%b", d, foo); + $finish; + end + + d = 1; + #1 if (d !== bar) begin + $display("FAILED -- d=%b, bar=%b", d, bar); + $finish; + end + + if (d !== foo) begin + $display("FAILED -- d=%b, foo=%b", d, foo); + $finish; + end + + d = 'bz; + #1 if (d !== bar) begin + $display("FAILED -- d=%b, bar=%b", d, bar); + $finish; + end + + if ('b0 !== foo) begin + $display("FAILED -- d=%b, foo=%b", d, foo); + $finish; + end + + + $display("PASSED"); + $finish; + end // initial begin + +endmodule // test diff --git a/ivtest/ivltests/pr1033.v b/ivtest/ivltests/pr1033.v new file mode 100644 index 000000000..2fcd4d9d7 --- /dev/null +++ b/ivtest/ivltests/pr1033.v @@ -0,0 +1,72 @@ +/* + * Test case showing the failure of the 'less than or equal' operator (note + * that the 'greather than or equal' comparison also fails) on two signed + * values. The 'foo' module defines inputs 'a' and 'b' as signed inputs, + * then performs a LTE comparison of those two values in order to select the + * smaller of the two as the result (via a mux). The generated output for + * this test (via the display call) for icarus and a well known commercial + * Verilog simulator are shown here. It is my belief that the commercial + * simulator results reflect the correct behavior for a simulator. + * Specifically, with signed numbers the value 32'h7fffffff represents the + * maximum positive value while 32'h80000000 represents the minimum negative + * value. Thus for Less Than or Equal comparison any negative value (ie + * 32'h80000000) should evaluate to less than any positive value + * (ie 32'h7fffffff). Note the difference in the last 4 comparisons between + * the icarus results and the commercial results. The commercial results show + * that the 32'h8000000? values are less than the 32'h7ffffff? values as is + * expected. + * + * icarus commercial simulator + * 7ffffff5 7ffffffa = 7ffffff5 # 7ffffff5 7ffffffa = 7ffffff5 + * 7ffffff6 7ffffffb = 7ffffff6 # 7ffffff6 7ffffffb = 7ffffff6 + * 7ffffff7 7ffffffc = 7ffffff7 # 7ffffff7 7ffffffc = 7ffffff7 + * 7ffffff8 7ffffffd = 7ffffff8 # 7ffffff8 7ffffffd = 7ffffff8 + * 7ffffff9 7ffffffe = 7ffffff9 # 7ffffff9 7ffffffe = 7ffffff9 + * 7ffffffa 7fffffff = 7ffffffa # 7ffffffa 7fffffff = 7ffffffa + * 7ffffffb 80000000 = 7ffffffb # 7ffffffb 80000000 = 80000000 + * 7ffffffc 80000001 = 7ffffffc # 7ffffffc 80000001 = 80000001 + * 7ffffffd 80000002 = 7ffffffd # 7ffffffd 80000002 = 80000002 + * 7ffffffe 80000003 = 7ffffffe # 7ffffffe 80000003 = 80000003 + * + * iverilog -version: + * Icarus Verilog version 0.7 ($Name: $) + * + * Compilation + * iverilog -o iverilog.out + * vvp iverilog.out + */ +module test (); + reg clk; + reg [31:0] a_dat; + reg [31:0] b_dat; + wire [31:0] result; + + initial begin + clk <= 0; + a_dat <= 32'h7fffFFF5; + b_dat <= 32'h7fffFFFA; + #500 $finish(0); + end + always #25 clk <= ~clk; + + always @(posedge clk) + begin + a_dat <= a_dat + 1; + b_dat <= b_dat + 1; + $display("%x %x = %x", a_dat, b_dat, result); + end + + foo foo_test(.a(a_dat), .b(b_dat), .RESULT(result)); + +endmodule // test + +module foo(a, b, RESULT); + input signed [31:0] a; + input signed [31:0] b; + output [31:0] RESULT; + wire lessThanEqualTo; + wire [31:0] mux; + assign lessThanEqualTo=a<=b; + assign mux=(lessThanEqualTo)?a:b; + assign RESULT=mux; +endmodule // foo diff --git a/ivtest/ivltests/pr1065.v b/ivtest/ivltests/pr1065.v new file mode 100644 index 000000000..26dfd778e --- /dev/null +++ b/ivtest/ivltests/pr1065.v @@ -0,0 +1,27 @@ +module test_file; + + reg [64:1] file_name; + initial begin + file_name = 64'h4242434442424344; + end + subtest1 subtest1(file_name); + +endmodule + +module subtest1(file_name); + + input [64:1] file_name; + wire [64:1] file_name; + integer outfile; + initial #0 begin + $display ("Execution started."); + $display ("%s",file_name); +// I don't know if the following line conforms to spec or not. + outfile = $fopen({"work/",file_name}); + $display ("Execution finished."); + $fdisplay (outfile, "Recorded data in %s",file_name); + $fclose (outfile); + $finish(0); + end + +endmodule diff --git a/ivtest/ivltests/pr1072.v b/ivtest/ivltests/pr1072.v new file mode 100644 index 000000000..d832ec6ea --- /dev/null +++ b/ivtest/ivltests/pr1072.v @@ -0,0 +1,32 @@ +/* + * This test program catches the essence of PR#1072 + */ +module main; + + parameter WIDTH = 4; + + wire [19:0] foo = { 1<> 16; +// PASS +//assign foo[31:16] = bar >> 16; + +initial + begin + bar = 32'ha5a5_3f3f; + #100; + $display("foo[31:16] = %x bar = %x",foo[31:16],bar); + //if(foo[31:16]==((bar & 32'hffffffff) >> 16)) + if(foo[31:16] === 16'ha5a5) + $display("PASS (%x)",foo[31:16]); + else + $display("FAIL (%x vs %x)",foo[31:16],((bar & 32'hffffffff) >> 16)); + $finish; + end +endmodule diff --git a/ivtest/ivltests/pr1353345.v b/ivtest/ivltests/pr1353345.v new file mode 100644 index 000000000..566cfc81c --- /dev/null +++ b/ivtest/ivltests/pr1353345.v @@ -0,0 +1,60 @@ +module main; + + parameter use_wid = 4; + + reg [use_wid-1:0] d; + wire [use_wid-1:0] q; + reg clk; + + B #(.wid(use_wid)) dut (.Q(q), .D(d), .C(clk)); + + initial begin + clk = 0; + d = 4'b0000; + + #1 clk = 1; + #1 clk = 0; + + if (q !== 4'b0000) begin + $display("FAILED -- d=%b, q=%b", d, q); + $finish; + end + + d = 4'b1111; + #1 clk = 1; + #1 clk = 0; + + if (q !== 4'b1111) begin + $display("FAILED -- d=%b, q=%b", d, q); + $finish; + end + + $display("PASSED"); + end + +endmodule // main + +/* + * although the wid paramter is default to 3 in this module, the point + * of this test is to have the instantiating module (main) give a + * different value and have that value properly handlued in all the + * situations of this module. + */ +module B + #(parameter wid = 3) + (output [wid-1:0] Q, + input [wid-1:0] D, + input C); + + // the override from main will cause this to be a width of 4. + prim U [wid-1:0] (Q, D, C); + //prim U [wid-1:0] (.Q(Q), .D(D), .C(C)); + +endmodule // B + +module prim(output reg Q, input D, C); + + always @(posedge C) + Q <= D; + +endmodule // prim diff --git a/ivtest/ivltests/pr1353345b.v b/ivtest/ivltests/pr1353345b.v new file mode 100644 index 000000000..26601b50b --- /dev/null +++ b/ivtest/ivltests/pr1353345b.v @@ -0,0 +1,61 @@ +module main; + + parameter use_wid = 4; + + reg [use_wid-1:0] d; + wire [use_wid-1:0] q; + reg clk; + + defparam dut.wid = use_wid; + B dut (.Q(q), .D(d), .C(clk)); + + initial begin + clk = 0; + d = 4'b0000; + + #1 clk = 1; + #1 clk = 0; + + if (q !== 4'b0000) begin + $display("FAILED -- d=%b, q=%b", d, q); + $finish; + end + + d = 4'b1111; + #1 clk = 1; + #1 clk = 0; + + if (q !== 4'b1111) begin + $display("FAILED -- d=%b, q=%b", d, q); + $finish; + end + + $display("PASSED"); + end + +endmodule // main + +/* + * although the wid paramter is default to 3 in this module, the point + * of this test is to have the instantiating module (main) give a + * different value and have that value properly handlued in all the + * situations of this module. + */ +module B + #(parameter wid = 3) + (output [wid-1:0] Q, + input [wid-1:0] D, + input C); + + // the override from main will cause this to be a width of 4. + prim U [wid-1:0] (Q, D, C); + //prim U [wid-1:0] (.Q(Q), .D(D), .C(C)); + +endmodule // B + +module prim(output reg Q, input D, C); + + always @(posedge C) + Q <= D; + +endmodule // prim diff --git a/ivtest/ivltests/pr136.v b/ivtest/ivltests/pr136.v new file mode 100644 index 000000000..20b0cd95e --- /dev/null +++ b/ivtest/ivltests/pr136.v @@ -0,0 +1,60 @@ +//**************************************************************************** +// +// MODULE : parameter_multiply_test +// +// DESCRIPTION : Test module to demonstrate parameter multiplication bug. +// +// AUTHOR : Brendan J Simon (brendan.simon@bigpond.com) +// +// DATE : Tuesday 6th January 2001. +// +// NOTES : It seems that Icarus Verilog 0.4 does not evaluate +// parameter multiplication properly. +// The code compiles OK, but gives a runtime error of: +// vpi_const.c:35: vpip_bits_to_dec_str: Assertion `nbits <= +// 8*sizeof(val)' failed. +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: multiply in parameter +//**************************************************************************** + +module parameter_multiply_test; + +parameter foo_size = 4 * 8; + +reg [31:0] testv; +initial begin + testv = foo_size; + if(testv !== 32) + begin + $write("foo_size = %d\n", testv); + $display("FAILED"); + end + else + begin + $write("foo_size = %d\n", testv); + $display("PASSED"); + end + $finish; +end + + +endmodule + +//**************************************************************************** +// EOF : parameter_multiply_test +//**************************************************************************** diff --git a/ivtest/ivltests/pr1367855.v b/ivtest/ivltests/pr1367855.v new file mode 100644 index 000000000..1e57e894c --- /dev/null +++ b/ivtest/ivltests/pr1367855.v @@ -0,0 +1,47 @@ +// test.v program starts here +// This program is based on iverilog report [ 1367855 ] vvp simulation error +module test(); + reg [3:0] S; + + mux m( .SEL(S) ); + + initial begin + S=3; #100; + S=2; #100; + $display("PASSED"); + $finish; + end +endmodule + +module mux(SEL); +input [3:0] SEL; +wire [3:0] SEL; +integer offset; + +always @(SEL) begin + offset = SEL[3] + SEL[0]*128 + SEL[2:1]*2; + $display("MUX: SEL=%d offset=%b", SEL, offset); + + case (SEL) + + 'bxxxx: begin + end + + 2: if (offset !== 'b00000000000000000000000000000010) begin + $display("FAILED"); + $finish; + end + + 3: if (offset !== 'b00000000000000000000000010000010) begin + $display("FAILED"); + $finish; + end + + default: begin + $display("FAILED -- SEL=%b", SEL); + $finish; + end + + endcase +end +endmodule diff --git a/ivtest/ivltests/pr1380261.v b/ivtest/ivltests/pr1380261.v new file mode 100644 index 000000000..6ec5a73d7 --- /dev/null +++ b/ivtest/ivltests/pr1380261.v @@ -0,0 +1,40 @@ +module bittest; + +reg signed [5:0] m; +reg signed [7:0] n; +reg signed [18:0] p; +reg signed [8:0] s; +reg b; +reg signed c; +reg d; + +always @(m, n, c) begin + p <= m * n; // m and n are signed, so do signed multiply + s <= m + b; // b is UNsigned, so do unsigned pad and add. + d <= c == 1; // c and the literal 1 are signed, so do signed compare. +end + +initial begin + #10; + m <= -25; + n <= 29; + b <= 1; + c <= 1; + #10; + $display("p=%d s=%d d=%d", p, s, d); + if (s !== 9'd40) begin + $display("FAILED -- s='b%b", s); + $finish; + end + if (p !== -19'd725) begin + $display("FAILED == p='b%b", p); + $finish; + end + if (d !== 0) begin + $display("FAILED == d='b%b", d); + $finish; + end + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr1388974.v b/ivtest/ivltests/pr1388974.v new file mode 100644 index 000000000..8d30e2cdc --- /dev/null +++ b/ivtest/ivltests/pr1388974.v @@ -0,0 +1,16 @@ +module main; + + initial begin + # 32 $display("PASSED"); + $finish; + end + + // This delay is 'h1_00000010. The idea here is if the delay is + // only treated as 32 bits anywhere in the processing, then the + // high bits are truncated, and it becomes 16, which is less then + // the 32 above and we fail. + initial begin + # 4294967312 $display("FAILED -- time=%d", $time); + $finish; + end +endmodule // main diff --git a/ivtest/ivltests/pr1403406-1.cf b/ivtest/ivltests/pr1403406-1.cf new file mode 100644 index 000000000..4e3798de9 --- /dev/null +++ b/ivtest/ivltests/pr1403406-1.cf @@ -0,0 +1 @@ ++timescale+1ns/1ns diff --git a/ivtest/ivltests/pr1403406-2.cf b/ivtest/ivltests/pr1403406-2.cf new file mode 100644 index 000000000..8ddeba8a0 --- /dev/null +++ b/ivtest/ivltests/pr1403406-2.cf @@ -0,0 +1 @@ ++timescale+1ns/1ps+ diff --git a/ivtest/ivltests/pr1403406.v b/ivtest/ivltests/pr1403406.v new file mode 100644 index 000000000..466e2675b --- /dev/null +++ b/ivtest/ivltests/pr1403406.v @@ -0,0 +1,20 @@ +// Use the default timescale. +module top; + initial begin + $printtimescale(top); + $printtimescale(other); + $printtimescale(other2); + end +endmodule + +`timescale 1ms/1ms + +// Use the given timescale. +module other; +endmodule + +`resetall + +// Use the default timescale. +module other2; +endmodule diff --git a/ivtest/ivltests/pr1403406a.v b/ivtest/ivltests/pr1403406a.v new file mode 100644 index 000000000..466e2675b --- /dev/null +++ b/ivtest/ivltests/pr1403406a.v @@ -0,0 +1,20 @@ +// Use the default timescale. +module top; + initial begin + $printtimescale(top); + $printtimescale(other); + $printtimescale(other2); + end +endmodule + +`timescale 1ms/1ms + +// Use the given timescale. +module other; +endmodule + +`resetall + +// Use the default timescale. +module other2; +endmodule diff --git a/ivtest/ivltests/pr1403406b.v b/ivtest/ivltests/pr1403406b.v new file mode 100644 index 000000000..466e2675b --- /dev/null +++ b/ivtest/ivltests/pr1403406b.v @@ -0,0 +1,20 @@ +// Use the default timescale. +module top; + initial begin + $printtimescale(top); + $printtimescale(other); + $printtimescale(other2); + end +endmodule + +`timescale 1ms/1ms + +// Use the given timescale. +module other; +endmodule + +`resetall + +// Use the default timescale. +module other2; +endmodule diff --git a/ivtest/ivltests/pr142.v b/ivtest/ivltests/pr142.v new file mode 100644 index 000000000..91295daef --- /dev/null +++ b/ivtest/ivltests/pr142.v @@ -0,0 +1,61 @@ +// +// Copyright (c) 2001 Ed Schwartz (schwartz@r11.ricoh.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Verify PR142 - Added something to print PASSED.. + +module testit; + + reg clk; + reg [2:0] cnt; + + always + begin + # 50 clk = ~clk; + end // always begin + + task idle; + input [15:0] waitcnt; + + begin: idletask + // begin + integer i; + for (i=0; i < waitcnt; i = i + 1) + begin + @ (posedge clk); + + end // for (i=0; i < waitcnt; i = i + 1) + + end + endtask // idle + + initial begin + clk = 0; + cnt = 0; + $display ("One"); + cnt = cnt + 1; + idle(3); + cnt = cnt + 1; + $display ("Two"); + if(cnt === 2) + $display("PASSED"); + else + $display("FAILED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/pr1421777.v b/ivtest/ivltests/pr1421777.v new file mode 100644 index 000000000..5f94b00b0 --- /dev/null +++ b/ivtest/ivltests/pr1421777.v @@ -0,0 +1,31 @@ +/* + * This is the essence of tracker id#1421777. The problem is the error + * message around the "... dut.tmp" expression. This probram won't + * compile while the reported bug still lives. + */ +module main; + + reg b; + wire a; + // The a.tmp is valid, but tricky because it is an implicit wire. + wire foo = dut.tmp; + X dut(a, b); + + initial begin + b = 0; + #1 $display("a=%b, tmp=%b", a, foo); + if (a !== foo) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end + +endmodule // main + +module X(output a, input b); + + not (tmp, b); + buf(a, tmp); + +endmodule // X diff --git a/ivtest/ivltests/pr1444055.v b/ivtest/ivltests/pr1444055.v new file mode 100644 index 000000000..b3e58e857 --- /dev/null +++ b/ivtest/ivltests/pr1444055.v @@ -0,0 +1,66 @@ +module bts ( z , a , e); + inout z ; wire z ; + input a ; wire a ; + input e ; wire e ; + + assign #4 z= ( (e==1'b1)? a : 1'bz ); +endmodule + +module test(); + reg [1:0] aa; + wire [1:0] zz; + reg [1:0] ee; + + bts sub1 (.z(zz[1]), .a(aa[1]), .e(ee[1])); + bts sub0 (.z(zz[0]), .a(aa[0]), .e(ee[0])); + + + initial begin +// $dumpvars; + ee=2'b00; + aa=2'b00; #100; + if (zz !== 2'bzz) begin + $display("FAILED -- (1) All disabled, expected HiZ, got %b", zz); + $finish; + end + aa=2'b11; #100; + if (zz !== 2'bzz) begin + $display("FAILED -- (2) All disabled, expected HiZ, got %b", zz); + $finish; + end + aa=2'b00; #100; + if (zz !== 2'bzz) begin + $display("FAILED -- (3) All disabled, expected HiZ, got %b", zz); + $finish; + end + aa=2'b11; #100; + if (zz !== 2'bzz) begin + $display("FAILED -- (4) All disabled, expected HiZ, got %b", zz); + $finish; + end + + ee=2'b11; + aa=2'b00; #100; + if (zz !== 2'b00) begin + $display("FAILED -- (5) All enabled, expected 00, got %b", zz); + $finish; + end + aa=2'b11; #100; + if (zz !== 2'b11) begin + $display("FAILED -- (6) All enabled, expected 11, got %b", zz); + $finish; + end + aa=2'b00; #100; + if (zz !== 2'b00) begin + $display("FAILED -- (7) All enabled, expected 00, got %b", zz); + $finish; + end + aa=2'b11; #100; + if (zz !== 2'b11) begin + $display("FAILED -- (8) All enabled, expected 11, got %b", zz); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1449749a.v b/ivtest/ivltests/pr1449749a.v new file mode 100644 index 000000000..a13163a39 --- /dev/null +++ b/ivtest/ivltests/pr1449749a.v @@ -0,0 +1,46 @@ +/* + * This tests the handling of signed/types parameters. This is a test + * of the complaints from pr 1449749. + */ +module main; + + parameter foo = -2; + parameter integer bar = -3; + parameter signed [5:0] bat = -7; + + initial begin + $display("foo=%d, bar=%d, tmp=%d", foo, bar, bat); + + if (foo >= 0) begin + $display("FAILED -- -2 > 0"); + $finish; + end + + if (foo != -2) begin + $display("FAILED"); + $finish; + end + + if (bar >= 0) begin + $display("FAILED -- -3 > 0"); + $finish; + end + + if (bar != -3) begin + $display("FAILED"); + $finish; + end + + if (bat >= 0) begin + $display("FAILED -- -7 > 0"); + $finish; + end + + if (bat != -7) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/pr1455873.v b/ivtest/ivltests/pr1455873.v new file mode 100644 index 000000000..77090d630 --- /dev/null +++ b/ivtest/ivltests/pr1455873.v @@ -0,0 +1,16 @@ +module main; + + reg [6:0] bar; + wire [31:0] foo = {{25{1'b0}}, bar}; + + initial begin + bar = 7'b1111111; + #1 if (foo !== 32'h00_00_00_7f) begin + $display("FAILED -- foo=%h", foo); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/pr1465769.v b/ivtest/ivltests/pr1465769.v new file mode 100644 index 000000000..26f7d197c --- /dev/null +++ b/ivtest/ivltests/pr1465769.v @@ -0,0 +1,20 @@ +module bug; + + reg [31:0] a; + integer i; + + initial + begin + i=4; + a=0; + a[i*4+:2] = 2'b11; + + $display("%h",a); + if (a !== 32'h00030000) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1467825.v b/ivtest/ivltests/pr1467825.v new file mode 100644 index 000000000..57e7430cd --- /dev/null +++ b/ivtest/ivltests/pr1467825.v @@ -0,0 +1,36 @@ +`celldefine +`suppress_faults +`enable_portfaults + + + + + + `timescale 1ns / 10ps + `delay_mode_path + + + + + +module test (Z, A, B); + + output Z; + input A; + input B; + + xor (Z, A, B); + + + + specify + + ifnone (A +=> Z) = (1.0,1.0); + + endspecify + + +endmodule +`disable_portfaults +`nosuppress_faults +`endcelldefine diff --git a/ivtest/ivltests/pr1474283.v b/ivtest/ivltests/pr1474283.v new file mode 100644 index 000000000..bf6388ced --- /dev/null +++ b/ivtest/ivltests/pr1474283.v @@ -0,0 +1,43 @@ +module test; + + reg [2:0] tmp1; + integer tmp2; + real tmp3; + + initial begin + t1(tmp1, 1); + if (tmp1 !== 2) begin + $display("FAILED -- tmp1=%b", tmp1); + $finish; + end + + t2(tmp2, 4); + if (tmp2 !== 6) begin + $display("FAILED == tmp2=%d", tmp2); + $finish; + end + + t3(tmp3, 0.5); + if (tmp3 != 2.0) begin + $display("FAILED -- tmp3=%f", tmp3); + $finish; + end + + $display("PASSED"); + end + + task t1(output [2:0] o, input [2:0] i); + begin + o = i + 1; + end + endtask // tt + + task t2(output integer o, input integer i); + o = i + 2; + endtask // t2 + + task t3(output real o, input real i); + o = i + 1.5; + endtask // t3 + +endmodule diff --git a/ivtest/ivltests/pr1474316.v b/ivtest/ivltests/pr1474316.v new file mode 100644 index 000000000..1fd81555e --- /dev/null +++ b/ivtest/ivltests/pr1474316.v @@ -0,0 +1,22 @@ +module test; +wire [3:0] a; +reg [1:0] b; +assign a[0+:2] = b; +assign a[3-:2] = b; + +initial begin + b = 2'b01; + #1 if (a !== 4'b0101) begin + $display("FAILED -- b=%b, a=%b", b, a); + $finish; + end + + b=2'b10; + #1 if (a !== 4'b1010) begin + $display("FAILED -- b=%b, a=%b", b, a); + $finish; + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/pr1474318.v b/ivtest/ivltests/pr1474318.v new file mode 100644 index 000000000..dd3f424c5 --- /dev/null +++ b/ivtest/ivltests/pr1474318.v @@ -0,0 +1,15 @@ +module test; + wire [5:0] a; + reg [3:0] b; + assign a[1:0] = {{2'b0},b}; + + initial begin + b = 4'b0110; + #1 if (a !== 6'bzzzz10) begin + $display("FAILED -- a=%b", a); + $finish; + end + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1476440.v b/ivtest/ivltests/pr1476440.v new file mode 100644 index 000000000..df085cfad --- /dev/null +++ b/ivtest/ivltests/pr1476440.v @@ -0,0 +1,28 @@ +`timescale 1ns/10ps + +module test(); +reg ck; +integer cnt; +real tval; + +initial begin +ck <= 0; +cnt <= 0; +tval <= 0.0; +end + + +always #2 ck <= !ck; + + +always @(posedge ck) begin +cnt <= cnt + 1; +tval <= $realtime; +$display ("tval = %g", tval); + +if (cnt >= 5) begin +$finish(0); +end +end + +endmodule // test diff --git a/ivtest/ivltests/pr1477190.v b/ivtest/ivltests/pr1477190.v new file mode 100644 index 000000000..8dec04580 --- /dev/null +++ b/ivtest/ivltests/pr1477190.v @@ -0,0 +1,41 @@ +module main; + + reg b, a; + + initial begin + b = 0; + a = 1; + #1 if (b !== 0) begin + $display("FAILED -- b starts out as %b", b); + $finish; + end + + force b = a; + #1 if (b !== 1) begin + $display("FAILED -- b=%b, a=%b", b, a); + $finish; + end + + a = 0; + #1 if (b !== 0) begin + $display("FAILED -- b=%b, a=%b", b, a); + $finish; + end + + a = 1; + #1 release b; + #1 a = 0; + #1 if (b !== 1) begin + $display("FAILED -- b=%b didnot hold value after release", b); + $finish; + end + + b = 0; + if (b !== 0) begin + $display("FAILED -- assign failed b=%b", b); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/pr1478121.v b/ivtest/ivltests/pr1478121.v new file mode 100644 index 000000000..79097c0f9 --- /dev/null +++ b/ivtest/ivltests/pr1478121.v @@ -0,0 +1,46 @@ +`begin_keywords "1364-2005" +module main; + + wire [1:0] di; + reg [1:0] do; + reg dir; + + wire [1:0] q; + + sub dut(.Q({q[0],q[1]}), .Di(di), .Do(do), .dir(dir)); + + initial begin + dir = 0; + do = 2'b10; + + #1 if (q !== 2'bzz) begin + $display("FAILED -- q=%b, dir=%b", q, dir); + $finish; + end + + dir = 1; + + #1 if (q !== 2'b01) begin + $display("FAILED -- q=%b, dir=%b, do=%b", q, dir, do); + $finish; + end + + if (di !== 2'b10) begin + $display("FAILED -- di=%b, dir=%b, do=%b", di, dir, do); + $finish; + end + + $display("PASSED"); + end + +endmodule // main + +module sub(inout [1:0]Q, + output[1:0]Di, + input [1:0]Do, + input dir); + + assign Di = Q; + assign Q = dir? Do : 2'bzz; +endmodule // sub +`end_keywords diff --git a/ivtest/ivltests/pr1478988.v b/ivtest/ivltests/pr1478988.v new file mode 100644 index 000000000..4da8d9b1e --- /dev/null +++ b/ivtest/ivltests/pr1478988.v @@ -0,0 +1,29 @@ +module main; + + reg [23:20] foo; + wire [3:0] test = {foo[22:20] == 3'd0, foo[22:20]}; + + initial begin + + foo = 4'b1_000; + #1 if (test !== 4'b1_000) begin + $display("FAILED -- foo=%b, test=%b", foo, test); + $finish; + end + + foo = 4'b0_111; + #1 if (test !== 4'b0_111) begin + $display("FAILED -- foo=%b, test=%b", foo, test); + $finish; + end + + foo = 4'b0_000; + #1 if (test !== 4'b1_000) begin + $display("FAILED -- foo=%b, test=%b", foo, test); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/pr1489568.v b/ivtest/ivltests/pr1489568.v new file mode 100644 index 000000000..646fac1d3 --- /dev/null +++ b/ivtest/ivltests/pr1489568.v @@ -0,0 +1,26 @@ +// pr1489568 + +module bug(); + + reg [15 : 0] in; + reg sel; + wire [31 : 0] result = { 16'd0, sel ? -in : in }; + + initial begin + in = 2; + sel = 0; + #1 if (result !== 32'h0000_0002) begin + $display("FAILED -- sel=%b, in=%h, result=%h", sel, in, result); + $finish; + end + + sel = 1; + #1 if (result !== 32'h0000_fffe) begin + $display("FAILED -- sel=%b, in=%h, result=%h", sel, in, result); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/pr1489570.v b/ivtest/ivltests/pr1489570.v new file mode 100644 index 000000000..a9856cb1d --- /dev/null +++ b/ivtest/ivltests/pr1489570.v @@ -0,0 +1,29 @@ +module bug(); + + reg [95:0] e; + reg [95:0] f; + initial e = 96'd10; + initial f = 96'hAAAAAAAAAAAAAAAAAAAAAAAA; + + wire [95:0] div = e / f ; + wire [95:0] mod = e % f ; // also fails + + initial begin + #1 $display("div=%h", div); + $display("mod=%h", mod); + + if (div !== 96'd0) begin + $display("FAILED"); + $finish; + end + + if (mod !== 96'd10) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/pr1491355.v b/ivtest/ivltests/pr1491355.v new file mode 100644 index 000000000..dac147320 --- /dev/null +++ b/ivtest/ivltests/pr1491355.v @@ -0,0 +1,27 @@ +module main; + + real rval; + + wire [63:0] wbits = $realtobits(rval); + reg [63:0] rbits; + + initial begin + rval = 1.5; + rbits = $realtobits(rval); + + #1 /* Let the wbits value propagate */ ; + + if (rbits !== 64'h3ff80000_00000000) begin + $display("FAILED -- rbits=%h", rbits); + $finish; + end + + if (wbits !== rbits) begin + $display("FAILED -- rval=%f, rbits=%h, wbits=%h", rval, rbits, wbits); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/pr1492075.v b/ivtest/ivltests/pr1492075.v new file mode 100644 index 000000000..e40599ae1 --- /dev/null +++ b/ivtest/ivltests/pr1492075.v @@ -0,0 +1,41 @@ +// -*- Mode: Verilog -*- +// Filename : cnr_tb.v +// Description : single row corner bender testbench +// Author : +// Created On : Thu Mar 23 16:23:01 2006 +// Last Modified By: $Id: pr1492075.v,v 1.1 2006/06/02 05:01:52 stevewilliams Exp $ +// Last Modified On: . +// Status : Unknown, Use with caution! + +`timescale 1ns / 10ps + +module cnr_tb (); + + reg clkb; + reg clocken; + integer cntb; + + // clock generation clkb + always @ (posedge clocken) + begin + for (cntb=0; cntb<5; cntb=cntb+1) + begin + #(10 + -2) clkb = 1; + #(10 - -2) clkb = 0; + end + end + + // + initial + begin + $monitor("clkb=%b at %t", clkb, $time); + clkb = 1'b0; + clocken = 0; + #1 clocken = 1; + #(10*20) clocken = 0; + + #100; + $finish(0); + end + +endmodule // cnr_tb diff --git a/ivtest/ivltests/pr1494799.v b/ivtest/ivltests/pr1494799.v new file mode 100644 index 000000000..9175567da --- /dev/null +++ b/ivtest/ivltests/pr1494799.v @@ -0,0 +1,34 @@ + module math(a, b, c, z); + input signed [19:0] a, b; + input signed [24:0] c; + output signed [24:0] z; + + assign z = a + b + c - (c >>> 1); + endmodule + + module test(); + reg signed [19:0] a, b; + reg signed [24:0] z, c; + + wire signed [24:0] y; + + wire signed [24:0] w = a + b + c - (c >>> 1); + + math m(a,b,c,y); + + initial begin + a = -5; + $display("a = %x %d", a, a); + b = 0; + $display("b = %x %d", b, b); + c = 8; + $display("c = %x %d", c, c); + z = a + b + c - (c >>> 1); + #1 /* delay for things to settle. */; + $display("z = %x, %d, %b", z, z, z); + $display("y = %x, %d, %b", y, y, y); + $display("w = %x, %d, %b", w, w, w); + $display("%b %b %b %b", $is_signed(a), + $is_signed(b), $is_signed(c), $is_signed(c >>> 1)); + end + endmodule diff --git a/ivtest/ivltests/pr1508882.v b/ivtest/ivltests/pr1508882.v new file mode 100644 index 000000000..ba0180cb7 --- /dev/null +++ b/ivtest/ivltests/pr1508882.v @@ -0,0 +1,35 @@ +/* + * This test is based on pr1508882. The output from the test module + * should produce a 5 bit result, and the widths of the vectors are + * correct for that assumption. But if an implicit part select is + * mitted in the assign out=tmp, then the vector widths can break. + */ +module main; + + reg [5:0] a, b; + wire [4:0] sum; + + test dut (.out(sum), .a(a), .b(b)); + + wire [5:0] padded = {1'b0, sum}; + + initial begin + a = 1; + b = 7; + + #1 if (padded !== (a+b)) begin + $display("FAILED -- sum=%0d, a=%0d, b=%0d", sum, a, b); + $finish; + end + + $display("PASSED"); + end + +endmodule // main + +module test (output [4:0] out, input [5:0] a, b); + + wire [5:0] tmp = a + b; + assign out = tmp; + +endmodule // test diff --git a/ivtest/ivltests/pr1510724.v b/ivtest/ivltests/pr1510724.v new file mode 100644 index 000000000..c73bee8d7 --- /dev/null +++ b/ivtest/ivltests/pr1510724.v @@ -0,0 +1,42 @@ +/* + * This test is really about the defparam working so it just does a + * simple test of the logic functionality (eveything in manyNands + * is a two bit bus). + */ + +module top; + parameter count = 2; + + reg pass = 1'b1; + wire [count-1:0] y; + reg [count-1:0] a, b; + + manyNands nandArray(y, a, b); + defparam nandArray.count = count; + + initial begin + a = 2'b00; b = 2'b00; + #1; + if (y !== 2'b11) begin + $display("FAILED: ~(2'b00 & 2'b00) should be 2'b11, got %b", y); + pass = 1'b0; + end + + a = 2'b11; b = 2'b11; + #1; + if (y !== 2'b00) begin + $display("FAILED: ~(2'b11 & 2'b11) should be 2'b00, got %b", y); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule + +module manyNands(y, a, b); + parameter count = 3; + output [count-1:0] y; + input [count-1:0] a, b; + + assign y = ~(a & b); +endmodule diff --git a/ivtest/ivltests/pr1515168.v b/ivtest/ivltests/pr1515168.v new file mode 100644 index 000000000..89943047d --- /dev/null +++ b/ivtest/ivltests/pr1515168.v @@ -0,0 +1,27 @@ +module extension_bug(); + +reg x; +reg [3:0] a, b; + +initial begin + x = 1'b1; + + a = ~1'b1; + b = ~x; + + $display("a = %b", a); + if (a !== 4'b1110) begin + $display("FAILED"); + $finish; + end + $display("b = %b", b); + if (b !== 4'b1110) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; +end + +endmodule diff --git a/ivtest/ivltests/pr1520314.v b/ivtest/ivltests/pr1520314.v new file mode 100644 index 000000000..38b0b3068 --- /dev/null +++ b/ivtest/ivltests/pr1520314.v @@ -0,0 +1,23 @@ +module kk_timing (A, B, C, D, E, F); + + input A, B, D, E, F; + output C; + wire A, B, D, E, F; + reg C; + wire [1:0] BL; + wire [1:0] BL_X; + + assign BL[0] = E; + assign BL_X[0] = F; + wire BL_0 = BL[0] ; + wire BL_X_0 = BL_X[0]; + + specify + $setuphold(posedge A &&& B, BL[0], 0, 0, C,,,D, BL_X[0]); // line 14 compile fail iverilog_20060618 + $setuphold(posedge A &&& B, BL_0 , 0, 0, C,,,D, BL_X[0]); // line 15 compile fail iverilog_20060618 + $setuphold(posedge A &&& B, BL[0], 0, 0, C,,,D, BL_X_0 ); // line 16 compile pass iverilog_20060618 + $setuphold(posedge A &&& B, BL_0 , 0, 0, C,,,D, BL_X_0 ); // line 17 compile pass iverilog_20060618 + endspecify + + + endmodule diff --git a/ivtest/ivltests/pr1522570.v b/ivtest/ivltests/pr1522570.v new file mode 100644 index 000000000..c9c826416 --- /dev/null +++ b/ivtest/ivltests/pr1522570.v @@ -0,0 +1,24 @@ +module main; + + reg signed [5:0] GAIN = 2; + reg signed [23:0] iir = -8; + + wire signed [23:0] iir_s1 = iir >>> 2; + wire signed [23:0] iir_s2 = iir >>> GAIN; + + initial begin + #1 /* Wait for inputs values to settle. */ ; + + if (iir_s1 !== -24'sd2) begin + $display("FAILED -- s1 = %d (%h)", iir_s1, iir_s1); + $finish; + end + + if (iir_s2 !== -24'sd2) begin + $display("FAILED -- s2 = %d (%h)", iir_s2, iir_s2); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/pr1528093.v b/ivtest/ivltests/pr1528093.v new file mode 100644 index 000000000..b7ca563eb --- /dev/null +++ b/ivtest/ivltests/pr1528093.v @@ -0,0 +1,21 @@ +module main; + + real x; + real y; + + real bar; + + initial begin + x = 5.0; + y = 10.0; + bar = x % y; + $display("bar=%f", bar); + + if (bar != 5.0) begin + $display("FAILED -- x %% y --> %f (s.b. 5.0)", bar); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/pr1530426.v b/ivtest/ivltests/pr1530426.v new file mode 100644 index 000000000..b53fdca2c --- /dev/null +++ b/ivtest/ivltests/pr1530426.v @@ -0,0 +1,19 @@ +module main; + + parameter N = 2**4; + + initial begin + if (N != 16) begin + $display("FAILED -- N = %u (%h)", N, N); + $finish; + end + + if (2**4 != 16) begin + $display("FAILED -- 2**16 = %u", 2**16); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/pr1561597.v b/ivtest/ivltests/pr1561597.v new file mode 100644 index 000000000..02e832a35 --- /dev/null +++ b/ivtest/ivltests/pr1561597.v @@ -0,0 +1,11 @@ +module evidence; + reg [4:0] y = 5'h10; + initial begin + $display(y[4], y[1<<2]); + if (y[1<<2] !== 1'b1) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1565544.v b/ivtest/ivltests/pr1565544.v new file mode 100644 index 000000000..55e11beb6 --- /dev/null +++ b/ivtest/ivltests/pr1565544.v @@ -0,0 +1,24 @@ +module test (); + + wire [2:0] d [0:2]; + reg [2:0] src[0:2]; + + genvar i; + for (i = 0 ; i < 3 ; i = i+1) + assign d[i] = src[i]; + + integer idx; + initial begin + for (idx = 0 ; idx < 3 ; idx = idx+1) + src[idx] = idx; + + #1 for (idx = 0 ; idx < 3 ; idx = idx+1) + if (d[idx] !== idx) begin + $display("FAILED -- d[%0d] = %b", idx, d[idx]); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/pr1565699b.v b/ivtest/ivltests/pr1565699b.v new file mode 100644 index 000000000..8e39de24b --- /dev/null +++ b/ivtest/ivltests/pr1565699b.v @@ -0,0 +1,37 @@ +module test (); + + reg [2:0] in; + wire Oand, Oor; + + dut #(.is_and(1)) dand (.O(Oand), .A(in[1]), .B(in[0])); + dut #(.is_and(0)) dor (.O(Oor ), .A(in[1]), .B(in[0])); + + initial begin + for (in = 0 ; in < 4 ; in = in+1) begin + #1 /* settle time. */ ; + if (Oand !== &in[1:0]) begin + $display("FAILED -- in=%b, Oand=%b", in, Oand); + $finish; + end + if (Oor !== |in[1:0]) begin + $display("FAILED -- in=%b, Oor=%b", in, Oor); + $finish; + end + end // for (in = 0 ; in < 4 ; in = in+1) + $display("PASSED"); + end + +endmodule + +module dut (output O, input A, input B); + + parameter is_and = 1; + + generate + if (is_and) + and g(O, A, B); + else + or g(O, A, B); + endgenerate + +endmodule // dut diff --git a/ivtest/ivltests/pr1570451.v b/ivtest/ivltests/pr1570451.v new file mode 100644 index 000000000..68101c02c --- /dev/null +++ b/ivtest/ivltests/pr1570451.v @@ -0,0 +1,47 @@ +module test; + + reg [1:0] bus; + reg [1:0] skewed_bus; + + integer delay0; initial delay0 = 5; + integer delay1; initial delay1 = 10; + + /* attempt to model skew across the bus using transport delays */ + + always @( bus[0] ) + begin + skewed_bus[0] <= #delay0 bus[0]; + end + + always @( bus[1] ) + begin + skewed_bus[1] <= #delay1 bus[1]; + end + + initial begin + #1 bus = 2'b00; + #11 if (skewed_bus !== 2'b00) begin + $display("FAILED -- setup failed."); + $finish; + end + + bus = 2'b11; + + #4 if (skewed_bus !== 2'b00) begin + $display("FAILED -- changed far too soon"); + $finish; + end + + #2 if (skewed_bus !== 2'b01) begin + $display("FAILED -- partial change not right."); + $finish; + end + + #5 if (skewed_bus !== 2'b11) begin + $display("FAILED -- final change not right"); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1570451b.v b/ivtest/ivltests/pr1570451b.v new file mode 100644 index 000000000..5315d4c22 --- /dev/null +++ b/ivtest/ivltests/pr1570451b.v @@ -0,0 +1,1213 @@ +module test; + + reg [7:0] bus; + reg [7:0] skewed_bus; + + integer delay0; initial delay0 = 4; + integer delay1; initial delay1 = 8; + integer delay2; initial delay2 = 12; + integer delay3; initial delay3 = 16; + integer delay4; initial delay4 = 20; + integer delay5; initial delay5 = 24; + integer delay6; initial delay6 = 28; + integer delay7; initial delay7 = 32; + + /* model skew across the bus using transport delays */ + + always @( bus[0] ) + begin + skewed_bus[0] <= #delay0 bus[0]; + end + + always @( bus[1] ) + begin + skewed_bus[1] <= #delay1 bus[1]; + end + + always @( bus[2] ) + begin + skewed_bus[2] <= #delay2 bus[2]; + end + + always @( bus[3] ) + begin + skewed_bus[3] <= #delay3 bus[3]; + end + + always @( bus[4] ) + begin + skewed_bus[4] <= #delay4 bus[4]; + end + + always @( bus[5] ) + begin + skewed_bus[5] <= #delay5 bus[5]; + end + + always @( bus[6] ) + begin + skewed_bus[6] <= #delay6 bus[6]; + end + + always @( bus[7] ) + begin + skewed_bus[7] <= #delay7 bus[7]; + end + + + initial + begin + bus = {8{1'b0}}; + #4; + bus = 8'b00100100; + #4; + bus = 8'b10000001; + #4; + bus = 8'b00001001; + #4; + bus = 8'b01100011; + #4; + bus = 8'b00001101; + #4; + bus = 8'b10001101; + #4; + bus = 8'b01100101; + #4; + bus = 8'b00010010; + #4; + bus = 8'b00000001; + #4; + bus = 8'b00001101; + #4; + bus = 8'b01110110; + #4; + bus = 8'b00111101; + #4; + bus = 8'b11101101; + #4; + bus = 8'b10001100; + #4; + bus = 8'b11111001; + #4; + bus = 8'b11000110; + #4; + bus = 8'b11000101; + #4; + bus = 8'b10101010; + #4; + bus = 8'b11100101; + #4; + bus = 8'b01110111; + #4; + bus = 8'b00010010; + #4; + bus = 8'b10001111; + #4; + bus = 8'b11110010; + #4; + bus = 8'b11001110; + #4; + bus = 8'b11101000; + #4; + bus = 8'b11000101; + #4; + bus = 8'b01011100; + #4; + bus = 8'b10111101; + #4; + bus = 8'b00101101; + #4; + bus = 8'b01100101; + #4; + bus = 8'b01100011; + #4; + bus = 8'b00001010; + #4; + bus = 8'b10000000; + #4; + bus = 8'b00100000; + #4; + bus = 8'b10101010; + #4; + bus = 8'b10011101; + #4; + bus = 8'b10010110; + #4; + bus = 8'b00010011; + #4; + bus = 8'b00001101; + #4; + bus = 8'b01010011; + #4; + bus = 8'b01101011; + #4; + bus = 8'b11010101; + #4; + bus = 8'b00000010; + #4; + bus = 8'b10101110; + #4; + bus = 8'b00011101; + #4; + bus = 8'b11001111; + #4; + bus = 8'b00100011; + #4; + bus = 8'b00001010; + #4; + bus = 8'b11001010; + #4; + bus = 8'b00111100; + #4; + bus = 8'b11110010; + #4; + bus = 8'b10001010; + #4; + bus = 8'b01000001; + #4; + bus = 8'b11011000; + #4; + bus = 8'b01111000; + #4; + bus = 8'b10001001; + #4; + bus = 8'b11101011; + #4; + bus = 8'b10110110; + #4; + bus = 8'b11000110; + #4; + bus = 8'b10101110; + #4; + bus = 8'b10111100; + #4; + bus = 8'b00101010; + #4; + bus = 8'b00001011; + #4; + bus = 8'b01110001; + #4; + bus = 8'b10000101; + #4; + bus = 8'b01001111; + #4; + bus = 8'b00111011; + #4; + bus = 8'b00111010; + #4; + bus = 8'b01111110; + #4; + bus = 8'b00010101; + #4; + bus = 8'b11110001; + #4; + bus = 8'b11011001; + #4; + bus = 8'b01100010; + #4; + bus = 8'b01001100; + #4; + bus = 8'b10011111; + #4; + bus = 8'b10001111; + #4; + bus = 8'b11111000; + #4; + bus = 8'b10110111; + #4; + bus = 8'b10011111; + #4; + bus = 8'b01011100; + #4; + bus = 8'b01011011; + #4; + bus = 8'b10001001; + #4; + bus = 8'b01001001; + #4; + bus = 8'b11010000; + #4; + bus = 8'b11010111; + #4; + bus = 8'b01010001; + #4; + bus = 8'b10010110; + #4; + bus = 8'b00001100; + #4; + bus = 8'b11000010; + #4; + bus = 8'b11001000; + #4; + bus = 8'b01110111; + #4; + bus = 8'b00111101; + #4; + bus = 8'b00010010; + #4; + bus = 8'b01111110; + #4; + bus = 8'b01101101; + #4; + bus = 8'b00111001; + #4; + bus = 8'b00011111; + #4; + bus = 8'b11010011; + #4; + bus = 8'b10000101; + #4; + bus = 8'b01111000; + #4; + bus = 8'b01011011; + #4; + bus = 8'b01001001; + #4; + bus = 8'b00111111; + #4; + bus = 8'b00101010; + #4; + bus = 8'b01011000; + #4; + bus = 8'b10000110; + #4; + bus = 8'b10001110; + #4; + bus = 8'b10011100; + #4; + bus = 8'b11111010; + #4; + bus = 8'b00100110; + #4; + bus = 8'b01110011; + #4; + bus = 8'b10100011; + #4; + bus = 8'b00101111; + #4; + bus = 8'b10110011; + #4; + bus = 8'b01011111; + #4; + bus = 8'b01000100; + #4; + bus = 8'b11110111; + #4; + bus = 8'b11001011; + #4; + bus = 8'b11100110; + #4; + bus = 8'b01011010; + #4; + bus = 8'b00101001; + #4; + bus = 8'b11101101; + #4; + bus = 8'b11011010; + #4; + bus = 8'b01100101; + #4; + bus = 8'b10110101; + #4; + bus = 8'b11011111; + #4; + bus = 8'b01111001; + #4; + bus = 8'b01000100; + end + + initial + begin + #2; + if (skewed_bus !== 8'bxxxxxxxx) + begin + $write("FAILED -- expected xxxxxxxx "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'bxxxxxxx0) + begin + $write("FAILED -- expected xxxxxxx0 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'bxxxxxx00) + begin + $write("FAILED -- expected xxxxxx00 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'bxxxxx001) + begin + $write("FAILED -- expected xxxxx001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'bxxxx0101) + begin + $write("FAILED -- expected xxxx0101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'bxxx00001) + begin + $write("FAILED -- expected xxx00001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'bxx000011) + begin + $write("FAILED -- expected xx000011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'bx0101001) + begin + $write("FAILED -- expected x0101001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00000101) + begin + $write("FAILED -- expected 00000101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00001100) + begin + $write("FAILED -- expected 00001100 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10101111) + begin + $write("FAILED -- expected 10101111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01000001) + begin + $write("FAILED -- expected 01000001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00000000) + begin + $write("FAILED -- expected 00000000 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00110111) + begin + $write("FAILED -- expected 00110111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11001101) + begin + $write("FAILED -- expected 11001101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00000100) + begin + $write("FAILED -- expected 00000100 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00011101) + begin + $write("FAILED -- expected 00011101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00111100) + begin + $write("FAILED -- expected 00111100 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01101011) + begin + $write("FAILED -- expected 01101011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00101100) + begin + $write("FAILED -- expected 00101100 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01010111) + begin + $write("FAILED -- expected 01010111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10100001) + begin + $write("FAILED -- expected 10100001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11001110) + begin + $write("FAILED -- expected 11001110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11000111) + begin + $write("FAILED -- expected 11000111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11100010) + begin + $write("FAILED -- expected 11100010 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10110110) + begin + $write("FAILED -- expected 10110110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11111010) + begin + $write("FAILED -- expected 11111010 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11000101) + begin + $write("FAILED -- expected 11000101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00011000) + begin + $write("FAILED -- expected 00011000 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00101101) + begin + $write("FAILED -- expected 00101101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11000101) + begin + $write("FAILED -- expected 11000101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11101101) + begin + $write("FAILED -- expected 11101101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11011101) + begin + $write("FAILED -- expected 11011101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11011110) + begin + $write("FAILED -- expected 11011110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11100010) + begin + $write("FAILED -- expected 11100010 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00100000) + begin + $write("FAILED -- expected 00100000 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10101000) + begin + $write("FAILED -- expected 10101000 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01100011) + begin + $write("FAILED -- expected 01100011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01000000) + begin + $write("FAILED -- expected 01000000 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00001111) + begin + $write("FAILED -- expected 00001111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00101111) + begin + $write("FAILED -- expected 00101111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10110001) + begin + $write("FAILED -- expected 10110001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00010111) + begin + $write("FAILED -- expected 00010111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10011011) + begin + $write("FAILED -- expected 10011011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10000000) + begin + $write("FAILED -- expected 10000000 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10011110) + begin + $write("FAILED -- expected 10011110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00000011) + begin + $write("FAILED -- expected 00000011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01110101) + begin + $write("FAILED -- expected 01110101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01001111) + begin + $write("FAILED -- expected 01001111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01001110) + begin + $write("FAILED -- expected 01001110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10111010) + begin + $write("FAILED -- expected 10111010 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00000010) + begin + $write("FAILED -- expected 00000010 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10001000) + begin + $write("FAILED -- expected 10001000 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01101110) + begin + $write("FAILED -- expected 01101110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10001011) + begin + $write("FAILED -- expected 10001011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00010000) + begin + $write("FAILED -- expected 00010000 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01111000) + begin + $write("FAILED -- expected 01111000 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10100001) + begin + $write("FAILED -- expected 10100001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01001001) + begin + $write("FAILED -- expected 01001001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10011010) + begin + $write("FAILED -- expected 10011010 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11011010) + begin + $write("FAILED -- expected 11011010 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01101110) + begin + $write("FAILED -- expected 01101110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11000110) + begin + $write("FAILED -- expected 11000110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00110100) + begin + $write("FAILED -- expected 00110100 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11101111) + begin + $write("FAILED -- expected 11101111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10001011) + begin + $write("FAILED -- expected 10001011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11111001) + begin + $write("FAILED -- expected 11111001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10101001) + begin + $write("FAILED -- expected 10101001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10100111) + begin + $write("FAILED -- expected 10100111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10010110) + begin + $write("FAILED -- expected 10010110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00101010) + begin + $write("FAILED -- expected 00101010 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01001011) + begin + $write("FAILED -- expected 01001011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00011101) + begin + $write("FAILED -- expected 00011101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11111101) + begin + $write("FAILED -- expected 11111101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00110000) + begin + $write("FAILED -- expected 00110000 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00110010) + begin + $write("FAILED -- expected 00110010 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01011001) + begin + $write("FAILED -- expected 01011001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00110111) + begin + $write("FAILED -- expected 00110111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01001110) + begin + $write("FAILED -- expected 01001110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11101101) + begin + $write("FAILED -- expected 11101101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11011011) + begin + $write("FAILED -- expected 11011011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01001110) + begin + $write("FAILED -- expected 01001110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00010101) + begin + $write("FAILED -- expected 00010101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10111111) + begin + $write("FAILED -- expected 10111111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11111001) + begin + $write("FAILED -- expected 11111001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10011000) + begin + $write("FAILED -- expected 10011000 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10011001) + begin + $write("FAILED -- expected 10011001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11001011) + begin + $write("FAILED -- expected 11001011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01000100) + begin + $write("FAILED -- expected 01000100 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00010010) + begin + $write("FAILED -- expected 00010010 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11010100) + begin + $write("FAILED -- expected 11010100 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01010110) + begin + $write("FAILED -- expected 01010110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11011001) + begin + $write("FAILED -- expected 11011001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11000011) + begin + $write("FAILED -- expected 11000011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00001100) + begin + $write("FAILED -- expected 00001100 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10000110) + begin + $write("FAILED -- expected 10000110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01011011) + begin + $write("FAILED -- expected 01011011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11110101) + begin + $write("FAILED -- expected 11110101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11111101) + begin + $write("FAILED -- expected 11111101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00011011) + begin + $write("FAILED -- expected 00011011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00101111) + begin + $write("FAILED -- expected 00101111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01111000) + begin + $write("FAILED -- expected 01111000 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01110101) + begin + $write("FAILED -- expected 01110101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00010011) + begin + $write("FAILED -- expected 00010011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00001001) + begin + $write("FAILED -- expected 00001001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01011010) + begin + $write("FAILED -- expected 01011010 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10111110) + begin + $write("FAILED -- expected 10111110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11001000) + begin + $write("FAILED -- expected 11001000 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01011010) + begin + $write("FAILED -- expected 01011010 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01101110) + begin + $write("FAILED -- expected 01101110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00110100) + begin + $write("FAILED -- expected 00110100 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00001110) + begin + $write("FAILED -- expected 00001110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01001011) + begin + $write("FAILED -- expected 01001011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00011111) + begin + $write("FAILED -- expected 00011111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10010011) + begin + $write("FAILED -- expected 10010011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10100011) + begin + $write("FAILED -- expected 10100011 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11110111) + begin + $write("FAILED -- expected 11110111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10101010) + begin + $write("FAILED -- expected 10101010 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01100101) + begin + $write("FAILED -- expected 01100101 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00111111) + begin + $write("FAILED -- expected 00111111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b10110110) + begin + $write("FAILED -- expected 10110110 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b00000010) + begin + $write("FAILED -- expected 00000010 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11011111) + begin + $write("FAILED -- expected 11011111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01100001) + begin + $write("FAILED -- expected 01100001 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b01001000) + begin + $write("FAILED -- expected 01001000 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11111111) + begin + $write("FAILED -- expected 11111111 "); + $display("received %b ", skewed_bus); + $finish; + end + #4; + if (skewed_bus !== 8'b11001001) + begin + $write("FAILED -- expected 11001001 "); + $display("received %b ", skewed_bus); + $finish; + end + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1570635.v b/ivtest/ivltests/pr1570635.v new file mode 100644 index 000000000..69268b1a0 --- /dev/null +++ b/ivtest/ivltests/pr1570635.v @@ -0,0 +1,72 @@ +module test; + + reg [2:0] ptr; + reg [2:0] size; + reg [2:0] ptr_nxt; + + always @* + begin + ptr_nxt = ptr; + + if ( ptr + size > 3 ) + begin + ptr_nxt = ptr + size - 3; + end + else + begin + ptr_nxt = 0; + end + end + + initial + begin + #1; + + ptr = 2; + size = 2; + #1 + $write("ptr_nxt=%0d ptr=%0d size=%0d", ptr_nxt, ptr, size); + if ( ptr_nxt == 1 ) + begin + $display(" OK"); + end + else + begin + $display(" ERROR"); + $finish; + end + + ptr = 3; + size = 4; + #1 + $write("ptr_nxt=%0d ptr=%0d size=%0d", ptr_nxt, ptr, size); + if ( ptr_nxt == 4 ) + begin + $display(" OK"); + end + else + begin + $display(" ERROR"); + $finish; + end + + ptr = 3; + size = 5; + #1 + $write("ptr_nxt=%0d ptr=%0d size=%0d", ptr_nxt, ptr, size); + if ( ptr_nxt == 5 ) + begin + $display(" OK"); + end + else + begin + $display(" ERROR"); + $finish; + end + + $display("PASSED"); + $finish; + + end + +endmodule diff --git a/ivtest/ivltests/pr1570635b.v b/ivtest/ivltests/pr1570635b.v new file mode 100644 index 000000000..bb56c88ec --- /dev/null +++ b/ivtest/ivltests/pr1570635b.v @@ -0,0 +1,25 @@ +module test; + +// This example was adapted from: + +// DRAFT STANDARD VERILOG HARDWARE DESCRIPTION LANGUAGE +// IEEE P1364-2005/D3, 1/7/04 +// Section 4.4.2 "An example of an expression bit-length problem" +// pg. 59 + +reg [15:0] a, b, answer; // 16-bit regs + +initial + begin + a = 16'h8000; + b = 16'h8000; + answer = (a + b + 0) >> 1; //will work correctly + if ( answer != 16'h8000 ) + begin + $display("FAILED -- expected 16'h8000 received 16'h%h", answer); + $finish; + end + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1574175.v b/ivtest/ivltests/pr1574175.v new file mode 100644 index 000000000..5226a5925 --- /dev/null +++ b/ivtest/ivltests/pr1574175.v @@ -0,0 +1,13 @@ +module top; + integer correct, incorrect; + reg [5:0] bits; + + initial begin + bits = 32; + incorrect = -180 + bits*(360.0/63.0); + correct = bits*(360.0/63.0) - 180; + $display("Both of these should be the same (3): %3d, %3d", incorrect, + correct); + $finish(0); + end +endmodule diff --git a/ivtest/ivltests/pr1581580.v b/ivtest/ivltests/pr1581580.v new file mode 100644 index 000000000..f6098c09a --- /dev/null +++ b/ivtest/ivltests/pr1581580.v @@ -0,0 +1,44 @@ +module test; + + parameter SIZE = 2; + + reg [SIZE-1:0] d ; // data in + reg c ; // latch control + wire [SIZE-1:0] q ; // output + + unit_latch u_lat[SIZE-1:0] (.Q(q), .G(c), .D(d)); + + initial begin + d = 0; + c = 1; + #1 if (q !== 2'b00) begin + $display("FAILED -- Initial load failed."); + $finish; + end + + d = 2'b01; + + #1 if (q !== 2'b01) begin + $display("FAILED -- Latch follow failed."); + $finish; + end + + c = 0; + #1 d = 2'b10; + #1 if (q !== 2'b01) begin + $display("FAILED -- Latch hold failed."); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule + +module unit_latch(output reg Q, input wire D, input wire G); + + always @* + if (G) Q = D; + +endmodule // unit_latch diff --git a/ivtest/ivltests/pr1587634.v b/ivtest/ivltests/pr1587634.v new file mode 100644 index 000000000..89f29768c --- /dev/null +++ b/ivtest/ivltests/pr1587634.v @@ -0,0 +1,32 @@ +// +// Test the specify block (pr1587634) +// + +`timescale 1 ns / 1 ps + +/* +module top(); + reg in; + initial begin + in = 0; + #10 in = 1; + end + + inv1 g1 (out, in); +endmodule +*/ + +module inv1 (z, a); + output z; + input a; + + not g1(z, a); + + specify + specparam tpd_a_z_lh = 0.400; + specparam tpd_a_z_hl = 0.300:0.400:0.500; + + (a -=> z) = (tpd_a_z_lh, tpd_a_z_hl); + + endspecify +endmodule diff --git a/ivtest/ivltests/pr1587669.v b/ivtest/ivltests/pr1587669.v new file mode 100644 index 000000000..c5a438f36 --- /dev/null +++ b/ivtest/ivltests/pr1587669.v @@ -0,0 +1,53 @@ +`timescale 1ns/1ps + +module fail (); + reg pz; + reg [4:0] p; + wire em, net0102; + + initial begin + p = 0; + pz = 0; + + $monitor("time=%0t", $time,": em=", em, ", pz=", pz, ", p=%b", p); + + while (p < 5'b11111) + #10 p = p+1; + + #1; // avoid final race + $finish(0); + end + + nr1 I1 (em, net0102, pz, p[0]); + nr2 I2 (net0102, p[1], p[2], p[3], p[4]); +endmodule + +module nr1 (zn, a1, a2, a3); + output zn; + input a1, a2, a3; + + not G1(N1, a1); + not G2(zn, N2); + or G3(N2, N1, a2, a3); + + specify + (a1 +=> zn) = (0.500, 0.500); + (a2 -=> zn) = (0.500, 0.500); + (a3 -=> zn) = (0.500, 0.500); + endspecify +endmodule + +module nr2 (zn, a1, a2, a3, a4); + output zn; + input a1, a2, a3, a4; + + or G1(N1, a1, a2, a3, a4); + not G2(zn, N1); + + specify + (a1 -=> zn) = (0.500, 0.500); + (a2 -=> zn) = (0.500, 0.500); + (a3 -=> zn) = (0.500, 0.500); + (a4 -=> zn) = (0.500, 0.500); + endspecify +endmodule diff --git a/ivtest/ivltests/pr1589497.v b/ivtest/ivltests/pr1589497.v new file mode 100644 index 000000000..9197f7017 --- /dev/null +++ b/ivtest/ivltests/pr1589497.v @@ -0,0 +1,25 @@ +module test; + + reg signed [31:0] mydata; + + + initial + begin + mydata = -6; + repeat ( 11 ) + begin + add_one(mydata); + $display("mydata = %0d", mydata); + end + $finish(0); + end + + +task add_one; + inout signed [31:0] myotherdata; + begin + myotherdata = myotherdata + 1; + end +endtask + +endmodule diff --git a/ivtest/ivltests/pr1598445.v b/ivtest/ivltests/pr1598445.v new file mode 100644 index 000000000..d3a70b707 --- /dev/null +++ b/ivtest/ivltests/pr1598445.v @@ -0,0 +1,42 @@ +module test(); + + wire sig; + reg en0, en1; + + pullup (sig); + assign sig = en0 ? 1'b0 : 1'bz; + assign sig = en1 ? 1'b1 : 1'bz; + + reg sig2; + always @(sig) + sig2 = sig; + + initial begin + + en0 = 0; + en1 = 1; + #1 en1 = 0; + + #1 if (sig2 !== 1'b1) begin + $display("FAILED -- sig2=%b, sig=%b", sig2, sig); + $finish; + end + + force sig = 0; + + #1 if (sig2 !== 1'b0) begin + $display("FAILED -- sig2=%b, sig=%b", sig2, sig); + $finish; + end + + release sig; + + #1 if (sig2 !== 1'b1) begin + $display("FAILED -- sig2=%b, sig=%b", sig2, sig); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/pr1601896.v b/ivtest/ivltests/pr1601896.v new file mode 100644 index 000000000..da3cb8b4e --- /dev/null +++ b/ivtest/ivltests/pr1601896.v @@ -0,0 +1,10 @@ +module test; + initial + begin + if(2) + $display("PASSED"); + else + $display("FAILED"); + end + + endmodule diff --git a/ivtest/ivltests/pr1601898.v b/ivtest/ivltests/pr1601898.v new file mode 100644 index 000000000..2ebbc5a6b --- /dev/null +++ b/ivtest/ivltests/pr1601898.v @@ -0,0 +1,17 @@ +module test; + initial begin + main; + $display("PASSED"); + end + + task main; + begin + if(1) + ; + else begin + $display("FAILED"); + $finish; + end + end + endtask +endmodule diff --git a/ivtest/ivltests/pr1603313.v b/ivtest/ivltests/pr1603313.v new file mode 100644 index 000000000..ee33fabce --- /dev/null +++ b/ivtest/ivltests/pr1603313.v @@ -0,0 +1,78 @@ +/* + * This program is explicitly placed in the public domain for any uses + * whatsoever. + */ + +module TestMultiplier(); + + reg clk; + initial begin + clk = 0; + forever #0.5 clk = ~clk; + end + + reg[5:0] left, right; + wire[2:0] exp; + Multiplier mul(clk, left, right, exp); + + parameter ONE = {3'b011, 3'b0}; // 1.000 * 2**(3 - bias of 3) == 1.000 + + always @ (posedge clk) begin + left = ONE; + right = ONE; + + #10 + + if (exp !== 3'b011) + $display("FAIL: expected %b, got %b", + 3'b011, exp); + else + $display("PASSED"); + + $finish(); + end +endmodule + + +/** + * A little bit of an incomplete floating-point multiplier. In/out format is + * [5:3] specify biased exponent (and hidden bit), [2:0] specify fraction. + * + * @param left[5:0], right[5:0] + * values being multiplied + * @param exp[2:0] + * exponent from product of left and right when put in the floating-point + * format of left/right + */ +module Multiplier(clk, + left, right, + exp); + input clk; + input[5:0] left, right; + + output[2:0] exp; + reg[2:0] exp; + + + // IMPLEMENTATION + + wire signed[2:0] expl = left[5:3] - 3; + wire signed[2:0] expr = right[5:3] - 3; + + /** Sum of unbiased exponents in operands. */ + reg signed[3:0] sumExp; + + + always @ (posedge clk) begin + + + + + sumExp <= (expl + expr) < -2 // why can't I move -2 to the right-hand side? + + ? -3 + : expl + expr; + + exp[2:0] <= sumExp + 3; + end +endmodule diff --git a/ivtest/ivltests/pr1603918.v b/ivtest/ivltests/pr1603918.v new file mode 100644 index 000000000..a40f91ae7 --- /dev/null +++ b/ivtest/ivltests/pr1603918.v @@ -0,0 +1,57 @@ +`timescale 1ns/1ns + +module top; + wire q; + reg a, b; + + initial begin +// $dumpfile("test.lx2"); // Need to also use the -lxt2 flags on exe. +// $dumpvars(0, top); + // Initial value should be X is 1. + #1 a = 1'b1; // Should be X is 1. + #1 if (q !== 1'bx) begin + $display("FAILED -- %b nand %b --> %b", a, b, q); + $finish; + end + #1 a = 1'b0; // Correct: 1. + #1 if (q !== 1'b1) begin + $display("FAILED -- %b nand %b --> %b", a, b, q); + $finish; + end + #1 a = 1'b1; // Should be X is 1. + #1 if (q !== 1'bx) begin + $display("FAILED -- %b nand %b --> %b", a, b, q); + $finish; + end + #1 a = 1'bx; // Should be X is 1. + #1 if (q !== 1'bx) begin + $display("FAILED -- %b nand %b --> %b", a, b, q); + $finish; + end + #1 a = 1'b1; // Should be X is 1. + #1 if (q !== 1'bx) begin + $display("FAILED -- %b nand %b --> %b", a, b, q); + $finish; + end + #1 a = 1'bx; b = 1'b1; // Correct: X. + #1 if (q !== 1'bx) begin + $display("FAILED -- %b nand %b --> %b", a, b, q); + $finish; + end + #1 b = 1'b0; // Correct: 1. + #1 if (q !== 1'b1) begin + $display("FAILED -- %b nand %b --> %b", a, b, q); + $finish; + end + #1 b = 1'b1; // Correct: X, but following #1 delay is missing. + #1 if (q !== 1'bx) begin + $display("FAILED -- %b nand %b --> %b", a, b, q); + $finish; + end + $display("PASSED"); + $finish; + end + + nand dut (q, a, b); +// nand dut (q, b, a); // This also produces incorrect results. +endmodule diff --git a/ivtest/ivltests/pr1609611.v b/ivtest/ivltests/pr1609611.v new file mode 100644 index 000000000..9cce473f7 --- /dev/null +++ b/ivtest/ivltests/pr1609611.v @@ -0,0 +1,25 @@ +module x; + + parameter bar0_low = 5'd16; // Register Space + reg [31:bar0_low] base_address0; + + reg [31:0] ad_in_d; + wire [0:5] hit_bar; + + wire a = |bar0_low; + wire [31:0] e = ad_in_d[31:bar0_low]; + wire b = (base_address0==e); + wire d = b; + + assign hit_bar[0] = a ? d : 0; + + initial begin + if ($bits(base_address0) != 16) begin + $display("FAILED -- $bits(base_address0) = %0d", $bits(base_address0)); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1612693.v b/ivtest/ivltests/pr1612693.v new file mode 100644 index 000000000..dcc427c17 --- /dev/null +++ b/ivtest/ivltests/pr1612693.v @@ -0,0 +1,14 @@ +/* pr1612693.v */ + +module test (); + reg [9:0] col; + wire [9:0] xsize; + // The setup for this expression caused an assertion at run time + // according to pr1612693. + wire vschg = (col == (xsize>>1)); + + initial begin + #1 $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1623097.v b/ivtest/ivltests/pr1623097.v new file mode 100644 index 000000000..496c52ef6 --- /dev/null +++ b/ivtest/ivltests/pr1623097.v @@ -0,0 +1,65 @@ +/* pr1623097 */ +`timescale 1ns/1ns + + +module top; + + reg [3:0] state; + reg [3:0] data; + reg [3:0] clear; + reg clk; + + genvar i; + + initial begin + #0; // avoid time-0 race + clk = 0; data = 4'b1111; clear = 4'b1111; + $monitor($time,,"clk=%b, data=%b, clear=%b, state=%b", + clk, data, clear, state); + + #10 clear = 4'b0000; + #10 clk = 1; + #10 clk = 0; clear = 4'b0010; + #10 clear = 4'b0000; data = 4'b1010; + #10 clk = 1; + #10 clk = 0; + end + + + // This fails! + generate for (i=0; i<4; i=i+1) begin:sm + always @(posedge clk or posedge clear[i]) begin + if (clear[i]) state[i] <= 1'b0; // Async. clear the flip bit. + else begin + state[i] <= #1 data[i]; + end + end + end endgenerate + + + + + + + + + + + + + + + + + + + + + + + + + + + +endmodule diff --git a/ivtest/ivltests/pr1625912.v b/ivtest/ivltests/pr1625912.v new file mode 100644 index 000000000..9af82b1eb --- /dev/null +++ b/ivtest/ivltests/pr1625912.v @@ -0,0 +1,23 @@ +/* PR1625912 */ + +/* + * Substatuting in either of the commented out lines caused VVP to fail. + */ + +module top; + integer cnt; + real result, win; + + initial begin + cnt = -10; + for (result=-10; result<=10; result=result+2) begin + #1 if (result != cnt) begin + $display("FAILED -- cnt=%0d, result=%f", cnt, result); + end + cnt = cnt + 2; + end + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/pr1628288.v b/ivtest/ivltests/pr1628288.v new file mode 100644 index 000000000..e31d24eee --- /dev/null +++ b/ivtest/ivltests/pr1628288.v @@ -0,0 +1,61 @@ +// `define READ read_good + +module top; + reg clk; + reg dout; + reg [7:0] data; + integer lp; + + always #10 clk = ~clk; // Build a clock generator. + + always @(negedge clk) dout = ~dout; // Build a bit stream. + + initial begin + clk = 0; + dout = 0; + @(negedge clk); + for (lp=0; lp<4; lp=lp+1) begin + #0 read_bad(data); + $display("Read(%0d) %b from the bit stream.", lp, data); + #20; // For the fun of it skip a clock. + end + + #1 $finish(0); + end + + // This one locks up on the third call. + task read_bad; + output [7:0] edata; + + integer i; + + reg [7:0] rddata; + + begin + for(i=7; i>=0; i=i-1) begin + @(posedge clk); + $display(" Reading bit %0d", i); + rddata[i] = dout; // <<--- This appears to be the problem line! + end + + assign edata = rddata; + end + endtask + + // This one works fine. + task read_good; + output [7:0] edata; + + integer i; + + reg [7:0] edata; + + begin + for(i=7; i>=0; i=i-1) begin + @(posedge clk); + $display(" Reading bit %0d", i); + edata[i] = dout; + end + end + endtask +endmodule diff --git a/ivtest/ivltests/pr1628300.v b/ivtest/ivltests/pr1628300.v new file mode 100644 index 000000000..41a89b646 --- /dev/null +++ b/ivtest/ivltests/pr1628300.v @@ -0,0 +1,15 @@ +module bug; + +function real sin; + input x; + real x; + sin = 1.570794*x; +endfunction + +real ax, ay; +initial begin + ax = 2.0; + ay = sin(ax); + $display("sin(%g) is not really %g", ax, ay); +end +endmodule diff --git a/ivtest/ivltests/pr1629683.v b/ivtest/ivltests/pr1629683.v new file mode 100644 index 000000000..feb598e7a --- /dev/null +++ b/ivtest/ivltests/pr1629683.v @@ -0,0 +1,35 @@ +`timescale 1ns/1ns + +module top; + reg [7:0] data; + reg [9:0] odata; + reg sout, clk; + integer lp; + + initial begin + data = 8'h55; + + #0 $display("Printing the byte %b with a header.", data); + $write("Bad - "); + odata = 10'b1x00000000; + odata[7:0] = data; + send_byte(odata); +// #0 send_byte(odata); // This fixes things, but should not be needed! + $write(", ok - "); + send_byte(odata); + $display("."); + + #1 data = 0; + #1 $finish(0); + end + + // Print a byte of data. + task send_byte; + input [9:0] sndbyte; + + begin + $write("%b", sndbyte); + end + endtask + +endmodule diff --git a/ivtest/ivltests/pr1632861.v b/ivtest/ivltests/pr1632861.v new file mode 100644 index 000000000..6bec9b7da --- /dev/null +++ b/ivtest/ivltests/pr1632861.v @@ -0,0 +1,19 @@ +module test; + reg[9:0] tst; + + initial begin + #1 tst = 0; + // This should set the register to 10'b00000xxxxx! + #1 tst = 5'hxx; + #1 tst = 10'h3ff; + #1 tst = 10'b00000xxxxx; + #1 tst = 0; + #1 tst = 8'hxx; + #1 tst = 0; + #1 $finish(0); + end + + always @(tst) begin + $display("At %0t value is %b", $time, tst); + end +endmodule diff --git a/ivtest/ivltests/pr1634526.v b/ivtest/ivltests/pr1634526.v new file mode 100644 index 000000000..0e50a204a --- /dev/null +++ b/ivtest/ivltests/pr1634526.v @@ -0,0 +1,19 @@ +/* pr1634526.v */ + +module test; + initial begin + $display("Working: This (%0d) should be 255.", minus1(256)); +// This crashes! + $display("Broken: This (%0d) should be 255", minus1(2**8)); +// And this gives the wrong result! + $display("Broken: This (%0d) should be 255.", minus1(2**8-1+1)); + $display(" started with %0d.", 2**8-1+1); + $finish(0); + end + + function integer minus1; + input value; + integer value; + minus1 = value - 1; + endfunction +endmodule diff --git a/ivtest/ivltests/pr1636409.v b/ivtest/ivltests/pr1636409.v new file mode 100644 index 000000000..005f10a60 --- /dev/null +++ b/ivtest/ivltests/pr1636409.v @@ -0,0 +1,33 @@ +/* pr1636409 */ +module top; + wire [3:0] fail, good; + wire eni; + reg [2:0] rg; + reg in, en, clk; + + assign #1 eni = en; + assign #1 fail = (eni) ? {rg,in} : 'b0; + assign #1 good = {4{eni}} & {rg,in}; + + always @(fail or good or eni) begin + $strobe("fail=%b, good=%b, en=%b at %0t", fail, good, eni, $time); + end + + always #10 clk = ~clk; + + always @(posedge clk) begin + en = ~en; + in = ~in; + rg = ~rg; + end + + initial begin +// $dumpfile("results.vcd"); +// $dumpvars(0, top); + clk = 0; + en = 0; + in = 0; + rg = 3'b101; + #50 $finish(0); + end +endmodule diff --git a/ivtest/ivltests/pr1637208.v b/ivtest/ivltests/pr1637208.v new file mode 100644 index 000000000..021cfc736 --- /dev/null +++ b/ivtest/ivltests/pr1637208.v @@ -0,0 +1,53 @@ +/* PR1637208 */ + +module main; + reg clock; + reg [31:0] pixel0; + reg [31:0] mem [0:1]; + + always @(posedge clock) begin + mem[0] <= pixel0; + end + + always @(posedge clock) begin + mem[1] <= mem[0]; + end + + reg sel; + wire [31:0] foo = sel? mem[1] : mem[0]; + + initial begin + clock = 1; + sel = 0; + #1 pixel0 = 'h55555555; + #1 clock = 0; + #1 clock = 1; + #1 pixel0 = 'haaaaaaaa; + #1 clock = 0; + #1 clock = 1; + #1 if (mem[0] !== 32'haaaaaaaa) begin + $display("FAILED -- mem[0] = %h", mem[0]); + $finish; + end + + if (mem[1] !== 32'h55555555) begin + $display("FAILED == mem[1] = %h", mem[1]); + $finish; + end + + if (foo !== mem[0]) begin + $display("FAILED -- mem[sel=0] != %h", foo); + $finish; + end + + sel = 1; + + #1 if (foo !== mem[1]) begin + $display("FAILED -- mem[sel=1] != %h", foo); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/pr1638985.v b/ivtest/ivltests/pr1638985.v new file mode 100644 index 000000000..9626ceeec --- /dev/null +++ b/ivtest/ivltests/pr1638985.v @@ -0,0 +1,16 @@ +module main; + real x; + + initial + begin + x = 1.0; + + $display("Hello, World"); + $display("Positive x is %f", x); + $display("-1.0 * x is %f", -1.0 * x); + $display("0.0 - x is %f", 0.0 - x); + $display("-x is %f", -x); + + $finish(0); + end +endmodule diff --git a/ivtest/ivltests/pr1639060.v b/ivtest/ivltests/pr1639060.v new file mode 100644 index 000000000..168d5744e --- /dev/null +++ b/ivtest/ivltests/pr1639060.v @@ -0,0 +1,26 @@ +// pr1639060 + +module top; + real value; + + initial begin + value = 10.0; + // value = -10.0; + print; + end + + task print; + + real tmp; + + begin + if (value < 0.0) tmp = value + 10.0; + else tmp = value; + $display("1. The result is %5.1f", tmp); + + // This line fails! + tmp = (value < 0.0) ? value+10.0 : value; + $display("2. The result is %5.1f", tmp); + end + endtask +endmodule diff --git a/ivtest/ivltests/pr1639064.v b/ivtest/ivltests/pr1639064.v new file mode 100644 index 000000000..01aa367b7 --- /dev/null +++ b/ivtest/ivltests/pr1639064.v @@ -0,0 +1,13 @@ +module top; + reg value = 1; + integer val = 100; + + initial begin + $display("1. The value is %3d", value*100); + $display("2. The value is %3.0f", value*100.0); + $display("3. The value is %3.0f", 100); + $display("4. The value is %3.0f", val); + $display("5. The value is %3.0f", value*100); // This fails! + $finish(0); + end +endmodule diff --git a/ivtest/ivltests/pr1639064b.v b/ivtest/ivltests/pr1639064b.v new file mode 100644 index 000000000..212e1958c --- /dev/null +++ b/ivtest/ivltests/pr1639064b.v @@ -0,0 +1,13 @@ +module top; + reg [31:0] value = 1000000; + integer val = 100; + + initial begin + $display("1. The value is %3d", value*100); + $display("2. The value is %3.0f", value*100.0); + $display("3. The value is %3.0f", 100); + $display("4. The value is %3.0f", val); + $display("5. The value is %3.0f", value*100000000); // This fails! + $finish(0); + end +endmodule diff --git a/ivtest/ivltests/pr1639968.v b/ivtest/ivltests/pr1639968.v new file mode 100644 index 000000000..76667d98d --- /dev/null +++ b/ivtest/ivltests/pr1639968.v @@ -0,0 +1,27 @@ + module RegisterArrayBug01; + + reg [15:0] rf[0:7]; + + wire [15:0] rf_0 = rf[1]; + + initial begin + $monitor($time,, "rf[0] is %h %h", rf[1], rf_0); + + rf[1] = 16'hffff; + #10 rf[1] = 16'h0000; + #10 rf[1] = 16'hbeef; + #10 $finish(0); + end + + endmodule + + /* + System prints: + 0 rf[0] is xxxx ffff + 10 rf[0] is xxxx 0000 + 20 rf[0] is beef beef + Expected is: + 0 rf[0] is ffff ffff + 10 rf[0] is 0000 0000 + 20 rf[0] is beef beef + */ diff --git a/ivtest/ivltests/pr1639971.v b/ivtest/ivltests/pr1639971.v new file mode 100644 index 000000000..e81f7857e --- /dev/null +++ b/ivtest/ivltests/pr1639971.v @@ -0,0 +1,21 @@ +module RegisterArrayBug01; + + reg [15:0] rf[0:7]; + wire [3:0] rf_0_slice0 = rf[0][3:0]; + + wire [15:0] rf_0 = rf[0]; + + initial begin + $monitor($time,, "rf and slice: %h %h", rf_0, rf_0_slice0); + + rf[0] = 16'hffff; + #10 rf[0] = 16'h0000; + #10 rf[0] = 16'hbeef; + #10 $finish(0); + end + +endmodule + +/* Program fails to compile with result: + elab_net.cc:1738: failed assertion `msb_ == 0' + */ diff --git a/ivtest/ivltests/pr1645277.v b/ivtest/ivltests/pr1645277.v new file mode 100644 index 000000000..4cf78ffee --- /dev/null +++ b/ivtest/ivltests/pr1645277.v @@ -0,0 +1,16 @@ +// pr1645277 + + module test; + initial main; + + task main; + integer foo; + begin + foo = 0; + while(foo < 5) begin: inner + foo = foo + 1; + end + $write("expected %d; got %d\n", 5, foo); + end + endtask + endmodule diff --git a/ivtest/ivltests/pr1645518.v b/ivtest/ivltests/pr1645518.v new file mode 100644 index 000000000..17d8a721e --- /dev/null +++ b/ivtest/ivltests/pr1645518.v @@ -0,0 +1,33 @@ +/* PR1645518 */ + +module testBench; + wire w1, w2, w3, w4, w5; + binaryToESeg d (w1, w2, w3, w4, w5); + test_bToESeg t (w1, w2, w3, w4, w5); +endmodule + +module binaryToESeg + (input A, B, C, D, + output eSeg); + nand #1 + g1 (p1, C, ~D), + g2 (p2, A, B), + g3 (p3, ~B, ~D), + g4 (p4, A, C), + g5 (eSeg, p1, p2, p3, p4); +endmodule // binaryToESeg + +module test_bToESeg + (output reg A, B, C, D, input eSeg); + initial // two slashes introduce a single line comment + begin + $monitor ($time,, + "A = %b B = %b C = %b D = %b, eSeg = %b", + A, B, C, D, eSeg); + //waveform for simulating the nand lip lop + #10 A = 0; B = 0; C = 0; D = 0; + #10 D = 1; + #10 C = 1; D = 0; + #10 $finish(0); + end +endmodule diff --git a/ivtest/ivltests/pr1648365.v b/ivtest/ivltests/pr1648365.v new file mode 100644 index 000000000..8f62970a4 --- /dev/null +++ b/ivtest/ivltests/pr1648365.v @@ -0,0 +1,65 @@ +module ivitest; + +reg clock_1x, clock_2x; + +reg [31:1] w [0:1]; + +wire [31:1] w0 = w[0]; +wire [31:1] w1 = w[1]; + +initial begin + #0; //avoid time-0 race + clock_1x = 0; + clock_2x = 0; + $monitor($time,,"w0=%h, w1=%h", w0, w1); + #1; + forever begin + clock_1x = !clock_1x; + clock_2x = !clock_2x; + #5; + clock_2x = !clock_2x; + #5; + end +end + +reg phase; +always @(clock_1x) begin + phase = #1 clock_1x; +end + +reg [31:1] u; + +always @(posedge clock_2x) begin + u <= 'haaaaaaaa; +end + + +reg [31:1] v; + +always @(posedge clock_2x) begin + v <= 'h99999999; + if (phase) begin + w[0] <= v; + w[1] <= u; + end +end + + +reg [31:1] x0, x1; + +always @(posedge clock_1x) begin + x0 <= w[0]; + x1 <= w[1]; +end + + +initial begin +// $dumpfile( "test.vcd" ); +// $dumpvars; + + #100; + $finish(0); +end + + +endmodule diff --git a/ivtest/ivltests/pr1650842.v b/ivtest/ivltests/pr1650842.v new file mode 100644 index 000000000..7ced79498 --- /dev/null +++ b/ivtest/ivltests/pr1650842.v @@ -0,0 +1,31 @@ +/* pr1650842 */ + + module test; + + initial main; + + task main; + integer _$ID241, _$ID246, _$ID247, _$ID248, _$ID249, a; + begin + a = 0; + _$ID241 = a; + a = 9; + _$ID246 = a; + _$ID247 = 3; + a = _$ID247; + _$ID248 = _$ID246 + _$ID247 ; + _$ID249 = _$ID248; + a = _$ID249; + if( a !== 12 ) begin + $write("FAIL: expected 12; got %d\n", a); + $display("_$ID241=%d", _$ID241); + $display("_$ID246=%d", _$ID246); + $display("_$ID247=%d", _$ID247); + $display("_$ID248=%d", _$ID248); + $display("_$ID249=%d", _$ID249); + end else begin + $write("PASSED\n"); + end + end + endtask + endmodule diff --git a/ivtest/ivltests/pr1657307.v b/ivtest/ivltests/pr1657307.v new file mode 100644 index 000000000..8c290ba3b --- /dev/null +++ b/ivtest/ivltests/pr1657307.v @@ -0,0 +1,43 @@ +module test; + integer dindex[2:0]; + integer cindex[2:0]; + + initial + main; + + task main; + integer index; + begin + dindex[0] = 3; + dindex[1] = 4; + dindex[2] = 5; + + cindex[0] = 1; + cindex[1] = 2; + cindex[2] = 3; + + index = get_index(3); + $write("index is %0d\n", index); + if (index !== 32) + $display("FAILED"); + else + $display("PASSED"); + end + endtask + + function integer get_index; + input rank; + integer rank; + integer i, sum, multiplier; + begin + multiplier = 1; + sum = 0; + for(i = rank-1; i >= 0; i = i-1) begin + sum = sum + (cindex[i] * multiplier); + multiplier = dindex[i] * multiplier; + end + get_index = sum-1; + end + endfunction + +endmodule // test diff --git a/ivtest/ivltests/pr1661640.v b/ivtest/ivltests/pr1661640.v new file mode 100644 index 000000000..d17d29b8d --- /dev/null +++ b/ivtest/ivltests/pr1661640.v @@ -0,0 +1,23 @@ +// pr1661640.v + + module test; + reg [112:1] hello1, hello2; + initial begin + hello1 = "Hello world!\n"; + hello2 = "Hello world!\012"; + main; + end + task main; + begin + $write ("%s\n", "Hello world!"); // Ok + $write ("%s", "Hello world!\n"); // bad + $write ("\nhello1; escaped NL:\n"); + $write ("%0s", hello1); // bad + $write ("%x", hello1); + $write ("\nhello2; octal NL:\n"); + $write ("%0s", hello2); // bad + $write ("%x", hello2); + $display(); + end + endtask + endmodule diff --git a/ivtest/ivltests/pr1662508.v b/ivtest/ivltests/pr1662508.v new file mode 100644 index 000000000..07e965164 --- /dev/null +++ b/ivtest/ivltests/pr1662508.v @@ -0,0 +1,52 @@ +// pr1662508.v + +`timescale 1ns / 1ns + +module ram( + input clk, + input we, + input [9:0] addr, + input [15:0] data, + output [15:0] read_bus +); + +reg [15:0] ram[31:0]; +assign read_bus = ram[addr[3:0]]; +always @(posedge clk) if (we) + ram[addr[3:0]] <= data; +endmodule + + +module ram_test; + +reg clk; +reg fail=0; +integer cc; +initial begin + for (cc = 0; cc < 33; cc=cc+1) begin + clk = 0; #5; + clk = 1; #5; + end + if (fail) $display("FAIL"); + else $display("PASSED"); +end + +reg we=0; +reg [9:0] addr=0; +reg [15:0] data=0; + +always @(posedge clk) begin + addr <= cc; + data <= cc*cc; + we <= cc<16; +end + +wire [15:0] read_bus; +ram ram(clk, we, addr, data, read_bus); + +always @(negedge clk) if (~we) begin + $display("%d %d", addr, read_bus); + if (read_bus !== addr[3:0]*addr[3:0]) fail=1; +end + +endmodule diff --git a/ivtest/ivltests/pr1664684.v b/ivtest/ivltests/pr1664684.v new file mode 100644 index 000000000..6d9b461ce --- /dev/null +++ b/ivtest/ivltests/pr1664684.v @@ -0,0 +1,32 @@ +// pr1664684 + +module bug (rdo, rm, cpen, up14, rdi); + output [31:0] rdo; + input rm, cpen; + input [31:0] up14, rdi; + + initial $monitor($time,,rdo,,rm,cpen,,up14,,rdi); + assign rdo = (rm | cpen) ? up14 : rdi; + + endmodule + + module bench; + + reg [31:0] up14; + wire [31:0] rdo; + reg rm, cpen; + tri0 [31:0] rdi; + + bug u1 (rdo, rm, cpen, up14, rdi); + + initial begin + rm = 1'bX; + cpen = 1'b0; + up14 = 'hX; + #40; + up14 = 32'd0; + rm = 1'b0; + #40; + $finish(0); + end + endmodule diff --git a/ivtest/ivltests/pr1675789.v b/ivtest/ivltests/pr1675789.v new file mode 100644 index 000000000..3c8d7d525 --- /dev/null +++ b/ivtest/ivltests/pr1675789.v @@ -0,0 +1,48 @@ +module main; + + parameter NIBBLE = 4; + reg [NIBBLE*4-1:0] array [1:0]; + reg [3:0] word; + + integer idx; + initial begin + for (idx = 0 ; idx < 4 ; idx = idx+1) begin + array[0][idx*NIBBLE +: 4] = +idx; + array[1][idx*NIBBLE +: 4] = -idx; + end + + if (array[0] !== 16'h3210) begin + $display("FAILED -- array[0] = %h", array[0]); + $finish; + end + + word = array[0][7:4]; + if (word !== 4'h1) begin + $display("FAILED == array[0][7:4] = %h", word); + $finish; + end + + word = array[1][7:4]; + if (word !== 4'hf) begin + $display("FAILED == array[0][7:4] = %h", word); + $finish; + end + + for (idx = 0 ; idx < 4 ; idx = idx+1) begin + word = array[0][idx*NIBBLE +: 4]; + if (word !== idx) begin + $display("FAILED == array[0][nibble=%d] = %h", idx, word); + $finish; + end + + word = array[1][idx*NIBBLE +: 4]; + if (word !== - idx[3:0]) begin + $display("FAILED == array[1][nibble=%d] = %h", idx, word); + $finish; + end + end // for (idx = 0 ; idx < 4 ; idx += 1) + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/pr1675789b.v b/ivtest/ivltests/pr1675789b.v new file mode 100644 index 000000000..19cf30242 --- /dev/null +++ b/ivtest/ivltests/pr1675789b.v @@ -0,0 +1,37 @@ +module main; + parameter WORD_WID = 3; + parameter WORD_CNT = 8; + + reg [WORD_WID-1: 0] mem [0:WORD_CNT-1], tmp; + + integer idx, jdx; + initial begin + for (idx = 0 ; idx < WORD_CNT ; idx = idx+1) + mem[idx] = idx; + + for (idx = 0 ; idx < WORD_CNT ; idx = idx+1) begin + tmp = idx; + + if (mem[idx][2:1] !== tmp[2:1]) begin + $display("FAILED -= mem[%d][2:1]=%b, tmp[2:1]=%b", + idx, mem[idx][2:1], tmp[2:1]); + $finish; + end + + if (mem[idx][1:0] !== tmp[1:0]) begin + $display("FAILED -= mem[%d][1:0]=%b, tmp[1:0]=%b", + idx, mem[idx][1:0], tmp[1:0]); + $finish; + end + + for (jdx = 0 ; jdx < WORD_WID ; jdx = jdx+1) + if (mem[idx][jdx +:2] !== tmp[jdx +:2]) begin + $display("FAILED -- mem[%d][%d +:2]=%b, tmp[%d +:2]=%b", + idx, jdx, mem[idx][jdx+:2], jdx, tmp[jdx+:2]); + $finish; + end + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/pr1676071.v b/ivtest/ivltests/pr1676071.v new file mode 100644 index 000000000..8761df9d5 --- /dev/null +++ b/ivtest/ivltests/pr1676071.v @@ -0,0 +1,60 @@ +`begin_keywords "1364-2005" +`timescale 1ns / 1ns + +module gentest; + +reg [7:0] a=0, b=0; +wire co; +wire [7:0] result; + +adder work(a, b, 1'b0, result, co); + +integer cc; +initial begin + for (cc=0; cc<10; cc=cc+1) begin + a=a+1; + #10; + $display("%d %d %d", a, b, result); + b=result; + end + if (b==55) $display("PASSED"); + else $display("FAIL"); +end + +endmodule + +module adder(a, b, ci, out, co); +parameter SIZE=8; +input [SIZE-1:0] a; +input [SIZE-1:0] b; +input ci; +output [SIZE-1:0] out; +output co; + +wire [SIZE:0] c; +assign c[0] = ci; +assign co = c[SIZE]; +`ifdef NOGENERATE + add1 bit0(a[0], b[0], c[0], out[0], c[0+1]); + add1 bit1(a[1], b[1], c[1], out[1], c[1+1]); + add1 bit2(a[2], b[2], c[2], out[2], c[2+1]); + add1 bit3(a[3], b[3], c[3], out[3], c[3+1]); + add1 bit4(a[4], b[4], c[4], out[4], c[4+1]); + add1 bit5(a[5], b[5], c[5], out[5], c[5+1]); + add1 bit6(a[6], b[6], c[6], out[6], c[6+1]); + add1 bit7(a[7], b[7], c[7], out[7], c[7+1]); +`else +genvar i; +generate for(i=0; i> shift; + wire [3:0] ls = foo << shift; + + wire tr = 4'b0100 > (foo >> shift); + + initial begin + foo = 4'b1001; + shift = 0; + + #1 if (rs !== 4'b1001 || ls !== 4'b1001) begin + $display("FAILED -- shift=%d, rs=%b, ls=%b", shift, rs, ls); + $finish; + end + + shift = 1; + + #1 if (rs !== 4'b0100 || ls !== 4'b0010 || tr !== 0) begin + $display("FAILED -- shift=%d, rs=%b, ls=%b", shift, rs, ls); + $finish; + end + + shift = 2; + + #1 if (rs !== 4'b0010 || ls !== 4'b0100 || tr !== 1) begin + $display("FAILED -- shift=%d, rs=%b, ls=%b", shift, rs, ls); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/pr1694413.v b/ivtest/ivltests/pr1694413.v new file mode 100644 index 000000000..98690e903 --- /dev/null +++ b/ivtest/ivltests/pr1694413.v @@ -0,0 +1,14 @@ +module test (); + parameter fuse_a_msb = 4; + parameter fuse_q_msb = (2**(fuse_a_msb+1))-1; + + initial begin + if (fuse_q_msb != 'h1f) begin + $display("FAILED -- fuse_q_msb = %d", fuse_q_msb); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1694427.v b/ivtest/ivltests/pr1694427.v new file mode 100644 index 000000000..f37bff5b3 --- /dev/null +++ b/ivtest/ivltests/pr1694427.v @@ -0,0 +1,30 @@ +module test (); + + reg[7:0] a; + reg b; + + always @* + begin + b = 1'b0; + case (a) + 8'd66: b = 1'b1; + default: ; + endcase + end + + initial begin + a = 0; + #1 if (b !== 0) begin + $display("FAILED -- a=%h b=%b", a, b); + $finish; + end + + a = 66; + #1 if (b !== 1) begin + $display("FAILED -- a=%h b=%b", a, b); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1695257.v b/ivtest/ivltests/pr1695257.v new file mode 100644 index 000000000..224ae3ea4 --- /dev/null +++ b/ivtest/ivltests/pr1695257.v @@ -0,0 +1,19 @@ +module test(CL, Q_data, D); + parameter + Bits = 84; + input CL; + output [Bits-1 : 0] Q_data; + input [Bits-1 : 0] D; + + reg WENreg; + reg ICGFlag; + + specify + specparam + + taa = 1.0; + + if (WENreg && !ICGFlag) (CL *> (Q_data[0] : D[0])) = (taa, taa); + endspecify + +endmodule diff --git a/ivtest/ivltests/pr1695309.v b/ivtest/ivltests/pr1695309.v new file mode 100644 index 000000000..92f574f54 --- /dev/null +++ b/ivtest/ivltests/pr1695309.v @@ -0,0 +1,34 @@ +module main; + + genvar i; + parameter MSB = 7; + + wire [MSB:0] Z; + reg [MSB:0] A, B; + generate + for (i = 0; i <= MSB; i = i+1) + begin: or2 + OR2 uor2 (.A(A[i]), .B(B[i]), .Z(Z[i])); + end + endgenerate + + initial begin + for (A = 0 ; A < 'hff ; A = A+1) + for (B = 0 ; B < 'hff ; B = B+1) + #1 if (Z !== (A|B)) begin + $display("FAILED -- A=%h, B=%h, Z=%h", A, B, Z); + $finish; + end + + $display("PASSED"); + end + +endmodule + +module OR2 (Z, A, B); + output Z; + input A; + input B; + + or (Z, A, B); +endmodule diff --git a/ivtest/ivltests/pr1695322.v b/ivtest/ivltests/pr1695322.v new file mode 100644 index 000000000..63f27b593 --- /dev/null +++ b/ivtest/ivltests/pr1695322.v @@ -0,0 +1,27 @@ +module test (); + + wire [5:0] a [0:2]; + + b b(.a(a[0])); + + initial begin + #1 if (a[0] !== 5) begin + $display("FAILED -- a[0] == %d", a[0]); + $finish; + end + + if (a[1] !== 6'bzzzzzz) begin + $display("FAILED -- a[1] == %h", a[1]); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule + +module b (output wire [5:0] a); + + assign a = 5; + +endmodule diff --git a/ivtest/ivltests/pr1695334.v b/ivtest/ivltests/pr1695334.v new file mode 100644 index 000000000..e45efad5d --- /dev/null +++ b/ivtest/ivltests/pr1695334.v @@ -0,0 +1,19 @@ +module test(); + parameter BITS = 4; + parameter C = 1; + + wire [BITS-1:0] a; + reg [BITS-1:0] a_bc; + assign a = a_bc - 2*C; + + initial begin + a_bc = 9; + #1 if (a !== 7) begin + $display("FAILED -- a_bc=%d, a=%d", a_bc, a); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1696137.v b/ivtest/ivltests/pr1696137.v new file mode 100644 index 000000000..58da6d1e5 --- /dev/null +++ b/ivtest/ivltests/pr1696137.v @@ -0,0 +1,25 @@ +//// +//// The following was written to illustrate a bug in iverilog. +//// In particular, this little lovely produces a 202 MB vvp file. +//// + +module ExplodedArrays1; + + reg [7:0] data [0:25600-1]; + + integer idx; + initial begin + for (idx = 0 ; idx < 25600 ; idx = idx+1) + data[idx] = idx[7:0]; + + for (idx = 0 ; idx < 256 ; idx = idx+ 1) begin + if (data[idx] !== idx) begin + $display("FAILED -- data[%d] = %d (%h)", idx, data[idx], data[idx]); + $finish; + end + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/pr1697250.v b/ivtest/ivltests/pr1697250.v new file mode 100644 index 000000000..6731f79de --- /dev/null +++ b/ivtest/ivltests/pr1697250.v @@ -0,0 +1,25 @@ +// pr1697250 + +module test(); + + wire active; + reg [63:0] bus; + + assign active = ((|(bus)===0)?0:1); + + initial begin + bus = 'haaaa; + #1 if (active !== 1) begin + $display("FAILED -- bus=%h, active=%b", bus, active); + $finish; + end + + bus = 0; + #1 if (active !== 0) begin + $display("FAILED == bus=%h, active=%b", bus, active); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1697732.v b/ivtest/ivltests/pr1697732.v new file mode 100644 index 000000000..188ec90bf --- /dev/null +++ b/ivtest/ivltests/pr1697732.v @@ -0,0 +1,22 @@ +module main; + + reg [3:0] value; + reg [2:0] addr; + + wire test_bit = value[addr] == 1; + + initial begin + value = 'b0110; + + for (addr = 0 ; addr < 4 ; addr = addr+1) begin + #1 if (test_bit !== value[addr]) begin + $display("FAILED -- value[%d]=%b, test_bit=%b", + addr, value[addr], test_bit); + $finish; + end + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/pr1698499.v b/ivtest/ivltests/pr1698499.v new file mode 100644 index 000000000..771679c57 --- /dev/null +++ b/ivtest/ivltests/pr1698499.v @@ -0,0 +1,133 @@ +module sysSimpleTest(); + reg CLK; + reg RST_N; + + initial begin + #0 + RST_N = 1'b0; + #1; + CLK = 1'b1; + $display("reset"); + #1; + RST_N = 1'b1; + $display("reset done"); + end + + always + begin + #5; + CLK = 1'b0 ; + #5; + CLK = 1'b1 ; + end + + + // register y + reg [98 : 0] y; + wire [98 : 0] y$D_IN; + wire y$EN; + + // register z + reg [98 : 0] z; + wire [98 : 0] z$D_IN; + wire z$EN; + + // remaining internal signals + wire [98 : 0] IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT_0_AND__ETC___d29, + IF_y_SLT_0_THEN_NEG_IF_y_SLT_0_THEN_NEG_y_0_EL_ETC___d28, + IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_QUOT_IF_z_SLT_ETC___d30, + IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_REM_IF_z_SLT__ETC___d31, + x__h201, + y__h141, + z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d17; + wire y_SLT_0___d33, + z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d22, + z_SLT_0___d32; + + // register y + assign y$D_IN = 99'h0 ; + assign y$EN = 1'b0 ; + + // register z + assign z$EN = 1'b0 ; + assign z$D_IN = 99'h0 ; + + // remaining internal signals + assign IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT_0_AND__ETC___d29 = + (y_SLT_0___d33 && !z_SLT_0___d32 || + !y_SLT_0___d33 && z_SLT_0___d32) ? + -IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_QUOT_IF_z_SLT_ETC___d30 : + IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_QUOT_IF_z_SLT_ETC___d30 ; + assign IF_y_SLT_0_THEN_NEG_IF_y_SLT_0_THEN_NEG_y_0_EL_ETC___d28 = + y_SLT_0___d33 ? + -IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_REM_IF_z_SLT__ETC___d31 : + IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_REM_IF_z_SLT__ETC___d31 ; + assign IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_QUOT_IF_z_SLT_ETC___d30 = + x__h201 / y__h141 ; + assign IF_y_SLT_0_THEN_NEG_y_0_ELSE_y_1_REM_IF_z_SLT__ETC___d31 = + x__h201 % y__h141 ; + assign x__h201 = y_SLT_0___d33 ? -y : y ; + assign y_SLT_0___d33 = + (y ^ 99'h4000000000000000000000000) < + 99'h4000000000000000000000000 ; + assign y__h141 = z_SLT_0___d32 ? -z : z ; + assign z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d17 = + z * IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT_0_AND__ETC___d29 ; + assign z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d22 = + z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d17 + + IF_y_SLT_0_THEN_NEG_IF_y_SLT_0_THEN_NEG_y_0_EL_ETC___d28 == + y ; + assign z_SLT_0___d32 = + (z ^ 99'h4000000000000000000000000) < + 99'h4000000000000000000000000 ; + + // handling of inlined registers + + always@(posedge CLK) + begin + if (!RST_N) + begin + // y <= 1; + // z <= 1; + y <= 99'h7FFFFFF04A62A1453402211B2; + z <= 99'h000000023E84321AAFCCC70C2; + end + else + begin + if (y$EN) y <= y$D_IN; + if (z$EN) z <= z$D_IN; + end + end + + // synopsys translate_off + initial + begin + y = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + z = 99'h2AAAAAAAAAAAAAAAAAAAAAAAA; + end + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N) + if (z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d22) + $display("OK: %0d * %0d + %0d == %0d", + $signed(z), + $signed(IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT_0_AND__ETC___d29), + $signed(IF_y_SLT_0_THEN_NEG_IF_y_SLT_0_THEN_NEG_y_0_EL_ETC___d28), + $signed(y)); + if (RST_N) + if (!z_MUL_IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT__ETC___d22) + $display("BAD: %0d * %0d + %0d != %0d", + $signed(z), + $signed(IF_y_SLT_0_AND_NOT_z_SLT_0_OR_NOT_y_SLT_0_AND__ETC___d29), + $signed(IF_y_SLT_0_THEN_NEG_IF_y_SLT_0_THEN_NEG_y_0_EL_ETC___d28), + $signed(y)); + if (RST_N) $finish(32'd0); + end + // synopsys translate_on +endmodule // sysSimpleTest diff --git a/ivtest/ivltests/pr1698658.v b/ivtest/ivltests/pr1698658.v new file mode 100644 index 000000000..456837c78 --- /dev/null +++ b/ivtest/ivltests/pr1698658.v @@ -0,0 +1,9 @@ +`timescale 1ns/10ps + +module top; + initial begin + $timeformat(-6, 0, " uS", 8); + #10 $display("The time is %t", $time); + #1000 $display("The time is %t", $time); + end +endmodule diff --git a/ivtest/ivltests/pr1698659.v b/ivtest/ivltests/pr1698659.v new file mode 100644 index 000000000..f9aab827a --- /dev/null +++ b/ivtest/ivltests/pr1698659.v @@ -0,0 +1,39 @@ +`timescale 1ns/10ps + +module top; + reg topvar; + initial begin + topvar = 0; + lwr.lowervar = 1; + lwr.elwr.evenlowervar = 0; + othertop.othertopvar = 1; + #10 $display("%m var is (%b)", topvar); + end + + lower lwr(); +endmodule + +module lower; + reg lowervar; + initial begin + #11 $display("%m var is (%b)", lowervar); + end + evenlower elwr(); +endmodule + +module evenlower; + reg evenlowervar; + initial begin + #12 $display("%m var is (%b)", evenlowervar); + $display("Up reference to me (%b)", elwr.evenlowervar); + $display("Up reference to parent (%b)", lwr.lowervar); + $display("Up reference is (%b)", lower.lowervar); + end +endmodule + +module othertop; + reg othertopvar; + initial begin + #20 $display("%m var is (%b)", othertopvar); + end +endmodule diff --git a/ivtest/ivltests/pr1698820.v b/ivtest/ivltests/pr1698820.v new file mode 100644 index 000000000..d27a8ec4b --- /dev/null +++ b/ivtest/ivltests/pr1698820.v @@ -0,0 +1,20 @@ +`begin_keywords "1364-2005" +module top; + reg [4:0] var; + integer fp; + + initial begin + var = 10; + fp = 1; + $fdisplay(fp, "The variable is ",var); + $fdisplayb(fp, "The variable is ",var); + $fdisplayo(fp, "The variable is ",var); + $fdisplayh(fp, "The variable is ",var); + $fwrite(fp, "The variable is ",var, "\n"); + $fwriteb(fp, "The variable is ",var, "\n"); + $fwriteo(fp, "The variable is ",var, "\n"); + $fwriteh(fp, "The variable is ",var, "\n"); + $fclose(fp); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr1699444.v b/ivtest/ivltests/pr1699444.v new file mode 100644 index 000000000..6003af213 --- /dev/null +++ b/ivtest/ivltests/pr1699444.v @@ -0,0 +1,7 @@ +module top; + + initial begin + $display("Output a slash \\."); + $display("Output a double slash \\\\."); + end +endmodule diff --git a/ivtest/ivltests/pr1699519.v b/ivtest/ivltests/pr1699519.v new file mode 100644 index 000000000..fc65db6be --- /dev/null +++ b/ivtest/ivltests/pr1699519.v @@ -0,0 +1,14 @@ +module top; + real rval; + reg [7:0] rgval; + + initial begin + rgval = 8'ha5; + rval = 1234567890; + + $display("Checking h and H: %h, %H", rgval, rgval); + $display("Checking x and X: %x, %X", rgval, rgval); + $display("Checking g and G: %g, %G", rval, rval); + $display("Checking e and E: %e, %E", rval, rval); + end +endmodule diff --git a/ivtest/ivltests/pr1701855.v b/ivtest/ivltests/pr1701855.v new file mode 100644 index 000000000..b52606200 --- /dev/null +++ b/ivtest/ivltests/pr1701855.v @@ -0,0 +1,36 @@ +`timescale 1us/1ns + +module top; + initial begin + + // This should print the following: + + // Time scale of (top) is 1us / 1ns + // Time scale of (top) is 1us / 1ns + // Time scale of (top.dut) is 10ns / 10ps + // Time scale of (top.dut.dut) is 1ns / 10ps + // Time scale of (othertop) is 1ms / 1us + + // But currently the precisions will all be 10ps the finest precision. + $printtimescale; + $printtimescale(); + $printtimescale(dut); + $printtimescale(dut.dut); + $printtimescale(othertop); + end + + lower dut(); +endmodule + +`timescale 10ns/10ps +module lower; + evenlower dut(); +endmodule + +`timescale 1ns/10ps +module evenlower; +endmodule + +`timescale 1ms/1us +module othertop; +endmodule diff --git a/ivtest/ivltests/pr1701855b.v b/ivtest/ivltests/pr1701855b.v new file mode 100644 index 000000000..c5f775b35 --- /dev/null +++ b/ivtest/ivltests/pr1701855b.v @@ -0,0 +1,72 @@ +`timescale 100ns/100ps +module dummy; + parameter [1:0] ipval = 2; +endmodule + +`timescale 1us/1ns + +module top; + parameter [1:0] ipval = 2; + parameter spval = "Help"; + parameter rpval = 1.0; + event evt; + reg [1:0] rgval; + reg rgarr [2:0]; + wire [1:0] wval; + wire warr [2:0]; + integer ival; + real rval; + real rarr [2:0]; + time tval; + + initial begin:blk + $printtimescale(dummy); + $printtimescale(dummy.ipval); + // These should all print a timescale of 1us / 1ns. + $printtimescale; + $printtimescale(top.ipval); + /* This does not currently work because Icarus does not know how + * to keep the parameter reference in the part select. For now + * it just returns a constant which the runtime will complain + * does not have a vpiModule. */ +// $printtimescale(top.ipval[0]); + $printtimescale(top.spval); + /* The same goes here. */ +// $printtimescale(top.spval[0]); + $printtimescale(top.rpval); + $printtimescale(top.evt); + $printtimescale(top.rgval); + $printtimescale(top.rgval[0]); + $printtimescale(top.rgarr); + $printtimescale(top.rgarr[0]); + $printtimescale(top.wval); + $printtimescale(top.wval[0]); + $printtimescale(top.warr); + $printtimescale(top.warr[0]); + $printtimescale(top.ival); + $printtimescale(top.ival[1]); + $printtimescale(top.rval); + $printtimescale(top.rarr); + $printtimescale(top.rarr[0]); + $printtimescale(top.tval); + $printtimescale(top.blk); + $printtimescale(top.frk); + $printtimescale(top.tsk); + $printtimescale(top.fnc); + end + + initial fork:frk + $write(""); + join + + task tsk; + begin + end + endtask + + function integer fnc; + input integer tmp; + fnc = 2 * tmp; + endfunction + +endmodule diff --git a/ivtest/ivltests/pr1701889.v b/ivtest/ivltests/pr1701889.v new file mode 100644 index 000000000..49e2e3522 --- /dev/null +++ b/ivtest/ivltests/pr1701889.v @@ -0,0 +1,26 @@ +module top; + time ioffset, ifuture; + realtime offset, future; + initial begin + offset = 1.0; + ioffset = 1; + future = 20.0; + ifuture = 120; + #1; + $display("----- Using real times -----"); + $display("The time one unit ago was : %t", $realtime - 1.0); + $display("The time one unit ago was : %t", $realtime - offset); + $display("The time now is : %t", $realtime); + $display("One time unit from now it will be: %t", $realtime + 1.0); + $display("The time at 20 will be : %t", future); + $display("The time at 40 will be : %t", 40.0); + #100; + $display("\n----- Using integer times -----"); + $display("The time one unit ago was : %t", $time - 1); + $display("The time one unit ago was : %t", $time - ioffset); + $display("The time now is : %t", $time); + $display("One time unit from now it will be: %t", $time + 1); + $display("The time at 120 will be : %t", ifuture); + $display("The time at 140 will be : %t", 140); + end +endmodule diff --git a/ivtest/ivltests/pr1701890.v b/ivtest/ivltests/pr1701890.v new file mode 100644 index 000000000..634c302db --- /dev/null +++ b/ivtest/ivltests/pr1701890.v @@ -0,0 +1,8 @@ +module top; + real rval1=1.0, rval2=2.0; + realtime rtval=1.0; + + initial begin + $display("rval1=", rval1,,"rval2=", rval2,,"rtval=",rtval); + end +endmodule diff --git a/ivtest/ivltests/pr1701921.v b/ivtest/ivltests/pr1701921.v new file mode 100644 index 000000000..806768fd0 --- /dev/null +++ b/ivtest/ivltests/pr1701921.v @@ -0,0 +1,23 @@ +// pr1701921 + +module top; + + reg foo, bar; + wire blend; + + assign blend = foo; + assign blend = bar; + + initial begin + bar = 1; + // Bar explicitly has a 1 value, foo gets its initial x value. + // Together, they should drive to an x value. + #1 if (blend !== 1'bx) begin + $display("FAILED -- blend=%b (foo=%b, bar=%b)", blend, foo, bar); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1702593.v b/ivtest/ivltests/pr1702593.v new file mode 100644 index 000000000..7e71addaf --- /dev/null +++ b/ivtest/ivltests/pr1702593.v @@ -0,0 +1,7 @@ +module top; + integer ival=-1; + initial begin + $display("The value is %5.2f", ival); + $display("The value is %5.2f", -1); + end +endmodule diff --git a/ivtest/ivltests/pr1703120.v b/ivtest/ivltests/pr1703120.v new file mode 100644 index 000000000..73bbdb79d --- /dev/null +++ b/ivtest/ivltests/pr1703120.v @@ -0,0 +1,31 @@ +module top; + integer ival; + real rval; + initial begin + $display("--- Printing as real ---"); + $display("1/0 is %f. (Should be 0 -- x prints as 0)", 1/0); + $display("1/0.0 is %f. (Should be inf)", 1/0.0); + $display("1.0/0 is %f. (Should be inf)", 1.0/0); + $display("1.0/0.0 is %f. (should be inf)", 1.0/0.0); + + // Moving these two lines before the previous four lines makes 1/0 print + // a large number, but not inf! + rval = 0.0; + ival = 0; + $display("1/integer zero is %f. (Should be 0 -- x prints as 0)", 1/ival); + $display("1/real zero is %f. (should be inf)", 1/rval); + $display("1.0/integer zero is %f. (Should be inf)", 1.0/ival); + $display("1.0/real zero is %f.", 1.0/rval); + + $display("\n--- Printing as integer ---"); + $display("1/0 is %d (Should be x)", 1/0); + $display("1/0.0 is %d", 1/0.0); + $display("1.0/0 is %d", 1.0/0); + $display("1.0/0.0 is %d", 1.0/0.0); + + $display("1/integer zero is %d. (Should be x)", 1/ival); + $display("1/real zero is %d.", 1/rval); + $display("1.0/integer zero is %d.", 1.0/ival); + $display("1.0/real zero is %d.", 1.0/rval); + end +endmodule diff --git a/ivtest/ivltests/pr1703346.v b/ivtest/ivltests/pr1703346.v new file mode 100644 index 000000000..f3fd56d54 --- /dev/null +++ b/ivtest/ivltests/pr1703346.v @@ -0,0 +1,27 @@ +module main; + + wire [1:0] foo [0:1]; + + assign (highz0, strong1) foo[0] = 2'b01; + assign (strong0, highz1) foo[0] = 2'b01; + + assign (highz0, strong1) foo[1] = 2'b10; + assign (strong0, highz1) foo[1] = 2'b10; + + initial begin + #1 $display("foo[0] = %b, foo[1] = %b", foo[0], foo[1]); + + if (foo[0] !== 2'b01) begin + $display("FAILED -- foo[0] = %b", foo[0]); + $finish; + end + + if (foo[1] !== 2'b10) begin + $display("FAILED == foo[1] = %b", foo[1]); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/pr1703959.v b/ivtest/ivltests/pr1703959.v new file mode 100644 index 000000000..a98917988 --- /dev/null +++ b/ivtest/ivltests/pr1703959.v @@ -0,0 +1,26 @@ +// pr1703959 + +module test(); + ma ia (.IO(b), .ZI(c)); + mb ib( .b({b}), .c({c})); +// mb ib( .b(b), .c(c)); + + initial #10 $display("PASSED"); +endmodule + +module ma(ZI,IO); + inout ZI; + inout IO; + + pmos (ZI, IO, 1'b0); +// pmos (IO, ZI, 1'b0); +endmodule + +module mb ( b, c); +// input b; + output b; + input c; +// inout b; +// inout c; + +endmodule // mb diff --git a/ivtest/ivltests/pr1704013.v b/ivtest/ivltests/pr1704013.v new file mode 100644 index 000000000..b3d89c219 --- /dev/null +++ b/ivtest/ivltests/pr1704013.v @@ -0,0 +1,19 @@ +module top; + reg clk = 0; + reg [1:0] in = 2'b00; + wire [1:0] out; + + test t1 (clk, out, in); +endmodule + +module test(clk, a, b); +input clk; +output a; +input [1:0] b; + +reg [1:0] a; + +always @(posedge clk) begin + a <= b; +end +endmodule diff --git a/ivtest/ivltests/pr1704726a.v b/ivtest/ivltests/pr1704726a.v new file mode 100644 index 000000000..4fb6f2ad5 --- /dev/null +++ b/ivtest/ivltests/pr1704726a.v @@ -0,0 +1,89 @@ +module top; + + /*********** + * Check parameters. + ***********/ + // Check parameter/parameter name issues. + parameter name_pp = 1; + parameter name_pp = 0; + + parameter name_pl = 1; + localparam name_pl = 0; + + localparam name_lp = 0; + parameter name_lp = 1; + + localparam name_ll = 1; + localparam name_ll = 0; + + /*********** + * Check genvars. + ***********/ + // Check genvar/genvar name issues. + genvar name_vv; + genvar name_vv; + + /*********** + * Check tasks. + ***********/ + // Check task/task name issues. + task name_tt; + $display("FAILED in task name_tt(a)"); + endtask + task name_tt; + $display("FAILED in task name_tt(b)"); + endtask + + // Check that task/task checks work in a generate block. + generate + begin: task_blk + task name_tt; + $display("FAILED in task name_tt(a)"); + endtask + task name_tt; + $display("FAILED in task name_tt(b)"); + endtask + end + endgenerate + + /*********** + * Check functions. + ***********/ + // Check function/function name issues. + function name_ff; + input in; + name_ff = in; + endfunction + function name_ff; + input in; + name_ff = 2*in; + endfunction + + // Check that function/function checks work in a generate block. + generate + begin: task_blk + function name_ff; + input in; + name_ff = in; + endfunction + function name_ff; + input in; + name_ff = 2*in; + endfunction + end + endgenerate + + /*********** + * Check named events + ***********/ + // Check named event/named event name issues. + event name_ee; + event name_ee; + + initial name_tt; + + specify + specparam name_ss = 1; + specparam name_ss = 0; + endspecify +endmodule diff --git a/ivtest/ivltests/pr1704726b.v b/ivtest/ivltests/pr1704726b.v new file mode 100644 index 000000000..90e60fefd --- /dev/null +++ b/ivtest/ivltests/pr1704726b.v @@ -0,0 +1,130 @@ +module top; + reg pass = 1'b1; + parameter parm = 1; + + /*********** + * Check generate tasks. + ***********/ + // Only one is created. + generate + if (parm) begin: name_ti + task name_task; + $display("OK in task from scope name_ti"); + endtask + end else begin: name_ti + task name_task; + begin + $display("FAILED in task from scope name_ti"); + pass = 1'b0; + end + endtask + end + endgenerate + + // Again only one is created. + generate + case (parm) + 1: begin: name_tc + task name_task; + $display("OK in task from scope name_tc"); + endtask + end + default: begin: name_tc + task name_task; + begin + $display("FAILED in task from scope name_tc"); + pass = 1'b0; + end + endtask + end + endcase + endgenerate + + // Two are created, but they are in a different scope. + genvar lpt; + + generate + for (lpt = 0; lpt < 2; lpt = lpt + 1) begin: name_tf + task name_task; + $display("OK in task from scope name_tf[%0d]", lpt); + endtask + end + endgenerate + + /*********** + * Check functions. + ***********/ + // Only one is created. + generate + if (parm) begin: name_fi + function name_func; + input in; + name_func = ~in; + endfunction + end else begin: name_fi + function name_func; + input in; + name_func = in; + endfunction + end + endgenerate + + // Again only one is created. + generate + case (parm) + 1: begin: name_fc + function name_func; + input in; + name_func = ~in; + endfunction + end + default: begin: name_fc + function name_func; + input in; + name_func = in; + endfunction + end + endcase + endgenerate + + // Two are created, but they are in a different scope. + genvar lpf; + + generate + for (lpf = 0; lpf < 2; lpf = lpf + 1) begin: name_ff + function name_func; + input in; + name_func = (lpf % 2) ? in : ~in ; + endfunction + end + endgenerate + + initial begin + name_ti.name_task; + name_tc.name_task; + name_tf[0].name_task; + name_tf[1].name_task; + + if (name_fi.name_func(1'b1) !== 1'b0) begin + $display("FAILED in function from scope name_fi"); + pass = 1'b0; + end else $display("OK in function from scope name_fi"); + + if (name_fc.name_func(1'b1) !== 1'b0) begin + $display("FAILED in function from scope name_fc"); + pass = 1'b0; + end else $display("OK in function from scope name_fc"); + + if (name_ff[0].name_func(1'b1) !== 1'b0) begin + $display("FAILED in function from scope name_ff[0]"); + pass = 1'b0; + end else $display("OK in function from scope name_ff[0]"); + + if (name_ff[1].name_func(1'b1) !== 1'b1) begin + $display("FAILED in function from scope name_ff[1]"); + pass = 1'b0; + end else $display("OK in function from scope name_ff[1]"); + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1704726c.v b/ivtest/ivltests/pr1704726c.v new file mode 100644 index 000000000..9c9647b49 --- /dev/null +++ b/ivtest/ivltests/pr1704726c.v @@ -0,0 +1,600 @@ +module top; + parameter parm = 1; + + parameter name_v = 1; // genvar + localparam name_lpv = 0; // genvar + + parameter name_t = 1; // task + parameter name_f = 1; // function + parameter name_i = 1; // module instance + parameter name_b = 1; // named block + parameter name_gl = 1; // generate block loop + parameter name_gi = 1; // generate block if + parameter name_gc = 1; // generate block case + parameter name_gb = 1; // generate block + parameter name_e = 1; // named event + parameter name_s = 1; // signal + + wire [1:0] out; + + /*********** + * Check genvars + ***********/ + // Check genvar/parameter name issues. + genvar name_v; + generate + for (name_v = 0; name_v < 2; name_v = name_v + 1) begin + assign out[name_v] = name_v; + end + endgenerate + + // Check genvar/localparam name issues. + genvar name_lpv; + generate + for (name_lpv = 0; name_lpv < 2; name_lpv = name_lpv + 1) begin + assign out[name_lpv] = name_lpv; + end + endgenerate + + // Check genvar/genvar name issues. + // This is in a different file since this fails during parsing. + + /*********** + * Check tasks. + ***********/ + // Check task/parameter name issues. + task name_t; + $display("FAILED in task name_t"); + endtask + + // Check task/task name issues. + // This is in a different file since this fails during parsing. + + // Check task/genvar name issues. + genvar name_tv; + generate + for (name_tv = 0; name_tv < 2; name_tv = name_tv + 1) begin + assign out[name_tv] = name_tv; + end + endgenerate + task name_tv; + $display("FAILED in task name_tv"); + endtask + + /*********** + * Check functions. + ***********/ + // Check function/parameter name issues. + function name_f; + input in; + name_f = in; + endfunction + + // Check function/task name issues. + task name_ft; + $display("FAILED in task name_ft"); + endtask + function name_ft; + input in; + name_tf = in; + endfunction + + // Check function/function name issues. + // This is in a different file since this fails during parsing. + + // Check function/genvar name issues. + genvar name_fv; + generate + for (name_fv = 0; name_fv < 2; name_fv = name_fv + 1) begin + assign out[name_fv] = name_fv; + end + endgenerate + function name_fv; + input in; + name_fv = in; + endfunction + + /*********** + * Check module instances. + ***********/ + // Check modul instance/parameter name issues. + test name_i(out[0]); + + // Check module instance/task name issues. + task name_it; + $display("FAILED in task name_it"); + endtask + test name_it(out[0]); + + // Check module instance/function name issues. + function name_if; + input in; + name_if = in; + endfunction + test name_if(out[0]); + + // Check module instance/genvar name issues. + genvar name_iv; + generate + for (name_iv = 0; name_iv < 2; name_iv = name_iv + 1) begin + assign out[name_iv] = name_iv; + end + endgenerate + test name_iv(out[1]); + + // Check module instance/module instance name issues. + test name_ii(out[0]); + test name_ii(out[1]); + + /*********** + * Check named blocks. + ***********/ + // Check named block/parameter name issues. + initial begin: name_b + $display("FAILED in name_b"); + end + + // Check named block/task name issues. + task name_bt; + $display("FAILED in task name_bt"); + endtask + initial begin: name_bt + $display("FAILED in name_bt"); + end + + // Check named block/function name issues. + function name_bf; + input in; + name_bf = in; + endfunction + initial begin: name_bf + $display("FAILED in name_bf"); + end + + // Check named block/genvar name issues. + genvar name_bv; + generate + for (name_bv = 0; name_bv < 2; name_bv = name_bv + 1) begin + assign out[name_bv] = name_bv; + end + endgenerate + initial begin: name_bv + $display("FAILED in name_bv"); + end + + // Check named block/module instance name issues. + test name_bi(out[0]); + initial begin: name_bi + $display("FAILED in name_bi"); + end + + // Check named block/named block name issues. + initial begin: name_bb + $display("FAILED in name_bb(a)"); + end + initial begin: name_bb + $display("FAILED in name_bb(b)"); + end + + /*********** + * Check named events + ***********/ + // Check named event/parameter name issues. + event name_e; + + // Check named event/task name issues. + task name_et; + $display("FAILED in task name_et"); + endtask + event name_et; + + // Check named event/function name issues. + function name_ef; + input in; + name_ef = in; + endfunction + event name_ef; + + // Check named event/genvar name issues. + genvar name_ev; + generate + for (name_ev = 0; name_ev < 2; name_ev = name_ev + 1) begin + assign out[name_ev] = name_ev; + end + endgenerate + event name_ev; + + // Check named event/module instance name issues. + test name_ei(out[0]); + event name_ei; + + // Check named event/named block name issues. + initial begin: name_eb + $display("FAILED in name_eb"); + end + event name_eb; + + // Check named event/named event name issues. + // This is in a different file since this fails during parsing. + + /*********** + * Check generate loop blocks + ***********/ + genvar i; + // Check generate loop/parameter name issues. + generate + for (i = 0; i < 2; i = i + 1) begin: name_gl + assign out[i] = i; + end + endgenerate + + // Check generate loop/task name issues. + task name_glt; + $display("FAILED in task name_glt"); + endtask + generate + for (i = 0; i < 2; i = i + 1) begin: name_glt + assign out[i] = i; + end + endgenerate + + // Check generate loop/function name issues. + function name_glf; + input in; + name_glf = in; + endfunction + generate + for (i = 0; i < 2; i = i + 1) begin: name_glf + assign out[i] = i; + end + endgenerate + + // Check generate loop/genvar name issues. + genvar name_glv; + generate + for (name_glv = 0; name_glv < 2; name_glv = name_glv + 1) begin + assign out[name_glv] = name_glv; + end + endgenerate + generate + for (i = 0; i < 2; i = i + 1) begin: name_glv + assign out[i] = i; + end + endgenerate + + // Check generate loop/module instance name issues. + test name_gli(out[0]); + generate + for (i = 0; i < 2; i = i + 1) begin: name_gli + assign out[i] = i; + end + endgenerate + + // Check generate loop/named block name issues. + initial begin: name_glb + $display("FAILED in name_glb"); + end + generate + for (i = 0; i < 2; i = i + 1) begin: name_glb + assign out[i] = i; + end + endgenerate + + // Check generate loop/named event name issues. + event name_gle; + generate + for (i = 0; i < 2; i = i + 1) begin: name_gle + assign out[i] = i; + end + endgenerate + + // Check generate loop/generate loop name issues. + generate + for (i = 0; i < 2; i = i + 1) begin: name_glgl + assign out[i] = i; + end + endgenerate + generate + for (i = 0; i < 2; i = i + 1) begin: name_glgl + assign out[i] = i; + end + endgenerate + + /*********** + * Check generate if blocks + ***********/ + // Check generate if/parameter name issues. + generate + if (parm == 1) begin: name_gi + assign out[1] = 1; + end + endgenerate + + // Check generate if/task name issues. + task name_git; + $display("FAILED in task name_git"); + endtask + generate + if (parm == 1) begin: name_git + assign out[1] = 1; + end + endgenerate + + // Check generate if/function name issues. + function name_gif; + input in; + name_gif = in; + endfunction + generate + if (parm == 1) begin: name_gif + assign out[1] = 1; + end + endgenerate + + // Check generate if/genvar name issues. + genvar name_giv; + generate + for (name_giv = 0; name_giv < 2; name_giv = name_giv + 1) begin + assign out[name_giv] = name_giv; + end + endgenerate + generate + if (parm == 1) begin: name_giv + assign out[1] = 1; + end + endgenerate + + // Check generate if/module instance name issues. + test name_gii(out); + generate + if (parm == 1) begin: name_gii + assign out[1] = 1; + end + endgenerate + + // Check generate if/named block name issues. + initial begin: name_gib + $display("FAILED in name_gib"); + end + generate + if (parm == 1) begin: name_gib + assign out[1] = 1; + end + endgenerate + + // Check generate if/named event name issues. + event name_gie; + generate + if (parm == 1) begin: name_gie + assign out[1] = 1; + end + endgenerate + + // Check generate if/generate if name issues. + generate + if (parm == 1) begin: name_gigi + assign out[1] = 1; + end + endgenerate + generate + if (parm == 1) begin: name_gigi + assign out[1] = 0; + end + endgenerate + + /*********** + * Check generate case blocks + ***********/ + // Check generate case/parameter name issues. + generate + case (parm) + 1: begin: name_gc + assign out[1] = 1; + end + default: begin: name_gc + assign out[1] = 0; + end + endcase + endgenerate + + // Check generate case/task name issues. + task name_gct; + $display("FAILED in task name_gct"); + endtask + generate + case (parm) + 1: begin: name_gct + assign out[1] = 1; + end + default: begin: name_gct + assign out[1] = 0; + end + endcase + endgenerate + + // Check generate case/function name issues. + function name_gcf; + input in; + name_gcf = in; + endfunction + generate + case (parm) + 1: begin: name_gcf + assign out[1] = 1; + end + default: begin: name_gcf + assign out[1] = 0; + end + endcase + endgenerate + + // Check generate case/genvar name issues. + genvar name_gcv; + generate + for (name_gcv = 0; name_gcv < 2; name_gcv = name_gcv + 1) begin + assign out[name_gcv] = name_gcv; + end + endgenerate + generate + case (parm) + 1: begin: name_gcv + assign out[1] = 1; + end + default: begin: name_gcv + assign out[1] = 0; + end + endcase + endgenerate + + // Check generate case/module instance name issues. + test name_gci(out[0]); + generate + case (parm) + 1: begin: name_gci + assign out[1] = 1; + end + default: begin: name_gci + assign out[1] = 0; + end + endcase + endgenerate + + // Check generate case/named block name issues. + initial begin: name_gcb + $display("FAILED in name_gcb"); + end + generate + case (parm) + 1: begin: name_gcb + assign out[1] = 1; + end + default: begin: name_gcb + assign out[1] = 0; + end + endcase + endgenerate + + // Check generate case/named event name issues. + event name_gce; + generate + case (parm) + 1: begin: name_gce + assign out[1] = 1; + end + default: begin: name_gce + assign out[1] = 0; + end + endcase + endgenerate + + // Check generate case/generate case name issues. + generate + case (parm) + 1: begin: name_gcgc + assign out[1] = 1; + end + default: begin: name_gcgc + assign out[1] = 0; + end + endcase + endgenerate + generate + case (parm) + 1: begin: name_gcgc + assign out[1] = 1; + end + default: begin: name_gcgc + assign out[1] = 0; + end + endcase + endgenerate + + /*********** + * Check generate blocks (from 1364-2001) + ***********/ + // Check generate block/parameter name issues. + generate + begin: name_gb + assign out[0] = 0; + end + endgenerate + + // Check generate block/task name issues. + task name_gbt; + $display("FAILED in task name_gbt"); + endtask + generate + begin: name_gbt + assign out[0] = 0; + end + endgenerate + + // Check generate block/function name issues. + function name_gbf; + input in; + name_gbf = in; + endfunction + generate + begin: name_gbf + assign out[0] = 0; + end + endgenerate + + // Check generate block/genvar name issues. + genvar name_gbv; + generate + for (name_gbv = 0; name_gbv < 2; name_gbv = name_gbv + 1) begin + assign out[name_gbv] = name_gbv; + end + endgenerate + generate + begin: name_gbv + assign out[0] = 0; + end + endgenerate + + // Check generate block/module instance name issues. + test name_gbi(out[0]); + generate + begin: name_gbi + assign out[0] = 0; + end + endgenerate + + // Check generate block/named block name issues. + initial begin: name_gbb + $display("FAILED in name_gbb"); + end + generate + begin: name_gbb + assign out[0] = 0; + end + endgenerate + + // Check generate case/named event name issues. + event name_gbe; + generate + begin: name_gbe + assign out[0] = 0; + end + endgenerate + + // Check generate case/generate case name issues. + generate + begin: name_gbgb + assign out[0] = 0; + end + endgenerate + generate + begin: name_gbgb + assign out[0] = 0; + end + endgenerate + + initial $display("FAILED"); +endmodule + +module test(out); + output out; + reg out = 1'b0; +endmodule diff --git a/ivtest/ivltests/pr1704726d.v b/ivtest/ivltests/pr1704726d.v new file mode 100644 index 000000000..424b2219d --- /dev/null +++ b/ivtest/ivltests/pr1704726d.v @@ -0,0 +1,94 @@ +module top; + parameter parm = 1; + + parameter name0_s = 1; // signal + + wire [1:0] out; + + /*********** + * Check signals + ***********/ + // Check signal/parameter name issues. + wire name0_s; + + // Check signal/genvar name issues. + genvar name0_v; + generate + for (name0_v = 0; name0_v < 2; name0_v = name0_v + 1) begin + assign out[name0_v] = name0_v; + end + endgenerate + wire name0_v; + + // Check signal/task name issues. + task name1_st; + $display("FAILED in task name1_st"); + endtask + wire name1_st; + + // Check signal/function name issues. + function name2_sf; + input in; + name2_sf = in; + endfunction + wire name2_sf; + + // Check signal/module instance name issues. + test name3_si(out[0]); + wire name3_si; + + // Check signal/named block name issues. + initial begin: name4_sb + $display("FAILED in name4_sb"); + end + wire name4_sb; + + // Check signal/named event name issues. + event name5_se; + wire name5_se; + + // Check signal/generate loop name issues. + genvar i; + generate + for (i = 0; i < 2 ; i = i + 1) begin: name6_sgl + assign out[i] = i; + end + endgenerate + wire name6_sgl; + + // Check signal/generate if name issues. + generate + if (parm == 1) begin: name7_sgi + assign out[1] = 1; + end + endgenerate + wire name7_sgi; + + // Check signal/generate case name issues. + generate + case (parm) + 1: begin: name8_sgc + assign out[1] = 1; + end + default: begin: name8_sgc + assign out[1] = 0; + end + endcase + endgenerate + wire name8_sgc; + + // Check signal/generate block name issues. + generate + begin: name9_sgb + assign out[0] = 0; + end + endgenerate + wire name9_sgb; + + initial $display("FAILED"); +endmodule + +module test(out); + output out; + reg out = 1'b0; +endmodule diff --git a/ivtest/ivltests/pr1705027.v b/ivtest/ivltests/pr1705027.v new file mode 100644 index 000000000..5368c5f24 --- /dev/null +++ b/ivtest/ivltests/pr1705027.v @@ -0,0 +1,8 @@ +module test(); +// wire r; +a ua ( .r ( !r )); +endmodule + +module a ( r ); +input r; +endmodule diff --git a/ivtest/ivltests/pr1716276.v b/ivtest/ivltests/pr1716276.v new file mode 100644 index 000000000..0989c8a61 --- /dev/null +++ b/ivtest/ivltests/pr1716276.v @@ -0,0 +1,68 @@ +/* + This incorrect code causes iverilog 20070421 and earlier to dump core. + + $ iverilog -t null empty_param.v + Segmentation Fault - core dumped + */ + +module param_test (clk, reset_n, test_expr); + parameter severity_level = 1; + parameter width = 32; + parameter property_type = 0; + + input clk, reset_n; + input [width-1:0] test_expr; + +endmodule + +module empty_param; + reg clk; + reg [3:0] fsm; + + // An empty parameter like is easy to cause with an undefined macro + // expanding to null + + param_test #( , 4) submod(clk, 1'b1, fsm); + + initial begin + if (submod.severity_level !== 1) begin + $display("FAILED -- severity_level = %d", submod.severity_level); + $finish; + end + + if (submod.width !== 4) begin + $display("FAILED -- width = %d", submod.width); + $finish; + end + + if (submod.property_type !== 0) begin + $display("FAILED -- property_type = %d", submod.property_type); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin + +endmodule + + + +/* Copyright (C) 1999 Stephen G. Tell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * n + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + * + */ diff --git a/ivtest/ivltests/pr1717361.v b/ivtest/ivltests/pr1717361.v new file mode 100644 index 000000000..a7f1b378a --- /dev/null +++ b/ivtest/ivltests/pr1717361.v @@ -0,0 +1,29 @@ +module adding; + +reg signed [20:0] s3, s4; +reg signed [21:0] t1, t2; +reg clk; +initial begin + clk=0; + s3=+400000; + s4=+200000; + #10; + clk=1; + #10; + $display("%d %d", t1, t2); + clk=0; + s3=-400000; + s4=-200000; + #10; + clk=1; + #10; + $display("%d %d", t1, t2); + $display("%s", (t1==t2) ? "PASSED" : "FAIL"); +end + +always @(posedge clk) begin + t1 <= s3 + 2*s4; + t2 <= s3 + s4*2; +end + +endmodule diff --git a/ivtest/ivltests/pr1719055.v b/ivtest/ivltests/pr1719055.v new file mode 100644 index 000000000..681e0af9e --- /dev/null +++ b/ivtest/ivltests/pr1719055.v @@ -0,0 +1,52 @@ +module array_assign(); + parameter MSB = 1; + integer ii; + reg signed [2:0] ar_reg[0:MSB]; + wire signed [4:0] as_wr; + + // compiled with "-g2 -g2x" + // FAILED at this line + assign as_wr = {{2{ar_reg[0][2]}},ar_reg[1]}; + + always @(as_wr) + for(ii=0; ii<(MSB+1); ii=ii+1) + begin + $display(" %t ar_reg=%0d w_assign=%0d", $time, ar_reg[ii], as_wr); + $display(" %t ar_reg[0]=3'b%3b ar_reg[1]=3'b%3b", $time, ar_reg[0], ar_reg[1]); + $display(" %t as_wr=5'b%5b", $time, as_wr); + end + + initial + begin + $display("\n*** module %m **************************************"); + + #10; + for(ii=0; ii<(MSB+1); ii=ii+1) + ar_reg[ii] <= 3'sd1; + #10; + for(ii=0; ii<(MSB+1); ii=ii+1) + ar_reg[ii] <= 3'sd0; + + $display("\n\n"); + end + +endmodule + +/* expected output - START +module array_assign + 10 ar_reg=1 w_assign=1 + 10 ar_reg[0]=3'b001 ar_reg[1]=3'b001 + 10 as_wr=5'b00001 + 10 ar_reg=1 w_assign=1 + 10 ar_reg[0]=3'b001 ar_reg[1]=3'b001 + 10 as_wr=5'b00001 + + + + 20 ar_reg=0 w_assign=0 + 20 ar_reg[0]=3'b000 ar_reg[1]=3'b000 + 20 as_wr=5'b00000 + 20 ar_reg=0 w_assign=0 + 20 ar_reg[0]=3'b000 ar_reg[1]=3'b000 + 20 as_wr=5'b00000 +expected output - END */ diff --git a/ivtest/ivltests/pr1723367.v b/ivtest/ivltests/pr1723367.v new file mode 100644 index 000000000..a1e57a70a --- /dev/null +++ b/ivtest/ivltests/pr1723367.v @@ -0,0 +1,310 @@ +/** + * Author: Evan Lavelle, Riverside Machines Ltd. + * Version: 0.1 (2007-05-22) + * Licence: This code is released into the public domain. + * + * Test implicit Verilog-95 style ports. According to 12.3.2 of the 2005 + * LRM: + * + * "The port reference for each port in the list of ports at the top of each + * module declaration can be one of the following: + * + * A simple identifier or escaped identifier + * A bit-select of a vector declared within the module + * A part-select of a vector declared within the module + * A concatenation of any of the above + * + * The port expression is optional because ports can be defined that do not + * connect to anything internal to the module." + * + * The expected output is: + * + * sum[ 1] = 0101010101100000 + * sum[ 2] = 0101010101100000 + * sum[ 3] = 0101010101100000 + * sum[ 4] = 0101010101100000 + * sum[ 5] = 0101010101100000 + * sum[ 6] = 0101010101100000 + * sum[ 7] = 0101010101100000 + * sum[ 8] = 0101010101100000 + * sum[ 9] = 0101010101100000 + * sum[ 10] = 0101010101100000 + * sum[ 11] = 0101010101100000 + * sum[ 12] = 0101010101100000 + * sum[ 13] = 0101010101100000 + * sum[ 14] = 0101010101100000 + * sum[ 15] = 0101010101100000 + * sum[ 16] = 0101010101100000 + * sum[ 17] = 0101010101100000 + * sum[ 18] = 0101010101100000 + * sum[ 19] = 0101010101100000 + * sum[ 20] = 0101010101100000 + * sum[ 21] = 0101010101100000 + * sum[ 22] = 0101010101100000 + * sum[ 23] = 0101010101100000 + * + */ +module test; + + reg [15:0] sum[23:1]; + wire [7:0] data = 1; + wire dummy1, dummy2; + wire [15:0] wire5, wire9, wire13, wire17, wire21; + + initial + main; + + task main; + integer i; + begin + for(i=1; i<=23; i=i+1) + sum[i] = 'h555f; + #2; + + sum[5] = wire5; + sum[9] = wire9; + sum[13] = wire13; + sum[17] = wire17; + sum[21] = wire21; + + for(i=1; i<=23; i=i+1) + $display("sum[%d] = %b", i, sum[i]); + end + endtask + + m1 m1(); + m2 m2(dummy1, dummy2); + m3 m3(dummy1, , dummy2); + + m4 m4(data); + m5 m5(data, wire5); + m6 m6(dummy1, data); + m7 m7(data, ); + + m8 m8 (data); + m9 m9 (data, wire9); + m10 m10( , data); + m11 m11(data, ); + + m12 m12(data[0]); + m13 m13(data[0], wire13); + m14 m14( , data[0]); + m15 m15(data[0], ); + + m16 m16(data); + m17 m17(data, wire17); + m18 m18(dummy1, data); + m19 m19(data, ); + + m20 m20(data); + m21 m21(data, wire21); + m22 m22(dummy1, data); + m23 m23(data, ); + +endmodule + +/* ---------------------------------------------------------------------------- + * the test modules + * ------------------------------------------------------------------------- */ + +// 95, no ports +module m1; + initial #1 test.sum[1] = test.sum[1] + test.data; +endmodule + +// 95, two ports, but neither has an internal connection +module m2(,); + initial #1 test.sum[2] = test.sum[2] + test.data; +endmodule + +// 95, three ports, but none have an internal connection +module m3(,,); + initial #1 test.sum[3] = test.sum[3] + test.data; +endmodule + +/* ---------------------------------------------------------------------------- + * 95, one and two ports, with implicit and simple identifiers + * ------------------------------------------------------------------------- */ + +// 95, one implicit port, simple identifier +module m4(a); + input a; + wire [7:0] a; + initial #1 test.sum[4] = test.sum[4] + a; +endmodule + +// 95, two implicit ports, simple identifiers +module m5(a, b); + input a; + output b; + wire [7:0] a; + reg [15:0] b; + initial #1 b <= test.sum[5] + a; +endmodule + +// 95, two ports; the first has no internal connection; the second is implicit/ +// simple +module m6(,a); + input a; + wire [7:0] a; + initial #1 test.sum[6] = test.sum[6] + a; +endmodule + +// 95, two ports; the second has no internal connection; the first is implicit/ +// simple +module m7(a,); + input a; + wire [7:0] a; + initial #1 test.sum[7] = test.sum[7] + a; +endmodule + +/* ---------------------------------------------------------------------------- + * 95, one and two ports, with implicit and extended identifiers + * ------------------------------------------------------------------------- */ + +// 95, one implicit port, extended identifier +module m8(\a ); + input \a ; + wire [7:0] \a ; + initial #1 test.sum[8] = test.sum[8] + \a ; +endmodule + +// 95, two implicit ports, extended identifiers +module m9(\a , \b ); + input \a ; + output \b ; + wire [7:0] \a ; + reg [15:0] \b ; + initial #1 \b = test.sum[9] + \a ; +endmodule + +// 95, two ports; the first has no internal connection; the second is implicit/ +// extended +module m10(,\a ); + input \a ; + wire [7:0] \a ; + initial #1 test.sum[10] = test.sum[10] + \a ; +endmodule + +// 95, two ports; the second has no internal connection; the first is implicit/ +// extended +module m11(\a ,); + input \a ; + wire [7:0] \a ; + initial #1 test.sum[11] = test.sum[11] + \a ; +endmodule + +/* ---------------------------------------------------------------------------- + * 95, one and two ports, with implicit and vector bit-select ports + * ------------------------------------------------------------------------- */ + +// 95, one implicit port, vector bit-select +module m12(a[0]); + input a; + wire [7:0] a; + initial #1 test.sum[12] = test.sum[12] + {test.data[7:1], a[0]}; +endmodule + +// 95, two implicit ports, vector bit-selects. the output is actually a part +// select, since ISE core dumps on the assign below, and doing anything +// else in -95 is difficult +module m13(a[0], b[15:0]); + input a; + output b; + wire [7:0] a; + reg [31:0] b; + reg [15:0] temp; + +// assign test.wire13[15:1] = temp[15:1]; // drives the rest of wire13 + + initial begin + #1 temp = test.sum[13] + {test.data[7:1], a[0]}; + b = temp; // drives wire13[0] + end +endmodule + +// 95, two ports; the first has no internal connection; the second is implicit/ +// vector bit-select +module m14(,a[0]); + input [7:0] a; + initial #1 test.sum[14] = test.sum[14] + {test.data[7:1], a[0]}; +endmodule + +// 95, two ports; the second has no internal connection; the first is implicit/ +// vector bit-select +module m15(a[0],); + input [7:0] a; + initial #1 test.sum[15] = test.sum[15] + {test.data[7:1], a[0]}; +endmodule + +/* ---------------------------------------------------------------------------- + * 95, one and two ports, with implicit and vector part-select ports + * ------------------------------------------------------------------------- */ + +// 95, one implicit port, vector bit-select +module m16(a[7:0]); + input a; + wire [15:0] a; + initial #1 test.sum[16] = test.sum[16] + {8'h00, a[7:0]}; +endmodule + +// 95, two implicit ports, vector bit-selects +module m17(a[7:0], b[15:0]); + input a; + output b; + wire [7:0] a; + reg [31:0] b; + initial #1 b[15:0] = test.sum[17] + a; +endmodule + +// 95, two ports; the first has no internal connection; the second is implicit/ +// vector part-select +module m18(,a[7:0]); + input [15:0] a; + initial #1 test.sum[18] = test.sum[18] + {8'h00, a[7:0]}; +endmodule + +// 95, two ports; the second has no internal connection; the first is implicit/ +// vector part-select +module m19(a[7:0],); + input [15:0] a; +// initial #1 test.sum[19] = test.sum[19] + a; + initial #1 test.sum[19] = test.sum[19] + {8'h00, a[7:0]}; +endmodule + +/* ---------------------------------------------------------------------------- + * 95, one and two ports, with ports which are a concatenation of a bit select + * and a 3-bit part select + * ------------------------------------------------------------------------- */ + +// 95, one implicit port, concatenation +module m20({a[7], a[6:0]}); + input a; + wire [15:0] a; + initial #1 test.sum[20] = test.sum[20] + {8'h00, a[7:0]}; +endmodule + +// 95, two implicit ports, concatenations +module m21({a[7], a[6:0]}, {b[15], b[14:0]}); + input a; + output b; + wire [7:0] a; + reg [15:0] b; + initial #1 b = test.sum[21] + {8'h00, a[7:0]}; +endmodule + +// 95, two ports; the first has no internal connection; the second is implicit/ +// concatenation +module m22(,{a[7], a[6:0]}); + input [15:0] a; + initial #1 test.sum[22] = test.sum[22] + {8'h00, a[7:0]}; +endmodule + +// 95, two ports; the second has no internal connection; the first is implicit/ +// concatenation. note that both modelsim and ISE set the entire sum, and not +// just the top 8 bits, to all x's for 'test.sum[23] = test.sum[23] + a' +module m23({a[7], a[6:0]},); + input a; + wire [15:0] a; + initial #1 test.sum[23] = test.sum[23] + a[7:0]; +endmodule diff --git a/ivtest/ivltests/pr1735724.v b/ivtest/ivltests/pr1735724.v new file mode 100644 index 000000000..5a2f3d718 --- /dev/null +++ b/ivtest/ivltests/pr1735724.v @@ -0,0 +1,12 @@ +module test; + parameter j=0; + + reg [3:0] in [7:0]; + wire [3:0] out [7:0]; + + assign out[(j+1)*4 - 1 : j*4] = in[j]; +// assign out[j] = in[j]; // This is what was probably wanted. + + initial $display("out[0]: %b", out[0]); + +endmodule diff --git a/ivtest/ivltests/pr1735822.v b/ivtest/ivltests/pr1735822.v new file mode 100644 index 000000000..60630b7c9 --- /dev/null +++ b/ivtest/ivltests/pr1735822.v @@ -0,0 +1,24 @@ +module test(); + + reg [0:(8*6)-1] identstr= "PASSED"; + reg [7:0] identdata= 8'b0; + integer i; + + initial + begin +// $dumpfile("indexed_part.vcd"); +// $dumpvars; + end + + initial + begin + for (i=0; i<6; i=i+1) + begin + #10 identdata = identstr[i*8 +:8]; + $write("%c", identdata); + end + $write("\n"); + $finish; + end + +endmodule // test diff --git a/ivtest/ivltests/pr1735836.v b/ivtest/ivltests/pr1735836.v new file mode 100644 index 000000000..83ad0d818 --- /dev/null +++ b/ivtest/ivltests/pr1735836.v @@ -0,0 +1,13 @@ +module top; + wire [1:0] out; + reg [1:0] in1, in2; + + initial begin + $monitor($time,,"out=%d", out); + in1 = 2'd1; + in2 = 2'd2; + #1 force out = in1; + #1 force out = in2; + #1 release out; + end +endmodule diff --git a/ivtest/ivltests/pr1740476b.v b/ivtest/ivltests/pr1740476b.v new file mode 100644 index 000000000..d59848019 --- /dev/null +++ b/ivtest/ivltests/pr1740476b.v @@ -0,0 +1,34 @@ +module main; + + wire [3:0] src [15:0]; + wire [3:0] dst [15:0]; + + genvar i; + for (i = 0 ; i < 16; i = i+1) begin:bb + buffer u (.out(dst[i]), .in(src[i])); + end + + for (i = 0 ; i < 16 ; i = i+1) begin:drv + assign src[i] = i; + end + + integer idx; + initial begin + #1 ; + for (idx = 0 ; idx < 16 ; idx = idx+1) begin + if (dst[idx] !== idx) begin + $display("FAILED -- src[%0d]==%b, dst[%0d]==%b", + idx, src[idx], idx, dst[idx]); + $finish; + end + end + $display("PASSED"); + end + +endmodule // main + +module buffer (input wire [3:0] in, output wire [3:0] out); + + assign out = in; + +endmodule // buffer diff --git a/ivtest/ivltests/pr1741212.v b/ivtest/ivltests/pr1741212.v new file mode 100644 index 000000000..6cfc6272d --- /dev/null +++ b/ivtest/ivltests/pr1741212.v @@ -0,0 +1,502 @@ +`begin_keywords "1364-2005" +/* + * This is a general recreation of the VHDL ieee.math_real package. + */ + +// Constants for use below and for general reference +// TODO: Bring it out to 12 (or more???) places beyond the decimal? +`define MATH_E 2.7182818284 +`define MATH_1_OVER_E 0.3678794411 +`define MATH_PI 3.1415926536 +`define MATH_2_PI 6.2831853071 +`define MATH_1_OVER_PI 0.3183098861 +`define MATH_PI_OVER_2 1.5707963267 +`define MATH_PI_OVER_3 1.0471975511 +`define MATH_PI_OVER_4 0.7853981633 +`define MATH_3_PI_OVER_2 4.7123889803 +`define MATH_LOG_OF_2 0.6931471805 +`define MATH_LOG_OF_10 2.3025850929 +`define MATH_LOG2_OF_E 1.4426950408 +`define MATH_LOG10_OF_E 0.4342944819 +`define MATH_SQRT_2 1.4142135623 +`define MATH_1_OVER_SQRT_2 0.7071067811 +`define MATH_SQRT_PI 1.7724538509 +`define MATH_DEG_TO_RAD 0.0174532925 +`define MATH_RAD_TO_DEG 57.2957795130 + +// The number of iterations to do for the Taylor series approximations +`define EXPLOG_ITERATIONS 50 +`define COS_ITERATIONS 13 + +module math ; + + /* Conversion Routines */ + + // Return the sign of a particular number. + function real sign ; + input real x ; + begin + sign = x < 0.0 ? 1.0 : 0.0 ; + end + endfunction + + // Return the trunc function of a number + function real trunc ; + input real x ; + begin + trunc = x - mod(x,1.0) ; + end + endfunction + + // Return the ceiling function of a number. + function real ceil ; + input real x ; + real retval ; + begin + retval = mod(x,1.0) ; + if( retval != 0.0 && x > 0.0 ) retval = x+1.0 ; + else retval = x ; + ceil = trunc(retval) ; + end + endfunction + + // Return the floor function of a number + function real floor ; + input real x ; + real retval ; + begin + retval = mod(x,1.0) ; + if( retval != 0.0 && x < 0.0 ) retval = x - 1.0 ; + else retval = x ; + floor = trunc(retval) ; + end + endfunction + + // Return the round function of a number + function real round ; + input real x ; + real retval ; + begin + retval = x > 0.0 ? x + 0.5 : x - 0.5 ; + round = trunc(retval) ; + end + endfunction + + // Return the fractional remainder of (x mod m) + function real mod ; + input real x ; + input real m ; + real retval ; + begin + retval = x ; + if( retval > m ) begin + while( retval > m ) begin + retval = retval - m ; + end + end + else begin + while( retval < -m ) begin + retval = retval + m ; + end + end + mod = retval ; + end + endfunction + + // Return the max between two real numbers + function real realmax ; + input real x ; + input real y ; + begin + realmax = x > y ? x : y ; + end + endfunction + + // Return the min between two real numbers + function real realmin ; + input real x ; + input real y ; + begin + realmin = x > y ? y : x ; + end + endfunction + + /* Random Numbers */ + + // Generate Gaussian distributed variables + function real gaussian ; + input real mean ; + input real var ; + real u1, u2, v1, v2, s ; + begin + s = 1.0 ; + while( s >= 1.0 ) begin + // Two random numbers between 0 and 1 + u1 = $random/pow(2.0,32) ; + u2 = $random/pow(2.0,32) ; + // Adjust to be between -1,1 + v1 = 2.0*u1-1.0 ; + v2 = 2.0*u2-1.0 ; + // Polar mag squared + s = v1*v1 + v2*v2 ; + end + gaussian = mean + sqrt(-2.0*log(s)/s) * v1 * sqrt(var) ; + // gaussian2 = mean + sqrt(-2*log(s)/s)*v2 * sqrt(var) ; + end + endfunction + + /* Roots and Log Functions */ + + // Return the square root of a number + function real sqrt ; + input real x ; + real retval ; + begin + // if( x == 0.0 ) retval = 0.0 ; + // else retval = powr(x,0.5) ; + // sqrt = retval ; + sqrt = (x == 0.0) ? 0.0 : powr(x,0.5) ; + end + endfunction + + // Return the cube root of a number + function real cbrt ; + input real x ; + real retval ; + begin + // if( x == 0.0 ) retval = 0.0 ; + // else retval = powr(x,1.0/3.0) ; + // cbrt = retval ; + cbrt = (x == 0.0) ? 0.0 : powr(x,1.0/3.0) ; + end + endfunction + + // Return the absolute value of a real value + function real abs ; + input real x ; + begin + abs = (x > 0.0) ? x : -x ; + end + endfunction + + // Return a real value raised to an integer power + function real pow ; + input real b ; + input integer x ; + integer i ; + integer absx ; + real retval ; + begin + retval = 1.0 ; + absx = abs(x) ; + for( i = 0 ; i < absx ; i = i+1 ) begin + retval = b*retval ; + end + pow = x < 0 ? (1.0/retval) : retval ; + end + endfunction + + // Return a real value raised to a real power + function real powr ; + input real b ; + input real x ; + begin + powr = exp(x*log(b)) ; + end + endfunction + + // Return the evaluation of e^x where e is the natural logarithm base + // NOTE: This is the Taylor series expansion of e^x + function real exp ; + input real x ; + real retval ; + integer i ; + real nm1_fact ; + real powm1 ; + begin + nm1_fact = 1.0 ; + powm1 = 1.0 ; + retval = 1.0 ; + for( i = 1 ; i < `EXPLOG_ITERATIONS ; i = i + 1 ) begin + powm1 = x*powm1 ; + nm1_fact = nm1_fact * i ; + retval = retval + powm1/nm1_fact ; + end + exp = retval ; + end + endfunction + + // Return the evaluation log(x) + function real log ; + input real x ; + integer i ; + real whole ; + real xm1oxp1 ; + real retval ; + real newx ; + begin + retval = 0.0 ; + whole = 0.0 ; + newx = x ; + while( newx > `MATH_E ) begin + whole = whole + 1.0 ; + newx = newx / `MATH_E ; + end + newx = x/pow(`MATH_E,whole) ; + xm1oxp1 = (newx-1.0)/(newx+1.0) ; + for( i = 0 ; i < `EXPLOG_ITERATIONS ; i = i + 1 ) begin + retval = retval + pow(xm1oxp1,2*i+1)/(2.0*i+1.0) ; + end + log = whole+2.0*retval ; + end + endfunction + + // Return the evaluation ln(x) (same as log(x)) + function real ln ; + input real x ; + begin + ln = log(x) ; + end + endfunction + + // Return the evaluation log_2(x) + function real log2 ; + input real x ; + begin + log2 = log(x)/`MATH_LOG_OF_2 ; + end + endfunction + + function real log10 ; + input real x ; + begin + log10 = log(x)/`MATH_LOG_OF_10 ; + end + endfunction + + function real log_base ; + input real x ; + input real b ; + begin + log_base = log(x)/log(b) ; + end + endfunction + + /* Trigonometric Functions */ + + // Internal function to reduce a value to be between [-pi:pi] + function real reduce ; + input real x ; + real retval ; + begin + retval = x ; + if( x > `MATH_PI ) begin + while( retval >= `MATH_PI ) begin + retval = retval - `MATH_PI ; + end + end + else begin + while( retval <= -`MATH_PI ) begin + retval = retval + `MATH_PI ; + end + end + reduce = retval ; + end + endfunction + + // Return the cos of a number in radians + function real cos ; + input real x ; + integer i ; + integer sign ; + real newx ; + real retval ; + real xsqnm1 ; + real twonm1fact ; + begin + newx = reduce(x) ; + xsqnm1 = 1.0 ; + twonm1fact = 1.0 ; + retval = 1.0 ; + for( i = 1 ; i < `COS_ITERATIONS ; i = i + 1 ) begin + sign = -2*(i % 2)+1 ; + xsqnm1 = xsqnm1*newx*newx ; + twonm1fact = twonm1fact * (2.0*i) * (2.0*i-1.0) ; + retval = retval + sign*(xsqnm1/twonm1fact) ; + end + cos = retval ; + end + endfunction + + // Return the sin of a number in radians + function real sin ; + input real x ; + begin + sin = cos(x - `MATH_PI_OVER_2) ; + end + endfunction + + // Return the tan of a number in radians + function real tan ; + input real x ; + begin + tan = sin(x) / cos(x) ; + end + endfunction + + // Return the arcsin in radians of a number + function real arcsin ; + input real x ; + begin + arcsin = 2.0*arctan(x/(1.0+sqrt(1.0-x*x))) ; + end + endfunction + + // Return the arccos in radians of a number + function real arccos ; + input real x ; + begin + arccos = `MATH_PI_OVER_2-arcsin(x) ; + end + endfunction + + // Return the arctan in radians of a number + // TODO: Make sure this REALLY does work as it is supposed to! + function real arctan ; + input real x ; + real retval ; + real y ; + real newx ; + real twoiotwoip1 ; + integer i ; + integer mult ; + begin + retval = 1.0 ; + twoiotwoip1 = 1.0 ; + mult = 1 ; + newx = abs(x) ; + while( newx > 1.0 ) begin + mult = mult*2 ; + newx = newx/(1.0+sqrt(1.0+newx*newx)) ; + end + y = 1.0 ; + for( i = 1 ; i < 2*`COS_ITERATIONS ; i = i + 1 ) begin + y = y*((newx*newx)/(1+newx*newx)) ; + twoiotwoip1 = twoiotwoip1 * (2.0*i)/(2.0*i+1.0) ; + retval = retval + twoiotwoip1*y ; + end + retval = retval * (newx/(1+newx*newx)) ; + retval = retval * mult ; + + arctan = (x > 0.0) ? retval : -retval ; + end + endfunction + + // Return the arctan in radians of a ratio x/y + // TODO: Test to make sure this works as it is supposed to! + function real arctan_xy ; + input real x ; + input real y ; + real retval ; + begin + retval = 0.0 ; + if( x < 0.0 ) retval = `MATH_PI - arctan(-abs(y)/x) ; + else if( x > 0.0 ) retval = arctan(abs(y)/x) ; + else if( x == 0.0 ) retval = `MATH_PI_OVER_2 ; + arctan_xy = (y < 0.0) ? -retval : retval ; + end + endfunction + + /* Hyperbolic Functions */ + + // Return the sinh of a number + function real sinh ; + input real x ; + begin + sinh = (exp(x) - exp(-x))/2.0 ; + end + endfunction + + // Return the cosh of a number + function real cosh ; + input real x ; + begin + cosh = (exp(x) + exp(-x))/2.0 ; + end + endfunction + + // Return the tanh of a number + function real tanh ; + input real x ; + real e2x ; + begin + e2x = exp(2.0*x) ; + tanh = (e2x+1.0)/(e2x-1.0) ; + end + endfunction + + // Return the arcsinh of a number + function real arcsinh ; + input real x ; + begin + arcsinh = log(x+sqrt(x*x+1.0)) ; + end + endfunction + + // Return the arccosh of a number + function real arccosh ; + input real x ; + begin + arccosh = ln(x+sqrt(x*x-1.0)) ; + end + endfunction + + // Return the arctanh of a number + function real arctanh ; + input real x ; + begin + arctanh = 0.5*ln((1.0+x)/(1.0-x)) ; + end + endfunction + + initial begin + $display( "cos(MATH_PI_OVER_3): %f", cos(`MATH_PI_OVER_3) ) ; + $display( "sin(MATH_PI_OVER_3): %f", sin(`MATH_PI_OVER_3) ) ; + $display( "sign(-10): %f", sign(-10) ) ; + $display( "realmax(MATH_PI,MATH_E): %f", realmax(`MATH_PI,`MATH_E) ) ; + $display( "realmin(MATH_PI,MATH_E): %f", realmin(`MATH_PI,`MATH_E) ) ; + $display( "mod(MATH_PI,MATH_E): %f", mod(`MATH_PI,`MATH_E) ) ; + $display( "ceil(-MATH_PI): %f", ceil(-`MATH_PI) ) ; + $display( "ceil(4.0): %f", ceil(4.0) ) ; + $display( "ceil(3.99999999999999): %f", ceil(3.99999999999999) ) ; + $display( "pow(MATH_PI,2): %f", pow(`MATH_PI,2) ) ; + $display( "gaussian(1.0,1.0): %f", gaussian(1.0,1.0) ) ; + $display( "round(MATH_PI): %f", round(`MATH_PI) ) ; + $display( "trunc(-MATH_PI): %f", trunc(-`MATH_PI) ) ; + $display( "ceil(-MATH_PI): %f", ceil(-`MATH_PI) ) ; + $display( "floor(MATH_PI): %f", floor(`MATH_PI) ) ; + $display( "round(e): %f", round(`MATH_E)) ; + $display( "ceil(-e): %f", ceil(-`MATH_E)) ; + $display( "exp(MATH_PI): %f", exp(`MATH_PI) ) ; + $display( "log2(MATH_PI): %f", log2(`MATH_PI) ) ; + $display( "log_base(pow(2,32),2): %f", log_base(pow(2,32),2) ) ; + $display( "ln(0.1): %f", log(0.1) ) ; + $display( "cbrt(7): %f", cbrt(7) ) ; + $display( "cos(%s): %f", ``MATH_2_PI, cos(20*`MATH_2_PI) ) ; + $display( "sin(-%s): %f", ``MATH_2_PI, sin(-50*`MATH_2_PI) ) ; + $display( "sinh(%s): %f", ``MATH_E, sinh(`MATH_E) ) ; + $display( "cosh(%s): %f", ``MATH_2_PI, cosh(`MATH_2_PI) ) ; + $display( "arctan_xy(-4,3): %f", arctan_xy(-4,3) ) ; + $display( "arctan(MATH_PI): %f", arctan(`MATH_PI) ) ; + $display( "arctan(-MATH_E/2): %f", arctan(-`MATH_E/2) ) ; + $display( "arctan(MATH_PI_OVER_2): %f", arctan(`MATH_PI_OVER_2) ) ; + $display( "arctan(1/7) = %f", arctan(1.0/7.0) ) ; + $display( "arctan(3/79) = %f", arctan(3.0/79.0) ) ; + $display( "pi/4 ?= %f", 5*arctan(1.0/7.0)+2*arctan(3.0/79.0) ) ; + $display( "arcsin(1.0): %f", arcsin(1.0) ) ; + $display( "cos(pi/2): %f", cos(`MATH_PI_OVER_2)) ; + $display( "arccos(cos(pi/2)): %f", arccos(cos(`MATH_PI_OVER_2)) ) ; + end + +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr1742910.v b/ivtest/ivltests/pr1742910.v new file mode 100644 index 000000000..bb1a7337d --- /dev/null +++ b/ivtest/ivltests/pr1742910.v @@ -0,0 +1,20 @@ +// pr1742910 + +module checktest(); + + parameter sum = 1'h1 + 1'h1; + + initial begin +`ifdef __ICARUS_UNSIZED__ + if (sum !== 2) begin +`else + if (sum !== 0) begin +`endif + $display("FAILED -- sum = %d", sum); + $finish; + end + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/pr1745005.v b/ivtest/ivltests/pr1745005.v new file mode 100644 index 000000000..9e816a0d1 --- /dev/null +++ b/ivtest/ivltests/pr1745005.v @@ -0,0 +1,37 @@ +`begin_keywords "1364-2005" +// pr1745005 +// +module main; + + reg [31:0] ref; + reg [3:0] addr; + + wire [3:0] out_net1 = ref[{addr,2'b00} +: 4]; + wire [3:0] out_net2 = ref[{addr,2'b11} -: 4]; + reg [3:0] out_reg; + + initial begin + ref = 32'h76543210; + for (addr = 0 ; addr < 8 ; addr = addr+1) begin + #1 ; + out_reg = ref[{addr,2'b00} +: 4]; + if (out_reg !== addr) begin + $display("FAILED -- addr=%d, out_reg=%b", addr, out_reg); + $finish; + end + + if (out_net1 !== addr) begin + $display("FAILED -- addr=%d, out_net1=%b", addr, out_net1); + $finish; + end + + if (out_net2 !== addr) begin + $display("FAILED -- addr=%d, out_net2=%b", addr, out_net2); + $finish; + end + end + $display("PASSED"); + end + +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr1746401.v b/ivtest/ivltests/pr1746401.v new file mode 100644 index 000000000..3ff966fea --- /dev/null +++ b/ivtest/ivltests/pr1746401.v @@ -0,0 +1,23 @@ +module test(); + reg [1:0] array[1:0]; + reg sign; + reg clk = 1'b0; + + always @(posedge clk) + sign = array[1][1]; + + initial begin + array[0] = 1; + array[1] = 2; + + #1 clk = 1; + + #1 if (sign !== 1'b1) begin + $display("FAILED -- array[1][1] = %b, sign=%b", array[1][1], sign); + $finish; + end + + $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/pr1746848.v b/ivtest/ivltests/pr1746848.v new file mode 100644 index 000000000..4818cbff6 --- /dev/null +++ b/ivtest/ivltests/pr1746848.v @@ -0,0 +1,15 @@ +module forBug(); + integer i; + integer j; + + initial + begin + // This loop sets i=4 .. -1 which is an error + for (i=4; i>-1; i=i-1) + $display("i=%d",i); + + // This loop sets j=4 .. 0 which is correct. + for (j=4; j>=0; j=j-1) + $display("j=%d",j); + end +endmodule // forBug diff --git a/ivtest/ivltests/pr1750870.v b/ivtest/ivltests/pr1750870.v new file mode 100644 index 000000000..a6bc4ba37 --- /dev/null +++ b/ivtest/ivltests/pr1750870.v @@ -0,0 +1,21 @@ +// pr1750870 + +module test (FUSE_Q); + + parameter fuse_a_msb = 4; + + parameter fuse_q_msb = (2**(fuse_a_msb+1))-1; + + input [fuse_q_msb:0] FUSE_Q; + + initial begin + $display("fuse_q_msb = %d", fuse_q_msb); + if ($bits(FUSE_Q) != 32) begin + $display("FAILED -- $bits(FUSE_Q) = %d", $bits(FUSE_Q)); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1752353.v b/ivtest/ivltests/pr1752353.v new file mode 100644 index 000000000..828cb1d6e --- /dev/null +++ b/ivtest/ivltests/pr1752353.v @@ -0,0 +1,24 @@ +module test; + + reg [31:0] src; + wire [7:0] tmp; + + subbuf U1 (.out(tmp), .in(src)); + + wire [31:0] dst = {24'h00_00_00, tmp}; + + initial begin + src = 32'h11_22_33_44; + #1 if (dst !== 32'h00_00_00_bb) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule + +module subbuf (output [31:0] out, input[31:0]in); + assign out = ~in; +endmodule // subbuf diff --git a/ivtest/ivltests/pr1752823a.v b/ivtest/ivltests/pr1752823a.v new file mode 100644 index 000000000..f2f81f729 --- /dev/null +++ b/ivtest/ivltests/pr1752823a.v @@ -0,0 +1,10 @@ +module top; + real zero, mzero; + + initial begin + zero = 0.0; + mzero = -1.0 * zero; + + $display("+0=%f and -0=%f.", zero, mzero); + end +endmodule diff --git a/ivtest/ivltests/pr1752823b.v b/ivtest/ivltests/pr1752823b.v new file mode 100644 index 000000000..c1071f06a --- /dev/null +++ b/ivtest/ivltests/pr1752823b.v @@ -0,0 +1,12 @@ +module top; + real zero, mzero, inf, minf; + + initial begin + zero = 0.0; + mzero = -1.0 * zero; + inf = 1/0.0; + minf = -1 * inf; + + $display("+0=%f, -0=%f, inf=%f and minf=%f.", zero, mzero, inf, minf); + end +endmodule diff --git a/ivtest/ivltests/pr1755593.v b/ivtest/ivltests/pr1755593.v new file mode 100644 index 000000000..d3d8fdf44 --- /dev/null +++ b/ivtest/ivltests/pr1755593.v @@ -0,0 +1,74 @@ +// pr1755593 + +module main; + + wire out; + reg [4:0] data; + reg [2:0] sel; + + test U1(out, data[0], data[1], data[2], data[3], sel[0], sel[1]); + + initial begin + for (sel=0 ; sel<4 ; sel=sel+1) + for (data=0 ; data<16 ; data=data+1) begin + #1 if (out !== data[sel]) begin + $display("FAILED -- data=%b, sel=%d", data, sel); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main + +module test (Z, D0, D1, D2, D3, E0, E1); + + output Z; + input D0; + input D1; + input D2; + input D3; + input E0; + input E1; + + u_test I48 (Z, D0, D1, D2, D3, E0, E1); + +endmodule +primitive u_test (Z, D0, D1, D2, D3, E0, E1); + + output Z; + input D0, D1, D2, D3, E0, E1; + + table + + 0 ? ? ? 0 0 : 0 ; + 1 ? ? ? 0 0 : 1 ; + + ? 0 ? ? 1 0 : 0 ; + ? 1 ? ? 1 0 : 1 ; + + ? ? 0 ? 0 1 : 0 ; + ? ? 1 ? 0 1 : 1 ; + + ? ? ? 0 1 1 : 0 ; + ? ? ? 1 1 1 : 1 ; + + 0 0 ? ? x 0 : 0 ; + 1 1 ? ? x 0 : 1 ; + + ? ? 0 0 x 1 : 0 ; + ? ? 1 1 x 1 : 1 ; + + 0 ? 0 ? 0 x : 0 ; + 1 ? 1 ? 0 x : 1 ; + + ? 0 ? 0 1 x : 0 ; + ? 1 ? 1 1 x : 1 ; + + 0 0 0 0 x x : 0 ; + 1 1 1 1 x x : 1 ; + + endtable + +endprimitive diff --git a/ivtest/ivltests/pr1755629.v b/ivtest/ivltests/pr1755629.v new file mode 100644 index 000000000..3791ce5b4 --- /dev/null +++ b/ivtest/ivltests/pr1755629.v @@ -0,0 +1,35 @@ +module test; + + parameter some = 4; + wire [some-1:0] flag1; + + genvar i; + + generate + for (i = 0; i < some; i = i + 1) + begin : what + wire [some-1:0] slice; + end + endgenerate + + generate + for (i = 0; i < some; i = i + 1) + begin : ab + assign what[i].slice[i] = 1'b1; + assign flag1[i] = &what[i].slice; + end + endgenerate + + integer idx; + initial #1 begin + for (idx = 0 ; idx < some ; idx = idx+1) begin + if (flag1[idx] !== 1'bx) begin + $display("FAILED -- flag1=%b", flag1); + $finish; + end + end + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/pr1758122.v b/ivtest/ivltests/pr1758122.v new file mode 100644 index 000000000..26e097b76 --- /dev/null +++ b/ivtest/ivltests/pr1758122.v @@ -0,0 +1,49 @@ +`begin_keywords "1364-2001-noconfig" +// Copyright 2007, Martin Whitaker. +// This code may be freely copied for any purpose. + +module gen_param_test(); + +localparam W = 3; +localparam D = 3; + +reg [W-1:0] A[1:D]; +reg [W-1:0] B[1:D]; +wire [W-1:0] Y[1:D]; + +generate + genvar j; + + for (j = 1; j <= D; j = j + 1) begin:sum + adder #(W) instance(A[j], B[j], Y[j]); + end +endgenerate + +integer i; + +initial begin + for (i = 1; i <= D; i = i + 1) begin + A[i] = i - 1; + B[i] = i + 1; + end + #1; + for (i = 1; i <= D; i = i + 1) begin + $display("%d + %d = %d", A[i-1], B[i-1], Y[i-1]); + end +end + +endmodule + + +module adder #(parameter W = 1) ( + +input wire [W-1:0] A, +input wire [W-1:0] B, +output wire [W-1:0] Y + +); + +assign Y = A + B; + +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr1758135.v b/ivtest/ivltests/pr1758135.v new file mode 100644 index 000000000..cc658ff4c --- /dev/null +++ b/ivtest/ivltests/pr1758135.v @@ -0,0 +1,19 @@ +// Copyright 2007, Martin Whitaker. +// This code may be freely copied for any purpose. + +module display_index_test(); + +reg [2:0] A[1:4]; + +integer i; + +initial begin + for (i = 1; i <= 4; i = i + 1) begin + A[i] = i; + end + for (i = 1; i <= 4; i = i + 1) begin + $display("%d", A[i]); + end +end + +endmodule diff --git a/ivtest/ivltests/pr1763333.v b/ivtest/ivltests/pr1763333.v new file mode 100644 index 000000000..d124f967f --- /dev/null +++ b/ivtest/ivltests/pr1763333.v @@ -0,0 +1,5 @@ +module test; +wire s1; +not(,s1); +not(s1,); +endmodule diff --git a/ivtest/ivltests/pr1765789.v b/ivtest/ivltests/pr1765789.v new file mode 100644 index 000000000..335e0b46d --- /dev/null +++ b/ivtest/ivltests/pr1765789.v @@ -0,0 +1,22 @@ +// pr1765789 + +module main; + + reg [32:0] addr = {1'b1, 32'h0040_0000 + 32'h8}; + + initial begin + #1 ; + if (addr !== 33'h1_0040_0008) begin + $display("FAILED -- addr = %h", addr); + $finish; + end + + if ($bits({32'h0040_0000 + 32'h8}) !== 32) begin + $display("FAILED -- bits count wrong"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/pr1770199.v b/ivtest/ivltests/pr1770199.v new file mode 100644 index 000000000..3721fdf40 --- /dev/null +++ b/ivtest/ivltests/pr1770199.v @@ -0,0 +1,12 @@ +module top; + wire net; + + assign (pull1, strong0) net = 1'b1; + + initial begin + #1; +// You can get the correct result by uncommenting the following line. +// $display("The value is: %b.", net); + $display("The strength is: %v:", net); + end +endmodule diff --git a/ivtest/ivltests/pr1771903.v b/ivtest/ivltests/pr1771903.v new file mode 100644 index 000000000..8150dd045 --- /dev/null +++ b/ivtest/ivltests/pr1771903.v @@ -0,0 +1,11 @@ +module top; + parameter rval = 1.23456; + real rlv = 1.23456; + + initial begin + $display("Real :%g: has a width of %0d.", rlv, $bits(rlv)); + $display("Parameter real :%g: has a width of %0d.", rval, $bits(rval)); + $display("Real constant :%g: has a width of %0d.", 1.23456, + $bits(1.23456)); + end +endmodule diff --git a/ivtest/ivltests/pr1776485.v b/ivtest/ivltests/pr1776485.v new file mode 100644 index 000000000..16530944f --- /dev/null +++ b/ivtest/ivltests/pr1776485.v @@ -0,0 +1,33 @@ +// pr1776485.v + +module vvp_fun_and; + + wire [7:0] ADC_gain; + reg [7:0] force_low; + wire [7:0] adc_gain_out = ADC_gain & ~force_low; + + UXO source(ADC_gain[5:0]); + + initial begin + force_low = 0; + + #1 $display("ADC_gain = %b, acd_gain_out = %b", ADC_gain, adc_gain_out); + + if (ADC_gain !== 8'bzz_101010) begin + $display("FAILED -- ADC_gain=%b", ADC_gain); + $finish; + end + + if (adc_gain_out !== 8'bxx_101010) begin + $display("FAILED -- adc_gain_out=%b", adc_gain_out); + $finish; + end + + $display("PASSED"); + end + +endmodule + +module UXO(output [5:0] gain); + assign gain = 6'b101010; +endmodule diff --git a/ivtest/ivltests/pr1777103.v b/ivtest/ivltests/pr1777103.v new file mode 100644 index 000000000..66e2c86a3 --- /dev/null +++ b/ivtest/ivltests/pr1777103.v @@ -0,0 +1,26 @@ +module test ( a, b); + +output a; +output reg [31:0] b; + +reg [1:0] c; + +assign a = (b == {16{c}}); + + initial begin + c = 2'b01; + b = 32'h55555555; + #1 if (a !== 1) begin + $display("FAILED -- a=%b, b=%h, c=%b", a, b, c); + $finish; + end + + b = 32'haaaaaaaa; + #1 if (a !== 0) begin + $display("FAILED -- a=%b, b=%h, c=%b", a, b, c); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1780480.v b/ivtest/ivltests/pr1780480.v new file mode 100644 index 000000000..2ae87ab93 --- /dev/null +++ b/ivtest/ivltests/pr1780480.v @@ -0,0 +1,23 @@ +// show bug in icarus verilog +// this shouldn't crash, should it? + +`timescale 1ns/1ns + +module top (); + +reg [1:0] count; + +initial begin + count = 0; + #70 $finish(0); +end + +always + count = #20 count + 1; + +initial + // It seems to be count[0] that does it here, + // If I change it to count then everything works fine. + $monitor("%0t\ta(%b)", $time, count[0]); + +endmodule diff --git a/ivtest/ivltests/pr1784984.v b/ivtest/ivltests/pr1784984.v new file mode 100644 index 000000000..04c8e9ace --- /dev/null +++ b/ivtest/ivltests/pr1784984.v @@ -0,0 +1,39 @@ +// pr1784984 +module signed_test; + + reg [31:0] a; + + initial begin + a = (32'h80000000); + a = a / 2; + $display ("Current Value of a = %h", a); + if (a !== 32'h40000000) begin + $display("FAILED"); + $finish; + end + + a = a * 2; + $display("Current value of a = %h", a); + if (a !== 32'h80000000) begin + $display("FAILED"); + $finish; + end + + a = (32'h80000000)/2; + $display ("Current Value of a = %h", a); + if (a !== 32'h40000000) begin + $display("FAILED"); + $finish; + end + + a = (32'h40000000)*2; + $display ("Current Value of a = %h", a); + if (a !== 32'h80000000) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // signed_test diff --git a/ivtest/ivltests/pr1787394a.v b/ivtest/ivltests/pr1787394a.v new file mode 100644 index 000000000..f263cb357 --- /dev/null +++ b/ivtest/ivltests/pr1787394a.v @@ -0,0 +1,33 @@ +/* + * This should produce x StL x StL + * + * When using both nmos and pmos you get the correct + * result if only one of the control signals is X, but + * when used individually you get StX not StL. This + * appears to be a vec4 vs vec8 problem. R versions + * give similar results. + * + * If both control inputs are X and the input is 0 the + * value is calculated incorrectly. + */ + +module top; + reg nctl, pctl, b; + wire c, d; + initial begin + $display("These should all produce:\nx StL x StL\n-----------"); + $monitor("c=%b(%v), d=%b(%v), b=%b, nctl=%b, pctl=%b", c, c, d, d, b, nctl, pctl); + b = 0; + nctl = 0; + pctl = 1'bx; + #1 nctl = 1'bx; + #1 b = 1; + end + + nmos n1 (c, b, nctl); + pmos p1 (c, b, pctl); + pmos p2 (d, b, pctl); +// bufif1 n1 (c, b, nctl); +// bufif0 p1 (c, b, pctl); +// bufif0 p2 (d, b, pctl); +endmodule diff --git a/ivtest/ivltests/pr1787394b.v b/ivtest/ivltests/pr1787394b.v new file mode 100644 index 000000000..a65865331 --- /dev/null +++ b/ivtest/ivltests/pr1787394b.v @@ -0,0 +1,33 @@ +/* + * This should produce x StL x StL + * + * When using both nmos and pmos you get the correct + * result if only one of the control signals is X, but + * when used individually you get StX not StL. This + * appears to be a vec4 vs vec8 problem. R versions + * give similar results. + * + * If both control inputs are X and the input is 0 the + * value is calculated incorrectly. + */ + +module top; + reg nctl, pctl, b; + wire c, d; + initial begin + $display("These should all produce:\nx StL x StL\n-----------"); + $monitor("c=%b(%v), d=%b(%v), b=%b, nctl=%b, pctl=%b", c, c, d, d, b, nctl, pctl); + b = 0; + nctl = 0; + pctl = 1'bx; + #1 nctl = 1'bx; + #1 b = 1; + end + + //nmos n1 (c, b, nctl); + //pmos p1 (c, b, pctl); + //pmos p2 (d, b, pctl); + bufif1 n1 (c, b, nctl); + bufif0 p1 (c, b, pctl); + bufif0 p2 (d, b, pctl); +endmodule diff --git a/ivtest/ivltests/pr1787423.v b/ivtest/ivltests/pr1787423.v new file mode 100644 index 000000000..87773b23e --- /dev/null +++ b/ivtest/ivltests/pr1787423.v @@ -0,0 +1,17 @@ +module top; + reg in; + wire bf1, bf2, nt1, nt2, pd1, pd2, pu1, pu2; + + initial begin + $monitor(bf1, bf2,, nt1, nt2,, pd1, pd2,, pu1, pu2,, in); + in = 0; + + #1 in = 1; + #1 in = 0; + end + + buf (bf1, bf2, in); + not (nt1, nt2, in); + pulldown (pd1, pd2); + pullup (pu1, pu2); +endmodule diff --git a/ivtest/ivltests/pr1787423b.v b/ivtest/ivltests/pr1787423b.v new file mode 100644 index 000000000..365041686 --- /dev/null +++ b/ivtest/ivltests/pr1787423b.v @@ -0,0 +1,70 @@ +module top; + reg pass = 1'b1; + reg in; + wire bf1, bf2, nt1, nt2, pd1, pd2, pu1, pu2; + + initial begin + // $monitor(bf1, bf2,, nt1, nt2,, pd1, pd2,, pu1, pu2,, in); + if (bf1 !== 1'bx && bf2 !== 1'bx) begin + $display("Buffer failed, expected 2'bxx, got %b%b", bf1, bf2); + pass = 1'b0; + end + if (nt1 !== 1'bx && nt2 !== 1'bx) begin + $display("Inverter (not) failed, expected 2'bxx, got %b%b", nt1, nt2); + pass = 1'b0; + end + if (pd1 !== 1'b0 && pd2 !== 1'b0) begin + $display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2); + pass = 1'b0; + end + if (pu1 !== 1'b1 && pu2 !== 1'b1) begin + $display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2); + pass = 1'b0; + end + + in = 1'b0; + #1; + if (bf1 !== 1'b0 && bf2 !== 1'b0) begin + $display("Buffer failed, expected 2'b00, got %b%b", bf1, bf2); + pass = 1'b0; + end + if (nt1 !== 1'b1 && nt2 !== 1'b1) begin + $display("Inverter (not) failed, expected 2'b11, got %b%b", nt1, nt2); + pass = 1'b0; + end + if (pd1 !== 1'b0 && pd2 !== 1'b0) begin + $display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2); + pass = 1'b0; + end + if (pu1 !== 1'b1 && pu2 !== 1'b1) begin + $display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2); + pass = 1'b0; + end + + in = 1'b1; + #1; + if (bf1 !== 1'b1 && bf2 !== 1'b1) begin + $display("Buffer failed, expected 2'b11, got %b%b", bf1, bf2); + pass = 1'b0; + end + if (nt1 !== 1'b0 && nt2 !== 1'b0) begin + $display("Inverter (not) failed, expected 2'b00, got %b%b", nt1, nt2); + pass = 1'b0; + end + if (pd1 !== 1'b0 && pd2 !== 1'b0) begin + $display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2); + pass = 1'b0; + end + if (pu1 !== 1'b1 && pu2 !== 1'b1) begin + $display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + + buf (bf1, bf2, in); + not (nt1, nt2, in); + pulldown (pd1, pd2); + pullup (pu1, pu2); +endmodule diff --git a/ivtest/ivltests/pr1787423b_std.v b/ivtest/ivltests/pr1787423b_std.v new file mode 100644 index 000000000..a642a1307 --- /dev/null +++ b/ivtest/ivltests/pr1787423b_std.v @@ -0,0 +1,71 @@ +module top; + reg pass = 1'b1; + reg in; + wire bf1, bf2, nt1, nt2, pd1, pd2, pu1, pu2; + + initial begin + // $monitor(bf1, bf2,, nt1, nt2,, pd1, pd2,, pu1, pu2,, in); + #1; + if (bf1 !== 1'bx && bf2 !== 1'bx) begin + $display("Buffer failed, expected 2'bxx, got %b%b", bf1, bf2); + pass = 1'b0; + end + if (nt1 !== 1'bx && nt2 !== 1'bx) begin + $display("Inverter (not) failed, expected 2'bxx, got %b%b", nt1, nt2); + pass = 1'b0; + end + if (pd1 !== 1'b0 && pd2 !== 1'b0) begin + $display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2); + pass = 1'b0; + end + if (pu1 !== 1'b1 && pu2 !== 1'b1) begin + $display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2); + pass = 1'b0; + end + + in = 1'b0; + #1; + if (bf1 !== 1'b0 && bf2 !== 1'b0) begin + $display("Buffer failed, expected 2'b00, got %b%b", bf1, bf2); + pass = 1'b0; + end + if (nt1 !== 1'b1 && nt2 !== 1'b1) begin + $display("Inverter (not) failed, expected 2'b11, got %b%b", nt1, nt2); + pass = 1'b0; + end + if (pd1 !== 1'b0 && pd2 !== 1'b0) begin + $display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2); + pass = 1'b0; + end + if (pu1 !== 1'b1 && pu2 !== 1'b1) begin + $display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2); + pass = 1'b0; + end + + in = 1'b1; + #1; + if (bf1 !== 1'b1 && bf2 !== 1'b1) begin + $display("Buffer failed, expected 2'b11, got %b%b", bf1, bf2); + pass = 1'b0; + end + if (nt1 !== 1'b0 && nt2 !== 1'b0) begin + $display("Inverter (not) failed, expected 2'b00, got %b%b", nt1, nt2); + pass = 1'b0; + end + if (pd1 !== 1'b0 && pd2 !== 1'b0) begin + $display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2); + pass = 1'b0; + end + if (pu1 !== 1'b1 && pu2 !== 1'b1) begin + $display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + + buf (bf1, bf2, in); + not (nt1, nt2, in); + pulldown (pd1, pd2); + pullup (pu1, pu2); +endmodule diff --git a/ivtest/ivltests/pr1787423c.v b/ivtest/ivltests/pr1787423c.v new file mode 100644 index 000000000..f9a38dea2 --- /dev/null +++ b/ivtest/ivltests/pr1787423c.v @@ -0,0 +1,31 @@ +module top; + + wire net1, net2; + reg [1:0] data; + + buf bus_drv[1:0] (net1, net2, data); + + initial begin + data = 0; + #1 $monitor(net1,,net2,,data); + #1 if (net1 !== 1'b0) begin + $display("FAILED"); + $finish; + end + + data = 3; + #1 if (net1 !== 1'b1) begin + $display("FAILED"); + $finish; + end + + data = 1; + #1 if (net1 !== 1'bx) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/pr1792108.v b/ivtest/ivltests/pr1792108.v new file mode 100644 index 000000000..b34ac1563 --- /dev/null +++ b/ivtest/ivltests/pr1792108.v @@ -0,0 +1,31 @@ +`begin_keywords "1364-2005" +module main; + wire y1, y2, y3; + reg a; + + initial begin + $monitor($time , " y1 = %d, y2 = %d, y3 = %d, a = %d", y1, y2, y3, a); + #1 a = 1; + #1 a = 0; + end + + sub s1(y1, y2, y3, a); + +endmodule // main + +module sub(y1, y2, y3, a); + output y1, y2, y3; + input a; + reg y1, y2, y3; + reg int; + + always @(*) begin + y1 <= a; + y2 <= y1; + + int <= a; + y3 <= int; + end + +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr1792152.v b/ivtest/ivltests/pr1792152.v new file mode 100644 index 000000000..d1e866d41 --- /dev/null +++ b/ivtest/ivltests/pr1792152.v @@ -0,0 +1,4 @@ +module top; + parameter value = (1:2:3); + initial $display(value); +endmodule diff --git a/ivtest/ivltests/pr1792734.v b/ivtest/ivltests/pr1792734.v new file mode 100644 index 000000000..180e1f068 --- /dev/null +++ b/ivtest/ivltests/pr1792734.v @@ -0,0 +1,43 @@ +module top; + reg [6:0] dx, dz, dz2; + + initial begin + // Check the unsigned version. + dx = 7'dx; + dz = 7'dz; + dz2 = 7'd?; + $display(" 7'dx: %b", dx, ", 7'dz: %b", dz, ", 7'd?: %b", dz2); + + dx = 'dx; + dz = 'dz; + dz2 = 'd?; + $display(" 'dx: %b", dx, ", 'dz: %b", dz, ", 'd?: %b", dz2); + + dx = 2'dx; + dz = 2'dz; + dz2 = 2'd?; + $display(" 2'dx: %b", dx, ", 2'dz: %b", dz, ", 2'd?: %b", dz2); + + // Check the signed version. + dx = 7'sdx; + dz = 7'sdz; + dz2 = 7'sd?; + $display("7'sdx: %b", dx, ", 7'sdz: %b", dz, ", 7'sd?: %b", dz2); + + dx = 'sdx; + dz = 'sdz; + dz2 = 'sd?; + $display(" 'sdx: %b", dx, ", 'sdz: %b", dz, ", 'sd?: %b", dz2); + + dx = 2'sdx; + dz = 2'sdz; + dz2 = 2'sd?; + $display("2'sdx: %b", dx, ", 2'sdz: %b", dz, ", 2'sd?: %b", dz2); + + // Check the trailing underscore. + dx = 7'dx_; + dz = 7'dz__; + dz2 = 7'd?___; + $display("7'dx_: %b", dx, ", 7'dz_: %b", dz, ", 7'd?_: %b", dz2); + end +endmodule diff --git a/ivtest/ivltests/pr1793157.v b/ivtest/ivltests/pr1793157.v new file mode 100644 index 000000000..368a24cbc --- /dev/null +++ b/ivtest/ivltests/pr1793157.v @@ -0,0 +1,11 @@ +module test; + reg [19:0] x1; + initial + main; + task main; + begin + x1 = 20'habcde; + $display("x1: %h; x2: %h", x1, (x1 - x1 - 1)); + end + endtask +endmodule // test diff --git a/ivtest/ivltests/pr1793749.v b/ivtest/ivltests/pr1793749.v new file mode 100644 index 000000000..2c2d93fd7 --- /dev/null +++ b/ivtest/ivltests/pr1793749.v @@ -0,0 +1,29 @@ +module test; + reg [8:0] t1; + initial + main; + + function integer log2; + input [31:0] arg; + for (log2=0; arg > 0; log2=log2+1) + arg = arg >> 1; + endfunction // log2 + + task main; + integer temp; + begin + t1 = 9'h0a5; + temp = log2($unsigned(t1 - t1 - 1'b1)); + $display("%d", temp); + + temp = log2($signed(t1 - t1 - 1'b1)); + $display("%d", temp); + + temp = log2({t1 - t1 - 1'b1}); + $display("%d", temp); + + temp = $bits(t1 - t1 - 1'b1); + $display("%d", temp); + end + endtask +endmodule diff --git a/ivtest/ivltests/pr1793749b.v b/ivtest/ivltests/pr1793749b.v new file mode 100644 index 000000000..494fa0d0d --- /dev/null +++ b/ivtest/ivltests/pr1793749b.v @@ -0,0 +1,17 @@ +module test; + reg [4:0] i; + reg [7:0] j, k, l; + + initial + main; + task main; + begin + i = 5'h14; + j = $signed(i); // works + k = $signed(5'h14); // doesn't work + l = 5'sh14; // works + + $display("i, j, k, l: '%b', '%b', '%b', '%b'", i, j, k, l); + end + endtask +endmodule diff --git a/ivtest/ivltests/pr1794362.v b/ivtest/ivltests/pr1794362.v new file mode 100644 index 000000000..a0a4a3ca8 --- /dev/null +++ b/ivtest/ivltests/pr1794362.v @@ -0,0 +1,43 @@ +module shift; + reg pass = 1'b1; + integer i; + reg [7:0] foo; + parameter [2:0] + ZERO = 0, + THREE = 3; + + initial begin + foo = 1'b1 << ZERO; + if (foo != 'd1) begin + $display("FAILED shift by ZERO, got %d expected 1", foo); + pass = 1'b0; + end + + foo = 1'b1 << THREE; + if (foo != 'd8) begin + $display("FAILED shift by THREE, got %d expected 8", foo); + pass = 1'b0; + end + + foo = 1'b1 << 3; + if (foo != 'd8) begin + $display("FAILED shift by 3, got %d expected 8", foo); + pass = 1'b0; + end + + foo = 1'b1 << 'd3; + if (foo != 'd8) begin + $display("FAILED shift by 'd3, got %d expected 8", foo); + pass = 1'b0; + end + + i = 'd3; + foo = 1'b1 << i; + if (foo != 'd8) begin + $display("FAILED shift by variable set to 'd3, got %d expected 8", foo); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1795005a.v b/ivtest/ivltests/pr1795005a.v new file mode 100644 index 000000000..7f2f7f1bb --- /dev/null +++ b/ivtest/ivltests/pr1795005a.v @@ -0,0 +1,23 @@ +module test; +reg [63:0] i, j; + +initial +main; +task main; +integer k, l, m, n; +begin +i = 64'hffff_ffff_ffff_ffff; +j = 64'hffff_ffff_ffff_ffff; + +k = $signed(i) < $signed(j); +l = $signed(i) <= $signed(j); +m = $signed(i) > $signed(j); +n = $signed(i) >= $signed(j); + +$display("< : %s", k? "Y":"N"); +$display("<=: %s", l? "Y":"N"); +$display("> : %s", m? "Y":"N"); +$display(">=: %s", n? "Y":"N"); +end +endtask +endmodule diff --git a/ivtest/ivltests/pr1795005b.v b/ivtest/ivltests/pr1795005b.v new file mode 100644 index 000000000..16766011d --- /dev/null +++ b/ivtest/ivltests/pr1795005b.v @@ -0,0 +1,23 @@ +module test; +reg [63:0] i, j; + +initial +main; +task main; +integer k, l, m, n; +begin +i = 64'hffff_ffff_ffff_ffff; +j = 64'hffff_ffff_ffff_fffe; + +k = $signed(i) < $signed(j); +l = $signed(i) <= $signed(j); +m = $signed(i) > $signed(j); +n = $signed(i) >= $signed(j); + +$display("< : %s", k? "Y":"N"); +$display("<=: %s", l? "Y":"N"); +$display("> : %s", m? "Y":"N"); +$display(">=: %s", n? "Y":"N"); +end +endtask +endmodule diff --git a/ivtest/ivltests/pr1799904.v b/ivtest/ivltests/pr1799904.v new file mode 100644 index 000000000..29eaff057 --- /dev/null +++ b/ivtest/ivltests/pr1799904.v @@ -0,0 +1,45 @@ +module test; + + +reg clock; +initial begin +clock = 0; +forever #5 clock = !clock; +end + +wire [0:31] read_data1 [0:7]; +reg [0:31] read_data2 [0:7]; + + +assign read_data1[0] = 0; +assign read_data1[1] = 1; +assign read_data1[2] = 2; +assign read_data1[3] = 3; +assign read_data1[4] = 4; +assign read_data1[5] = 5; +assign read_data1[6] = 6; +assign read_data1[7] = 7; + + +always @(posedge clock) begin: we +reg [3:0] x; +for (x=0; x<8; x=x+1) begin +read_data2[x[2:0]] <= read_data1[x[2:0]]; +end +end + +always @(posedge clock) begin: wg +integer i; +#1 for (i=0; i<8; i=i+1) begin +$write("%x ", read_data2[i]); +end +$display; +end + +initial begin +#20; +$finish(0); +end + + +endmodule // test diff --git a/ivtest/ivltests/pr1804877.v b/ivtest/ivltests/pr1804877.v new file mode 100644 index 000000000..d32bc8812 --- /dev/null +++ b/ivtest/ivltests/pr1804877.v @@ -0,0 +1,11 @@ +module test; + reg [128:1] str [0:0]; + reg [31:0] idx; + + initial begin + str[0] = "test_counter"; + idx = 0; + $write("String is %s\n", str[0]); // This works. + $write("String is %s\n", str[idx]); // This fails. + end +endmodule diff --git a/ivtest/ivltests/pr1805837.v b/ivtest/ivltests/pr1805837.v new file mode 100644 index 000000000..7c2a9edb7 --- /dev/null +++ b/ivtest/ivltests/pr1805837.v @@ -0,0 +1,15 @@ +module test(); + wire [2:0] var1 = 3'bx01; // Incorrect results 101 vs x01. + wire [2:0] var2 = 3'bx10; // Incorrect results 010 vs x10. + wire [2:0] var3 = 3'bx0z; // Incorrect results zzz vs x0z. + wire [2:0] var4 = 3'bx1z; // Incorrect results zzz vs x1z. + wire [2:0] var5 = 3'bxz1; // Incorrect results 1z1 vs xz1. + wire [2:0] var6 = 3'bxz0; // Incorrect results 0z0 vs xz0. + wire [3:0] var7 = 4'bx0z0; // Incorrect results 0000 vs x0z0. + wire [2:0] var8 = 3'bxxx; // This works correctly. + + initial begin + $displayb("Should be:\nx01 x10 x0z x1z xz1 xz0 x0z0 xxx"); + $strobeb (var1,, var2,, var3,, var4,, var5,, var6,, var7,, var8); + end +endmodule diff --git a/ivtest/ivltests/pr1812297.v b/ivtest/ivltests/pr1812297.v new file mode 100644 index 000000000..9610c1046 --- /dev/null +++ b/ivtest/ivltests/pr1812297.v @@ -0,0 +1,25 @@ +module ttop; + reg tpass = 0, fpass = 0; + task ttop; + #1 tpass = 1; + endtask + initial begin + ttop; + #2; + case ({tpass, fpass}) + 2'b00: $display("FAILED - both task and function test"); + 2'b01: $display("FAILED - task test"); + 2'b10: $display("FAILED - function test"); + 2'b11: $display("PASSED"); + endcase + end +endmodule + +module ftop; + function ftop; + input a; + ftop = ~a; + endfunction + + initial if (ftop(0)) #1 ttop.fpass = 1; +endmodule diff --git a/ivtest/ivltests/pr1819452.txt b/ivtest/ivltests/pr1819452.txt new file mode 100644 index 000000000..9a23d972d --- /dev/null +++ b/ivtest/ivltests/pr1819452.txt @@ -0,0 +1,11 @@ +in_0 +in_1 +in_2 +in_3 +in_4 +in_5 +in_6 +in_7 +in_8 +in_9 +in_10 diff --git a/ivtest/ivltests/pr1819452.v b/ivtest/ivltests/pr1819452.v new file mode 100644 index 000000000..6c1cf336e --- /dev/null +++ b/ivtest/ivltests/pr1819452.v @@ -0,0 +1,45 @@ +module top; + reg [8*80-1:0] str; + integer fd, pos, result; + + initial begin + fd = $fopen("ivltests/pr1819452.txt","rb"); + result = $fgets(str, fd); + while (!$feof(fd)) begin + pos = $ftell(fd); + $display("Found: %5s currently at byte %0d", str[8*10-1:8], pos); + result = $fgets(str, fd); + end + + result = $rewind(fd); + result = $fgets(str, fd); + pos = $ftell(fd); + $display("Found: %5s currently at byte %0d", str[8*10-1:8], pos); + + result = $fseek(fd, 0, 0); + result = $fgets(str, fd); + pos = $ftell(fd); + $display("Found: %5s currently at byte %0d", str[8*10-1:8], pos); + + result = $fseek(fd, -3, 2); + result = $fgets(str, fd); + pos = $ftell(fd); + $display("Found: %5s currently at byte %0d", str[8*10-1:8], pos); + + result = $fseek(fd, -6, 1); + result = $fgets(str, fd); + pos = $ftell(fd); + $display("Found: %5s currently at byte %0d", str[8*10-1:8], pos); + + result = $fseek(32'hffffffff, 0, 0); + $display("Check fseek EOF = %0d", result); + + result = $ftell(32'hffffffff); + $display("Check ftell EOF = %0d", result); + + result = $rewind(32'hffffffff); + $display("Check rewind EOF = %0d", result); + + $fclose(fd); + end +endmodule diff --git a/ivtest/ivltests/pr1820472.v b/ivtest/ivltests/pr1820472.v new file mode 100644 index 000000000..e270ea852 --- /dev/null +++ b/ivtest/ivltests/pr1820472.v @@ -0,0 +1,31 @@ +module test; +// parameter j=0; + + reg [5:0] j; + reg [5:0] in [7:0]; + wire [5:0] out [7:0]; + + assign out[0][1:0] = 2'b10; + assign out[0][3:2] = 2'b01; + assign out[1] = in[j]; // This uses the current j! + assign out[2] = in[2]; + assign out[3] = in[3]; + + initial begin + j = 1; + in[j] = 2'b10; + in[2][3:2] = 2'b01; + in[j+2][3:2] = 2'b10; + + #1; + $display("out[0]: %b", out[0]); + $display("out[1]: %b", out[1]); + $display("out[2]: %b", out[2]); + $display("out[3]: %b", out[3]); + for (j=0; j<4; j=j+1) begin + #0; // wait for change to propagate + $display("out[1]-%0d: %b", j, out[1]); + end + end + +endmodule diff --git a/ivtest/ivltests/pr1822658.v b/ivtest/ivltests/pr1822658.v new file mode 100644 index 000000000..7f6a0c14a --- /dev/null +++ b/ivtest/ivltests/pr1822658.v @@ -0,0 +1,8 @@ +`define _variable 1 + +module top; + initial begin + if (`_variable == 1) $display("PASSED"); + else $display("Fail"); + end +endmodule diff --git a/ivtest/ivltests/pr1823732.v b/ivtest/ivltests/pr1823732.v new file mode 100644 index 000000000..ecce08ebc --- /dev/null +++ b/ivtest/ivltests/pr1823732.v @@ -0,0 +1,19 @@ +// +// The output from the display should be: +// i is '1'; j is '111'; k is '0' +// +module test; + reg one = 1; + reg i, k, kr; + reg [2:0] j, jr; + initial + begin + i = ($signed(3'b111) === 3'b111); + j = $signed(3'b110) >>> 1; + jr = $signed(3'b110) >>> one; + k = (($signed(3'b110) >>> 1) === 3'b111); + kr = (($signed(3'b110) >>> one) === 3'b111); + $display("i is '%b'; j is '%b'; k is '%b'", i, j, k); + $display("runtime ; j is '%b'; k is '%b'", jr, kr); + end +endmodule diff --git a/ivtest/ivltests/pr1828642.v b/ivtest/ivltests/pr1828642.v new file mode 100644 index 000000000..89f97d1fe --- /dev/null +++ b/ivtest/ivltests/pr1828642.v @@ -0,0 +1,30 @@ +// Copyright 2007, Martin Whitaker. +// This code may be freely copied for any purpose. +module generate_memory(); + +generate + genvar b; + + for (b = 0; b < 4; b = b + 1) begin: Byte + reg [7:0] Data[0:3]; + end +endgenerate + +integer i; + +initial begin + for (i = 0; i < 4; i = i + 1) begin + Byte[0].Data[i] = i*16 + 1; + Byte[1].Data[i] = i*16 + 2; + Byte[2].Data[i] = i*16 + 3; + Byte[3].Data[i] = i*16 + 4; + end + for (i = 0; i < 4; i = i + 1) begin + $display("%h", Byte[0].Data[i]); + $display("%h", Byte[1].Data[i]); + $display("%h", Byte[2].Data[i]); + $display("%h", Byte[3].Data[i]); + end +end + +endmodule diff --git a/ivtest/ivltests/pr183.v b/ivtest/ivltests/pr183.v new file mode 100644 index 000000000..2113afc70 --- /dev/null +++ b/ivtest/ivltests/pr183.v @@ -0,0 +1,16 @@ +// Sample Code +module main( stb, a ); + + input stb; + output [1:0] a; + wire [1:0] b; + + buf (a[0], b[0]); + buf (a[1], b[1]); + + specify + (posedge stb => (a[0]:1'bx)) = 1.0; + (posedge stb => (a[1]:1'bx)) = 1.0; + endspecify + +endmodule // main diff --git a/ivtest/ivltests/pr1830834.v b/ivtest/ivltests/pr1830834.v new file mode 100644 index 000000000..12eb60bab --- /dev/null +++ b/ivtest/ivltests/pr1830834.v @@ -0,0 +1,26 @@ +// Here are two examples of $strobe failing. It appears that thread data +// is being cleaned up too soon for the $strobe to access it. +module test; + reg[4:0] j; + reg [5:0] in [1:0]; + wire [5:0] out; + + assign out = in[j]; // This uses the current j. + + initial begin + in[1] = 6'b110001; + + j = 1; + #1; // Need some delay for the calculations to run. + $display("out: %b, in[%0d] %b:", out, j, in[j]); + $display("out[3:0]: %b, in[%0d] %b:", out[j*1-1 +: 4], j, in[j]); + + // in[j] is what is failing. + $strobe("out: %b, in[%0d] %b:", out, j, in[j]); + + // out[j... is what is failing. + $strobe("out[3:0]: %b, in[%0d] %b:", out[j*1-1 +: 4], j, in[j]); +// #1; // Adding this will work around the bug. + end + +endmodule diff --git a/ivtest/ivltests/pr1831724.v b/ivtest/ivltests/pr1831724.v new file mode 100644 index 000000000..a0f1a00f0 --- /dev/null +++ b/ivtest/ivltests/pr1831724.v @@ -0,0 +1,11 @@ +// pr1831724 + +module test; + reg [15:0] tmp1, tmp2; + initial + begin + tmp1 = 9'bxxx000000; + tmp2 = {9'bxxx000000}; + $display("tmp1: '%b'; tmp2: '%b'", tmp1, tmp2); + end +endmodule diff --git a/ivtest/ivltests/pr1832097a.v b/ivtest/ivltests/pr1832097a.v new file mode 100644 index 000000000..ad0510d7f --- /dev/null +++ b/ivtest/ivltests/pr1832097a.v @@ -0,0 +1,40 @@ +module test; + reg fail = 0; + reg [3:0] in = 4'b0; + wire [3:0] bus = in; + + initial begin + #1; // Need some delay for the calculations to run. + if (bus !== 4'b0) begin + $display("FAILED: initial value, got %b, expected 0000.", bus); + fail = 1; + end + + #1 force bus[0] = 1'b1; + #1 in[0] = 1'bz; + if (bus !== 4'b0001) begin + $display("FAILED: force of bus[0], got %b, expected 0001.", bus); + fail = 1; + end + + #1 force bus[3:2] = 2'b11; + if (bus !== 4'b1101) begin + $display("FAILED: force of bus[3:2], got %b, expected 1101.", bus); + fail = 1; + end + + #1 release bus[0]; + if (bus !== 4'b110z) begin + $display("FAILED: release of bus[0], got %b, expected 110z.", bus); + fail = 1; + end + + #1 release bus[3:2]; + if (bus !== 4'b000z) begin + $display("FAILED: release of bus[3:2], got %b, expected 000z.", bus); + fail = 1; + end + + if (!fail) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1832097b.v b/ivtest/ivltests/pr1832097b.v new file mode 100644 index 000000000..57529e21e --- /dev/null +++ b/ivtest/ivltests/pr1832097b.v @@ -0,0 +1,41 @@ +module test; + reg fail = 0; + reg [3:0] bus = 4'b0; + + initial begin + if (bus !== 4'b0) begin + $display("FAILED: initial value, got %b, expected 0000.", bus); + fail = 1; + end + + #1 force bus[0] = 1; + bus[0] = 1'bz; + if (bus !== 4'b0001) begin + $display("FAILED: force of bus[0], got %b, expected 0001.", bus); + fail = 1; + end + + #1 force bus[3:2] = 2'b11; + if (bus !== 4'b1101) begin + $display("FAILED: force of bus[3:2], got %b, expected 1101.", bus); + fail = 1; + end + + #1 release bus[0]; + bus = 4'b000z; + #0; + if (bus !== 4'b110z) begin + $display("FAILED: release of bus[0], got %b, expected 110z.", bus); + fail = 1; + end + + #1 release bus[3:2]; + bus[3] = 1'b0; + if (bus !== 4'b010z) begin + $display("FAILED: release of bus[3:2], got %b, expected 010z.", bus); + fail = 1; + end + + if (!fail) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1833024.v b/ivtest/ivltests/pr1833024.v new file mode 100644 index 000000000..36c300db5 --- /dev/null +++ b/ivtest/ivltests/pr1833024.v @@ -0,0 +1,93 @@ +`begin_keywords "1364-2005" +module top; + reg svar; + reg sarr [1:0]; + reg sout, stmp; + wire wsarr [1:0]; + wire wsbslv, wspslv, wsuplv, wsdolv; + wire wsbstr, wspstr, wsuptr, wsdotr; + + wire wsbs = svar[0]; + wire wsps = svar[0:0]; + wire wsup = svar[0+:1]; + wire wsdo = svar[0-:1]; + + wire wsabs = sarr[0][0]; + wire wsaps = sarr[0][0:0]; + wire wsaup = sarr[0][0+:1]; + wire wsado = sarr[0][0-:1]; + + assign wsbslv[0] = svar; + assign wspslv[0:0] = svar; + assign wsuplv[0+:1] = svar; + assign wsdolv[0-:1] = svar; + + assign wsarr[0][0] = svar; + assign wsarr[0][0:0] = svar; + assign wsarr[0][0+:1] = svar; + assign wsarr[0][0-:1] = svar; + + tran(wsbstr[0], wsarr[1]); + tran(wspstr[0:0], wsarr[1]); + tran(wsuptr[0+:1], wsarr[1]); + tran(wsdotr[0-:1], wsarr[1]); + + submod1 s1 (wsbstr[0], wspstr[0:0], wsuptr[0+:1], wsdotr[0-:1]); + submod2 s2 (wsbstr[0], wspstr[0:0], wsuptr[0+:1], wsdotr[0-:1]); + submod3 s3 (wsbstr[0], wspstr[0:0], wsuptr[0+:1], wsdotr[0-:1]); + + task stask; + input a; + reg local; + begin + local = a[0]; + local = a[0:0]; + local = a[0+:1]; + local = a[0-:1]; + end + endtask + + initial begin + stmp = svar[0]; + stmp = svar[0:0]; + stmp = svar[0+:1]; + stmp = svar[0-:1]; + + stmp = sarr[0][0]; + stmp = sarr[0][0:0]; + stmp = sarr[0][0+:1]; + stmp = sarr[0][0-:1]; + + sout[0] = 1'b0; + sout[0:0] = 1'b0; + sout[0+:1] = 1'b0; + sout[0-:1] = 1'b0; + + sarr[0][0] = 1'b0; + sarr[0][0:0] = 1'b0; + sarr[0][0+:1] = 1'b0; + sarr[0][0-:1] = 1'b0; + end +endmodule + +module submod1(arg1, arg2, arg3, arg4); + input arg1, arg2, arg3, arg4; + wire arg1, arg2, arg3, arg4; + + initial $display("In submod1 with %b, %b, %b, %b", arg1, arg2, arg3, arg4); +endmodule + +module submod2(arg1, arg2, arg3, arg4); + output arg1, arg2, arg3, arg4; + wire arg1, arg2, arg3, arg4; + + initial $display("In submod2 with %b, %b, %b, %b", arg1, arg2, arg3, arg4); +endmodule + +module submod3(arg1, arg2, arg3, arg4); + inout arg1, arg2, arg3, arg4; + wire arg1, arg2, arg3, arg4; + + initial $display("In submod3 with %b, %b, %b, %b", arg1, arg2, arg3, arg4); +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr1833754.v b/ivtest/ivltests/pr1833754.v new file mode 100644 index 000000000..18a2fefb8 --- /dev/null +++ b/ivtest/ivltests/pr1833754.v @@ -0,0 +1,36 @@ +// Copyright 2007, Martin Whitaker. +// This code may be freely copied for any purpose. + +module duplicate_names(); + +localparam up = 1; + +generate + if (up) + begin:block1 + wire [2:0] count1; + count_up counter(count1); + end +endgenerate + +initial begin:block1 + reg [2:0] count2; + + #1 count2 = 4; + #1 count2 = 5; + #1 count2 = 6; + #1 count2 = 7; +end + +endmodule + +module count_up(output reg [2:0] count); + +initial begin + #1 count = 0; + #1 count = 1; + #1 count = 2; + #1 count = 3; +end + +endmodule diff --git a/ivtest/ivltests/pr1841300.v b/ivtest/ivltests/pr1841300.v new file mode 100644 index 000000000..1a7ad650c --- /dev/null +++ b/ivtest/ivltests/pr1841300.v @@ -0,0 +1,18 @@ +// PR1841300 +// The output should be: +// a is '14'; b is 'fffffff4'; c is 'fffffff4' +module test; + reg[4:0] a; + reg [31:0] b, c; + initial begin + a = 5'b10100; + b = $signed(a); + c = $signed(_$Finv5(32'hab)); + $display("a is '%h'; b is '%h'; c is '%h'", a, b, c); + end + function [4:0] _$Finv5; + input l; + reg [4:0] l; + _$Finv5 = ~l; + endfunction +endmodule diff --git a/ivtest/ivltests/pr1845683.v b/ivtest/ivltests/pr1845683.v new file mode 100644 index 000000000..00fb7bbaa --- /dev/null +++ b/ivtest/ivltests/pr1845683.v @@ -0,0 +1,27 @@ +// PR1845683 +/** +* Author: Evan Lavelle +* Company: Riverside Machines Ltd. +* Date: 06/12/2007 +* +* Cver feature #1; signed arithmetic +* +* The correct output should be: +* +* res1: '00101010'; res2: '00101010'; res3: '00101010' +* +* Cver reports: +* +* res1: '10101010'; res2: '10101010'; res3: '10101010' +*/ +module test; +reg [7:0] res1, res2; +reg signed [7:0] res3; +initial +begin +res1 = 8'sb11001100 ^ 7'sb1100110; +res2 = $signed(8'b11001100) ^ $signed(7'b1100110); +res3 = $signed(8'b11001100) ^ $signed(7'b1100110); +$display("res1: '%b'; res2: '%b'; res3: '%b'", res1, res2, res3); +end +endmodule diff --git a/ivtest/ivltests/pr1851310.v b/ivtest/ivltests/pr1851310.v new file mode 100644 index 000000000..9c083f737 --- /dev/null +++ b/ivtest/ivltests/pr1851310.v @@ -0,0 +1,24 @@ +// Copyright 2007, Martin Whitaker. +// This file may be freely copied for any purpose. +module memory_monitor(); + +reg [7:0] Memory[0:15]; + +reg [3:0] Index; + +wire Flag1; +wire FlagI; + +assign Flag1 = (Memory[1] == 0); + +assign FlagI = (Memory[Index] == 0); + +initial begin + Index = 1; + Memory[Index] = 0; + #1 $display("Flag1 = %b, FlagI = %b", Flag1, FlagI); + Memory[Index] = 1; + #1 $display("Flag1 = %b, FlagI = %b", Flag1, FlagI); +end + +endmodule diff --git a/ivtest/ivltests/pr1855504.v b/ivtest/ivltests/pr1855504.v new file mode 100644 index 000000000..c2eb47a39 --- /dev/null +++ b/ivtest/ivltests/pr1855504.v @@ -0,0 +1,22 @@ +// pr1855504 + +module mul_test(); + + reg [15:0] prod; + reg [7:0] op2; + reg [15:0] op1; + + + initial begin + op1 = 16'h0DA0; + op2 = 8'h0A; + prod = 16'h0000; + end + + always begin + prod <= op1[7:0] * op2; + #5 $display("op1 = %h, op2 = %h, prod = %h", op1, op2, prod); + #5 $finish(0); + end + +endmodule // mul_test diff --git a/ivtest/ivltests/pr1861212a.v b/ivtest/ivltests/pr1861212a.v new file mode 100644 index 000000000..be25b6ab1 --- /dev/null +++ b/ivtest/ivltests/pr1861212a.v @@ -0,0 +1,12 @@ +module top2; + real vo; + + initial begin + vo = 3.3; + #1000 vo = 4.5776; + #1000 vo = -4; + end + + always @(vo) + $display("Real value is %f at %g", vo, $time); +endmodule diff --git a/ivtest/ivltests/pr1861212b.v b/ivtest/ivltests/pr1861212b.v new file mode 100644 index 000000000..52c42aaa8 --- /dev/null +++ b/ivtest/ivltests/pr1861212b.v @@ -0,0 +1,24 @@ +module top; + wire [63:0] vo; + + rcvr U1(vo); + drvr U2(vo); +endmodule + +module rcvr(input wire [63:0] vo); + + always @(vo) + $display("Real value is %f at %g", $bitstoreal(vo), $time); +endmodule + +module drvr(output wire [63:0] vo); + real vint; + + assign vo = $realtobits(vint); + + initial begin + vint = 3.3; + #1000 vint = 4.5776; + #1000 vint = -4; + end +endmodule diff --git a/ivtest/ivltests/pr1861212c.v b/ivtest/ivltests/pr1861212c.v new file mode 100644 index 000000000..8e644f9d3 --- /dev/null +++ b/ivtest/ivltests/pr1861212c.v @@ -0,0 +1,25 @@ +module top; + wire real vo; + + rcvr U1(vo); + drvr U2(vo); +endmodule + +module rcvr(vo); + input vo; + wire real vo; + + always @(vo) + $display("Real value is %f at %g", vo, $time); +endmodule + +module drvr(vo); + output vo; + reg real vo; + + initial begin + vo = 3.3; + #1000 vo = 4.5776; + #1000 vo = -4; + end +endmodule diff --git a/ivtest/ivltests/pr1861212d.v b/ivtest/ivltests/pr1861212d.v new file mode 100644 index 000000000..54f16549e --- /dev/null +++ b/ivtest/ivltests/pr1861212d.v @@ -0,0 +1,19 @@ +module top; + reg real vo; + + initial begin + vo = 3.3; + #1000 vo = 4.5776; + #1000 vo = -4; + end + + rcvr U1(vo); +endmodule + +module rcvr(vo); + input vo; + wire real vo; + + always @(vo) + $display("Real value is %f at %g", vo, $time); +endmodule diff --git a/ivtest/ivltests/pr1862744a.v b/ivtest/ivltests/pr1862744a.v new file mode 100644 index 000000000..8062db324 --- /dev/null +++ b/ivtest/ivltests/pr1862744a.v @@ -0,0 +1,117 @@ +module main; + reg pass = 1'b1; + + reg v1 = 1'b0; + reg v2 = 1'b0; + reg v3 = 1'b0; + reg v4 = 1'b0; + reg v5 = 1'b0; + reg v6 = 1'b0; + reg v7 = 1'b0; + reg v8 = 1'b0; + reg v9 = 1'b0; + reg v10 = 1'b0; + reg v11 = 1'b0; + reg v12 = 1'b0; + reg cond = 1'b1; + reg [1:0] cval = 2'b00; + + always #1 v1 = 1'b1; + + always v2 = #1 1'b1; + + always if (1'b1) #1 v3 = 1'b1; + + // This will pass since the else is optimized away! + always if (1'b1) #1 v4 = 1'b1; else v4 = 1'b0; + + always if (cond) #1 v5 = 1'b1; else #1 v5 = 1'b0; + + always begin #1 v6 = 1'b1; end // 1 + + always begin #1; v7 = 1'b1; end // 2 + + always begin #0; #1 v8 = 1'b1; end // 3 + + always begin if (cond) #1 v9 = 1'b0; else v9 = 1'b0; #1 v9 = 1'b1; end // 4 + + always repeat(1) #1 v10 = 1'b1; + + always case(cval) + 2'b00: #1 v11 = 1'b1; + 2'b01: #1 v11 = 1'bx; + default: #1 v11 = 1'bz; + endcase + + always definite_delay; + + task definite_delay; + #1 v12 = 1'b1; + endtask + + initial begin + #3; + if (v1 != 1'b1) begin + $display("Failed delayed assignment."); + pass = 1'b0; + end + + if (v2 != 1'b1) begin + $display("Failed intra-assignment delay."); + pass = 1'b0; + end + + if (v3 != 1'b1) begin + $display("Failed simple if statement."); + pass = 1'b0; + end + + if (v4 != 1'b1) begin + $display("Failed constant if/else statement."); + pass = 1'b0; + end + + if (v5 != 1'b1) begin + $display("Failed if/else statement."); + pass = 1'b0; + end + + if (v6 != 1'b1) begin + $display("Failed block (1)."); + pass = 1'b0; + end + + if (v7 != 1'b1) begin + $display("Failed block (2)."); + pass = 1'b0; + end + + if (v8 != 1'b1) begin + $display("Failed block (3)."); + pass = 1'b0; + end + + if (v9 != 1'b1) begin + $display("Failed block (4)."); + pass = 1'b0; + end + + if (v10 != 1'b1) begin + $display("Failed repeat."); + pass = 1'b0; + end + + if (v11 != 1'b1) begin + $display("Failed case."); + pass = 1'b0; + end + + if (v12 != 1'b1) begin + $display("Failed task."); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/pr1862744b.v b/ivtest/ivltests/pr1862744b.v new file mode 100644 index 000000000..c6d057ad1 --- /dev/null +++ b/ivtest/ivltests/pr1862744b.v @@ -0,0 +1,126 @@ +// Note: The for is translated to a begin/while is it tests the while. + +module main; + reg val = 1'b0; + reg cond = 1'b1; + reg [1:0] cval; + integer idx; + integer dly = 1; + + // Simple assign (error). + always val = 1'b1; + + // A zero delay assign (error). + always #0 val = 1'b1; + + // A variable delay assign (warning). + always #dly val = 1'b1; + + // Non-blocking assign (error). + always val <= #1 1'b1; + + // No delay if (error). + always if (cond) val = 1'b1; + + // No delay if/else (error). + always if (cond) val = 1'b1; else val = 1'b0; + + // Delay if/no delay else (warning). + always if (cond) #1 val = 1'b1; else val = 1'b0; + + // Delay if/no delay else (warning). + always #0 if (cond) #1 val = 1'b1; else val = 1'b0; + + // No delay if/delay else (warning). + always if (cond) val = 1'b1; else #1 val = 1'b0; + + // No delay forever (error). + always forever val = 1'b1; + + // Zero delay forever (error). + always forever #0 val = 1'b1; + + // Possible delay forever (warning). + always forever if (cond) #1 val = 1'b1; else val = 1'b0; + + // No delay for (error). + always for(idx=0; idx<1; idx=idx+1) val = 1'b1; + + // Zero delay for (error). + always for(idx=0; idx<1; idx=idx+1) #0 val = 1'b1; + + // Possible delay for (warning). + always for(idx=0; idx<1; idx=idx+1) if (cond) #1 val = 1'b1; else val = 1'b0; + + // Never run for (error). + always for(idx=0; 0; idx=idx+1) #1 val = 1'b1; + + // Always run for (error). + always for(idx=0; 1; idx=idx+1) #0 val = 1'b1; + + // An empty bock (error). + always begin end + + // Block with no delay (error). + always begin val = 1'b1; end + + // Block with zero delay (error). + always begin #0 val = 1'b1; end + + // Block with zero delay (warning). + always begin #0; if (cond) #1 val = 1'b1; else val = 1'b0; end + + // Never run repeat (error). + always repeat(0) #1 val = 1'b1; + + // Always run repeat (error). + always repeat(1) #0 val = 1'b1; + + // Possibly run repeat (warning). + always repeat(cond) #1 val = 1'b1; + + // No wait (error). + always wait(1) val = 1'b1; + + // May wait (warning). + always wait(cond) val = 1'b1; + + // Not all paths covered (warning). + always case(cval) + 2'b00: #1 val = 1'b1; + 2'b10: #1 val = 1'b1; + endcase + + // Not all paths have delay (warning). + always case(cval) + 2'b00: #1 val = 1'b1; + 2'b10: #1 val = 1'b1; + default: #0 val = 1'b1; + endcase + + // Check task calls (error, error, warning). + always no_delay; + always zero_delay; + always possible_delay; + + task no_delay; + val = 1'b1; + endtask + + task zero_delay; + #0 val = 1'b1; + endtask + + task possible_delay; + #dly val = 1'b1; + endtask + + // Check a function call (error). + always val = func(1'b1); + + function func; + input in; + func = in; + endfunction + +endmodule diff --git a/ivtest/ivltests/pr1864110a.v b/ivtest/ivltests/pr1864110a.v new file mode 100644 index 000000000..d1092d62d --- /dev/null +++ b/ivtest/ivltests/pr1864110a.v @@ -0,0 +1,10 @@ +module top; + wire real plus, minus; + + assign plus = 3.0; + assign minus = -3.0; // This does not generate a Cr<>, so it core dumps. + + initial begin + #1 $display(plus,, minus); + end +endmodule diff --git a/ivtest/ivltests/pr1864110b.v b/ivtest/ivltests/pr1864110b.v new file mode 100644 index 000000000..aff9e5bbe --- /dev/null +++ b/ivtest/ivltests/pr1864110b.v @@ -0,0 +1,14 @@ +module top; + wire real minus; + real in; + + assign minus = -in; // Should be arith/sub.r Cr<0>, + + initial begin + $monitor(minus,, in); + + in = 3.0; + #1 in = 4.0; + #1 in = 6.0; + end +endmodule diff --git a/ivtest/ivltests/pr1864110c.v b/ivtest/ivltests/pr1864110c.v new file mode 100644 index 000000000..6e8cc2b2f --- /dev/null +++ b/ivtest/ivltests/pr1864110c.v @@ -0,0 +1,18 @@ +module top; + wire real result; + reg [63:0] bits; + + // This generates incorrect code: + // The .net/real temporary is not needed. + // The .alias/real temporary is not needed. + // The .sfunc should connect directly to the "results" net. + // The .part is not needed and is causing a core dump. + assign result = $bitstoreal(bits); + + initial begin + $monitor("%g %h", result, bits); + + bits = 64'b0; + #1 bits = {1'b0,{62{1'b1}}}; + end +endmodule diff --git a/ivtest/ivltests/pr1864115.v b/ivtest/ivltests/pr1864115.v new file mode 100644 index 000000000..12f734602 --- /dev/null +++ b/ivtest/ivltests/pr1864115.v @@ -0,0 +1,23 @@ +module top; + wire real result; + wire [63:0] bits; + real in; + + assign bits = $realtobits(in); + + // This generates incorrect code: + // The .net/real temporary is not needed. + // The .alias/real temporary is not needed. + // The .sfunc should connect directly to the "results" net. + // The .part is not needed and is causing a core dump. + // + // Once these are fixed it appears there is a concurrency issues + assign result = $bitstoreal(bits); + + initial begin + $monitor(result,, bits,, in); + + in = 0.0; + #1 in = 2.0; + end +endmodule diff --git a/ivtest/ivltests/pr1866215.v b/ivtest/ivltests/pr1866215.v new file mode 100644 index 000000000..7b7a23616 --- /dev/null +++ b/ivtest/ivltests/pr1866215.v @@ -0,0 +1,46 @@ +// pr1866215 + +module A (CH, CL, SH, SL); + +wire [31:6] S1L; +wire [39:32] S1H; +wire [31:6] C1L; +wire [38:32] C1H; + +output [31:0] SL; +output [31:0] CL; +output [47:32] SH; +output [47:32] CH; + +B B0 (C1H[38:32], {C1L[31:6], CL[5:0]}, S1H[39:32], {S1L[31:6], SL[5:0]}); + +initial begin + #1 $display("C1H=%h, {C1L, CL}={%h, %h}, S1H=%h, {S1L, SL}={%h, %h}", + C1H, C1L, CL, S1H, S1L, SL); +end + +endmodule + +module B (CH, CL, SH, SL); + +output [37:32] CH; +output [31:0] CL; +output [38:32] SH; +output [31:0] SL; + +C C0 (CH, CL, SH, SL); + +endmodule + +module C (CH, CL, SH, SL); + +output [38:32] CH; +output [31:0] CL; +output [39:32] SH; +output [31:0] SL; + + assign CH = 6'h33; + assign CL = 32'h55555555; + assign SH = 7'h66; + assign SL = 32'haaaaaaaa; +endmodule diff --git a/ivtest/ivltests/pr1866215b.v b/ivtest/ivltests/pr1866215b.v new file mode 100644 index 000000000..fd0069a69 --- /dev/null +++ b/ivtest/ivltests/pr1866215b.v @@ -0,0 +1,39 @@ +// pr1866215 + +module A (CH, CL, SH, SL); + +output [31:0] SL; +output [31:0] CL; +output [47:32] SH; +output [47:32] CH; + +B B0 (CH, CL, SH, SL); + + assign SH = 'hff; + assign SL = 32'haaaaaaaa; + assign CH = 'hff; + assign CL = 32'h55555555; + +endmodule + +module B (CH, CL, SH, SL); + +input [37:32] CH; +input [31:0] CL; +input [38:32] SH; +input [31:0] SL; + +C C0 (CH, CL, SH, SL); + +endmodule + +module C (CH, CL, SH, SL); + +input [38:32] CH; +input [31:0] CL; +input [39:32] SH; +input [31:0] SL; + + initial #1 $display("CH=%h, CL=%h, SH=%h, SL=%h", CH, CL, SH, SL); + +endmodule diff --git a/ivtest/ivltests/pr1867161a.v b/ivtest/ivltests/pr1867161a.v new file mode 100644 index 000000000..3cafb1465 --- /dev/null +++ b/ivtest/ivltests/pr1867161a.v @@ -0,0 +1,20 @@ +module test; + /* The base+b calculation uses %load/vp0 and this will cause invalid + * results when the sum of base+b is larger than what will fit + * in b. The addition is done at b's width. It appears that + * %load/vp0 needs to be enhanced, or something else needs to + * be used. + * + * The workaround is to make b large enough to access + * the largest a index not a's range. */ + parameter base = 8; + reg [31:0] a[15:base]; + reg [2:0] b; + + initial begin + for (b=0; b<7; b=b+1) begin + a[base+b] = 32'd2+b; + $display("Value[%0d]: %1d", b, a[base+b]); + end + end +endmodule diff --git a/ivtest/ivltests/pr1867161b.v b/ivtest/ivltests/pr1867161b.v new file mode 100644 index 000000000..645bdc44f --- /dev/null +++ b/ivtest/ivltests/pr1867161b.v @@ -0,0 +1,22 @@ +module test ( + input rst +); + + reg [31:0] a[99-1:35]; + reg [5:0] b; + + always @(b) begin + a[35 + (b<<3)] <= #1 a[35 + (b<<3)] + 32'd1; + end + + initial begin + $monitor(a[35],, a[43]); + a[35] = 32'd0; + a[43] = 32'd8; + b = 0; + #2 b = 1; + #2 b = 0; + #2 b = 1; + #2 b = 0; + end +endmodule diff --git a/ivtest/ivltests/pr1867332.v b/ivtest/ivltests/pr1867332.v new file mode 100644 index 000000000..9dd09d7de --- /dev/null +++ b/ivtest/ivltests/pr1867332.v @@ -0,0 +1,13 @@ +module test ( + input CL, + input CSB +); + + reg a; + + specify specparam + tps = 0.0; + $setup(posedge CSB, edge[01,0x,x1,1x] CL, tps, a); + endspecify + +endmodule diff --git a/ivtest/ivltests/pr1868792.v b/ivtest/ivltests/pr1868792.v new file mode 100644 index 000000000..48409bee1 --- /dev/null +++ b/ivtest/ivltests/pr1868792.v @@ -0,0 +1,28 @@ +module top; + parameter amax = 9; + reg [31:0] mem [amax:0]; + integer i, tmp; + integer fail [amax:0]; + integer pass; + + initial begin + pass = 1; + for (i=0; i rl1; + assign ge = rl2 >= rl1; + assign lt = rl2 < rl1; + assign le = rl2 <= rl1; + + initial begin + rl1 = 0.0; + rl2 = 0.0; + #1 if ({eq,ne,gt,ge,lt,le} != 6'b100101) begin + $display("Failed: expected %b, received %b", 6'b100101, + {eq,ne,gt,ge,lt,le}); + passed = 1'b0; + end + #1 rl2 = -1.0; + #1 if ({eq,ne,gt,ge,lt,le} != 6'b010011) begin + $display("Failed: expected %b, received %b", 6'b010011, + {eq,ne,gt,ge,lt,le}); + passed = 1'b0; + end + #1 rl2 = 1.0; + #1 if ({eq,ne,gt,ge,lt,le} != 6'b011100) begin + $display("Failed: expected %b, received %b", 6'b001100, + {eq,ne,gt,ge,lt,le}); + passed = 1'b0; + end + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1869772.v b/ivtest/ivltests/pr1869772.v new file mode 100644 index 000000000..3199744a1 --- /dev/null +++ b/ivtest/ivltests/pr1869772.v @@ -0,0 +1,17 @@ +module top; + reg [7:0] vec = 8'b10100101; + reg passed = 1; + + function [3:0] copy; + input [3:0] in; + copy = in; + endfunction + + initial begin + if (copy(vec>>4) != 4'b1010) begin + passed = 0; + $display("Failed!"); + end + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1869781.v b/ivtest/ivltests/pr1869781.v new file mode 100644 index 000000000..ccedf39be --- /dev/null +++ b/ivtest/ivltests/pr1869781.v @@ -0,0 +1,29 @@ +module dummy; + +integer i; +integer foo_value; +reg [1:0] foo_bit; + +initial +begin + i = 1; + foo_value = 10; + foo_bit[i] <= #foo_value 1'b0; + + /* + NOTE: + if you replace previous line either with: + foo_bit[1] <= #foo_value 1'b0; + or with: + foo_bit[i] <= #10 1'b0; + then "invalid opcode" is not shown + */ + + #20 if (foo_bit[1] !== 1'b0) begin + $display("FAILED -- foo_bit[1] = %b", foo_bit[1]); + $finish; + end + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr1873146.v b/ivtest/ivltests/pr1873146.v new file mode 100644 index 000000000..c57f8255a --- /dev/null +++ b/ivtest/ivltests/pr1873146.v @@ -0,0 +1,18 @@ +module test (a, b); + + output [31 : 0] a; + input b; + + buf bufd[31:0] (a, b); + initial#1 $display("PASSED"); + specify + specparam + + th = 0.9; + + // This incomplete set of specify cases needs to be handled. + if (!b) + (b *> a[0]) = (0); + endspecify + +endmodule diff --git a/ivtest/ivltests/pr1873372.v b/ivtest/ivltests/pr1873372.v new file mode 100644 index 000000000..13f3869b5 --- /dev/null +++ b/ivtest/ivltests/pr1873372.v @@ -0,0 +1,11 @@ +module top; + wire real sml; + wire real big; + wire real prec; + + assign sml = 1e-20; + assign big = 1e20; + assign prec = 0.123456789; + + initial $display("big: %g, small: %g, precision: %0.11f", big, sml, prec); +endmodule diff --git a/ivtest/ivltests/pr1875866.v b/ivtest/ivltests/pr1875866.v new file mode 100644 index 000000000..407c319e3 --- /dev/null +++ b/ivtest/ivltests/pr1875866.v @@ -0,0 +1,25 @@ +`timescale 1ns/1ns + +module test(); + + reg [4 : 0] A = 5'b0; + reg CLK = 1'b0; + + integer pipe; + + + initial + begin + #2000 if (A !== 0) + $display("FAILED"); + else + $display("PASSED"); + $finish; + end + always #20 CLK = !CLK; + + always @(posedge CLK) + for(pipe = 2; pipe <= -1; pipe = pipe + 1) + A<=A+1; + +endmodule // test diff --git a/ivtest/ivltests/pr1875866b.v b/ivtest/ivltests/pr1875866b.v new file mode 100644 index 000000000..656528c91 --- /dev/null +++ b/ivtest/ivltests/pr1875866b.v @@ -0,0 +1,28 @@ +`timescale 1ns/1ns + +module test(); + + reg [4 : 0] A = 5'b0; + reg CLK = 1'b0; + + parameter stages = 0; + + integer pipe; + + + initial + begin + #2000 $display("PASSED"); + $finish; + end + + always #20 CLK = !CLK; + + always @(posedge CLK) + for(pipe = 2; pipe <= stages -1; pipe = pipe + 1) begin + $display("FAILED"); + $finish; + A<=A+1; + end + +endmodule // test diff --git a/ivtest/ivltests/pr1876798.v b/ivtest/ivltests/pr1876798.v new file mode 100644 index 000000000..a1401b306 --- /dev/null +++ b/ivtest/ivltests/pr1876798.v @@ -0,0 +1,31 @@ +// Copyright 2008, Martin Whitaker. +// This file may be freely copied for any purpose. + +module scan_int_array(); + +integer f; + +integer i; +integer n; + +integer v[0:3]; + +initial begin + f = $fopen("work/temp.txt", "w"); + for (i = 0; i < 4; i = i + 1) begin + $fdisplay(f, "%d", i); + end + $fclose(f); + + f = $fopen("work/temp.txt", "r"); + for (i = 0; i < 4; i = i + 1) begin + n = $fscanf(f, " %d ", v[i]); + end + $fclose(f); + + for (i = 0; i < 4; i = i + 1) begin + $display("%1d", v[i]); + end +end + +endmodule diff --git a/ivtest/ivltests/pr1877740.v b/ivtest/ivltests/pr1877740.v new file mode 100644 index 000000000..6dc835d4f --- /dev/null +++ b/ivtest/ivltests/pr1877740.v @@ -0,0 +1,22 @@ +module top; + reg pass = 1; + initial begin + if (4'sd2 < -2) begin + $display("Failed for operator <"); + pass = 0; + end + if (4'sd2 <= -2) begin + $display("Failed for operator <="); + pass = 0; + end + if (-2 > 4'sd2) begin + $display("Failed for operator >"); + pass = 0; + end + if (-2 >= 4'sd2) begin + $display("Failed for operator >="); + pass = 0; + end + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1877743.v b/ivtest/ivltests/pr1877743.v new file mode 100644 index 000000000..d47583935 --- /dev/null +++ b/ivtest/ivltests/pr1877743.v @@ -0,0 +1,91 @@ +`timescale 1ns/10ps +module top; + reg pass = 1'b1; + reg a, b, ci; + wire co, s; + adder dut(co, s, a, b, ci); + + initial begin + // The initial value propagates in 1.6 nS. + #1.59 check_result(1'bx, 1'bx, 1); + + #1 a = 0; b = 0; ci = 0; // 1.7 + #1.69 check_result(1'bx, 1'b0, 2); + + // Check the a => s delays. + #1 a = 1; b = 0; ci = 0; // 1.1 + #1.09 check_result(1'b0, 1'b1, 3); + #1 a = 0; b = 0; ci = 0; // 1.9 + #1.89 check_result(1'b1, 1'b0, 4); + + // Check the b => s delays. + #1 a = 0; b = 1; ci = 0; // 1.2 + #1.19 check_result(1'b0, 1'b1, 5); + #1 a = 0; b = 0; ci = 0; // 1.8 + #1.79 check_result(1'b1, 1'b0, 6); + + // Check the ci => s delays. + #1 a = 0; b = 0; ci = 1; // 1.3 + #1.29 check_result(1'b0, 1'b1, 7); + #1 a = 0; b = 0; ci = 0; // 1.7 + #1.69 check_result(1'b1, 1'b0, 8); + + // Check the a => s delays (state-dependent). + #1 a = 0; b = 1; ci = 0; + #3 a = 1; b = 1; ci = 0; // 2.0 + #1.99 check_result(1'b1, 1'b0, 9); + #1 a = 0; b = 1; ci = 0; // 1.0 + #0.99 check_result(1'b0, 1'b1, 10); + + #1 a = 0; b = 1; ci = 1; + #3 a = 1; b = 1; ci = 1; // 1.4 + #1.39 check_result(1'b0, 1'b1, 11); + #1 a = 0; b = 1; ci = 1; // 1.6 + #1.59 check_result(1'b1, 1'b0, 12); + + // Check the co delay. + #1 a = 0; b = 1; ci = 0; + #1.49; + if (co !== 1'b1) begin + $display("Failed initial value for co test, %b != 1'b1", co); + pass = 1'b0; + end + #0.02; + if (co !== 1'b0) begin + $display("Failed final value for co test, %b != 1'b0", co); + pass = 1'b0; + end + + #10 if (pass) $display("PASSED"); + end + + task check_result(input cur, input next, input integer num); + begin + if (s !== cur) begin + $display("Failed initial value for test %0d, %b != %b", num, s, cur); + pass = 1'b0; + end + #0.02; + if (s !== next) begin + $display("Failed final value for test %0d, %b != %b", num, s, next); + pass = 1'b0; + end + end + endtask +endmodule + +module adder (co, s, a, b, ci); + input a, b, ci; + output co, s; + + assign {co, s} = a + b + ci; + + specify + (a, b, ci => co) = 1.5; + (ci => s) = (1.3, 1.7); + if (b === 1'b1 && ci === 1'b0) (a => s) = (1, 2); + if (b === 1'b1 && ci === 1'b1) (a => s) = (1.4, 1.6); + ifnone (a => s) = (1.1, 1.9); + ifnone (b => s) = (1.2, 1.8); + endspecify +endmodule diff --git a/ivtest/ivltests/pr1878909.v b/ivtest/ivltests/pr1878909.v new file mode 100644 index 000000000..04ab15d0a --- /dev/null +++ b/ivtest/ivltests/pr1878909.v @@ -0,0 +1,32 @@ +module test_top(); + + wire [3:0] test_val; + + test_mod test_mod0 [3:0]( + .in_0(1'b1), + .out_0(test_val) + ); + + initial begin + #1; + if(test_val != 4'b0000) $display("Failed"); + else $display("PASSED"); + end +endmodule + +module test_mod( + in_0, out_0 + ); + input in_0; + output out_0; + + function test; + input moo; + begin + test = ~moo; + end + endfunction + + assign out_0 = test(in_0); + +endmodule diff --git a/ivtest/ivltests/pr1879226.v b/ivtest/ivltests/pr1879226.v new file mode 100644 index 000000000..bbac01619 --- /dev/null +++ b/ivtest/ivltests/pr1879226.v @@ -0,0 +1,46 @@ +`timescale 1ns/1ns + +module test; + +reg pass = 1; + +reg [3 : 0] A = 4'hf; +wire [3 : 0] a_lls, a_lrs; + +reg signed [3 : 0] B = 7; +wire signed [3 : 0] b_als, b_ars; + +assign a_lls = A<<4; +assign a_lrs = A>>4; +assign b_als = B<<<4; +assign b_ars = B>>>4; + +initial begin + #1; + if (a_lls !== 4'b0) begin + $display("FAILED assigning logical left shift"); + pass = 0; + end + if (a_lrs !== 4'b0) begin + $display("FAILED assigning logical right shift"); + pass = 0; + end + if (b_als !== 4'b0) begin + $display("FAILED assigning arithmetic left shift"); + pass = 0; + end + if (b_ars !== 4'h0) begin + $display("FAILED assigning arithmetic right shift (0)"); + pass = 0; + end + #1 B = -8; + #1; + if (b_ars !== 4'hf) begin + $display("FAILED assigning arithmetic right shift (1)"); + pass = 0; + end + + if (pass) $display("PASSED"); +end + +endmodule // test diff --git a/ivtest/ivltests/pr1880003.v b/ivtest/ivltests/pr1880003.v new file mode 100644 index 000000000..e255b36f7 --- /dev/null +++ b/ivtest/ivltests/pr1880003.v @@ -0,0 +1,33 @@ +`timescale 1us/100ns + +module top; + reg pass = 1'b1; + + real ra = 1.0; + wire real rufunc; + + assign #10 rufunc = rl_func(ra); + + initial begin + #1 if (rufunc == 2.0) begin + pass = 1'b0; + $display("Real: user function value (%f) not delayed.", rufunc); + end + #8 if (rufunc == 2.0) begin + pass = 1'b0; + $display("Real: user function value (%f) not delayed.", rufunc); + end + #2; + if (rufunc != 2.0) begin + pass = 1'b0; + $display("Real: user function value not delayed correctly."); + end + if (pass) $display("PASSED"); + end + + function real rl_func; + input real in; + rl_func = in * 2.0; + endfunction + +endmodule diff --git a/ivtest/ivltests/pr1883052.v b/ivtest/ivltests/pr1883052.v new file mode 100644 index 000000000..429b16bd7 --- /dev/null +++ b/ivtest/ivltests/pr1883052.v @@ -0,0 +1,27 @@ +`timescale 1us/100ns + +module top; + reg pass = 1'b1; + + reg [3:0] ia = 4'd1, ib = 4'd2; + wire signed [3:0] icon; + + assign #1 icon = {ib[1:0], ia[0]}; // Should give 5 after a delay. + + initial begin + #0.9; + if (icon !== 4'bx) begin + pass = 1'b0; + $display("concatenation value not delayed, expected 4'bx got %b.", icon); + end + + #0.1; + #0; + if (icon !== 4'd5) begin + pass = 1'b0; + $display("concatenation value not correct, expected 4'd5 got %d.", icon); + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1883052b.v b/ivtest/ivltests/pr1883052b.v new file mode 100644 index 000000000..55f6db6c0 --- /dev/null +++ b/ivtest/ivltests/pr1883052b.v @@ -0,0 +1,76 @@ +`timescale 1us/100ns + +module top; + reg pass = 1'b1; + + reg [3:0] ia = 4'd1; + wire signed [3:0] iconstp, iconstm, isfunc, iufunc; + wire [7:0] istring; + + /* Integer constant value. */ + assign #1 iconstp = 2; // 2 + assign #1 iconstm = -2; // -2 + assign #1 istring = "0"; // "0" + + /* Integer System Function. */ + assign #1 isfunc = $rtoi(2.0); // 2 + + /* Integer User Function. */ + assign #1 iufunc = int_func(ia); // 2 + + initial begin +// $monitor($realtime,, iconstp,, iconstm,, istring,, iufunc,, isfunc); + #0.9; + if (iconstp !== 4'bx) begin + pass = 1'b0; + $display("Integer: constant (positive) value not delayed."); + end + if (iconstm !== 4'bx) begin + pass = 1'b0; + $display("Integer: constant (negative) value not delayed."); + end + if (istring !== 8'bx) begin + pass = 1'b0; + $display("Integer: string value not delayed."); + end + if (isfunc !== 4'bx) begin + pass = 1'b0; + $display("Integer: system function value not delayed."); + end + if (iufunc !== 4'bx) begin + pass = 1'b0; + $display("Integer: user function value not delayed."); + end + + #0.1; + #0; + if (iconstp !== 2) begin + pass = 1'b0; + $display("Integer: constant (positive) value not delayed correctly."); + end + if (iconstm !== -2) begin + pass = 1'b0; + $display("Integer: constant (negative) value not delayed correctly."); + end + if (istring !== "0") begin + pass = 1'b0; + $display("Integer: string value not delayed correctly."); + end + if (isfunc !== 2) begin + pass = 1'b0; + $display("Integer: system function value not delayed correctly."); + end + if (iufunc !== 2) begin + pass = 1'b0; + $display("Integer: user function value not delayed correctly."); + end + + if (pass) $display("PASSED"); + end + + function [31:0] int_func; + input [31:0] in; + int_func = in * 2; + endfunction + +endmodule diff --git a/ivtest/ivltests/pr1885847.v b/ivtest/ivltests/pr1885847.v new file mode 100644 index 000000000..c432fccda --- /dev/null +++ b/ivtest/ivltests/pr1885847.v @@ -0,0 +1,21 @@ +// Copyright 2008, Martin Whitaker. +// This file may be freely copied for any purpose. + +module localparam_sign(); + +localparam P1 = 16; +localparam P2 = P1 * 2; + +submodule #(P2) submodule(); + +endmodule + +module submodule(); + +parameter P3 = 1; + +initial begin + $display("P3 = %0d", P3); +end + +endmodule diff --git a/ivtest/ivltests/pr1887168.v b/ivtest/ivltests/pr1887168.v new file mode 100644 index 000000000..6de9d069d --- /dev/null +++ b/ivtest/ivltests/pr1887168.v @@ -0,0 +1,76 @@ +// Copyright 2008, Martin Whitaker. +// This file may be freely copied for any purpose. + +module constant_integer_div_mod(); + +initial begin + $display("%4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d", + 31'd10 / 'd3, + 31'd11 / 'd3, + 31'd12 / 'd3, + 31'sd10 / 3, + 31'sd11 / 3, + 31'sd12 / 3, + -31'sd10 / 3, + -31'sd11 / 3, + -31'sd12 / 3, + 31'sd10 / -3, + 31'sd11 / -3, + 31'sd12 / -3, + -31'sd10 / -3, + -31'sd11 / -3, + -31'sd12 / -3); + + $display("%4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d", + 65'd10 / 'd3, + 65'd11 / 'd3, + 65'd12 / 'd3, + 65'sd10 / 3, + 65'sd11 / 3, + 65'sd12 / 3, + -65'sd10 / 3, + -65'sd11 / 3, + -65'sd12 / 3, + 65'sd10 / -3, + 65'sd11 / -3, + 65'sd12 / -3, + -65'sd10 / -3, + -65'sd11 / -3, + -65'sd12 / -3); + + $display("%4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d", + 31'd10 % 'd3, + 31'd11 % 'd3, + 31'd12 % 'd3, + 31'sd10 % 3, + 31'sd11 % 3, + 31'sd12 % 3, + -31'sd10 % 3, + -31'sd11 % 3, + -31'sd12 % 3, + 31'sd10 % -3, + 31'sd11 % -3, + 31'sd12 % -3, + -31'sd10 % -3, + -31'sd11 % -3, + -31'sd12 % -3); + + $display("%4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d %4d", + 65'd10 % 'd3, + 65'd11 % 'd3, + 65'd12 % 'd3, + 65'sd10 % 3, + 65'sd11 % 3, + 65'sd12 % 3, + -65'sd10 % 3, + -65'sd11 % 3, + -65'sd12 % 3, + 65'sd10 % -3, + 65'sd11 % -3, + 65'sd12 % -3, + -65'sd10 % -3, + -65'sd11 % -3, + -65'sd12 % -3); +end + +endmodule diff --git a/ivtest/ivltests/pr1892959.v b/ivtest/ivltests/pr1892959.v new file mode 100644 index 000000000..c418ee836 --- /dev/null +++ b/ivtest/ivltests/pr1892959.v @@ -0,0 +1,36 @@ +module top; + reg pass = 1'b1; + reg [1:0] in; + wire out; + + function IS_NOT_ZERO; + input [3:0] in; + begin + IS_NOT_ZERO = |in; + end + endfunction + + assign out = (IS_NOT_ZERO(in) == 1'b1); + + initial begin + in = 2'b00; + #1 if (out != 1'b0) begin + $display("Failed for 2'b00 case."); + pass = 1'b0; + end + + in = 2'b01; + #1 if (out != 1'b1) begin + $display("Failed for 2'b01 case."); + pass = 1'b0; + end + + in = 2'b10; + #1 if (out != 1'b1) begin + $display("Failed for 2'b01 case."); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1892959b.v b/ivtest/ivltests/pr1892959b.v new file mode 100644 index 000000000..8b72d58a1 --- /dev/null +++ b/ivtest/ivltests/pr1892959b.v @@ -0,0 +1,51 @@ +`define DEV_TYPE "DEVICE 2" + +module top; + parameter device = `DEV_TYPE; + wire res; + +function is_dev1; + input[8*20:1] device; + reg is_device; +begin + if ((device == "DEVICE1") || (device == "DEVICE 1")) + is_device = 1; + else + is_device = 0; + + is_dev1 = is_device; +end +endfunction + +function is_dev2; + input[8*20:1] device; + reg is_device; +begin + if ((device == "DEVICE2") || (device == "DEVICE 2")) + is_device = 1; + else + is_device = 0; + + is_dev2 = is_device; +end +endfunction + +function is_dev; + input[8*20:1] device; + reg is_device; +begin +// Changing this to a single item makes things work. + if (is_dev1(device) || is_dev2(device)) + is_device = 1; + else + is_device = 0; + + is_dev = is_device; +end +endfunction + + assign res = (is_dev(device) == 1) ? 1'b1 : 1'b0; + + initial #1 if (res == 1'b1) $display("PASSED"); + else $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/pr1898293.v b/ivtest/ivltests/pr1898293.v new file mode 100644 index 000000000..03974fa06 --- /dev/null +++ b/ivtest/ivltests/pr1898293.v @@ -0,0 +1,37 @@ +module top; + reg pass = 1'b1; + + reg [1:0] rval = 2'b10; + wire [1:0] wval = (wval > 0) ? 2'b01 : 2'b00; + // This works as follows: + // rlval starts are 0.0 which is not greater than 0.0 (false). + // This sets rlval to 2.0 which is greater than 0.0 (true). + // This then sets the value to 1.0 which is still true and stable. + wire real rlval = (rlval > 0.0) ? 1.0 : 2.0; + + initial begin + #1; + if (rval != 2'b10) begin + $display("FAILED initial value expected 2'b10, got %b.", rval); + pass = 1'b0; + end + + if (wval !== 2'b0x) begin + $display("FAILED net value expected 2'b0x, got %b.", wval); + pass = 1'b0; + end + + if (rlval != 1.0) begin + $display("FAILED net real value expected 1.0, got %f.", rlval); + pass = 1'b0; + end + + #1 assign rval = (rval > 0) ? 2'b01 : 2'b00; + if (rval != 2'b01) begin + $display("FAILED forced value expected 2'b01, got %b.", rval); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1898983.v b/ivtest/ivltests/pr1898983.v new file mode 100644 index 000000000..391d4d66e --- /dev/null +++ b/ivtest/ivltests/pr1898983.v @@ -0,0 +1,17 @@ +module top; + reg [1:0] in; + subm sm [1:0](in); + + initial begin + // This should trigger instance 0. + in[0] = 0; + #1 in[0] = 1; + // This should trigger instance 1. + in[1] = 0; + #1 in[1] = 1; + end +endmodule + +module subm(input wire in); + always @(posedge in) $display("In %m at %0t", $time); +endmodule diff --git a/ivtest/ivltests/pr1901125.v b/ivtest/ivltests/pr1901125.v new file mode 100644 index 000000000..1db757e20 --- /dev/null +++ b/ivtest/ivltests/pr1901125.v @@ -0,0 +1,18 @@ +// pr1901125 + +module test(); + function integer hallo (input integer x); + hallo = x - 1; + endfunction // hallo + + integer foo; + initial begin + foo = hallo(10); + if (foo !== 9) begin + $display("FAILED -- foo=%d", foo); + $finish; + end + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1903157.v b/ivtest/ivltests/pr1903157.v new file mode 100644 index 000000000..1ce8b1b5a --- /dev/null +++ b/ivtest/ivltests/pr1903157.v @@ -0,0 +1,12 @@ +module test; + +parameter DATA_DEPTH_A = 8; +parameter DATA_DEPTH_B = 2**8; +reg [(2**8)-1:0] data1 ; //this gets compiled +reg [7:0] data2 [DATA_DEPTH_A-1:0]; // this gets compiled +reg [DATA_DEPTH_A-1:0] data3 [7:0]; // this gets compiled +reg [DATA_DEPTH_B-1:0] data4 [7:0]; // this gets compiled +reg [7:0] data5 [(2**8)-1:0]; // results in compilation error +reg [7:0] data6 [DATA_DEPTH_B-1:0]; // results in compilation error + +endmodule diff --git a/ivtest/ivltests/pr1903324.v b/ivtest/ivltests/pr1903324.v new file mode 100644 index 000000000..9bab377a6 --- /dev/null +++ b/ivtest/ivltests/pr1903324.v @@ -0,0 +1,34 @@ +module top; + reg pass = 1'b1; + + reg [7:0] d_reg = 8'b10100101; + wire [7:0] d_wire = 8'b01011010; + + test tstr(d_reg); + test tstw(d_wire); + + initial begin + #1; + /* Check with a register. */ + if (tstr.data_in_array[3] != d_reg) begin + $display("FAILED: with a register value."); + pass = 1'b0; + end + + /* Check with a wire. */ + if (tstw.data_in_array[3] != d_wire) begin + $display("FAILED: with a net value."); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule + +module test(input [8:1] data_in) ; + + wire [7:0] data_in_array[4:3]; + + assign data_in_array[3] = data_in; + assign data_in_array[4] = 8'b0; +endmodule diff --git a/ivtest/ivltests/pr1903343.v b/ivtest/ivltests/pr1903343.v new file mode 100644 index 000000000..3566214e7 --- /dev/null +++ b/ivtest/ivltests/pr1903343.v @@ -0,0 +1,36 @@ +`timescale 1ns/10ps + +module top; +// Comment out this line and the $display below to get elaboration to fail. + integer max = 2 ** 2; + + initial begin + test_ok; +// test_fail; + $display("Main: %3d", max); + end + + // This works. + task test_ok; + integer max; + + begin + max = 2 ** 8; + $display("OK: %3d", max); + end + endtask + +/* + * This is invalid syntax! You can not do an assignment in a block + * level variable declaration (task, function, etc.). + // And this is failing! It appears to be looking in the wrong scope. + task test_fail; + integer max = 2 ** 8; + + begin + $display("Fail: %3d", max); + end + endtask + */ + +endmodule diff --git a/ivtest/ivltests/pr1903520.v b/ivtest/ivltests/pr1903520.v new file mode 100644 index 000000000..c287b762a --- /dev/null +++ b/ivtest/ivltests/pr1903520.v @@ -0,0 +1,13 @@ +module test(); +wire [1:0] b; + +assign b[0] = 0; + +a a(~b[0]); + +endmodule + +module a(b); +input b; +initial #1 if (b) $display("PASSED"); else $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/pr1907192.v b/ivtest/ivltests/pr1907192.v new file mode 100644 index 000000000..c5bf7866b --- /dev/null +++ b/ivtest/ivltests/pr1907192.v @@ -0,0 +1,16 @@ +module top; + + parameter cond = 1; + parameter value = 25; + parameter test = (cond) ? 5: 0; + + defparam dut.lwrval = (cond == 1) ? 6: (100/value) + 0.5; + + lower dut(); + +endmodule + +module lower; + parameter lwrval = 4; + initial if (lwrval != 6.0) $display("FAILED"); else $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/pr1909940.v b/ivtest/ivltests/pr1909940.v new file mode 100644 index 000000000..5fcb0f787 --- /dev/null +++ b/ivtest/ivltests/pr1909940.v @@ -0,0 +1,7 @@ +module top; + wire out; +// wire in; // Adding this makes it compile. + assign out = ~in; + assign in = 1'b0; + initial #1 if (out == 1'b1) $display("PASSED"); else $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/pr1909940b.v b/ivtest/ivltests/pr1909940b.v new file mode 100644 index 000000000..978b9db31 --- /dev/null +++ b/ivtest/ivltests/pr1909940b.v @@ -0,0 +1,11 @@ +module top; + wire out; +// wire in; // Adding this makes it compile. + assign out = ~in; + zero zzz(in); + initial #1 if (out == 1'b1) $display("PASSED"); else $display("FAILED"); +endmodule + +module zero(output wire foo); + assign foo = 1'b0; +endmodule diff --git a/ivtest/ivltests/pr1912112.v b/ivtest/ivltests/pr1912112.v new file mode 100644 index 000000000..fbae97bdd --- /dev/null +++ b/ivtest/ivltests/pr1912112.v @@ -0,0 +1,6 @@ +`define world World +`define test Hello `world + +module test; + initial $display("The `test definition is: `define %s", ``test); +endmodule diff --git a/ivtest/ivltests/pr1912843.v b/ivtest/ivltests/pr1912843.v new file mode 100644 index 000000000..be0821426 --- /dev/null +++ b/ivtest/ivltests/pr1912843.v @@ -0,0 +1,12 @@ +`timescale 1ps / 1ps + +module test(); + reg[31:0] arr[1:0]; + + initial begin + arr[0] = 'd1; + arr[1] = 'd5; + if (arr[0] + 1 + 1 > 4) $display("FAILED"); else $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1913918a.v b/ivtest/ivltests/pr1913918a.v new file mode 100644 index 000000000..3a2d6374e --- /dev/null +++ b/ivtest/ivltests/pr1913918a.v @@ -0,0 +1,16 @@ +// pr1913918 +module test(); + parameter a = 4'b1000; + b b(a[3]); +endmodule // test + +module b(c); + input c; + initial #1 begin + if (c !== 1'b1) begin + $display("FAILED -- c = %b", c); + $finish; + end + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1913918b.v b/ivtest/ivltests/pr1913918b.v new file mode 100644 index 000000000..cce82fd44 --- /dev/null +++ b/ivtest/ivltests/pr1913918b.v @@ -0,0 +1,17 @@ +// pr1913918b + +module test ( output a); + + parameter [9:1] b = 9'b0_0000_0010; + + assign a = b[1] ^ b[9]; + + initial #1 begin + if (a !== 1'b0) begin + $display("FAILED -- b=%b, a=%b", b, a); + $finish; + end + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1913918c.v b/ivtest/ivltests/pr1913918c.v new file mode 100644 index 000000000..34eacee27 --- /dev/null +++ b/ivtest/ivltests/pr1913918c.v @@ -0,0 +1,16 @@ +// pr1913918c + +module test ( output reg a); + + parameter [9:1] b = 9'b0_0000_0010; + + initial begin + a = b[1] ^ b[9]; + if (a !== 1'b0) begin + $display("FAILED -- b=%b, a=%b", b, a); + $finish; + end + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1913937.v b/ivtest/ivltests/pr1913937.v new file mode 100644 index 000000000..7f06adc12 --- /dev/null +++ b/ivtest/ivltests/pr1913937.v @@ -0,0 +1,35 @@ +/* This test checks two thing: + * + * The first is that the AND arguments are padded if one is + * smaller than the other. This was causing an assert. + * + * The second is that the reduction operator does not pass + * the expression width to its arguments. This will give an + * incorrect result (01 vs 00). + */ +module test (); + reg pass = 1'b1; + + reg [1:0] ra; + wire [1:0] a; + wire [3:0] b = 4'b1111; + wire [3:0] c = 4'b1111; + + assign a = |((c & ~(1'b1<<9'h00)) & b); + + initial begin + #1; + if (a !== 2'b01) begin + $display("FAILED: cont. assign, expected 2'b01, got %b", a); + pass = 1'b0; + end + + ra = |((c & ~(1'b1<<9'h00)) & b); + if (ra !== 2'b01) begin + $display("FAILED: proc. assign, expected 2'b01, got %b", ra); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1916261.v b/ivtest/ivltests/pr1916261.v new file mode 100644 index 000000000..e2b7d1586 --- /dev/null +++ b/ivtest/ivltests/pr1916261.v @@ -0,0 +1,24 @@ +module top; + reg pass = 1'b1; + + parameter one = 1'b1; + parameter zero = 1'b0; + + wire [3:0] ca_tru = one ? 4'b0001 : 4'b0000; + wire [3:0] ca_fal = zero ? 4'b0000 : 4'b0010; + + initial begin + #1; + if (ca_tru != 4'b0001) begin + $display("FAILED: CA true expression (%b != 4'b0001)", ca_tru); + pass = 1'b0; + end + + if (ca_fal != 4'b0010) begin + $display("FAILED: CA false expression (%b != 4'b0010)", ca_fal); + pass = 1'b0; + end + + if(pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1916261a.v b/ivtest/ivltests/pr1916261a.v new file mode 100644 index 000000000..4fe8e1e8b --- /dev/null +++ b/ivtest/ivltests/pr1916261a.v @@ -0,0 +1,11 @@ +module top; + parameter one = 1'b1; + parameter zero = 1'b0; + + // These should fail since a zero replication is invalid in this context. + wire [3:0] ca_tru = one ? 4'b0001 : {0{1'b0}}; + wire [3:0] ca_fal = zero ? {0{1'b0}} : 4'b0010; + + // We used to not check for this so just pass for that case + initial $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/pr1921332.v b/ivtest/ivltests/pr1921332.v new file mode 100644 index 000000000..4271713bb --- /dev/null +++ b/ivtest/ivltests/pr1921332.v @@ -0,0 +1,18 @@ +module test (D); + + input D; + + prim p (a, D, D, D); + +endmodule + +primitive prim (Z, A, B, S); + + output Z; + input A, B, S; + + table + 0 0 x : 0 ; + endtable + +endprimitive diff --git a/ivtest/ivltests/pr1924845.v b/ivtest/ivltests/pr1924845.v new file mode 100644 index 000000000..e44891254 --- /dev/null +++ b/ivtest/ivltests/pr1924845.v @@ -0,0 +1,40 @@ +module test; + reg pass = 1'b1; + + parameter con = 1 * -2; + parameter a = 1; + parameter b = -2; + parameter mul = a * b; + parameter sum = a + b; + parameter div = b / a; + parameter sub = b - a; + + initial begin + if (con != -2) begin + $display("FAILED: constant mult. expected -2, got %d (%b)", con, con); + pass = 1'b0; + end + + if (mul != -2) begin + $display("FAILED: multiplication expected -2, got %d (%b)", mul, mul); + pass = 1'b0; + end + + if (div != -2) begin + $display("FAILED: division expected -2, got %d (%b)", div, div); + pass = 1'b0; + end + + if (sum != -1) begin + $display("FAILED: summation expected -1, got %d (%b)", sum, sum); + pass = 1'b0; + end + + if (sub != -3) begin + $display("FAILED: subtraction expected -3, got %d (%b)", sub, sub); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1925356.v b/ivtest/ivltests/pr1925356.v new file mode 100644 index 000000000..5f7b9854a --- /dev/null +++ b/ivtest/ivltests/pr1925356.v @@ -0,0 +1,16 @@ +module top; + reg pass = 1'b0; + + integer lp; + reg [7:0] ival = 8'b0; + + initial begin + /* If `ival' is replaced by a literal `0' this works... */ + for(lp = ival; lp < 5; lp = lp + 1) begin + pass = 1'b1; + end + + if(pass) $display("PASSED"); + else $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/pr1925360.v b/ivtest/ivltests/pr1925360.v new file mode 100644 index 000000000..9e4f64d03 --- /dev/null +++ b/ivtest/ivltests/pr1925360.v @@ -0,0 +1,9 @@ +`define MAC(i) $display(i); + +module top; +initial begin + if ("$display(in);" != ``MAC(in)) + $display("FAILED: expected \"display(in);\", got \"`MAC(in)\""); + else $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/pr1925363a.v b/ivtest/ivltests/pr1925363a.v new file mode 100644 index 000000000..3ff508211 --- /dev/null +++ b/ivtest/ivltests/pr1925363a.v @@ -0,0 +1,9 @@ +module top; + parameter wid = 9; + + wire [31:0] apass; + wire [31:0] afail; + + assign apass = {(wid-8){ 8'b0}}; // This will pass. + assign afail = {(wid-16){8'b0}}; // and this will fail. +endmodule diff --git a/ivtest/ivltests/pr1925363b.v b/ivtest/ivltests/pr1925363b.v new file mode 100644 index 000000000..a20fa14b8 --- /dev/null +++ b/ivtest/ivltests/pr1925363b.v @@ -0,0 +1,11 @@ +module top; + parameter wid = 9; + + reg [31:0] rpass; + reg [31:0] rfail; + + initial begin + rpass = {(wid-8){ 8'b0}}; // This will pass + rfail = {(wid-16){8'b0}}; // and this will fail. + end +endmodule diff --git a/ivtest/ivltests/pr1932444.v b/ivtest/ivltests/pr1932444.v new file mode 100644 index 000000000..dba89d9f2 --- /dev/null +++ b/ivtest/ivltests/pr1932444.v @@ -0,0 +1,39 @@ +module test; + reg pass = 1'b1; + + reg array[1:0]; + reg [7:0] delay[1:0]; + integer i = 1, j = 0; + + initial begin + delay[0] = 8'd4; + delay[1] = 8'd6; + array[j] <= #(delay[0]) 1'b0; + array[i] <= #(delay[i]) 1'b1; + #3; + if (array[0] !== 1'bx) begin + $display("FAILED: array[0] != 1'bx @ 3"); + pass = 1'b0; + end + + #2; + if (array[0] !== 1'b0) begin + $display("FAILED: array[0] != 1'b0 @ 5"); + pass = 1'b0; + end + + if (array[1] !== 1'bx) begin + $display("FAILED: array[1] != 1'bx @ 5"); + pass = 1'b0; + end + + #2; + if (array[1] !== 1'b1) begin + $display("FAILED: array[1] != 1'b1 @ 7"); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + + end +endmodule diff --git a/ivtest/ivltests/pr1934744.v b/ivtest/ivltests/pr1934744.v new file mode 100644 index 000000000..5e31e6de3 --- /dev/null +++ b/ivtest/ivltests/pr1934744.v @@ -0,0 +1,37 @@ +// $ iverilog -Wall simpler.v -o simpler +// $ vvp simpler +// simpler:37: syntax error + +`timescale 1ns / 1ns + +module simpler; + +reg [1:0] cnt=0; +wire result; + +defparam \Mcount_cnt_xor<3>11 .INIT = 4'hC; +test_lut \Mcount_cnt_xor<3>11 ( + .a0(cnt[0]), + .a1(cnt[1]), + .O(result) +); + +initial $display("PASSED"); + +endmodule + + +module test_lut (output O, input a0, input a1); + parameter INIT = 4'h0; + + reg tmp; + always @(*) tmp = mux ( INIT, {a1, a0}); + assign O = tmp; + + function mux; + input [3:0] d; + input [1:0] s; + mux = d[s]; + endfunction + +endmodule diff --git a/ivtest/ivltests/pr1936363.v b/ivtest/ivltests/pr1936363.v new file mode 100644 index 000000000..4822f7c57 --- /dev/null +++ b/ivtest/ivltests/pr1936363.v @@ -0,0 +1,28 @@ +module tern; + +reg [13:0] fdbk_err_wide; + +// arithmetic saturation from 14 bits down to 13 bits, and drop lsb +wire [11:0] fdbk_err = ((fdbk_err_wide[13:12]==2'b00) | (fdbk_err_wide[13:12]==2'b11)) ? + fdbk_err_wide[12:1] : {fdbk_err_wide[13],{11{~fdbk_err_wide[13]}}}; + +initial begin + #10; + $display(fdbk_err_wide, fdbk_err); + // 2008-03-04 snapshot prints x x, 2008-04-02 git prints x z + // 01eb298228d0adce9d62818e21d47fb274af9060 is first "bad" commit + #10; + fdbk_err_wide = 42; + #10; + $display(fdbk_err_wide, fdbk_err); + // everybody agrees this is 42 21 + #10; + fdbk_err_wide = 14'bxxxxxxxxxxxxxx; + #10; + // everybody agrees this is x x + $display(fdbk_err_wide, fdbk_err); + #10; + $finish(0); +end + +endmodule diff --git a/ivtest/ivltests/pr1938138.v b/ivtest/ivltests/pr1938138.v new file mode 100644 index 000000000..5a61b1780 --- /dev/null +++ b/ivtest/ivltests/pr1938138.v @@ -0,0 +1,12 @@ +module a(); +endmodule + +module test(); +a a(); +endmodule + +module a(); +endmodule + +module b(); +endmodule diff --git a/ivtest/ivltests/pr1939165.v b/ivtest/ivltests/pr1939165.v new file mode 100644 index 000000000..ac80130fe --- /dev/null +++ b/ivtest/ivltests/pr1939165.v @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2008 Gyorgy Jeney (nog@sdf.lonestar.org) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module fpu_li_s1(); + +parameter eh = 11; +parameter [eh - 1:0] alap = 1023; + +parameter ih2 = 6; + +parameter fh = 7; +parameter [fh - 1:0] falap = 63; + +localparam ih = 1 << ih2; +localparam nh = (eh > fh ? eh : fh) + 1; + +wire [nh - 1:0] exp_norm; + +/* IVL compiles this fine but when trying to run it through vvp, it throws + * this error: + * + * internal error: port 0 expects wid=11, got wid=12 + * vvp: concat.cc:56: virtual void vvp_fun_concat::recv_vec4(vvp_net_ptr_t, const + * vvp_vector4_t&): Assertion `0' failed. + * Aborted + * + * This is a regression caused by this commit: + * commit a914eda5eff8b088837432a6516584b6a075fcd6 + * Author: Stephen Williams + * Date: Tue Apr 8 20:50:36 2008 -0700 + * + * Get part select from vectored parameters correct. + * + * Parameters with vector descriptions that are not zero based and + * are used in net contexts should generate the properly ranged + * temporary signals. This causes subsequent part selects to work + * out properly. + */ +assign exp_norm = alap - falap + ih; + +initial +begin + #1 $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr1946411.v b/ivtest/ivltests/pr1946411.v new file mode 100644 index 000000000..14544e323 --- /dev/null +++ b/ivtest/ivltests/pr1946411.v @@ -0,0 +1,14 @@ +// pr1946411 + +module test(); + localparam integer a = 99; + + initial begin + if (a !== 99) begin + $display("FAILED -- a = %d", a); + $finish; + end + $display("PASSED\n"); + end + +endmodule diff --git a/ivtest/ivltests/pr1948110.v b/ivtest/ivltests/pr1948110.v new file mode 100644 index 000000000..e31bae087 --- /dev/null +++ b/ivtest/ivltests/pr1948110.v @@ -0,0 +1,39 @@ +module top; + reg pass = 1'b1; + reg a, b; + real c, d; + + initial begin + c = 0.0; + d = 1.0; + a = 1'b0; + b = 1'b0; + assign c = 6/(2 - d*(b & ~a) + d*(a & ~b)); + + #1; + if (c != 3.0) begin + $display("FAILED, expected 3.0, got %f", c); + pass = 1'b0; + end + + a = 1'b1; + b = 1'b0; + assign c = 6/(2 - d*(b & ~a) + d*(a & ~b)); + #1; + if (c != 2.0) begin + $display("FAILED, expected 2.0, got %f", c); + pass = 1'b0; + end + + a = 1'b0; + b = 1'b1; + assign c = 6/(2 - d*(b & ~a) + d*(a & ~b)); + #1; + if (c != 6.0) begin + $display("FAILED, expected 6.0, got %f", c); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1948342.v b/ivtest/ivltests/pr1948342.v new file mode 100644 index 000000000..f9103f72f --- /dev/null +++ b/ivtest/ivltests/pr1948342.v @@ -0,0 +1,36 @@ +module test; + + wire a; + reg [20:0] b; + + assign a = ((b[20:4]) || (b[3] && b[2:0])) ? 1'b0 : 1'b1; + + initial begin + b = 0; + #1 if (a !== 1'b1) begin + $display("FAILED -- b=%h, a=%b", b, a); + $finish; + end + + b = 8; + #1 if (a !== 1'b1) begin + $display("FAILED -- b=%h, a=%b", b, a); + $finish; + end + + b = 12; + #1 if (a !== 1'b0) begin + $display("FAILED -- b=%h, a=%b", b, a); + $finish; + end + + b = 16; + #1 if (a !== 1'b0) begin + $display("FAILED -- b=%h, a=%b", b, a); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1949025.v b/ivtest/ivltests/pr1949025.v new file mode 100644 index 000000000..094ad8c90 --- /dev/null +++ b/ivtest/ivltests/pr1949025.v @@ -0,0 +1,9 @@ +module main; + reg [2:0] value; + + initial begin + for(value = 0; value <= 6; value = value + 1) begin + $displayh(value,, 1<<(6-value)); + end + end +endmodule diff --git a/ivtest/ivltests/pr1950282.v b/ivtest/ivltests/pr1950282.v new file mode 100644 index 000000000..e8d83d756 --- /dev/null +++ b/ivtest/ivltests/pr1950282.v @@ -0,0 +1,10 @@ +module test; + function integer fn (input integer a, b, input integer c); + fn = ((a > b) ? a : b) + c; + endfunction + + initial begin + if (fn(2, 4, 3) != 7) $display("Failed"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1956211.v b/ivtest/ivltests/pr1956211.v new file mode 100644 index 000000000..848d3d6d0 --- /dev/null +++ b/ivtest/ivltests/pr1956211.v @@ -0,0 +1,39 @@ +module top; + reg clk; + reg pass = 1'b1; + + generate + genvar n; + for (n=0; n<4; n=n+1) begin : loop + reg [n:0] r; + always @(clk) r = n; + end + endgenerate + + initial begin + clk = 0; + #1; + + if (loop[0].r !== 0) begin + $display("Failed generate instance 0"); + pass = 1'b0; + end + + if (loop[1].r !== 1) begin + $display("Failed generate instance 1"); + pass = 1'b0; + end + + if (loop[2].r !== 2) begin + $display("Failed generate instance 2"); + pass = 1'b0; + end + + if (loop[3].r !== 3) begin + $display("Failed generate instance 3"); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1958801.v b/ivtest/ivltests/pr1958801.v new file mode 100644 index 000000000..aa5c408b3 --- /dev/null +++ b/ivtest/ivltests/pr1958801.v @@ -0,0 +1,39 @@ +// pr1958001 + +module s_cmpGe( in00, in01, out00 ); + + parameter bw_in00 = 32; + parameter bw_in01 = 32; + + input signed [bw_in00-1:0] in00; + input signed [bw_in01-1:0] in01; + output out00; + + assign out00 = ( in00 >= in01 ); +endmodule + +module x; + + reg signed [31:0] a; + reg signed b; + wire c; + + s_cmpGe #(32, 1) inst(a, b, c); + + initial + begin + b = 0; + a = -1; + + #1; + + $display("%d >= %d = %d", a, b, c); + if (c !== 0) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr1960545.v b/ivtest/ivltests/pr1960545.v new file mode 100644 index 000000000..8fdde8af8 --- /dev/null +++ b/ivtest/ivltests/pr1960545.v @@ -0,0 +1,12 @@ +module test; + initial + begin: A1 + while(1 != 0) + begin: A2 + reg B; + B = 1; + $display("B is %d", B); + disable A1; + end + end +endmodule diff --git a/ivtest/ivltests/pr1960548.v b/ivtest/ivltests/pr1960548.v new file mode 100644 index 000000000..c4b5f0e65 --- /dev/null +++ b/ivtest/ivltests/pr1960548.v @@ -0,0 +1,6 @@ +// pr1960548 + +module test; + initial + $display("B`x"); +endmodule diff --git a/ivtest/ivltests/pr1960558.v b/ivtest/ivltests/pr1960558.v new file mode 100644 index 000000000..02f266058 --- /dev/null +++ b/ivtest/ivltests/pr1960558.v @@ -0,0 +1,10 @@ +module test; + initial + begin: A1 + reg[1:0] v2; + v2 = 2'b0z; + $write( + "expected 1; got %0b\n", + (($signed(v2) === 1'sbx) || ($signed(v2 + 1'b1) === 1'sbx))); + end +endmodule diff --git a/ivtest/ivltests/pr1960575.v b/ivtest/ivltests/pr1960575.v new file mode 100644 index 000000000..7f8b8d83a --- /dev/null +++ b/ivtest/ivltests/pr1960575.v @@ -0,0 +1,4 @@ +module test; + initial + $write("expected x; got %0b\n", 1'b0 ^ 1'bz); +endmodule diff --git a/ivtest/ivltests/pr1960596.v b/ivtest/ivltests/pr1960596.v new file mode 100644 index 000000000..f2fa5b2c2 --- /dev/null +++ b/ivtest/ivltests/pr1960596.v @@ -0,0 +1,6 @@ +module test; + initial begin + $write("expected 32'h55555552; got 32'h%0h\n", (-(32'h9) / 32'h3)); + $write("expected 1; got %0d\n", (-(32'h9) % 32'h3)); + end +endmodule diff --git a/ivtest/ivltests/pr1960619.v b/ivtest/ivltests/pr1960619.v new file mode 100644 index 000000000..85e7490d7 --- /dev/null +++ b/ivtest/ivltests/pr1960619.v @@ -0,0 +1,59 @@ +module test; + initial begin: A + reg [4:0] a; + reg [31:0] b, c, d; + a = 5'h14; + b = $signed(a); + c = {_$Finv5(_$Fsub8(_$Fadd8((32'haa ^ (32'hcc & _$Fsll32(_$Fsrl32(_$Fsll32(32'h78, 32'h2), 32'h3), 32'h1))), 32'h69), (32'h50 * 32'h2)))}; + d = $signed(_$Finv5(_$Fsub8(_$Fadd8((32'haa ^ (32'hcc & _$Fsll32(_$Fsrl32(_$Fsll32(32'h78, 32'h2), 32'h3), 32'h1))), 32'h69), (32'h50 * 32'h2)))); + $write("a is %0h; b is %0h; c is %0h; d is %0h\n", a, b, c, d); + end + + function [4:0] _$Finv5; + input l; + reg [4:0] l; + _$Finv5 = ~l; + endfunction + + function [7:0] _$Fsub8; + input l,r; + reg [7:0] l,r; + _$Fsub8 = l-r; + endfunction + + function [7:0] _$Fadd8; + input l,r; + reg [7:0] l,r; + _$Fadd8 = l+r; + endfunction + + function [31:0] _$Fsll32; + input l,r; + reg [31:0] l; + integer r; + begin + if(r < 0) begin + if(r + 32 <= 0) _$Fsll32 = 32'b0; + else _$Fsll32 = l >> -r; + end else if(r > 0) begin + if(r >= 32) _$Fsll32 = 32'b0; + else _$Fsll32 = l << r; + end else _$Fsll32 = l; + end + endfunction + + function [31:0] _$Fsrl32; + input l,r; + reg [31:0] l; + integer r; + begin + if(r < 0) begin + if(r + 32 <= 0) _$Fsrl32 = 32'b0; + else _$Fsrl32 = l << -r; + end else if(r > 0) begin + if(r >= 32) _$Fsrl32 = 32'b0; + else _$Fsrl32 = l >> r; + end else _$Fsrl32 = l; + end + endfunction +endmodule diff --git a/ivtest/ivltests/pr1960625.v b/ivtest/ivltests/pr1960625.v new file mode 100644 index 000000000..8eab4b6bc --- /dev/null +++ b/ivtest/ivltests/pr1960625.v @@ -0,0 +1,37 @@ +module top; + reg pass = 1'b1; + + generate + genvar n; + for (n=0; n<4; n=n+1) begin : loop + reg [2:0] r = n; // This fails. +// wire [2:0] r = n; // This works. + end + endgenerate + + initial begin + #1; + + if (loop[0].r !== 0) begin + $display("Failed generate instance 0"); + pass = 1'b0; + end + + if (loop[1].r !== 1) begin + $display("Failed generate instance 1"); + pass = 1'b0; + end + + if (loop[2].r !== 2) begin + $display("Failed generate instance 2"); + pass = 1'b0; + end + + if (loop[3].r !== 3) begin + $display("Failed generate instance 3"); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1960633.v b/ivtest/ivltests/pr1960633.v new file mode 100644 index 000000000..d07d2089e --- /dev/null +++ b/ivtest/ivltests/pr1960633.v @@ -0,0 +1,37 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module main; + + reg [7:0] foo; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + wire [3:0] below = foo[2:-1]; + wire [3:0] above = foo[8:5]; + wire [9:0] span = foo[8:-1]; +`else + wire [3:0] below = {foo[2:0], 1'bx}; + wire [3:0] above = {1'bx, foo[7:5]}; + wire [9:0] span = {1'bx, foo[7:0], 1'bx}; +`endif + + initial begin + foo = 'h55; + #1 ; + if (below !== 4'b101_x) begin + $display("FAILED"); + $finish; + end + if (above !== 4'bx_010) begin + $display("FAILED"); + $finish; + end + if (span !== 10'bx_01010101_x) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/pr1963240.v b/ivtest/ivltests/pr1963240.v new file mode 100644 index 000000000..c834b2f36 --- /dev/null +++ b/ivtest/ivltests/pr1963240.v @@ -0,0 +1,14 @@ +module test; + reg [7:0] i8, j8; + reg [31:0] i32; + initial begin + i8 = 32'hf7; + j8 = 32'h3; + i32 = $signed(i8 / j8); + $write("expected %0h; got %0h\n", 8'h52, i32); + i8 = 32'hf7; + j8 = 32'h1; + i32 = $signed(i8 / j8); + $write("expected %0h; got %0h\n", 32'hffffff_f7, i32); + end +endmodule diff --git a/ivtest/ivltests/pr1963960.v b/ivtest/ivltests/pr1963960.v new file mode 100644 index 000000000..fc9757f47 --- /dev/null +++ b/ivtest/ivltests/pr1963960.v @@ -0,0 +1,60 @@ +module top; + integer chr, fd, code; + reg [14*8:1] str; + + initial begin + // Put a string into the file. + fd = $fopen("work/test.txt", "w"); + if (fd == 0) begin + $display("Failed to open test file for writing!"); + $finish; + end + $fdisplay(fd, "Hello World!"); + $fclose(fd); + + // Now read it back and verify that $ungetc() and other things work. + fd = $fopen("work/test.txt", "r"); + if (fd == 0) begin + $display("Failed to open test file for reading!"); + $finish; + end + + chr = $fgetc(fd); + if (chr != "H") begin + $display("Failed first character read!"); + $finish; + end + + code = $ungetc(chr, fd); + if (code == -1) begin + $display("Failed to ungetc() character!"); + $finish; + end + + chr = $fgetc(fd); + if (chr != "H") begin + $display("Failed first character reread!"); + $finish; + end + + code = $ungetc(chr, fd); + if (code == -1) begin + $display("Failed to ungetc() character (2)!"); + $finish; + end + + code = $fgets(str, fd); + if (code == 0) begin + $display("Failed to read characters!"); + $finish; + end + if (str[13*8:9] != "Hello World!") begin + $display("Read wrong characters!"); + $finish; + end + + $fclose(fd); + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1963962.v b/ivtest/ivltests/pr1963962.v new file mode 100644 index 000000000..bf751ce39 --- /dev/null +++ b/ivtest/ivltests/pr1963962.v @@ -0,0 +1,9 @@ +module top; + reg [256*8:1] name; + + initial begin + name = "work/dumptest"; + $dumpfile({name, ".vcd"}); + $dumpvars; + end +endmodule diff --git a/ivtest/ivltests/pr1971662a.v b/ivtest/ivltests/pr1971662a.v new file mode 100644 index 000000000..40eeb2be3 --- /dev/null +++ b/ivtest/ivltests/pr1971662a.v @@ -0,0 +1,10 @@ +module top; + parameter rep = 4'bx; + + reg [31:0] a; + + initial begin + a = {rep{8'hab}}; // This should be a compilation error! + $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/pr1971662b.v b/ivtest/ivltests/pr1971662b.v new file mode 100644 index 000000000..3aedf4f77 --- /dev/null +++ b/ivtest/ivltests/pr1971662b.v @@ -0,0 +1,7 @@ +module top; + parameter rep = 4'bx; + + wire [31:0] b = {rep{8'hab}}; // This should be a compilation error. + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/pr1978358.v b/ivtest/ivltests/pr1978358.v new file mode 100644 index 000000000..e9453fa03 --- /dev/null +++ b/ivtest/ivltests/pr1978358.v @@ -0,0 +1,39 @@ +`begin_keywords "1364-2005" + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass = 1'b1; + reg [3:0] var = 4'b1001; +// wire [3:0] var = 4'b1001; +// parameter [3:0] var = 4'b1001; + reg [3:0] part; + reg [5:0] big; + + initial begin +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = var[1:-2]; // should be 01xx. + if (part !== 4'b01xx) begin + $display("part select [1:-2] failed, expected 4'b01xx, got %b", part); + pass = 1'b0; + end + + part = var[5:2]; // should be xx10. + if (part !== 4'bxx10) begin + $display("part select [5:2] failed, expected 4'bxx10, got %b", part); + pass = 1'b0; + end + + big = var[4:-1]; // should be x10100101x. + if (big !== 6'bx1001x) begin + $display("part select [4:-1] failed, expected 6'bx1001x, got %b", big); + pass = 1'b0; + end +`endif + + if (pass) $display("PASSED"); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr1978358b.v b/ivtest/ivltests/pr1978358b.v new file mode 100644 index 000000000..a570e04e3 --- /dev/null +++ b/ivtest/ivltests/pr1978358b.v @@ -0,0 +1,39 @@ +`begin_keywords "1364-2005" + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass = 1'b1; +// reg [3:0] var = 4'b1001; + wire [3:0] var = 4'b1001; +// parameter [3:0] var = 4'b1001; + reg [3:0] part; + reg [5:0] big; + + initial begin +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = var[1:-2]; // should be 01xx. + if (part !== 4'b01xx) begin + $display("part select [1:-2] failed, expected 4'b01xx, got %b", part); + pass = 1'b0; + end + + part = var[5:2]; // should be xx10. + if (part !== 4'bxx10) begin + $display("part select [5:2] failed, expected 4'bxx10, got %b", part); + pass = 1'b0; + end + + big = var[4:-1]; // should be x10100101x. + if (big !== 6'bx1001x) begin + $display("part select [4:-1] failed, expected 6'bx1001x, got %b", big); + pass = 1'b0; + end +`endif + + if (pass) $display("PASSED"); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr1978358c.v b/ivtest/ivltests/pr1978358c.v new file mode 100644 index 000000000..5a5ec7527 --- /dev/null +++ b/ivtest/ivltests/pr1978358c.v @@ -0,0 +1,39 @@ +`begin_keywords "1364-2005" + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass = 1'b1; +// reg [3:0] var = 4'b1001; +// wire [3:0] var = 4'b1001; + parameter [3:0] var = 4'b1001; + reg [3:0] part; + reg [5:0] big; + + initial begin +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = var[1:-2]; // should be 01xx. + if (part !== 4'b01xx) begin + $display("part select [1:-2] failed, expected 4'b01xx, got %b", part); + pass = 1'b0; + end + + part = var[5:2]; // should be xx10. + if (part !== 4'bxx10) begin + $display("part select [5:2] failed, expected 4'bxx10, got %b", part); + pass = 1'b0; + end + + big = var[4:-1]; // should be x10100101x. + if (big !== 6'bx1001x) begin + $display("part select [4:-1] failed, expected 6'bx1001x, got %b", big); + pass = 1'b0; + end +`endif + + if (pass) $display("PASSED"); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr1978358d.v b/ivtest/ivltests/pr1978358d.v new file mode 100644 index 000000000..a8f78861f --- /dev/null +++ b/ivtest/ivltests/pr1978358d.v @@ -0,0 +1,39 @@ +`begin_keywords "1364-2005" + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass = 1'b1; +// reg [3:0] var = 4'b1001; +// wire [3:0] var = 4'b1001; + parameter [3:0] var = 4'b1001; + reg [3:0] part; + reg [5:0] big; + + initial begin +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = var[-2 +: 4]; // should be 01xx. + if (part !== 4'b01xx) begin + $display("part select [1:-2] failed, expected 4'b01xx, got %b", part); + pass = 1'b0; + end + + part = var[2 +: 4]; // should be xx10. + if (part !== 4'bxx10) begin + $display("part select [5:2] failed, expected 4'bxx10, got %b", part); + pass = 1'b0; + end + + big = var[-1 +: 6]; // should be x10100101x. + if (big !== 6'bx1001x) begin + $display("part select [4:-1] failed, expected 6'bx1001x, got %b", big); + pass = 1'b0; + end +`endif + + if (pass) $display("PASSED"); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr1983762.v b/ivtest/ivltests/pr1983762.v new file mode 100644 index 000000000..2655dc5b2 --- /dev/null +++ b/ivtest/ivltests/pr1983762.v @@ -0,0 +1,29 @@ +module main; + + reg clk; + + localparam integer TEST = 100; + print #("PASSED", TEST) foo (clk); + + initial begin + clk = 0; + #1 clk = 1; + #1 $finish; + end + +endmodule // main + +module print (input wire clk); + + parameter message = ""; + parameter number = 0; + + always @(posedge clk) begin + if (number !== 100) begin + $display("FAILED -- number=%d\n", number); + $finish; + end + $display("%s", message); + end + +endmodule // print diff --git a/ivtest/ivltests/pr1985582.v b/ivtest/ivltests/pr1985582.v new file mode 100644 index 000000000..2b9489550 --- /dev/null +++ b/ivtest/ivltests/pr1985582.v @@ -0,0 +1,23 @@ +`timescale 1ns/1ps + +module top; + realtime rtime; + time itime; + + initial begin + repeat (5) begin + rtime = $realtime; + itime = $time; + $display("%4t %.2f %2d, %4t %0.2f %2d, %4t %.2f, %4t %0.2f, %4t %.2f,", + $time, $time, $time, itime, itime, itime, + $realtime, $realtime, rtime, rtime, rtm($realtime), + rtm($realtime),, $time,, $realtime); + #0.6; + end + end + + function real rtm; + input real rin; + rtm = rin; + endfunction +endmodule diff --git a/ivtest/ivltests/pr1985582_std.v b/ivtest/ivltests/pr1985582_std.v new file mode 100644 index 000000000..5ceed92a1 --- /dev/null +++ b/ivtest/ivltests/pr1985582_std.v @@ -0,0 +1,23 @@ +`timescale 1ns/1ps + +module top; + realtime rtime; + time itime; + + initial begin + repeat (5) begin + rtime = $realtime; + itime = $time; + $display("%t %.2f %2d, %t %0.2f %2d, %t %.2f, %t %0.2f, %t %.2f,", + $time, $time, $time, itime, itime, itime, + $realtime, $realtime, rtime, rtime, rtm($realtime), + rtm($realtime),, $time,, $realtime); + #0.6; + end + end + + function real rtm; + input real rin; + rtm = rin; + endfunction +endmodule diff --git a/ivtest/ivltests/pr1988302.v b/ivtest/ivltests/pr1988302.v new file mode 100644 index 000000000..0fe0fe050 --- /dev/null +++ b/ivtest/ivltests/pr1988302.v @@ -0,0 +1,39 @@ +module main; + + generate + genvar i; + for( i=0; i<4; i=i+2 ) + begin : U + reg [1:0] a; + initial begin : V + a = 2'b0; + #10; + a = i; + end + end + endgenerate + + initial begin + #5 ; + if (U[0].a !== 2'd0) begin + $display("FAILED -- U[0].a = %d", U[0].a); + $finish; + end + if (U[2].a !== 2'd0) begin + $display("FAILED -- U[2].a = %d", U[2].a); + $finish; + end + #10 ; + if (U[0].a !== 2'd0) begin + $display("FAILED -- U[0].a = %d", U[0].a); + $finish; + end + if (U[2].a !== 2'd2) begin + $display("FAILED -- U[2].a = %d", U[2].a); + $finish; + end + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/pr1988302b.v b/ivtest/ivltests/pr1988302b.v new file mode 100644 index 000000000..fc65a04c0 --- /dev/null +++ b/ivtest/ivltests/pr1988302b.v @@ -0,0 +1,39 @@ +module main; + + generate + genvar i; + for( i=0; i<4; i=i+2 ) + begin : U + reg [1:0] a; + initial begin : V + a = 2'b0; + #10; + a = i; + end + end + endgenerate + + initial begin + #5 ; + if (U[0].V.a !== 2'd0) begin + $display("FAILED -- U[0].V.a = %d", U[0].V.a); + $finish; + end + if (U[2].V.a !== 2'd0) begin + $display("FAILED -- U[2].V.a = %d", U[2].V.a); + $finish; + end + #10 ; + if (U[0].V.a !== 2'd0) begin + $display("FAILED -- U[0].V.a = %d", U[0].V.a); + $finish; + end + if (U[2].V.a !== 2'd2) begin + $display("FAILED -- U[2].V.a = %d", U[2].V.a); + $finish; + end + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/pr1988310.v b/ivtest/ivltests/pr1988310.v new file mode 100644 index 000000000..90efa96b1 --- /dev/null +++ b/ivtest/ivltests/pr1988310.v @@ -0,0 +1,46 @@ +module top; + localparam A = 0; + reg pass = 1'b1; + + generate + if (A < 1) begin: gen + task foo_task; + reg x; + begin + x = 1'b0; + #10; + x = 1'b1; + end + endtask + end else begin: gen + task foo_task; + reg x; + begin + x = 1'b1; + #10; + x = 1'b0; + end + endtask + end + endgenerate + + initial begin + gen.foo_task; + end + + initial begin + #9 + if (gen.foo_task.x !== 1'b0) begin + $display("Failed: expected 1'b0, got %b", gen.foo_task.x); + pass = 1'b0; + end + + #2 + if (gen.foo_task.x !== 1'b1) begin + $display("Failed: expected 1'b1, got %b", gen.foo_task.x); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1990029.v b/ivtest/ivltests/pr1990029.v new file mode 100644 index 000000000..6560cf1ed --- /dev/null +++ b/ivtest/ivltests/pr1990029.v @@ -0,0 +1,41 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top(); + reg pass = 1'b1; + integer fp, i, n; + reg [8:0] v; +`ifndef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + reg [11:-4] w; +`endif + + initial begin + fp = $fopen("work/temp.txt", "w"); + for (i = 0; i < 4; i = i + 1) begin + $fdisplay(fp, "%d", i + 16'he020); + end + $fclose(fp); + + fp = $fopen("work/temp.txt", "r"); + for (i = 0; i < 4; i = i + 1) begin + v = 9'd0; + // Use the following line and change the base in the a.out file + // to -4 and the width to 16 to get correct functionality. + //n = $fscanf(fp, " %d ", v[7:0]); // This uses the &PV<> +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + n = $fscanf(fp, " %d ", v[11:-4]); // This does not use &PV<> (bug) +`else + n = $fscanf(fp, " %d ", w); + v = w[8:0]; +`endif + if (v != 2) begin + $display("FAILED: iteration %d, got %b, expected 9'b000000010", i, v); + pass = 1'b0; + end + end + $fclose(fp); + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1990164.v b/ivtest/ivltests/pr1990164.v new file mode 100644 index 000000000..2fc08abb3 --- /dev/null +++ b/ivtest/ivltests/pr1990164.v @@ -0,0 +1,11 @@ +module top; + reg signed [7:0] test = -1; + integer result; + + initial begin + result = test[7:0]; // A part select is always unsigned (1364-2001 4.5.1)! + if (result != 32'h0ff) begin + $display("FAILED part selects are unsigned, got %h, expected 32'h0ff", result); + end else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1990269.v b/ivtest/ivltests/pr1990269.v new file mode 100644 index 000000000..732421777 --- /dev/null +++ b/ivtest/ivltests/pr1990269.v @@ -0,0 +1,32 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass = 1'b1; + reg [7:0] val; + + initial begin +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + val[3:-4] = 8'h6f; +`else + val[3:0] = 4'h6; +`endif + if (val !== 8'hx6) begin + $display("FAILED underflow, got %h, expected 8'hx6", val); + pass = 1'b0; + end + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + val[11:4] = 8'hfe; +`else + val[7:4] = 4'he; +`endif + if (val !== 8'he6) begin + $display("FAILED overflow, got %h, expected 8'he6", val); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr1992244.v b/ivtest/ivltests/pr1992244.v new file mode 100644 index 000000000..e3da472b1 --- /dev/null +++ b/ivtest/ivltests/pr1992244.v @@ -0,0 +1,10 @@ +module top; + wire [15:0] number =16'h20; + wire shift_cmp = (number == (1 << 5)); + + initial begin + #1; // Make sure things are settled. + if (shift_cmp === 1'b1) $display("PASSED"); + else $display("FAILED, got %b expected 1'b1", shift_cmp); + end +endmodule diff --git a/ivtest/ivltests/pr1992729.v b/ivtest/ivltests/pr1992729.v new file mode 100644 index 000000000..50e7eb866 --- /dev/null +++ b/ivtest/ivltests/pr1992729.v @@ -0,0 +1,32 @@ +module main; + + function integer my_ceil; + input number; + real number; + if (number > $rtoi(number)) + my_ceil = $rtoi(number) + 1; + else + my_ceil = number; + endfunction + + real tck; + parameter CL_TIME = 13125; + wire [31:0] result1 = my_ceil( CL_TIME/tck ); + integer result2; + initial begin + tck = 2.0; + + result2 = my_ceil( CL_TIME/tck ); + if (result2 !== 6563) begin + $display("FAILED -- result2=%d", result2); + $finish; + end + + #1 if (result1 !== 6563) begin + $display("FAILED -- result1=%d", result1); + $finish; + end + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/pr1993479.v b/ivtest/ivltests/pr1993479.v new file mode 100644 index 000000000..5de3a783f --- /dev/null +++ b/ivtest/ivltests/pr1993479.v @@ -0,0 +1,21 @@ +/* + * The base vpi_get() is not returning the correct result for + * a signed value. There are obviously other problems as well. + */ +module top; + reg [7:0] rval; + reg signed [7:0] base; // This fails (no sign extension?). +// reg signed [31:0] base; // This works on a 32 bit machine. +// integer base; // And this works + + initial begin + rval = 8'b10100101; + for (base = 0; base > -8; base = base -1) begin + $displayb("%3d %b ", base, rval[base +: 8], rval[base +: 8]); + end + $display; + for (base = 0; base > -8; base = base -1) begin + $displayb("%3d %b ", base+1, rval[base+1 +: 8], rval[base+1 +: 8]); + end + end +endmodule diff --git a/ivtest/ivltests/pr2001162.v b/ivtest/ivltests/pr2001162.v new file mode 100644 index 000000000..ecf770e44 --- /dev/null +++ b/ivtest/ivltests/pr2001162.v @@ -0,0 +1,59 @@ +`define PERIOD 10 + +module main; + reg CLK; + integer counter; + + initial begin // reset and clock generator + counter = 0; + CLK = 0; + #2; // wait 2, and then... + repeat(10) // generate 5 clock cycles + #(`PERIOD/2) CLK = !CLK; + $display("time %0t; the counter is %0d", $time, counter); + $finish(0); + end + + task test1; + begin + @(posedge CLK); + $display("test1 increment; reading counter as %0d", counter); + // the function call is necessary to get the problem + counter = _$Fadd32(counter, 1'b1); + end + endtask + + task test2; + begin + @(posedge CLK); + $display("test2 increment; reading counter as %0d", counter); + counter = _$Fadd32(counter, 1'b1); + end + endtask + + function [31:0] _$Fadd32; + input l,r; + reg [31:0] l,r; + _$Fadd32 = l+r; + endfunction +endmodule // main + +module trig1; + always begin + #`PERIOD; + top.main.test1; + end +endmodule + +module trig2; + always begin + #`PERIOD; + top.main.test2; + end +endmodule + +module top; + main main(); + trig1 trig1(); + trig2 trig2(); +endmodule diff --git a/ivtest/ivltests/pr2002443.v b/ivtest/ivltests/pr2002443.v new file mode 100644 index 000000000..d9cc08019 --- /dev/null +++ b/ivtest/ivltests/pr2002443.v @@ -0,0 +1,7 @@ +`define MACRO(_param_,_def_) \ +`ifdef _def_ \ +module _param_ (); \ +endmodule \ +`endif + +`MACRO(FOFO, CFG_FOFO) diff --git a/ivtest/ivltests/pr2011429.v b/ivtest/ivltests/pr2011429.v new file mode 100644 index 000000000..ef2de3adf --- /dev/null +++ b/ivtest/ivltests/pr2011429.v @@ -0,0 +1,38 @@ +`timescale 1 ps/1 ps + +// extracted from altera_mf.v +module bug2011429; + reg pass = 1'b1; + reg [7:0] vco_tap; + reg vco_c0_last_value; + integer c_ph_val[0:5]; + + always @(vco_tap[c_ph_val[0]]) + vco_c0_last_value = vco_tap[c_ph_val[0]]; + + initial begin + vco_tap = 8'b10101010; + c_ph_val[0] = 0; + #1; + if (vco_c0_last_value != 1'b0) begin + $display("FAILED initial value, got %b", vco_c0_last_value); + pass = 1'b0; + end + + vco_tap = vco_tap >> 1; + #1; + if (vco_c0_last_value != 1'b1) begin + $display("FAILED shifted value, got %b", vco_c0_last_value); + pass = 1'b0; + end + + c_ph_val[0] = 1; + #1; + if (vco_c0_last_value != 1'b0) begin + $display("FAILED index change, got %b", vco_c0_last_value); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2013758.v b/ivtest/ivltests/pr2013758.v new file mode 100644 index 000000000..a7489505c --- /dev/null +++ b/ivtest/ivltests/pr2013758.v @@ -0,0 +1,36 @@ +// pr2013758 + +module test; + + reg reset; + initial begin +// $dumpfile( "test.vcd" ); +// $dumpvars; + + reset = 0; + #100; + reset = 1; + #100; + reset = 0; + #100 $display("PASSED"); + $finish; + end + + submod1 s1 (.reset(reset)); + submod2 s2 (.reset(reset)); + +endmodule + +module submod1(input reset); + wire reset2 = 1; + assign reset2 = reset; +endmodule + +module submod2(input reset); + + always #10 @(reset) + if (reset === 1'bx) begin + $display("FAILED -- X escaped into sibling module!"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/pr2014673.v b/ivtest/ivltests/pr2014673.v new file mode 100644 index 000000000..be196658c --- /dev/null +++ b/ivtest/ivltests/pr2014673.v @@ -0,0 +1,18 @@ +// I ran this with "iverilog -y. bugreport.v -s bugreport && ./a.out" +// on Icarus Verilog version 0.9.devel (s20080429) +// and got "Bug observed: Got xxxxx, expected 0004b." +// (some code taken from async_transmitter.v at http://www.fpga4fun.com) +module bugreport; + + parameter ClkFrequency = 50000000; + parameter Baud = 57600; + parameter BaudGeneratorAccWidth = 16; + wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4); + wire [BaudGeneratorAccWidth:0] BaudGeneratorIncShouldBe = 17'h4b; + + initial #1 if (BaudGeneratorInc !== BaudGeneratorIncShouldBe) + $display("FAILED -- Got %x, expected %x.",BaudGeneratorInc,BaudGeneratorIncShouldBe); + else + $display("PASSED"); + +endmodule // bugreport diff --git a/ivtest/ivltests/pr2015466.v b/ivtest/ivltests/pr2015466.v new file mode 100644 index 000000000..b2a59277e --- /dev/null +++ b/ivtest/ivltests/pr2015466.v @@ -0,0 +1,36 @@ +// Copyright 2008, Martin Whitaker +// This file may be freely copied for any purpose. No attribution required. + +module prXXX(); + +reg [3:0] value1; +wire [1:0] value2; + +assign value2 = (value1 == 0) ? 0 : (value1 == 1) ? 1 : 2; + + initial begin + value1 = 0; + #1 if (value2 !== 0) begin + $display("FAILED -- value1=%b, value2=%b", value1, value2); + $finish; + end + value1 = 1; + #1 if (value2 !== 1) begin + $display("FAILED -- value1=%b, value2=%b", value1, value2); + $finish; + end + value1 = 2; + #1 if (value2 !== 2) begin + $display("FAILED -- value1=%b, value2=%b", value1, value2); + $finish; + end + value1 = 3; + #1 if (value2 !== 2) begin + $display("FAILED -- value1=%b, value2=%b", value1, value2); + $finish; + end + $display("PASSED"); + $finish; + end // initial begin + +endmodule diff --git a/ivtest/ivltests/pr2018235a.v b/ivtest/ivltests/pr2018235a.v new file mode 100644 index 000000000..bcbaa1dd2 --- /dev/null +++ b/ivtest/ivltests/pr2018235a.v @@ -0,0 +1,34 @@ +module test(); + parameter N_CH = 1; + + reg pass = 1'b1; + reg clk; + reg [31:0] data[0: N_CH-1]; + + generate + genvar i; + for (i=0; iStart; + #1 $display("%d %d", Value1, Value2); +end + +endmodule diff --git a/ivtest/ivltests/pr2076363.v b/ivtest/ivltests/pr2076363.v new file mode 100644 index 000000000..176a62daf --- /dev/null +++ b/ivtest/ivltests/pr2076363.v @@ -0,0 +1,24 @@ +module top; + reg [10*8-1:0] str [2:0]; + reg [31:0] idx [2:0]; + reg [4*8-1:0] pvstr, pvstr2; + reg [15:0] pvidx, pvidx2, pvbase; + + initial begin + pvstr = "S"; + pvstr2 = "SF"; + pvidx = 'd2; + pvidx2 = 'd8; + pvbase = 'd0; + str[0] = "FAIL"; + str[1] = "PA"; + str[2] = "ED"; + idx[0] = 0; + idx[1] = 1; + idx[2] = 2; + $write("%0s", str[idx[1]]); // This prints PA or FAIL. + $write("%0s", pvstr[idx[0] +: 16]); // This adds an S. + $write("%0s", pvstr2[pvidx2[pvbase +: 4] +: 8]); // This adds another S. + $display("%0s", str[pvidx[pvbase +: 8]]); // This adds the ED. + end +endmodule diff --git a/ivtest/ivltests/pr2076391.v b/ivtest/ivltests/pr2076391.v new file mode 100644 index 000000000..67b78414d --- /dev/null +++ b/ivtest/ivltests/pr2076391.v @@ -0,0 +1,17 @@ +module top; + reg [40*8-1:0] result; + integer iindex [1:0]; + reg signed [15:0] rindex [1:0]; + wire signed [15:0] windex [1:0]; + + assign windex[0] = -1; + + initial begin + iindex[0] = -1; + rindex[0] = -1; + #1; + $display("iindex[0] = %0d", iindex[0]); + $display("rindex[0] = %0d", rindex[0]); + $display("windex[0] = %0d", windex[0]); + end +endmodule diff --git a/ivtest/ivltests/pr2076425.v b/ivtest/ivltests/pr2076425.v new file mode 100644 index 000000000..d239359ed --- /dev/null +++ b/ivtest/ivltests/pr2076425.v @@ -0,0 +1,21 @@ +module top; + + task delay; + z.delay; + endtask + + always begin + delay; + end + + initial begin + #10 $display("PASSED"); + $finish; + end +endmodule + +module z; + task delay; + #1; + endtask +endmodule diff --git a/ivtest/ivltests/pr2085984.v b/ivtest/ivltests/pr2085984.v new file mode 100644 index 000000000..954bafd91 --- /dev/null +++ b/ivtest/ivltests/pr2085984.v @@ -0,0 +1,16 @@ +module top; + reg [1:0] a[3:0]; + reg [2:0] b[7:0], c[2:0]; + + integer i; + + always @(b[c[0]]) a[2] <= b[c[0]]; + + initial begin + for (i=0; i<8; i=i+1) b[i] = i; + c[0] = 3'b001; + #1; + if (a[2] != 2'b01) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2091455.v b/ivtest/ivltests/pr2091455.v new file mode 100644 index 000000000..383220a4f --- /dev/null +++ b/ivtest/ivltests/pr2091455.v @@ -0,0 +1,21 @@ +/* + * Based on Request id 2091455 in the iverilog Bugs database +*/ +module main; + + parameter foo = 2; + + generate + case (foo) + 0: initial #1 $display("I am in %m, case foo=%0d", foo); + 1: initial #1 $display("I am in %m, case foo=%0d", foo); + 2: initial #1 $display("I am in %m, case foo=%0d", foo); + endcase // case (foo) + case (foo) + 0: begin : X initial $display("I am in %m, case foo=%0d", foo); end + 1: begin : X initial $display("I am in %m, case foo=%0d", foo); end + 2: begin : X initial $display("I am in %m, case foo=%0d", foo); end + endcase // case (foo) + endgenerate + +endmodule // bug diff --git a/ivtest/ivltests/pr2109179.v b/ivtest/ivltests/pr2109179.v new file mode 100644 index 000000000..1980216ff --- /dev/null +++ b/ivtest/ivltests/pr2109179.v @@ -0,0 +1,30 @@ +module t(); + +reg [1:0] f; +reg [1:0] oszok; +wire [2:0] vosz1; + +genvar i; + +generate + for(i = 0; i < 4; i = i + 1) begin : reg_tomb_gen + wire [2:0] vosz1; + assign vosz1 = i - f + oszok + 1; + initial begin + #1; + if(!i && vosz1 !== 0) begin + $display("FAIL -- i=%b, f=%b, oszok=%b, vosz1=%b", + i, f, oszok, vosz1); + $finish; + end + end + end +endgenerate + +initial +begin + f = 3; + oszok = 2; + #2 $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/pr2117473.v b/ivtest/ivltests/pr2117473.v new file mode 100644 index 000000000..0c7dd38cf --- /dev/null +++ b/ivtest/ivltests/pr2117473.v @@ -0,0 +1,24 @@ +// Copyright 2008, Martin Whitaker. +// This file may be freely copied for any purpose. + +module multiply(); + +reg signed [31:0] A; +reg signed [31:0] B; + +wire signed [63:0] Y; + +assign Y = A * B; + +initial begin + A = -1; + B = -1; + #1 $display("(%0d)*(%0d) = %0d", A, B, Y); + if (Y !== 64'd1) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2117488.v b/ivtest/ivltests/pr2117488.v new file mode 100644 index 000000000..c04de61dd --- /dev/null +++ b/ivtest/ivltests/pr2117488.v @@ -0,0 +1,28 @@ +// Copyright 2008, Martin Whitaker. +// This file may be freely copied for any purpose. + +module ternary_add(); + +reg Enable; + +reg [7:0] A; +reg [7:0] B; +reg C; +wire [8:0] Y; + +assign Y = Enable ? A + B + C : 0; + +initial begin + Enable = 1'b1; + A = 8'd1; + B = 8'd254; + C = 1'd1; + #1 $display("%0d + %0d + %0d = %0d", A, B, C, Y); + if (Y !== 9'd256) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2119622.v b/ivtest/ivltests/pr2119622.v new file mode 100644 index 000000000..3c8562b85 --- /dev/null +++ b/ivtest/ivltests/pr2119622.v @@ -0,0 +1,16 @@ +// Copyright 2008, Martin Whitaker +// This file may be freely copied for any purpose + +module shift(); + +reg [5:0] S; +wire [63:0] Y; + +assign Y = 1 << S; + +initial begin + S = 32; + #1 $display("1 << %0d = %b", S, Y); +end + +endmodule diff --git a/ivtest/ivltests/pr2121536.v b/ivtest/ivltests/pr2121536.v new file mode 100644 index 000000000..ed9d00a4f --- /dev/null +++ b/ivtest/ivltests/pr2121536.v @@ -0,0 +1,53 @@ +module top(); + reg pass = 1'b1; + reg [31:0] in = 'bx; + reg signed [31:0] sin = 'bx; + wire [63:0] res; + wire signed [63:0] sres; + + lower lwr(res, in); + slower slwr(sres, sin); + + initial begin + #1; + if (res !== {32'b0, 32'bx}) begin + $display("FAILED: unsigned output (%b)", res); + pass = 1'b0; + end + + if (lwr.lout !== {32'b0, 32'bx}) begin + $display("FAILED: unsigned input (%b)", lwr.lout); + pass = 1'b0; + end + + if (sres !== 64'bx) begin + $display("FAILED: signed output (%b)", sres); + pass = 1'b0; + end + + if (slwr.lout !== 64'bx) begin + $display("FAILED: signed input (%b)", slwr.lout); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule + +module lower(lrtn, lin); + output [31:0] lrtn; + input [63:0] lin; + + wire [63:0] lout = lin; + + assign lrtn = lout[31:0]; +endmodule + +module slower(lrtn, lin); + output signed [31:0] lrtn; + input signed[63:0] lin; + + wire signed [63:0] lout = lin; + + assign lrtn = lout[31:0]; +endmodule diff --git a/ivtest/ivltests/pr2121536b.v b/ivtest/ivltests/pr2121536b.v new file mode 100644 index 000000000..a1023f17f --- /dev/null +++ b/ivtest/ivltests/pr2121536b.v @@ -0,0 +1,52 @@ +module top(); + reg pass = 1'b1; + reg [31:0] in = 'bx; + reg signed [31:0] sin = 'bx; + wire [63:0] res, sres; + + lower lwr(res, in); + slower slwr(sres, sin); + + initial begin + #1; + if (res !== {32'b0, 32'bx}) begin + $display("FAILED: unsigned output (%b)", res); + pass = 1'b0; + end + + if (lwr.lout !== {32'b0, 32'bx}) begin + $display("FAILED: unsigned input (%b)", lwr.lout); + pass = 1'b0; + end + + if (sres !== 64'bx) begin + $display("FAILED: signed output (%b)", sres); + pass = 1'b0; + end + + if (slwr.lout !== 64'bx) begin + $display("FAILED: signed input (%b)", slwr.lout); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule + +module lower(lrtn, lin); + output [31:0] lrtn; + input [63:0] lin; + + wire [63:0] lout = lin; + + assign lrtn = lout[31:0]; +endmodule + +module slower(lrtn, lin); + output signed [31:0] lrtn; + input [63:0] lin; + + wire [63:0] lout = lin; + + assign lrtn = lout[31:0]; +endmodule diff --git a/ivtest/ivltests/pr2123158.v b/ivtest/ivltests/pr2123158.v new file mode 100644 index 000000000..673b8bd19 --- /dev/null +++ b/ivtest/ivltests/pr2123158.v @@ -0,0 +1,22 @@ +module top; + reg pass = 1'b1; + wire real rval; + real in; + + assign rval = in + 2; + + initial begin + // $monitor(rval,, in); + in = 0; + #1 in = 1; + #1 in = 2; + #1 if (pass) $display("PASSED"); + end + + always @(rval) begin + if (rval != in + 2.0) begin + $display("FAILED: expected %f, got %f", in + 2.0, rval); + pass = 1'b0; + end + end +endmodule diff --git a/ivtest/ivltests/pr2123190.v b/ivtest/ivltests/pr2123190.v new file mode 100644 index 000000000..009032695 --- /dev/null +++ b/ivtest/ivltests/pr2123190.v @@ -0,0 +1,31 @@ +`ifdef __ICARUS__ + `define SUPPORT_REAL_NETS_IN_IVTEST +`endif + +module top; + reg pass = 1'b1; + integer scale = 2, offset = 1; + real rin; + +`ifdef SUPPORT_REAL_NETS_IN_IVTEST + wire real ress = scale * rin; + wire real reso = rin + offset; +`endif + + initial begin +`ifdef SUPPORT_REAL_NETS_IN_IVTEST + #1 if (ress != 0.0 || reso != 1.0) begin + $display("FAILED: initial value, expected 0.0/1.0, got %f/%f", ress, reso); + pass = 1'b0; + end + rin = 2.0; + #1 if (ress != 4.0 || reso != 3.0) begin + $display("FAILED: rin=%f, scale=%f, expected 2.0/2.0, got %f/%f", rin, scale, ress, reso); + pass = 1'b0; + end +`endif + + if (pass) + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2132552.v b/ivtest/ivltests/pr2132552.v new file mode 100644 index 000000000..d1c3cd7a7 --- /dev/null +++ b/ivtest/ivltests/pr2132552.v @@ -0,0 +1,25 @@ +module pr2132552(); + +task test_task; + +parameter depth = 16; +parameter width = 8; + +reg [width-1:0] mem [depth-1:0]; + +integer i; + +begin + for (i = 0; i < depth; i = i + 1) begin + mem[i] = i; + end + for (i = 0; i < depth; i = i + 1) begin + $display("%0d", mem[i]); + end +end + +endtask + +initial test_task; + +endmodule diff --git a/ivtest/ivltests/pr2136787.v b/ivtest/ivltests/pr2136787.v new file mode 100644 index 000000000..046c255ca --- /dev/null +++ b/ivtest/ivltests/pr2136787.v @@ -0,0 +1,30 @@ +module signed_mux_bug(); + +reg s; +reg [3:0] a, b; +reg [7:0] y, z; + +initial begin + // Example vector + s = 1'b1; + a = 4'b1010; + b = 4'b0000; + + // Manually sign extend operands before multiplexer + y = s ? {{4{a[3]}}, a} : {{4{b[3]}}, b}; + + // Use $signed() to sign extend operands before multiplexer + // - Note that Icarus is not sign extending as expected + z = s ? $signed(a) : $signed(b); + + // Display results + $display("a = %b", a); + $display("b = %b", b); + $display("y = %b", y); + $display("z = %b", z); + + // Finished + $finish(0); +end + +endmodule diff --git a/ivtest/ivltests/pr2138682.v b/ivtest/ivltests/pr2138682.v new file mode 100644 index 000000000..e7ba23f7c --- /dev/null +++ b/ivtest/ivltests/pr2138682.v @@ -0,0 +1,27 @@ +module bug(); + +wire [2:0] Value1 = 0; + +generate + genvar i; + + for (i = 0; i < 8; i = i + 1) begin:Block + wire [2:0] Value2; + + assign Value2 = Value1 + 7 - i; + end +endgenerate + +initial begin + #1; + $display("Block 0 value = %0d", Block[0].Value2); + $display("Block 1 value = %0d", Block[1].Value2); + $display("Block 2 value = %0d", Block[2].Value2); + $display("Block 3 value = %0d", Block[3].Value2); + $display("Block 4 value = %0d", Block[4].Value2); + $display("Block 5 value = %0d", Block[5].Value2); + $display("Block 6 value = %0d", Block[6].Value2); + $display("Block 7 value = %0d", Block[7].Value2); +end + +endmodule diff --git a/ivtest/ivltests/pr2138979.v b/ivtest/ivltests/pr2138979.v new file mode 100644 index 000000000..2c42716c5 --- /dev/null +++ b/ivtest/ivltests/pr2138979.v @@ -0,0 +1,48 @@ +// This program is based on pr2138979. In particular, the signed +// expressions are sign-extended before the '|' is evaluated. This +// behavior is verified by modelsim and ncverilog. (It appears that +// gplcver gets this wrong.) + +module main; + + reg [7:0] a, b; + wire [15:0] y; + reg [15:0] z; + + // Use $signed() to sign extend operands before logic OR + // - Note that Icarus Verilog is not sign extending as expected + assign y = $signed(a) | $signed(b); + + initial begin + a = 8'h55; + b = 8'haa; + z = $signed(a) | $signed(b); + + #1 if (y !== 16'hff_ff || y !== z) begin + $display("FAILED -- a=%h, b=%h, y=%h, z=%h", a, b, y, z); + $finish; + end + + a = 8'haa; + b = 8'h55; + z = $signed(a) | $signed(b); + + #1 if (y !== 16'hff_ff || y !== z) begin + $display("FAILED -- a=%h, b=%h, y=%h, z=%h", a, b, y, z); + $finish; + end + + a = 8'h7f; + b = 8'h00; + z = $signed(a) | $signed(b); + + #1 if (y !== 16'h00_7f || y !== z) begin + $display("FAILED -- a=%h, b=%h, y=%h, z=%h", a, b, y, z); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin + +endmodule diff --git a/ivtest/ivltests/pr2138979b.v b/ivtest/ivltests/pr2138979b.v new file mode 100644 index 000000000..705da2b79 --- /dev/null +++ b/ivtest/ivltests/pr2138979b.v @@ -0,0 +1,65 @@ +module signed_logic_operators_bug(); + +reg [7:0] a, b; +wire [15:0] yuu, yus, ysu, yss; +wire [15:0] zuu, zus, zsu, zss; + +initial begin + // Example vector + a = 8'b10110110; + b = 8'b10010010; + + // Wait for results to be calculated + #1; + + // Display results + $display("a = %b", a); + $display("b = %b", b); + $display("yuu = %b", yuu); + $display("zuu = %b", zuu); + $display("yus = %b", yus); + $display("zus = %b", zus); + $display("ysu = %b", ysu); + $display("zsu = %b", zsu); + $display("yss = %b", yss); + $display("zss = %b", zss); + + // Finished + $finish(0); +end + +// Calculate signed logical OR +manually_extended_logical_or INST1(.a(a), .b(b), .yuu(yuu), .yus(yus), .ysu(ysu), .yss(yss)); +signed_logical_or INST2(.a(a), .b(b), .yuu(zuu), .yus(zus), .ysu(zsu), .yss(zss)); + +endmodule + +module manually_extended_logical_or(a, b, yuu, yus, ysu, yss); + +input [7:0] a, b; +output [15:0] yuu, yus, ysu, yss; + +// Manually zero or sign extend operands before logic OR +// - Note the operands are zero extended in "yuu", "yus" and "ysu" +// - The operands are sign extended in "yss" +assign yuu = {{8{1'b0}}, a} | {{8{1'b0}}, b}; +assign yus = {{8{1'b0}}, a} | {{8{1'b0}}, b}; +assign ysu = {{8{1'b0}}, a} | {{8{1'b0}}, b}; +assign yss = {{8{a[7]}}, a} | {{8{b[7]}}, b}; + +endmodule + +module signed_logical_or(a, b, yuu, yus, ysu, yss); + +input [7:0] a, b; +output [15:0] yuu, yus, ysu, yss; + +// Note that the operation is only consider signed if ALL data operands are signed +// - Therefore $signed(a) does NOT sign extend "a" in expression "ysu" +// - But "a" and "b" are both sign extended before the OR in expression "yss" +assign yuu = a | b ; +assign yus = a | $signed(b); +assign ysu = $signed(a) | b ; +assign yss = $signed(a) | $signed(b); + +endmodule diff --git a/ivtest/ivltests/pr2138979c.v b/ivtest/ivltests/pr2138979c.v new file mode 100644 index 000000000..0e8d8bb05 --- /dev/null +++ b/ivtest/ivltests/pr2138979c.v @@ -0,0 +1,47 @@ +module signed_assignment_bug(); + +reg [7:0] a; +wire [15:0] y; +wire [15:0] z; + +initial begin + // Example vector + a = 8'b10110110; + + // Wait for results to be calculated + #1; + + // Display results + $display("a = %b", a); + $display("y = %b", y); + $display("z = %b", z); + + // Finished + $finish(0); +end + +// Calculate signed logical OR +manually_extended_assignment INST1(.a(a), .y(y)); +signed_assignment INST2(.a(a), .y(z)); + +endmodule + +module manually_extended_assignment(a, y); + +input [7:0] a; +output [15:0] y; + +// Manually sign extend before assignment +assign y = {{8{a[7]}}, a}; + +endmodule + +module signed_assignment(a, y); + +input [7:0] a; +output [15:0] y; + +// $signed() sign extends before assignment +assign y = $signed(a); + +endmodule diff --git a/ivtest/ivltests/pr2138979d.v b/ivtest/ivltests/pr2138979d.v new file mode 100644 index 000000000..db14044a7 --- /dev/null +++ b/ivtest/ivltests/pr2138979d.v @@ -0,0 +1,253 @@ +module signed_logic_operators_bug(); + +reg sel; +reg [7:0] a, b; +reg [5:0] c; +wire [15:0] y_mux_uu, y_mux_us, y_mux_su, y_mux_ss; +wire y_eql_uu, y_eql_us, y_eql_su, y_eql_ss; +wire y_neq_uu, y_neq_us, y_neq_su, y_neq_ss; +wire [15:0] y_sgn_u, y_sgn_s; +wire [15:0] y_add_uu, y_add_us, y_add_su, y_add_ss; +wire [15:0] y_sub_uu, y_sub_us, y_sub_su, y_sub_ss; +wire [15:0] y_mul_uu, y_mul_us, y_mul_su, y_mul_ss; +wire y_ltn_uu, y_ltn_us, y_ltn_su, y_ltn_ss; +wire y_leq_uu, y_leq_us, y_leq_su, y_leq_ss; +wire [15:0] z_mux_uu, z_mux_us, z_mux_su, z_mux_ss; +wire z_eql_uu, z_eql_us, z_eql_su, z_eql_ss; +wire z_neq_uu, z_neq_us, z_neq_su, z_neq_ss; +wire [15:0] z_sgn_u, z_sgn_s; +wire [15:0] z_add_uu, z_add_us, z_add_su, z_add_ss; +wire [15:0] z_sub_uu, z_sub_us, z_sub_su, z_sub_ss; +wire [15:0] z_mul_uu, z_mul_us, z_mul_su, z_mul_ss; +wire z_ltn_uu, z_ltn_us, z_ltn_su, z_ltn_ss; +wire z_leq_uu, z_leq_us, z_leq_su, z_leq_ss; + +integer i; + +initial begin + for (i = 0; i < 100; i = i + 1) begin + // Example vector + sel = $random; + a = $random; + b = $random; + c = $random; + + // Wait for results to be calculated + #1; + + // Display results + $display("sel = %b", sel); + $display("a = %b", a); + $display("b = %b", b); + $display("c = %b", c); + $display("y_mux_uu = %b y_mux_us = %b y_mux_su = %b y_mux_ss = %b", y_mux_uu, y_mux_us, y_mux_su, y_mux_ss); + $display("z_mux_uu = %b z_mux_us = %b z_mux_su = %b z_mux_ss = %b", z_mux_uu, z_mux_us, z_mux_su, z_mux_ss); + $display("y_eql_uu = %b y_eql_us = %b y_eql_su = %b y_eql_ss = %b", y_eql_uu, y_eql_us, y_eql_su, y_eql_ss); + $display("z_eql_uu = %b z_eql_us = %b z_eql_su = %b z_eql_ss = %b", z_eql_uu, z_eql_us, z_eql_su, z_eql_ss); + $display("y_neq_uu = %b y_neq_us = %b y_neq_su = %b y_neq_ss = %b", y_neq_uu, y_neq_us, y_neq_su, y_neq_ss); + $display("z_neq_uu = %b z_neq_us = %b z_neq_su = %b z_neq_ss = %b", z_neq_uu, z_neq_us, z_neq_su, z_neq_ss); + $display("y_sgn_u = %b y_sgn_s = %b" , y_sgn_u, y_sgn_s); + $display("z_sgn_u = %b z_sgn_s = %b" , z_sgn_u, z_sgn_s); + $display("y_add_uu = %b y_add_us = %b y_add_su = %b y_add_ss = %b", y_add_uu, y_add_us, y_add_su, y_add_ss); + $display("z_add_uu = %b z_add_us = %b z_add_su = %b z_add_ss = %b", z_add_uu, z_add_us, z_add_su, z_add_ss); + $display("y_sub_uu = %b y_sub_us = %b y_sub_su = %b y_sub_ss = %b", y_sub_uu, y_sub_us, y_sub_su, y_sub_ss); + $display("z_sub_uu = %b z_sub_us = %b z_sub_su = %b z_sub_ss = %b", z_sub_uu, z_sub_us, z_sub_su, z_sub_ss); + $display("y_mul_uu = %b y_mul_us = %b y_mul_su = %b y_mul_ss = %b", y_mul_uu, y_mul_us, y_mul_su, y_mul_ss); + $display("z_mul_uu = %b z_mul_us = %b z_mul_su = %b z_mul_ss = %b", z_mul_uu, z_mul_us, z_mul_su, z_mul_ss); + $display("y_ltn_uu = %b y_ltn_us = %b y_ltn_su = %b y_ltn_ss = %b", y_ltn_uu, y_ltn_us, y_ltn_su, y_ltn_ss); + $display("z_ltn_uu = %b z_ltn_us = %b z_ltn_su = %b z_ltn_ss = %b", z_ltn_uu, z_ltn_us, z_ltn_su, z_ltn_ss); + $display("y_leq_uu = %b y_leq_us = %b y_leq_su = %b y_leq_ss = %b", y_leq_uu, y_leq_us, y_leq_su, y_leq_ss); + $display("z_leq_uu = %b z_leq_us = %b z_leq_su = %b z_leq_ss = %b", z_leq_uu, z_leq_us, z_leq_su, z_leq_ss); + end + + // Finished + $finish(0); +end + +// Manually sign extended operators +manually_extended_operators INST1( + sel, + a, b, + c, + y_mux_uu, y_mux_us, y_mux_su, y_mux_ss, + y_eql_uu, y_eql_us, y_eql_su, y_eql_ss, + y_neq_uu, y_neq_us, y_neq_su, y_neq_ss, + y_sgn_u, y_sgn_s, + y_add_uu, y_add_us, y_add_su, y_add_ss, + y_sub_uu, y_sub_us, y_sub_su, y_sub_ss, + y_mul_uu, y_mul_us, y_mul_su, y_mul_ss, + y_ltn_uu, y_ltn_us, y_ltn_su, y_ltn_ss, + y_leq_uu, y_leq_us, y_leq_su, y_leq_ss + ); + +// $signed() sign extended operators +signed_operators INST2( + sel, + a, b, + c, + z_mux_uu, z_mux_us, z_mux_su, z_mux_ss, + z_eql_uu, z_eql_us, z_eql_su, z_eql_ss, + z_neq_uu, z_neq_us, z_neq_su, z_neq_ss, + z_sgn_u, z_sgn_s, + z_add_uu, z_add_us, z_add_su, z_add_ss, + z_sub_uu, z_sub_us, z_sub_su, z_sub_ss, + z_mul_uu, z_mul_us, z_mul_su, z_mul_ss, + z_ltn_uu, z_ltn_us, z_ltn_su, z_ltn_ss, + z_leq_uu, z_leq_us, z_leq_su, z_leq_ss + ); + +endmodule + +module signed_operators( + sel, + a, b, + c, + mux_uu, mux_us, mux_su, mux_ss, + eql_uu, eql_us, eql_su, eql_ss, + neq_uu, neq_us, neq_su, neq_ss, + sgn_u, sgn_s, + add_uu, add_us, add_su, add_ss, + sub_uu, sub_us, sub_su, sub_ss, + mul_uu, mul_us, mul_su, mul_ss, + ltn_uu, ltn_us, ltn_su, ltn_ss, + leq_uu, leq_us, leq_su, leq_ss + ); + +input sel; +input [7:0] a, b; +input [5:0] c; +output [15:0] mux_uu, mux_us, mux_su, mux_ss; +output eql_uu, eql_us, eql_su, eql_ss; +output neq_uu, neq_us, neq_su, neq_ss; +output [15:0] sgn_u, sgn_s; +output [15:0] add_uu, add_us, add_su, add_ss; +output [15:0] sub_uu, sub_us, sub_su, sub_ss; +output [15:0] mul_uu, mul_us, mul_su, mul_ss; +output ltn_uu, ltn_us, ltn_su, ltn_ss; +output leq_uu, leq_us, leq_su, leq_ss; + +// Note that the operation is only consider signed if ALL data operands are signed +// - Therefore $signed(a) does NOT sign extend "a" in expression "X_su" +// - But "a" and "b" are both sign extended before the operation in expression "X_ss" + +assign mux_uu = sel ? a : b ; +assign mux_us = sel ? a : $signed(b); +assign mux_su = sel ? $signed(a) : b ; +assign mux_ss = sel ? $signed(a) : $signed(b); + +assign eql_uu = a == c ; +assign eql_us = a == $signed(c); +assign eql_su = $signed(a) == c ; +assign eql_ss = $signed(a) == $signed(c); + +assign neq_uu = a != c ; +assign neq_us = a != $signed(c); +assign neq_su = $signed(a) != c ; +assign neq_ss = $signed(a) != $signed(c); + +assign sgn_u = ~$unsigned(c) ; +assign sgn_s = ~$signed(c) ; + +assign add_uu = a + c ; +assign add_us = a + $signed(c); +assign add_su = $signed(a) + c ; +assign add_ss = $signed(a) + $signed(c); + +assign sub_uu = a - c ; +assign sub_us = a - $signed(c); +assign sub_su = $signed(a) - c ; +assign sub_ss = $signed(a) - $signed(c); + +assign mul_uu = a * c ; +assign mul_us = a * $signed(c); +assign mul_su = $signed(a) * c ; +assign mul_ss = $signed(a) * $signed(c); + +assign ltn_uu = a < c ; +assign ltn_us = a < $signed(c); +assign ltn_su = $signed(a) < c ; +assign ltn_ss = $signed(a) < $signed(c); + +assign leq_uu = a <= c ; +assign leq_us = a <= $signed(c); +assign leq_su = $signed(a) <= c ; +assign leq_ss = $signed(a) <= $signed(c); + +endmodule + +module manually_extended_operators( + sel, + a, b, + c, + mux_uu, mux_us, mux_su, mux_ss, + eql_uu, eql_us, eql_su, eql_ss, + neq_uu, neq_us, neq_su, neq_ss, + sgn_u, sgn_s, + add_uu, add_us, add_su, add_ss, + sub_uu, sub_us, sub_su, sub_ss, + mul_uu, mul_us, mul_su, mul_ss, + ltn_uu, ltn_us, ltn_su, ltn_ss, + leq_uu, leq_us, leq_su, leq_ss + ); + +input sel; +input [7:0] a, b; +input [5:0] c; +output [15:0] mux_uu, mux_us, mux_su, mux_ss; +output eql_uu, eql_us, eql_su, eql_ss; +output neq_uu, neq_us, neq_su, neq_ss; +output [15:0] sgn_u, sgn_s; +output [15:0] add_uu, add_us, add_su, add_ss; +output [15:0] sub_uu, sub_us, sub_su, sub_ss; +output [15:0] mul_uu, mul_us, mul_su, mul_ss; +output ltn_uu, ltn_us, ltn_su, ltn_ss; +output leq_uu, leq_us, leq_su, leq_ss; + +// Manually zero or sign extend operands before the operation. +// - Note the operands are zero extended in "X_uu", "X_us" and "X_su" +// - The operands are sign extended in "X_ss" + +assign mux_uu = sel ? {{8{1'b0}}, a} : {{8{1'b0}}, b}; +assign mux_us = sel ? {{8{1'b0}}, a} : {{8{1'b0}}, b}; +assign mux_su = sel ? {{8{1'b0}}, a} : {{8{1'b0}}, b}; +assign mux_ss = sel ? {{8{a[7]}}, a} : {{8{b[7]}}, b}; + +assign eql_uu = {a} == {{2{1'b0}}, c}; +assign eql_us = {a} == {{2{1'b0}}, c}; +assign eql_su = {a} == {{2{1'b0}}, c}; +assign eql_ss = {a} == {{2{c[5]}}, c}; + +assign neq_uu = {a} != {{2{1'b0}}, c}; +assign neq_us = {a} != {{2{1'b0}}, c}; +assign neq_su = {a} != {{2{1'b0}}, c}; +assign neq_ss = {a} != {{2{c[5]}}, c}; + +assign sgn_u = ~{{10{1'b0}}, c} ; +assign sgn_s = ~{{10{c[5]}}, c} ; + +assign add_uu = {{8{1'b0}}, a} + {{10{1'b0}}, c}; +assign add_us = {{8{1'b0}}, a} + {{10{1'b0}}, c}; +assign add_su = {{8{1'b0}}, a} + {{10{1'b0}}, c}; +assign add_ss = {{8{a[7]}}, a} + {{10{c[5]}}, c}; + +assign sub_uu = {{8{1'b0}}, a} - {{10{1'b0}}, c}; +assign sub_us = {{8{1'b0}}, a} - {{10{1'b0}}, c}; +assign sub_su = {{8{1'b0}}, a} - {{10{1'b0}}, c}; +assign sub_ss = {{8{a[7]}}, a} - {{10{c[5]}}, c}; + +assign mul_uu = {{8{1'b0}}, a} * {{10{1'b0}}, c}; +assign mul_us = {{8{1'b0}}, a} * {{10{1'b0}}, c}; +assign mul_su = {{8{1'b0}}, a} * {{10{1'b0}}, c}; +assign mul_ss = {{8{a[7]}}, a} * {{10{c[5]}}, c}; + +assign ltn_uu = {{8{1'b0}}, a} < {{10{1'b0}}, c}; +assign ltn_us = {{8{1'b0}}, a} < {{10{1'b0}}, c}; +assign ltn_su = {{8{1'b0}}, a} < {{10{1'b0}}, c}; +assign ltn_ss = {c[5],{7{a[7]}}, a} < {a[7],{9{c[5]}}, c}; + +assign leq_uu = {{8{1'b0}}, a} <= {{10{1'b0}}, c}; +assign leq_us = {{8{1'b0}}, a} <= {{10{1'b0}}, c}; +assign leq_su = {{8{1'b0}}, a} <= {{10{1'b0}}, c}; +assign leq_ss = {c[5],{7{a[7]}}, a} <= {a[7],{9{c[5]}}, c}; + +endmodule diff --git a/ivtest/ivltests/pr2139593.v b/ivtest/ivltests/pr2139593.v new file mode 100644 index 000000000..bc6154814 --- /dev/null +++ b/ivtest/ivltests/pr2139593.v @@ -0,0 +1,24 @@ +module top; + tb #(1024) dut(); + defparam dut.Y = 2048; +endmodule + +module tb; + reg pass = 1'b1; + parameter Z = 256; + parameter Y = 128; + parameter B = $clog2(Z); + localparam C = $clog2(Y); + + initial begin + if (B !== 10) begin + $display("FAILED: parameter value, expected 10, got %0d", B); + pass = 1'b0; + end + if (C !== 11) begin + $display("FAILED: localparam value, expected 11, got %0d", C); + pass = 1'b0; + end + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2146620.v b/ivtest/ivltests/pr2146620.v new file mode 100644 index 000000000..72d768ded --- /dev/null +++ b/ivtest/ivltests/pr2146620.v @@ -0,0 +1,17 @@ +module bug(); + +integer i; +integer j; + +reg [7:0] Value; + +initial begin + for (i = 0; i < 2; i = i + 1) begin + for (j = 0; j < 2; j = j + 1) begin + Value = i * 256 + j * 128; + $display(Value); + end + end +end + +endmodule diff --git a/ivtest/ivltests/pr2146620b.v b/ivtest/ivltests/pr2146620b.v new file mode 100644 index 000000000..944f17ed7 --- /dev/null +++ b/ivtest/ivltests/pr2146620b.v @@ -0,0 +1,16 @@ +module bug(); + +localparam Size = 24; + +reg [2:0] Value; + +integer n; + +initial begin + for (n = 0; n < (Size/4); n = n + 1) begin + Value = (Size/4) - n - 1; + $display(Value); + end +end + +endmodule diff --git a/ivtest/ivltests/pr2146620c.v b/ivtest/ivltests/pr2146620c.v new file mode 100644 index 000000000..31ad2ce5c --- /dev/null +++ b/ivtest/ivltests/pr2146620c.v @@ -0,0 +1,14 @@ +module comp1001a; +// extracted from comp1001.v, +// Copyright (c) 2000 Paul Campbell (paul@verifarm.com) +// GPLv2 or later blah blah blah + +reg [4:0] r170; +initial begin + r170 = (5'h1c % 25'h5b50) - 20'h05818; + $displayb("r170 = ",r170); + if (r170 == 5'b00100) $display("PASSED"); + else $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2146824.v b/ivtest/ivltests/pr2146824.v new file mode 100644 index 000000000..204087a34 --- /dev/null +++ b/ivtest/ivltests/pr2146824.v @@ -0,0 +1,12 @@ +module bug(); + +reg [9:0] i; +reg [7:0] j; + +initial begin + i = 10'h3ff; + j = (i / 4) & 8'hfe; + $display("'h%h", j); +end + +endmodule diff --git a/ivtest/ivltests/pr2148401.v b/ivtest/ivltests/pr2148401.v new file mode 100644 index 000000000..f247273e9 --- /dev/null +++ b/ivtest/ivltests/pr2148401.v @@ -0,0 +1,9 @@ +module top; + reg [79:0] data = 0; + + initial begin + data = data + 80'h12345678901234567890; + if (data !== 80'h12345678901234567890) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2152011.v b/ivtest/ivltests/pr2152011.v new file mode 100644 index 000000000..5e661843a --- /dev/null +++ b/ivtest/ivltests/pr2152011.v @@ -0,0 +1,10 @@ +module dupe; + +integer cc; +reg signed [19:0] y; +initial for (cc=0; cc<20; cc=cc+1) begin + y = $floor(200000.0*$sin(cc*0.81)+0.5); + $display("%7d", y); +end + +endmodule diff --git a/ivtest/ivltests/pr2159630.v b/ivtest/ivltests/pr2159630.v new file mode 100644 index 000000000..915126d3d --- /dev/null +++ b/ivtest/ivltests/pr2159630.v @@ -0,0 +1,17 @@ +module test(); + parameter N_N = 3; + + reg signed [2*N_N-1:0] val_neg; + reg signed [2*N_N-1:0] val_pos; + + + initial + begin + val_neg = {{N_N+1{1'b1}},{N_N-1{1'b0}}}; + val_pos = {{N_N+1{1'b0}},{N_N-1{1'b1}}}; + #1 $display("Var %d vs signed(concat) %d", + val_neg, + $signed({{N_N+1{1'b1}},{N_N-1{1'b0}}})); + $finish(0); + end // initial begin +endmodule // test diff --git a/ivtest/ivltests/pr2166188.v b/ivtest/ivltests/pr2166188.v new file mode 100644 index 000000000..f96485d84 --- /dev/null +++ b/ivtest/ivltests/pr2166188.v @@ -0,0 +1,32 @@ +module t(); + +parameter eh = 11; +parameter mh = 52; + +parameter ih2 = 6; +parameter fh = 7; + +localparam ih = 1 << ih2; + +reg [ih - 1:0] i_abs; + +reg at; +reg [ih2 - 1:0] fls; + +wire [ih - 1:0] i_norm; + +assign i_norm = i_abs << (at ? ih - mh - 1 : fls); + +initial +begin + at = 1; + fls = 123; + i_abs = 'h123; + #1; + if(i_norm !== ('h123 << 11)) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2166311.v b/ivtest/ivltests/pr2166311.v new file mode 100644 index 000000000..fc4c39102 --- /dev/null +++ b/ivtest/ivltests/pr2166311.v @@ -0,0 +1,79 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass = 1'b1; + wire [3:0] part_idx_up, part_idx_down, part_sel; + wire [3:0] ps_array [1:0]; + + // Check the positive indexed part select. +// assign part_idx_up[-1+:2] = 2'b01; // We do not currently support this! + assign part_idx_up[1+:2] = 2'b01; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign part_idx_up[3+:2] = 2'b01; + assign part_idx_up[5+:2] = 2'b01; // This should be skipped + assign part_idx_up[7+:3] = 3'b001; // This should be skipped +`else + assign part_idx_up[3] = 1'b1; +`endif + + // Check the negative indexed part select. +// assign part_idx_down[0-:2] = 2'b10; // We do not currently support this! + assign part_idx_down[2-:2] = 2'b10; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign part_idx_down[4-:2] = 2'b10; + assign part_idx_down[6-:2] = 2'b10; // This should be skipped + assign part_idx_down[9-:3] = 3'b100; // This should be skipped +`else + assign part_idx_down[3] = 1'b0; +`endif + + // Check a normal constant part select. +// assign part_sel[1:-1] = 2'b01; // We do not currently support this! + assign part_sel[2:1] = 2'b01; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign part_sel[4:3] = 2'b01; + assign part_sel[6:5] = 2'b01; // This should be skipped + assign part_sel[9:7] = 3'b001; // This should be skipped +`else + assign part_sel[3] = 1'b1; +`endif + + // Check a normal constant part select on an array. +// assign ps_array[0][1:-1] = 2'b01; // We do not currently support this! + assign ps_array[0][2:1] = 2'b01; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign ps_array[0][4:3] = 2'b01; + assign ps_array[0][6:5] = 2'b01; // This should be skipped + assign ps_array[0][9:7] = 3'b001; // This should be skipped +`else + assign ps_array[0][3] = 1'b1; +`endif + + initial begin + #1; + if (part_idx_up !== 4'b101z) begin + $display("Failed +: select, expected 4'b101z, got %b", part_idx_up); + pass = 1'b0; + end + + if (part_idx_down !== 4'b010z) begin + $display("Failed -: select, expected 4'b010z, got %b", part_idx_down); + pass = 1'b0; + end + + if (part_sel !== 4'b101z) begin + $display("Failed const. part select, expected 4'b101z, got %b", part_sel); + pass = 1'b0; + end + + if (ps_array[0] !== 4'b101z) begin + $display("Failed array part select, expected 4'b101z, got %b", + ps_array[0]); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2169870.v b/ivtest/ivltests/pr2169870.v new file mode 100644 index 000000000..8382332e9 --- /dev/null +++ b/ivtest/ivltests/pr2169870.v @@ -0,0 +1,24 @@ +// Copyright 2008, Martin Whitaker. +// This file may be copied freely for any purpose. No attribution required. + +module pr2169870(); + +task automatic count; + +integer i; + +begin + i = 0; + while (i < 10) begin + #1 $display("%0d", i); + i = i + 1; + end +end + +endtask + +initial count; + +initial count; + +endmodule diff --git a/ivtest/ivltests/pr2172606.v b/ivtest/ivltests/pr2172606.v new file mode 100644 index 000000000..8264927eb --- /dev/null +++ b/ivtest/ivltests/pr2172606.v @@ -0,0 +1,50 @@ +module main; + reg passed = 1'b1; + wire out1; + reg local_out; + reg mode; + + assign out1 = mode ? 1'bz : local_out; + pullup(out1); + + initial begin + mode = 1'b1; + local_out = 1'bx; + // The pull up device sets the level. + #1 if (out1 !== 1'b1) begin + $display("FAILED test 1, expected 1'b1, got %b", out1); + passed = 1'b0; + end + + mode = 1'b0; + local_out = 1'b0; + // Set by local out. + #1 if (out1 !== local_out) begin + $display("FAILED test 1, expected %b, got %b", local_out, out1); + passed = 1'b0; + end + + local_out = 1'b1; + // Set by local out. + #1 if (out1 !== local_out) begin + $display("FAILED test 1, expected %b, got %b", local_out, out1); + passed = 1'b0; + end + + local_out = 1'bx; + // Set by local out. + #1 if (out1 !== local_out) begin + $display("FAILED test 1, expected %b, got %b", local_out, out1); + passed = 1'b0; + end + + local_out = 1'bz; + // The pull up device sets the level. + #1 if (out1 !== 1'b1) begin + $display("FAILED test 1, expected 1'b1, got %b", out1); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2172606b.v b/ivtest/ivltests/pr2172606b.v new file mode 100644 index 000000000..3bbd2598f --- /dev/null +++ b/ivtest/ivltests/pr2172606b.v @@ -0,0 +1,134 @@ +`begin_keywords "1364-2005" +module top; + reg passed = 1'b1; + wire out, cout0, cout1; + reg sel, in_1, in_0; + reg pout; + +`ifdef __ICARUS__ + // This is technically incorrect for 1'bz inputs. The standard + // states that we should produce 1'bx for that case (idiotic)! + localparam zz_blend = 1'bz; +`else + localparam zz_blend = 1'bx; +`endif + + assign cout0 = sel ? 1'bz : in_0; + assign cout1 = sel ? in_1: 1'bz; + assign out = sel ? in_1: in_0; + + task automatic check; + input bit, in_1, in_0; + input [63:0] comment; + begin + if (sel === 1'b1) begin + if (bit !== in_1) begin + $display("FAILED: %0s sel = 1'b1, expected %b, got %b", + comment, in_1, bit); + passed = 1'b0; + end + end else if (sel === 1'b0) begin + if (bit !== in_0) begin + $display("FAILED: %0s sel = 1'b0, expected %b, got %b", + comment, in_0, bit); + passed = 1'b0; + end + end else begin + if (in_0 === 1'bz && in_1 === 1'bz && bit !== zz_blend) begin + $display("FAILED: %0s sel = 1'bx/z & ins = %b, expected 1'b%b, got %b", + comment, in_0, zz_blend, bit); + passed = 1'b0; + end else if (in_0 === in_1 && in_0 !== bit) begin + $display("FAILED: %0s sel = 1'bx/z & ins = %b, expected 1'b%b, got %b", + comment, in_0, in_0, bit); + passed = 1'b0; + end else if (in_0 !== in_1 && bit !== 1'bx) begin + $display("FAILED: %0s sel = 1'bx/z & %b %b, expected 1'bx, got %b", + comment, in_1, in_0, bit); + passed = 1'b0; + end + end + end + endtask + + // Check the 1 case as a constant Z + always @(cout0) begin + check(cout0, 1'bz, in_0, "CZ 1"); + end + + // Check the 0 case as a constant Z + always @(cout1) begin + check(cout1, in_1, 1'bz, "CZ 0"); + end + + // Check the continuous assign + always @(out) begin + check(out, in_1, in_0, "CA"); + end + + // Check procedural assign. + always @(sel, in_1, in_0) begin + check(sel ? in_1 : in_0, in_1, in_0, "PR"); + end + + initial begin + #1 sel = 1'b1; + #1 in_1 = 1'b0; + #1 in_1 = 1'b1; + #1 in_1 = 1'bz; + #1 in_1 = 1'bx; + + #1 sel = 1'b0; + #1 in_0 = 1'b0; + #1 in_0 = 1'b1; + #1 in_0 = 1'bz; + #1 in_0 = 1'bx; + + #1 sel = 1'bx; + #1 in_1 = 1'b0; // + #1 in_0 = 1'b0; + #1 in_0 = 1'b1; + #1 in_0 = 1'bz; + #1 in_0 = 1'bx; + #1 in_1 = 1'b1; // + #1 in_0 = 1'b0; + #1 in_0 = 1'b1; + #1 in_0 = 1'bz; + #1 in_0 = 1'bx; + #1 in_1 = 1'bz; // + #1 in_0 = 1'b0; + #1 in_0 = 1'b1; + #1 in_0 = 1'bz; + #1 in_0 = 1'bx; + #1 in_1 = 1'bx; // + #1 in_0 = 1'b0; + #1 in_0 = 1'b1; + #1 in_0 = 1'bz; + #1 in_0 = 1'bx; + + #1 sel = 1'bz; + #1 in_1 = 1'b0; // + #1 in_0 = 1'b0; + #1 in_0 = 1'b1; + #1 in_0 = 1'bz; + #1 in_0 = 1'bx; + #1 in_1 = 1'b1; // + #1 in_0 = 1'b0; + #1 in_0 = 1'b1; + #1 in_0 = 1'bz; + #1 in_0 = 1'bx; + #1 in_1 = 1'bz; // + #1 in_0 = 1'b0; + #1 in_0 = 1'b1; + #1 in_0 = 1'bz; + #1 in_0 = 1'bx; + #1 in_1 = 1'bx; // + #1 in_0 = 1'b0; + #1 in_0 = 1'b1; + #1 in_0 = 1'bz; + #1 in_0 = 1'bx; + + #1 if (passed) $display("PASSED"); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr2181249.v b/ivtest/ivltests/pr2181249.v new file mode 100644 index 000000000..de158f58a --- /dev/null +++ b/ivtest/ivltests/pr2181249.v @@ -0,0 +1,11 @@ +module pr0; + reg r; + initial r = ( 1'b1 ? 1'b0 : 1'b0) ? 1'b0 : 1'b0; + initial begin + #1 if (r !== 1'b0) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2190323.v b/ivtest/ivltests/pr2190323.v new file mode 100644 index 000000000..25bff7e76 --- /dev/null +++ b/ivtest/ivltests/pr2190323.v @@ -0,0 +1,19 @@ +/* + * This is a reduced example from comp1001 to demonstrate a problem + * in Icarus Verilog. Since this fails using just the compiler this + * appears to be a problem in the elaboration of the expression. + * + * The division should be done at the L-value width not at the + * argument width. This is not the case for this example. + */ +module compl1001; + reg [133:124]r66; + + initial begin +// r66 = ((!1'b1) / ((18'h0 - (1'b1 + 1'b1)) <= 10'h000)); + r66 = (!1'b1) / 1'b0; // This fails. +// r66 = 1'b0 / 1'b0; // This passes. + if (r66 !== 10'bx) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2201909.v b/ivtest/ivltests/pr2201909.v new file mode 100644 index 000000000..5a6e05c8c --- /dev/null +++ b/ivtest/ivltests/pr2201909.v @@ -0,0 +1,21 @@ +module top; + reg passed = 1'b1; + real rvar [1:0]; + + initial begin + #1; + rvar[0] = -1.0; + if (rvar[0] != -1.0) begin + $display("Failed: real array[0], expected -1.0, got %g", rvar[0]); + passed = 1'b0; + end + + rvar[1] = 2.0; + if (rvar[1] != 2.0) begin + $display("Failed: real array[1], expected 2.0, got %g", rvar[1]); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2201909b.v b/ivtest/ivltests/pr2201909b.v new file mode 100644 index 000000000..c6baa8478 --- /dev/null +++ b/ivtest/ivltests/pr2201909b.v @@ -0,0 +1,21 @@ +module top; + reg passed = 1'b1; + realtime rvar [1:0]; + + initial begin + #1; + rvar[0] = -1.0; + if (rvar[0] != -1.0) begin + $display("Failed: real time array[0], expected -1.0, got %g", rvar[0]); + passed = 1'b0; + end + + rvar[1] = 2.0; + if (rvar[1] != 2.0) begin + $display("Failed: real time array[1], expected 2.0, got %g", rvar[1]); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2202706.v b/ivtest/ivltests/pr2202706.v new file mode 100644 index 000000000..b88e8cb1a --- /dev/null +++ b/ivtest/ivltests/pr2202706.v @@ -0,0 +1,28 @@ +module top; + reg passed; + reg [63:0] wide; + reg [31:0] norm; + + initial begin + passed = 1'b1; + if (! $value$plusargs("option=%h", wide)) begin + $display("FAILED: Unable to read wide option"); + passed = 1'b0; + end + if (wide !== 64'h0123456789abcdef) begin + $display("FAILED: wide expected 64'h0123456789abcdef, got %h", wide); + passed = 1'b0; + end + + if (! $value$plusargs("option=%h", norm)) begin + $display("FAILED: Unable to read normal option"); + passed = 1'b0; + end + if (norm !== 32'h89abcdef) begin + $display("FAILED: normal expected 32'h89abcdef, got %h", norm); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2202706b.v b/ivtest/ivltests/pr2202706b.v new file mode 100644 index 000000000..3330f5ab6 --- /dev/null +++ b/ivtest/ivltests/pr2202706b.v @@ -0,0 +1,21 @@ +module top; + reg passed; + + initial begin + passed = 1'b1; + if ($test$plusargs("opt") == 0) begin + $display("Failed to find +opt"); + passed = 1'b0; + end + if ($test$plusargs("option") == 0) begin + $display("Failed to find +option"); + passed = 1'b0; + end + if ($test$plusargs("options") != 0) begin + $display("Failed, found +options"); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2202706c.v b/ivtest/ivltests/pr2202706c.v new file mode 100644 index 000000000..a6bce5a7c --- /dev/null +++ b/ivtest/ivltests/pr2202706c.v @@ -0,0 +1,277 @@ +module top; + reg passed; + reg [9*8:1] check; + reg [71:0] value; + reg [7:0] nval; + real rval; + + initial begin + passed = 1'b1; + // Look for the hex value using a runtime string. + check = "hex=%h"; + if (! $value$plusargs(check, value)) begin + $display("FAILED: Unable to get hex value."); + passed = 1'b0; + end + if (value !== 72'h0123456789abcdefxz) begin + $display("FAILED: expected hex value 72'h0123456789abcdefxz, got %h", + value); + passed = 1'b0; + end + + // Look for a hex (x) value. + if (! $value$plusargs("hex=%x", value)) begin + $display("FAILED: Unable to get hex value."); + passed = 1'b0; + end + if (value !== 72'h0123456789abcdefxz) begin + $display("FAILED: expected hex value 72'h0123456789abcdefxz, got %h", + value); + passed = 1'b0; + end + + // Look for an octal value. + if (! $value$plusargs("oct=%o", value)) begin + $display("FAILED: Unable to get octal value."); + passed = 1'b0; + end + if (value !== 72'o01234567xz) begin + $display("FAILED: expected octal value 72'o01234567xz, got %o", + value); + passed = 1'b0; + end + + // Look for a binary value. + if (! $value$plusargs("bin=%b", value)) begin + $display("FAILED: Unable to get binary value."); + passed = 1'b0; + end + if (value !== 72'b0101xz) begin + $display("FAILED: expected binary value 72'b0101xz, got %b", + value); + passed = 1'b0; + end + + // Look for a negative binary value. + if (! $value$plusargs("neg=%b", value)) begin + $display("FAILED: Unable to get negative binary value."); + passed = 1'b0; + end + if (value !== 72'hfffffffffffffffffc) begin + $display("FAILED: expected binary value 72'hff...fc, got %h", + value); + passed = 1'b0; + end + + // Look for a negative octal value. + if (! $value$plusargs("neg=%o", value)) begin + $display("FAILED: Unable to get negative octal value."); + passed = 1'b0; + end + if (value !== 72'hffffffffffffffffc0) begin + $display("FAILED: expected octal value 72'hff...fc0, got %h", + value); + passed = 1'b0; + end + + // Look for a truncated negative hex value. + if (! $value$plusargs("neg=%h", nval)) begin + $display("FAILED: Unable to get negative hex value."); + passed = 1'b0; + end + if (nval !== 8'h00) begin + $display("FAILED: expected hex value 8'h00, got %h", + nval); + passed = 1'b0; + end + + // Look for a bad binary value. + if (! $value$plusargs("bad_num=%b", value)) begin + $display("FAILED: Unable to get bad binary value."); + passed = 1'b0; + end + if (value !== 'bx) begin + $display("FAILED: expected bad binary value 'bx, got %d", + value); + passed = 1'b0; + end + + // Look for a bad octal value. + if (! $value$plusargs("bad_num=%o", value)) begin + $display("FAILED: Unable to get bad octal value."); + passed = 1'b0; + end + if (value !== 'bx) begin + $display("FAILED: expected bad octal value 'bx, got %d", + value); + passed = 1'b0; + end + + // Look for a bad hex value. + if (! $value$plusargs("bad_num=%h", value)) begin + $display("FAILED: Unable to get bad hex value."); + passed = 1'b0; + end + if (value !== 'bx) begin + $display("FAILED: expected bad hex value 'bx, got %d", + value); + passed = 1'b0; + end + + // Look for a bad hex (x) value. + if (! $value$plusargs("bad_num=%x", value)) begin + $display("FAILED: Unable to get bad hex (x) value."); + passed = 1'b0; + end + if (value !== 'bx) begin + $display("FAILED: expected bad hex (x) value 'bx, got %d", + value); + passed = 1'b0; + end + + // Look for a decimal value. + if (! $value$plusargs("dec=%d", value)) begin + $display("FAILED: Unable to get decimal value."); + passed = 1'b0; + end + if (value !== 'd0123456789) begin + $display("FAILED: expected decimal value 'd0123456789, got %d", + value); + passed = 1'b0; + end + + // Look for a negative decimal value. + if (! $value$plusargs("neg=%d", value)) begin + $display("FAILED: Unable to get negative decimal value."); + passed = 1'b0; + end + if (value !== -100) begin + $display("FAILED: expected decimal value 72'hff...fc0, got %h", + value); + passed = 1'b0; + end + + // Look for a bad decimal value. + if (! $value$plusargs("bad_num=%d", value)) begin + $display("FAILED: Unable to get bad decimal value."); + passed = 1'b0; + end + if (value !== 'bx) begin + $display("FAILED: expected bad decimal value 'bx, got %d", + value); + passed = 1'b0; + end + + // Look for a decimal "x" value. + if (! $value$plusargs("dec_x=%d", value)) begin + $display("FAILED: Unable to get decimal \"x\" value."); + passed = 1'b0; + end + if (value !== 'dx) begin + $display("FAILED: expected decimal value 'dx, got %d", + value); + passed = 1'b0; + end + + // Look for a decimal "z" value. + if (! $value$plusargs("dec_z=%d", value)) begin + $display("FAILED: Unable to get decimal \"z\" value."); + passed = 1'b0; + end + if (value !== 'dz) begin + $display("FAILED: expected decimal value 'dz, got %d", + value); + passed = 1'b0; + end + + // Look for a real value. + if (! $value$plusargs("real=%f", rval)) begin + $display("FAILED: Unable to get real value."); + passed = 1'b0; + end + if (rval != 12.3456789) begin + $display("FAILED: expected real value 12.3456789, got %f", + rval); + passed = 1'b0; + end + + // Look for a negative real value. + if (! $value$plusargs("neg_real=%f", rval)) begin + $display("FAILED: Unable to get a negative real value."); + passed = 1'b0; + end + if (rval != -23456.0) begin + $display("FAILED: expected negative real value -23456.0, got %f", + rval); + passed = 1'b0; + end + + // Look for an infinite real value. + if (! $value$plusargs("real_inf=%f", rval)) begin + $display("FAILED: Unable to get infinite real value."); + passed = 1'b0; + end + if (rval != 1.0/0.0) begin + $display("FAILED: expected infinite real value Inf, got %f", + rval); + passed = 1'b0; + end + + // Look for a bad real value. + if (! $value$plusargs("bad_num=%f", rval)) begin + $display("FAILED: Unable to get bad real value."); + passed = 1'b0; + end + if (rval != 0.0) begin + $display("FAILED: expected bad real value 0.0, got %f", + rval); + passed = 1'b0; + end + + // Look for a warning real value. + if (! $value$plusargs("warn_real=%f", rval)) begin + $display("FAILED: Unable to get warning real value."); + passed = 1'b0; + end + if (rval != 9.825) begin + $display("FAILED: expected warning real value 9.825, got %f", + rval); + passed = 1'b0; + end + + // Put a decimal value into a real based value. + if (! $value$plusargs("dec=%d", rval)) begin + $display("FAILED: Unable to get decimal (real) value."); + passed = 1'b0; + end + if (rval != 123456789.0) begin + $display("FAILED: expected decimal as real value 12...89.0, got %f", + rval); + passed = 1'b0; + end + + // Put a negative decimal into a real based value. + if (! $value$plusargs("neg=%d", rval)) begin + $display("FAILED: Unable to get negative decimal (real) value."); + passed = 1'b0; + end + if (rval != -100.0) begin + $display("FAILED: expected decimal as real value -100, got %f", + rval); + passed = 1'b0; + end + + // Put a real value into a bit based value. + if (! $value$plusargs("real=%f", value)) begin + $display("FAILED: Unable to get real (bit) value."); + passed = 1'b0; + end + if (value !== 12) begin + $display("FAILED: expected real as bit value 12, got %d", + value); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2202846a.v b/ivtest/ivltests/pr2202846a.v new file mode 100644 index 000000000..491ff9ff0 --- /dev/null +++ b/ivtest/ivltests/pr2202846a.v @@ -0,0 +1,23 @@ +module test (d, en, g, s, a); + + input [31:2] d; + input en; + output g, s, a; + + reg g, s, a; + reg [31:21] r14; + reg [2:0] r18; + + always @(d or r18 or r14 or en) begin + casex ({d[31:12],r18[2:0],en}) + {20'b1111_1111_0011_????_????, 3'b???, 1'b1} : s = 1'b1; + {20'b1111_1111_0010_????_????, 3'b???, 1'b1} : g = 1'b1; + {{r14[31:21], 9'b0_01??_????}, 3'b???, 1'b?} : a = 1'b1; + {{r14[31:21], 9'b1_????_????}, 3'b???, 1'b?} : a = 1'b1; + endcase + end + + // Other tests check functionality so if this compiles it is fine. + initial $display("PASSED"); + +endmodule diff --git a/ivtest/ivltests/pr2202846b.v b/ivtest/ivltests/pr2202846b.v new file mode 100644 index 000000000..ffcb5f78b --- /dev/null +++ b/ivtest/ivltests/pr2202846b.v @@ -0,0 +1,70 @@ +module top; + reg pass; + reg [5:0] cond; + reg [2:1] expr; + integer result; + + always @(cond or expr) begin + casex (cond) + 6'b01_??10 : result = 1; + {2'b10, 4'b??10} : result = 2; + {expr, 4'b??01} : result = 3; + {expr[2], 5'b0??11} : result = 4; + {expr[2:1], 4'b??11} : result = 5; + {expr, 4'b??00} : result = 6; + default : result = 0; + endcase + end + + initial begin + pass = 1'b1; + + cond = 6'b01_xx10; + #1; + if (result != 1) begin + $display("Failed case expr 1 test, got expr %0d", result); + pass = 1'b0; + end + + cond = 6'b10_zz10; + #1; + if (result != 2) begin + $display("Failed case expr 2 test, got expr %0d", result); + pass = 1'b0; + end + + expr = 2'b1?; + cond = 6'b1x_xx01; + #1; + if (result != 3) begin + $display("Failed case expr 3 test, got expr %0d", result); + pass = 1'b0; + end + + expr = 2'b0z; + cond = 6'b00_xx11; + #1; + if (result != 4) begin + $display("Failed case expr 4 test, got expr %0d", result); + pass = 1'b0; + end + + expr = 2'b?1; + cond = 6'bx1_xx11; + #1; + if (result != 5) begin + $display("Failed case expr 5 test, got expr %0d", result); + pass = 1'b0; + end + + expr = 2'b11; + cond = 6'b11_xx00; + #1; + if (result != 6) begin + $display("Failed case expr 6 test, got expr %0d", result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2202846c.v b/ivtest/ivltests/pr2202846c.v new file mode 100644 index 000000000..bdf47b1fc --- /dev/null +++ b/ivtest/ivltests/pr2202846c.v @@ -0,0 +1,62 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + reg [5:0] cond; + reg [2:1] expr; + integer result; + + always @(cond or expr) begin + casex (cond) + 6'b01_??10 : result = 1; + {2'b10, 4'b??10} : result = 2; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + {expr[1:0], 4'b??01} : result = 3; + expr[11:6] : result = 4; +`else + {expr[1], 1'bx, 4'b??01} : result = 3; + 6'bxxxxxx : result = 4; +`endif + default : result = 0; + endcase + end + + initial begin + pass = 1'b1; + + expr = 2'b10; + cond = 6'b01_xx10; + #1 if (result != 1) begin + $display("Failed case expr 1 test, got expr %0d", result); + pass = 1'b0; + end + + cond = 6'bxx_xxxx; + #1 if (result != 1) begin + $display("Failed case expr 1a test, got expr %0d", result); + pass = 1'b0; + end + + cond = 6'b10_zz10; + #1 if (result != 2) begin + $display("Failed case expr 2 test, got expr %0d", result); + pass = 1'b0; + end + + cond = 6'b0x_zz01; + #1 if (result != 3) begin + $display("Failed case expr 3 test, got expr %0d", result); + pass = 1'b0; + end + + cond = 6'b11_1111; + #1 if (result != 4) begin + $display("Failed case expr 1a test, got expr %0d", result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2208681.v b/ivtest/ivltests/pr2208681.v new file mode 100644 index 000000000..22953e7dc --- /dev/null +++ b/ivtest/ivltests/pr2208681.v @@ -0,0 +1,10 @@ +module top; + reg [31:0] in; + wire [31:0] out = (~in) + 1'b1 + 31'h1234; + + initial begin + in = 'h0; + #1 if (out !== 'h1234) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2215342.v b/ivtest/ivltests/pr2215342.v new file mode 100644 index 000000000..75c40a2c9 --- /dev/null +++ b/ivtest/ivltests/pr2215342.v @@ -0,0 +1,5 @@ +`include "pr2215342_inc.v" // Include a file + +module top; + initial $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/pr2215342_inc.v b/ivtest/ivltests/pr2215342_inc.v new file mode 100644 index 000000000..864694184 --- /dev/null +++ b/ivtest/ivltests/pr2215342_inc.v @@ -0,0 +1,2 @@ +/* Start with a comment to verify that the include comment + * is correct. */ diff --git a/ivtest/ivltests/pr2219441.v b/ivtest/ivltests/pr2219441.v new file mode 100644 index 000000000..89c187bb7 --- /dev/null +++ b/ivtest/ivltests/pr2219441.v @@ -0,0 +1,46 @@ +module top; + reg passed; + reg [1:0] sel; + reg [1:0] A; + wire [1:0] Z; + + parent parent(.sel(sel), .A(A), .Z(Z)); + + initial begin + passed = 1'b1; + sel = 2'b11; + A = 2'b00; + #1 if (Z !== 2'b00) begin + $display("FAILED: selected, expected 2'b00, got %b", Z); + passed = 1'b0; + end + + A = 2'b10; + #1 if (Z !== 2'b10) begin + $display("FAILED: selected, expected 2'b10, got %b", Z); + passed = 1'b0; + end + + A = 2'b01; + #1 if (Z !== 2'b01) begin + $display("FAILED: selected, expected 2'b01, got %b", Z); + passed = 1'b0; + end + + sel = 2'b00; + #1 if (Z !== 2'bzz) begin + $display("FAILED: deselected, expected 2'bzz, got %b", Z); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule + +module parent(input[1:0] sel, input [1:0] A, inout [1:0] Z); + child child[1:0](.sel(sel), .A(A), .Z(Z)); +endmodule + +module child(input sel, input A, inout Z); + assign Z = (sel) ? A : 1'bz; +endmodule diff --git a/ivtest/ivltests/pr2219441b.v b/ivtest/ivltests/pr2219441b.v new file mode 100644 index 000000000..f735bf435 --- /dev/null +++ b/ivtest/ivltests/pr2219441b.v @@ -0,0 +1,59 @@ +module top; + reg passed; + reg [1:0] sel; + reg [1:0] A; + wire Z; + + parent parent(.sel(sel), .A(A), .Z(Z)); + + initial begin + // $monitor("1: %b, 0: %b", parent.child[1].Z, parent.child[0].Z); + passed = 1'b1; + sel = 2'b11; + A = 2'b00; + #1 if (Z !== 1'b0) begin + $display("FAILED: selected both, expected 1'b0, got %b", Z); + passed = 1'b0; + end + + A = 2'b11; + #1 if (Z !== 1'b1) begin + $display("FAILED: selected both, expected 1'b1, got %b", Z); + passed = 1'b0; + end + + A = 2'b10; + #1 if (Z !== 1'bx) begin + $display("FAILED: selected both, expected 1'bx, got %b", Z); + passed = 1'b0; + end + + sel = 2'b00; + #1 if (Z !== 1'bz) begin + $display("FAILED: deselected, expected 1'bz, got %b", Z); + passed = 1'b0; + end + + sel = 2'b10; + #1 if (Z !== 1'b1) begin + $display("FAILED: selected (1), expected 1'b1, got %b", Z); + passed = 1'b0; + end + + sel = 2'b01; + #1 if (Z !== 1'b0) begin + $display("FAILED: selected (0), expected 1'b0, got %b", Z); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule + +module parent(input[1:0] sel, input [1:0] A, inout Z); + child child[1:0](.sel(sel), .A(A), .Z(Z)); +endmodule + +module child(input sel, input A, inout Z); + assign Z = (sel) ? A : 1'bz; +endmodule diff --git a/ivtest/ivltests/pr2224845.v b/ivtest/ivltests/pr2224845.v new file mode 100644 index 000000000..f04ebba4d --- /dev/null +++ b/ivtest/ivltests/pr2224845.v @@ -0,0 +1,30 @@ +`define VUG_PCREL(u, uch) ({ {(uch - 12 - 1 > 0 ? uch - 12 - 1 : 1){u[11]}}, \ + u[10:0], 2'b00 }) + +module t(); + +parameter uch = 16; +parameter u_hossz = 32; +parameter u_prefix = 3; + +reg [u_hossz - u_prefix - 1:0] v_utas; +reg [uch - 1:0] v_cim; +wire [uch - 1:0] v_ugras_ide; + +assign v_ugras_ide = v_cim + `VUG_PCREL(v_utas, uch); + +initial +begin + v_utas = 'h0fff; + v_cim = 'h7; + #1; + + if(v_ugras_ide !== 'h3) + $display("FAILED"); + else + $display("PASSED"); + + $finish; +end + +endmodule diff --git a/ivtest/ivltests/pr2224949.v b/ivtest/ivltests/pr2224949.v new file mode 100644 index 000000000..bf77d526c --- /dev/null +++ b/ivtest/ivltests/pr2224949.v @@ -0,0 +1,30 @@ +module t(); + +wire [63:0] a; +wire [63:0] b; + +assign a = 3; + +am dut(a, b); + +initial +begin + #1; + if(b !== 2) + $display("FAILED"); + else + $display("PASSED"); + $finish; +end +endmodule + +module am( + a, b +); + +input [15:0] a; +output [15:0] b; + +assign b = a ^ 1; + +endmodule diff --git a/ivtest/ivltests/pr2233180.v b/ivtest/ivltests/pr2233180.v new file mode 100644 index 000000000..597c0829e --- /dev/null +++ b/ivtest/ivltests/pr2233180.v @@ -0,0 +1,35 @@ +module bug04_integerDiv; + +reg passed; + +reg signed[31:0] reg0; +reg signed[31:0] reg1; +reg signed[31:0] rquot; +wire signed[31:0] dividend=reg0; +wire signed[31:0] divisor=reg1; +wire signed[31:0] quotient; + +assign quotient= dividend/divisor; + +initial begin + passed = 1'b1; + reg0=32'h76c3625e; + reg1=32'hffffffff; + //BUG here: quotient==32'hxxxxxxxx, should be 32'h893c9da2 + #1 if (quotient !== 32'h893c9da2) begin + $display("Failed: CA division, expected 32'h893c9da2, got %h", + quotient); + passed = 1'b0; + end + + rquot = reg0/reg1; + if (rquot !== 32'h893c9da2) begin + $display("Failed: division, expected 32'h893c9da2, got %h", + rquot); + passed = 1'b0; + end + + if (passed) $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2233180b.v b/ivtest/ivltests/pr2233180b.v new file mode 100644 index 000000000..640ed2f0b --- /dev/null +++ b/ivtest/ivltests/pr2233180b.v @@ -0,0 +1,107 @@ +module top; + reg passed; + + reg signed[31:0] m_one, m_two, zero, one, two; + + // Both argument positive. + reg signed[31:0] rem; + wire signed[31:0] wrem = two / one; + + // First argument negative. + reg signed[31:0] rem1n; + wire signed[31:0] wrem1n = m_two / one; + + // Second argument negative. + reg signed[31:0] rem2n; + wire signed[31:0] wrem2n = two / m_one; + + // Both arguments negative. + reg signed[31:0] rembn; + wire signed[31:0] wrembn = m_two / m_one; + + // Divide by zero. + reg signed[31:0] remd0; + wire signed[31:0] wremd0 = one / zero; + + initial begin + passed = 1'b1; + m_one = 32'hffffffff; + m_two = 32'hfffffffe; + zero = 32'h00000000; + one = 32'h00000001; + two = 32'h00000002; + + #1; + // Both positive. + if (wrem !== 32'h00000002) begin + $display("Failed: CA divide, expected 32'h00...02, got %h", + wrem); + passed = 1'b0; + end + + rem = two / one; + if (rem !== 32'h00000002) begin + $display("Failed: divide, expected 32'h00...02, got %h", + rem); + passed = 1'b0; + end + + // First negative. + if (wrem1n !== 32'hfffffffe) begin + $display("Failed: CA divide (1n), expected 32'hff...fe, got %h", + wrem1n); + passed = 1'b0; + end + + rem1n = m_two / one; + if (rem1n !== 32'hfffffffe) begin + $display("Failed: divide (1n), expected 32'hff...fe, got %h", + rem1n); + passed = 1'b0; + end + + // Second negative. + if (wrem2n !== 32'hfffffffe) begin + $display("Failed: CA divide (2n), expected 32'hff...fe, got %h", + wrem2n); + passed = 1'b0; + end + + rem2n = two / m_one; + if (rem2n !== 32'hfffffffe) begin + $display("Failed: divide (2n), expected 32'hff...fe, got %h", + rem2n); + passed = 1'b0; + end + + // Both negative. + if (wrembn !== 32'h00000002) begin + $display("Failed: CA divide (bn), expected 32'h00...02, got %h", + wrembn); + passed = 1'b0; + end + + rembn = m_two / m_one; + if (rembn !== 32'h00000002) begin + $display("Failed: divide (bn), expected 32'h00...02, got %h", + rembn); + passed = 1'b0; + end + + // Divide by zero. + if (wremd0 !== 32'hxxxxxxxx) begin + $display("Failed: CA divide (d0), expected 32'hxx...xx, got %h", + wremd0); + passed = 1'b0; + end + + remd0 = one / zero; + if (remd0 !== 32'hxxxxxxxx) begin + $display("Failed: divide (d0), expected 32'hxx...xx, got %h", + remd0); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2233180c.v b/ivtest/ivltests/pr2233180c.v new file mode 100644 index 000000000..426444def --- /dev/null +++ b/ivtest/ivltests/pr2233180c.v @@ -0,0 +1,107 @@ +module top; + reg passed; + + reg signed[95:0] m_one, m_two, zero, one, two; + + // Both argument positive. + reg signed[95:0] rem; + wire signed[95:0] wrem = two / one; + + // First argument negative. + reg signed[95:0] rem1n; + wire signed[95:0] wrem1n = m_two / one; + + // Second argument negative. + reg signed[95:0] rem2n; + wire signed[95:0] wrem2n = two / m_one; + + // Both arguments negative. + reg signed[95:0] rembn; + wire signed[95:0] wrembn = m_two / m_one; + + // Divide by zero. + reg signed[95:0] remd0; + wire signed[95:0] wremd0 = one / zero; + + initial begin + passed = 1'b1; + m_one = 96'hffffffffffffffffffffffff; + m_two = 96'hfffffffffffffffffffffffe; + zero = 96'h000000000000000000000000; + one = 96'h000000000000000000000001; + two = 96'h000000000000000000000002; + + #1; + // Both positive. + if (wrem !== 96'h000000000000000000000002) begin + $display("Failed: CA divide, expected 96'h00...02, got %h", + wrem); + passed = 1'b0; + end + + rem = two / one; + if (rem !== 96'h000000000000000000000002) begin + $display("Failed: divide, expected 96'h00...02, got %h", + rem); + passed = 1'b0; + end + + // First negative. + if (wrem1n !== 96'hfffffffffffffffffffffffe) begin + $display("Failed: CA divide (1n), expected 96'hff...fe, got %h", + wrem1n); + passed = 1'b0; + end + + rem1n = m_two / one; + if (rem1n !== 96'hfffffffffffffffffffffffe) begin + $display("Failed: divide (1n), expected 96'hff...fe, got %h", + rem1n); + passed = 1'b0; + end + + // Second negative. + if (wrem2n !== 96'hfffffffffffffffffffffffe) begin + $display("Failed: CA divide (2n), expected 96'hff...fe, got %h", + wrem2n); + passed = 1'b0; + end + + rem2n = two / m_one; + if (rem2n !== 96'hfffffffffffffffffffffffe) begin + $display("Failed: divide (2n), expected 96'hff...fe, got %h", + rem2n); + passed = 1'b0; + end + + // Both negative. + if (wrembn !== 96'h000000000000000000000002) begin + $display("Failed: CA divide (bn), expected 96'h00...02, got %h", + wrembn); + passed = 1'b0; + end + + rembn = m_two / m_one; + if (rembn !== 96'h000000000000000000000002) begin + $display("Failed: divide (bn), expected 96'h00...02, got %h", + rembn); + passed = 1'b0; + end + + // Divide by zero. + if (wremd0 !== 96'hxxxxxxxxxxxxxxxxxxxxxxxx) begin + $display("Failed: CA divide (d0), expected 96'hxx...xx, got %h", + wremd0); + passed = 1'b0; + end + + remd0 = one / zero; + if (remd0 !== 96'hxxxxxxxxxxxxxxxxxxxxxxxx) begin + $display("Failed: divide (d0), expected 96'hxx...xx, got %h", + remd0); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2233192.v b/ivtest/ivltests/pr2233192.v new file mode 100644 index 000000000..666c8f543 --- /dev/null +++ b/ivtest/ivltests/pr2233192.v @@ -0,0 +1,35 @@ +module bug05_integerRem; + +reg passed; + +reg signed[31:0] reg0; +reg signed[31:0] reg1; +reg signed[31:0] rrem; +wire signed[31:0] dividend=reg0; +wire signed[31:0] divisor=reg1; +wire signed[31:0] remainder; + +assign remainder= dividend%divisor; + +initial begin + passed = 1'b1; + reg0=32'hffffffff; + reg1=32'h0d1f0796; + //BUG here: remainder==32'h06b26fdd, should be 32'hffffffff + #1 if (remainder !== 32'hffffffff) begin + $display("Failed: CA remainder, expected 32'hffffffff, got %h", + remainder); + passed = 1'b0; + end + + rrem = reg0 % reg1; + #1 if (rrem !== 32'hffffffff) begin + $display("Failed: remainder, expected 32'hffffffff, got %h", + rrem); + passed = 1'b0; + end + + if (passed) $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2233192b.v b/ivtest/ivltests/pr2233192b.v new file mode 100644 index 000000000..f6b5b3259 --- /dev/null +++ b/ivtest/ivltests/pr2233192b.v @@ -0,0 +1,107 @@ +module top; + reg passed; + + reg signed[31:0] m_one, m_two, zero, one, two; + + // Both argument positive. + reg signed[31:0] rem; + wire signed[31:0] wrem = one % two; + + // First argument negative. + reg signed[31:0] rem1n; + wire signed[31:0] wrem1n = m_one % two; + + // Second argument negative. + reg signed[31:0] rem2n; + wire signed[31:0] wrem2n = one % m_two; + + // Both arguments negative. + reg signed[31:0] rembn; + wire signed[31:0] wrembn = m_one % m_two; + + // Divide by zero. + reg signed[31:0] remd0; + wire signed[31:0] wremd0 = one % zero; + + initial begin + passed = 1'b1; + m_one = 32'hffffffff; + m_two = 32'hfffffffe; + zero = 32'h00000000; + one = 32'h00000001; + two = 32'h00000002; + + #1; + // Both positive. + if (wrem !== 32'h00000001) begin + $display("Failed: CA remainder, expected 32'h00...01, got %h", + wrem); + passed = 1'b0; + end + + rem = one % two; + if (rem !== 32'h00000001) begin + $display("Failed: remainder, expected 32'h00...01, got %h", + rem); + passed = 1'b0; + end + + // First negative. + if (wrem1n !== 32'hffffffff) begin + $display("Failed: CA remainder (1n), expected 32'hff...ff, got %h", + wrem1n); + passed = 1'b0; + end + + rem1n = m_one % two; + if (rem1n !== 32'hffffffff) begin + $display("Failed: remainder (1n), expected 32'hff...ff, got %h", + rem1n); + passed = 1'b0; + end + + // Second negative. + if (wrem2n !== 32'h00000001) begin + $display("Failed: CA remainder (2n), expected 32'h00...01, got %h", + wrem2n); + passed = 1'b0; + end + + rem2n = one % m_two; + if (rem2n !== 32'h00000001) begin + $display("Failed: remainder (2n), expected 32'h00...01, got %h", + rem2n); + passed = 1'b0; + end + + // Both negative. + if (wrembn !== 32'hffffffff) begin + $display("Failed: CA remainder (bn), expected 32'hff...ff, got %h", + wrembn); + passed = 1'b0; + end + + rembn = m_one % m_two; + if (rembn !== 32'hffffffff) begin + $display("Failed: remainder (bn), expected 32'hff...ff, got %h", + rembn); + passed = 1'b0; + end + + // Divide by zero. + if (wremd0 !== 32'hxxxxxxxx) begin + $display("Failed: CA remainder (d0), expected 32'hxx...xx, got %h", + wremd0); + passed = 1'b0; + end + + remd0 = one % zero; + if (remd0 !== 32'hxxxxxxxx) begin + $display("Failed: remainder (d0), expected 32'hxx...xx, got %h", + remd0); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2233192c.v b/ivtest/ivltests/pr2233192c.v new file mode 100644 index 000000000..bfdaa2d9a --- /dev/null +++ b/ivtest/ivltests/pr2233192c.v @@ -0,0 +1,107 @@ +module top; + reg passed; + + reg signed[95:0] m_one, m_two, zero, one, two; + + // Both argument positive. + reg signed[95:0] rem; + wire signed[95:0] wrem = one % two; + + // First argument negative. + reg signed[95:0] rem1n; + wire signed[95:0] wrem1n = m_one % two; + + // Second argument negative. + reg signed[95:0] rem2n; + wire signed[95:0] wrem2n = one % m_two; + + // Both arguments negative. + reg signed[95:0] rembn; + wire signed[95:0] wrembn = m_one % m_two; + + // Divide by zero. + reg signed[95:0] remd0; + wire signed[95:0] wremd0 = one % zero; + + initial begin + passed = 1'b1; + m_one = 96'hffffffffffffffffffffffff; + m_two = 96'hfffffffffffffffffffffffe; + zero = 96'h000000000000000000000000; + one = 96'h000000000000000000000001; + two = 96'h000000000000000000000002; + + #1; + // Both positive. + if (wrem !== 96'h000000000000000000000001) begin + $display("Failed: CA remainder, expected 96'h00...01, got %h", + wrem); + passed = 1'b0; + end + + rem = one % two; + if (rem !== 96'h000000000000000000000001) begin + $display("Failed: remainder, expected 96'h00...01, got %h", + rem); + passed = 1'b0; + end + + // First negative. + if (wrem1n !== 96'hffffffffffffffffffffffff) begin + $display("Failed: CA remainder (1n), expected 96'hff...ff, got %h", + wrem1n); + passed = 1'b0; + end + + rem1n = m_one % two; + if (rem1n !== 96'hffffffffffffffffffffffff) begin + $display("Failed: remainder (1n), expected 96'hff...ff, got %h", + rem1n); + passed = 1'b0; + end + + // Second negative. + if (wrem2n !== 96'h000000000000000000000001) begin + $display("Failed: CA remainder (2n), expected 96'h00...01, got %h", + wrem2n); + passed = 1'b0; + end + + rem2n = one % m_two; + if (rem2n !== 96'h000000000000000000000001) begin + $display("Failed: remainder (2n), expected 96'h00...01, got %h", + rem2n); + passed = 1'b0; + end + + // Both negative. + if (wrembn !== 96'hffffffffffffffffffffffff) begin + $display("Failed: CA remainder (bn), expected 96'hff...ff, got %h", + wrembn); + passed = 1'b0; + end + + rembn = m_one % m_two; + if (rembn !== 96'hffffffffffffffffffffffff) begin + $display("Failed: remainder (bn), expected 96'hff...ff, got %h", + rembn); + passed = 1'b0; + end + + // Divide by zero. + if (wremd0 !== 96'hxxxxxxxxxxxxxxxxxxxxxxxx) begin + $display("Failed: CA remainder (d0), expected 96'hxx...xx, got %h", + wremd0); + passed = 1'b0; + end + + remd0 = one % zero; + if (remd0 !== 96'hxxxxxxxxxxxxxxxxxxxxxxxx) begin + $display("Failed: remainder (d0), expected 96'hxx...xx, got %h", + remd0); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr224.v b/ivtest/ivltests/pr224.v new file mode 100644 index 000000000..c678a5918 --- /dev/null +++ b/ivtest/ivltests/pr224.v @@ -0,0 +1,37 @@ +// Extracted from PR#224 + +module test; + + reg clk; + reg [3:0] ack; + + task first; + input [1:0] p; + begin + @(posedge clk); $display("got posedge clk"); +`ifdef LINE_A +//A: line below compiles under XL/NC - iverilog complains + @(posedge ack[p]); $display("got posedge ack[p]"); +`else +//B: line below core dumps under vvp - OK under vvm + @(posedge ack); $display("got posedge ack"); +`endif + @(posedge clk); $display("got posedge clk"); + $display("PASSED"); + $finish; + end + endtask + + initial #5 first(1); + + initial + begin + ack <= 0; clk <= 0; + #10 clk <= 1; + #10 ack <= 3; clk <= 0; + #10 clk <= 1; + #10 $display("FAILED"); + $finish; + end + +endmodule // test diff --git a/ivtest/ivltests/pr2248925.v b/ivtest/ivltests/pr2248925.v new file mode 100644 index 000000000..4bf15ecfb --- /dev/null +++ b/ivtest/ivltests/pr2248925.v @@ -0,0 +1,10 @@ +module bug(); + +time t1; + +initial begin + t1 = 1000; + $display("%0d", t1 + 1000 - 500); +end + +endmodule diff --git a/ivtest/ivltests/pr224a.v b/ivtest/ivltests/pr224a.v new file mode 100644 index 000000000..a52fa4e18 --- /dev/null +++ b/ivtest/ivltests/pr224a.v @@ -0,0 +1,2 @@ +`define LINE_A +`include "ivltests/pr224.v" diff --git a/ivtest/ivltests/pr2251119.v b/ivtest/ivltests/pr2251119.v new file mode 100644 index 000000000..37f6b7c82 --- /dev/null +++ b/ivtest/ivltests/pr2251119.v @@ -0,0 +1,15 @@ +module bug(); + +real t1; +integer t2; + +initial begin + t1 = 2000; + t2 = 1000; + if (0.55*t1 < t2) + $display("FAILED: %0d < %0d true branch taken", 0.55*t1, t2); + else + $display("PASSED: %0d < %0d false branch taken", 0.55*t1, t2); +end + +endmodule diff --git a/ivtest/ivltests/pr2257003.v b/ivtest/ivltests/pr2257003.v new file mode 100644 index 000000000..79f63752d --- /dev/null +++ b/ivtest/ivltests/pr2257003.v @@ -0,0 +1,18 @@ +module inner (); + initial + a.dump; +endmodule + +module outer (); + inner i (); + + generate + begin : a + task dump; + begin + $display ("PASSED"); + end + endtask + end + endgenerate +endmodule diff --git a/ivtest/ivltests/pr2257003b.v b/ivtest/ivltests/pr2257003b.v new file mode 100644 index 000000000..a4fed963a --- /dev/null +++ b/ivtest/ivltests/pr2257003b.v @@ -0,0 +1,14 @@ +module test2 (); + + generate + begin : a + reg b; + end + endgenerate + + initial begin + a.b = 1'b1; + if (a.b) $display("PASSED"); + else $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/pr2270035.v b/ivtest/ivltests/pr2270035.v new file mode 100644 index 000000000..b99f61ce0 --- /dev/null +++ b/ivtest/ivltests/pr2270035.v @@ -0,0 +1,11 @@ +module test (); + reg [30:0] a, b; + + initial begin + b = 1; + a = (0 << b); + // $display ("a: %d", a); + if (a !== 31'b0) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2272468.v b/ivtest/ivltests/pr2272468.v new file mode 100644 index 000000000..1c804fde6 --- /dev/null +++ b/ivtest/ivltests/pr2272468.v @@ -0,0 +1,28 @@ +module sub(); + +task task1; + +input [1023:0] a; +input [1023:0] b; + +begin + if (a + b > 1026'd2) $display(1); +end + +endtask + +initial task1(1, 2); + +endmodule + +module top(); + +generate + genvar i; + + for (i = 0; i < 256; i = i + 1) begin:block + sub sub(); + end +endgenerate + +endmodule diff --git a/ivtest/ivltests/pr2276163.v b/ivtest/ivltests/pr2276163.v new file mode 100644 index 000000000..8269361eb --- /dev/null +++ b/ivtest/ivltests/pr2276163.v @@ -0,0 +1,38 @@ +// Adapted from test case submitted by Geoff Blackman + +module pr2276163(); + function automatic integer f1; + input integer in; + f1 = in + 1; + endfunction + + function integer f2; + input integer in; + f2 = in * 2; + endfunction + + integer ret; + initial begin + ret = f1 ( f1 (1) ); + if (ret !== 3) begin + $display("FAILED: expected 3, got %0d", ret); + $finish; + end + ret = f1 ( f2 (2) ); + if (ret !== 5) begin + $display("FAILED: expected 5, got %0d", ret); + $finish; + end + ret = f2 ( f1 (3) ); + if (ret !== 8) begin + $display("FAILED: expected 8, got %0d", ret); + $finish; + end + ret = f2 ( f2 (4) ); + if (ret !== 16) begin + $display("FAILED: expected 16, got %0d", ret); + $finish; + end + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2281479.v b/ivtest/ivltests/pr2281479.v new file mode 100644 index 000000000..8dbee6e8e --- /dev/null +++ b/ivtest/ivltests/pr2281479.v @@ -0,0 +1,42 @@ +module top; + reg passed; + reg[1:0] in; + integer where; + + always @(in) begin + casez(in) + 2'b10: where = 1; + 2'bx?: where = 2; // MSB is X + 2'b??: where = 3; // The same as default. + endcase + end + + initial begin + passed = 1'b1; + + in = 2'b10; + #1 if (where != 1) begin + $display("FAILED 2'b10 case, found case %d", where); + passed = 1'b0; + end + + in = 2'bx0; + #1 if (where != 2) begin + $display("FAILED 2'bx? case (1), found case %d", where); + passed = 1'b0; + end + in = 2'bx1; + #1 if (where != 2) begin + $display("FAILED 2'bx? case (2), found case %d", where); + passed = 1'b0; + end + + in = 2'b00; + #1 if (where != 3) begin + $display("FAILED 2'b?? case, found case %d", where); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2305307.v b/ivtest/ivltests/pr2305307.v new file mode 100644 index 000000000..ab7e84c3b --- /dev/null +++ b/ivtest/ivltests/pr2305307.v @@ -0,0 +1,66 @@ +`begin_keywords "1364-2005" +module top; + reg passed, in, expect, out; + integer lp; + + initial begin + passed = 1'b1; + + for (lp=0; lp < 3 ; lp = lp + 1) begin + case (lp) + 0: {in,expect} = 2'b00; + 1: {in,expect} = 2'b11; + 2: {in,expect} = 2'bzx; + 3: {in,expect} = 2'bxx; + endcase + + // Check the normal reductions. +// These can fail be need a %buf opcode. + out = ∈ + if (out !== expect) begin + $display("FAILED reduction & with input %b, expected %b, got %b", + in, expect, out); + passed = 1'b0; + end + + out = |in; + if (out !== expect) begin + $display("FAILED reduction | with input %b, expected %b, got %b", + in, expect, out); + passed = 1'b0; + end + + out = ^in; + if (out !== expect) begin + $display("FAILED reduction ^ with input %b, expected %b, got %b", + in, expect, out); + passed = 1'b0; + end + + // Check the inverted reductions. + out = ~∈ + if (out !== ~expect) begin + $display("FAILED reduction ~& with input %b, expected %b, got %b", + in, ~expect, out); + passed = 1'b0; + end + + out = ~|in; + if (out !== ~expect) begin + $display("FAILED reduction ~| with input %b, expected %b, got %b", + in, ~expect, out); + passed = 1'b0; + end + + out = ~^in; + if (out !== ~expect) begin + $display("FAILED reduction ~^ with input %b, expected %b, got %b", + in, ~expect, out); + passed = 1'b0; + end + end + + if (passed) $display("PASSED"); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr2305307b.v b/ivtest/ivltests/pr2305307b.v new file mode 100644 index 000000000..3c2036596 --- /dev/null +++ b/ivtest/ivltests/pr2305307b.v @@ -0,0 +1,68 @@ +`begin_keywords "1364-2005" +module top; + reg passed, in, expect; + integer lp; + + wire rand = ∈ + wire ror = |in; + wire rxor = ^in; + wire rnand = ~∈ + wire rnor = ~|in; + wire rxnor = ~^in; + + initial begin + passed = 1'b1; + + for (lp=0; lp < 3 ; lp = lp + 1) begin + case (lp) + 0: {in,expect} = 2'b00; + 1: {in,expect} = 2'b11; + 2: {in,expect} = 2'bzx; + 3: {in,expect} = 2'bxx; + endcase + + #1; + + // Check the normal reductions. + if (rand !== expect) begin + $display("FAILED CA reduction & with input %b, expected %b, got %b", + in, expect, rand); + passed = 1'b0; + end + + if (ror !== expect) begin + $display("FAILED CA reduction | with input %b, expected %b, got %b", + in, expect, ror); + passed = 1'b0; + end + + if (rxor !== expect) begin + $display("FAILED CA reduction ^ with input %b, expected %b, got %b", + in, expect, rxor); + passed = 1'b0; + end + + // Check the inverted reductions. + if (rnand !== ~expect) begin + $display("FAILED CA reduction ~& with input %b, expected %b, got %b", + in, ~expect, rnand); + passed = 1'b0; + end + + if (rnor !== ~expect) begin + $display("FAILED CA reduction ~| with input %b, expected %b, got %b", + in, ~expect, rnor); + passed = 1'b0; + end + + if (rxnor !== ~expect) begin + $display("FAILED CA reduction ~^ with input %b, expected %b, got %b", + in, ~expect, rxnor); + passed = 1'b0; + end + end + + if (passed) $display("PASSED"); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr2305307c.v b/ivtest/ivltests/pr2305307c.v new file mode 100644 index 000000000..83d7c9b73 --- /dev/null +++ b/ivtest/ivltests/pr2305307c.v @@ -0,0 +1,139 @@ +module top; + reg passed; + parameter zero = 1'b0; + parameter one = 1'b1; + parameter highz = 1'bz; + parameter undef = 1'bx; + + initial begin + passed = 1'b1; + + if (&zero !== 1'b0) begin + $display("FAILED const. reduction & with input 1'b0, expected 1'b0, ", + " got %b", &zero); + passed = 1'b0; + end + if (&one !== 1'b1) begin + $display("FAILED const. reduction & with input 1'b1, expected 1'b1, ", + " got %b", &one); + passed = 1'b0; + end + if (&highz !== 1'bx) begin + $display("FAILED const. reduction & with input 1'bz, expected 1'bx, ", + " got %b", &highz); + passed = 1'b0; + end + if (&undef !== 1'bx) begin + $display("FAILED const. reduction & with input 1'bx, expected 1'bx, ", + " got %b", &undef); + passed = 1'b0; + end + + if (|zero !== 1'b0) begin + $display("FAILED const. reduction | with input 1'b0, expected 1'b0, ", + " got %b", |zero); + passed = 1'b0; + end + if (|one !== 1'b1) begin + $display("FAILED const. reduction | with input 1'b1, expected 1'b1, ", + " got %b", |one); + passed = 1'b0; + end + if (|highz !== 1'bx) begin + $display("FAILED const. reduction | with input 1'bz, expected 1'bx, ", + " got %b", |highz); + passed = 1'b0; + end + if (|undef !== 1'bx) begin + $display("FAILED const. reduction | with input 1'bx, expected 1'bx, ", + " got %b", |undef); + passed = 1'b0; + end + + if (^zero !== 1'b0) begin + $display("FAILED const. reduction ^ with input 1'b0, expected 1'b0, ", + " got %b", ^zero); + passed = 1'b0; + end + if (^one !== 1'b1) begin + $display("FAILED const. reduction ^ with input 1'b1, expected 1'b1, ", + " got %b", ^one); + passed = 1'b0; + end + if (^highz !== 1'bx) begin + $display("FAILED const. reduction ^ with input 1'bz, expected 1'bx, ", + " got %b", ^highz); + passed = 1'b0; + end + if (^undef !== 1'bx) begin + $display("FAILED const. reduction ^ with input 1'bx, expected 1'bx, ", + " got %b", ^undef); + passed = 1'b0; + end + + if (~&zero !== 1'b1) begin + $display("FAILED const. reduction ~& with input 1'b0, expected 1'b1, ", + " got %b", ~&zero); + passed = 1'b0; + end + if (~&one !== 1'b0) begin + $display("FAILED const. reduction ~& with input 1'b1, expected 1'b0, ", + " got %b", ~&one); + passed = 1'b0; + end + if (~&highz !== 1'bx) begin + $display("FAILED const. reduction ~& with input 1'bz, expected 1'bx, ", + " got %b", ~&highz); + passed = 1'b0; + end + if (~&undef !== 1'bx) begin + $display("FAILED const. reduction ~& with input 1'bx, expected 1'bx, ", + " got %b", ~&undef); + passed = 1'b0; + end + + if (~|zero !== 1'b1) begin + $display("FAILED const. reduction ~| with input 1'b0, expected 1'b1, ", + " got %b", ~|zero); + passed = 1'b0; + end + if (~|one !== 1'b0) begin + $display("FAILED const. reduction ~| with input 1'b1, expected 1'b0, ", + " got %b", ~|one); + passed = 1'b0; + end + if (~|highz !== 1'bx) begin + $display("FAILED const. reduction ~| with input 1'bz, expected 1'bx, ", + " got %b", ~|highz); + passed = 1'b0; + end + if (~|undef !== 1'bx) begin + $display("FAILED const. reduction ~| with input 1'bx, expected 1'bx, ", + " got %b", ~|undef); + passed = 1'b0; + end + + if (~^zero !== 1'b1) begin + $display("FAILED const. reduction ~^ with input 1'b0, expected 1'b1, ", + " got %b", ~^zero); + passed = 1'b0; + end + if (~^one !== 1'b0) begin + $display("FAILED const. reduction ~^ with input 1'b1, expected 1'b0, ", + " got %b", ~^one); + passed = 1'b0; + end + if (~^highz !== 1'bx) begin + $display("FAILED const. reduction ~^ with input 1'bz, expected 1'bx, ", + " got %b", ~^highz); + passed = 1'b0; + end + if (~^undef !== 1'bx) begin + $display("FAILED const. reduction ~^ with input 1'bx, expected 1'bx, ", + " got %b", ~^undef); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2306259.v b/ivtest/ivltests/pr2306259.v new file mode 100644 index 000000000..4ca142f0b --- /dev/null +++ b/ivtest/ivltests/pr2306259.v @@ -0,0 +1,11 @@ +module test (); + generate + if (1) begin + initial begin : a + integer i; + i=0; + $display("PASSED"); + end + end + endgenerate +endmodule diff --git a/ivtest/ivltests/pr2350934.v b/ivtest/ivltests/pr2350934.v new file mode 100644 index 000000000..d93575979 --- /dev/null +++ b/ivtest/ivltests/pr2350934.v @@ -0,0 +1,45 @@ +module test (); + parameter param = 3; + reg [2:0] dummy; + + initial dummy = block.f(0); + + generate + if (param==1) begin : block + function [2:0] f; + input i; + begin + $display ("if param==1"); + f = param; + end + endfunction + end else if (param==2) begin : block + function [2:0] f; + input i; + begin + $display ("else if param==2"); + f = param; + end + endfunction + end + endgenerate +endmodule + +module top (); + test #(1) a(); + test #(2) b(); + + initial begin + #1 if (a.dummy !== 1) begin + $display("FAILED -- a.dummy = %d", a.dummy); + $finish; + end + if (b.dummy !== 2) begin + $display("FAILED -- b.dummy = %d", b.dummy); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/pr2350934b.v b/ivtest/ivltests/pr2350934b.v new file mode 100644 index 000000000..d535862ce --- /dev/null +++ b/ivtest/ivltests/pr2350934b.v @@ -0,0 +1,62 @@ +module test (); + parameter param = 3; + reg [2:0] dummy; + + initial dummy = block.f(0); + + generate + case (param) + 1, 2: if (param==1) begin : block + function [2:0] f; + input i; + begin + $display ("if param==1"); + f = param; + end + endfunction + end else begin : block + function [2:0] f; + input i; + begin + $display ("else if param==2"); + f = param; + end + endfunction + end + + 4: begin : block + function [2:0] f; + input i; + begin + $display ("if param==4"); + f = param; + end + endfunction // f + end + endcase + endgenerate +endmodule + +module top (); + test #(1) a(); + test #(2) b(); + test #(4) c(); + + initial begin + #1 if (a.dummy !== 1) begin + $display("FAILED -- a.dummy = %d", a.dummy); + $finish; + end + if (b.dummy !== 2) begin + $display("FAILED -- b.dummy = %d", b.dummy); + $finish; + end + if (c.dummy !== 4) begin + $display("FAILED -- c.dummy = %d", c.dummy); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/pr2350988.v b/ivtest/ivltests/pr2350988.v new file mode 100644 index 000000000..963800820 --- /dev/null +++ b/ivtest/ivltests/pr2350988.v @@ -0,0 +1,38 @@ +module test (); + parameter p = 0; + + reg dummy; + initial dummy = block.f(0); + + + + generate case(1) + p==0: + begin : block + function f; + input i; + begin + $display("p == 0: %0s", p==0?"OK":"FAILED"); + if (! (p==0)) $finish; + end + endfunction + end + default: + begin : block + function f; + input i; + begin + $display("default: %0s", p!=0?"OK":"FAILED"); + if (p==0) $finish; + end + endfunction + end + endcase + endgenerate +endmodule + +module top (); + test #(0) a(); + test #(1) b(); + initial #1 $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/pr2352834.v b/ivtest/ivltests/pr2352834.v new file mode 100644 index 000000000..cf1bed68d --- /dev/null +++ b/ivtest/ivltests/pr2352834.v @@ -0,0 +1,26 @@ +module top; + reg pass; + reg [31:0] in2; + integer in1; + reg signed [128:0] res; + + initial begin + pass = 1'b1; + + in1 = -2; in2 = 63; + res = in1 ** in2; + if (res !== -128'sd9223372036854775808) begin + $display("Failed: -2 ** 65, expected -9223372036854775808, got %0d", res); + pass = 1'b0; + end + + in1 = -2; in2 = 65; + res = in1 ** in2; + if (res !== -128'sd36893488147419103232) begin + $display("Failed: -2 ** 65, expected -36893488147419103232, got %0d", res); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2355304.v b/ivtest/ivltests/pr2355304.v new file mode 100644 index 000000000..c54a5a02a --- /dev/null +++ b/ivtest/ivltests/pr2355304.v @@ -0,0 +1,28 @@ +module test (); + parameter t=0; + reg t_not, t_zero; + + generate + if (!t) begin + initial t_not = 1; + end + endgenerate + + generate + if (t==0) begin + initial t_zero = 1; + end + endgenerate + + initial begin + #1 if (t_not !== 1) begin + $display("FAILED -- t_not=%b", t_not); + $finish; + end + if (t_zero !== 1) begin + $display("FAILED -- t_zero=%b", t_zero); + $finish; + end + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2355304b.v b/ivtest/ivltests/pr2355304b.v new file mode 100644 index 000000000..68c385b93 --- /dev/null +++ b/ivtest/ivltests/pr2355304b.v @@ -0,0 +1,12 @@ +module test2 (); + reg [1:0] d; + + always @(posedge |d) begin + $display ("PASSED"); + end + initial begin + d=0; + # 1; + d=6'b01; + end +endmodule diff --git a/ivtest/ivltests/pr2358264.v b/ivtest/ivltests/pr2358264.v new file mode 100644 index 000000000..045d6d190 --- /dev/null +++ b/ivtest/ivltests/pr2358264.v @@ -0,0 +1,37 @@ +module test(); +reg [13:0] a; +reg b; +reg c; + +always @(a or b) +begin + + case ({1'b0,~b,a[3:0]}) + 6'b00_0000 : begin + c = 1'b1; + end + default : begin + c = 1'b0; + end + endcase +end + +initial begin + #1 /* Wait for the always block above to get settled. */; + a = 0; + b = 0; + #1 if (c !== 0) begin + $display("FAILED - a=%b, b=%b, c=%b", a, b, c); + $finish; + end + + b = 1; + #1 if (c !== 1) begin + $display("FAILED - a=%b, b=%b, c=%b", a, b, c); + $finish; + end + + $display("PASSED"); +end // initial begin + +endmodule diff --git a/ivtest/ivltests/pr2358848.v b/ivtest/ivltests/pr2358848.v new file mode 100644 index 000000000..93908e6de --- /dev/null +++ b/ivtest/ivltests/pr2358848.v @@ -0,0 +1,95 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module t(); + reg passed; + parameter ch = 14; + parameter csek2 = 1; + parameter offset = 10/0; + localparam csek = 1 << csek2; + + wire [ch + csek2 - 1:0] cim_k; + wire [csek - 1:0] up1, up2, up3, up4, up5, dwn1, dwn2, dwn3; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + // This checks the always above code. + assign up1 = cim_k[(csek2 + ch)+:csek2]; + // This checks the always above code. + assign up2 = cim_k[(csek2 + ch + 2)+:csek2]; + // This checks the always below code. + assign up3 = cim_k[(csek2 + ch - 17)+:csek2]; + // This checks that -4 goes into three bits not two. + assign up4 = cim_k[(csek2 + ch - 18)+:csek2]; + // This checks that an undef base gives 'bx out. + assign up5 = cim_k[(csek2 + ch - offset)+:csek2]; + + // This checks the always above code. + assign dwn1 = cim_k[(csek2 + ch + 2)-:csek2]; + // This checks the always below code. + assign dwn2 = cim_k[(csek2 + ch - 17)-:csek2]; + // This checks that an undef base gives 'bx out. + assign dwn3 = cim_k[(csek2 + ch - offset)-:csek2]; +`else + assign up1 = 2'b0x; + assign up2 = 2'b0x; + assign up3 = 2'b0x; + assign up4 = 2'b0x; + assign up5 = 2'b0x; + assign dwn1 = 2'b0x; + assign dwn2 = 2'b0x; + assign dwn3 = 2'b0x; +`endif + + initial begin + #1; + passed = 1'b1; + + if (cim_k !== 15'bz) begin + $display("FAILED: cim_k should be 15'bz, got %b", cim_k); + passed = 1'b0; + end + + if (up1 !== 2'b0x) begin + $display("FAILED: up1 should be 2'b0x, got %b", up1); + passed = 1'b0; + end + + if (up2 !== 2'b0x) begin + $display("FAILED: up2 should be 2'b0x, got %b", up2); + passed = 1'b0; + end + + if (up3 !== 2'b0x) begin + $display("FAILED: up3 should be 2'b0x, got %b", up3); + passed = 1'b0; + end + + if (up4 !== 2'b0x) begin + $display("FAILED: up4 should be 2'b0x, got %b", up4); + passed = 1'b0; + end + + if (up5 !== 2'b0x) begin + $display("FAILED: up5 should be 2'b0x, got %b", up5); + passed = 1'b0; + end + + if (dwn1 !== 2'b0x) begin + $display("FAILED: dwn1 should be 2'b0x, got %b", dwn1); + passed = 1'b0; + end + + if (dwn2 !== 2'b0x) begin + $display("FAILED: dwn2 should be 2'b0x, got %b", dwn2); + passed = 1'b0; + end + + if (dwn3 !== 2'b0x) begin + $display("FAILED: dwn3 should be 2'b0x, got %b", dwn3); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2395378a.v b/ivtest/ivltests/pr2395378a.v new file mode 100644 index 000000000..9e698546e --- /dev/null +++ b/ivtest/ivltests/pr2395378a.v @@ -0,0 +1,3 @@ +module top; + buf(strong0, highz1) #1 sclbuf0(iscl); +endmodule diff --git a/ivtest/ivltests/pr2395378b.v b/ivtest/ivltests/pr2395378b.v new file mode 100644 index 000000000..6958faa86 --- /dev/null +++ b/ivtest/ivltests/pr2395378b.v @@ -0,0 +1,3 @@ +module top; + buf sclbuf0(); +endmodule diff --git a/ivtest/ivltests/pr2395378c.v b/ivtest/ivltests/pr2395378c.v new file mode 100644 index 000000000..a4ff7ba71 --- /dev/null +++ b/ivtest/ivltests/pr2395378c.v @@ -0,0 +1,3 @@ +module top; + not(strong0, highz1) #1 sclbuf0(iscl); +endmodule diff --git a/ivtest/ivltests/pr2395835.v b/ivtest/ivltests/pr2395835.v new file mode 100644 index 000000000..9a173d0b1 --- /dev/null +++ b/ivtest/ivltests/pr2395835.v @@ -0,0 +1,28 @@ +module t(); + + reg passed = 1; + + task abc; + input [7:0] a; + + begin + if(a == 1) + $display("OK"); + else + begin $display("FAILURE"); passed = 0; end + end + endtask + + reg [7:0] b; + + initial + begin + #1 ; + abc(500 >> 8); + b = 500 >> 8; + abc(b); + + if (passed) + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2425055a.v b/ivtest/ivltests/pr2425055a.v new file mode 100644 index 000000000..74b956af6 --- /dev/null +++ b/ivtest/ivltests/pr2425055a.v @@ -0,0 +1,14 @@ +module main; + + reg [31:0] a, b, c; + + initial begin + a = 1; + b = 1; + b[2] = 1'bx; + c = a << b; + //$display( "a: %b, b: %b, c: %b", a, b, c ); + if (c != 32'bx) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2425055b.v b/ivtest/ivltests/pr2425055b.v new file mode 100644 index 000000000..0f7908634 --- /dev/null +++ b/ivtest/ivltests/pr2425055b.v @@ -0,0 +1,44 @@ +module top; + reg pass; + reg [1:0] in, shift, result; + reg signed [1:0] ins; + + initial begin + pass = 1'b1; + in = 2'b01; + shift = 2'bx1; + + result = in << shift; + if (result !== 2'bxx) begin + $display("Failed <<, expected 2'bxx, got %b", result); + pass = 1'b0; + end + + result = in <<< shift; + if (result !== 2'bxx) begin + $display("Failed <<<, expected 2'bxx, got %b", result); + pass = 1'b0; + end + + result = in >> shift; + if (result !== 2'bxx) begin + $display("Failed >>, expected 2'bxx, got %b", result); + pass = 1'b0; + end + + result = in >>> shift; + if (result !== 2'bxx) begin + $display("Failed >>>, expected 2'bxx, got %b", result); + pass = 1'b0; + end + + ins = 2'b10; + result = ins >>> shift; + if (result !== 2'bxx) begin + $display("Failed >>> (signed), expected 2'bxx, got %b", result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2425055c.v b/ivtest/ivltests/pr2425055c.v new file mode 100644 index 000000000..fa72272f4 --- /dev/null +++ b/ivtest/ivltests/pr2425055c.v @@ -0,0 +1,46 @@ +module top; + reg pass; + reg [1:0] in, shift, result; + reg signed [1:0] ins; + + wire [1:0] ls = in << shift; + wire [1:0] als = in <<< shift; + wire [1:0] rs = in >> shift; + wire [1:0] rs2 = in >>> shift; + wire [1:0] ars = ins >> shift; + + initial begin + pass = 1'b1; + in = 2'b01; + ins = 2'b10; + shift = 2'bx1; + #1 + + if (ls !== 2'bxx) begin + $display("Failed << (CA), expected 2'bxx, got %b", ls); + pass = 1'b0; + end + + if (als !== 2'bxx) begin + $display("Failed <<< (CA), expected 2'bxx, got %b", als); + pass = 1'b0; + end + + if (rs !== 2'bxx) begin + $display("Failed >> (CA), expected 2'bxx, got %b", rs); + pass = 1'b0; + end + + if (rs2 !== 2'bxx) begin + $display("Failed >>> (CA), expected 2'bxx, got %b", rs2); + pass = 1'b0; + end + + if (ars !== 2'bxx) begin + $display("Failed >>> (signed, CA), expected 2'bxx, got %b", ars); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2428890.v b/ivtest/ivltests/pr2428890.v new file mode 100644 index 000000000..be823b111 --- /dev/null +++ b/ivtest/ivltests/pr2428890.v @@ -0,0 +1,22 @@ +module top; + lower #(0, 0, 1) dut(); +endmodule + +module lower; + parameter one = 0; // This should be 'sd0 + parameter two = 0; // This should be 'sd0 + parameter three = 0; // This should be 'sd1 + parameter local1 = one - two; // This should be 'sd0 + // This line is not working correctly. + // The 1 is not considered signed! + // local1 + 1 is giving 'd1 not 'sd1. + parameter local2 = local1+1-three; // This should be 'sd0 + // Even this fails. +// parameter local2 = local1+'sd1-three; // This should be 'sd0 + + initial begin + // This should be 2 < -1. + if (2 < local2-1) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2428890b.v b/ivtest/ivltests/pr2428890b.v new file mode 100644 index 000000000..24cd98fd4 --- /dev/null +++ b/ivtest/ivltests/pr2428890b.v @@ -0,0 +1,35 @@ +module top; + lower #(1, 2, 3) dut(); +endmodule + +module lower; + parameter one = 1; // This should be 'sd1 + parameter two = 2; // This should be 'sd2 + parameter three = 0; // This should be 'sd3 + parameter local1 = one - two; // This should be -'sd1 + + parameter local_lt0 = local1 < 0; // This should be 'd1 + parameter local_le0 = local1 <= 0; // This should be 'd1 + parameter local_gt0 = local1 > 0; // This should be 'd0 + parameter local_ge0 = local1 >= 0; // This should be 'd0 + parameter local_0lt = 0 < local1; // This should be 'd1 + parameter local_0le = 0 <= local1; // This should be 'd1 + parameter local_0gt = 0 > local1; // This should be 'd0 + parameter local_0ge = 0 >= local1; // This should be 'd0 + + reg err; + initial begin + err = 0; + if (!local_lt0) err = 1; + if (!local_le0) err = 1; + if ( local_gt0) err = 1; + if ( local_ge0) err = 1; + if ( local_0lt) err = 1; + if ( local_0le) err = 1; + if (!local_0gt) err = 1; + if (!local_0ge) err = 1; + + if (err == 0) $display("PASSED"); + else $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/pr2428890c.v b/ivtest/ivltests/pr2428890c.v new file mode 100644 index 000000000..2858d3daf --- /dev/null +++ b/ivtest/ivltests/pr2428890c.v @@ -0,0 +1,29 @@ +module top; + lower #(1, 2, 3) dut(); +endmodule + +module lower; + parameter one = 1; // This should be 'sd1 + parameter two = 2; // This should be 'sd2 + parameter three = 0; // This should be 'sd3 + parameter local1 = one - two; // This should be -'sd1 + + parameter local_t1 = local1 * 1; // This should be -'d1 + parameter local_d1 = local1 / 1; // This should be -'d1 + + reg err; + initial begin + err = 0; + if (local_t1 !== -1) err = 1; + if (local_t1 > 0) err = 1; + if (local_d1 !== -1) err = 1; + if (local_d1 > 0) err = 1; + + if (! $is_signed(local_t1)) err = 1; + if (! $is_signed(local_d1)) err = 1; + if (! $is_signed(local1)) err = 1; + + if (err == 0) $display("PASSED"); + else $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/pr243.v b/ivtest/ivltests/pr243.v new file mode 100644 index 000000000..30b12d30e --- /dev/null +++ b/ivtest/ivltests/pr243.v @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2001 Uwe Bonnes + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +`define ADC_DATA_OFFSET 5 +`define ADC_CHANELS 8*48 +//`define ADC_CHANELS 348 + +module mymod (out1,out2,state,reset); + + input [8:0] state; + input reset; + output out1,out2; + assign out1 = (state > `ADC_DATA_OFFSET) ? 1 : 0; + assign out2 = (state > `ADC_CHANELS + `ADC_DATA_OFFSET +1)|| (reset); + +endmodule // mymod + +module t; + reg [8:0] state; + reg reset; + wire out1,out2; + + mymod m1 (out1,out2,state,reset); + + initial + begin + //$timeformat(-9,0,"ns",5); + $display(" TIME:state:out1:out2"); + $monitor("%7t:%5d:%3d:%3d",$time,state,out1,out2); + state =0; + reset = 0; + #10 + reset=1; + #20 + reset=0; + #5110 + $finish(0); + end + always + begin + #10 + if (reset) + state = 0; + else + state=state+1; + end +endmodule // t diff --git a/ivtest/ivltests/pr2434688.v b/ivtest/ivltests/pr2434688.v new file mode 100644 index 000000000..7c8daf297 --- /dev/null +++ b/ivtest/ivltests/pr2434688.v @@ -0,0 +1,78 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + reg [7:0] in; + reg [3:0] out; + + initial begin + pass = 1'b1; + in = 8'b10100101; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out = in[7:'dx]; +`else + out = 4'bxxxx; +`endif + if (out !== 4'bxxxx) begin + $display("FAILED: part select LSB is X, expected 4'bxxxx, got %b", out); + pass = 1'b0; + end + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out = in['dx:0]; +`else + out = 4'bxxxx; +`endif + if (out !== 4'bxxxx) begin + $display("FAILED: part select MSB is X, expected 4'bxxxx, got %b", out); + pass = 1'b0; + end + + out = 4'b0000; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out[0] = in['dx]; +`else + out[0] = 1'bx; +`endif + if (out !== 4'b000x) begin + $display("FAILED: bit select is X, expected 4'b000x, got %b", out); + pass = 1'b0; + end + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out = in[7:'dz]; +`else + out = 4'bxxxx; +`endif + if (out !== 4'bxxxx) begin + $display("FAILED: part select LSB is Z, expected 4'bxxxx, got %b", out); + pass = 1'b0; + end + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out = in['dz:0]; +`else + out = 4'bxxxx; +`endif + if (out !== 4'bxxxx) begin + $display("FAILED: part select MSB is Z, expected 4'bxxxx, got %b", out); + pass = 1'b0; + end + + out = 4'b0000; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out[0] = in['dz]; +`else + out[0] = 1'bx; +`endif + if (out !== 4'b000x) begin + $display("FAILED: bit select is Z, expected 4'b000x, got %b", out); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2434688b.v b/ivtest/ivltests/pr2434688b.v new file mode 100644 index 000000000..c14b66d47 --- /dev/null +++ b/ivtest/ivltests/pr2434688b.v @@ -0,0 +1,77 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + parameter [7:0] in = 8'b10100101; + reg [3:0] out; + + initial begin + pass = 1'b1; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out = in[7:'dx]; +`else + out = 4'bxxxx; +`endif + if (out !== 4'bxxxx) begin + $display("FAILED: part select LSB is X, expected 4'bxxxx, got %b", out); + pass = 1'b0; + end + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out = in['dx:0]; +`else + out = 4'bxxxx; +`endif + if (out !== 4'bxxxx) begin + $display("FAILED: part select MSB is X, expected 4'bxxxx, got %b", out); + pass = 1'b0; + end + + out = 4'b0000; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out[0] = in['dx]; +`else + out[0] = 1'bx; +`endif + if (out !== 4'b000x) begin + $display("FAILED: bit select is X, expected 4'b000x, got %b", out); + pass = 1'b0; + end + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out = in[7:'dz]; +`else + out = 4'bxxxx; +`endif + if (out !== 4'bxxxx) begin + $display("FAILED: part select LSB is Z, expected 4'bxxxx, got %b", out); + pass = 1'b0; + end + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out = in['dz:0]; +`else + out = 4'bxxxx; +`endif + if (out !== 4'bxxxx) begin + $display("FAILED: part select MSB is Z, expected 4'bxxxx, got %b", out); + pass = 1'b0; + end + + out = 4'b0000; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + out[0] = in['dz]; +`else + out[0] = 1'bx; +`endif + if (out !== 4'b000x) begin + $display("FAILED: bit select is Z, expected 4'b000x, got %b", out); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr243_std.v b/ivtest/ivltests/pr243_std.v new file mode 100644 index 000000000..4f91249e3 --- /dev/null +++ b/ivtest/ivltests/pr243_std.v @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2001 Uwe Bonnes + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +`define ADC_DATA_OFFSET 5 +`define ADC_CHANELS 8*48 +//`define ADC_CHANELS 348 + +module mymod (out1,out2,state,reset); + + input [8:0] state; + input reset; + output out1,out2; + assign out1 = (state > `ADC_DATA_OFFSET) ? 1 : 0; + assign out2 = (state > `ADC_CHANELS + `ADC_DATA_OFFSET +1)|| (reset); + +endmodule // mymod + +module t; + reg [8:0] state; + reg reset; + wire out1,out2; + + mymod m1 (out1,out2,state,reset); + + initial + begin + //$timeformat(-9,0,"ns",5); + $display(" TIME:state:out1:out2"); + $monitor("%t:%5d:%4d:%4d",$time,state,out1,out2); + state =0; + reset = 0; + #10 + reset=1; + #20 + reset=0; + #5110 + $finish; + end + always + begin + #10 + if (reset) + state = 0; + else + state=state+1; + end +endmodule // t diff --git a/ivtest/ivltests/pr245.v b/ivtest/ivltests/pr245.v new file mode 100644 index 000000000..2100b0a33 --- /dev/null +++ b/ivtest/ivltests/pr245.v @@ -0,0 +1,24 @@ +/* + * See pr245 in the ivtest test suite. + */ + +`timescale 1ns/1ns + +module t; + wire [11:0] iodata; + integer i; + + + initial + begin + $timeformat(-9,0,"ns",5); + $display(" TIME:IOD"); + $monitor( "%7t:%3x", + $time,iodata); + #0 + force iodata =0; + for (i=0; i<512;i=i+1) + #10 + force iodata =i; + end // initial begin +endmodule // t diff --git a/ivtest/ivltests/pr2450244.v b/ivtest/ivltests/pr2450244.v new file mode 100644 index 000000000..be8248192 --- /dev/null +++ b/ivtest/ivltests/pr2450244.v @@ -0,0 +1,39 @@ +module main; + parameter [15:0] a = 16'h8421; + reg [3:0] b, c; + reg pass; + + always @* begin + b = a[c+:4]; +// $display($time, " c: %d, b: %h", c, b); + end + + initial begin + pass = 1'b1; + c = 0; + #1 if (b !== 4'd1) begin + $display("FAILED: c = 0, expected 1, got %0d", b); + pass = 1'b0; + end + + #9 c = 4; + #1 if (b !== 4'd2) begin + $display("FAILED: c = 4, expected 2, got %0d", b); + pass = 1'b0; + end + + #9 c = 8; + #1 if (b !== 4'd4) begin + $display("FAILED: c = 8, expected 4, got %0d", b); + pass = 1'b0; + end + + #9 c = 12; + #1 if (b !== 4'd8) begin + $display("FAILED: c = 12, expected 8, got %0d", b); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2453002.v b/ivtest/ivltests/pr2453002.v new file mode 100644 index 000000000..230b8b383 --- /dev/null +++ b/ivtest/ivltests/pr2453002.v @@ -0,0 +1,37 @@ +module top; + reg pass = 1'b1; + + parameter one = 1'b1; + parameter zero = 1'b0; + parameter udef = 1'bx; + + real rl1 = one ? 4 : 4.5; // 4.0 + real rl2 = zero ? 4.0 : 5; // 5.0 + real rl3 = udef ? 6 : 6.0; // 6.0 + real rl4 = udef ? 7 : 7; // 7.0 + + initial begin + #1; + if (rl1 != 4.0) begin + $display("FAILED: real expression one, expected 4.0, got %f", rl1); + pass = 1'b0; + end + + if (rl2 != 5.0) begin + $display("FAILED: real expression two, expected 5.0, got %f)", rl2); + pass = 1'b0; + end + + if (rl3 != 6.0) begin + $display("FAILED: real expression three, expected 6.0, got %f", rl3); + pass = 1'b0; + end + + if (rl4 != 7.0) begin + $display("FAILED: real expression four, expected 7.0, got %f", rl4); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2453002b.v b/ivtest/ivltests/pr2453002b.v new file mode 100644 index 000000000..3a405b0aa --- /dev/null +++ b/ivtest/ivltests/pr2453002b.v @@ -0,0 +1,42 @@ +module top; + reg pass = 1'b1; + + parameter one = 1'b1; + parameter zero = 1'b0; + parameter udef = 1'bx; + + reg [2:0] four = 3'd4; + reg [2:0] five = 3'd5; + reg [2:0] six = 3'd6; + reg [2:0] seven = 3'd7; + + wire real rl1 = one ? four : 4.5; // 4.0 + wire real rl2 = zero ? 4.0 : five; // 5.0 + wire real rl3 = udef ? six : 6.0; // 6.0 + wire real rl4 = udef ? seven : seven; // 7.0 + + initial begin + #1; + if (rl1 != 4.0) begin + $display("FAILED: real expression one, expected 4.0, got %f", rl1); + pass = 1'b0; + end + + if (rl2 != 5.0) begin + $display("FAILED: real expression two, expected 4.0, got %f", rl2); + pass = 1'b0; + end + + if (rl3 != 6.0) begin + $display("FAILED: real expression three, expected 4.0, got %f", rl3); + pass = 1'b0; + end + + if (rl4 != 7.0) begin + $display("FAILED: real expression four, expected 7.0, got %f", rl4); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2456943.v b/ivtest/ivltests/pr2456943.v new file mode 100644 index 000000000..c49213feb --- /dev/null +++ b/ivtest/ivltests/pr2456943.v @@ -0,0 +1,8 @@ +module top; + wire real test; + + initial begin + if (test != 0.0) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2459681.v b/ivtest/ivltests/pr2459681.v new file mode 100644 index 000000000..c25428f96 --- /dev/null +++ b/ivtest/ivltests/pr2459681.v @@ -0,0 +1,16 @@ +module bug(); + +reg [7:0] memory[1:0]; + +reg index; + +initial begin + index = 0; + memory[~index] = 1; + if (memory[1] === 1) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/pr245_std.v b/ivtest/ivltests/pr245_std.v new file mode 100644 index 000000000..276cf8a41 --- /dev/null +++ b/ivtest/ivltests/pr245_std.v @@ -0,0 +1,24 @@ +/* + * See pr245 in the ivtest test suite. + */ + +`timescale 1ns/1ns + +module t; + wire [11:0] iodata; + integer i; + + + initial + begin + $timeformat(-9,0,"ns",7); + $display(" TIME:IOD"); + $monitor( "%t:%3x", + $time,iodata); + #0 + force iodata =0; + for (i=0; i<512;i=i+1) + #10 + force iodata =i; + end // initial begin +endmodule // t diff --git a/ivtest/ivltests/pr2470181a.v b/ivtest/ivltests/pr2470181a.v new file mode 100644 index 000000000..8b5701d70 --- /dev/null +++ b/ivtest/ivltests/pr2470181a.v @@ -0,0 +1,39 @@ +module main; + reg a, b, reset, pass; + + always @* + a = b | reset; + + always @* begin + b = 1'b0; + #2; + b = a; + end + + initial begin + pass = 1'b1; + reset = 1'b1; + #1 if(b !== 1'b0) begin + $display("FAILED initial zero for 1'b1, got %b", b); + pass = 1'b0; + end + #2 if(b !== 1'b1) begin + $display("FAILED initial set to 1'b1, got %b", b); + pass = 1'b0; + end + + // Since b is already 1'b1 reset can not change a to zero. + reset = 1'b0; + #1 if(b !== 1'b1) begin + $display("FAILED block of initial zero for 1'b0, got %b", b); + pass = 1'b0; + end + #2 if(b !== 1'b1) begin + $display("FAILED block of initial set to 1'b0, got %b", b); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr2470181b.v b/ivtest/ivltests/pr2470181b.v new file mode 100644 index 000000000..d2fd3ec16 --- /dev/null +++ b/ivtest/ivltests/pr2470181b.v @@ -0,0 +1,40 @@ +`begin_keywords "1364-2005" +module main; + reg pass; + reg a, b; + + always @* begin + b = a; + #2; + b = 1'b0; + end + + task check_bit; + input bit; + + begin + a = bit; + #1 if (a !== b) begin + $display("FAILED, expected %b, got %b", a, b); + pass = 1'b0; + end + #2 if (b !== 1'b0) begin + $display("FAILED return to zero, got %b", b); + pass = 1'b0; + end + end + endtask + + initial begin + pass = 1'b1; + + check_bit(1'b1); + check_bit(1'b0); + check_bit(1'bx); + check_bit(1'bz); + + if (pass) $display("PASSED"); + end + +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr2476430.v b/ivtest/ivltests/pr2476430.v new file mode 100644 index 000000000..93134c92e --- /dev/null +++ b/ivtest/ivltests/pr2476430.v @@ -0,0 +1,310 @@ +`timescale 1ns/10ps +module top; + reg pass; + reg [60*8-1:0] str, cmp; + reg [7:0] bval; + reg [15:0] oval, hval; + integer dval; + time tval; + real rval; + + initial begin + pass = 1'b1; + + // Check the %b conversion. + bval = 8'b01101001; + cmp = "1101001"; + $sformat(str, "%0b", bval); + if (str != cmp) begin + $display("FAILED: %%0b, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "0000000001101001"; + $sformat(str, "%016b", bval); + if (str != cmp) begin + $display("FAILED: %%016b, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "1101001 "; + $sformat(str, "%-016b", bval); + if (str != cmp) begin + $display("FAILED: %%-016b, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + // Check the %o conversion. + oval = 16'o01234; + cmp = "1234"; + $sformat(str, "%0o", oval); + if (str != cmp) begin + $display("FAILED: %%0o, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "00001234"; + $sformat(str, "%08o", oval); + if (str != cmp) begin + $display("FAILED: %%08o, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "1234 "; + $sformat(str, "%-08o", oval); + if (str != cmp) begin + $display("FAILED: %%-08o, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + // Check the %h conversion. + hval = 16'h0abc; + cmp = "abc"; + $sformat(str, "%0h", hval); + if (str != cmp) begin + $display("FAILED: %%0h, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "00000abc"; + $sformat(str, "%08h", hval); + if (str != cmp) begin + $display("FAILED: %%08h, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "abc "; + $sformat(str, "%-08h", hval); + if (str != cmp) begin + $display("FAILED: %%-08h, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + // Check the %c conversion. + bval = "c"; + cmp = "c"; + $sformat(str, "%0c", bval); + if (str != cmp) begin + $display("FAILED: %%0c, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "000c"; + $sformat(str, "%04c", bval); + if (str != cmp) begin + $display("FAILED: %%04c, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + // Check the %d conversion. + dval = 123; + cmp = "00000123"; + $sformat(str, "%08d", dval); + if (str != cmp) begin + $display("FAILED: %%08d, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "+0000123"; + $sformat(str, "%+08d", dval); + if (str != cmp) begin + $display("FAILED: %%+08d, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = " 123"; + $sformat(str, "%d", dval); + if (str != cmp) begin + $display("FAILED: %%d, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "123 "; + $sformat(str, "%-08d", dval); + if (str != cmp) begin + $display("FAILED: %%-08d, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "123"; + $sformat(str, "%0d", dval); + if (str != cmp) begin + $display("FAILED: %%0d, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + dval = -123; + cmp = "-0000123"; + $sformat(str, "%08d", dval); + if (str != cmp) begin + $display("FAILED: %%08d, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + $sformat(str, "%+08d", dval); + if (str != cmp) begin + $display("FAILED: %%+08d, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = " -123"; + $sformat(str, "%d", dval); + if (str != cmp) begin + $display("FAILED: %%d, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + // Check the %t conversion. + tval = 100_000; + cmp = "0010000000"; + $sformat(str, "%010t", tval); + if (str != cmp) begin + $display("FAILED: %%010t, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = " 10000000"; // Default width is 20. + $sformat(str, "%t", tval); + if (str != cmp) begin + $display("FAILED: %%t, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "10000000 "; + $sformat(str, "%-010t", tval); + if (str != cmp) begin + $display("FAILED: %%-010t, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "10000000"; + $sformat(str, "%0t", tval); + if (str != cmp) begin + $display("FAILED: %%0t, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + rval=100_000.25; + cmp = "0010000025"; + $sformat(str, "%010t", rval); + if (str != cmp) begin + $display("FAILED: %%010t (real), expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = " 10000025"; // Default width is 20. + $sformat(str, "%t", rval); + if (str != cmp) begin + $display("FAILED: %%t (real), expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "10000025 "; + $sformat(str, "%-010t", rval); + if (str != cmp) begin + $display("FAILED: %%-010t (real), expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "10000025"; + $sformat(str, "%0t", rval); + if (str != cmp) begin + $display("FAILED: %%0t (real), expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + // Display in ns with 10ps resolution. + $timeformat(-9, 2, " ns", 15); + + cmp = "000100000.00 ns"; + $sformat(str, "%015t", tval); + if (str != cmp) begin + $display("FAILED: %%015t (w/$tf), expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = " 100000.00 ns"; + $sformat(str, "%t", tval); + if (str != cmp) begin + $display("FAILED: %%t (w/$tf), expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "100000.00 ns "; + $sformat(str, "%-015t", tval); + if (str != cmp) begin + $display("FAILED: %%-015t (w/$tf), expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "100000.00 ns"; + $sformat(str, "%-0t", tval); + if (str != cmp) begin + $display("FAILED: %%-0t (w/$tf), expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "000100000.25 ns"; + $sformat(str, "%015t", rval); + if (str != cmp) begin + $display("FAILED: %%015t (w/$tf, rl), expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = " 100000.25 ns"; + $sformat(str, "%t", rval); + if (str != cmp) begin + $display("FAILED: %%t (w/$tf, rl), expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "100000.25 ns "; + $sformat(str, "%-015t", rval); + if (str != cmp) begin + $display("FAILED: %%-015t (w/$tf, rl), expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "100000.25 ns"; + $sformat(str, "%-0t", rval); + if (str != cmp) begin + $display("FAILED: %%-0t (w/$tf, rl), expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + // Check the real conversions (%e, %f, %g). If one works they all + // they all work (uses system conversion). + + rval = 1.25; + cmp = "000000001.250000"; + $sformat(str, "%016.6f", rval); + if (str != cmp) begin + $display("FAILED: %%016.6f, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "+00000001.250000"; + $sformat(str, "%+016.6f", rval); + if (str != cmp) begin + $display("FAILED: %%+016.6f, expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + rval = -1.25; + cmp = "-00000001.250000"; + $sformat(str, "%016.6f", rval); + if (str != cmp) begin + $display("FAILED: %%016.6f (negative), expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + cmp = "-00000001.250000"; + $sformat(str, "%+016.6f", rval); + if (str != cmp) begin + $display("FAILED: %%+016.6f (negative), expected %0s, got %0s", cmp, str); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2486350.v b/ivtest/ivltests/pr2486350.v new file mode 100644 index 000000000..b6a2f9217 --- /dev/null +++ b/ivtest/ivltests/pr2486350.v @@ -0,0 +1,18 @@ +`timescale 1 s / 1 fs + +module main; + + reg a; + + initial begin + a = 1'b0; + #10 ; + $display("simtime=%d (%h)", $simtime, $simtime); + a = 1'b1; + end + + initial begin + #100 $finish(0); + end + +endmodule // main diff --git a/ivtest/ivltests/pr2503208.v b/ivtest/ivltests/pr2503208.v new file mode 100644 index 000000000..7dc384755 --- /dev/null +++ b/ivtest/ivltests/pr2503208.v @@ -0,0 +1,16 @@ +module tb; + +parameter A = 34; +parameter B = 17; +parameter C = ((A+1)>>1) + (B-((A+1)>>1)); + +initial begin + if (C !== 17) begin + $display("FAILED -- C == %d (%b)", C, C); + $finish; + end + $display("PASSED"); + $finish; +end + +endmodule diff --git a/ivtest/ivltests/pr2509349.txt b/ivtest/ivltests/pr2509349.txt new file mode 100644 index 000000000..95caba1b1 --- /dev/null +++ b/ivtest/ivltests/pr2509349.txt @@ -0,0 +1,8 @@ +0 +1 +2 +3 +4 +5 +6 +7 diff --git a/ivtest/ivltests/pr2509349a.v b/ivtest/ivltests/pr2509349a.v new file mode 100644 index 000000000..27a342070 --- /dev/null +++ b/ivtest/ivltests/pr2509349a.v @@ -0,0 +1,23 @@ +module top; + reg pass; + reg [7:0] idx; + reg [7:0] mem [0:7]; + + initial begin + pass = 1'b1; + + // Neither no_dir or no_dir2 should exist and vsim should be a file. + $readmempath("/tmp:/no_dir:no_dir2:vsim:ivltests"); + + $readmemh("pr2509349.txt", mem); + + for (idx = 0; idx < 8; idx = idx + 1) begin + if (mem[idx] !== idx) begin + $display("Failed mem[%0d], expected %d, got %d", idx, idx, mem[idx]); + pass = 1'b0; + end + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2509349b.v b/ivtest/ivltests/pr2509349b.v new file mode 100644 index 000000000..6cf00b223 --- /dev/null +++ b/ivtest/ivltests/pr2509349b.v @@ -0,0 +1,10 @@ +module top; + reg [79:0] str; + + initial begin + $readmempath(str); + str = "test"; + str[7:0] = 'd2; + $readmempath(str); + end +endmodule diff --git a/ivtest/ivltests/pr2528915.v b/ivtest/ivltests/pr2528915.v new file mode 100644 index 000000000..c86b7dcfb --- /dev/null +++ b/ivtest/ivltests/pr2528915.v @@ -0,0 +1,12 @@ +module mainp_tb; + +reg clk=0; +integer usb_stream; +// reg [15:0] out_usb_stream; + +always @(posedge clk) begin + // This should generate an error, not crash. + $fwrite(usb_stream, "%c", out_usb_stream[7:0]); +end + +endmodule diff --git a/ivtest/ivltests/pr2533175.v b/ivtest/ivltests/pr2533175.v new file mode 100644 index 000000000..825fd3fa2 --- /dev/null +++ b/ivtest/ivltests/pr2533175.v @@ -0,0 +1,25 @@ +module pr2533175(); + +task fill_array; + +begin:block + reg [7:0] array[3:0]; + integer i; + + for (i = 0; i < 4; i = i + 1) begin + array[i] = i; + end + for (i = 0; i < 4; i = i + 1) begin + if (array[i] != i) begin + $display("FAILED: %0d != %0d", array[i], i); + $finish; + end + end + $display("PASSED"); +end + +endtask + +initial fill_array; + +endmodule diff --git a/ivtest/ivltests/pr2579479.v b/ivtest/ivltests/pr2579479.v new file mode 100644 index 000000000..e6f002a36 --- /dev/null +++ b/ivtest/ivltests/pr2579479.v @@ -0,0 +1,22 @@ +// Based on pr2579479 + +module main; + + supply0 gnd; + supply1 vdd; + wire A,B; + + tranif1 uA(gnd, A, vdd); + tranif1 uB(A, B, vdd); + tranif1 uC(B, vdd, gnd); + + initial begin + #1 $display("A=%d, B=%d", A,B); + if ((A !== 1'b0) || (B !== 1'b0)) begin + $display("FAILED -- A=%b, B=%b", A, B); + $finish; + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/pr2580730.v b/ivtest/ivltests/pr2580730.v new file mode 100644 index 000000000..7b466c6d4 --- /dev/null +++ b/ivtest/ivltests/pr2580730.v @@ -0,0 +1,73 @@ +/* + * Verify that the various non-blocking assignments support a delay + * that is greater than 32 bits. The top delays are in seconds and + * the other delays are in ps. The second delays all require more + * than 32 bits to work correctly. They will use the /d version. + */ + +`timescale 1s/1s +module gt32b; + real rlval; + reg rval; + reg aval[1:0]; + reg [7:0] psval; + + initial begin + $timeformat(-12, 0, " ps", 16); + #1; + $display("dl:gt32b- %t", $realtime); + rlval <= #1 1.0; + rval <= #2 1'b1; + aval[0] <= #3 1'b0; + psval[1] <= #4 1'b1; + end + + always @(rlval) begin + $display("rl:gt32b- %t", $realtime); + end + + always @(rval) begin + $display("rg:gt32b- %t", $realtime); + end + + always @(aval[0]) begin + $display("ar:gt32b- %t", $realtime); + end + + always @(psval) begin + $display("ps:gt32b- %t", $realtime); + end +endmodule + +`timescale 1ps/1ps +module ls32b; + real rlval; + reg rval; + reg aval[1:0]; + reg [7:0] psval; + + initial begin + #1; + $display("dl:ls32b- %t", $realtime); + rlval <= #1 1.0; + rval <= #2 1'b1; + aval[0] <= #3 1'b0; + psval[1] <= #4 1'b1; + end + + always @(rlval) begin + $display("rl:ls32b- %t", $realtime); + end + + always @(rval) begin + $display("rg:ls32b- %t", $realtime); + end + + always @(aval[0]) begin + $display("ar:ls32b- %t", $realtime); + end + + always @(psval) begin + $display("ps:ls32b- %t", $realtime); + end +endmodule diff --git a/ivtest/ivltests/pr2590274a.v b/ivtest/ivltests/pr2590274a.v new file mode 100644 index 000000000..5132216ee --- /dev/null +++ b/ivtest/ivltests/pr2590274a.v @@ -0,0 +1,24 @@ +// We want to print a warning if we find a delay that comes from the +// default timescale (1s) and then one from a given timescale. +// Basically we want to have either the case of no timescales or +// timescales for all delays. +module wo_time; + reg in; + wire #1 out = in; + + initial begin + in = 1'b1; + #2 $finish(0); + end + + always @(out) $display("The time in %m is: %e", $abstime); +endmodule + +`timescale 1ns/1ns +module w_time; + reg in; + wire #1 out = in; + + initial in = 1'b1; + always @(out) $display("The time in %m is: %e", $abstime); +endmodule diff --git a/ivtest/ivltests/pr2590274b.v b/ivtest/ivltests/pr2590274b.v new file mode 100644 index 000000000..a509c0d0e --- /dev/null +++ b/ivtest/ivltests/pr2590274b.v @@ -0,0 +1,12 @@ +// We want to print a warning if we find a delay that comes from the +// default timescale (1s) and then one from a given timescale. +// Basically we want to have either the case of no timescales or +// timescales for all delays. +module wo_time; + initial #1 $display("The time in %m is: %e", $abstime); +endmodule + +`timescale 1ns/1ns +module w_time; + initial #1 $display("The time in %m is: %e", $abstime); +endmodule diff --git a/ivtest/ivltests/pr2590274c.v b/ivtest/ivltests/pr2590274c.v new file mode 100644 index 000000000..c401bdcd1 --- /dev/null +++ b/ivtest/ivltests/pr2590274c.v @@ -0,0 +1,42 @@ +// We want to print a warning if we find a delay that comes from the +// default timescale (1s) and then one from a given timescale. +// Basically we want to have either the case of no timescales or +// timescales for all delays. +module wo_time(out, in); + output out; + input in; + + buf(out, in); + + specify + (in => out) = 1; + endspecify +endmodule + +module top; + reg in; + wire out_wo, out_w; + + wo_time wo(out_wo, in); + w_time w(out_w, in); + + initial begin + in = 1'b1; + #2 $finish(0); + end + + always @(out_wo) $display("The time in wo_time is: %e", $abstime); + always @(out_w) $display("The time in w_time is: %e", $abstime); +endmodule + +`timescale 1ns/1ns +module w_time(out, in); + output out; + input in; + + buf(out, in); + + specify + (in => out) = 1; + endspecify +endmodule diff --git a/ivtest/ivltests/pr2593733.v b/ivtest/ivltests/pr2593733.v new file mode 100644 index 000000000..ebf856c9c --- /dev/null +++ b/ivtest/ivltests/pr2593733.v @@ -0,0 +1,19 @@ +`timescale 1 ps / 1 ps +module use_wid_gt_zero_assert ( +); + +parameter width = 1; +parameter option = "OFF"; + +reg [width-1:0] dst; + +initial +begin + dst = (option == "ON") ? {width{1'b1}} : {width{1'b0}}; + if (dst === 1'b0) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2597278.v b/ivtest/ivltests/pr2597278.v new file mode 100644 index 000000000..8ba545ec9 --- /dev/null +++ b/ivtest/ivltests/pr2597278.v @@ -0,0 +1,29 @@ +module top; + reg [1:0] q; + reg [4:0] icim[1:0]; + integer j; + + always @(q) begin + /* + * The following line had the muli problem, the other line has a + * different problem. + */ + icim[0] <= #1 0 + 8 * (0 >> q); + icim[1] <= #1 1 + 8 * (1 >> q); + end + + initial begin + q = 2'd1; + #2; + if (icim[0] !== 0) begin + $display("FAILED"); + $finish; + end + if (icim[1] !== 1) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr2597278b.v b/ivtest/ivltests/pr2597278b.v new file mode 100644 index 000000000..52d74238a --- /dev/null +++ b/ivtest/ivltests/pr2597278b.v @@ -0,0 +1,29 @@ +module top; + reg [1:0] q; + wire [4:0] icim[1:0]; + integer j; + + always @(q) begin + /* + * The following line had the muli problem, the other line has a + * different problem. + */ + icim[0] <= #1 0 + 8 * (0 >> q); + icim[1] <= #1 1 + 8 * (1 >> q); + end + + initial begin + q = 2'd1; + #2; + if (icim[0] !== 0) begin + $display("FAILED"); + $finish; + end + if (icim[1] !== 1) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr2605006.v b/ivtest/ivltests/pr2605006.v new file mode 100644 index 000000000..3433f7422 --- /dev/null +++ b/ivtest/ivltests/pr2605006.v @@ -0,0 +1,21 @@ +module test(); + reg clk; + + reg [15:0] usb_shadow [0: 32]; + + initial begin + usb_shadow[6'b0_00000] = 'b0101; + usb_shadow[6'b1_00000] = 'b1001; + clk = 0; + if (usb_shadow[{!clk,5'b0}][15:2] !== 2) begin + $display("FAILED"); + $finish; + end + clk = 1; + if (usb_shadow[{!clk,5'b0}][15:2] !== 1) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end +endmodule // test diff --git a/ivtest/ivltests/pr2673846.v b/ivtest/ivltests/pr2673846.v new file mode 100644 index 000000000..eb50bfccb --- /dev/null +++ b/ivtest/ivltests/pr2673846.v @@ -0,0 +1,33 @@ +module top; + reg [39:0] x, x_inv_bug, temp_x; + integer i, j; + + wire [39:0] res2 = {40 {1'd1}} / x; + + initial begin +// Using this assignment instead of the procedural assignment below +// will work with out asserting. +// x = 1; +// assign x_inv_bug = {40 {1'd1}} / x; + + temp_x = 2**31; + for (i=30 ; i < 38; i=i+1) begin + temp_x = temp_x << 1; + for (j=0 ; j<3; j=j+1) begin + x = temp_x + (j-1); + $display(" // i,j,temp_x,x => %2d,%1d,%d,%h", i, j, temp_x, x); + // The following statement is asserting and it looks to be a + // problem in the division algorithm. This specific case is + // likely only a 32 bit problem, but by scaling I'm sure this + // could be made to trigger on a 64 bit machine. + x_inv_bug = {40 {1'd1}} / x; + #1 $display("x_inv_bug=%h, res2=%h", x_inv_bug, res2); + if (x_inv_bug !== res2) begin + $display("FAILED"); + $finish; + end + end + end // for (i=30 ; i < 38; i=i+1) + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2688910.v b/ivtest/ivltests/pr2688910.v new file mode 100644 index 000000000..65b0c9a8a --- /dev/null +++ b/ivtest/ivltests/pr2688910.v @@ -0,0 +1,22 @@ +module top; + reg passed = 1'b1; + reg [7:0] in; + + lwr dut(in); + + initial begin + #1 in = 8'd1; + #1 in = 8'd2; + + #1 if (passed) $display("PASSED"); + end +endmodule + +module lwr(input [7:0] xin); + wire [7:0] x1 = {xin,{0{1'b0}}}; + + always @(x1) if (x1 != $time) begin + $display("Failed at time %2d, expected %2d, got %2d", $time, $time, x1); + top.passed = 1'b0; + end +endmodule diff --git a/ivtest/ivltests/pr2709097.hex b/ivtest/ivltests/pr2709097.hex new file mode 100644 index 000000000..5384148d9 --- /dev/null +++ b/ivtest/ivltests/pr2709097.hex @@ -0,0 +1 @@ +0000000a diff --git a/ivtest/ivltests/pr2709097.v b/ivtest/ivltests/pr2709097.v new file mode 100644 index 000000000..603e2352e --- /dev/null +++ b/ivtest/ivltests/pr2709097.v @@ -0,0 +1,10 @@ +module top; + reg [31:0] mem[0:0]; + + initial begin + $readmemh( "ivltests/pr2709097.hex", mem ); +// $display("mem[0] = %d", mem[0]); + if (mem[0] !== 10) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2715547.v b/ivtest/ivltests/pr2715547.v new file mode 100644 index 000000000..f07a9cb88 --- /dev/null +++ b/ivtest/ivltests/pr2715547.v @@ -0,0 +1,11 @@ +module top; + reg [31:0] mem [3:0]; + + initial begin + mem[1] = {32{1'b1}}; + mem[1][15] = 1'b0; + + if (mem[1] !== 32'hffff7fff) $display("Failed, got %h", mem[1]); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2715558.v b/ivtest/ivltests/pr2715558.v new file mode 100644 index 000000000..3b743e9e6 --- /dev/null +++ b/ivtest/ivltests/pr2715558.v @@ -0,0 +1,102 @@ +// NOTE: This test program is WRONG, in that it ignores the fact +// that continuous assigns drive with their own strength and drop +// any strength that the r-value may have. + +module strength(); + +wire sup1; assign (supply0, supply1) sup1 = 1'b1; +wire str1; assign (strong0, strong1) str1 = 1'b1; +wire pl1; assign (pull0, pull1) pl1 = 1'b1; +wire we1; assign (weak0, weak1) we1 = 1'b1; + +wire sup0; assign (supply0, supply1) sup0 = 1'b0; +wire str0; assign (strong0, strong1) str0 = 1'b0; +wire pl0; assign (pull0, pull1) pl0 = 1'b0; +wire we0; assign (weak0, weak1) we0 = 1'b0; + +wire sup1_sup0; +wire sup1_str0; +wire sup1_pl0; +wire sup1_we0; + +assign sup1_sup0 = sup1; +assign sup1_sup0 = sup0; +assign sup1_str0 = sup1; +assign sup1_str0 = str0; +assign sup1_pl0 = sup1; +assign sup1_pl0 = pl0; +assign sup1_we0 = sup1; +assign sup1_we0 = we0; + +initial begin + #1; + $display("sup1_sup0 resulted in: %b", sup1_sup0); + $display("sup1_str0 resulted in: %b", sup1_str0); + $display("sup1_pl0 resulted in: %b", sup1_pl0); + $display("sup1_we0 resulted in: %b", sup1_we0); +end + +wire str1_sup0; +wire str1_str0; +wire str1_pl0; +wire str1_we0; +assign str1_sup0 = str1; +assign str1_sup0 = sup0; +assign str1_str0 = str1; +assign str1_str0 = str0; +assign str1_pl0 = str1; +assign str1_pl0 = pl0; +assign str1_we0 = str1; +assign str1_we0 = we0; + +initial begin + #2; + $display("str1_sup0 resulted in: %b", str1_sup0); + $display("str1_str0 resulted in: %b", str1_str0); + $display("str1_pl0 resulted in: %b", str1_pl0); + $display("str1_we0 resulted in: %b", str1_we0); +end + +wire pl1_sup0; +wire pl1_str0; +wire pl1_pl0; +wire pl1_we0; +assign pl1_sup0 = pl1; +assign pl1_sup0 = sup0; +assign pl1_str0 = pl1; +assign pl1_str0 = str0; +assign pl1_pl0 = pl1; +assign pl1_pl0 = pl0; +assign pl1_we0 = pl1; +assign pl1_we0 = we0; + +initial begin + #3; + $display("pl1_sup0 resulted in: %b", pl1_sup0); + $display("pl1_str0 resulted in: %b", pl1_str0); + $display("pl1_pl0 resulted in: %b", pl1_pl0); + $display("pl1_we0 resulted in: %b", pl1_we0); +end + +wire we1_sup0; +wire we1_str0; +wire we1_pl0; +wire we1_we0; +assign we1_sup0 = we1; +assign we1_sup0 = sup0; +assign we1_str0 = we1; +assign we1_str0 = str0; +assign we1_pl0 = we1; +assign we1_pl0 = pl0; +assign we1_we0 = we1; +assign we1_we0 = we0; + +initial begin + #4; + $display("we1_sup0 resulted in: %b", we1_sup0); + $display("we1_str0 resulted in: %b", we1_str0); + $display("we1_pl0 resulted in: %b", we1_pl0); + $display("we1_we0 resulted in: %b", we1_we0); +end + +endmodule diff --git a/ivtest/ivltests/pr2715558b.v b/ivtest/ivltests/pr2715558b.v new file mode 100644 index 000000000..19bc1537a --- /dev/null +++ b/ivtest/ivltests/pr2715558b.v @@ -0,0 +1,95 @@ +/* The original test case submitted for pr2715558 should not have + given the the results the bug reporter expected (see pr2986806). + This is a reworked version that does give those results. +*/ +module pr2715558b(); + +wire sup1_sup0; +wire sup1_str0; +wire sup1_pl0; +wire sup1_we0; + +assign (supply0, supply1) sup1_sup0 = 1'b1; +assign (supply0, supply1) sup1_sup0 = 1'b0; +assign (supply0, supply1) sup1_str0 = 1'b1; +assign (strong0, strong1) sup1_str0 = 1'b0; +assign (supply0, supply1) sup1_pl0 = 1'b1; +assign (pull0, pull1) sup1_pl0 = 1'b0; +assign (supply0, supply1) sup1_we0 = 1'b1; +assign (weak0, weak1) sup1_we0 = 1'b0; + +initial begin + #1; + $display("sup1_sup0 resulted in: %b", sup1_sup0); + $display("sup1_str0 resulted in: %b", sup1_str0); + $display("sup1_pl0 resulted in: %b", sup1_pl0); + $display("sup1_we0 resulted in: %b", sup1_we0); +end + +wire str1_sup0; +wire str1_str0; +wire str1_pl0; +wire str1_we0; + +assign (strong0, strong1) str1_sup0 = 1'b1; +assign (supply0, supply1) str1_sup0 = 1'b0; +assign (strong0, strong1) str1_str0 = 1'b1; +assign (strong0, strong1) str1_str0 = 1'b0; +assign (strong0, strong1) str1_pl0 = 1'b1; +assign (pull0, pull1) str1_pl0 = 1'b0; +assign (strong0, strong1) str1_we0 = 1'b1; +assign (weak0, weak1) str1_we0 = 1'b0; + +initial begin + #1; + $display("str1_sup0 resulted in: %b", str1_sup0); + $display("str1_str0 resulted in: %b", str1_str0); + $display("str1_pl0 resulted in: %b", str1_pl0); + $display("str1_we0 resulted in: %b", str1_we0); +end + +wire pl1_sup0; +wire pl1_str0; +wire pl1_pl0; +wire pl1_we0; + +assign (pull0, pull1) pl1_sup0 = 1'b1; +assign (supply0, supply1) pl1_sup0 = 1'b0; +assign (pull0, pull1) pl1_str0 = 1'b1; +assign (strong0, strong1) pl1_str0 = 1'b0; +assign (pull0, pull1) pl1_pl0 = 1'b1; +assign (pull0, pull1) pl1_pl0 = 1'b0; +assign (pull0, pull1) pl1_we0 = 1'b1; +assign (weak0, weak1) pl1_we0 = 1'b0; + +initial begin + #1; + $display("pl1_sup0 resulted in: %b", pl1_sup0); + $display("pl1_str0 resulted in: %b", pl1_str0); + $display("pl1_pl0 resulted in: %b", pl1_pl0); + $display("pl1_we0 resulted in: %b", pl1_we0); +end + +wire we1_sup0; +wire we1_str0; +wire we1_pl0; +wire we1_we0; + +assign (weak0, weak1) we1_sup0 = 1'b1; +assign (supply0, supply1) we1_sup0 = 1'b0; +assign (weak0, weak1) we1_str0 = 1'b1; +assign (strong0, strong1) we1_str0 = 1'b0; +assign (weak0, weak1) we1_pl0 = 1'b1; +assign (pull0, pull1) we1_pl0 = 1'b0; +assign (weak0, weak1) we1_we0 = 1'b1; +assign (weak0, weak1) we1_we0 = 1'b0; + +initial begin + #1; + $display("we1_sup0 resulted in: %b", we1_sup0); + $display("we1_str0 resulted in: %b", we1_str0); + $display("we1_pl0 resulted in: %b", we1_pl0); + $display("we1_we0 resulted in: %b", we1_we0); +end + +endmodule diff --git a/ivtest/ivltests/pr2715748.v b/ivtest/ivltests/pr2715748.v new file mode 100644 index 000000000..a83db54b1 --- /dev/null +++ b/ivtest/ivltests/pr2715748.v @@ -0,0 +1,30 @@ +module top; + integer res; + + real rvar [1:0]; + realtime rtvar [1:0]; + + wire real rnet [1:0]; + + assign rnet[0] = 2.0; + + initial begin + rvar[0] = -1.0; + rtvar[0] = 1.0; + #1; + // Check the various get routines. + $display("Real %g, Realtime %g", rvar[0], rtvar[0]); + $display("Real as int %d, Realtime as int %d", rvar[0], rtvar[0]); + $display("Real net %g", rnet[0]); + $display("Real net as int %d", rnet[0]); + + // Check some put routines. + res = $sscanf("3.5", "%f", rvar[1]); + if (rvar[1] != 3.5) $display("Failed %%f put"); + else $display("Passed %%f put"); + + res = $sscanf("4", "%d", rtvar[1]); + if (rtvar[1] != 4.0) $display("Failed %%d put"); + else $display("Passed %%d put"); + end +endmodule diff --git a/ivtest/ivltests/pr2721213.v b/ivtest/ivltests/pr2721213.v new file mode 100644 index 000000000..54a28be99 --- /dev/null +++ b/ivtest/ivltests/pr2721213.v @@ -0,0 +1,7 @@ +module top; + task foo(); + $display("PASSED"); + endtask + + initial foo; +endmodule diff --git a/ivtest/ivltests/pr2722330a.v b/ivtest/ivltests/pr2722330a.v new file mode 100644 index 000000000..3a44edc3d --- /dev/null +++ b/ivtest/ivltests/pr2722330a.v @@ -0,0 +1,57 @@ +// Check that the >> and >>> operators with unsigned values. +module top; + parameter py = 8'b10101010 >> 3'b101; + parameter pz = 8'b10101010 >>> 3'b101; + + reg passed; + reg [7:0] a; + reg [2:0] b; + wire [7:0] wy, wz; + reg [7:0] ry, rz; + + // Check CA code. + assign wy = a >> b; + assign wz = a >>> b; + + initial begin + passed = 1'b1; + // Example vector + a = 8'b10101010; + b = 3'b101; + #1; + + // Check the parameter results. + if (py !== 8'b00000101) begin + $display("Failed param. >>, expected 8'b00000101, got %b", py); + passed = 1'b0; + end + if (pz !== 8'b00000101) begin + $display("Failed param. >>>, expected 8'b00000101, got %b", pz); + passed = 1'b0; + end + + // Check the procedural results. + ry = a >> b; + if (ry !== 8'b00000101) begin + $display("Failed procedural >>, expected 8'b00000101, got %b", ry); + passed = 1'b0; + end + rz = a >>> b; + if (rz !== 8'b00000101) begin + $display("Failed procedural >>>, expected 8'b00000101, got %b", rz); + passed = 1'b0; + end + + // Check the CA results. + if (wy !== 8'b00000101) begin + $display("Failed CA >>, expected 8'b00000101, got %b", wy); + passed = 1'b0; + end + if (wz !== 8'b00000101) begin + $display("Failed CA >>>, expected 8'b00000101, got %b", wz); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2722330b.v b/ivtest/ivltests/pr2722330b.v new file mode 100644 index 000000000..92c60a79a --- /dev/null +++ b/ivtest/ivltests/pr2722330b.v @@ -0,0 +1,52 @@ +module top; + parameter py = 8'sb10101010 >> 3'sb110; + parameter pz = 8'sb10101010 >>> 3'sb110; + + reg passed; + reg signed [7:0] ry, rz, a; + wire signed [7:0] wy, wz; + + assign wy = a >> 3'sb110; + assign wz = a >>> 3'sb110; + + initial begin + passed = 1'b1; + // Example vector + a = 8'sb10101010; + #1; + + // Check the parameter results. + if (py !== 8'b00000010) begin + $display("Failed parameter >>, expected 8'b00000010, got %b", py); + passed = 1'b0; + end + if (pz !== 8'b11111110) begin + $display("Failed parameter >>>, expected 8'b11111110, got %b", pz); + passed = 1'b0; + end + + // Check the procedural results. + ry = a >> 3'sb110; + if (ry !== 8'b00000010) begin + $display("Failed procedural >>, expected 8'b00000010, got %b", ry); + passed = 1'b0; + end + rz = a >>> 3'sb110; + if (rz !== 8'b11111110) begin + $display("Failed procedural >>>, expected 8'b11111110, got %b", rz); + passed = 1'b0; + end + + // Check the CA results. + if (wy !== 8'b00000010) begin + $display("Failed CA >>, expected 8'b00000010, got %b", wy); + passed = 1'b0; + end + if (wz !== 8'b11111110) begin + $display("Failed CA >>>, expected 8'111111110, got %b", wz); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2722339a.v b/ivtest/ivltests/pr2722339a.v new file mode 100644 index 000000000..84a324bc3 --- /dev/null +++ b/ivtest/ivltests/pr2722339a.v @@ -0,0 +1,48 @@ +module top; + reg pass; + reg [7:0] a, b; + wire [15:0] ruu, rsu, rus, rss; + reg signed [15:0] res; + integer i; + + assign ruu = a / b; + assign rsu = $signed(a) / b; + assign rus = a / $signed(b); + assign rss = $signed(a) / $signed(b); + + initial begin + pass = 1'b1; + + // Run 1000 random vectors + for (i = 0; i < 1000; i = i + 1) begin + // Random vectors + a = $random; + b = $random; + #1; + + // Check unsigned / unsigned. + if (ruu !== a/b) begin + $display("FAILED: u/u (%b/%b) gave %b, expected %b", a, b, ruu, a/b); + pass = 1'b0; + end + // Check signed / unsigned. + if (rsu !== a/b) begin + $display("FAILED: s/u (%b/%b) gave %b, expected %b", a, b, rsu, a/b); + pass = 1'b0; + end + // Check unsigned / signed. + if (rus !== a/b) begin + $display("FAILED: u/s (%b/%b) gave %b, expected %b", a, b, rus, a/b); + pass = 1'b0; + end + // Check signed / signed. + res = $signed(a)/$signed(b); + if (rss !== res) begin + $display("FAILED: s/s (%b/%b) gave %b, expected %b", a, b, rss, res); + pass = 1'b0; + end + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2722339b.v b/ivtest/ivltests/pr2722339b.v new file mode 100644 index 000000000..3bfb26a51 --- /dev/null +++ b/ivtest/ivltests/pr2722339b.v @@ -0,0 +1,48 @@ +module top; + reg pass; + reg [7:0] a, b; + wire [15:0] ruu, rsu, rus, rss; + reg signed [15:0] res; + integer i; + + assign ruu = a % b; + assign rsu = $signed(a) % b; + assign rus = a % $signed(b); + assign rss = $signed(a) % $signed(b); + + initial begin + pass = 1'b1; + + // Run 1000 random vectors + for (i = 0; i < 1000; i = i + 1) begin + // Random vectors + a = $random; + b = $random; + #1; + + // Check unsigned % unsigned. + if (ruu !== a%b) begin + $display("FAILED: u%%u (%b%%%b) gave %b, expected %b", a, b, ruu, a%b); + pass = 1'b0; + end + // Check signed % unsigned division. + if (rsu !== a%b) begin + $display("FAILED: s%%u (%b%%%b) gave %b, expected %b", a, b, rsu, a%b); + pass = 1'b0; + end + // Check unsigned % signed division. + if (rus !== a%b) begin + $display("FAILED: u%%s (%b%%%b) gave %b, expected %b", a, b, rus, a%b); + pass = 1'b0; + end + // Check signed % signed division. + res = $signed(a)%$signed(b); + if (rss !== res) begin + $display("FAILED: s%%s (%b%%%b) gave %b, expected %b", a, b, rss, res); + pass = 1'b0; + end + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2723712.v b/ivtest/ivltests/pr2723712.v new file mode 100644 index 000000000..4dcc2d1d4 --- /dev/null +++ b/ivtest/ivltests/pr2723712.v @@ -0,0 +1,21 @@ +module top; + reg [7:0] a; + reg [2:0] b; + wire [7:0] y, z; + + assign y = a >> b; + assign z = $signed(a) >> $signed(b); + + initial begin + // Example vector + a = 8'b10101010; + b = 3'b101; + #1; + + // Test for correctness + if (y === z && y === 8'b00000101) + $display("PASSED"); + else + $display("FAILED, expected 8'b00000101, got %b/%b", y, z); + end +endmodule diff --git a/ivtest/ivltests/pr2725700a.v b/ivtest/ivltests/pr2725700a.v new file mode 100644 index 000000000..390d731a1 --- /dev/null +++ b/ivtest/ivltests/pr2725700a.v @@ -0,0 +1,64 @@ +module top; + reg pass; + wire out; + reg drive_val; + reg oe_n; + reg [1:0] pull_vec; + + bufif0 (out, drive_val, oe_n); + assign (pull0, pull1) out = pull_vec[0]; + + initial begin + pass = 1'b1; + pull_vec = 2'b00; + oe_n = 1'b0; + + // Drive is selected. + drive_val = 1'b0; + #1; + if (out !== drive_val) begin + $display("Failed to drive 0, got %b", out); + pass = 1'b0; + end + + drive_val = 1'b1; + #1; + if (out !== drive_val) begin + $display("Failed to drive 1, got %b", out); + pass = 1'b0; + end + + // The pull is selected (low). + oe_n = 1'b1; + drive_val = 1'b0; + #1; + if (out !== pull_vec[0]) begin + $display("Failed pull #1, expected 1'b0, got %b", out); + pass = 1'b0; + end + + drive_val = 1'b1; + #1; + if (out !== pull_vec[0]) begin + $display("Failed pull #2, expected 1'b0, got %b", out); + pass = 1'b0; + end + + // The pull is selected (high). + pull_vec = 2'b11; + drive_val = 1'b0; + #1; + if (out !== pull_vec[0]) begin + $display("Failed pull #3, expected 1'b1, got %b", out); + pass = 1'b0; + end + + drive_val = 1'b1; + if (out !== pull_vec[0]) begin + $display("Failed pull #4, expected 1'b1, got %b", out); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2725700b.v b/ivtest/ivltests/pr2725700b.v new file mode 100644 index 000000000..9de40c870 --- /dev/null +++ b/ivtest/ivltests/pr2725700b.v @@ -0,0 +1,64 @@ +module top; + reg pass; + wire [1:0] out; + reg [1:0] drive_val; + reg [1:0] oe_n; + reg [2:0] pull_vec; + + bufif0 bufs[1:0] (out, drive_val, oe_n); + assign (pull0, pull1) out = pull_vec[1:0]; + + initial begin + pass = 1'b1; + pull_vec = 3'b000; + oe_n = 2'b00; + + // Drive is selected. + drive_val = 2'b00; + #1; + if (out !== drive_val) begin + $display("Failed to drive 2'b00, got %b", out); + pass = 1'b0; + end + + drive_val = 1'b1; + #1; + if (out !== drive_val) begin + $display("Failed to drive 2'b11, got %b", out); + pass = 1'b0; + end + + // The pull is selected (low). + oe_n = 2'b11; + drive_val = 2'b00; + #1; + if (out !== pull_vec[1:0]) begin + $display("Failed pull #1, expected 2'b00, got %b", out); + pass = 1'b0; + end + + drive_val = 1'b1; + #1; + if (out !== pull_vec[1:0]) begin + $display("Failed pull #2, expected 2'b00, got %b", out); + pass = 1'b0; + end + + // The pull is selected (high). + pull_vec = 3'b111; + drive_val = 2'b00; + #1; + if (out !== pull_vec[1:0]) begin + $display("Failed pull #3, expected 2'b11, got %b", out); + pass = 1'b0; + end + + drive_val = 2'b11; + if (out !== pull_vec[1:0]) begin + $display("Failed pull #4, expected 2'b11, got %b", out); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2725700c.v b/ivtest/ivltests/pr2725700c.v new file mode 100644 index 000000000..4956c9ad6 --- /dev/null +++ b/ivtest/ivltests/pr2725700c.v @@ -0,0 +1,66 @@ +module top; + reg pass; + wire [1:0] out; + reg [1:0] drive_val; + reg [1:0] oe_n; + reg [2:0] pull_vec; + reg [1:0] base; + + bufif0 bufs[1:0] (out, drive_val, oe_n); + assign (pull0, pull1) out = pull_vec[base+:2]; + + initial begin + pass = 1'b1; + base = 2'b00; + pull_vec = 3'b000; + oe_n = 2'b00; + + // Drive is selected. + drive_val = 2'b00; + #1; + if (out !== drive_val) begin + $display("Failed to drive 2'b00, got %b", out); + pass = 1'b0; + end + + drive_val = 1'b1; + #1; + if (out !== drive_val) begin + $display("Failed to drive 2'b11, got %b", out); + pass = 1'b0; + end + + // The pull is selected (low). + oe_n = 2'b11; + drive_val = 2'b00; + #1; + if (out !== pull_vec[1:0]) begin + $display("Failed pull #1, expected 2'b00, got %b", out); + pass = 1'b0; + end + + drive_val = 1'b1; + #1; + if (out !== pull_vec[1:0]) begin + $display("Failed pull #2, expected 2'b00, got %b", out); + pass = 1'b0; + end + + // The pull is selected (high). + pull_vec = 3'b111; + drive_val = 2'b00; + #1; + if (out !== pull_vec[1:0]) begin + $display("Failed pull #3, expected 2'b11, got %b", out); + pass = 1'b0; + end + + drive_val = 2'b11; + if (out !== pull_vec[1:0]) begin + $display("Failed pull #4, expected 2'b11, got %b", out); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2728032.v b/ivtest/ivltests/pr2728032.v new file mode 100644 index 000000000..cade60435 --- /dev/null +++ b/ivtest/ivltests/pr2728032.v @@ -0,0 +1,232 @@ +module top; + reg pass; + time change; + reg in; + wire c1, c2a, c2b, c3; + wire v1, v2, v3; + + const_1 d_c1(c1, in); + const_2a d_c2a(c2a, in); + const_2b d_c2b(c2b, in); + const_3 d_c3(c3, in); + + var_1 d_v1(v1, in); +// var_2 d_v2(v2, in); + var_3 d_v3(v2, in); + + initial begin + pass = 1'b1; + #1000 in = 1'b0; + #1000 in = 1'b1; + #1000 in = 1'b0; + #1000 in = 1'b1; + #1000 in = 1'bx; + #1000 in = 1'b0; + #1000 in = 1'bx; + #1000 in = 1'b1; + #1000 in = 1'b0; + #1000 if (pass) $display("PASSED"); + end + + always @(in) change = $time; +endmodule + +// All delays should be 200. +module const_1 (output out, input in); + assign #(200) out = (in === 1'bx) ? 1'bz : ~in; + + always @(out) begin + case (out) + 1'b0: if ($time - top.change != 200) begin + $display("Failed const_1 fall"); + top.pass = 1'b0; + end + 1'b1: if ($time - top.change != 200) begin + $display("Failed const_1 rise"); + top.pass = 1'b0; + end + 1'bz: if ($time - top.change != 200) begin + $display("Failed const_1 high-Z"); + top.pass = 1'b0; + end + default: begin + $display("FAILED const_1 default"); + top.pass = 1'b0; + end + endcase + end +endmodule + +// Decay should also be 100. +module const_2a (output out, input in); + assign #(200, 100) out = (in === 1'bx) ? 1'bz : ~in; + + always @(out) begin + case (out) + 1'b0: if ($time - top.change != 100) begin + $display("Failed const_2a fall"); + top.pass = 1'b0; + end + 1'b1: if ($time - top.change != 200) begin + $display("Failed const_2a rise"); + top.pass = 1'b0; + end + 1'bz: if ($time - top.change != 100) begin + $display("Failed const_2a high-Z"); + top.pass = 1'b0; + end + default: begin + $display("FAILED const_2a default"); + top.pass = 1'b0; + end + endcase + end +endmodule + +// Decay should also be 100. +module const_2b (output out, input in); + assign #(100, 200) out = (in === 1'bx) ? 1'bz : ~in; + + always @(out) begin + case (out) + 1'b0: if ($time - top.change != 200) begin + $display("Failed const_2b fall"); + top.pass = 1'b0; + end + 1'b1: if ($time - top.change != 100) begin + $display("Failed const_2b rise"); + top.pass = 1'b0; + end + 1'bz: if ($time - top.change != 100) begin + $display("Failed const_2b high-Z"); + top.pass = 1'b0; + end + default: begin + $display("FAILED const_2b default"); + top.pass = 1'b0; + end + endcase + end +endmodule + +// All delays as given. +module const_3 (output out, input in); + assign #(100, 200, 300) out = (in === 1'bx) ? 1'bz : ~in; + + always @(out) begin + case (out) + 1'b0: if ($time - top.change != 200) begin + $display("Failed const_3 fall"); + top.pass = 1'b0; + end + 1'b1: if ($time - top.change != 100) begin + $display("Failed const_3 rise"); + top.pass = 1'b0; + end + 1'bz: if ($time - top.change != 300) begin + $display("Failed const_3 high-Z"); + top.pass = 1'b0; + end + default: begin + $display("FAILED const_3 default"); + top.pass = 1'b0; + end + endcase + end +endmodule + +// All delays should be delay. +module var_1 (output out, input in); + time delay = 200; + assign #(delay) out = (in === 1'bx) ? 1'bz : ~in; + + always @(out) begin + case (out) + 1'b0: if ($time - top.change != delay) begin + $display("Failed var_1 fall"); + top.pass = 1'b0; + end + 1'b1: if ($time - top.change != delay) begin + $display("Failed var_1 rise"); + top.pass = 1'b0; + end + 1'bz: if ($time - top.change != delay) begin + $display("Failed var_1 high-Z"); + top.pass = 1'b0; + end + default: begin + $display("FAILED var_1 default"); + top.pass = 1'b0; + end + endcase + end +endmodule + +/* + * We do not currently support calculating the decay time from the + * variable rise and fall times. The compiler will print a message + * and assert in the code generator. + * + * We need an a and b version to check both ways. + * +// Decay should be the minimum of rise and fall delay. +module var_2 (output out, input in); + time delayr = 100; + time delayf = 200; + assign #(delayr, delayf) out = ~in; + + function automatic real min_real(real a, real b); + min_real = a < b ? a : b; + endfunction + + always @(out) begin + case (out) + 1'b0: if ($time - top.change != delayf) begin + $display("Failed var_2 fall"); + top.pass = 1'b0; + end + 1'b1: if ($time - top.change != delayr) begin + $display("Failed var_2 rise"); + top.pass = 1'b0; + end + 1'bz: if ($time - top.change != min_real(delayf, delayr)) begin + $display("Failed var_2 high-Z"); + top.pass = 1'b0; + end + default: begin + $display("FAILED var_2 default"); + top.pass = 1'b0; + end + endcase + end +endmodule +*/ + +// All delays as given. +module var_3 (output out, input in); + time delayr = 100; + time delayf = 200; + time delayd = 300; + assign #(delayr, delayf, delayd) out = (in === 1'bx) ? 1'bz : ~in; + + always @(out) begin + case (out) + 1'b0: if ($time - top.change != delayf) begin + $display("Failed var_3 fall"); + top.pass = 1'b0; + end + 1'b1: if ($time - top.change != delayr) begin + $display("Failed var_3 rise"); + top.pass = 1'b0; + end + 1'bz: if ($time - top.change != delayd) begin + $display("Failed var_3 high-Z"); + top.pass = 1'b0; + end + default: begin + $display("FAILED var_3 default"); + top.pass = 1'b0; + end + endcase + end +endmodule diff --git a/ivtest/ivltests/pr2728547.v b/ivtest/ivltests/pr2728547.v new file mode 100644 index 000000000..9b06a09a0 --- /dev/null +++ b/ivtest/ivltests/pr2728547.v @@ -0,0 +1,40 @@ +module top; + parameter in = "First Second Third 15"; + reg pass; + integer res, arg4; + reg [32*8:1] arg1, arg2, arg3; + + initial begin + pass = 1'b1; + + res = $sscanf(in, "%s%s%s%d", arg1, arg2, arg3, arg4); + + if (res != 4) begin + $display("FAILED: wrong number of arguments, expected 4, got %0d", res); + pass = 1'b0; + end + + if (arg1[5*8:1] !== "First") begin + $display("FAILED: arg1, expected \"First\", got \"%0s\"", arg1); + pass = 1'b0; + end + + if (arg2[6*8:1] !== "Second") begin + $display("FAILED: arg2, expected \"Second\", got \"%0s\"", arg2); + pass = 1'b0; + end + + if (arg3[5*8:1] !== "Third") begin + $display("FAILED: arg3, expected \"Third\", got \"%0s\"", arg3); + pass = 1'b0; + end + + if (arg4 != 15) begin + $display("FAILED: arg4, expected 15, got %0d", arg4); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + + end +endmodule diff --git a/ivtest/ivltests/pr2728812a.v b/ivtest/ivltests/pr2728812a.v new file mode 100644 index 000000000..1f2bacc22 --- /dev/null +++ b/ivtest/ivltests/pr2728812a.v @@ -0,0 +1,50 @@ +`timescale 1ns/1ns + +module sum_test; + reg clk; + wire [10:0] s; + + initial begin + clk = 0; + forever #10 clk = ~clk; + end + + sum #(5, 8) sum (clk, {8'd10,8'd20,8'd30,8'd40,8'd50}, s); + + initial begin + $display("Starting..."); + repeat (50) @(posedge clk); + $display("sum = %d",s); + if (s !== 150) + $display("FAILED: expected 150, received %0d",s); + else + $display("PASSED"); + $finish; + end +endmodule + +module sum + #( + parameter n = 4, + parameter width = 8, + parameter log_n = $clog2(n) + ) + ( + input clk, + input [n*width-1:0]addends, + output reg [log_n+width-1:0] s + ); + + generate + if (n==1) + always @(*) s = addends; + else begin + wire [$clog2(n/2)+width-1:0] a1; + wire [$clog2(n-n/2)+width-1:0] a2; + sum #(n/2, width) s0 (clk, addends[(n/2)*width-1:0], a1); + sum #(n-n/2, width) s1 (clk, addends[n*width-1:(n/2)*width], a2); + always @(posedge clk) s <= a1 + a2; + end + endgenerate + +endmodule // sum diff --git a/ivtest/ivltests/pr2728812b.v b/ivtest/ivltests/pr2728812b.v new file mode 100644 index 000000000..dbe6180e0 --- /dev/null +++ b/ivtest/ivltests/pr2728812b.v @@ -0,0 +1,52 @@ +`timescale 1ns/1ns + +// Run this with -pRECURSIVE_MOD_LIMIT=5 to keep the output file small. +module sum_test; + reg clk; + wire [10:0] s; + + initial begin + clk = 0; + forever #10 clk = ~clk; + end + + sum #(5, 8) sum (clk, {8'd10,8'd20,8'd30,8'd40,8'd50}, s); + + initial begin + $display("Starting..."); + repeat (50) @(posedge clk); + $display("sum = %d",s); + if (s !== 150) + $display("FAILED: expected 150, received %0d",s); + else + $display("PASSED"); + $finish; + end +endmodule + +module sum + #( + parameter n = 4, + parameter width = 8, + parameter log_n = $clog2(n) + ) + ( + input clk, + input [n*width-1:0]addends, + output reg [log_n+width-1:0] s + ); + + generate + // This does not terminate and should fail after 100 loops. + if (n==-1) + always @(*) s = addends; + else begin + wire [$clog2(n/2)+width-1:0] a1; + wire [$clog2(n-n/2)+width-1:0] a2; + sum #(n/2, width) s0 (clk, addends[(n/2)*width-1:0], a1); + sum #(n-n/2, width) s1 (clk, addends[n*width-1:(n/2)*width], a2); + always @(posedge clk) s <= a1 + a2; + end + endgenerate + +endmodule // sum diff --git a/ivtest/ivltests/pr2728812c.v b/ivtest/ivltests/pr2728812c.v new file mode 100644 index 000000000..d101c5d1e --- /dev/null +++ b/ivtest/ivltests/pr2728812c.v @@ -0,0 +1,46 @@ +`timescale 1ns/1ns + +module sum_test; + reg clk; + wire [10:0] s; + + initial begin + clk = 0; + forever #10 clk = ~clk; + end + + sum #(5, 8) sum (clk, {8'd10,8'd20,8'd30,8'd40,8'd50}, s); + + initial begin + $display("Starting..."); + repeat (50) @(posedge clk); + $display("sum = %d",s); + if (s !== 150) + $display("FAILED: expected 150, received %0d",s); + else + $display("PASSED"); + $finish; + end +endmodule + +module sum + #( + parameter n = 4, + parameter width = 8, + parameter log_n = $clog2(n) + ) + ( + input clk, + input [n*width-1:0]addends, + output reg [log_n+width-1:0] s + ); + + // This should fail at the first recursion since this is not inside + // a generate block. + wire [$clog2(n/2)+width-1:0] a1; + wire [$clog2(n-n/2)+width-1:0] a2; + sum #(n/2, width) s0 (clk, addends[(n/2)*width-1:0], a1); + sum #(n-n/2, width) s1 (clk, addends[n*width-1:(n/2)*width], a2); + always @(posedge clk) s <= a1 + a2; + +endmodule // sum diff --git a/ivtest/ivltests/pr273.v b/ivtest/ivltests/pr273.v new file mode 100644 index 000000000..926f51922 --- /dev/null +++ b/ivtest/ivltests/pr273.v @@ -0,0 +1,64 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@telocity.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Test non-constant bit selects - causes compile error right now + +module test; + +reg clk; +reg [1:0] in0; +reg [1:0] in1; +reg sel0,sel1; +wire [1:0] q; + +dff2 u1 (q,clk,in0[sel0],in1[sel1]); + +initial + begin + clk = 0; + in0 = 2'b0; + in1 = 2'b0; + sel0 = 1'b0; + sel1 = 1'b1; + #8; + $display("initial val =%x",q); + #8; + if(q == 2'b0) + $display("PASSED"); + else + $display("FAILED"); + $finish ; + end + +always #5 clk = ~clk; + +endmodule + + +// This is just a dual dff +module dff2 (q,clk,d0,d1); + +input clk,d0,d1; +output [1:0] q; + +reg [1:0] q; + + always @(posedge clk) + q <= {d1,d0}; + +endmodule diff --git a/ivtest/ivltests/pr2745281.v b/ivtest/ivltests/pr2745281.v new file mode 100644 index 000000000..5139f0ba4 --- /dev/null +++ b/ivtest/ivltests/pr2745281.v @@ -0,0 +1,20 @@ +`define MERROR(code, msg) if (code == 0) begin $display(msg); end + +module top; + integer return_code; + integer msg_out; + + initial begin + // This shows that the macro is okay for the simple case + `MERROR(0, "This message works") + + // This one gives a syntax error. + `MERROR($value$plusargs("msgOut=%d", msg_out), "This message does not work") + + // This was a workaround + return_code = $value$plusargs("msgOut=%d", msg_out); + `MERROR(return_code, "This last message works") + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2781595.v b/ivtest/ivltests/pr2781595.v new file mode 100644 index 000000000..e0cc7d44a --- /dev/null +++ b/ivtest/ivltests/pr2781595.v @@ -0,0 +1,74 @@ +module xortest(out, a, b); + output out; + input a, b; + parameter tdelay=2; + wire a_, b_, i1, i2, i3; + + supply0 gnd; + supply1 vdd; + + nmos #(tdelay) n5(a_, gnd, a); + pmos #(tdelay) p5(a_, vdd, a); + + nmos #(tdelay) n6(b_, gnd, b); + pmos #(tdelay) p6(b_, vdd, b); + + + nmos #(tdelay) n1(out, i1, a); + nmos #(tdelay) n2(i1, gnd, b); + nmos #(tdelay) n3(out, i2, a_); + nmos #(tdelay) n4(i2, gnd, b_); + + pmos #(tdelay) p1(out, i3, a); + pmos #(tdelay) p2(out, i3, b); + pmos #(tdelay) p3(i3, vdd, a_); + pmos #(tdelay) p4(i3, vdd, b_); + +endmodule + +module testXor(); + wire out; + reg a, b; + reg pass; + + xortest x1(out, a, b); + + initial begin + pass = 1'b1; + a=1;b=1; + #100; $display("A=%b B=%b Out=%b",a,b,out); + a=0;b=1; + #100; $display("A=%b B=%b Out=%b",a,b,out); + a=1;b=0; + #100; $display("A=%b B=%b Out=%b",a,b,out); + a=0;b=0; + #100; $display("A=%b B=%b Out=%b",a,b,out); + + repeat (3) begin + a=0;b=1; + #100; $display("REP A=%b B=%b Out=%b",a,b,out); + a=1;b=0; + #100; $display("REP A=%b B=%b Out=%b",a,b,out); + end + + a=1;b=1; + #100; $display("A=%b B=%b Out=%b",a,b,out); + a=0;b=1; + #100; $display("A=%b B=%b Out=%b",a,b,out); + a=1;b=0; + #100; $display("A=%b B=%b Out=%b",a,b,out); + a=0;b=0; + #100; $display("A=%b B=%b Out=%b",a,b,out); + + if (pass) $display("PASSED"); + end + + always @(out) begin + // Wait for the value to settle. + #10 if (out !== (a ^ b)) begin + $display("Failed at %0t, expected %b, got %b, with a=%b, b=%b", + $time, a ^ b, out, a, b); + pass = 1'b0; + end + end +endmodule diff --git a/ivtest/ivltests/pr2785294.v b/ivtest/ivltests/pr2785294.v new file mode 100644 index 000000000..9d2efa9ea --- /dev/null +++ b/ivtest/ivltests/pr2785294.v @@ -0,0 +1,30 @@ +module top; + // The array code does not currently work because we need &APV<>! + // Both &PV<> and &APV<> (when implemented) need to have bit + // specific value change callbacks to function correctly. + reg [7:0] array [1:0]; + reg [7:0] bs, ps; + integer idx; + + initial begin + bs = 8'b0; + ps = 8'b0; + array[0] = 8'b0; + $monitor($time," BS = ", bs[1], ", PS = ", ps[2:1], ", AR = ", array[0][1]); + + // This should only trigger the $monitor when bit 1 changes. + for (idx = 0; idx < 8 ; idx = idx + 1) begin + #1 bs[idx] = 1'b1; + end + + // This should only trigger the $monitor when bit 1 or 2 changes. + for (idx = 0; idx < 8 ; idx = idx + 1) begin + #1 ps[idx] = 1'b1; + end + + // This should only trigger the $monitor when bit 1 of array[0] changes.. + for (idx = 0; idx < 8 ; idx = idx + 1) begin + #1 array[0][idx] = 1'b1; + end + end +endmodule diff --git a/ivtest/ivltests/pr2788686.v b/ivtest/ivltests/pr2788686.v new file mode 100644 index 000000000..fe41de6b2 --- /dev/null +++ b/ivtest/ivltests/pr2788686.v @@ -0,0 +1,76 @@ +module top; + reg pass; + reg [7:0] vec; + integer off; + time delay; + event trig; + + initial begin + pass = 1'b1; + delay = 1; + + // Assign before the vector (constant delay). + vec = 8'hff; + off = -1; + vec[off] <= #1 1'b0; + #2 if (vec !== 8'hff) begin + $display("Failed the before vector (C) test, expected 8'hff, got %h", + vec); + pass = 1'b0; + end + + // Assign after the vector (constant delay). + vec = 8'hff; + off = 8; + vec[off] <= #1 1'b0; + #2 if (vec !== 8'hff) begin + $display("Failed the after vector (C) test, expected 8'hff, got %h", + vec); + pass = 1'b0; + end + + // Assign before the vector (variable delay). + vec = 8'hff; + off = -1; + vec[off] <= #(delay) 1'b0; + #2 if (vec !== 8'hff) begin + $display("Failed the before vector (V) test, expected 8'hff, got %h", + vec); + pass = 1'b0; + end + + // Assign after the vector (variable delay). + vec = 8'hff; + off = 8; + vec[off] <= #(delay) 1'b0; + #2 if (vec !== 8'hff) begin + $display("Failed the after vector (V) test, expected 8'hff, got %h", + vec); + pass = 1'b0; + end + + // Assign before the vector (event trigger). + vec = 8'hff; + off = -1; + vec[off] <= @(trig) 1'b0; + ->trig; + #1 if (vec !== 8'hff) begin + $display("Failed the before vector (E) test, expected 8'hff, got %h", + vec); + pass = 1'b0; + end + + // Assign after the vector (event trigger). + vec = 8'hff; + off = 8; + vec[off] <= @(trig) 1'b0; + ->trig; + #1 if (vec !== 8'hff) begin + $display("Failed the after vector (V) test, expected 8'hff, got %h", + vec); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2790236.v b/ivtest/ivltests/pr2790236.v new file mode 100644 index 000000000..3fbab66f8 --- /dev/null +++ b/ivtest/ivltests/pr2790236.v @@ -0,0 +1,18 @@ +module test (a, b); + output a; + reg a = 1'b0; + output reg b = 1'b1; +endmodule + +module top; + wire out1, out2; + + test dut(out1, out2); + + initial begin + #1; + if (out1 !== 1'b0 || out2 !== 1'b1) begin + $display("Failed: expected 0:1, got %b:%b", out1, out2); + end else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2792883.v b/ivtest/ivltests/pr2792883.v new file mode 100644 index 000000000..5f1d7cccb --- /dev/null +++ b/ivtest/ivltests/pr2792883.v @@ -0,0 +1,9 @@ +module top; + parameter WIDTH = dut.WIDTH; + + test dut(); +endmodule + +module test; + parameter WIDTH = 8; +endmodule diff --git a/ivtest/ivltests/pr2792897.v b/ivtest/ivltests/pr2792897.v new file mode 100644 index 000000000..2b9bc5040 --- /dev/null +++ b/ivtest/ivltests/pr2792897.v @@ -0,0 +1,10 @@ +module top; + parameter parm = 1.4; + reg [31:0] str; + + initial begin + $sformat(str, "R: %d", parm); + if (str !== "R: 1") $display("FAILED: expected 'R: 1', got %s", str); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2792897_std.v b/ivtest/ivltests/pr2792897_std.v new file mode 100644 index 000000000..2e8c66b41 --- /dev/null +++ b/ivtest/ivltests/pr2792897_std.v @@ -0,0 +1,10 @@ +module top; + parameter parm = 1.4; + reg [31:0] str; + + initial begin + $sformat(str, "R: %d", parm); + if (str !== " 1") $display("FAILED: expected ' 1', got %s", str); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2794144.v b/ivtest/ivltests/pr2794144.v new file mode 100644 index 000000000..8c7def233 --- /dev/null +++ b/ivtest/ivltests/pr2794144.v @@ -0,0 +1,14 @@ +module top; + reg res; + reg [1:0] in; + + initial begin + in = 2'b00; + + res = ~ |in; + res = ~ ∈ + res = ~ ^in; + + $display("FAILED: These expressions should be a syntax error."); + end +endmodule diff --git a/ivtest/ivltests/pr2800985a.v b/ivtest/ivltests/pr2800985a.v new file mode 100644 index 000000000..3a813ce57 --- /dev/null +++ b/ivtest/ivltests/pr2800985a.v @@ -0,0 +1,389 @@ +/* + * Do some run time checks with $ferror(). We can not count on the return + * code or the strings to be the same on different machines so we can only + * look for the existence of an error and call that good enough. We humans + * can look at the full output to see if it is correct. + */ +module top; + parameter work_file = "work/pr2800985.txt"; + reg pass; + integer errno, bfd, vfd, mcd, res; + reg [639:0] result, str; + + /* + * Tasks to check and clear the error state. + */ + task check_error; + begin + // Check that there was an error. + if (errno == 0) begin + $display(" FAILED: expected an error!"); + pass = 1'b0; + end + clear_error; + end + endtask + + task clear_error; + begin + // Clear the error state. + res = $ftell(vfd); + errno = $ferror(vfd, result); + if (errno != 0) begin + $display("Failed to clear error state (%0s)", result); + $finish; + end + end + endtask + + initial begin + pass = 1'b1; + vfd = $fopen(work_file, "w+"); + if (vfd == 0) begin + errno = $ferror(vfd, result); + $display("Failed to open required file %s (%0s).", work_file, result); + $finish; + end + + /* + * $ferror() only takes a fd, so a valid MCD is not valid.. + */ + $display("Check a valid MCD."); + errno = $ferror(1, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + /* + * Basic $fopen() checking. + */ + $display("Opening a file that does not exist."); + bfd = $fopen("FileDoesNotExist", "r"); + $display(" $fopen returned: %h", bfd); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + +/* + * These do not work when the user has root privileges, so we need to + * just skip them. + * + $display("Opening a file that we should not be able to write to."); + bfd = $fopen("/FileDoesNotExist", "w"); + $display(" $fopen returned: %h", bfd); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + $display("Opening a file that we should not be able to write to (MCD)."); + mcd = $fopen("/FileDoesNotExist"); + $display(" $fopen returned: %h", mcd); + errno = $ferror(mcd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; +*/ + + $display("Opening a directory we should not be able to write."); + bfd = $fopen("/", "w"); + $display(" $fopen returned: %h", bfd); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + /* + * Check $fclose(). + */ + $display("Checking $fclose with fd 0 and -1."); + bfd = 0; + $fclose(bfd); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + bfd = -1; + $fclose(bfd); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + /* + * Check $fdisplay(), assume the b/h/o version work the same. + */ + $display("Checking $fdisplay with fd 0 and -1."); + bfd = 0; + $fdisplay(bfd); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + bfd = -1; + $fdisplay(bfd); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + /* + * Check $fwrite(), assume the b/h/o version work the same. + */ + $display("Checking $fwrite with fd 0 and -1."); + bfd = 0; + $fwrite(bfd); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + bfd = -1; + $fwrite(bfd); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + /* + * Check $fstrobe(), assume the b/h/o version work the same. + */ + $display("Checking $fstrobe with fd 0 and -1."); + bfd = 0; + $fstrobe(bfd); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + bfd = -1; + $fstrobe(bfd); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + /* + * Check $fgetc(). + */ + $display("Checking $fgetc with fd 0 and -1."); + bfd = 0; + res = $fgetc(bfd); + $display(" $fgetc returned: %0d", res); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + bfd = -1; + res = $fgetc(bfd); + $display(" $fgetc returned: %0d", res); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + + /* + * Check $ungetc(). + */ + $display("Checking $ungetc with fd 0 and -1 and char = EOF."); + bfd = 0; + res = $ungetc(0, bfd); + $display(" $ungetc returned: %0d", res); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + bfd = -1; + res = $ungetc(0, bfd); + $display(" $ungetc returned: %0d", res); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + // This returns EOF (-1), but does not set errno. + res = $ungetc(-1, vfd); + $display(" $ungetc returned: %0d", res); + errno = $ferror(vfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + if (res != -1 || errno != 0) begin + $display(" Failed expected result (-1, 0), got (%0d, %0d).", res, errno); + // It's OK if this returns a value in errno. + if (res != -1) pass = 1'b0; + clear_error; + end + + /* + * Check $fgets(). + */ + $display("Checking $fgets with fd 0 and -1."); + bfd = 0; + res = $fgets(str, bfd); + $display(" $fgets returned: %0d, '%0s'", res, str); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + bfd = -1; + res = $fgets(str, bfd); + $display(" $fgets returned: %0d, '%0s'", res, str); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + /* + * Check $fscanf(). + */ + $display("Checking $fscanf with fd 0 and -1."); + bfd = 0; + res = $fscanf(bfd, "%s", str); + $display(" $fscanf returned: %0d, '%0s'", res, str); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + bfd = -1; + res = $fscanf(bfd, "%s", str); + $display(" $fscanf returned: %0d, '%0s'", res, str); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + /* + * Check $fread(). + */ + $display("Checking $fread with fd 0 and -1."); + bfd = 0; + res = $fread(str, bfd); + $display(" $fread returned: %0d, '%0s'", res, str); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + bfd = -1; + res = $fread(str, bfd); + $display(" $fread returned: %0d, '%0s'", res, str); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + /* + * Check $ftell(). + */ + $display("Checking $ftell with fd 0 and -1."); + bfd = 0; + res = $ftell(bfd); + $display(" $ftell returned: %0d", res); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + bfd = -1; + res = $ftell(bfd); + $display(" $ftell returned: %0d", res); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + /* + * Check $fseek(). + */ + $display("Checking $fseek."); + bfd = 0; + res = $fseek(bfd, 0, 0); + $display(" $fseek returned: %0d", res); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + bfd = -1; + res = $fseek(bfd, 0, 0); + $display(" $fseek returned: %0d", res); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + // A valid fd, but an invalid operation. + res = $fseek(vfd, 0, 4); + $display(" $fseek returned: %0d", res); + errno = $ferror(vfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + /* + * Check $rewind(). + */ + $display("Checking $rewind with fd 0 and -1."); + bfd = 0; + res = $rewind(bfd); + $display(" $rewind returned: %0d", res); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + bfd = -1; + res = $rewind(bfd); + $display(" $rewind returned: %0d", res); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + /* + * Check $fflush(). + */ + $display("Checking $fflush with fd 0 and -1."); + bfd = 0; + $fflush(bfd); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + bfd = -1; + $fflush(bfd); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + /* + * Check $feof(). + */ + $display("Checking $feof with fd 0 and -1."); + bfd = 0; + res = $feof(bfd); + $display(" $feof returned: %0d", res); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + bfd = -1; + res = $feof(bfd); + $display(" $feof returned: %0d", res); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + + /* + * Check $fputc() (Icarus specific). + */ +`ifdef __ICARUS__ + $display("Checking $fputc with fd 0 and -1."); + bfd = 0; + res = $fputc(0, bfd); + $display(" $fputc returned: %0d", res); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; + bfd = -1; + res = $fputc(0, bfd); + $display(" $fputc returned: %0d", res); + errno = $ferror(bfd, result); + $display(" $ferror returned: %0d, '%0s'", errno, result); + check_error; +`endif + + /* + * Check that $fstrobe does not access a file after it is closed. + */ + $display("Checking $fstrobe after $fclose."); + res = $rewind(vfd); + if (res != 0) begin + $display("Failed to rewind file"); + $finish; + end + $fwrite(vfd, "test-"); + $fstrobe(vfd, "FAILED"); + $fclose(vfd); + vfd = $fopen(work_file, "r"); + if (vfd == 0) begin + errno = $ferror(vfd, result); + $display("Failed to open required file %s (%0s).", work_file, result); + $finish; + end + res = $fgets(str, vfd); + if (res == 0) begin + errno = $ferror(vfd, result); + $display("Failed to read back result (%0s)", result); + str = "failed"; + end + if (str !== "test-") begin + $display("$fstrobe was not skipped, expected 'test-', got '%0s'", str); + pass = 1'b0; + end + $fclose(vfd); + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2800985b.v b/ivtest/ivltests/pr2800985b.v new file mode 100644 index 000000000..b9dccf7b9 --- /dev/null +++ b/ivtest/ivltests/pr2800985b.v @@ -0,0 +1,17 @@ +/* + * Check $ferror() compile time errors. + */ +module top; + integer errno, fd; + reg [639:0] result; + reg [63:0] sresult; + + initial begin + fd = 0; + errno = $ferror("string", result); // Invalid first argument. + errno = $ferror(fd); // Missing second argument. + errno = $ferror(fd, "string"); // Invalid second argument. + errno = $ferror(fd, sresult); // Second argument is too small. + errno = $ferror(fd, result, "xx"); // Extra arguments. + end +endmodule diff --git a/ivtest/ivltests/pr2801134.v b/ivtest/ivltests/pr2801134.v new file mode 100644 index 000000000..319a1527d --- /dev/null +++ b/ivtest/ivltests/pr2801134.v @@ -0,0 +1,57 @@ +module top; + parameter a_res = 16'b000001xx0xxx0xxx; + parameter o_res = 16'b01xx1111x1xxx1xx; + parameter x_res = 16'b01xx10xxxxxxxxxx; + reg pass; + reg [15:0] y, z, a, o, x; + reg [127:0] yl, zl, al, ol, xl; + initial begin + pass = 1'b1; + + y = 16'b01xz01xz01xz01xz; + z = 16'b00001111xxxxzzzz; + yl = {8{y}}; + zl = {8{z}}; + + // Check the & results + a = y & z; + if (a !== a_res) begin + $display("FAILED: & test, expected %b, got %b", a_res, a); + pass = 1'b0; + end + + al = yl & zl; + if (al !== {8{a_res}}) begin + $display("FAILED: & (large) test, expected %b, got %b", {8{a_res}}, al); + pass = 1'b0; + end + + // Check the | results + o = y | z; + if (o !== o_res) begin + $display("FAILED: | test, expected %b, got %b", o_res, o); + pass = 1'b0; + end + + ol = yl | zl; + if (ol !== {8{o_res}}) begin + $display("FAILED: | (large) test, expected %b, got %b", {8{o_res}}, ol); + pass = 1'b0; + end + + // Check the ^ results + x = y ^ z; + if (x !== x_res) begin + $display("FAILED: | test, expected %b, got %b", x_res, x); + pass = 1'b0; + end + + xl = yl ^ zl; + if (xl !== {8{x_res}}) begin + $display("FAILED: ^ (large) test, expected %b, got %b", {8{x_res}}, xl); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2801662.v b/ivtest/ivltests/pr2801662.v new file mode 100644 index 000000000..3dd8c2d13 --- /dev/null +++ b/ivtest/ivltests/pr2801662.v @@ -0,0 +1,25 @@ +`timescale 1ns/1ps +module test; + reg in, pass; + wire out; + + assign #(1?2:1) out = in; +// assign #(1+1) out = in; + + initial begin + pass = 1'b1; + in = 1'b0; + #1.999; + if (out !== 1'bx) begin + $display("Failed signal at begining, expected 1'bx, got %b", out); + pass = 1'b0; + end + #0.002; + if (out !== in) begin + $display("Failed signal at end, expected %b, got %b", in, out); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2806449.v b/ivtest/ivltests/pr2806449.v new file mode 100644 index 000000000..369206d35 --- /dev/null +++ b/ivtest/ivltests/pr2806449.v @@ -0,0 +1,13 @@ +module top; + reg[63:0] a; + + initial begin + a = 64'h7fe8000000000000; + // This used to fail because we printed floating point using + // the default buffer which was only 256 bytes long. To fix + // this the default size was changed to 512 bytes and this is + // increased when needed (%400.300f, etc.). + $display("%6.3f", $bitstoreal(a)); + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2806474.v b/ivtest/ivltests/pr2806474.v new file mode 100644 index 000000000..d4fac5645 --- /dev/null +++ b/ivtest/ivltests/pr2806474.v @@ -0,0 +1,79 @@ +module top; + reg pass; + + real a, b; + integer i; + + wire real b1 = 42.0 + 10/100; + wire real b2 = a + 10/100; + wire real b3 = 42.0 + i/100; + wire real b4 = a + i/100; + + initial begin + pass = 1'b1; + + // Check the compiler for the whole expression. + b = 42.0 + 10/100; + if (b != 42.0) begin + $display("FAILED: compiler constant, expected 42.0, got %6.1f", b); + pass = 1'b0; + end + + // Check the compiler for just the division. + a = 42; + b = a + 10/100; + if (b != 42.0) begin + $display("FAILED: compiler constant div., expected 42.0, got %6.1f", b); + pass = 1'b0; + end + + // Check the run time with a constant sum value (just the division). + i = 10; + b = 42.0 + i/100; + if (b != 42.0) begin + $display("FAILED: runtime constant real, expected 42.0, got %6.1f", b); + pass = 1'b0; + end + + // Check the original expression. + b = a + i/100; + if (b != 42.0) begin + $display("FAILED: runtime, expected 42.0, got %6.1f", b); + pass = 1'b0; + end + + // Check the ternary operator with one clause needing to be converted. + b = (i === 10) ? i/100 : 1.0; + if (b != 0.0) begin + $display("FAILED: runtime (ternary), expected 0.0, got %6.1f", b); + pass = 1'b0; + end + + b = |i; + if (b != 1.0) begin + $display("FAILED: runtime (reduction), expected 1.0, got %6.1f", b); + pass = 1'b0; + end + + // Check the continuous assigns. + #1; + if (b1 != 42.0) begin + $display("FAILED: CA test 1, expected 42.0, got %6.1f", b1); + pass = 1'b0; + end + if (b2 != 42.0) begin + $display("FAILED: CA test 2, expected 42.0, got %6.1f", b2); + pass = 1'b0; + end + if (b3 != 42.0) begin + $display("FAILED: CA test 3, expected 42.0, got %6.1f", b3); + pass = 1'b0; + end + if (b4 != 42.0) begin + $display("FAILED: CA test 4, expected 42.0, got %6.1f", b4); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2809288.v b/ivtest/ivltests/pr2809288.v new file mode 100644 index 000000000..bf041c8cd --- /dev/null +++ b/ivtest/ivltests/pr2809288.v @@ -0,0 +1,11 @@ +module top; + integer i = 0; + + generate + for(i=0; i<4; i=i+1) begin:U + reg [1:0] a = i; + end + endgenerate + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/pr2815398a.v b/ivtest/ivltests/pr2815398a.v new file mode 100644 index 000000000..1c1e78239 --- /dev/null +++ b/ivtest/ivltests/pr2815398a.v @@ -0,0 +1,71 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + reg [2:0] res [0:7]; + reg [2:0] in [0:7]; + reg [7:0] dummy [0:6]; + time run_time [0:7]; + time exp_time [0:7]; + integer i; + + initial begin + pass = 1'b1; + #1; + // Initialize the input array. + for (i=0; i<8; i=i+1) begin + in[i] = i[2:0]; + end + #1; + for (i=0; i<8; i=i+1) begin + exp_time[i] = $time-1; + end + check; + + // We only have 6 dummy items, check that each triggers correctly. + for (i=0; i<7; i=i+1) begin + dummy[i] = 1'b0; + #1; + exp_time[i] = $time-1; + check; + end + + if (pass) $display("PASSED"); + end + + // Check that the value and time are correct. + task check; + integer j; + begin + for (j=0; j<8; j=j+1) begin + if (res[j] !== j[2:0]) begin + $display("FAILED: index %0d value, at %2t, expexted %b, got %b.", + j, $time, j[2:0], res[j]); + pass = 1'b0; + end + if (run_time[j] !== exp_time[j]) begin + $display("FAILED: index %0d time, at %2t, expexted %2t, got %2t.", + j, $time, exp_time[j], run_time[j]); + pass = 1'b0; + end + end + end + endtask + + genvar m; + generate +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + for (m=0; m<=7; m=m+1) begin: idac_loop +`else + for (m=0; m<=6; m=m+1) begin: idac_loop +`endif + // This should complain that dummy[7] is out of bounds. + always @ (in[m] or dummy[m]) begin + res[m] = in[m]; + run_time[m] = $time; + end + end + endgenerate +endmodule diff --git a/ivtest/ivltests/pr2815398a_std.v b/ivtest/ivltests/pr2815398a_std.v new file mode 100644 index 000000000..d38a45322 --- /dev/null +++ b/ivtest/ivltests/pr2815398a_std.v @@ -0,0 +1,71 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + reg [2:0] res [0:7]; + reg [2:0] in [0:7]; + reg [7:0] dummy [0:6]; + time run_time [0:7]; + time exp_time [0:7]; + integer i; + + initial begin + pass = 1'b1; + #1; + // Initialize the input array. + for (i=0; i<8; i=i+1) begin + in[i] = i[2:0]; + end + #1; + for (i=0; i<8; i=i+1) begin + exp_time[i] = $time-1; + end + check; + + // We only have 6 dummy items, check that each triggers correctly. + for (i=0; i<7; i=i+1) begin + dummy[i] = 1'b0; + #1; + exp_time[i] = $time-1; + check; + end + + if (pass) $display("PASSED"); + end + + // Check that the value and time are correct. + task check; + integer j; + begin + for (j=0; j<8; j=j+1) begin + if (res[j] !== j[2:0]) begin + $display("FAILED: index %0d value, at %t, expexted %b, got %b.", + j, $time, j[2:0], res[j]); + pass = 1'b0; + end + if (run_time[j] !== exp_time[j]) begin + $display("FAILED: index %0d time, at %t, expexted %t, got %t.", + j, $time, exp_time[j], run_time[j]); + pass = 1'b0; + end + end + end + endtask + + genvar m; + generate +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + for (m=0; m<=7; m=m+1) begin: idac_loop +`else + for (m=0; m<=6; m=m+1) begin: idac_loop +`endif + // This should complain that dummy[7] is out of bounds. + always @ (in[m] or dummy[m]) begin + res[m] = in[m]; + run_time[m] = $time; + end + end + endgenerate +endmodule diff --git a/ivtest/ivltests/pr2815398b.v b/ivtest/ivltests/pr2815398b.v new file mode 100644 index 000000000..03ae2c24a --- /dev/null +++ b/ivtest/ivltests/pr2815398b.v @@ -0,0 +1,42 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + wire [2:0] arr [0:7]; + reg rarr [0:7]; + integer i; + + initial begin + pass = 1'b1; + #1; + for (i = 0; i <=7 ; i = i + 1) begin + if (arr[i] !== i) begin + $display("FAILED: index %1d, expected %1d, got %1d", i, i, arr[i]); + pass = 1'b0; + end + end + + if (pass) $display("PASSED"); + end + + // This should display a warning and just ignore the whole statement. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign arr[20] = 'b0; + assign arr[-1] = 'b0; +`endif + + + genvar m; + generate + // This like above should warn when 8 <= m <= 15. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + for (m=0; m<=15; m=m+1) begin: arr_loop +`else + for (m=0; m<=7; m=m+1) begin: arr_loop +`endif + assign arr[m] = m; + end + endgenerate +endmodule diff --git a/ivtest/ivltests/pr2818823.v b/ivtest/ivltests/pr2818823.v new file mode 100644 index 000000000..ade6546cf --- /dev/null +++ b/ivtest/ivltests/pr2818823.v @@ -0,0 +1,36 @@ +module top; + parameter C1 = 1.0e-6; + + reg pass; + real rval; + real exp_result; + + initial begin + pass = 1'b1; + exp_result = -1000000.0; + + // Check with a constant and a parameter. + rval = -1 / C1; + if (rval != exp_result) begin + $display ("FAILED: -1/%f gave %f, expected %f", C1, rval, exp_result); + pass = 1'b0; + end + + // Check with both constants. + rval = -1 / 1.0e-6; + if (rval != exp_result) begin + $display ("FAILED: -1/1.0e-6 gave %f, expected %f", rval, exp_result); + pass = 1'b0; + end + + // Check with a positive value. + exp_result = 1000000.0; + rval = 1 / C1; + if (rval != exp_result) begin + $display ("FAILED: 1/%f gave %f, not expected %f", C1, rval, exp_result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2823414.v b/ivtest/ivltests/pr2823414.v new file mode 100644 index 000000000..13ebceee2 --- /dev/null +++ b/ivtest/ivltests/pr2823414.v @@ -0,0 +1,13 @@ +module top; + + initial begin +`ifdef CAUSES_PROBLEM + /* + * C-Style comment in a skipped `ifdef is loosing the '\n'. + */ +`endif + // This should report an error at line 10. + fail_at_line_10(); + end + +endmodule diff --git a/ivtest/ivltests/pr2823711.v b/ivtest/ivltests/pr2823711.v new file mode 100644 index 000000000..ab631f03b --- /dev/null +++ b/ivtest/ivltests/pr2823711.v @@ -0,0 +1,30 @@ +// The basic example is from 1364-2005 +module top; + reg pass; + reg [3:0] a; + reg [5:0] b; + reg [15:0] c; + + initial begin + pass = 1'b1; + + a = 4'hF; + b = 6'hA; + + // Self-determined context so the width is the same as a (4 bits). + c = { a**b }; + if (c !== 16'h0001) begin + $display("FAILED self-determined power, expected 0001, got %h", c); + pass = 1'b0; + end + + // The width is determined by a and c so use 16 bits here. + c = a**b; + if (c !== 16'hac61) begin + $display("FAILED context-determined power, expected ac61, got %h", c); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2824189.txt b/ivtest/ivltests/pr2824189.txt new file mode 100644 index 000000000..789819226 --- /dev/null +++ b/ivtest/ivltests/pr2824189.txt @@ -0,0 +1 @@ +a diff --git a/ivtest/ivltests/pr2824189.v b/ivtest/ivltests/pr2824189.v new file mode 100644 index 000000000..190c63af1 --- /dev/null +++ b/ivtest/ivltests/pr2824189.v @@ -0,0 +1,31 @@ +`begin_keywords "1364-2005" +module top; + reg pass; + reg [3:0] var; + integer fd, code; + + initial begin + pass = 1'b1; + fd = $fopen("ivltests/pr2824189.txt", "r"); + code = $fscanf(fd, "%x\n", var); + if (code != 1) begin + $display("Failed initial variable read count expected 1, got %d", code); + pass = 1'b0; + end + if (var !== 4'ha) begin + $display("Failed initial variable read value expected a, got %h", var); + pass = 1'b0; + end + + code = $fscanf(fd, "%x\n", var); + if (code != -1) begin + $display("Failed $fscanf() at EOF"); + pass = 1'b0; + end + + $fclose(fd); + + if (pass) $display("PASSED"); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr2829776.v b/ivtest/ivltests/pr2829776.v new file mode 100644 index 000000000..2a1c7b610 --- /dev/null +++ b/ivtest/ivltests/pr2829776.v @@ -0,0 +1,120 @@ +module top; + reg in1, in2, pass, checkc, checkg, checkp; + wire outc, outg, outp; + + assign #400 outc = in1 | in2; + or #400 g1(outg, in1, in2); + my_or #400 g2(outp, in1, in2); + + initial begin +// $monitor($time,,outc, outg, outp,, in1,, in2); + pass = 1'b1; + checkc = 1'b0; + checkg = 1'b0; + checkp = 1'b0; + in1 = 1'b0; + in2 = 1'b0; + #100 in1 = 1'b1; + #200 in2 = 1'b1; + #199; + // Check to see if the output changed early. + if (outc !== 1'bz && outc !== 1'bx) begin + $display("CA output changed early!"); + pass = 1'b0; + end + if (outg !== 1'bz && outg !== 1'bx) begin + $display("Gate output changed early!"); + pass = 1'b0; + end + if (outp !== 1'bz && outp !== 1'bx) begin + $display("UDP output changed early!"); + pass = 1'b0; + end + #2; + // Check to see if the output changed late. + if (outc !== 1'b1) begin + $display("CA output changed late!"); + pass = 1'b0; + checkc = 1'b1; + end + if (outg !== 1'b1) begin + $display("Gate output changed late!"); + pass = 1'b0; + checkg = 1'b1; + end + if (outp !== 1'b1) begin + $display("UDP output changed late!"); + pass = 1'b0; + checkp = 1'b1; + end + #198; + // We need to execute the three if checks in parallel. + fork + if (checkc) begin + if (outc === 1'bz || outc === 1'bx) begin + #2; + // Check to see if the output changed off of the wrong edge. + if (outc === 1'b1) + $display("CA output triggered off of in2 change instead of in1."); + else + $display("CA output triggered very late."); + end + end + if (checkg) begin + if (outg === 1'bz || outg === 1'bx) begin + #2; + // Check to see if the output changed off of the wrong edge. + if (outg === 1'b1) + $display("Gate output triggered off of in2 change instead of in1."); + else + $display("Gate output triggered very late."); + end + end + if (checkp) begin + if (outp === 1'bz || outp === 1'bx) begin + #2; + // Check to see if the output changed off of the wrong edge. + if (outp === 1'b1) + $display("UDP output triggered off of in2 change instead of in1."); + else + $display("UDP output triggered very late."); + end + end + #2; // This keeps the passing case alligned with the fails. + join + + // Generate a 399 wide negative pulse that should be skipped. + in1 = 1'b0; + in2 = 1'b0; + #399; + in1 = 1'b1; + in2 = 1'b1; + #2; + // Check that the pulse did not propagate. + if (outc !== 1'b1) begin + $display("CA does not have inertial delay."); + pass = 1'b0; + end + if (outg !== 1'b1) begin + $display("Gate does not have inertial delay."); + pass = 1'b0; + end + if (outp !== 1'b1) begin + $display("UDP does not have inertial delay."); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule + +primitive my_or (out, in1, in2); + output out; + input in1, in2; + + table + 0 0 : 0; + 1 ? : 1; + ? 1 : 1; + endtable +endprimitive diff --git a/ivtest/ivltests/pr2829776b.v b/ivtest/ivltests/pr2829776b.v new file mode 100644 index 000000000..458f5bc3e --- /dev/null +++ b/ivtest/ivltests/pr2829776b.v @@ -0,0 +1,62 @@ +`timescale 1ns/1ps + +module top; + reg pass; + reg ina, inb; + wire out; + + my_or dut(out, ina, inb); + + initial begin + pass = 1'b1; + ina = 1'b0; + inb = 1'b0; + #0.399 + if (out !== 1'bx && out !== 1'bz) begin + $display("FAILED: gate had incorrect delay, expected x/z, got %b.", out); + pass = 1'b0; + end + #0.002 + if (out !== 1'b0) begin + $display("FAILED: gate had incorrect delay, expected 0, got %b.", out); + pass = 1'b0; + end + + // Check inertial delays. + ina = 1'b1; + #0.399 + ina = 1'b0; + #0.002 + if (out !== 1'b0) begin + $display("FAILED: inertial delay, expected 0, got %b.", out); + pass = 1'b0; + end + + // Check that this change is relative to the first edge. + ina = 1'b1; + #0.200; + inb = 1'b1; + #0.201; + if (out !== 1'b1) begin + $display("FAILED: double edge delay, expected 1, got %b.", out); + pass = 1'b0; + #0.200; + if (out === 1'b1) begin + $display("FAILED: double edge delay was off second edge."); + end + end + + if (pass) $display("PASSED"); + end +endmodule + +module my_or(out, ina, inb); + output out; + input ina, inb; + + or(out, ina, inb); + + specify + (ina, inb *> out) = 0.4; + endspecify +endmodule diff --git a/ivtest/ivltests/pr2832234.v b/ivtest/ivltests/pr2832234.v new file mode 100644 index 000000000..a00b784ae --- /dev/null +++ b/ivtest/ivltests/pr2832234.v @@ -0,0 +1,113 @@ +/* + * There are a number of problem that this example uncovers. + * + * It appears that the inverter connected to the ctl input of the + * tranif gate is not getting the signal passed to it. It looks + * like once the ctl signal is pulled into the island it can not + * propagate the signal back out. The fix may be in the compiler + * where we should only use the island port signal for the tranif + * control instead of any signal that connects to the ctl net. + * + * When the ctl signal removes the connection between the two + * nets they should self resolve. Is appears that when the ctl + * signal is removed the nets stay at their current value. + */ +module top; + reg pass; + reg ctl, ctl2, in, in2; + wire y1, y2, ctlb, y2b; + + assign y1 = in; + pullup (weak1) (y2); + + tranif0 q1(y1, y2, ctl); + + assign y2 = ctl2 ? in2 : 1'bz; + + not q2(ctlb, ctl); + not q3(y2b, y2); + + initial begin + pass = 1'b1; + // The tran gate is closed and both sides should track 'in'. + ctl = 1'b0; + ctl2 = 1'b0; + in = 1'b1; + #1; + if (ctlb !== 1'b1) begin + $display("Failed ctlb with ctl = 0, expected 1'b1, got %b", ctlb); + pass = 1'b0; + end + if (y2 !== 1'b1) begin + $display("Failed tran with ctl = 0, in = 1, expected 1'b1, got %b", y2); + pass = 1'b0; + end + if (y2b !== 1'b0) begin + $display("Failed y2b with ctl = 0, in = 1, expected 1'b0, got %b", y2b); + pass = 1'b0; + end + in = 1'b0; + #1; + if (y2 !== 1'b0) begin + $display("Failed tran with ctl = 0, in = 0, expected 1'b0, got %b", y2); + pass = 1'b0; + end + if (y2b !== 1'b1) begin + $display("Failed y2b with ctl = 0, in = 0, expected 1'b1, got %b", y2b); + pass = 1'b0; + end + + // The tran gate is open so y2 should go high (pullup). + ctl = 1'b1; + #1; + if (ctlb !== 1'b0) begin + $display("Failed ctlb with ctl = 1, expected 1'b0, got %b", ctlb); + pass = 1'b0; + end + if (y2 !== 1'b1) begin + $display("Failed tran with ctl = 1, expected 1'b1, got %b", y2); + pass = 1'b0; + end + if (y2b !== 1'b0) begin + $display("Failed y2b with ctl = 1, expected 1'b0, got %b", y2b); + pass = 1'b0; + end + + // Now try driving y2 from in2. + ctl2 = 1'b1; + in2 = 1'b1; + #1; + if (y2 !== 1'b1) begin + $display("Failed tran with ctl2 = 1, in2 = 1, expected 1'b1, got %b", y2); + pass = 1'b0; + end + if (y2b !== 1'b0) begin + $display("Failed y2b with ctl2 = 1, in2 = 1, expected 1'b0, got %b", y2b); + pass = 1'b0; + end + in2 = 1'b0; + #1; + if (y2 !== 1'b0) begin + $display("Failed tran with ctl2 = 1, in2 = 0, expected 1'b0, got %b", y2); + pass = 1'b0; + end + if (y2b !== 1'b1) begin + $display("Failed y2b with ctl2 = 1, in2 = 0, expected 1'b1, got %b", y2b); + pass = 1'b0; + end + + // Now back to just a pullup on y2. + ctl2 = 1'b0; + #1; + if (y2 !== 1'b1) begin + $display("Failed tran with ctl2 = 0, expected 1'b1, got %b", y2); + pass = 1'b0; + end + if (y2b !== 1'b0) begin + $display("Failed y2b with ctl2 = 0, expected 1'b0, got %b", y2b); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2834340.v b/ivtest/ivltests/pr2834340.v new file mode 100644 index 000000000..dd1b87c71 --- /dev/null +++ b/ivtest/ivltests/pr2834340.v @@ -0,0 +1,48 @@ +//`timescale 1ns/1ps + +module test; + +reg c1reg,c2reg; +pulldown (weak0) pd1 (r1a,r1c,r1o); +pulldown (weak0) pd2 (r2a,r2c,r2o); + +pulldown pd (r1a); +pullup pu (r2a); + +wire c1 = c1reg; +wire c2 = c2reg; +SPDT_RELAY r1 (.COIL1(c1), .COIL2(c2), .ARM(r1a), .NC(r1c), .NO(r1o)); +SPDT_RELAY r2 (.COIL1(c1), .COIL2(c2), .ARM(r2a), .NC(r2c), .NO(r2o)); + +initial +begin + c1reg = 0; + c2reg = 0; + repeat (16) + begin + c1reg = 1; + #10; + c1reg = 0; + #10; + end + $display ("%t: Test passed.",$realtime); + $display ("PASSED"); + $finish; +end +endmodule + + +module SPDT_RELAY (COIL1, COIL2, ARM, NC, NO); +inout COIL1, COIL2, ARM, NC, NO; +wire coil = ((COIL1===1'b1) && (COIL2===1'b0)) || ((COIL1===1'b0) && (COIL2===1'b1)); + +wire #1 dly_coil = coil; +wire coil_on = coil & dly_coil; +wire coil_off = !coil & !dly_coil; + +//assign NC = (coil_off) ? ARM : 1'bz; +//assign NO = (coil_on) ? ARM : 1'bz; + +tranif1 t1 (ARM,NC,coil_off); +tranif1 t2 (ARM,NO,coil_on); +endmodule diff --git a/ivtest/ivltests/pr2834340b.v b/ivtest/ivltests/pr2834340b.v new file mode 100644 index 000000000..34654b89e --- /dev/null +++ b/ivtest/ivltests/pr2834340b.v @@ -0,0 +1,99 @@ +`timescale 1ns/1ps + +module test; + + reg pass; + reg c1reg,c2reg; + wire rla, rlc, rlo; + wire rha, rhc, rho; + wire c1 = c1reg; + wire c2 = c2reg; + + // Pull the pins opposite to the arm. + pulldown pd1 (rla); + pullup (weak1) pu1 (rlc,rlo); + + pulldown (weak0) pd2 (rhc,rho); + pullup pu2 (rha); + + SPDT_RELAY rl (.COIL1(c1), .COIL2(c2), .ARM(rla), .NC(rlc), .NO(rlo)); + SPDT_RELAY rh (.COIL1(c1), .COIL2(c2), .ARM(rha), .NC(rhc), .NO(rho)); + + initial begin + pass = 1'b1; + + // Test both coil terminals low. + c1reg = 0; + c2reg = 0; + #10; + if (rla !== 1'b0 || rlo !== 1'b1 || rlc !== 1'b0) begin + $display("Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b", + c1, c2, rla, rlc, rlo); + pass = 1'b0; + end + if (rha !== 1'b1 || rho !== 1'b0 || rhc !== 1'b1) begin + $display("Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b", + c1, c2, rha, rhc, rho); + pass = 1'b0; + end + + // Test c1 low and c2 high. + c2reg = 1; + #10; + if (rla !== 1'b0 || rlo !== 1'b0 || rlc !== 1'b1) begin + $display("Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b", + c1, c2, rla, rlc, rlo); + pass = 1'b0; + end + if (rha !== 1'b1 || rho !== 1'b1 || rhc !== 1'b0) begin + $display("Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b", + c1, c2, rha, rhc, rho); + pass = 1'b0; + end + + // Test both coil terminal high. + c1reg = 1; + #10; + if (rla !== 1'b0 || rlo !== 1'b1 || rlc !== 1'b0) begin + $display("Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b", + c1, c2, rla, rlc, rlo); + pass = 1'b0; + end + if (rha !== 1'b1 || rho !== 1'b0 || rhc !== 1'b1) begin + $display("Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b", + c1, c2, rha, rhc, rho); + pass = 1'b0; + end + + // Test c1 high and c2 low. + c2reg = 0; + #10; + if (rla !== 1'b0 || rlo !== 1'b0 || rlc !== 1'b1) begin + $display("Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b", + c1, c2, rla, rlc, rlo); + pass = 1'b0; + end + if (rha !== 1'b1 || rho !== 1'b1 || rhc !== 1'b0) begin + $display("Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b", + c1, c2, rha, rhc, rho); + pass = 1'b0; + end + + if (pass) $display ("PASSED"); + $finish; + end +endmodule + + +module SPDT_RELAY (COIL1, COIL2, ARM, NC, NO); + inout COIL1, COIL2, ARM, NC, NO; + wire coil = ((COIL1===1'b1) && (COIL2===1'b0)) || + ((COIL1===1'b0) && (COIL2===1'b1)); + + wire #1 dly_coil = coil; + wire coil_on = coil & dly_coil; + wire coil_off = !coil & !dly_coil; + + tranif1 t1 (ARM,NC,coil_off); + tranif1 t2 (ARM,NO,coil_on); +endmodule diff --git a/ivtest/ivltests/pr2835632a.v b/ivtest/ivltests/pr2835632a.v new file mode 100644 index 000000000..b2e1ff1b2 --- /dev/null +++ b/ivtest/ivltests/pr2835632a.v @@ -0,0 +1,857 @@ +// This checks various constant selects using the indexed select operators +// +: and -: for both big and little endian vectors. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + parameter base = -1; + + parameter [base+15:base] p_big = 16'h0123; + parameter [base:base+15] p_ltl = 16'h3210; + parameter p_base = 16'h0123; + + reg [base+15:base] big = 16'h0123; + reg [base:base+15] ltl = 16'h3210; + reg [base+15:base] big_l; + reg [base:base+15] ltl_l; + + wire [base+15:base] w_big = 16'h0123; + wire [base:base+15] w_ltl = 16'h3210; + + reg [3:0] big0, big1, big2, big3, ltl0, ltl1, ltl2, ltl3; + reg [3:0] big0a, big3a, bigx, bigo, ltl0a, ltl3a, ltlx, ltlo; + + reg pass; + + /* + * Check a constant +: as a CA R-value. + */ +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + wire [3:0] wcu_big3a = w_big[(base-1)+:4]; +`else + wire [3:0] wcu_big3a = {w_big[(base)+:3],1'bx}; +`endif + wire [3:0] wcu_big3 = w_big[(base)+:4]; + wire [3:0] wcu_big2 = w_big[(base+4)+:4]; + wire [3:0] wcu_big1 = w_big[(base+8)+:4]; + wire [3:0] wcu_big0 = w_big[(base+12)+:4]; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + wire [3:0] wcu_big0a = w_big[(base+13)+:4]; + wire [3:0] wcu_bigx = w_big[(1'bx)+:4]; + wire [3:0] wcu_ltl3a = w_ltl[(base-1)+:4]; +`else + wire [3:0] wcu_big0a = {1'bx,w_big[(base+13)+:3]}; + wire [3:0] wcu_bigx = 4'bxxxx; + wire [3:0] wcu_ltl3a = {1'bx,w_ltl[(base)+:3]}; +`endif + wire [3:0] wcu_ltl3 = w_ltl[(base)+:4]; + wire [3:0] wcu_ltl2 = w_ltl[(base+4)+:4]; + wire [3:0] wcu_ltl1 = w_ltl[(base+8)+:4]; + wire [3:0] wcu_ltl0 = w_ltl[(base+12)+:4]; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + wire [3:0] wcu_ltl0a = w_ltl[(base+13)+:4]; + wire [3:0] wcu_ltlx = w_ltl[(1'bx)+:4]; +`else + wire [3:0] wcu_ltl0a = {w_ltl[(base+13)+:3],1'bx}; + wire [3:0] wcu_ltlx = 4'bxxxx; +`endif + + /* + * Check a constant -: as a CA R-value. + */ +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + wire [3:0] wcd_big3a = w_big[(base+2)-:4]; +`else + wire [3:0] wcd_big3a = {w_big[(base+2)-:3],1'bx}; +`endif + wire [3:0] wcd_big3 = w_big[(base+3)-:4]; + wire [3:0] wcd_big2 = w_big[(base+7)-:4]; + wire [3:0] wcd_big1 = w_big[(base+11)-:4]; + wire [3:0] wcd_big0 = w_big[(base+15)-:4]; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + wire [3:0] wcd_big0a = w_big[(base+16)-:4]; + wire [3:0] wcd_bigx = w_big[(1'bx)-:4]; + wire [3:0] wcd_ltl3a = w_ltl[(base+2)-:4]; +`else + wire [3:0] wcd_big0a = {1'bx,w_big[(base+15)-:3]}; + wire [3:0] wcd_bigx = 4'bxxxx; + wire [3:0] wcd_ltl3a = {1'bx,w_ltl[(base+2)-:3]}; +`endif + wire [3:0] wcd_ltl3 = w_ltl[(base+3)-:4]; + wire [3:0] wcd_ltl2 = w_ltl[(base+7)-:4]; + wire [3:0] wcd_ltl1 = w_ltl[(base+11)-:4]; + wire [3:0] wcd_ltl0 = w_ltl[(base+15)-:4]; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + wire [3:0] wcd_ltl0a = w_ltl[(base+16)-:4]; + wire [3:0] wcd_ltlx = w_ltl[(1'bx)-:4]; +`else + wire [3:0] wcd_ltl0a = {w_ltl[(base+15)-:3],1'bx}; + wire [3:0] wcd_ltlx = 4'bxxxx; +`endif + + /* + * Check a constant +: as a CA L-value. + */ + wire [base+15:base] wcu_big_l; + wire [base:base+15] wcu_ltl_l; + + assign wcu_big_l[(base)+:4] = 4'd3; + assign wcu_big_l[(base+4)+:4] = 4'd2; + assign wcu_big_l[(base+8)+:4] = 4'd1; + assign wcu_big_l[(base+12)+:4] = 4'd0; + assign wcu_ltl_l[(base)+:4] = 4'd3; + assign wcu_ltl_l[(base+4)+:4] = 4'd2; + assign wcu_ltl_l[(base+8)+:4] = 4'd1; + assign wcu_ltl_l[(base+12)+:4] = 4'd0; + + /* + * Check a constant -: as a CA L-value. + */ + wire [base+15:base] wcd_big_l; + wire [base:base+15] wcd_ltl_l; + + assign wcd_big_l[(base+3)-:4] = 4'd3; + assign wcd_big_l[(base+7)-:4] = 4'd2; + assign wcd_big_l[(base+11)-:4] = 4'd1; + assign wcd_big_l[(base+15)-:4] = 4'd0; + assign wcd_ltl_l[(base+3)-:4] = 4'd3; + assign wcd_ltl_l[(base+7)-:4] = 4'd2; + assign wcd_ltl_l[(base+11)-:4] = 4'd1; + assign wcd_ltl_l[(base+15)-:4] = 4'd0; + + /* + * Check a constant +: and -: with a 'bx index as a CA L-value. + */ + wire [base+15:base] wcu_big_lx; + wire [base:base+15] wcu_ltl_lx; + wire [base+15:base] wcd_big_lx; + wire [base:base+15] wcd_ltl_lx; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign wcu_big_lx[(1'bx)+:4] = 4'hf; + assign wcu_ltl_lx[(1'bx)+:4] = 4'hf; + assign wcd_big_lx[(1'bx)-:4] = 4'hf; + assign wcd_ltl_lx[(1'bx)-:4] = 4'hf; +`endif + + /* + * Check a constant +: and -: with out of bounds values as a CA L-value. + */ + wire [base+15:base] wcu_big_lo; + wire [base:base+15] wcu_ltl_lo; + wire [base+15:base] wcd_big_lo; + wire [base:base+15] wcd_ltl_lo; + +// For now Icarus does not support before base selects in a CA L-value. +// This test needs to be updated when this is added. +// assign wcu_big_lo[(base-1)+:4] = 4'b011x; + assign wcu_big_lo[(base)+:3] = 3'b011; + assign wcu_big_lo[(base+3)+:10] = 10'b0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign wcu_big_lo[(base+13)+:4] = 4'bx001; + assign wcu_ltl_lo[(base-1)+:4] = 4'bx001; +`else + assign wcu_big_lo[(base+13)+:3] = 3'b001; + assign wcu_ltl_lo[(base)+:3] = 3'b001; +`endif + assign wcu_ltl_lo[(base+3)+:10] = 10'b0; + assign wcu_ltl_lo[(base+13)+:3] = 3'b011; +// assign wcu_ltl_lo[(base+13)+:4] = 4'b011x; + +// assign wcd_big_lo[(base+2)-:4] = 4'b011x; + assign wcd_big_lo[(base+2)-:3] = 3'b011; + assign wcd_big_lo[(base+12)-:10] = 10'b0; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign wcd_big_lo[(base+16)-:4] = 4'bx001; + assign wcd_ltl_lo[(base+2)-:4] = 4'bx001; +`else + assign wcd_big_lo[(base+15)-:3] = 3'b001; + assign wcd_ltl_lo[(base+2)-:3] = 3'b001; +`endif + assign wcd_ltl_lo[(base+12)-:10] = 10'b0; + assign wcd_ltl_lo[(base+15)-:3] = 3'b011; +// assign wcd_ltl_lo[(base+16)-:4] = 4'b011x; + + initial begin + pass = 1'b1; + #1; + + $displayh("p_big/big: %h, p_ltl/ltl: %h, base: %0d", p_big, p_ltl, base); + + /* + * Check a constant +: on a parameter. + */ + $display(); + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("p_big[%0d+:4]: ", base-1, p_big[(base-1)+:4], + ", p_ltl[%0d+:4]: ", base-1, p_ltl[(base-1)+:4]); +`else + $displayb("p_big[%0d+:4]: ", base-1, {p_big[(base)+:3],1'bx}, + ", p_ltl[%0d+:4]: ", base-1, {1'bx,p_ltl[(base)+:3]}); +`endif + $displayh("p_big[%0d+:4]: ", base, p_big[(base)+:4], + ", p_ltl[%0d+:4]: ", base, p_ltl[(base)+:4]); + $displayh("p_big[%0d+:4]: ", base+4, p_big[(base+4)+:4], + ", p_ltl[%0d+:4]: ", base+4, p_ltl[(base+4)+:4]); + $displayh("p_big[%0d+:4]: ", base+8, p_big[(base+8)+:4], + ", p_ltl[%0d+:4]: ", base+8, p_ltl[(base+8)+:4]); + $displayh("p_big[%0d+:4]: ", base+12, p_big[(base+12)+:4], + ", p_ltl[%0d+:4]: ", base+12, p_ltl[(base+12)+:4]); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("p_big[%0d+:4]: ", base+13, p_big[(base+13)+:4], + ", p_ltl[%0d+:4]: ", base+13, p_ltl[(base+13)+:4]); + $displayb("p_big[%0d+:4]: ", 1'bx, p_big[(1'bx)+:4], + ", p_ltl[%0d+:4]: ", 1'bx, p_ltl[(1'bx)+:4]); +`else + $displayb("p_big[%0d+:4]: ", base+13, {1'bx,p_big[(base+13)+:3]}, + ", p_ltl[%0d+:4]: ", base+13, {p_ltl[(base+13)+:3],1'bx}); + $displayb("p_big[%0d+:4]: ", 1'bx, 4'bxxxx, + ", p_ltl[%0d+:4]: ", 1'bx, 4'bxxxx); +`endif + if (p_big[ (base) +: 4] !== 4'd3 || p_big[ (base+4) +: 4] !== 4'd2 || + p_big[(base+8) +: 4] !== 4'd1 || p_big[(base+12) +: 4] !== 4'd0 || +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + p_big[ (base-1) +: 4] !== 4'b011x || + p_big[(base+13) +: 4] !== 4'bx000 || + p_big[(1'bx) +: 4] !== 4'bxxxx) begin +`else + {p_big[ (base) +: 3],1'bx} !== 4'b011x || + {1'bx,p_big[(base+13) +: 3]} !== 4'bx000 || + 4'bxxxx !== 4'bxxxx) begin +`endif + $display("FAILED: big endian parameter constant +: indexed select."); + pass = 1'b0; + end + if (p_ltl[ (base) +: 4] !== 4'd3 || p_ltl[ (base+4) +: 4] !== 4'd2 || + p_ltl[(base+8) +: 4] !== 4'd1 || p_ltl[(base+12) +: 4] !== 4'd0 || +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + p_ltl[ (base-1) +: 4] !== 4'bx001 || + p_ltl[(base+13) +: 4] !== 4'b000x || + p_ltl[(1'bx) +: 4] !== 4'bxxxx) begin +`else + {1'bx,p_ltl[ (base) +: 3]} !== 4'bx001 || + {p_ltl[(base+13) +: 3],1'bx} !== 4'b000x || + 4'bxxxx !== 4'bxxxx) begin +`endif + $display("FAILED: little endian parameter constant +: indexed select."); + pass = 1'b0; + end + + /* + * Check a constant -: on a parameter. + */ + $display(); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("p_big[%0d-:4]: ", base+2, p_big[(base+2)-:4], + ", p_ltl[%0d-:4]: ", base+2, p_ltl[(base+2)-:4]); +`else + $displayb("p_big[%0d-:4]: ", base+2, {p_big[(base+2)-:3],1'bx}, + ", p_ltl[%0d-:4]: ", base+2, {1'bx,p_ltl[(base+2)-:3]}); +`endif + $displayh("p_big[%0d-:4]: ", base+3, p_big[(base+3)-:4], + ", p_ltl[%0d-:4]: ", base+3, p_ltl[(base+3)-:4]); + $displayh("p_big[%0d-:4]: ", base+7, p_big[(base+7)-:4], + ", p_ltl[%0d-:4]: ", base+7, p_ltl[(base+7)-:4]); + $displayh("p_big[%0d-:4]: ", base+11, p_big[(base+11)-:4], + ", p_ltl[%0d-:4]: ", base+11, p_ltl[(base+11)-:4]); + $displayh("p_big[%0d-:4]: ", base+15, p_big[(base+15)-:4], + ", p_ltl[%0d-:4]: ", base+15, p_ltl[(base+15)-:4]); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("p_big[%0d-:4]: ", base+16, p_big[(base+16)-:4], + ", p_ltl[%0d-:4]: ", base+16, p_ltl[(base+16)-:4]); + $displayb("p_big[%0d-:4]: ", 1'bx, p_big[(1'bx)-:4], + ", p_ltl[%0d-:4]: ", 1'bx, p_ltl[(1'bx)-:4]); +`else + $displayb("p_big[%0d-:4]: ", base+16, {1'bx,p_big[(base+15)-:3]}, + ", p_ltl[%0d-:4]: ", base+16, {p_ltl[(base+15)-:3],1'bx}); + $displayb("p_big[%0d-:4]: ", 1'bx, 4'bxxxx, + ", p_ltl[%0d-:4]: ", 1'bx, 4'bxxxx); +`endif + if (p_big[ (base+3) -: 4] !== 4'd3 || p_big[ (base+7) -: 4] !== 4'd2 || + p_big[(base+11) -: 4] !== 4'd1 || p_big[(base+15) -: 4] !== 4'd0 || +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + p_big[ (base+2) -: 4] !== 4'b011x || + p_big[(base+16) -: 4] !== 4'bx000 || + p_big[(1'bx) -: 4] !== 4'bxxxx) begin +`else + {p_big[ (base+2) -: 3],1'bx} !== 4'b011x || + {1'bx,p_big[(base+15) -: 3]} !== 4'bx000 || + 4'bxxxx !== 4'bxxxx) begin +`endif + $display("FAILED: big endian parameter constant -: indexed select."); + pass = 1'b0; + end + if (p_ltl[ (base+3) -: 4] !== 4'd3 || p_ltl[ (base+7) -: 4] !== 4'd2 || + p_ltl[(base+11) -: 4] !== 4'd1 || p_ltl[(base+15) -: 4] !== 4'd0 || +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + p_ltl[ (base+2) -: 4] !== 4'bx001 || + p_ltl[(base+16) -: 4] !== 4'b000x || + p_ltl[(1'bx) -: 4] !== 4'bxxxx) begin +`else + {1'bx,p_ltl[ (base+2) -: 3]} !== 4'bx001 || + {p_ltl[(base+15) -: 3],1'bx} !== 4'b000x || + 4'bxxxx !== 4'bxxxx) begin +`endif + $display("FAILED: little endian parameter constant -: indexed select."); + pass = 1'b0; + end + + /* + * Check a constant +: on a parameter with out a width specification. + */ + $display(); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("p_base[-1+:4]: ", p_base[-1+:4]); +`else + $displayb("p_base[-1+:4]: ", {p_base[0+:3],1'bx}); +`endif + $displayh("p_base[0+:4]: ", p_base[0+:4]); + $displayh("p_base[4+:4]: ", p_base[4+:4]); + $displayh("p_base[8+:4]: ", p_base[8+:4]); + $displayh("p_base[12+:4]: ", p_base[12+:4]); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("p_base[13+:4]: ", p_base[13+:4]); + $displayb("p_base[x+:4]: ", p_base[(1'bx)+:4]); +`else + $displayb("p_base[13+:4]: ", {1'bx,p_base[13+:3]}); + $displayb("p_base[x+:4]: ", 4'bxxxx); +`endif + if (p_base[ 0 +: 4] !== 4'd3 || p_base[ 4 +: 4] !== 4'd2 || + p_base[ 8 +: 4] !== 4'd1 || p_base[12 +: 4] !== 4'd0 || +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + p_base[-1 +: 4] !== 4'b011x || p_base[13 +: 4] !== 4'bx000 || + p_base[1'bx +: 4] !== 4'bxxxx) begin +`else + {p_base[0 +: 3],1'bx} !== 4'b011x || + {1'bx,p_base[13 +: 3]} !== 4'bx000 || + 4'bxxxx !== 4'bxxxx) begin +`endif + $display("FAILED: base parameter constant +: indexed select."); + pass = 1'b0; + end + + /* + * Check a constant -: on a parameter with out a width specification. + */ + $display(); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("p_base[2-:4]: ", p_base[2-:4]); +`else + $displayb("p_base[2-:4]: ", {p_base[2-:3],1'bx}); +`endif + $displayh("p_base[3-:4]: ", p_base[3-:4]); + $displayh("p_base[7-:4]: ", p_base[7-:4]); + $displayh("p_base[11-:4]: ", p_base[11-:4]); + $displayh("p_base[15-:4]: ", p_base[15-:4]); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("p_base[16-:4]: ", p_base[16-:4]); + $displayb("p_base[x-:4]: ", p_base[(1'bx)-:4]); +`else + $displayb("p_base[16-:4]: ", {1'bx,p_base[15-:3]}); + $displayb("p_base[x-:4]: ", 4'bxxxx); +`endif + if (p_base[ 3 -: 4] !== 4'd3 || p_base[ 7 -: 4] !== 4'd2 || + p_base[11 -: 4] !== 4'd1 || p_base[15 -: 4] !== 4'd0 || +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + p_base[ 2 -: 4] !== 4'b011x || p_base[16 -: 4] !== 4'bx000 || + p_base[(1'bx) -: 4] !== 4'bxxxx) begin +`else + {p_base[ 2 -: 3],1'bx} !== 4'b011x || + {1'bx,p_base[15 -: 3]} !== 4'bx000 || + 4'bxxxx !== 4'bxxxx) begin +`endif + $display("FAILED: base parameter constant -: indexed select."); + pass = 1'b0; + end + + /* + * Check a constant +: on a register. + */ + $display(); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("big[%0d+:4]: ", base-1, big[(base-1)+:4], + ", ltl[%0d+:4]: ", base-1, ltl[(base-1)+:4]); +`else + $displayb("big[%0d+:4]: ", base-1, {big[(base)+:3],1'bx}, + ", ltl[%0d+:4]: ", base-1, {1'bx,ltl[(base)+:3]}); +`endif + $displayh("big[%0d+:4]: ", base, big[(base)+:4], + ", ltl[%0d+:4]: ", base, ltl[(base)+:4]); + $displayh("big[%0d+:4]: ", base+4, big[(base+4)+:4], + ", ltl[%0d+:4]: ", base+4, ltl[(base+4)+:4]); + $displayh("big[%0d+:4]: ", base+8, big[(base+8)+:4], + ", ltl[%0d+:4]: ", base+8, ltl[(base+8)+:4]); + $displayh("big[%0d+:4]: ",base+12, big[(base+12)+:4], + ", ltl[%0d+:4]: ",base+12, ltl[(base+12)+:4]); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("big[%0d+:4]: ",base+13, big[(base+13)+:4], + ", ltl[%0d+:4]: ",base+13, ltl[(base+13)+:4]); + $displayb("big[%0d+:4]: ",1'bx, big[(1'bx)+:4], + ", ltl[%0d+:4]: ",1'bx, ltl[(1'bx)+:4]); +`else + $displayb("big[%0d+:4]: ",base+13, {1'bx,big[(base+13)+:3]}, + ", ltl[%0d+:4]: ",base+13, {ltl[(base+13)+:3],1'bx}); + $displayb("big[%0d+:4]: ",1'bx, 4'bxxxx, + ", ltl[%0d+:4]: ",1'bx, 4'bxxxx); +`endif + if (big[ (base) +: 4] !== 4'd3 || big[ (base+4) +: 4] !== 4'd2 || + big[(base+8) +: 4] !== 4'd1 || big[(base+12) +: 4] !== 4'd0 || +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + big[ (base-1) +: 4] !== 4'b011x || + big[(base+13) +: 4] !== 4'bx000 || + big[(1'bx) +: 4] !== 4'bxxxx) begin +`else + {big[ (base) +: 3],1'bx} !== 4'b011x || + {1'bx,big[(base+13) +: 3]} !== 4'bx000 || + 4'bxxxx !== 4'bxxxx) begin +`endif + $display("FAILED: big endian register constant +: indexed select."); + pass = 1'b0; + end + if (ltl[ (base) +: 4] !== 4'd3 || ltl[ (base+4) +: 4] !== 4'd2 || + ltl[(base+8) +: 4] !== 4'd1 || ltl[(base+12) +: 4] !== 4'd0 || +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + ltl[ (base-1) +: 4] !== 4'bx001 || + ltl[(base+13) +: 4] !== 4'b000x || + ltl[(1'bx) +: 4] !== 4'bxxxx) begin +`else + {1'bx,ltl[ (base) +: 3]} !== 4'bx001 || + {ltl[(base+13) +: 3],1'bx} !== 4'b000x || + 4'bxxxx !== 4'bxxxx) begin +`endif + $display("FAILED: little endian register constant +: indexed select."); + pass = 1'b0; + end + + /* + * Check a constant -: on a register. + */ + $display(); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("big[%0d-:4]: ", base+2, big[(base+2)-:4], + ", ltl[%0d-:4]: ", base+2, ltl[(base+2)-:4]); +`else + $displayb("big[%0d-:4]: ", base+2, {big[(base+2)-:3],1'bx}, + ", ltl[%0d-:4]: ", base+2, {1'bx,ltl[(base+2)-:3]}); +`endif + $displayh("big[%0d-:4]: ", base+3, big[(base+3)-:4], + ", ltl[%0d-:4]: ", base+3, ltl[(base+3)-:4]); + $displayh("big[%0d-:4]: ", base+7, big[(base+7)-:4], + ", ltl[%0d-:4]: ", base+7, ltl[(base+7)-:4]); + $displayh("big[%0d-:4]: ", base+11, big[(base+11)-:4], + ", ltl[%0d-:4]: ", base+11, ltl[(base+11)-:4]); + $displayh("big[%0d-:4]: ", base+15, big[(base+15)-:4], + ", ltl[%0d-:4]: ", base+15, ltl[(base+15)-:4]); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("big[%0d-:4]: ", base+16, big[(base+16)-:4], + ", ltl[%0d-:4]: ", base+16, ltl[(base+16)-:4]); + $displayb("big[%0d-:4]: ", 1'bx, big[(1'bx)-:4], + ", ltl[%0d-:4]: ", 1'bx, ltl[(1'bx)-:4]); +`else + $displayb("big[%0d-:4]: ", base+16, {1'bx,big[(base+15)-:3]}, + ", ltl[%0d-:4]: ", base+16, {ltl[(base+15)-:3],1'bx}); + $displayb("big[%0d-:4]: ", 1'bx, 4'bxxxx, + ", ltl[%0d-:4]: ", 1'bx, 4'bxxxx); +`endif + if (big[ (base+3) -: 4] !== 4'd3 || big[ (base+7) -: 4] !== 4'd2 || + big[(base+11) -: 4] !== 4'd1 || big[(base+15) -: 4] !== 4'd0 || +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + big[ (base+2) -: 4] !== 4'b011x || + big[(base+16) -: 4] !== 4'bx000 || + big[(1'bx) -: 4] !== 4'bxxxx) begin +`else + {big[ (base+2) -: 3],1'bx} !== 4'b011x || + {1'bx,big[(base+15) -: 3]} !== 4'bx000 || + 4'bxxxx !== 4'bxxxx) begin +`endif + $display("FAILED: big endian register constant -: indexed select."); + pass = 1'b0; + end + if (ltl[ (base+3) -: 4] !== 4'd3 || ltl[ (base+7) -: 4] !== 4'd2 || + ltl[(base+11) -: 4] !== 4'd1 || ltl[(base+15) -: 4] !== 4'd0 || +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + ltl[ (base+2) -: 4] !== 4'bx001 || + ltl[(base+16) -: 4] !== 4'b000x || + ltl[(1'bx) -: 4] !== 4'bxxxx) begin +`else + {1'bx,ltl[ (base+2) -: 3]} !== 4'bx001 || + {ltl[(base+15) -: 3],1'bx} !== 4'b000x || + 4'bxxxx !== 4'bxxxx) begin +`endif + $display("FAILED: little endian register constant -: indexed select."); + pass = 1'b0; + end + + /* + * Check a constant +: on a wire. + */ + $display(); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("w_big[%0d+:4]: ", base-1, w_big[(base-1)+:4], + ", w_ltl[%0d+:4]: ", base-1, w_ltl[(base-1)+:4]); +`else + $displayb("w_big[%0d+:4]: ", base-1, {w_big[(base)+:3],1'bx}, + ", w_ltl[%0d+:4]: ", base-1, {1'bx,w_ltl[(base)+:3]}); +`endif + $displayh("w_big[%0d+:4]: ", base, w_big[(base)+:4], + ", w_ltl[%0d+:4]: ", base, w_ltl[(base)+:4]); + $displayh("w_big[%0d+:4]: ", base+4, w_big[(base+4)+:4], + ", w_ltl[%0d+:4]: ", base+4, w_ltl[(base+4)+:4]); + $displayh("w_big[%0d+:4]: ", base+8, w_big[(base+8)+:4], + ", w_ltl[%0d+:4]: ", base+8, w_ltl[(base+8)+:4]); + $displayh("w_big[%0d+:4]: ", base+12, w_big[(base+12)+:4], + ", w_ltl[%0d+:4]: ", base+12, w_ltl[(base+12)+:4]); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("w_big[%0d+:4]: ", base+13, w_big[(base+13)+:4], + ", w_ltl[%0d+:4]: ", base+13, w_ltl[(base+13)+:4]); + $displayb("w_big[%0d+:4]: ", 1'bx, w_big[(1'bx)+:4], + ", w_ltl[%0d+:4]: ", 1'bx, w_ltl[(1'bx)+:4]); +`else + $displayb("w_big[%0d+:4]: ", base+13, {1'bx,w_big[(base+13)+:3]}, + ", w_ltl[%0d+:4]: ", base+13, {w_ltl[(base+13)+:3],1'bx}); + $displayb("w_big[%0d+:4]: ", 1'bx, 4'bxxxx, + ", w_ltl[%0d+:4]: ", 1'bx, 4'bxxxx); +`endif + if (w_big[ (base) +: 4] !== 4'd3 || w_big[ (base+4) +: 4] !== 4'd2 || + w_big[(base+8) +: 4] !== 4'd1 || w_big[(base+12) +: 4] !== 4'd0 || +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + w_big[ (base-1) +: 4] !== 4'b011x || + w_big[(base+13) +: 4] !== 4'bx000 || + w_big[(1'bx) +: 4] !== 4'bxxxx) begin +`else + {w_big[ (base) +: 3],1'bx} !== 4'b011x || + {1'bx,w_big[(base+13) +: 3]} !== 4'bx000 || + 4'bxxxx !== 4'bxxxx) begin +`endif + $display("FAILED: big endian wire constant +: indexed select."); + pass = 1'b0; + end + if (w_ltl[ (base) +: 4] !== 4'd3 || w_ltl[ (base+4) +: 4] !== 4'd2 || + w_ltl[(base+8) +: 4] !== 4'd1 || w_ltl[(base+12) +: 4] !== 4'd0 || +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + w_ltl[ (base-1) +: 4] !== 4'bx001 || + w_ltl[(base+13) +: 4] !== 4'b000x || + w_ltl[(1'bx) +: 4] !== 4'bxxxx) begin +`else + {1'bx,w_ltl[ (base) +: 3]} !== 4'bx001 || + {w_ltl[(base+13) +: 3],1'bx} !== 4'b000x || + 4'bxxxx !== 4'bxxxx) begin +`endif + $display("FAILED: little endian wire constant +: indexed select."); + pass = 1'b0; + end + + /* + * Check a constant -: on a wire. + */ + $display(); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("w_big[%0d-:4]: ", base+2, w_big[(base+2)-:4], + ", w_ltl[%0d-:4]: ", base+2, w_ltl[(base+2)-:4]); +`else + $displayb("w_big[%0d-:4]: ", base+2, {w_big[(base+2)-:3],1'bx}, + ", w_ltl[%0d-:4]: ", base+2, {1'bx,w_ltl[(base+2)-:3]}); +`endif + $displayh("w_big[%0d-:4]: ", base+3, w_big[(base+3)-:4], + ", w_ltl[%0d-:4]: ", base+3, w_ltl[(base+3)-:4]); + $displayh("w_big[%0d-:4]: ", base+7, w_big[(base+7)-:4], + ", w_ltl[%0d-:4]: ", base+7, w_ltl[(base+7)-:4]); + $displayh("w_big[%0d-:4]: ", base+11, w_big[(base+11)-:4], + ", w_ltl[%0d-:4]: ", base+11, w_ltl[(base+11)-:4]); + $displayh("w_big[%0d-:4]: ", base+15, w_big[(base+15)-:4], + ", w_ltl[%0d-:4]: ", base+15, w_ltl[(base+15)-:4]); +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $displayb("w_big[%0d-:4]: ", base+16, w_big[(base+16)-:4], + ", w_ltl[%0d-:4]: ", base+16, w_ltl[(base+16)-:4]); + $displayb("w_big[%0d-:4]: ", 1'bx, w_big[(1'bx)-:4], + ", w_ltl[%0d-:4]: ", 1'bx, w_ltl[(1'bx)-:4]); +`else + $displayb("w_big[%0d-:4]: ", base+16, {1'bx,w_big[(base+15)-:3]}, + ", w_ltl[%0d-:4]: ", base+16, {w_ltl[(base+15)-:3],1'bx}); + $displayb("w_big[%0d-:4]: ", 1'bx, 4'bxxxx, + ", w_ltl[%0d-:4]: ", 1'bx, 4'bxxxx); +`endif + if (w_big[ (base+3) -: 4] !== 4'd3 || w_big[ (base+7) -: 4] !== 4'd2 || + w_big[(base+11) -: 4] !== 4'd1 || w_big[(base+15) -: 4] !== 4'd0 || +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + w_big[ (base+2) -: 4] !== 4'b011x || + w_big[(base+16) -: 4] !== 4'bx000 || + w_big[(1'bx) -: 4] !== 4'bxxxx) begin +`else + {w_big[ (base+2) -: 3],1'bx} !== 4'b011x || + {1'bx,w_big[(base+15) -: 3]} !== 4'bx000 || + 4'bxxxx !== 4'bxxxx) begin +`endif + $display("FAILED: big endian wire constant -: indexed select."); + pass = 1'b0; + end + if (w_ltl[ (base+3) -: 4] !== 4'd3 || w_ltl[ (base+7) -: 4] !== 4'd2 || + w_ltl[(base+11) -: 4] !== 4'd1 || w_ltl[(base+15) -: 4] !== 4'd0 || +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + w_ltl[ (base+2) -: 4] !== 4'bx001 || + w_ltl[(base+16) -: 4] !== 4'b000x || + w_ltl[(1'bx) -: 4] !== 4'bxxxx) begin +`else + {1'bx,w_ltl[ (base+2) -: 3]} !== 4'bx001 || + {w_ltl[(base+15) -: 3],1'bx} !== 4'b000x || + 4'bxxxx !== 4'bxxxx) begin +`endif + $display("FAILED: little endian wire constant -: indexed select."); + pass = 1'b0; + end + + /* + * Check a constant +: on a CA R-value. + */ + $display(); + $displayb("wcu_big3a: ", wcu_big3a, ", wcu_ltl3a: ", wcu_ltl3a); + $displayh("wcu_big3: ", wcu_big3, ", wcu_ltl3: ", wcu_ltl3); + $displayh("wcu_big2: ", wcu_big2, ", wcu_ltl2: ", wcu_ltl2); + $displayh("wcu_big1: ", wcu_big1, ", wcu_ltl1: ", wcu_ltl1); + $displayh("wcu_big0: ", wcu_big0, ", wcu_ltl0: ", wcu_ltl0); + $displayb("wcu_big0a: ", wcu_big0a, ", wcu_ltl0a: ", wcu_ltl0a); + $displayb("wcu_bigx: ", wcu_bigx, ", wcu_ltlx: ", wcu_ltlx); + if (wcu_big3 !== 4'd3 || wcu_big2 !== 4'd2 || + wcu_big1 !== 4'd1 || wcu_big0 !== 4'd0 || + wcu_big3a !== 4'b011x || wcu_big0a !== 4'bx000 || + wcu_bigx !== 4'bxxxx) begin + $display("FAILED: big endian CA R-value constant +: indexed select."); + pass = 1'b0; + end + if (wcu_ltl3 !== 4'd3 || wcu_ltl2 !== 4'd2 || + wcu_ltl1 !== 4'd1 || wcu_ltl0 !== 4'd0 || + wcu_ltl3a !== 4'bx001 || wcu_ltl0a !== 4'b000x || + wcu_ltlx !== 4'bxxxx) begin + $display("FAILED: little endian CA R-value constant +: indexed select."); + pass = 1'b0; + end + + /* + * Check a constant -: on a CA R-value. + */ + $display(); + $displayb("wcd_big3a: ", wcd_big3a, ", wcd_ltl3a: ", wcd_ltl3a); + $displayh("wcd_big3: ", wcd_big3, ", wcd_ltl3: ", wcd_ltl3); + $displayh("wcd_big2: ", wcd_big2, ", wcd_ltl2: ", wcd_ltl2); + $displayh("wcd_big1: ", wcd_big1, ", wcd_ltl1: ", wcd_ltl1); + $displayh("wcd_big0: ", wcd_big0, ", wcd_ltl0: ", wcd_ltl0); + $displayb("wcd_big0a: ", wcd_big0a, ", wcd_ltl0a: ", wcd_ltl0a); + $displayb("wcd_bigx: ", wcd_bigx, ", wcd_ltlx: ", wcd_ltlx); + if (wcd_big3 !== 4'd3 || wcd_big2 !== 4'd2 || + wcd_big1 !== 4'd1 || wcd_big0 !== 4'd0 || + wcd_big3a !== 4'b011x || wcd_big0a !== 4'bx000 || + wcd_bigx !== 4'bxxxx) begin + $display("FAILED: big endian CA R-value constant -: indexed select."); + pass = 1'b0; + end + if (wcd_ltl3 !== 4'd3 || wcd_ltl2 !== 4'd2 || + wcd_ltl1 !== 4'd1 || wcd_ltl0 !== 4'd0 || + wcd_ltl3a !== 4'bx001 || wcd_ltl0a !== 4'b000x || + wcd_ltlx !== 4'bxxxx) begin + $display("FAILED: little endian CA R-value constant -: indexed select."); + pass = 1'b0; + end + + /* + * Check a constant +: on a simple L-value. + */ + $display(); + big_l = 16'hxxxx; + ltl_l = 16'hxxxx; + big_l[(base)+:4] = 4'd3; + ltl_l[(base)+:4] = 4'd3; + big_l[(base+4)+:4] = 4'd2; + ltl_l[(base+4)+:4] = 4'd2; + big_l[(base+8)+:4] = 4'd1; + ltl_l[(base+8)+:4] = 4'd1; + big_l[(base+12)+:4] = 4'd0; + ltl_l[(base+12)+:4] = 4'd0; + $displayh("big_l[simple]: ", big_l, ", ltl_l[simple]: ", ltl_l); + if (big_l !== big) begin + $display("FAILED: big endian simple L-value constant +: indexed select."); + pass = 1'b0; + end + if (ltl_l !== ltl) begin + $display("FAILED: little endian simple L-value constant +: indexed select."); + pass = 1'b0; + end + + big_l = 16'hxxxx; + ltl_l = 16'hxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + big_l[(1'bx)+:4] = 4'd0; + ltl_l[(1'bx)+:4] = 4'd0; +`endif + $displayh("big_l[1'bx]: ", big_l, ", ltl_l[1'bx]: ", ltl_l); + if (big_l !== 16'hxxxx) begin + $display("FAILED: big endian L-value constant 'bx index +: indexed select."); + pass = 1'b0; + end + if (ltl_l !== 16'hxxxx) begin + $display("FAILED: little endian L-value constant 'bx index +: indexed select."); + pass = 1'b0; + end + + big_l = 16'h0000; + ltl_l = 16'h0000; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + big_l[(base-1)+:4] = 4'b011x; + ltl_l[(base-1)+:4] = 4'bx001; + big_l[(base+13)+:4] = 4'bx001; + ltl_l[(base+13)+:4] = 4'b011x; +`else + big_l[(base)+:3] = 3'b011; + ltl_l[(base)+:3] = 3'b001; + big_l[(base+13)+:3] = 3'b001; + ltl_l[(base+13)+:3] = 3'b011; +`endif + $displayh("big_l[edge]: ", big_l, ", ltl_l[edge]: ", ltl_l); + if (big_l !== 16'h2003) begin + $display("FAILED: big endian edge L-value constant +: indexed select."); + pass = 1'b0; + end + if (ltl_l !== 16'h2003) begin + $display("FAILED: little endian edge L-value constant +: indexed select."); + pass = 1'b0; + end + + /* + * Check a constant -: on a simple L-value. + */ + $display(); + big_l = 16'hxxxx; + ltl_l = 16'hxxxx; + big_l[(base+3)-:4] = 4'd3; + ltl_l[(base+3)-:4] = 4'd3; + big_l[(base+7)-:4] = 4'd2; + ltl_l[(base+7)-:4] = 4'd2; + big_l[(base+11)-:4] = 4'd1; + ltl_l[(base+11)-:4] = 4'd1; + big_l[(base+15)-:4] = 4'd0; + ltl_l[(base+15)-:4] = 4'd0; + $displayh("big_l: ", big_l, ", ltl_l: ", ltl_l); + if (big_l !== big) begin + $display("FAILED: big endian simple L-value constant -: indexed select."); + pass = 1'b0; + end + if (ltl_l !== ltl) begin + $display("FAILED: little endian simple L-value constant -: indexed select."); + pass = 1'b0; + end + + big_l = 16'hxxxx; + ltl_l = 16'hxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + big_l[(1'bx)-:4] = 4'd0; + ltl_l[(1'bx)-:4] = 4'd0; +`endif + $displayh("big_l[1'bx]: ", big_l, ", ltl_l[1'bx]: ", ltl_l); + if (big_l !== 16'hxxxx) begin + $display("FAILED: big endian L-value constant 'bx index -: indexed select."); + pass = 1'b0; + end + if (ltl_l !== 16'hxxxx) begin + $display("FAILED: little endian L-value constant 'bx index -: indexed select."); + pass = 1'b0; + end + + big_l = 16'h0000; + ltl_l = 16'h0000; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + big_l[(base+2)-:4] = 4'b011x; + ltl_l[(base+2)-:4] = 4'bx001; + big_l[(base+16)-:4] = 4'bx001; + ltl_l[(base+16)-:4] = 4'b011x; +`else + big_l[(base+2)-:3] = 3'b011; + ltl_l[(base+2)-:3] = 3'b001; + big_l[(base+15)-:3] = 3'b001; + ltl_l[(base+15)-:3] = 3'b011; +`endif + $displayh("big_l[edge]: ", big_l, ", ltl_l[edge]: ", ltl_l); + if (big_l !== 16'h2003) begin + $display("FAILED: big endian edge L-value constant -: indexed select."); + pass = 1'b0; + end + if (ltl_l !== 16'h2003) begin + $display("FAILED: little endian edge L-value constant -: indexed select."); + pass = 1'b0; + end + + /* + * Check a constant +: on a CA L-value. + */ + $display(); + $displayh("wcu_big_l: ", wcu_big_l, ", wcu_ltl_l: ", wcu_ltl_l); + if (wcu_big_l !== big) begin + $display("FAILED: big endian CA L-value constant +: indexed select."); + pass = 1'b0; + end + if (wcu_ltl_l !== ltl) begin + $display("FAILED: little endian CA L-value constant +: indexed select."); + pass = 1'b0; + end + + $displayh("wcu_big_lx: ", wcu_big_lx, ", wcu_ltl_lx: ", wcu_ltl_lx); + if (wcu_big_lx !== 16'hzzzz) begin + $display("FAILED: big endian CA L-value constant 'bx +: indexed select."); + pass = 1'b0; + end + if (wcu_ltl_lx !== 16'hzzzz) begin + $display("FAILED: little endian CA L-value constant 'bx +: indexed select."); + pass = 1'b0; + end + + $displayh("wcu_big_lo: ", wcu_big_lo, ", wcu_ltl_lo: ", wcu_ltl_lo); + if (wcu_big_lo !== 16'h2003) begin + $display("FAILED: big endian edge CA L-value constant +: indexed select."); + pass = 1'b0; + end + if (wcu_ltl_lo !== 16'h2003) begin + $display("FAILED: little endian edge CA L-value constant +: indexed select."); + pass = 1'b0; + end + + /* + * Check a constant -: on a CA L-value. + */ + $display(); + $displayh("wcd_big_l: ", wcd_big_l, ", wcd_ltl_l: ", wcd_ltl_l); + if (wcd_big_l !== big) begin + $display("FAILED: big endian CA L-value constant -: indexed select."); + pass = 1'b0; + end + if (wcd_ltl_l !== ltl) begin + $display("FAILED: little endian CA L-value constant -: indexed select."); + pass = 1'b0; + end + + $displayh("wcd_big_lx: ", wcd_big_lx, ", wcd_ltl_lx: ", wcd_ltl_lx); + if (wcd_big_lx !== 16'hzzzz) begin + $display("FAILED: big endian CA L-value constant 'bx -: indexed select."); + pass = 1'b0; + end + if (wcd_ltl_lx !== 16'hzzzz) begin + $display("FAILED: little endian CA L-value constant 'bx -: indexed select."); + pass = 1'b0; + end + + $displayh("wcd_big_lo: ", wcd_big_lo, ", wcd_ltl_lo: ", wcd_ltl_lo); + if (wcd_big_lo !== 16'h2003) begin + $display("FAILED: big endian edge CA L-value constant -: indexed select."); + pass = 1'b0; + end + if (wcd_ltl_lo !== 16'h2003) begin + $display("FAILED: little endian edge CA L-value constant -: indexed select."); + pass = 1'b0; + end + + /* + * All done. + */ + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2835632b.v b/ivtest/ivltests/pr2835632b.v new file mode 100644 index 000000000..609c239d5 --- /dev/null +++ b/ivtest/ivltests/pr2835632b.v @@ -0,0 +1,555 @@ +// This checks various variable selects using the indexed select operators +// +: and -: for both big and little endian vectors. +module top; + parameter base = -1; + + parameter [base+15:base] p_big = 16'h0123; + parameter [base:base+15] p_ltl = 16'h3210; + + reg [base+15:base] big = 16'h0123; + reg [base:base+15] ltl = 16'h3210; + reg [base+15:base] bigr; + reg [base:base+15] ltlr; + + wire [base+15:base] w_big = 16'h0123; + wire [base:base+15] w_ltl = 16'h3210; + + integer a; + + reg [3:0] big0, big1, big2, big3, ltl0, ltl1, ltl2, ltl3; + reg [3:0] big0a, big3a, bigx, ltl0a, ltl3a, ltlx; + + reg pass; + + /* + * Check a variable +: as a CA R-value. + */ + wire [3:0] wvu_big = w_big[a+:4]; + wire [3:0] wvu_ltl = w_ltl[a+:4]; + + /* + * Check a variable -: as a CA R-value. + */ + wire [3:0] wvd_big = w_big[a-:4]; + wire [3:0] wvd_ltl = w_ltl[a-:4]; + + initial begin + pass = 1'b1; + #1; + + $displayh("p_big/big: %h, p_ltl/ltl: %h, base: %0d", p_big, p_ltl, base); + + /* + * Check a variable +: on a parameter. + */ + $display(); + a = base-1; + big3a = p_big[a+:4]; + ltl3a = p_ltl[a+:4]; + $displayb("a==%0d; p_big[a+:4]: ", a, p_big[a+:4], + ", p_ltl[a+:4]: ", p_ltl[a+:4]); + a = base; + big3 = p_big[a+:4]; + ltl3 = p_ltl[a+:4]; + $displayh("a==%0d; p_big[a+:4]: ", a, p_big[a+:4], + ", p_ltl[a+:4]: ", p_ltl[a+:4]); + a = base+4; + big2 = p_big[a+:4]; + ltl2 = p_ltl[a+:4]; + $displayh("a==%0d; p_big[a+:4]: ", a, p_big[a+:4], + ", p_ltl[a+:4]: ", p_ltl[a+:4]); + a = base+8; + big1 = p_big[a+:4]; + ltl1 = p_ltl[a+:4]; + $displayh("a==%0d; p_big[a+:4]: ", a, p_big[a+:4], + ", p_ltl[a+:4]: ", p_ltl[a+:4]); + a = base+12; + big0 = p_big[a+:4]; + ltl0 = p_ltl[a+:4]; + $displayh("a==%0d; p_big[a+:4]: ", a, p_big[a+:4], + ", p_ltl[a+:4]: ", p_ltl[a+:4]); + a = base+13; + big0a = p_big[a+:4]; + ltl0a = p_ltl[a+:4]; + $displayb("a==%0d; p_big[a+:4]: ", a, p_big[a+:4], + ", p_ltl[a+:4]: ", p_ltl[a+:4]); + a = 1'bx; + bigx = p_big[a+:4]; + ltlx = p_ltl[a+:4]; + $displayb("a==%0d; p_big[a+:4]: ", a, p_big[a+:4], + ", p_ltl[a+:4]: ", p_ltl[a+:4]); + if (big3 !== 4'd3 || big2 !== 4'd2 || big1 !== 4'd1 || big0 !== 4'd0 || + big3a !== 4'b011x || big0a !== 4'bx000 || bigx !== 4'bxxxx) begin + $display("FAILED: big endian parameter variable +: indexed select."); + pass = 1'b0; + end + if (ltl3 !== 4'd3 || ltl2 !== 4'd2 || ltl1 !== 4'd1 || ltl0 !== 4'd0 || + ltl3a !== 4'bx001 || ltl0a !== 4'b000x || ltlx !== 4'bxxxx) begin + $display("FAILED: little endian parameter variable +: indexed select."); + pass = 1'b0; + end + + /* + * Check a variable -: on a parameter. + */ + $display(); + a = base+2; + big3a = p_big[a-:4]; + ltl3a = p_ltl[a-:4]; + $displayb("a== %0d; p_big[a-:4]: ", a, p_big[a-:4], + ", p_ltl[a-:4]: ", p_ltl[a-:4]); + a = base+3; + big3 = p_big[a-:4]; + ltl3 = p_ltl[a-:4]; + $displayh("a== %0d; p_big[a-:4]: ", a, p_big[a-:4], + ", p_ltl[a-:4]: ", p_ltl[a-:4]); + a = base+7; + big2 = p_big[a-:4]; + ltl2 = p_ltl[a-:4]; + $displayh("a== %0d; p_big[a-:4]: ", a, p_big[a-:4], + ", p_ltl[a-:4]: ", p_ltl[a-:4]); + a = base+11; + big1 = p_big[a-:4]; + ltl1 = p_ltl[a-:4]; + $displayh("a== %0d; p_big[a-:4]: ", a, p_big[a-:4], + ", p_ltl[a-:4]: ", p_ltl[a-:4]); + a = base+15; + big0 = p_big[a-:4]; + ltl0 = p_ltl[a-:4]; + $displayh("a== %0d; p_big[a-:4]: ", a, p_big[a-:4], + ", p_ltl[a-:4]: ", p_ltl[a-:4]); + a = base+16; + big0a = p_big[a-:4]; + ltl0a = p_ltl[a-:4]; + $displayb("a== %0d; p_big[a-:4]: ", a, p_big[a-:4], + ", p_ltl[a-:4]: ", p_ltl[a-:4]); + a = 1'bx; + bigx = p_big[a-:4]; + ltlx = p_ltl[a-:4]; + $displayb("a== %0d; p_big[a-:4]: ", a, p_big[a-:4], + ", p_ltl[a-:4]: ", p_ltl[a-:4]); + if (big3 !== 4'd3 || big2 !== 4'd2 || big1 !== 4'd1 || big0 !== 4'd0 || + big3a !== 4'b011x || big0a !== 4'bx000 || bigx !== 4'bxxxx) begin + $display("FAILED: big endian parameter variable -: indexed select."); + pass = 1'b0; + end + if (ltl3 !== 4'd3 || ltl2 !== 4'd2 || ltl1 !== 4'd1 || ltl0 !== 4'd0 || + ltl3a !== 4'bx001 || ltl0a !== 4'b000x || ltlx !== 4'bxxxx) begin + $display("FAILED: little endian parameter variable -: indexed select."); + pass = 1'b0; + end + + /* + * Check a variable +: on a register. + */ + $display(); + a = base-1; + big3a = big[a+:4]; + ltl3a = ltl[a+:4]; + $displayb("a==%0d; big[a+:4]: ", a, big[a+:4], ", ltl[a+:4]: ", ltl[a+:4]); + a = base; + big3 = big[a+:4]; + ltl3 = ltl[a+:4]; + $displayh("a==%0d; big[a+:4]: ", a, big[a+:4], ", ltl[a+:4]: ", ltl[a+:4]); + a = base+4; + big2 = big[a+:4]; + ltl2 = ltl[a+:4]; + $displayh("a==%0d; big[a+:4]: ", a, big[a+:4], ", ltl[a+:4]: ", ltl[a+:4]); + a = base+8; + big1 = big[a+:4]; + ltl1 = ltl[a+:4]; + $displayh("a==%0d; big[a+:4]: ", a, big[a+:4], ", ltl[a+:4]: ", ltl[a+:4]); + a = base+12; + big0 = big[a+:4]; + ltl0 = ltl[a+:4]; + $displayh("a==%0d; big[a+:4]: ", a, big[a+:4], ", ltl[a+:4]: ", ltl[a+:4]); + a = base+13; + big0a = big[a+:4]; + ltl0a = ltl[a+:4]; + $displayb("a==%0d; big[a+:4]: ", a, big[a+:4], ", ltl[a+:4]: ", ltl[a+:4]); + a = 1'bx; + bigx = big[a+:4]; + ltlx = ltl[a+:4]; + $displayb("a==%0d; big[a+:4]: ", a, big[a+:4], ", ltl[a+:4]: ", ltl[a+:4]); + if (big3 !== 4'd3 || big2 !== 4'd2 || big1 !== 4'd1 || big0 !== 4'd0 || + big3a !== 4'b011x || big0a !== 4'bx000 || bigx !== 4'bxxxx) begin + $display("FAILED: big endian register variable +: indexed select."); + pass = 1'b0; + end + if (ltl3 !== 4'd3 || ltl2 !== 4'd2 || ltl1 !== 4'd1 || ltl0 !== 4'd0 || + ltl3a !== 4'bx001 || ltl0a !== 4'b000x || ltlx !== 4'bxxxx) begin + $display("FAILED: little endian register variable +: indexed select."); + pass = 1'b0; + end + + /* + * Check a variable -: on a register. + */ + $display(); + a = base+2; + big3a = big[a-:4]; + ltl3a = ltl[a-:4]; + $displayb("a== %0d; big[a-:4]: ", a, big[a-:4], ", ltl[a-:4]: ", ltl[a-:4]); + a = base+3; + big3 = big[a-:4]; + ltl3 = ltl[a-:4]; + $displayh("a== %0d; big[a-:4]: ", a, big[a-:4], ", ltl[a-:4]: ", ltl[a-:4]); + a = base+7; + big2 = big[a-:4]; + ltl2 = ltl[a-:4]; + $displayh("a== %0d; big[a-:4]: ", a, big[a-:4], ", ltl[a-:4]: ", ltl[a-:4]); + a = base+11; + big1 = big[a-:4]; + ltl1 = ltl[a-:4]; + $displayh("a== %0d; big[a-:4]: ", a, big[a-:4], ", ltl[a-:4]: ", ltl[a-:4]); + a = base+15; + big0 = big[a-:4]; + ltl0 = ltl[a-:4]; + $displayh("a== %0d; big[a-:4]: ", a, big[a-:4], ", ltl[a-:4]: ", ltl[a-:4]); + a = base+16; + big0a = big[a-:4]; + ltl0a = ltl[a-:4]; + $displayb("a== %0d; big[a-:4]: ", a, big[a-:4], ", ltl[a-:4]: ", ltl[a-:4]); + a = 1'bx; + bigx = big[a-:4]; + ltlx = ltl[a-:4]; + $displayb("a== %0d; big[a-:4]: ", a, big[a-:4], ", ltl[a-:4]: ", ltl[a-:4]); + if (big3 !== 4'd3 || big2 !== 4'd2 || big1 !== 4'd1 || big0 !== 4'd0 || + big3a !== 4'b011x || big0a !== 4'bx000 || bigx !== 4'bxxxx) begin + $display("FAILED: big endian register variable -: indexed select."); + pass = 1'b0; + end + if (ltl3 !== 4'd3 || ltl2 !== 4'd2 || ltl1 !== 4'd1 || ltl0 !== 4'd0 || + ltl3a !== 4'bx001 || ltl0a !== 4'b000x || ltlx !== 4'bxxxx) begin + $display("FAILED: little endian register variable -: indexed select."); + pass = 1'b0; + end + + /* + * Check a variable +: on a wire. + */ + $display(); + a = base-1; + big3a = w_big[a+:4]; + ltl3a = w_ltl[a+:4]; + $displayb("a==%0d; w_big[a+:4]: ", a, w_big[a+:4], + ", w_ltl[a+:4]: ", w_ltl[a+:4]); + a = base; + big3 = w_big[a+:4]; + ltl3 = w_ltl[a+:4]; + $displayh("a==%0d; w_big[a+:4]: ", a, w_big[a+:4], + ", w_ltl[a+:4]: ", w_ltl[a+:4]); + a = base+4; + big2 = w_big[a+:4]; + ltl2 = w_ltl[a+:4]; + $displayh("a==%0d; w_big[a+:4]: ", a, w_big[a+:4], + ", w_ltl[a+:4]: ", w_ltl[a+:4]); + a = base+8; + big1 = w_big[a+:4]; + ltl1 = w_ltl[a+:4]; + $displayh("a==%0d; w_big[a+:4]: ", a, w_big[a+:4], + ", w_ltl[a+:4]: ", w_ltl[a+:4]); + a = base+12; + big0 = w_big[a+:4]; + ltl0 = w_ltl[a+:4]; + $displayh("a==%0d; w_big[a+:4]: ", a, w_big[a+:4], + ", w_ltl[a+:4]: ", w_ltl[a+:4]); + a = base+13; + big0a = w_big[a+:4]; + ltl0a = w_ltl[a+:4]; + $displayb("a==%0d; w_big[a+:4]: ", a, w_big[a+:4], + ", w_ltl[a+:4]: ", w_ltl[a+:4]); + a = 1'bx; + bigx = w_big[a+:4]; + ltlx = w_ltl[a+:4]; + $displayb("a==%0d; w_big[a+:4]: ", a, w_big[a+:4], + ", w_ltl[a+:4]: ", w_ltl[a+:4]); + if (big3 !== 4'd3 || big2 !== 4'd2 || big1 !== 4'd1 || big0 !== 4'd0 || + big3a !== 4'b011x || big0a !== 4'bx000 || bigx !== 4'bxxxx) begin + $display("FAILED: big endian wire variable +: indexed select."); + pass = 1'b0; + end + if (ltl3 !== 4'd3 || ltl2 !== 4'd2 || ltl1 !== 4'd1 || ltl0 !== 4'd0 || + ltl3a !== 4'bx001 || ltl0a !== 4'b000x || ltlx !== 4'bxxxx) begin + $display("FAILED: little endian wire variable +: indexed select."); + pass = 1'b0; + end + + /* + * Check a variable -: on a wire. + */ + $display(); + a = base+2; + big3 = w_big[a-:4]; + ltl3 = w_ltl[a-:4]; + $displayb("a== %0d; w_big[a-:4]: ", a, w_big[a-:4], + ", w_ltl[a-:4]: ", w_ltl[a-:4]); + a = base+3; + big3 = w_big[a-:4]; + ltl3 = w_ltl[a-:4]; + $displayh("a== %0d; w_big[a-:4]: ", a, w_big[a-:4], + ", w_ltl[a-:4]: ", w_ltl[a-:4]); + a = base+7; + big2 = w_big[a-:4]; + ltl2 = w_ltl[a-:4]; + $displayh("a== %0d; w_big[a-:4]: ", a, w_big[a-:4], + ", w_ltl[a-:4]: ", w_ltl[a-:4]); + a = base+11; + big1 = w_big[a-:4]; + ltl1 = w_ltl[a-:4]; + $displayh("a== %0d; w_big[a-:4]: ", a, w_big[a-:4], + ", w_ltl[a-:4]: ", w_ltl[a-:4]); + a = base+15; + big0 = w_big[a-:4]; + ltl0 = w_ltl[a-:4]; + $displayh("a== %0d; w_big[a-:4]: ", a, w_big[a-:4], + ", w_ltl[a-:4]: ", w_ltl[a-:4]); + a = base+16; + big0a = w_big[a-:4]; + ltl0a = w_ltl[a-:4]; + $displayb("a== %0d; w_big[a-:4]: ", a, w_big[a-:4], + ", w_ltl[a-:4]: ", w_ltl[a-:4]); + a = 1'bx; + bigx = w_big[a-:4]; + ltlx = w_ltl[a-:4]; + $displayb("a== %0d; w_big[a-:4]: ", a, w_big[a-:4], + ", w_ltl[a-:4]: ", w_ltl[a-:4]); + if (big3 !== 4'd3 || big2 !== 4'd2 || big1 !== 4'd1 || big0 !== 4'd0 || + big3a !== 4'b011x || big0a !== 4'bx000 || bigx !== 4'bxxxx) begin + $display("FAILED: big endian wire variable -: indexed select."); + pass = 1'b0; + end + if (ltl3 !== 4'd3 || ltl2 !== 4'd2 || ltl1 !== 4'd1 || ltl0 !== 4'd0 || + ltl3a !== 4'bx001 || ltl0a !== 4'b000x || ltlx !== 4'bxxxx) begin + $display("FAILED: little endian wire variable -: indexed select."); + pass = 1'b0; + end + + /* + * Check a variable +: on a CA R-value. + */ + $display(); + a = base-1; + #1; + big3a = wvu_big; + ltl3a = wvu_ltl; + $displayb("a==%0d; wvu_big: ", a, wvu_big, ", wvu_ltl: ", wvu_ltl); + a = base; + #1; + big3 = wvu_big; + ltl3 = wvu_ltl; + $displayh("a==%0d; wvu_big: ", a, wvu_big, ", wvu_ltl: ", wvu_ltl); + a = base+4; + #1; + big2 = wvu_big; + ltl2 = wvu_ltl; + $displayh("a==%0d; wvu_big: ", a, wvu_big, ", wvu_ltl: ", wvu_ltl); + a = base+8; + #1; + big1 = wvu_big; + ltl1 = wvu_ltl; + $displayh("a==%0d; wvu_big: ", a, wvu_big, ", wvu_ltl: ", wvu_ltl); + a = base+12; + #1; + big0 = wvu_big; + ltl0 = wvu_ltl; + $displayh("a==%0d; wvu_big: ", a, wvu_big, ", wvu_ltl: ", wvu_ltl); + a = base+13; + #1; + big0a = wvu_big; + ltl0a = wvu_ltl; + $displayb("a==%0d; wvu_big: ", a, wvu_big, ", wvu_ltl: ", wvu_ltl); + a = 1'bx; + #1; + bigx = wvu_big; + ltlx = wvu_ltl; + $displayb("a==%0d; wvu_big: ", a, wvu_big, ", wvu_ltl: ", wvu_ltl); + if (big3 !== 4'd3 || big2 !== 4'd2 || big1 !== 4'd1 || big0 !== 4'd0 || + big3a !== 4'b011x || big0a !== 4'bx000 || bigx !== 4'bxxxx) begin + $display("FAILED: big endian CA R-value variable +: indexed select."); + pass = 1'b0; + end + if (ltl3 !== 4'd3 || ltl2 !== 4'd2 || ltl1 !== 4'd1 || ltl0 !== 4'd0 || + ltl3a !== 4'bx001 || ltl0a !== 4'b000x || ltlx !== 4'bxxxx) begin + $display("FAILED: little endian CA R-value variable +: indexed select."); + pass = 1'b0; + end + + /* + * Check a variable -: on a CA R-value. + */ + $display(); + a = base+2; + #1; + big3a = wvd_big; + ltl3a = wvd_ltl; + $displayb("a==%0d; wvd_big: ", a, wvd_big, ", wvd_ltl: ", wvd_ltl); + a = base+3; + #1; + big3 = wvd_big; + ltl3 = wvd_ltl; + $displayh("a==%0d; wvd_big: ", a, wvd_big, ", wvd_ltl: ", wvd_ltl); + a = base+7; + #1; + big2 = wvd_big; + ltl2 = wvd_ltl; + $displayh("a==%0d; wvd_big: ", a, wvd_big, ", wvd_ltl: ", wvd_ltl); + a = base+11; + #1; + big1 = wvd_big; + ltl1 = wvd_ltl; + $displayh("a==%0d; wvd_big: ", a, wvd_big, ", wvd_ltl: ", wvd_ltl); + a = base+15; + #1; + big0 = wvd_big; + ltl0 = wvd_ltl; + $displayh("a==%0d; wvd_big: ", a, wvd_big, ", wvd_ltl: ", wvd_ltl); + a = base+16; + #1; + big0a = wvd_big; + ltl0a = wvd_ltl; + $displayb("a==%0d; wvd_big: ", a, wvd_big, ", wvd_ltl: ", wvd_ltl); + a = 1'bx; + #1; + bigx = wvd_big; + ltlx = wvd_ltl; + $displayb("a==%0d; wvd_big: ", a, wvd_big, ", wvd_ltl: ", wvd_ltl); + if (big3 !== 4'd3 || big2 !== 4'd2 || big1 !== 4'd1 || big0 !== 4'd0 || + big3a !== 4'b011x || big0a !== 4'bx000 || bigx !== 4'bxxxx) begin + $display("FAILED: big endian CA R-value variable -: indexed select."); + pass = 1'b0; + end + if (ltl3 !== 4'd3 || ltl2 !== 4'd2 || ltl1 !== 4'd1 || ltl0 !== 4'd0 || + ltl3a !== 4'bx001 || ltl0a !== 4'b000x || ltlx !== 4'bxxxx) begin + $display("FAILED: little endian CA R-value variable -: indexed select."); + pass = 1'b0; + end + + /* + * Check a variable +: on a simple L-value. + */ + $display(); + bigr = 16'hxxxx; + ltlr = 16'hxxxx; + a = base; + bigr[(a)+:4] = 4'd3; + ltlr[(a)+:4] = 4'd3; + a = base+4; + bigr[(a)+:4] = 4'd2; + ltlr[(a)+:4] = 4'd2; + a = base+8; + bigr[(a)+:4] = 4'd1; + ltlr[(a)+:4] = 4'd1; + a = base+12; + bigr[(a)+:4] = 4'd0; + ltlr[(a)+:4] = 4'd0; + $displayh("bigr[a+:4]: ", bigr, ", ltlr[a+:4]: ", ltlr); + if (bigr !== big) begin + $display("FAILED: big endian variable L-value +: indexed select."); + pass = 1'b0; + end + if (ltlr !== ltl) begin + $display("FAILED: little endian variable L-value +: indexed select."); + pass = 1'b0; + end + + bigr = 16'h0000; + ltlr = 16'h0000; + a = 'bx; + bigr[(a)+:4] = 4'hf; + ltlr[(a)+:4] = 4'hf; + $displayh("bigr[a+='bx :4]: ", bigr, ", ltlr[a='bx +:4]: ", ltlr); + if (bigr !== 16'h0000) begin + $display("FAILED: big endian variable ('bx) L-value +: indexed select."); + pass = 1'b0; + end + if (ltlr !== 16'h0000) begin + $display("FAILED: little endian variable ('bx) L-value +: indexed select."); + pass = 1'b0; + end + + bigr = 16'h0000; + ltlr = 16'h0000; + a = base-1; + bigr[(a)+:4] = 4'b011x; + ltlr[(a)+:4] = 4'bx001; + a = base+13; + bigr[(a)+:4] = 4'bx001; + ltlr[(a)+:4] = 4'b011x; + $displayh("bigr[a=edge +:4]: ", bigr, ", ltlr[a=edge +:4]: ", ltlr); + if (bigr !== 16'h2003) begin + $display("FAILED: big endian edge L-value constant +: indexed select."); + pass = 1'b0; + end + if (ltlr !== 16'h2003) begin + $display("FAILED: little endian edge L-value constant +: indexed select."); + pass = 1'b0; + end + + /* + * Check a variable -: on a simple L-value. + */ + $display(); + bigr = 16'hxxxx; + ltlr = 16'hxxxx; + a = base+3; + bigr[(a)-:4] = 4'd3; + ltlr[(a)-:4] = 4'd3; + a = base+7; + bigr[(a)-:4] = 4'd2; + ltlr[(a)-:4] = 4'd2; + a = base+11; + bigr[(a)-:4] = 4'd1; + ltlr[(a)-:4] = 4'd1; + a = base+15; + bigr[(a)-:4] = 4'd0; + ltlr[(a)-:4] = 4'd0; + $displayh("bigr[a-:4]: ", bigr, ", ltlr[a-:4]: ", ltlr); + if (bigr !== big) begin + $display("FAILED: big endian variable L-value -: indexed select."); + pass = 1'b0; + end + if (ltlr !== ltl) begin + $display("FAILED: little endian variable L-value -: indexed select."); + pass = 1'b0; + end + + bigr = 16'h0000; + ltlr = 16'h0000; + a = 'bx; + bigr[(a)-:4] = 4'hf; + ltlr[(a)-:4] = 4'hf; + $displayh("bigr[a='bx -:4]: ", bigr, ", ltlr[a='bx -:4]: ", ltlr); + if (bigr !== 16'h0000) begin + $display("FAILED: big endian variable ('bx) L-value -: indexed select."); + pass = 1'b0; + end + if (ltlr !== 16'h0000) begin + $display("FAILED: little endian variable ('bx) L-value -: indexed select."); + pass = 1'b0; + end + + bigr = 16'h0000; + ltlr = 16'h0000; + a = base+2; + bigr[(a)-:4] = 4'b011x; + ltlr[(a)-:4] = 4'bx001; + a = base+16; + bigr[(a)-:4] = 4'bx001; + ltlr[(a)-:4] = 4'b011x; + $displayh("bigr[a=edge -:4]: ", bigr, ", ltlr[a=edge -:4]: ", ltlr); + if (bigr !== 16'h2003) begin + $display("FAILED: big endian edge L-value constant -: indexed select."); + pass = 1'b0; + end + if (ltlr !== 16'h2003) begin + $display("FAILED: little endian edge L-value constant -: indexed select."); + pass = 1'b0; + end + + /* + * All done. + */ + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2837451.v b/ivtest/ivltests/pr2837451.v new file mode 100644 index 000000000..c24797908 --- /dev/null +++ b/ivtest/ivltests/pr2837451.v @@ -0,0 +1,31 @@ +module pr2837451(); + +// this code provides a regression test that exercises +// vvp_fun_part_sa::recv_vec4_pv + +reg [3:0] a; +wire [7:0] b; +wire [3:0] c; +wire [3:0] d; +wire [3:0] e; + +assign b[5:2] = a; + +assign c = b[4:1]; +assign d = b[5:2]; +assign e = b[6:3]; + +initial begin + a = 4'b0101; + #1; + $display("%b %b %b %b %b", a, b, c, d, e); + if ((b === 8'bzz0101zz) + && (c === 4'b101z) + && (d === 4'b0101) + && (e === 4'bz010)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2842185.v b/ivtest/ivltests/pr2842185.v new file mode 100644 index 000000000..b43a4ce17 --- /dev/null +++ b/ivtest/ivltests/pr2842185.v @@ -0,0 +1,20 @@ +module pr2842185(); + +// check that dection of signal/genvar name collisions +// observes scope boundaries. + +genvar i; + +task MyTask; + +integer i; + +begin + $display("PASSED"); +end + +endtask + +initial MyTask; + +endmodule diff --git a/ivtest/ivltests/pr2842621.v b/ivtest/ivltests/pr2842621.v new file mode 100644 index 000000000..81adf4580 --- /dev/null +++ b/ivtest/ivltests/pr2842621.v @@ -0,0 +1,46 @@ +// A zero value MCD should be allowed, but does it process the arguments? +module top; + integer mcd, test; + + initial begin + test = 0; + // Skipped, but function is called. + #1; + $display($stime); + mcd = 0; + $fstrobe(mcd, "The $fstrobe(%d, ...) ran.", mcd); + $fdisplay(mcd, "The result for $fdisplay(%d, ...) is %d", mcd, my_func(1)); + $fwrite(mcd, "The result for $fwrite(%d, ...) is %d\n", mcd, my_func(1)); + $fflush(mcd); + + #1; + $display($stime); + mcd = 1; + $fstrobe(mcd, "The $fstrobe(%d, ...) ran.", mcd); + $fdisplay(mcd, "The result for $fdisplay(%d, ...) is %d", mcd, my_func(1)); + $fwrite(mcd, "The result for $fwrite(%d, ...) is %d\n", mcd, my_func(1)); + $fflush(mcd); + + // Skipped, but function is called. + #1; + $display($stime); + mcd = 0; + $fstrobe(mcd, "The $fstrobe(%d, ...) ran.", mcd); + $fdisplay(mcd, "The result for $fdisplay(%d, ...) is %d", mcd, my_func(1)); + $fwrite(mcd, "The result for $fwrite(%d, ...) is %d\n", mcd, my_func(1)); + $fflush(mcd); + + #1; + $display($stime); + if (test != 6) $display("FAILED side effect test"); + else $display("PASSED"); + end + + function integer my_func; + input incr; + begin + test = test + incr; + my_func = test; + end + endfunction +endmodule diff --git a/ivtest/ivltests/pr2842621_std.v b/ivtest/ivltests/pr2842621_std.v new file mode 100644 index 000000000..4ae121682 --- /dev/null +++ b/ivtest/ivltests/pr2842621_std.v @@ -0,0 +1,44 @@ +// A zero value MCD should be allowed, but does it process the arguments? +module top; + integer mcd, test; + + initial begin + test = 0; + // Skipped, but function is called. + #1; + $display($stime); + mcd = 0; + $fstrobe(mcd, "The $fstrobe(%d, ...) ran.", mcd); + $fdisplay(mcd, "The result for $fdisplay(%d, ...) is %d", mcd, my_func(1)); + $fwrite(mcd, "The result for $fwrite(%d, ...) is %d\n", mcd, my_func(1)); + + #1; + $display($stime); + mcd = 1; + $fstrobe(mcd, "The $fstrobe(%d, ...) ran.", mcd); + $fdisplay(mcd, "The result for $fdisplay(%d, ...) is %d", mcd, my_func(1)); + $fwrite(mcd, "The result for $fwrite(%d, ...) is %d\n", mcd, my_func(1)); + $fflush(mcd); + + // Skipped, but function is called. + #1; + $display($stime); + mcd = 0; + $fstrobe(mcd, "The $fstrobe(%d, ...) ran.", mcd); + $fdisplay(mcd, "The result for $fdisplay(%d, ...) is %d", mcd, my_func(1)); + $fwrite(mcd, "The result for $fwrite(%d, ...) is %d\n", mcd, my_func(1)); + + #1; + $display($stime); + if (test != 6) $display("FAILED side effect test"); + else $display("PASSED"); + end + + function integer my_func; + input incr; + begin + test = test + incr; + my_func = test; + end + endfunction +endmodule diff --git a/ivtest/ivltests/pr2848986.v b/ivtest/ivltests/pr2848986.v new file mode 100644 index 000000000..1581bb61f --- /dev/null +++ b/ivtest/ivltests/pr2848986.v @@ -0,0 +1,28 @@ +module top; + event evt; + reg rval; + + // Call user function with event (continuous assign). + wire wval = func(evt); + + function func; + input arg; + begin + $display("FAILED func."); + func = 1'bx; + end + endfunction + + task tsk; + input arg; + begin + $display("FAILED task."); + end + endtask + + // Call user function with event (procedural) and user task. + initial begin + rval = func(evt); + tsk(evt); + end +endmodule diff --git a/ivtest/ivltests/pr2849783.v b/ivtest/ivltests/pr2849783.v new file mode 100644 index 000000000..ea9798d7b --- /dev/null +++ b/ivtest/ivltests/pr2849783.v @@ -0,0 +1,41 @@ +module pr2849783(); + +reg i; +wire a, b, c, d; + +assign a = i; +assign b = a; + +assign c = 1; +assign d = c; + +reg pass; + +initial begin + i = 1; + pass = 1; + #1 $display("%b %b", a, b); + if ((a !== 1) || (b !== 1)) pass = 0; + #1 force a = 0; + #1 $display("%b %b", a, b); + if ((a !== 0) || (b !== 0)) pass = 0; + #1 release a; + #1 $display("%b %b", a, b); + if ((a !== 1) || (b !== 1)) pass = 0; + + #1 $display("%b %b", c, d); + if ((c !== 1) || (d !== 1)) pass = 0; + #1 force c = 0; + #1 $display("%b %b", c, d); + if ((c !== 0) || (d !== 0)) pass = 0; + #1 release c; + #1 $display("%b %b", c, d); + if ((c !== 1) || (d !== 1)) pass = 0; + + if (pass) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2859628.v b/ivtest/ivltests/pr2859628.v new file mode 100644 index 000000000..15fa0fd1a --- /dev/null +++ b/ivtest/ivltests/pr2859628.v @@ -0,0 +1,13 @@ +module top; + reg [3:0] array [0:1]; + + initial begin + $dumpfile("work/pr2859628.vcd"); + $dumpvars(0, top); + // This will complain that the array words have already been included! + // They have not been since array words are only explicitly added. + // The word/scope check code needs to be updated to ignore array words. + $dumpvars(0, array[0], array[1]); + #1; + end +endmodule diff --git a/ivtest/ivltests/pr2865563.v b/ivtest/ivltests/pr2865563.v new file mode 100644 index 000000000..b6fd229f1 --- /dev/null +++ b/ivtest/ivltests/pr2865563.v @@ -0,0 +1,24 @@ +module foo (); + + parameter CLOCK_FREQUENCY = 90e6; + + // CLOCK_PERIOD_BIT_WIDTH <= log2(90e6) + // log2(90e6) = 26.423 + parameter CLOCK_PERIOD_BIT_WIDTH = 26; + + // build something big enaugh to hold CLOCK_FREQUENCY x CLOCK_PERIOD_BIT_WIDTH sums. + parameter CP_SUM_BIT_WIDTH = 2 * CLOCK_PERIOD_BIT_WIDTH; + + // + // calculate a sane reset value. + // + wire [CLOCK_PERIOD_BIT_WIDTH-1:0] rst, rst2; + + assign rst = {1'd1, {CP_SUM_BIT_WIDTH-1 {1'd0}}} / CLOCK_FREQUENCY; + assign rst2 = (52'd2**(CP_SUM_BIT_WIDTH-1)) / CLOCK_FREQUENCY; + + initial + #1 if (rst == rst2) $display("PASSED"); + else $display("FAILED"); + +endmodule // foo diff --git a/ivtest/ivltests/pr2877555.v b/ivtest/ivltests/pr2877555.v new file mode 100644 index 000000000..e2dbf0199 --- /dev/null +++ b/ivtest/ivltests/pr2877555.v @@ -0,0 +1,10 @@ +module testbench; + // This should give us a vector of [-1:0] (A == 0). + parameter A = $clog2(1); + wire [A-1:0] x; + wire [A-1:0] y = x; + + // Check to see that we got a two bit wide wire. + initial if ($bits(x) == 2) $display("PASSED"); + else $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/pr2877564.v b/ivtest/ivltests/pr2877564.v new file mode 100644 index 000000000..26c48dc28 --- /dev/null +++ b/ivtest/ivltests/pr2877564.v @@ -0,0 +1,6 @@ +module testbench; +foo #(ASDF) bar(); +endmodule + +module foo #(parameter A=1); +endmodule diff --git a/ivtest/ivltests/pr2883958.v b/ivtest/ivltests/pr2883958.v new file mode 100644 index 000000000..19b199a05 --- /dev/null +++ b/ivtest/ivltests/pr2883958.v @@ -0,0 +1,77 @@ +`timescale 1s/1s + +module test(outp, outm, outl, in); + output outp, outm, outl; + input in; + + // Check a primitive. + assign #1 outp = ~in; + + // Check a multiplexer. + assign #1 outm = in ? in : 1'b0; + + // Check a LPM. + assign #1 outl = in === 1'b1; +endmodule + +// This is not exactly the same as the original code, but it is effectively +// the same and should test the same things that were failing. +`timescale 1ns/100ps + +module top; + reg in, passed; + wire outp, outm, outl; + + test dut(outp, outm, outl, in); + + initial begin + passed = 1'b1; + + #1100000000; + if (outp !== 1'bx) begin + $display("Failed initial prim. check, expected 1'bx, got %b.", outp); + passed = 1'b0; + end + if (outm !== 1'bx) begin + $display("Failed initial mux. check, expected 1'bx, got %b.", outm); + passed = 1'b0; + end + if (outl !== 1'b0) begin + $display("Failed initial LPM check, expected 1'b0, got %b.", outl); + passed = 1'b0; + end + + in = 0; + #1100000000; + if (outp !== 1'b1) begin + $display("Failed in=0 prim. check, expected 1'b1, got %b.", outp); + passed = 1'b0; + end + if (outm !== 1'b0) begin + $display("Failed in=0 mux. check, expected 1'b0, got %b.", outm); + passed = 1'b0; + end + if (outl !== 1'b0) begin + $display("Failed in=0 LPM check, expected 1'b0, got %b.", outl); + passed = 1'b0; + end + + in = 1; + #1100000000; + if (outp !== 1'b0) begin + $display("Failed in=1 prim. check, expected 1'b0, got %b.", outp); + passed = 1'b0; + end + if (outm !== 1'b1) begin + $display("Failed in=1 mux. check, expected 1'b1, got %b.", outm); + passed = 1'b0; + end + if (outl !== 1'b1) begin + $display("Failed in=1 LPM check, expected 1'b1, got %b.", outl); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + + end +endmodule diff --git a/ivtest/ivltests/pr2885048.v b/ivtest/ivltests/pr2885048.v new file mode 100644 index 000000000..8ff98a0f2 --- /dev/null +++ b/ivtest/ivltests/pr2885048.v @@ -0,0 +1,43 @@ +module bug; + +wire [7:0] r1; +wire [7:0] r2; +wire [7:0] r3; +wire [7:0] r4; +wire [7:0] r5; +wire [7:0] r6; +wire [7:0] r7; + +wire [7:0] r; + +function [7:0] fn; + +input [7:0] a; +input [7:0] b; +input [7:0] c; +input [7:0] d; +input [7:0] e; +input [7:0] f; +input [7:0] g; +input [7:0] h; + +begin + fn = a + b + c + d + e + f + g + h; +end + +endfunction + +assign {r1, r2, r3, r4, r5, r6, r7} = 56'd257; + +assign r = fn(r1, r2, r3, r4, r5, r6, r7, 8'd0); + +initial begin + #1 $display("r=%0d", r); + if (r !== 8'd2) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2890322.v b/ivtest/ivltests/pr2890322.v new file mode 100644 index 000000000..7a2d1a4e8 --- /dev/null +++ b/ivtest/ivltests/pr2890322.v @@ -0,0 +1,28 @@ +module pr2890322; + +reg [7:0] Array[0:1]; + +function [7:0] Sum; + +input [7:0] a; +input [7:0] b; + +begin + Sum = a + b; +end + +endfunction + +wire [7:0] Result = Sum(Array[0], Array[1]); + +initial begin + Array[0] = 1; + Array[1] = 2; + #1 $display(Result); + if (Result === 3) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2901556.v b/ivtest/ivltests/pr2901556.v new file mode 100644 index 000000000..55a3257b3 --- /dev/null +++ b/ivtest/ivltests/pr2901556.v @@ -0,0 +1,26 @@ +module top; + integer lp; + + wire signed [5:0] in = lp[5:0]; + + // If these two are combined "$signed({1'b0,in[5]})" then this will work + // as expected. + wire [5:0] #1 base = (in + (in >>> 2)) >>> 2; + wire signed [5:0] #1 fix = base + in[5]; + +// wire [5:0] base; // If this is missing the program will core dump! +// wire signed [5:0] #1 fix = ((in + (in >>> 2)) >>> 2) + $signed({1'b0,in[5]}); + + wire [6:0] #1 res = in + fix; + + always @(*) $display("%0d: %d %d %d %d", $time, $signed(in), $signed(base), + $signed(fix), $signed(res)); + // It appears that the final calculation event is being lost for fix == -1. + initial begin + lp = -7; + #5 lp = -5; + #1 lp = -6; + #5 if ($signed(res) !== -7) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2909386a.v b/ivtest/ivltests/pr2909386a.v new file mode 100644 index 000000000..933472920 --- /dev/null +++ b/ivtest/ivltests/pr2909386a.v @@ -0,0 +1,229 @@ +// Check the power operator (compile time). +module top; + reg pass; + + integer res; + + initial begin + pass = 1'b1; + + // Check the constant ** with various arguments (table 5-6 1364-2005). + + res = -3**'bx; + if (res !== 'bx) begin + $display("Failed: constant -3**'bx, expected 'bx, got %0d", res); + pass = 1'b0; + end + res = -1**'bx; + if (res !== 'bx) begin + $display("Failed: constant -1**'bx, expected 'bx, got %0d", res); + pass = 1'b0; + end + res = 0**'bx; + if (res !== 'bx) begin + $display("Failed: constant 0**'bx, expected 'bx, got %0d", res); + pass = 1'b0; + end + res = 1**'bx; + if (res !== 'bx) begin + $display("Failed: constant 1**'bx, expected 'bx, got %0d", res); + pass = 1'b0; + end + res = 3**'bx; + if (res !== 'bx) begin + $display("Failed: constant 3**'bx, expected 'bx, got %0d", res); + pass = 1'b0; + end + + res = 'bx**-3; + if (res !== 'bx) begin + $display("Failed: constant 'bx**-3, expected 'bx, got %0d", res); + pass = 1'b0; + end + res = 'bx**-2; + if (res !== 'bx) begin + $display("Failed: constant 'bx**-2, expected 'bx, got %0d", res); + pass = 1'b0; + end + res = 'bx**-1; + if (res !== 'bx) begin + $display("Failed: constant 'bx**-1, expected 'bx, got %0d", res); + pass = 1'b0; + end + res = 'bx**0; + if (res !== 'bx) begin + $display("Failed: constant 'bx**0, expected 'bx, got %0d", res); + pass = 1'b0; + end + res = 'bx**1; + if (res !== 'bx) begin + $display("Failed: constant 'bx**1, expected 'bx, got %0d", res); + pass = 1'b0; + end + res = 'bx**2; + if (res !== 'bx) begin + $display("Failed: constant 'bx**2, expected 'bx, got %0d", res); + pass = 1'b0; + end + res = 'bx**3; + if (res !== 'bx) begin + $display("Failed: constant 'bx**3, expected 'bx, got %0d", res); + pass = 1'b0; + end + + // Check the 1st line (rvalue is positive). + res = -3**3; + if (res !== -27) begin + $display("Failed: constant -3**3, expected -27, got %0d", res); + pass = 1'b0; + end + res = -3**2; + if (res !== 9) begin + $display("Failed: constant -3**2, expected 9, got %0d", res); + pass = 1'b0; + end + + res = -1**3; + if (res !== -1) begin + $display("Failed: constant -1**3, expected -1, got %0d", res); + pass = 1'b0; + end + res = -1**2; + if (res !== 1) begin + $display("Failed: constant -1**2, expected 1, got %0d", res); + pass = 1'b0; + end + + res = 0**3; + if (res !== 0) begin + $display("Failed: constant 0**3, expected 0, got %0d", res); + pass = 1'b0; + end + res = 0**2; + if (res !== 0) begin + $display("Failed: constant 0**2, expected 0, got %0d", res); + pass = 1'b0; + end + + res = 1**3; + if (res !== 1) begin + $display("Failed: constant 1**3, expected 1, got %0d", res); + pass = 1'b0; + end + res = 1**2; + if (res !== 1) begin + $display("Failed: constant 1**2, expected 1, got %0d", res); + pass = 1'b0; + end + + res = 3**3; + if (res !== 27) begin + $display("Failed: constant 3**3, expected 27, got %0d", res); + pass = 1'b0; + end + res = 3**2; + if (res !== 9) begin + $display("Failed: constant 3**2, expected 9, got %0d", res); + pass = 1'b0; + end + + // Check the 2nd line (rvalue is zero). + res = -3**0; + if (res !== 1) begin + $display("Failed: constant -3**0, expected 1, got %0d", res); + pass = 1'b0; + end + res = -2**0; + if (res !== 1) begin + $display("Failed: constant -2**0, expected 1, got %0d", res); + pass = 1'b0; + end + + res = -1**0; + if (res !== 1) begin + $display("Failed: constant -1**0, expected 1, got %0d", res); + pass = 1'b0; + end + + res = 0**0; + if (res !== 1) begin + $display("Failed: constant 0**0, expected 1, got %0d", res); + pass = 1'b0; + end + + res = 1**0; + if (res !== 1) begin + $display("Failed: constant 1**0, expected 1, got %0d", res); + pass = 1'b0; + end + + res = 2**0; + if (res !== 1) begin + $display("Failed: constant 2**0, expected 1, got %0d", res); + pass = 1'b0; + end + res = 3**0; + if (res !== 1) begin + $display("Failed: constant 3**0, expected 1, got %0d", res); + pass = 1'b0; + end + + // Check the 3rd line (rvalue is negative). + res = -2**-3; + if (res !== 0) begin + $display("Failed: constant -2**-3, expected 0, got %0d", res); + pass = 1'b0; + end + res = -2**-2; + if (res !== 0) begin + $display("Failed: constant -2**-2, expected 0, got %0d", res); + pass = 1'b0; + end + + res = -1**-3; + if (res !== -1) begin + $display("Failed: constant -1**-3, expected -1, got %0d", res); + pass = 1'b0; + end + res = -1**-2; + if (res !== 1) begin + $display("Failed: constant -1**-2, expected 1, got %0d", res); + pass = 1'b0; + end + + res = 0**-3; + if (res !== 'bx) begin + $display("Failed: constant 0**-3, expected 'bx, got %0d", res); + pass = 1'b0; + end + res = 0**-2; + if (res !== 'bx) begin + $display("Failed: constant 0**-2, expected 'bx, got %0d", res); + pass = 1'b0; + end + + res = 1**-3; + if (res !== 1) begin + $display("Failed: constant 1**-3, expected 1, got %0d", res); + pass = 1'b0; + end + res = 1**-2; + if (res !== 1) begin + $display("Failed: constant 1**-2, expected 1, got %0d", res); + pass = 1'b0; + end + + res = 2**-3; + if (res !== 0) begin + $display("Failed: constant 2**-3, expected 0, got %0d", res); + pass = 1'b0; + end + res = 2**-2; + if (res !== 0) begin + $display("Failed: constant 2**-2, expected 0, got %0d", res); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2909386b.v b/ivtest/ivltests/pr2909386b.v new file mode 100644 index 000000000..f22542022 --- /dev/null +++ b/ivtest/ivltests/pr2909386b.v @@ -0,0 +1,298 @@ +// Check the power operator (run time). +module top; + reg pass; + + integer res; + reg signed [31:0] l, r; + + initial begin + pass = 1'b1; + + // Check the constant ** with various arguments (table 5-6 1364-2005). + + l = -3; + r = 'bx; + res = l**r; + if (res !== 'bx) begin + $display("Failed: constant -3**'bx, expected 'bx, got %0d", res); + pass = 1'b0; + end + l = -1; + res = l**r; + if (res !== 'bx) begin + $display("Failed: constant -1**'bx, expected 'bx, got %0d", res); + pass = 1'b0; + end + l = 0; + res = l**r; + if (res !== 'bx) begin + $display("Failed: constant 0**'bx, expected 'bx, got %0d", res); + pass = 1'b0; + end + l = 1; + res = l**r; + if (res !== 'bx) begin + $display("Failed: constant 1**'bx, expected 'bx, got %0d", res); + pass = 1'b0; + end + l = 3; + res = l**r; + if (res !== 'bx) begin + $display("Failed: constant 3**'bx, expected 'bx, got %0d", res); + pass = 1'b0; + end + + l = 'bx; + r=-3; + res = l**r; + if (res !== 'bx) begin + $display("Failed: constant 'bx**-3, expected 'bx, got %0d", res); + pass = 1'b0; + end + r=-2; + res = l**r; + if (res !== 'bx) begin + $display("Failed: constant 'bx**-2, expected 'bx, got %0d", res); + pass = 1'b0; + end + r=-1; + res = l**r; + if (res !== 'bx) begin + $display("Failed: constant 'bx**-1, expected 'bx, got %0d", res); + pass = 1'b0; + end + r=0; + res = l**r; + if (res !== 'bx) begin + $display("Failed: constant 'bx**0, expected 'bx, got %0d", res); + pass = 1'b0; + end + r=1; + res = l**r; + if (res !== 'bx) begin + $display("Failed: constant 'bx**1, expected 'bx, got %0d", res); + pass = 1'b0; + end + r=2; + res = l**r; + if (res !== 'bx) begin + $display("Failed: constant 'bx**2, expected 'bx, got %0d", res); + pass = 1'b0; + end + r=3; + res = l**r; + if (res !== 'bx) begin + $display("Failed: constant 'bx**3, expected 'bx, got %0d", res); + pass = 1'b0; + end + + // Check the 1st line (rvalue is positive). + l=-3; + r=3; + res = l**r; + if (res !== -27) begin + $display("Failed: constant -3**3, expected -27, got %0d", res); + pass = 1'b0; + end + l=-3; + r=2; + res = l**r; + if (res !== 9) begin + $display("Failed: constant -3**2, expected 9, got %0d", res); + pass = 1'b0; + end + + l=-1; + r=3; + res = l**r; + if (res !== -1) begin + $display("Failed: constant -1**3, expected -1, got %0d", res); + pass = 1'b0; + end + l=-1; + r=2; + res = l**r; + if (res !== 1) begin + $display("Failed: constant -1**2, expected 1, got %0d", res); + pass = 1'b0; + end + + l=0; + r=3; + res = l**r; + if (res !== 0) begin + $display("Failed: constant 0**3, expected 0, got %0d", res); + pass = 1'b0; + end + l=0; + r=2; + res = l**r; + if (res !== 0) begin + $display("Failed: constant 0**2, expected 0, got %0d", res); + pass = 1'b0; + end + + l=1; + r=3; + res = l**r; + if (res !== 1) begin + $display("Failed: constant 1**3, expected 1, got %0d", res); + pass = 1'b0; + end + l=1; + r=2; + res = l**r; + if (res !== 1) begin + $display("Failed: constant 1**2, expected 1, got %0d", res); + pass = 1'b0; + end + + l=3; + r=3; + res = l**r; + if (res !== 27) begin + $display("Failed: constant 3**3, expected 27, got %0d", res); + pass = 1'b0; + end + l=3; + r=2; + res = l**r; + if (res !== 9) begin + $display("Failed: constant 3**2, expected 9, got %0d", res); + pass = 1'b0; + end + + // Check the 2nd line (rvalue is zero). + l=-3; + r=0; + res = l**r; + if (res !== 1) begin + $display("Failed: constant -3**0, expected 1, got %0d", res); + pass = 1'b0; + end + l=-2; + r=0; + res = l**r; + if (res !== 1) begin + $display("Failed: constant -2**0, expected 1, got %0d", res); + pass = 1'b0; + end + + l=-1; + r=0; + res = l**r; + if (res !== 1) begin + $display("Failed: constant -1**0, expected 1, got %0d", res); + pass = 1'b0; + end + + l=0; + r=0; + res = l**r; + if (res !== 1) begin + $display("Failed: constant 0**0, expected 1, got %0d", res); + pass = 1'b0; + end + + l=1; + r=0; + res = l**r; + if (res !== 1) begin + $display("Failed: constant 1**0, expected 1, got %0d", res); + pass = 1'b0; + end + + l=2; + r=0; + res = l**r; + if (res !== 1) begin + $display("Failed: constant 2**0, expected 1, got %0d", res); + pass = 1'b0; + end + l=3; + r=0; + res = l**r; + if (res !== 1) begin + $display("Failed: constant 3**0, expected 1, got %0d", res); + pass = 1'b0; + end + + // Check the 3rd line (rvalue is negative). + l=-2; + r=-3; + res = l**r; + if (res !== 0) begin + $display("Failed: constant -2**-3, expected 0, got %0d", res); + pass = 1'b0; + end + l=-2; + r=-2; + res = l**r; + if (res !== 0) begin + $display("Failed: constant -2**-2, expected 0, got %0d", res); + pass = 1'b0; + end + + l=-1; + r=-3; + res = l**r; + if (res !== -1) begin + $display("Failed: constant -1**-3, expected -1, got %0d", res); + pass = 1'b0; + end + l=-1; + r=-2; + res = l**r; + if (res !== 1) begin + $display("Failed: constant -1**-2, expected 1, got %0d", res); + pass = 1'b0; + end + + l=0; + r=-3; + res = l**r; + if (res !== 'bx) begin + $display("Failed: constant 0**-3, expected 'bx, got %0d", res); + pass = 1'b0; + end + l=0; + r=-2; + res = l**r; + if (res !== 'bx) begin + $display("Failed: constant 0**-2, expected 'bx, got %0d", res); + pass = 1'b0; + end + + l=1; + r=-3; + res = l**r; + if (res !== 1) begin + $display("Failed: constant 1**-3, expected 1, got %0d", res); + pass = 1'b0; + end + l=1; + r=-2; + res = l**r; + if (res !== 1) begin + $display("Failed: constant 1**-2, expected 1, got %0d", res); + pass = 1'b0; + end + + l=2; + r=-3; + res = l**r; + if (res !== 0) begin + $display("Failed: constant 2**-3, expected 0, got %0d", res); + pass = 1'b0; + end + l=2; + r=-2; + res = l**r; + if (res !== 0) begin + $display("Failed: constant 2**-2, expected 0, got %0d", res); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2909414.v b/ivtest/ivltests/pr2909414.v new file mode 100644 index 000000000..5bbac33a0 --- /dev/null +++ b/ivtest/ivltests/pr2909414.v @@ -0,0 +1,42 @@ +module Top; + +generate + genvar i; + + for (i = 0; i < 1; i = i + 1) begin + Sub1 SubMod1(); + end +endgenerate + +endmodule + + +module Sub1; + +wire [7:0] Value; + +Sub2 SubMod2(Value); + +defparam SubMod2.Width = 8; + +initial begin + #1; + $display("Value = %h", Value); + if (Value === 8'hff) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule + + +module Sub2(Out); + +parameter Width = 4; + +output [Width-1:0] Out; + +assign Out = {Width{1'b1}}; + +endmodule diff --git a/ivtest/ivltests/pr2909555.v b/ivtest/ivltests/pr2909555.v new file mode 100644 index 000000000..98067cb60 --- /dev/null +++ b/ivtest/ivltests/pr2909555.v @@ -0,0 +1,48 @@ +module top; + reg pass; + + reg [8:0] a; + wire [7:0] res_a; + + reg [6:0] b; + wire [7:0] res_b; + + reg signed [6:0] c; + wire [7:0] res_c; + + assign res_a = Copy(a); + assign res_b = Copy(b); + assign res_c = Copy(c); + + initial begin + pass = 1'b1; + a = 9'h101; + b = -7'd1; + c = -7'd1; + #1; + + if (res_a !== 8'h01) begin + $display("Failed to crop a vector, got %b.", res_a); + pass = 1'b0; + end + + if (res_b !== 8'h7f) begin + $display("Failed to zero extend an unsigned vector, got %b.", res_b); + pass = 1'b0; + end + + if (res_c !== 8'hff) begin + $display("Failed to sign extend a signed vector, got %b.", res_c); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + + function [7:0] Copy; + input [7:0] Value; + begin + Copy = Value; + end + endfunction +endmodule diff --git a/ivtest/ivltests/pr2913404.v b/ivtest/ivltests/pr2913404.v new file mode 100644 index 000000000..4a7c8cef5 --- /dev/null +++ b/ivtest/ivltests/pr2913404.v @@ -0,0 +1,70 @@ +module cast_large_real; + +reg [63:0] u64; +reg signed [63:0] i64; + +reg [64:0] u65; +reg signed [64:0] i65; + +real r; + +reg fail; + +initial begin + fail = 0; + + u64 = {1'b1, 63'd0}; + r = u64; + $display("Convert u64 to real"); + $display("Expect : %0f", 2.0**63); + $display("Got : %0f", r); + if (r != 2.0**63) fail = 1; + u64 = r; + $display("Convert real to u64"); + $display("Expect : %0d", {1'b1, 63'd0}); + $display("Got : %0d", u64); + if (u64 != {1'b1, 63'd0}) fail = 1; + + i64 = {1'b1, 63'd0}; + r = i64; + $display("Convert i64 to real"); + $display("Expect : %0f", -(2.0**63)); + $display("Got : %0f", r); + if (r != -(2.0**63)) fail = 1; + i64 = r; + $display("Convert real to i64"); + $display("Expect : %0d", $signed({1'b1, 63'd0})); + $display("Got : %0d", i64); + if (i64 != {1'b1, 63'd0}) fail = 1; + + u65 = {1'b1, 64'd0}; + r = u65; + $display("Convert u65 to real"); + $display("Expect : %0f", 2.0**64); + $display("Got : %0f", r); + if (r != 2.0**64) fail = 1; + u65 = r; + $display("Convert real to u65"); + $display("Expect : %0d", {1'b1, 64'd0}); + $display("Got : %0d", u65); + if (u65 != {1'b1, 64'd0}) fail = 1; + + i65 = {1'b1, 64'd0}; + r = i65; + $display("Convert i65 to real"); + $display("Expect : %0f", -(2.0**64)); + $display("Got : %0f", r); + if (r != -(2.0**64)) fail = 1; + i65 = r; + $display("Convert real to i65"); + $display("Expect : %0d", $signed({1'b1, 64'd0})); + $display("Got : %0d", i65); + if (i65 != {1'b1, 64'd0}) fail = 1; + + if (fail) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2913416.v b/ivtest/ivltests/pr2913416.v new file mode 100644 index 000000000..27423084e --- /dev/null +++ b/ivtest/ivltests/pr2913416.v @@ -0,0 +1,28 @@ +module bug; +reg pass; +reg Select; +reg signed [3:0] Delta; +reg signed [5:0] Value; + +wire signed [5:0] Value_ca = (Select ? 12 : 8) + Delta; + +initial begin + pass = 1'b1; + Select = 1; + Delta = -7; + Value = (Select ? 12 : 8) + Delta; + if (Value !== 5) begin + $display("FAILED: procedural assign, expected 5, got %d", Value); + pass = 1'b0; + end + + #1; + if (Value_ca !== 5) begin + $display("FAILED: continuous assign, expected 5, got %d", Value_ca); + pass = 1'b0; + end + + if (pass) $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2913438a.v b/ivtest/ivltests/pr2913438a.v new file mode 100644 index 000000000..7ded48148 --- /dev/null +++ b/ivtest/ivltests/pr2913438a.v @@ -0,0 +1,35 @@ +module bug; + +function [1:0] Copy; + +input [1:0] Value; + +begin + Copy = Value; +end + +endfunction + +integer i; +integer j; + +reg [1:0] Expect; +reg [1:0] Actual; +reg Failed; + +initial begin + Failed = 0; + for (i = 0; i < 4; i = i + 1) begin + for (j = 0; j < 4; j = j + 1) begin + Expect = (i%2)*2 + (j%2); + Actual = Copy((i%2)*2 + (j%2)); + if (Actual !== Expect) begin + $display("Failed: %0d,%0d expected %0d, got %0d", i, j, Expect, Actual); + Failed = 1; + end + end + end + if (!Failed) $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2913438b.v b/ivtest/ivltests/pr2913438b.v new file mode 100644 index 000000000..1711dc979 --- /dev/null +++ b/ivtest/ivltests/pr2913438b.v @@ -0,0 +1,44 @@ +module top; + reg [6:0] ltl; + reg signed [6:0] ltl_s; + reg [15:0] big; + reg result, pass; + + initial begin + pass = 1'b1; + + // An unsigned value should be zero padded. + ltl = 7'd127; + result = test(ltl); + if (result) begin + $display("Failed: unsigned argument was sign extended"); + pass = 1'b0; + end + + // This should be evaluated in an eight bit context since the + // function argument is eight bits. This will set the eight bit. + result = test(ltl+7'd1); + if (!result) begin + $display("Failed: function width does not determines expression width."); + pass = 1'b0; + end + + // A signed value should be sign padded. + ltl_s = -7'd1; + result = test(ltl_s); + if (!result) begin + $display("Failed: signed argument was not sign extended"); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + + function test ; + input signed [7:0] in; + begin + if (in[7]) test = 1'b1; + else test = 1'b0; + end + endfunction +endmodule diff --git a/ivtest/ivltests/pr2913927.v b/ivtest/ivltests/pr2913927.v new file mode 100644 index 000000000..a9ced2ad8 --- /dev/null +++ b/ivtest/ivltests/pr2913927.v @@ -0,0 +1,246 @@ +module top; + // We expect bits for the zero or mone parameters. The + // big test must also be at least , but Icarus currently + // creates 48 bits. I personally think this is the correct behavior. + parameter zero = 0; + parameter mone = -1; + parameter big = 'hffffffffffff; + + parameter max = 2**16; // We will call this many bits unlimited. + reg pass; + integer idx; + + initial begin + pass = 1'b1; + + /* + * Check with a bit select. + */ + $display("Checking the size with a bit select."); + $display("------------------------------------"); + // Test to see how far a decimal 0 is extended. + begin: loop_zero + for (idx = 0; idx < max; idx = idx + 1) begin + if (zero[idx] !== 0) disable loop_zero; + end + end + if (idx != max) begin + $display("The size of a decimal 0 parameter is %0d bits.", idx); + // Check that after the parameter is 1'bx. + if (zero[idx] !== 1'bx) begin + $display(" Failed: after bit must be 1'bx, got %b.", zero[idx]); + pass = 1'b0; + end + end else begin + $display("The size of a decimal 0 parameter is unlimited."); + end + // An unsized parameter must be at least 32 bits. + if (idx < 32) begin + $display(" Failed: unsized parameter must be >= 32 bits, got %0d.", idx); + pass = 1'b0; + end + // Check that before the parameter is 1'bx. + idx = -1; + if (zero[idx] !== 1'bx) begin + $display(" Failed: before bit must be 1'bx, got %b.", zero[idx]); + pass = 1'b0; + end + // Check that an undefined index gives 1'bx. + idx = 'bx; + if (zero[idx] !== 1'bx) begin + $display(" Failed: undefined select must be 1'bx, got %b.", zero[idx]); + pass = 1'b0; + end + + // Test to see how far a decimal -1 is extended. + begin: loop_mone + for (idx = 0; idx < max; idx = idx + 1) begin + if (mone[idx] !== 1) disable loop_mone; + end + end + if (idx != max) begin + $display("The size of a decimal -1 parameter is %0d bits.", idx); + // Check that after the parameter is 1'bx. + if (mone[idx] !== 1'bx) begin + $display(" Failed: after bit must be 1'bx, got %b", mone[idx]); + pass = 1'b0; + end + end else begin + $display("The size of a decimal -1 parameter is unlimited."); + end + // An unsized parameter must be at least 32 bits. + if (idx < 32) begin + $display(" Failed: unsized parameter must be >= 32 bits, got %0d.", idx); + pass = 1'b0; + end + // Check that before the parameter is 1'bx. + idx = -1; + if (mone[idx] !== 1'bx) begin + $display(" Failed: before bit must be 1'bx, got %b.", mone[idx]); + pass = 1'b0; + end + // Check that an undefined index gives 1'bx. + idx = 'bx; + if (mone[idx] !== 1'bx) begin + $display(" Failed: undefined select must be 1'bx, got %b.", mone[idx]); + pass = 1'b0; + end + + // Check to see if a parameter can be more than 32 bits (I expect + // unlimited or 48 bits). If they exist the first 48 bits must be 1 + // any remaining bits are 0. + begin: loop_big + for (idx = 0; idx < max; idx = idx + 1) begin + if (big[idx] !== (idx < 48)) disable loop_big; + end + end + if (idx != max) begin + $display("The size of a big decimal parameter is %0d bits.", idx); + // Check that after the parameter is 1'bx. + if (big[idx] !== 1'bx) begin + $display(" Failed: after bit must be 1'bx, got %b", big[idx]); + pass = 1'b0; + end + end else begin + $display("The size of a big decimal parameter is unlimited."); + end + // An unsized parameter must be at least 32 bits. + if (idx < 48) begin + $display(" Warning: 48 bit unsized parameter was truncated to %0d bits", + idx); + end + if (idx < 32) begin + $display(" Failed: unsized parameter must be >= 32 bits, got %0d.", idx); + pass = 1'b0; + end + // Check that before the parameter is 1'bx. + idx = -1; + if (big[idx] !== 1'bx) begin + $display(" Failed: before bit must be 1'bx, got %b.", big[idx]); + pass = 1'b0; + end + // Check that an undefined index gives 1'bx. + idx = 'bx; + if (big[idx] !== 1'bx) begin + $display(" Failed: undefined select must be 1'bx, got %b.", big[idx]); + pass = 1'b0; + end + + + /* + * Check with an indexed up select. + */ + $display(""); + $display("Checking the size with an indexed part select."); + $display("----------------------------------------------"); + // Test to see how far a decimal 0 is extended. + begin: loop_zero2 + for (idx = 0; idx < max; idx = idx + 1) begin + if (zero[idx+:1] !== 0) disable loop_zero2; + end + end + if (idx != max) begin + $display("The size of a decimal 0 parameter is %0d bits.", idx); + // Check that after the parameter is 1'bx. + if (zero[idx+:1] !== 1'bx) begin + $display(" Failed: after bit must be 1'bx, got %b", zero[idx+:1]); + pass = 1'b0; + end + end else begin + $display("The size of a decimal 0 parameter is unlimited."); + end + // An unsized parameter must be at least 32 bits. + if (idx < 32) begin + $display(" Failed: unsized parameter must be >= 32 bits, got %0d.", idx); + pass = 1'b0; + end + // Check that before the parameter is 1'bx. + idx = -1; + if (zero[idx+:1] !== 1'bx) begin + $display(" Failed: before bit must be 1'bx, got %b.", zero[idx+:1]); + pass = 1'b0; + end + // Check that an undefined index gives 1'bx. + idx = 'bx; + if (zero[idx+:1] !== 1'bx) begin + $display(" Failed: undefined select must be 1'bx, got %b.", zero[idx+:1]); + pass = 1'b0; + end + + // Test to see how far a decimal -1 is extended. + begin: loop_mone2 + for (idx = 0; idx < max; idx = idx + 1) begin + if (mone[idx+:1] !== 1) disable loop_mone2; + end + end + if (idx != max) begin + $display("The size of a decimal -1 parameter is %0d bits.", idx); + // Check that after the parameter is 1'bx. + if (mone[idx+:1] !== 1'bx) begin + $display(" Failed: after bit must be 1'bx, got %b", mone[idx+:1]); + pass = 1'b0; + end + end else begin + $display("The size of a decimal -1 parameter is unlimited."); + end + // An unsized parameter must be at least 32 bits. + if (idx < 32) begin + $display(" Failed: unsized parameter must be >= 32 bits, got %0d.", idx); + pass = 1'b0; + end + // Check that before the parameter is 1'bx. + idx = -1; + if (mone[idx+:1] !== 1'bx) begin + $display(" Failed: before bit must be 1'bx, got %b.", mone[idx+:1]); + pass = 1'b0; + end + // Check that an undefined index gives 1'bx. + idx = 'bx; + if (mone[idx+:1] !== 1'bx) begin + $display(" Failed: undefined select must be 1'bx, got %b.", mone[idx+:1]); + pass = 1'b0; + end + + // Check to see if a parameter can be more than 32 bits (I expect + // unlimited or 48 bits). If they exist the first 48 bits must be 1 + // any remaining bits are 0. + begin: loop_big2 + for (idx = 0; idx < max; idx = idx + 1) begin + if (big[idx+:1] !== (idx < 48)) disable loop_big2; + end + end + if (idx != max) begin + $display("The size of a big decimal parameter is %0d bits.", idx); + // Check that after the parameter is 1'bx. + if (big[idx+:1] !== 1'bx) begin + $display("Failed: after bit must be 1'bx, got %b", big[idx+:1]); + pass = 1'b0; + end + end else begin + $display("The size of a big decimal parameter is unlimited."); + end + // An unsized parameter must be at least 32 bits. + if (idx < 48) begin + $display(" Warning: 48 bit unsized parameter was truncated to %0d bits", + idx); + end + if (idx < 32) begin + $display(" Failed: unsized parameter must be >= 32 bits, got %0d.", idx); + pass = 1'b0; + end + // Check that before the parameter is 1'bx. + idx = -1; + if (big[idx+:1] !== 1'bx) begin + $display(" Failed: before bit must be 1'bx, got %b.", big[idx+:1]); + pass = 1'b0; + end + // Check that an undefined index gives 1'bx. + idx = 'bx; + if (big[idx+:1] !== 1'bx) begin + $display(" Failed: undefined select must be 1'bx, got %b.", big[idx+:1]); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2918095.v b/ivtest/ivltests/pr2918095.v new file mode 100644 index 000000000..8fff1c5a0 --- /dev/null +++ b/ivtest/ivltests/pr2918095.v @@ -0,0 +1,32 @@ +module bug; + reg pass; + reg [7:0] a, b; + real r; + + initial begin + pass = 1'b1; + a = 8'd255; + b = 8'd255; + if ((a + b) != 254.0) begin + $display("FAILED: addition != real constant."); + pass = 1'b0; + end + r = 254.0; + if ((a + b) != r) begin + $display("FAILED: addition != real variable."); + pass = 1'b0; + end + + if ((a * b) != 1.0) begin + $display("FAILED: multiplication != real constant."); + pass = 1'b0; + end + r = 1.0; + if ((a * b) != r) begin + $display("FAILED: multiplication != real variable."); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2922063.v b/ivtest/ivltests/pr2922063.v new file mode 100644 index 000000000..d91f25dfa --- /dev/null +++ b/ivtest/ivltests/pr2922063.v @@ -0,0 +1,60 @@ +module top; + reg pass; + integer val; + + initial begin + pass = 1'b1; + + // Check ARS in a fully signed context. + // All operands are signed. + val = -1; + val = 7'sd10 + (val >>> 1); + if (val !== 9) begin + $display("Failed ARS in signed context, got %d", val); + pass = 1'b0; + end + + // Check ARS in a cast signed context. + // This is fully signed as well because of the cast. + val = -1; + val = $signed(7'd10) + (val >>> 1); + if (val !== 9) begin + $display("Failed ARS in cast signed context, got %d", val); + pass = 1'b0; + end + // Check ARS in a self determined context. + // The system function is a primary and should create a self-determined + // context for the ARS. The addition is then done in an unsigned + // context, but this should still give the correct result. + // + // The bug is that Icarus is not sign padding the ARS since the + // addition is casting it to be unsigned. It should only be able to + // cast the sign of the result not the actual ARS! This casting is + // happening in suppress_binary_operand_sign_if_needed() defined in + // elab_expr.cc. It looks like $signed and $unsigned need some way + // to protect their argument self-determined context. + val = -1; + val = 7'd10 + $signed(val >>> 1); + if (val !== 9) begin + $display("Failed ARS in $signed context, got %d", val); + pass = 1'b0; + end + // Check ARS in a different self determined context. + // See comments above for $signed. + val = -1; + val = 7'd10 + $unsigned(val >>> 1); + if (val !== 9) begin + $display("Failed ARS in $unsigned context, got %d", val); + pass = 1'b0; + end + + // Check ARS in a different self determined context. + val = -1; + val = 7'd10 + {val >>> 1}; + if (val !== 9) begin + $display("Failed ARS in a concatenation context, got %d", val); + pass = 1'b0; + end + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2922063a.v b/ivtest/ivltests/pr2922063a.v new file mode 100644 index 000000000..eeaa948e6 --- /dev/null +++ b/ivtest/ivltests/pr2922063a.v @@ -0,0 +1,92 @@ +// This is the first part of a two-part test that checks that the argument to +// a $signed or $unsigned function is treated as a self-determined expression. +// This part performs tests where the argument is unsigned. + +module pr2922063a; + +reg [3:0] op1; +reg [2:0] op2; +reg [7:0] result; +reg fail; + +task check_result; + +input [7:0] value; + +begin + $write("Expected %b, got %b", value, result); + if (result !== value) begin + $write(" *"); + fail = 1; + end + $write("\n"); +end + +endtask + +initial begin + fail = 0; + + $display("-- Addition tests --"); + + op1 = 4'b1111; op2 = 3'b111; + result = 8'sd0 + $signed(op1 + op2); + check_result(8'b00000110); + result = 8'sd0 + $unsigned(op1 + op2); + check_result(8'b00000110); + + op1 = 4'b1000; op2 = 3'b011; + result = 8'sd0 + $signed(op1 + op2); + check_result(8'b11111011); + result = 8'sd0 + $unsigned(op1 + op2); + check_result(8'b00001011); + + $display("-- Multiply tests --"); + + op1 = 4'b0101; op2 = 3'b100; + result = 8'sd0 + $signed(op1 * op2); + check_result(8'b00000100); + result = 8'sd0 + $unsigned(op1 * op2); + check_result(8'b00000100); + + op1 = 4'b0010; op2 = 3'b100; + result = 8'sd0 + $signed(op1 * op2); + check_result(8'b11111000); + result = 8'sd0 + $unsigned(op1 * op2); + check_result(8'b00001000); + + $display("-- Left ASR tests --"); + + op1 = 4'b1010; + result = 8'sd0 + $signed(op1 <<< 1); + check_result(8'b00000100); + result = 8'sd0 + $unsigned(op1 <<< 1); + check_result(8'b00000100); + + op1 = 4'b0101; + result = 8'sd0 + $signed(op1 <<< 1); + check_result(8'b11111010); + result = 8'sd0 + $unsigned(op1 <<< 1); + check_result(8'b00001010); + + $display("-- Right ASR tests --"); + + op1 = 4'b1010; + result = 8'sd0 + $signed(op1 >>> 1); + check_result(8'b00000101); + result = 8'sd0 + $unsigned(op1 >>> 1); + check_result(8'b00000101); + + op1 = 4'b1010; + result = 8'sd0 + $signed(op1 >>> 0); + check_result(8'b11111010); + result = 8'sd0 + $unsigned(op1 >>> 0); + check_result(8'b00001010); + + if (fail) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2922063b.v b/ivtest/ivltests/pr2922063b.v new file mode 100644 index 000000000..10edf670b --- /dev/null +++ b/ivtest/ivltests/pr2922063b.v @@ -0,0 +1,92 @@ +// This is the second part of a two-part test that checks that the argument to +// a $signed or $unsigned function is treated as a self-determined expression. +// This part performs tests where the argument is signed. + +module pr2922063b; + +reg signed [3:0] op1; +reg signed [2:0] op2; +reg [7:0] result; +reg fail; + +task check_result; + +input [7:0] value; + +begin + $write("Expected %b, got %b", value, result); + if (result !== value) begin + $write(" *"); + fail = 1; + end + $write("\n"); +end + +endtask + +initial begin + fail = 0; + + $display("-- Addition tests --"); + + op1 = 4'b1111; op2 = 3'b111; + result = 8'sd0 + $signed(op1 + op2); + check_result(8'b11111110); + result = 8'sd0 + $unsigned(op1 + op2); + check_result(8'b00001110); + + op1 = 4'b1000; op2 = 3'b011; + result = 8'sd0 + $signed(op1 + op2); + check_result(8'b11111011); + result = 8'sd0 + $unsigned(op1 + op2); + check_result(8'b00001011); + + $display("-- Multiply tests --"); + + op1 = 4'b0101; op2 = 3'b100; + result = 8'sd0 + $signed(op1 * op2); + check_result(8'b11111100); + result = 8'sd0 + $unsigned(op1 * op2); + check_result(8'b00001100); + + op1 = 4'b0010; op2 = 3'b100; + result = 8'sd0 + $signed(op1 * op2); + check_result(8'b11111000); + result = 8'sd0 + $unsigned(op1 * op2); + check_result(8'b00001000); + + $display("-- Left ASR tests --"); + + op1 = 4'b1010; + result = 8'sd0 + $signed(op1 <<< 1); + check_result(8'b00000100); + result = 8'sd0 + $unsigned(op1 <<< 1); + check_result(8'b00000100); + + op1 = 4'b0101; + result = 8'sd0 + $signed(op1 <<< 1); + check_result(8'b11111010); + result = 8'sd0 + $unsigned(op1 <<< 1); + check_result(8'b00001010); + + $display("-- Right ASR tests --"); + + op1 = 4'b0101; + result = 8'sd0 + $signed(op1 >>> 1); + check_result(8'b00000010); + result = 8'sd0 + $unsigned(op1 >>> 1); + check_result(8'b00000010); + + op1 = 4'b1010; + result = 8'sd0 + $signed(op1 >>> 1); + check_result(8'b11111101); + result = 8'sd0 + $unsigned(op1 >>> 1); + check_result(8'b00001101); + + if (fail) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2924354.v b/ivtest/ivltests/pr2924354.v new file mode 100644 index 000000000..e4983b47c --- /dev/null +++ b/ivtest/ivltests/pr2924354.v @@ -0,0 +1,18 @@ +module main; + + assign impl = 1; + wire expl = 1; + + genvar i; + for (i = 0; i < 4; i = i+1) begin : scope + test dut(.foo(impl), .bar(expl)); + end + +endmodule // main + +module test(input wire foo, bar); + + initial begin + #1 $display("foo=%b, bar=%b", foo, bar); + end +endmodule // test diff --git a/ivtest/ivltests/pr2929913.v b/ivtest/ivltests/pr2929913.v new file mode 100644 index 000000000..05c499b36 --- /dev/null +++ b/ivtest/ivltests/pr2929913.v @@ -0,0 +1,18 @@ +`timescale 1ns/1ps + +module test; + + reg [3:0] fred[3:0]; + + initial + begin + $display("About to assign to array in initial block ..."); + fred[0] = 0; + $display("PASSED"); + end + + task automatic wilma; + wait (fred[0]); + endtask + +endmodule diff --git a/ivtest/ivltests/pr2930506.v b/ivtest/ivltests/pr2930506.v new file mode 100644 index 000000000..2442c85b0 --- /dev/null +++ b/ivtest/ivltests/pr2930506.v @@ -0,0 +1,14 @@ +`begin_keywords "1364-2005" +module test; + reg [800:1] string; + integer code; + real f; + + initial begin + string = "1e1"; + code = $sscanf(string, "%f", f); + if (f != 10.0) $display("FAILED: got %f", f); + else $display("PASSED"); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr2937417.v b/ivtest/ivltests/pr2937417.v new file mode 100644 index 000000000..4e0762993 --- /dev/null +++ b/ivtest/ivltests/pr2937417.v @@ -0,0 +1,52 @@ +module top; + reg a, pass; + wire x, y, ab; + + assign (weak1, weak0) x = (a === 1'b1) ? 1'b0 : 1'b1; + assign y = a; + // We need this since Icarus currently has a bug when forcing from + // an expression (it only uses the value when the force ran). + assign ab = ~a; + + tran (x, y); + + initial begin + // $monitor ($realtime,, x,y,,a); + pass = 1'b1; + // Check matching values. + #1 if ( x !== 1'bx || y !== 1'bx) begin + $display("Failed initial value, expected 1'bx, 1'bx, got %b %b", x, y); + pass = 1'b0; + end + #1 a = 1'b0; + #1 if ( x !== 1'b0 || y !== 1'b0) begin + $display("Failed same value, expected 1'b0, 1'b0, got %b %b", x, y); + pass = 1'b0; + end + #1 a = 1'b1; + #1 if ( x !== 1'b1 || y !== 1'b1) begin + $display("Failed same value, expected 1'b1, 1'b1, got %b %b", x, y); + pass = 1'b0; + end + // Now force and release the driving signal. + #1 force a = 1'bx; + #1 if ( x !== 1'bx || y !== 1'bx) begin + $display("Failed driver value, expected 1'bx, 1'bx, got %b %b", x, y); + pass = 1'b0; + end + #1 release a; + a = 1'b0; + #1 if ( x !== 1'b0 || y !== 1'b0) begin + $display("Failed driver value, expected 1'b0, 1'b0, got %b %b", x, y); + pass = 1'b0; + end + // Check that the other driver works. + #1 a = 1'bz; + #1 if ( x !== 1'b1 || y !== 1'b1) begin + $display("Failed alt. value, expected 1'b1, 1'b1, got %b %b", x, y); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2937417b.v b/ivtest/ivltests/pr2937417b.v new file mode 100644 index 000000000..9fb70fed0 --- /dev/null +++ b/ivtest/ivltests/pr2937417b.v @@ -0,0 +1,74 @@ +module top; + reg a, pass; + wire x, y, ab; + + assign (weak1, weak0) x = (a === 1'b1) ? 1'b0 : 1'b1; + assign y = a; + // We need this since Icarus currently has a bug when forcing from + // an expression (it only uses the value when the force ran). + assign ab = ~a; + + tran (x, y); + + initial begin + // $monitor ($realtime,, x,y,,a); + pass = 1'b1; + // Check matching values. + #1 if ( x !== 1'bx || y !== 1'bx) begin + $display("Failed initial value, expected 1'bx, 1'bx, got %b %b", x, y); + pass = 1'b0; + end + #1 a = 1'b0; + #1 if ( x !== 1'b0 || y !== 1'b0) begin + $display("Failed same value, expected 1'b0, 1'b0, got %b %b", x, y); + pass = 1'b0; + end + #1 a = 1'b1; + #1 if ( x !== 1'b1 || y !== 1'b1) begin + $display("Failed same value, expected 1'b1, 1'b1, got %b %b", x, y); + pass = 1'b0; + end + // Check force with opposite values. + #1 force x = ab; + #1 if ( x !== 1'b0 || y !== 1'bx) begin + $display("Failed force value, expected 1'b0, 1'bx, got %b %b", x, y); + pass = 1'b0; + end + #1 a = 1'b0; + #1 if ( x !== 1'b1 || y !== 1'bx) begin + $display("Failed force value, expected 1'b1, 1'bx, got %b %b", x, y); + pass = 1'b0; + end + // Now release. + #1 release x; + #1 if ( x !== 1'b0 || y !== 1'b0) begin + $display("Failed release value, expected 1'b0, 1'b0, got %b %b", x, y); + pass = 1'b0; + end + #1 a = 1'b1; + #1 if ( x !== 1'b1 || y !== 1'b1) begin + $display("Failed release value, expected 1'b1, 1'b1, got %b %b", x, y); + pass = 1'b0; + end + // Now force and release the driving signal. + #1 force a = 1'bx; + #1 if ( x !== 1'bx || y !== 1'bx) begin + $display("Failed driver value, expected 1'bx, 1'bx, got %b %b", x, y); + pass = 1'b0; + end + #1 release a; + a = 1'b0; + #1 if ( x !== 1'b0 || y !== 1'b0) begin + $display("Failed driver value, expected 1'b0, 1'b0, got %b %b", x, y); + pass = 1'b0; + end + // Check that the other driver works. + #1 a = 1'bz; + #1 if ( x !== 1'b1 || y !== 1'b1) begin + $display("Failed alt. value, expected 1'b1, 1'b1, got %b %b", x, y); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2937417c.v b/ivtest/ivltests/pr2937417c.v new file mode 100644 index 000000000..9fb70fed0 --- /dev/null +++ b/ivtest/ivltests/pr2937417c.v @@ -0,0 +1,74 @@ +module top; + reg a, pass; + wire x, y, ab; + + assign (weak1, weak0) x = (a === 1'b1) ? 1'b0 : 1'b1; + assign y = a; + // We need this since Icarus currently has a bug when forcing from + // an expression (it only uses the value when the force ran). + assign ab = ~a; + + tran (x, y); + + initial begin + // $monitor ($realtime,, x,y,,a); + pass = 1'b1; + // Check matching values. + #1 if ( x !== 1'bx || y !== 1'bx) begin + $display("Failed initial value, expected 1'bx, 1'bx, got %b %b", x, y); + pass = 1'b0; + end + #1 a = 1'b0; + #1 if ( x !== 1'b0 || y !== 1'b0) begin + $display("Failed same value, expected 1'b0, 1'b0, got %b %b", x, y); + pass = 1'b0; + end + #1 a = 1'b1; + #1 if ( x !== 1'b1 || y !== 1'b1) begin + $display("Failed same value, expected 1'b1, 1'b1, got %b %b", x, y); + pass = 1'b0; + end + // Check force with opposite values. + #1 force x = ab; + #1 if ( x !== 1'b0 || y !== 1'bx) begin + $display("Failed force value, expected 1'b0, 1'bx, got %b %b", x, y); + pass = 1'b0; + end + #1 a = 1'b0; + #1 if ( x !== 1'b1 || y !== 1'bx) begin + $display("Failed force value, expected 1'b1, 1'bx, got %b %b", x, y); + pass = 1'b0; + end + // Now release. + #1 release x; + #1 if ( x !== 1'b0 || y !== 1'b0) begin + $display("Failed release value, expected 1'b0, 1'b0, got %b %b", x, y); + pass = 1'b0; + end + #1 a = 1'b1; + #1 if ( x !== 1'b1 || y !== 1'b1) begin + $display("Failed release value, expected 1'b1, 1'b1, got %b %b", x, y); + pass = 1'b0; + end + // Now force and release the driving signal. + #1 force a = 1'bx; + #1 if ( x !== 1'bx || y !== 1'bx) begin + $display("Failed driver value, expected 1'bx, 1'bx, got %b %b", x, y); + pass = 1'b0; + end + #1 release a; + a = 1'b0; + #1 if ( x !== 1'b0 || y !== 1'b0) begin + $display("Failed driver value, expected 1'b0, 1'b0, got %b %b", x, y); + pass = 1'b0; + end + // Check that the other driver works. + #1 a = 1'bz; + #1 if ( x !== 1'b1 || y !== 1'b1) begin + $display("Failed alt. value, expected 1'b1, 1'b1, got %b %b", x, y); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2941939.v b/ivtest/ivltests/pr2941939.v new file mode 100644 index 000000000..269192cf1 --- /dev/null +++ b/ivtest/ivltests/pr2941939.v @@ -0,0 +1,37 @@ +`timescale 1ns/10ps + +module top; + reg pass; + reg a; + reg p; + wire y; + supply1 vdd; + supply0 gnd; + + tranif1 #(5) nmos_0(gnd, y, a); + tranif0 #(5) pmos_0(y, vdd, a); + + initial begin + $monitor($realtime,, y,, a); + pass = 1'b1; + p = 1'bx; + a <= 1'b0; + repeat (2) #10 a = ~a; + + #10; + if (pass) $display("PASSED"); + $finish; + end + + always @(a) begin + #4.99 if (y !== p) begin + $display("Failed at %.2f (early), expected %b, got %b", $realtime, p, y); + pass = 1'b0; + end + #0.02 if (y !== ~a) begin + $display("Failed at %.2f (late), expected %b, got %b", $realtime, ~a, y); + pass = 1'b0; + end + p = y; + end +endmodule diff --git a/ivtest/ivltests/pr2943394.v b/ivtest/ivltests/pr2943394.v new file mode 100644 index 000000000..1edf111fa --- /dev/null +++ b/ivtest/ivltests/pr2943394.v @@ -0,0 +1,93 @@ +module top; + reg pass; + reg [3:0] val; + reg [3:0] pv_val; + real rval; + + initial begin + pass = 1'b1; + + // A release of an unforced variable should not change the variable. + val = 4'b0110; + release val; + if (val !== 4'b0110) begin + $display("Failed release of unforced sig, expected 4'b0110, got %b", + val); + pass = 1'b0; + end + + // Verify that a force/release leaves the variable set correctly. + force val = 4'b1001; + release val; + if (val !== 4'b1001) begin + $display("Failed release of forced sig, expected 4'b1001, got %b", + val); + pass = 1'b0; + end + + // A release of a currently unforced varaible should not change it. + val = 4'b0110; + release val; + if (val !== 4'b0110) begin + $display("Failed release of unforced sig(2), expected 4'b0110, got %b", + val); + pass = 1'b0; + end + + // A release of an unforced variable should not change the variable. + pv_val = 4'b1001; + release pv_val[1]; + if (pv_val !== 4'b1001) begin + $display("Failed pv release of unforced sig, expected 4'b1001, got %b", + pv_val); + pass = 1'b0; + end + + // Verify that a force/release leaves the variable set correctly. + force pv_val[1] = 1'b1; + release pv_val[2:0]; + if (pv_val !== 4'b1011) begin + $display("Failed pv release of forced sig, expected 4'b1011, got %b", + pv_val); + pass = 1'b0; + end + + // A release of a currently unforced varaible should not change it. + pv_val = 4'b1001; + release pv_val[1]; + if (pv_val !== 4'b1001) begin + $display("Failed pv release of unforced sig(2), expected 4'b1001, got %b", + pv_val); + pass = 1'b0; + end + + // A release of an unforced variable should not change the variable. + rval = 1.0; + release rval; + if (rval != 1.0) begin + $display("Failed release of unforced sig, expected 1.0, got %.1f", + rval); + pass = 1'b0; + end + + // Verify that a force/release leaves the variable set correctly. + force rval = 2.0; + release rval; + if (rval != 2.0) begin + $display("Failed release of forced sig, expected 2.0, got %.1f", + rval); + pass = 1'b0; + end + + // A release of a currently unforced varaible should not change it. + rval = 1.0; + release rval; + if (rval != 1.0) begin + $display("Failed release of unforced sig(2), expected 1.0, got %.1f", + rval); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2951657.v b/ivtest/ivltests/pr2951657.v new file mode 100644 index 000000000..236e53f82 --- /dev/null +++ b/ivtest/ivltests/pr2951657.v @@ -0,0 +1,33 @@ +module m; + + reg [15:0] x,y; + + initial + begin + y = 0; + x <= 0; + x <= 1; + x <= 2; + x <= 3; + x <= 4; + x <= 5; + x <= 6; // Only this should cause an event, so y should become 1. + #10 + $display("x = %d (expect 6)", x); + $display("y = %d (expect 1)", y); + if (x !== 16'd6) begin + $display("FAILED"); + $finish; + end + if (y !== 16'd1) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + $finish; + end + + always @(x[0]) + y <= y + 1; + +endmodule diff --git a/ivtest/ivltests/pr2969724.v b/ivtest/ivltests/pr2969724.v new file mode 100644 index 000000000..f1a64f8c1 --- /dev/null +++ b/ivtest/ivltests/pr2969724.v @@ -0,0 +1,29 @@ +module top; + reg pass; + real rval; + reg [7:0] res; + + initial begin + pass = 1'b1; + res = 6.0; + if (res !== 8'd6) begin + $display("Failed blocking assignment, expeted 6, got %d", res); + pass = 1'b0; + end + + // The compiler is generating bad code for a NB-assign with a real r-value. + res <= 7.0; + #1 if (res !== 8'd7) begin + $display("Failed nonblocking assignment, expeted 7, got %d", res); + pass = 1'b0; + end + rval = 8.0; + res <= rval; + #1 if (res !== 8'd8) begin + $display("Failed nonblocking assignment, expeted 8, got %d", res); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2971207.v b/ivtest/ivltests/pr2971207.v new file mode 100644 index 000000000..c64303a1f --- /dev/null +++ b/ivtest/ivltests/pr2971207.v @@ -0,0 +1,132 @@ +module top; + reg pass, pass_f1, pass_f2, pass_f3, pass_f4, pass_f5; + reg [8*30:1] res; + + initial begin + pass = 1'b1; + + // Verify that the initial scope is correct. + $swrite(res, "%m"); + if (res != "top") begin + $display("Failed initial, got \"%0s\"", res); + pass = 1'b0; + end + + // Test %m in a named begin. + begin : my_begin + $swrite(res, "%m"); + if (res != "top.my_begin") begin + $display("Failed named begin (1st), got \"%0s\"", res); + pass = 1'b0; + end + + begin : my_begin_begin + // Test %m in a nested named begin. + $swrite(res, "%m"); + if (res != "top.my_begin.my_begin_begin") begin + $display("Failed nested named begin, got \"%0s\"", res); + pass = 1'b0; + end + end + + $swrite(res, "%m"); + if (res != "top.my_begin") begin + $display("Failed named begin (2nd), got \"%0s\"", res); + pass = 1'b0; + end + + // Test a named fork inside a named begin. + pass_f1 = 1'b1; + pass_f2 = 1'b1; + fork : my_begin_fork + begin + $swrite(res, "%m"); + if (res != "top.my_begin.my_begin_fork") begin + $display("Failed after named begin/fork (1), got \"%0s\"", res); + pass_f1 = 1'b0; + end + end + begin + $swrite(res, "%m"); + if (res != "top.my_begin.my_begin_fork") begin + $display("Failed after named begin/fork (2), got \"%0s\"", res); + pass_f2 = 1'b0; + end + end + join + + pass = pass & pass_f1 & pass_f2; + + $swrite(res, "%m"); + if (res != "top.my_begin") begin + $display("Failed named begin (3rd), got \"%0s\"", res); + pass = 1'b0; + end + end + + // Verify that the scope is back to normal. + $swrite(res, "%m"); + if (res != "top") begin + $display("Failed after named begin, got \"%0s\"", res); + pass = 1'b0; + end + + // Test %m in a named fork. + pass_f1 = 1'b1; + pass_f2 = 1'b1; + pass_f3 = 1'b1; + pass_f4 = 1'b1; + pass_f5 = 1'b1; + fork : my_fork + begin + $swrite(res, "%m"); + if (res != "top.my_fork") begin + $display("Failed after named fork (1), got \"%0s\"", res); + pass_f1 = 1'b0; + end + end + // Test a %m in a nested named begin. + begin : my_fork_begin + $swrite(res, "%m"); + if (res != "top.my_fork.my_fork_begin") begin + $display("Failed after named fork/begin, got \"%0s\"", res); + pass_f4 = 1'b0; + end + end + begin + $swrite(res, "%m"); + if (res != "top.my_fork") begin + $display("Failed after named fork (2), got \"%0s\"", res); + pass_f2 = 1'b0; + end + end + fork : my_fork_fork + begin + $swrite(res, "%m"); + if (res != "top.my_fork.my_fork_fork") begin + $display("Failed after named fork/fork, got \"%0s\"", res); + pass_f2 = 1'b0; + end + end + join + begin + $swrite(res, "%m"); + if (res != "top.my_fork") begin + $display("Failed after named fork (3), got \"%0s\"", res); + pass_f3 = 1'b0; + end + end + join + + pass = pass & pass_f1 & pass_f2 & pass_f3; + + // Verify that the scope is back to normal. + $swrite(res, "%m"); + if (res != "top") begin + $display("Failed final, got \"%0s\"", res); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2972866.sdf b/ivtest/ivltests/pr2972866.sdf new file mode 100644 index 000000000..e0e716815 --- /dev/null +++ b/ivtest/ivltests/pr2972866.sdf @@ -0,0 +1,24 @@ +(DELAYFILE + (TIMESCALE 1ns) + + (CELL + (CELLTYPE "CLK_BUF") + (INSTANCE L1) + (DELAY + (ABSOLUTE + (IOPATH in out (0.12::0.25) (0.11::0.25)) + ) + ) + ) + + (CELL + (CELLTYPE "CLK_BUF") + (INSTANCE L2) + (DELAY + (ABSOLUTE + (IOPATH in out (0.20::0.48) (0.19::0.44)) + ) + ) + ) + +) diff --git a/ivtest/ivltests/pr2972866.v b/ivtest/ivltests/pr2972866.v new file mode 100644 index 000000000..cf8ab2c74 --- /dev/null +++ b/ivtest/ivltests/pr2972866.v @@ -0,0 +1,46 @@ +`timescale 1ns/10ps + +module top; + reg pass, clk; + wire out; + + initial begin + $monitor("%f %b %b", $realtime, out, clk); + pass = 1'b1; + $sdf_annotate("ivltests/pr2972866.sdf", dut); + clk = 1'b0; + #10 clk = 1'b1; + #10 clk = 1'b0; + // Don't check for just PASSED since we are looking for modpath + // problems (SDF WARNING)! + #10 if (pass) $display("Simulation ran correctly."); + end + + always @(out) if (out !== clk && $time != 0) begin + $display("Failed to match, expected %b, got %b.", clk, out); + pass = 1'b0; + end + + + ckt dut (out, clk); +endmodule + +module ckt(clk_out, clk_in); + output clk_out; + input clk_in; + wire clk_l1; + + CLK_BUF L1 (clk_l1, clk_in); + CLK_BUF L2 (clk_out, clk_l1); +endmodule + +module CLK_BUF(out, in); + output out; + input in; + + buf b1 (out, in); + + specify + (in +=> out) = (0.1:0.1:0.1, 0.1:0.1:0.1); + endspecify +endmodule diff --git a/ivtest/ivltests/pr2973532.v b/ivtest/ivltests/pr2973532.v new file mode 100644 index 000000000..9c26acf91 --- /dev/null +++ b/ivtest/ivltests/pr2973532.v @@ -0,0 +1,22 @@ +module pr2973532; + +wire [15:0] a; +wire [7:0] b; +wire [7:0] c; + +assign b[5:2] = 4'b1111; + +assign c = 8'b00000000; + +assign a = {b, c}; + +initial begin + #1; + $display("%b", a); + if (a === 16'bzz1111zz00000000) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2974051.v b/ivtest/ivltests/pr2974051.v new file mode 100644 index 000000000..35487d5d5 --- /dev/null +++ b/ivtest/ivltests/pr2974051.v @@ -0,0 +1,54 @@ +// Extended version of original test case, covering part-driven operands +// for all logical operations. +module pr2974051; + +wire [7:0] a; +wire [7:0] b; +reg c; + +assign a[5:2] = 4'b0101; +assign b[5:2] = 4'b1010; + +wire [7:0] d = c ? b : a; + +wire [7:0] e = a & b; +wire [7:0] f = a | b; +wire [7:0] g = a ^ b; + +wire [7:0] h = a; +wire [7:0] i = ~a; + +reg fail; + +initial begin + fail = 0; + + c = 0; + #1 $display("%b", d); + if (d !== 8'bzz0101zz) fail = 1; + c = 1; + #1 $display("%b", d); + if (d !== 8'bzz1010zz) fail = 1; + + #1 $display("%b", e); + if (e !== 8'bxx0000xx) fail = 1; + + #1 $display("%b", f); + if (f !== 8'bxx1111xx) fail = 1; + + #1 $display("%b", g); + if (g !== 8'bxx1111xx) fail = 1; + + #1 $display("%b", h); + if (h !== 8'bzz0101zz) fail = 1; + + #1 $display("%b", i); + if (i !== 8'bxx1010xx) fail = 1; + + if (fail) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2974216.v b/ivtest/ivltests/pr2974216.v new file mode 100644 index 000000000..b476a54a5 --- /dev/null +++ b/ivtest/ivltests/pr2974216.v @@ -0,0 +1,46 @@ +// Verify that a zero width constant replication is handled correctly. +module top; + reg pass; + reg [31:0] in_full; + wire [31:0] pa_out_full, ca_out_full; + reg [29:0] in_part; + wire [31:0] pa_out_part, ca_out_part; + + initial begin + pass = 1'b1; + in_full = {16{2'b10}}; + in_part = {15{2'b01}}; + #1; + if (pa_out_full !== 32'b10101010101010101010101010101010) begin + $display("Failed: pa_out_full, got %b", pa_out_full); + pass = 1'b1; + end + if (ca_out_full !== 32'b10101010101010101010101010101010) begin + $display("Failed: ca_out_full, got %b", ca_out_full); + pass = 1'b1; + end + if (pa_out_part !== 32'bxx010101010101010101010101010101) begin + $display("Failed: pa_out_part, got %b", pa_out_part); + pass = 1'b1; + end + if (ca_out_part !== 32'bzz010101010101010101010101010101) begin + $display("Failed: ca_out_part, got %b", ca_out_part); + pass = 1'b1; + end + + if (pass) $display("PASSED"); + end + + param #(32) full(pa_out_full, ca_out_full, in_full); + param #(30) part(pa_out_part, ca_out_part, in_part); +endmodule + +module param #(parameter width = 32) ( + output reg [31:0] pa_out, + output wire [31:0] ca_out, + input [width-1:0] in); + + assign ca_out = {{32-width{1'bz}}, in}; + + always @* pa_out = {{32-width{1'bx}}, in}; +endmodule diff --git a/ivtest/ivltests/pr2974216b.v b/ivtest/ivltests/pr2974216b.v new file mode 100644 index 000000000..1d1a53882 --- /dev/null +++ b/ivtest/ivltests/pr2974216b.v @@ -0,0 +1,48 @@ +// Verify that a zero width signal replication is handled correctly. +module top; + reg pass; + reg [31:0] in_full; + wire [31:0] pa_out_full, ca_out_full; + reg [29:0] in_part; + wire [31:0] pa_out_part, ca_out_part; + + initial begin + pass = 1'b1; + in_full = {16{2'b10}}; + in_part = {15{2'b01}}; + #1; + if (pa_out_full !== 32'b10101010101010101010101010101010) begin + $display("Failed: pa_out_full, got %b", pa_out_full); + pass = 1'b1; + end + if (ca_out_full !== 32'b10101010101010101010101010101010) begin + $display("Failed: ca_out_full, got %b", ca_out_full); + pass = 1'b1; + end + if (pa_out_part !== 32'bxx010101010101010101010101010101) begin + $display("Failed: pa_out_part, got %b", pa_out_part); + pass = 1'b1; + end + if (ca_out_part !== 32'bzz010101010101010101010101010101) begin + $display("Failed: ca_out_part, got %b", ca_out_part); + pass = 1'b1; + end + + if (pass) $display("PASSED"); + end + + param #(32) full(pa_out_full, ca_out_full, in_full); + param #(30) part(pa_out_part, ca_out_part, in_part); +endmodule + +module param #(parameter width = 32) ( + output reg [31:0] pa_out, + output wire [31:0] ca_out, + input [width-1:0] in); + wire z_pad = 1'bz; + wire x_pad = 1'bx; + + assign ca_out = {{32-width{z_pad}}, in}; + + always @* pa_out = {{32-width{x_pad}}, in}; +endmodule diff --git a/ivtest/ivltests/pr2974294.v b/ivtest/ivltests/pr2974294.v new file mode 100644 index 000000000..54d030cfe --- /dev/null +++ b/ivtest/ivltests/pr2974294.v @@ -0,0 +1,24 @@ +module pr2974294; + +reg [7:0] array[1:0]; +wire [7:0] word; +reg fail; + +assign word = array[0]; + +initial begin + fail = 0; + #0 $display("%b", word); + if (word !== 8'bx) fail = 1; + #1 $display("%b", word); + if (word !== 8'bx) fail = 1; + array[0] = 8'd0; + #0 $display("%b", word); + if (word !== 8'd0) fail = 1; + if (fail) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr2976242.v b/ivtest/ivltests/pr2976242.v new file mode 100644 index 000000000..e5f0a2f30 --- /dev/null +++ b/ivtest/ivltests/pr2976242.v @@ -0,0 +1,72 @@ +`begin_keywords "1364-2005" +module top; + reg pass; + real rvar; + wire [3:0] var; + + assign var = rvar; + + initial begin + pass = 1'b1; + rvar <= 1'b0; + #1 rvar = 1'b1; + #1 rvar = 2'b10; + #1 rvar = 2'b11; + #1 if (pass) $display("PASSED"); + end + + real_to_bit u1(rvar); + real_to_real u2(rvar); + real_to_real u3[1:0](rvar); + real_to_vec u4(rvar); + real_to_vec u5[1:0](rvar); + bit_to_real u6(var[0]); + vec_to_real u7(var); + vec_to_real u8[1:0](var); +endmodule + +// Check a real value going to a single bit. +module real_to_bit (input wire in); + always @(in) if (in !== $stime%2) begin + $display("Failed real_to_bit %m at %1d, got %b, expected %2b", + $stime, in, $stime%2); + top.pass = 1'b0; + end +endmodule + +// Check a real value going to a real wire. +module real_to_real (input wire real in); + always @(in) if (in != $stime) begin + $display("Failed real_to_real %m at %1d, got %0d, expected %0d", + $stime, in, $stime); + top.pass = 1'b0; + end +endmodule + +// Check a real value going to multiple bit. +module real_to_vec (input wire [3:0] in); + always @(in) if (in !== $stime) begin + $display("Failed real_to_vec %m at %1d, got %0d, expected %0d", + $stime, in, $stime); + top.pass = 1'b0; + end +endmodule + +// Check a single bit going to a real wire. +module bit_to_real (input wire real in); + always @(in) if (in != $stime%2) begin + $display("Failed bit_to_real %m at %1d, got %0d, expected %0d", + $stime, in, $stime%2); + top.pass = 1'b0; + end +endmodule + +// Check a vector going to a real wire. +module vec_to_real (input wire real in); + always @(in) if (in != $stime) begin + $display("Failed vec_to_real %m at %1d, got %0d, expected %0d", + $stime, in, $stime); + top.pass = 1'b0; + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr2976242b.v b/ivtest/ivltests/pr2976242b.v new file mode 100644 index 000000000..3eadcb66f --- /dev/null +++ b/ivtest/ivltests/pr2976242b.v @@ -0,0 +1,74 @@ +`timescale 1ns/100ps +module top; + reg pass; + reg in; + wire out_bit; + wire [3:0] out_vec, out_arr; + wire real r_bit, r_vec; + wire real r_arr[1:0]; + + initial begin + pass = 1'b1; + in <= 1'b0; + #1 in = 1'b1; + #0.5 in = 1'b0; + #0.5 in = 1'b1; + #0.5 in = 1'b0; + #0.5 in = 1'b1; + #0.5 in = 1'b0; + #0.5 in = 1'b1; + #1 if (pass) $display("PASSED"); + end + + real_to_xx u1(out_bit, in); + always @(out_bit) if (out_bit !== ($stime % 2)) begin + $display("Failed real_to_xx, got %b, expected %1b", out_bit, $stime%2); + pass = 1'b0; + end + + real_to_xx u2(out_vec, in); + always @(out_vec) if (out_vec !== $stime) begin + $display("Failed real_to_xx(vec), got %b, expected %2b", out_vec, $stime); + pass = 1'b0; + end + + real_to_xx u3[1:0](out_arr, in); + always @(out_arr) #0.1 if ((out_arr[1:0] !== ($stime % 4)) && + (out_arr[3:2] !== ($stime % 4))) begin + $display("Failed real_to_xx[1:0], got %b, expected %2b%2b", out_arr, + $stime%4, $stime%4); + pass = 1'b0; + end + + bit_to_real u4(r_bit, in); + always @(r_bit) if (r_bit != ($stime % 2)) begin + $display("Failed bit_to_real, got %f, expected %1b", r_bit, $stime%2); + pass = 1'b0; + end + + vec_to_real u5(r_vec, in); + always @(r_vec) if (r_vec != $stime) begin + $display("Failed vec_to_real, got %f, expected %1b", r_vec, $stime); + pass = 1'b0; + end + +endmodule + +// Check a real value going to a various things. +module real_to_xx (output wire real out, input wire in); + real rval; + assign out = rval; + always @(posedge in) rval = rval + 1; +endmodule + +module bit_to_real (output wire out, input wire in); + reg rval = 0; + assign out = rval; + always @(posedge in) rval = rval + 1; +endmodule + +module vec_to_real (output wire [3:0] out, input wire in); + reg [3:0] rval = 0; + assign out = rval; + always @(posedge in) rval = rval + 1; +endmodule diff --git a/ivtest/ivltests/pr2976242c.v b/ivtest/ivltests/pr2976242c.v new file mode 100644 index 000000000..174c2fb2c --- /dev/null +++ b/ivtest/ivltests/pr2976242c.v @@ -0,0 +1,47 @@ +`timescale 1ns/100ps +module top; + reg in; + wire [3:0] vec; + wire [4:0] bvec; + wire real r_vec, r_arr, r_io; + + initial in <= 1'b0; + + // You cannot go to multiple real values (have multiple instances). + vec_to_real u1[1:0](r_vec, in); + + // A real port cannot be used in an arrayed instance. + arr_real u2a[1:0](bvec, in); + arr_real u2b[1:0](r_arr, in); + + // You cannot connect a real to an inout port. + io_vec_to_real u3(r_io, in); + + // You cannot have a inout port declared real. + io_real_to_vec u4(vec, in); + +endmodule + +module vec_to_real (output wire [3:0] out, input wire in); + reg [3:0] rval = 0; + assign out = rval; + always @(posedge in) rval = rval + 1; +endmodule + +module arr_real(output wire real out, input wire in); + real rval; + assign out = rval; + always @(posedge in) rval = rval + 1; +endmodule + +module io_vec_to_real(inout wire [3:0] out, input wire in); + reg [3:0] rval = 0; + assign out = rval; + always @(posedge in) rval = rval + 1; +endmodule + +module io_real_to_vec(inout wire real out, input wire in); + real rval; + assign out = rval; + always @(posedge in) rval = rval + 1; +endmodule diff --git a/ivtest/ivltests/pr298.v b/ivtest/ivltests/pr298.v new file mode 100644 index 000000000..150b90e35 --- /dev/null +++ b/ivtest/ivltests/pr298.v @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2001 Philip Blundell + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +primitive p (Q, D); +input D; +output Q; +reg Q; +initial Q = 1'b0; +table + 0 : ? : 0; + 1 : ? : 1; +endtable +endprimitive + +module m; + +reg D; +wire Q; +reg A; +wire QQ; + +p(Q, D); +buf(QQ, Q); + +initial + begin + // The #1 is needed here to allow the initial values to + // settle. Without it, there is a time-0 race. + #1 $display(QQ, Q); + #10 + D = 0; + #15 + $display(QQ, Q); + #20 + D = 1; + #25 + $display(QQ, Q); + $finish(0); + end +endmodule diff --git a/ivtest/ivltests/pr2985542.v b/ivtest/ivltests/pr2985542.v new file mode 100644 index 000000000..72aa63d5d --- /dev/null +++ b/ivtest/ivltests/pr2985542.v @@ -0,0 +1,24 @@ +module main; + + wire [3:0] b = 4'b1111; + wire [3:0] c = 4'b1111; + + initial begin + #0; // avoid time-0 race + $display("%b", ((c & ~(1'b1<<9'h00)) & b)); // s.b. 1110 + $display("%b", |((c & ~(1'b1<<9'h00)) & b)); // s.b. 1 + + if ( ((c & ~(1'b1<<9'h00)) & b) !== 4'b1110) begin + $display("FAILED (1)"); + $finish; + end + + if (|((c & ~(1'b1<<9'h00)) & b) !== 1'b1) begin + $display("FAILED (2)"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/pr2986497.v b/ivtest/ivltests/pr2986497.v new file mode 100644 index 000000000..afefe9dbe --- /dev/null +++ b/ivtest/ivltests/pr2986497.v @@ -0,0 +1,22 @@ +`begin_keywords "1364-2005" +module top(arg); + input [31:0] arg; + + wire [31:0] out_0; + wire [31:0] out_1; + reg [31:0] var; + + add dut_0 (var, var, out_0); + add dut_1 (arg, var, out_1); + +endmodule + +module add(in0, in1, out); + input [31:0] in0; + input [31:0] in1; + output reg [31:0] out; + + // This works if you explicitly specify the sensitivity list. + always @* out = in0 + in1; +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr2986528.v b/ivtest/ivltests/pr2986528.v new file mode 100644 index 000000000..69f5b9f94 --- /dev/null +++ b/ivtest/ivltests/pr2986528.v @@ -0,0 +1,49 @@ +// Icarus has a number of places where it can calculate %. +module top; + parameter out0 = 64'shF333333333333392 % 3'sd3; + reg passed; + wire signed [63:0] in; + wire signed [2:0] const_w0; + reg signed [63:0] out1; + wire signed [63:0] out2; + reg signed [63:0] out3; + + assign in = 64'hF333333333333392; + assign const_w0 = 3'sd3; + + always @* begin + out1 = (in % const_w0); + end + + assign out2 = (in % const_w0); + + initial begin + passed = 1'b1; + #1; + $display("Testing %0d %% %0d.", in, const_w0); + // Check the parameter result. + if (out0 !== -2) begin + $display("Failed: constant %%, expected -2, got %0d.", out0); + passed = 1'b0; + end + // Check the always result. + if (out1 !== -2) begin + $display("Failed: procedural %%, expected -2, got %0d.", out1); + passed = 1'b0; + end + // Check the CA result. + if (out2 !== -2) begin + $display("Failed: CA %%, expected -2, got %0d.", out2); + passed = 1'b0; + end + // Check a compile time constant result. + out3 = 64'shF333333333333392 % 3'sd3; + if (out3 !== -2) begin + $display("Failed: CA %%, expected -2, got %0d.", out3); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/pr2991457.v b/ivtest/ivltests/pr2991457.v new file mode 100644 index 000000000..953c00164 --- /dev/null +++ b/ivtest/ivltests/pr2991457.v @@ -0,0 +1,13 @@ +module top; + reg [3:0] val; + + initial begin + val = 4'b1111; + // The 'b0 should have a minimum size of integer width. This implies + // that val should be zero extended before it is inverted. Making + // this a false expression. See 1364-2005 (3.5.1 for width and 5.4 + // for how the width is propagated. + if (~val == 'b0) $display("Failed."); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr2991457b.v b/ivtest/ivltests/pr2991457b.v new file mode 100644 index 000000000..f76147684 --- /dev/null +++ b/ivtest/ivltests/pr2991457b.v @@ -0,0 +1,22 @@ +/* + * This is interesting, and not completely intuitive. In the code + * below, the variable "tmp" is assigned the value 4'bxxxx, then + * compated with the unsized literal 'hx. Since 'hx is unsized, it + * is padded to the width of an integer, and the padding is done + * by extending the 'bx. But in the comparison, the unsigned "tmp" + * is ZERO extended. Therefore, "tmp" and 'hx are NOT equal. + */ +module main; + + reg [3:0] tmp; + + initial begin + tmp = 'hx; + if (tmp !== 'hx) begin + $display("PASSED"); + $finish; + end + $display("FAILED"); + end + +endmodule // main diff --git a/ivtest/ivltests/pr2994193.v b/ivtest/ivltests/pr2994193.v new file mode 100644 index 000000000..9fe9badfa --- /dev/null +++ b/ivtest/ivltests/pr2994193.v @@ -0,0 +1,85 @@ +/* Crash.v - reproduces a simulation-time crash (PLI assertion failure) + +Copyright: Bluespec, Inc. 2010 +License: GPLv2 or later + +Transcript: +> uname -a +Linux jnewbern-laptop 2.6.32-21-generic #32-Ubuntu SMP Fri Apr 16 08:09:38 UTC 2010 x86_64 GNU/Linux +> iverilog -V +Icarus Verilog version 0.9.2 (v0_9_2) + ... +> iverilog -v -o crash -Wall Crash.v +... +/usr/lib/ivl/system.sft: Processing System Function Table file. +/usr/lib/ivl/v2005_math.sft: Processing System Function Table file. +/usr/lib/ivl/va_math.sft: Processing System Function Table file. +Using language generation: IEEE1364-2005,no-specify,xtypes,icarus-misc +PARSING INPUT +LOCATING TOP-LEVEL MODULES + Crash + ... done, 0 seconds. +ELABORATING DESIGN + ... done, 0 seconds. +RUNNING FUNCTORS + -F cprop ... + -F nodangle ... + ... 1 iterations deleted 0 dangling signals and 0 events. + ... 2 iterations deleted 0 dangling signals and 1 events. +CALCULATING ISLANDS + ... done, 0 seconds. +CODE GENERATION + ... invoking target_design + ... done, 0 seconds. +STATISTICS +lex_string: add_count=50 hit_count=17 +> ./crash +VCD info: dumpfile dump.vcd opened for output. +VCD warning: $dumpvars ignored, previously called at simtime 0 +vvp: vpi_priv.cc:165: PLI_INT32 vpi_free_object(__vpiHandle*): Assertion `ref' failed. +Aborted +*/ +module Crash(); + + // Create clock + reg CLK; + + initial begin + CLK = 1'b0; + end + + always begin + #5; + CLK = 1'b1; + #5; + CLK = 1'b0; + end + + // Setup dumpfile at startup + initial begin + $dumpfile("dump.vcd"); + $dumpvars; + end + + // Count cycles + reg [7:0] counter; + + initial begin + counter = 8'd0; + end + + always @(posedge CLK) begin + counter <= counter + 1; + end + + // Call system tasks on particular cycles + always@(posedge CLK) + begin + if (counter == 8'd2) $dumpvars; // repeated! + if (counter >= 8'd200) begin + $display("PASSED"); + $finish(32'd0); + end + end + +endmodule diff --git a/ivtest/ivltests/pr2998515.v b/ivtest/ivltests/pr2998515.v new file mode 100644 index 000000000..058cf8c11 --- /dev/null +++ b/ivtest/ivltests/pr2998515.v @@ -0,0 +1,24 @@ +module top; + reg pass; + reg signed [63:0] error; + + initial begin + pass = 1'b1; + error = 0; + error = error + 64'h40000000; + error = error + 64'h80000000; + if (error !== 64'hc0000000) begin + $display("FAILED immediate add, got %h", error); + pass = 1'b0; + end + + error = error + -64'sh40000000; + error = error + -64'sh80000000; + if (error !== 64'h00000000) begin + $display("FAILED immediate add, got %h", error); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3011327.v b/ivtest/ivltests/pr3011327.v new file mode 100644 index 000000000..f1491b275 --- /dev/null +++ b/ivtest/ivltests/pr3011327.v @@ -0,0 +1,42 @@ +module main; + reg pass; + + genvar i; + generate + for( i=1; i<3; i=i+1 ) + begin : U + reg [1:0] x; + end + for( i=0; i<2; i=i+1 ) + begin : V + initial begin + U[(i+1)%4].x = 2'd0; + #5; + U[(i+1)%4].x = i; + end + end + endgenerate + + initial begin + pass = 1'b1; + #4; + if (U[1].x != 2'd0) begin + $display("Failed to clear U[1].x, got %b", U[1].x); + pass = 1'b0; + end + if (U[2].x != 2'd0) begin + $display("Failed to clear U[2].x, got %b", U[1].x); + pass = 1'b0; + end + #2; + if (U[1].x != 2'd0) begin + $display("Failed to set U[1].x, expected 2'd0, got %b", U[1].x); + pass = 1'b0; + end + if (U[2].x != 2'd1) begin + $display("Failed to set U[2].x, expected 2'd1, got %b", U[1].x); + pass = 1'b0; + end + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3012758.inc b/ivtest/ivltests/pr3012758.inc new file mode 100644 index 000000000..3574e4766 --- /dev/null +++ b/ivtest/ivltests/pr3012758.inc @@ -0,0 +1,3 @@ + initial begin + $display("PASSED"); + end diff --git a/ivtest/ivltests/pr3012758.v b/ivtest/ivltests/pr3012758.v new file mode 100644 index 000000000..33445a789 --- /dev/null +++ b/ivtest/ivltests/pr3012758.v @@ -0,0 +1,4 @@ +`define TESTFILE "ivltests/pr3012758.inc" +module top; +`include `TESTFILE +endmodule diff --git a/ivtest/ivltests/pr3015421.v b/ivtest/ivltests/pr3015421.v new file mode 100644 index 000000000..c7635be40 --- /dev/null +++ b/ivtest/ivltests/pr3015421.v @@ -0,0 +1,17 @@ +// This test verifies that an incorrect function and task definition +// does not crash the compiler. +module main(); + // A number of errors here: int and return are not supported + // (SystemVerilog), so the function definition will fail. The + // return should also be inside the begin/end pair. + function int pick; + input myvar; + begin + end + return 0 + endfunction + + // This is a syntax error missing ';' on the task line. + task foo + endtask +endmodule diff --git a/ivtest/ivltests/pr3022502.v b/ivtest/ivltests/pr3022502.v new file mode 100644 index 000000000..401aa4a2d --- /dev/null +++ b/ivtest/ivltests/pr3022502.v @@ -0,0 +1,44 @@ +/* Verify that a tail recursive real ternary expression does not + * overflow the available thread words. */ +module top; + reg pass; + real vout; + integer j; + + always @(j) begin + vout = (j == 0) ? 0.0 : + (j == 1) ? 0.1 : + (j == 2) ? 0.2 : + (j == 3) ? 0.3 : + (j == 4) ? 0.4 : + (j == 5) ? 0.5 : + (j == 6) ? 0.6 : + (j == 7) ? 0.7 : + (j == 8) ? 0.8 : + (j == 9) ? 0.9 : + (j == 10) ? 1.0 : + (j == 11) ? 1.1 : + (j == 12) ? 1.2 : + (j == 13) ? 1.3 : + (j == 14) ? 1.4 : + (j == 15) ? 1.5 : + (j == 16) ? 1.6 : + (j == 17) ? 1.7 : + (j == 18) ? 1.8 : + (j == 19) ? 1.9 : 0.0; + end + + initial begin + pass = 1'b1; + + for (j=0; j<20; j=j+1) begin + #1; + if (vout != j/10.0) begin + $display("Failed: at %0d, got %f", j, vout); + pass = 1'b0; + end + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3024131.v b/ivtest/ivltests/pr3024131.v new file mode 100644 index 000000000..cf2c21ccf --- /dev/null +++ b/ivtest/ivltests/pr3024131.v @@ -0,0 +1,13 @@ +// Verify that the width is only propagated for a vector multiply. +// The second (real valued) multiply should not set the expression +// width to 1. +module top; + integer Ival = 14; + integer result; + + initial begin + result = Ival * 216 * 140e-3; + if (result !== 423) $display("Failed:, expected 423, got %0d", result); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3039548.v b/ivtest/ivltests/pr3039548.v new file mode 100644 index 000000000..291272e22 --- /dev/null +++ b/ivtest/ivltests/pr3039548.v @@ -0,0 +1,11 @@ +module check_this; + +reg [5:0] offset; +reg [9:0] enablemask; + initial begin + enablemask = 10'b00000_00110; + offset = 0; + $display("%b", {enablemask, (16'h0 + 8'h80 + offset )}); + $display("%b", {enablemask, (16'h0 + (8'h80 + offset))}); + end +endmodule // check_this diff --git a/ivtest/ivltests/pr304.v b/ivtest/ivltests/pr304.v new file mode 100644 index 000000000..49b02e530 --- /dev/null +++ b/ivtest/ivltests/pr304.v @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module stimulus; + +reg[9:0] foo; + +initial +begin + foo <= 0-155; + #1000 if (foo !== 10'h365) begin + $display("FAILED -- foo = %b", foo); + $finish; + end + + $display("PASSED"); + +end + +endmodule diff --git a/ivtest/ivltests/pr3044843.v b/ivtest/ivltests/pr3044843.v new file mode 100644 index 000000000..e2ef408e2 --- /dev/null +++ b/ivtest/ivltests/pr3044843.v @@ -0,0 +1,12 @@ +module top; + parameter ab = 8; + parameter ch = 2; + + reg [63:0] r; + + initial begin + r[0+:ab * ch] = 2; + if (r !== 64'hxxxxxxxxxxxx0002) $display("Failed, got %h", r); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3054101a.v b/ivtest/ivltests/pr3054101a.v new file mode 100644 index 000000000..1e1043c5f --- /dev/null +++ b/ivtest/ivltests/pr3054101a.v @@ -0,0 +1,321 @@ +// Check the various variable bit selects (MSB > LSB). +module top; + parameter [4:1] ap = 4'h8; + parameter [4:1] bp = 4'h7; + parameter [0:-3] cp = 4'h8; + parameter [0:-3] dp = 4'h7; + + reg passed; + + wire [4:1] a = 4'h8; + wire [4:1] b = 4'h7; + wire [0:0] s0 = 0; + wire [1:0] s1 = 0; + wire [2:0] s2 = 0; + reg [4:1] ar = 4'h8; + reg [4:1] br = 4'h7; + + wire [0:-3] c = 4'h8; + wire [0:-3] d = 4'h7; + wire [0:0] s3 = 0; + wire [1:0] s4 = 0; + reg [0:-3] cr = 4'h8; + reg [0:-3] dr = 4'h7; + + wire res_a0 = a[s0]; + wire res_b0 = b[s0]; + wire res_a1 = a[s1]; + wire res_b1 = b[s1]; + wire res_a2 = a[s2]; + wire res_b2 = b[s2]; + + wire res_c3 = c[s3]; + wire res_d3 = d[s3]; + wire res_c4 = c[s4]; + wire res_d4 = d[s4]; + + reg [4:1] res_ab; + reg [0:-3] res_cd; + + initial begin + #1; + passed = 1'b1; + + // Check procedural R-value variable bit selects of a net. + + $display("a[s0]: %b", a[s0]); + if (a[s0] !== 1'bx) begin + $display("Failed a[s0], expected 1'bx, got %b", a[s0]); + passed = 1'b0; + end + + $display("b[s0]: %b", b[s0]); + if (b[s0] !== 1'bx) begin + $display("Failed b[s0], expected 1'bx, got %b", b[s0]); + passed = 1'b0; + end + + $display("a[s1]: %b", a[s1]); + if (a[s1] !== 1'bx) begin + $display("Failed a[s1], expected 1'bx, got %b", a[s1]); + passed = 1'b0; + end + + $display("b[s1]: %b", b[s1]); + if (b[s1] !== 1'bx) begin + $display("Failed b[s1], expected 1'bx, got %b", b[s1]); + passed = 1'b0; + end + + $display("a[s2]: %b", a[s2]); + if (a[s2] !== 1'bx) begin + $display("Failed a[s2], expected 1'bx, got %b", a[s2]); + passed = 1'b0; + end + + $display("b[s2]: %b", b[s2]); + if (b[s2] !== 1'bx) begin + $display("Failed b[s2], expected 1'bx, got %b", b[s2]); + passed = 1'b0; + end + + $display("c[s3]: %b", c[s3]); + if (c[s3] !== 1'b1) begin + $display("Failed c[s3], expected 1'b1, got %b", c[s3]); + passed = 1'b0; + end + + $display("d[s3]: %b", d[s3]); + if (d[s3] !== 1'b0) begin + $display("Failed d[s3], expected 1'b0, got %b", d[s3]); + passed = 1'b0; + end + + $display("c[s4]: %b", c[s4]); + if (c[s4] !== 1'b1) begin + $display("Failed c[s4], expected 1'b1, got %b", c[s4]); + passed = 1'b0; + end + + $display("d[s4]: %b", d[s4]); + if (d[s4] !== 1'b0) begin + $display("Failed d[s4], expected 1'b0, got %b", d[s4]); + passed = 1'b0; + end + + // Check procedural R-value variable bit selects of a parameter. + + $display("ap[s0]: %b", ap[s0]); + if (ap[s0] !== 1'bx) begin + $display("Failed ap[s0], expected 1'bx, got %b", ap[s0]); + passed = 1'b0; + end + + $display("bp[s0]: %b", bp[s0]); + if (bp[s0] !== 1'bx) begin + $display("Failed bp[s0], expected 1'bx, got %b", bp[s0]); + passed = 1'b0; + end + + $display("ap[s1]: %b", ap[s1]); + if (ap[s1] !== 1'bx) begin + $display("Failed ap[s1], expected 1'bx, got %b", ap[s1]); + passed = 1'b0; + end + + $display("bp[s1]: %b", bp[s1]); + if (bp[s1] !== 1'bx) begin + $display("Failed bp[s1], expected 1'bx, got %b", bp[s1]); + passed = 1'b0; + end + + $display("ap[s2]: %b", ap[s2]); + if (ap[s2] !== 1'bx) begin + $display("Failed ap[s2], expected 1'bx, got %b", ap[s2]); + passed = 1'b0; + end + + $display("bp[s2]: %b", bp[s2]); + if (bp[s2] !== 1'bx) begin + $display("Failed bp[s2], expected 1'bx, got %b", bp[s2]); + passed = 1'b0; + end + + $display("cp[s3]: %b", cp[s3]); + if (cp[s3] !== 1'b1) begin + $display("Failed cp[s3], expected 1'b1, got %b", cp[s3]); + passed = 1'b0; + end + + $display("dp[s3]: %b", dp[s3]); + if (dp[s3] !== 1'b0) begin + $display("Failed dp[s3], expected 1'b0, got %b", dp[s3]); + passed = 1'b0; + end + + $display("cp[s4]: %b", cp[s4]); + if (cp[s4] !== 1'b1) begin + $display("Failed cp[s4], expected 1'b1, got %b", cp[s4]); + passed = 1'b0; + end + + $display("dp[s4]: %b", dp[s4]); + if (dp[s4] !== 1'b0) begin + $display("Failed dp[s4], expected 1'b0, got %b", dp[s4]); + passed = 1'b0; + end + + // Check procedural R-value variable bit selects of a reg. + + $display("ar[s0]: %b", ar[s0]); + if (ar[s0] !== 1'bx) begin + $display("Failed ar[s0], expected 1'bx, got %b", ar[s0]); + passed = 1'b0; + end + + $display("br[s0]: %b", br[s0]); + if (br[s0] !== 1'bx) begin + $display("Failed br[s0], expected 1'bx, got %b", br[s0]); + passed = 1'b0; + end + + $display("ar[s1]: %b", ar[s1]); + if (ar[s1] !== 1'bx) begin + $display("Failed ar[s1], expected 1'bx, got %b", ar[s1]); + passed = 1'b0; + end + + $display("br[s1]: %b", br[s1]); + if (br[s1] !== 1'bx) begin + $display("Failed br[s1], expected 1'bx, got %b", br[s1]); + passed = 1'b0; + end + + $display("ar[s2]: %b", ar[s2]); + if (ar[s2] !== 1'bx) begin + $display("Failed ar[s2], expected 1'bx, got %b", ar[s2]); + passed = 1'b0; + end + + $display("br[s2]: %b", br[s2]); + if (br[s2] !== 1'bx) begin + $display("Failed br[s2], expected 1'bx, got %b", br[s2]); + passed = 1'b0; + end + + $display("cr[s3]: %b", cr[s3]); + if (cr[s3] !== 1'b1) begin + $display("Failed cr[s3], expected 1'b1, got %b", cr[s3]); + passed = 1'b0; + end + + $display("dr[s3]: %b", dr[s3]); + if (dr[s3] !== 1'b0) begin + $display("Failed dr[s3], expected 1'b0, got %b", dr[s3]); + passed = 1'b0; + end + + $display("cr[s4]: %b", cr[s4]); + if (cr[s4] !== 1'b1) begin + $display("Failed cr[s4], expected 1'b1, got %b", cr[s4]); + passed = 1'b0; + end + + $display("dr[s4]: %b", dr[s4]); + if (dr[s4] !== 1'b0) begin + $display("Failed dr[s4], expected 1'b0, got %b", dr[s4]); + passed = 1'b0; + end + + // Check continuous assignment R-value variable bit selects. + + if (res_a0 !== 1'bx) begin + $display("Failed res_a0, expected 1'bx, got %b", res_a0); + passed = 1'b0; + end + + if (res_b0 !== 1'bx) begin + $display("Failed res_b0, expected 1'bx, got %b", res_b0); + passed = 1'b0; + end + + if (res_a1 !== 1'bx) begin + $display("Failed res_a1, expected 1'bx, got %b", res_a1); + passed = 1'b0; + end + + if (res_b1 !== 1'bx) begin + $display("Failed res_b1, expected 1'bx, got %b", res_b1); + passed = 1'b0; + end + + if (res_a2 !== 1'bx) begin + $display("Failed res_a2, expected 1'bx, got %b", res_a2); + passed = 1'b0; + end + + if (res_b2 !== 1'bx) begin + $display("Failed res_b2, expected 1'bx, got %b", res_b2); + passed = 1'b0; + end + + if (res_c3 !== 1'b1) begin + $display("Failed res_c3, expected 1'b1, got %b", res_c3); + passed = 1'b0; + end + + if (res_d3 !== 1'b0) begin + $display("Failed res_d3, expected 1'b0, got %b", res_d3); + passed = 1'b0; + end + + if (res_c4 !== 1'b1) begin + $display("Failed res_c4, expected 1'b1, got %b", res_c4); + passed = 1'b0; + end + + if (res_d4 !== 1'b0) begin + $display("Failed res_d4, expected 1'b0, got %b", res_d4); + passed = 1'b0; + end + + // Check procedural L-value variable bit selects. + + res_ab = 4'bxxxx; + res_ab[s0] = 1'b0; + if (res_ab !== 4'bxxxx) begin + $display("Failed res_ab[s0], expected 4'bxxxx, got %b", res_ab); + passed = 1'b0; + end + + res_ab = 4'bxxxx; + res_ab[s1] = 1'b0; + if (res_ab !== 4'bxxxx) begin + $display("Failed res_ab[s1], expected 4'bxxxx, got %b", res_ab); + passed = 1'b0; + end + + res_ab = 4'bxxxx; + res_ab[s2] = 1'b0; + if (res_ab !== 4'bxxxx) begin + $display("Failed res_ab[s2], expected 4'bxxxx, got %b", res_ab); + passed = 1'b0; + end + + res_cd = 4'bxxxx; + res_cd[s3] = 1'b0; + if (res_cd !== 4'b0xxx) begin + $display("Failed res_cd[s3], expected 4'b0xxx, got %b", res_cd); + passed = 1'b0; + end + + res_cd = 4'bxxxx; + res_cd[s4] = 1'b0; + if (res_cd !== 4'b0xxx) begin + $display("Failed res_cd[s4], expected 4'b0xxx, got %b", res_cd); + passed = 1'b0; + end + + if (passed) $display("Compare tests passed"); + end +endmodule diff --git a/ivtest/ivltests/pr3054101b.v b/ivtest/ivltests/pr3054101b.v new file mode 100644 index 000000000..f72e4d334 --- /dev/null +++ b/ivtest/ivltests/pr3054101b.v @@ -0,0 +1,321 @@ +// Check the various variable bit selects (LSB > MSB). +module top; + parameter [-4:-1] ap = 4'h1; + parameter [-4:-1] bp = 4'he; + parameter [-3:0] cp = 4'h1; + parameter [-3:0] dp = 4'he; + + reg passed; + + wire [-4:-1] a = 4'h1; + wire [-4:-1] b = 4'he; + wire [0:0] s0 = 0; + wire [1:0] s1 = 0; + wire [2:0] s2 = 0; + reg [-4:-1] ar = 4'h1; + reg [-4:-1] br = 4'he; + + wire [-3:0] c = 4'h1; + wire [-3:0] d = 4'he; + wire [0:0] s3 = 0; + wire [1:0] s4 = 0; + reg [-3:0] cr = 4'h1; + reg [-3:0] dr = 4'he; + + wire res_a0 = a[s0]; + wire res_b0 = b[s0]; + wire res_a1 = a[s1]; + wire res_b1 = b[s1]; + wire res_a2 = a[s2]; + wire res_b2 = b[s2]; + + wire res_c3 = c[s3]; + wire res_d3 = d[s3]; + wire res_c4 = c[s4]; + wire res_d4 = d[s4]; + + reg [-4:-1] res_ab; + reg [-3:0] res_cd; + + initial begin + #1; + passed = 1'b1; + + // Check procedural R-value variable bit selects of a net. + + $display("a[s0]: %b", a[s0]); + if (a[s0] !== 1'bx) begin + $display("Failed a[s0], expected 1'bx, got %b", a[s0]); + passed = 1'b0; + end + + $display("b[s0]: %b", b[s0]); + if (b[s0] !== 1'bx) begin + $display("Failed b[s0], expected 1'bx, got %b", b[s0]); + passed = 1'b0; + end + + $display("a[s1]: %b", a[s1]); + if (a[s1] !== 1'bx) begin + $display("Failed a[s1], expected 1'bx, got %b", a[s1]); + passed = 1'b0; + end + + $display("b[s1]: %b", b[s1]); + if (b[s1] !== 1'bx) begin + $display("Failed b[s1], expected 1'bx, got %b", b[s1]); + passed = 1'b0; + end + + $display("a[s2]: %b", a[s2]); + if (a[s2] !== 1'bx) begin + $display("Failed a[s2], expected 1'bx, got %b", a[s2]); + passed = 1'b0; + end + + $display("b[s2]: %b", b[s2]); + if (b[s2] !== 1'bx) begin + $display("Failed b[s2], expected 1'bx, got %b", b[s2]); + passed = 1'b0; + end + + $display("c[s3]: %b", c[s3]); + if (c[s3] !== 1'b1) begin + $display("Failed c[s3], expected 1'b1, got %b", c[s3]); + passed = 1'b0; + end + + $display("d[s3]: %b", d[s3]); + if (d[s3] !== 1'b0) begin + $display("Failed d[s3], expected 1'b0, got %b", d[s3]); + passed = 1'b0; + end + + $display("c[s4]: %b", c[s4]); + if (c[s4] !== 1'b1) begin + $display("Failed c[s4], expected 1'b1, got %b", c[s4]); + passed = 1'b0; + end + + $display("d[s4]: %b", d[s4]); + if (d[s4] !== 1'b0) begin + $display("Failed d[s4], expected 1'b0, got %b", d[s4]); + passed = 1'b0; + end + + // Check procedural R-value variable bit selects of a parameter. + + $display("ap[s0]: %b", ap[s0]); + if (ap[s0] !== 1'bx) begin + $display("Failed ap[s0], expected 1'bx, got %b", ap[s0]); + passed = 1'b0; + end + + $display("bp[s0]: %b", bp[s0]); + if (bp[s0] !== 1'bx) begin + $display("Failed bp[s0], expected 1'bx, got %b", bp[s0]); + passed = 1'b0; + end + + $display("ap[s1]: %b", ap[s1]); + if (ap[s1] !== 1'bx) begin + $display("Failed ap[s1], expected 1'bx, got %b", ap[s1]); + passed = 1'b0; + end + + $display("bp[s1]: %b", bp[s1]); + if (bp[s1] !== 1'bx) begin + $display("Failed bp[s1], expected 1'bx, got %b", bp[s1]); + passed = 1'b0; + end + + $display("ap[s2]: %b", ap[s2]); + if (ap[s2] !== 1'bx) begin + $display("Failed ap[s2], expected 1'bx, got %b", ap[s2]); + passed = 1'b0; + end + + $display("bp[s2]: %b", bp[s2]); + if (bp[s2] !== 1'bx) begin + $display("Failed bp[s2], expected 1'bx, got %b", bp[s2]); + passed = 1'b0; + end + + $display("cp[s3]: %b", cp[s3]); + if (cp[s3] !== 1'b1) begin + $display("Failed cp[s3], expected 1'b1, got %b", cp[s3]); + passed = 1'b0; + end + + $display("dp[s3]: %b", dp[s3]); + if (dp[s3] !== 1'b0) begin + $display("Failed dp[s3], expected 1'b0, got %b", dp[s3]); + passed = 1'b0; + end + + $display("cp[s4]: %b", cp[s4]); + if (cp[s4] !== 1'b1) begin + $display("Failed cp[s4], expected 1'b1, got %b", cp[s4]); + passed = 1'b0; + end + + $display("dp[s4]: %b", dp[s4]); + if (dp[s4] !== 1'b0) begin + $display("Failed dp[s4], expected 1'b0, got %b", dp[s4]); + passed = 1'b0; + end + + // Check procedural R-value variable bit selects of a reg. + + $display("ar[s0]: %b", ar[s0]); + if (ar[s0] !== 1'bx) begin + $display("Failed ar[s0], expected 1'bx, got %b", ar[s0]); + passed = 1'b0; + end + + $display("br[s0]: %b", br[s0]); + if (br[s0] !== 1'bx) begin + $display("Failed br[s0], expected 1'bx, got %b", br[s0]); + passed = 1'b0; + end + + $display("ar[s1]: %b", ar[s1]); + if (ar[s1] !== 1'bx) begin + $display("Failed ar[s1], expected 1'bx, got %b", ar[s1]); + passed = 1'b0; + end + + $display("br[s1]: %b", br[s1]); + if (br[s1] !== 1'bx) begin + $display("Failed br[s1], expected 1'bx, got %b", br[s1]); + passed = 1'b0; + end + + $display("ar[s2]: %b", ar[s2]); + if (ar[s2] !== 1'bx) begin + $display("Failed ar[s2], expected 1'bx, got %b", ar[s2]); + passed = 1'b0; + end + + $display("br[s2]: %b", br[s2]); + if (br[s2] !== 1'bx) begin + $display("Failed br[s2], expected 1'bx, got %b", br[s2]); + passed = 1'b0; + end + + $display("cr[s3]: %b", cr[s3]); + if (cr[s3] !== 1'b1) begin + $display("Failed cr[s3], expected 1'b1, got %b", cr[s3]); + passed = 1'b0; + end + + $display("dr[s3]: %b", dr[s3]); + if (dr[s3] !== 1'b0) begin + $display("Failed dr[s3], expected 1'b0, got %b", dr[s3]); + passed = 1'b0; + end + + $display("cr[s4]: %b", cr[s4]); + if (cr[s4] !== 1'b1) begin + $display("Failed cr[s4], expected 1'b1, got %b", cr[s4]); + passed = 1'b0; + end + + $display("dr[s4]: %b", dr[s4]); + if (dr[s4] !== 1'b0) begin + $display("Failed dr[s4], expected 1'b0, got %b", dr[s4]); + passed = 1'b0; + end + + // Check continuous assignment R-value variable bit selects. + + if (res_a0 !== 1'bx) begin + $display("Failed res_a0, expected 1'bx, got %b", res_a0); + passed = 1'b0; + end + + if (res_b0 !== 1'bx) begin + $display("Failed res_b0, expected 1'bx, got %b", res_b0); + passed = 1'b0; + end + + if (res_a1 !== 1'bx) begin + $display("Failed res_a1, expected 1'bx, got %b", res_a1); + passed = 1'b0; + end + + if (res_b1 !== 1'bx) begin + $display("Failed res_b1, expected 1'bx, got %b", res_b1); + passed = 1'b0; + end + + if (res_a2 !== 1'bx) begin + $display("Failed res_a2, expected 1'bx, got %b", res_a2); + passed = 1'b0; + end + + if (res_b2 !== 1'bx) begin + $display("Failed res_b2, expected 1'bx, got %b", res_b2); + passed = 1'b0; + end + + if (res_c3 !== 1'b1) begin + $display("Failed res_c3, expected 1'b1, got %b", res_c3); + passed = 1'b0; + end + + if (res_d3 !== 1'b0) begin + $display("Failed res_d3, expected 1'b0, got %b", res_d3); + passed = 1'b0; + end + + if (res_c4 !== 1'b1) begin + $display("Failed res_c4, expected 1'b1, got %b", res_c4); + passed = 1'b0; + end + + if (res_d4 !== 1'b0) begin + $display("Failed res_d4, expected 1'b0, got %b", res_d4); + passed = 1'b0; + end + + // Check procedural L-value variable bit selects. + + res_ab = 4'bxxxx; + res_ab[s0] = 1'b0; + if (res_ab !== 4'bxxxx) begin + $display("Failed res_ab[s0], expected 4'bxxxx, got %b", res_ab); + passed = 1'b0; + end + + res_ab = 4'bxxxx; + res_ab[s1] = 1'b0; + if (res_ab !== 4'bxxxx) begin + $display("Failed res_ab[s1], expected 4'bxxxx, got %b", res_ab); + passed = 1'b0; + end + + res_ab = 4'bxxxx; + res_ab[s2] = 1'b0; + if (res_ab !== 4'bxxxx) begin + $display("Failed res_ab[s2], expected 4'bxxxx, got %b", res_ab); + passed = 1'b0; + end + + res_cd = 4'bxxxx; + res_cd[s3] = 1'b0; + if (res_cd !== 4'bxxx0) begin + $display("Failed res_cd[s3], expected 4'bxxx0, got %b", res_cd); + passed = 1'b0; + end + + res_cd = 4'bxxxx; + res_cd[s4] = 1'b0; + if (res_cd !== 4'bxxx0) begin + $display("Failed res_cd[s4], expected 4'bxxx0, got %b", res_cd); + passed = 1'b0; + end + + if (passed) $display("Compare tests passed"); + end +endmodule diff --git a/ivtest/ivltests/pr3054101c.v b/ivtest/ivltests/pr3054101c.v new file mode 100644 index 000000000..6b9af2505 --- /dev/null +++ b/ivtest/ivltests/pr3054101c.v @@ -0,0 +1,321 @@ +// Check the various variable indexed up selects (MSB > LSB). +module top; + parameter [4:1] ap = 4'h8; + parameter [4:1] bp = 4'h7; + parameter [0:-3] cp = 4'h8; + parameter [0:-3] dp = 4'h7; + + reg passed; + + wire [4:1] a = 4'h8; + wire [4:1] b = 4'h7; + wire [0:0] s0 = 0; + wire [1:0] s1 = 0; + wire [2:0] s2 = 0; + reg [4:1] ar = 4'h8; + reg [4:1] br = 4'h7; + + wire [0:-3] c = 4'h8; + wire [0:-3] d = 4'h7; + wire [0:0] s3 = 0; + wire [1:0] s4 = 0; + reg [0:-3] cr = 4'h8; + reg [0:-3] dr = 4'h7; + + wire [1:0] res_a0 = a[s0+:2]; + wire [1:0] res_b0 = b[s0+:2]; + wire [1:0] res_a1 = a[s1+:2]; + wire [1:0] res_b1 = b[s1+:2]; + wire [1:0] res_a2 = a[s2+:2]; + wire [1:0] res_b2 = b[s2+:2]; + + wire [1:0] res_c3 = c[s3+:2]; + wire [1:0] res_d3 = d[s3+:2]; + wire [1:0] res_c4 = c[s4+:2]; + wire [1:0] res_d4 = d[s4+:2]; + + reg [4:1] res_ab; + reg [0:-3] res_cd; + + initial begin + #1; + passed = 1'b1; + + // Check procedural R-value variable index up selects of a net. + + $display("a[s0+:2]: %b", a[s0+:2]); + if (a[s0+:2] !== 2'b0x) begin + $display("Failed a[s0+:2], expected 2'b0x, got %b", a[s0+:2]); + passed = 1'b0; + end + + $display("b[s0+:2]: %b", b[s0+:2]); + if (b[s0+:2] !== 2'b1x) begin + $display("Failed b[s0+:2], expected 2'b1x, got %b", b[s0+:2]); + passed = 1'b0; + end + + $display("a[s1+:2]: %b", a[s1+:2]); + if (a[s1+:2] !== 2'b0x) begin + $display("Failed a[s1+:2], expected 2'b0x, got %b", a[s1+:2]); + passed = 1'b0; + end + + $display("b[s1+:2]: %b", b[s1+:2]); + if (b[s1+:2] !== 2'b1x) begin + $display("Failed b[s1+:2], expected 2'b1x, got %b", b[s1+:2]); + passed = 1'b0; + end + + $display("a[s2+:2]: %b", a[s2+:2]); + if (a[s2+:2] !== 2'b0x) begin + $display("Failed a[s2+:2], expected 2'b0x, got %b", a[s2+:2]); + passed = 1'b0; + end + + $display("b[s2+:2]: %b", b[s2+:2]); + if (b[s2+:2] !== 2'b1x) begin + $display("Failed b[s2+:2], expected 2'b1x, got %b", b[s2+:2]); + passed = 1'b0; + end + + $display("c[s3+:2]: %b", c[s3+:2]); + if (c[s3+:2] !== 2'bx1) begin + $display("Failed c[s3+:2], expected 2'bx1, got %b", c[s3+:2]); + passed = 1'b0; + end + + $display("d[s3+:2]: %b", d[s3+:2]); + if (d[s3+:2] !== 2'bx0) begin + $display("Failed d[s3+:2], expected 2'bx0, got %b", d[s3+:2]); + passed = 1'b0; + end + + $display("c[s4+:2]: %b", c[s4+:2]); + if (c[s4+:2] !== 2'bx1) begin + $display("Failed c[s4+:2], expected 2'bx1, got %b", c[s4+:2]); + passed = 1'b0; + end + + $display("d[s4+:2]: %b", d[s4+:2]); + if (d[s4+:2] !== 2'bx0) begin + $display("Failed d[s4+:2], expected 2'bx0, got %b", d[s4+:2]); + passed = 1'b0; + end + + // Check procedural R-value variable index up selects of a parameter. + + $display("ap[s0+:2]: %b", ap[s0+:2]); + if (ap[s0+:2] !== 2'b0x) begin + $display("Failed ap[s0+:2], expected 2'b0x, got %b", ap[s0+:2]); + passed = 1'b0; + end + + $display("bp[s0+:2]: %b", bp[s0+:2]); + if (bp[s0+:2] !== 2'b1x) begin + $display("Failed bp[s0+:2], expected 2'b1x, got %b", bp[s0+:2]); + passed = 1'b0; + end + + $display("ap[s1+:2]: %b", ap[s1+:2]); + if (ap[s1+:2] !== 2'b0x) begin + $display("Failed ap[s1+:2], expected 2'b0x, got %b", ap[s1+:2]); + passed = 1'b0; + end + + $display("bp[s1+:2]: %b", bp[s1+:2]); + if (bp[s1+:2] !== 2'b1x) begin + $display("Failed bp[s1+:2], expected 2'b1x, got %b", bp[s1+:2]); + passed = 1'b0; + end + + $display("ap[s2+:2]: %b", ap[s2+:2]); + if (ap[s2+:2] !== 2'b0x) begin + $display("Failed ap[s2+:2], expected 2'b0x, got %b", ap[s2+:2]); + passed = 1'b0; + end + + $display("bp[s2+:2]: %b", bp[s2+:2]); + if (bp[s2+:2] !== 2'b1x) begin + $display("Failed bp[s2+:2], expected 2'b1x, got %b", bp[s2+:2]); + passed = 1'b0; + end + + $display("cp[s3+:2]: %b", cp[s3+:2]); + if (cp[s3+:2] !== 2'bx1) begin + $display("Failed cp[s3+:2], expected 2'bx1, got %b", cp[s3+:2]); + passed = 1'b0; + end + + $display("dp[s3+:2]: %b", dp[s3+:2]); + if (dp[s3+:2] !== 2'bx0) begin + $display("Failed dp[s3+:2], expected 2'bx0, got %b", dp[s3+:2]); + passed = 1'b0; + end + + $display("cp[s4+:2]: %b", cp[s4+:2]); + if (cp[s4+:2] !== 2'bx1) begin + $display("Failed cp[s4+:2], expected 2'bx1, got %b", cp[s4+:2]); + passed = 1'b0; + end + + $display("dp[s4+:2]: %b", dp[s4+:2]); + if (dp[s4+:2] !== 2'bx0) begin + $display("Failed dp[s4+:2], expected 2'bx0, got %b", dp[s4+:2]); + passed = 1'b0; + end + + // Check procedural R-value variable index up selects of a reg. + + $display("ar[s0+:2]: %b", ar[s0+:2]); + if (ar[s0+:2] !== 2'b0x) begin + $display("Failed ar[s0+:2], expected 2'b0x, got %b", ar[s0+:2]); + passed = 1'b0; + end + + $display("br[s0+:2]: %b", br[s0+:2]); + if (br[s0+:2] !== 2'b1x) begin + $display("Failed br[s0+:2], expected 2'b1x, got %b", br[s0+:2]); + passed = 1'b0; + end + + $display("ar[s1+:2]: %b", ar[s1+:2]); + if (ar[s1+:2] !== 2'b0x) begin + $display("Failed ar[s1+:2], expected 2'b0x, got %b", ar[s1+:2]); + passed = 1'b0; + end + + $display("br[s1+:2]: %b", br[s1+:2]); + if (br[s1+:2] !== 2'b1x) begin + $display("Failed br[s1+:2], expected 2'b1x, got %b", br[s1+:2]); + passed = 1'b0; + end + + $display("ar[s2+:2]: %b", ar[s2+:2]); + if (ar[s2+:2] !== 2'b0x) begin + $display("Failed ar[s2+:2], expected 2'b0x, got %b", ar[s2+:2]); + passed = 1'b0; + end + + $display("br[s2+:2]: %b", br[s2+:2]); + if (br[s2+:2] !== 2'b1x) begin + $display("Failed br[s2+:2], expected 2'b1x, got %b", br[s2+:2]); + passed = 1'b0; + end + + $display("cr[s3+:2]: %b", cr[s3+:2]); + if (cr[s3+:2] !== 2'bx1) begin + $display("Failed cr[s3+:2], expected 2'bx1, got %b", cr[s3+:2]); + passed = 1'b0; + end + + $display("dr[s3+:2]: %b", dr[s3+:2]); + if (dr[s3+:2] !== 2'bx0) begin + $display("Failed dr[s3+:2], expected 2'bx0, got %b", dr[s3+:2]); + passed = 1'b0; + end + + $display("cr[s4+:2]: %b", cr[s4+:2]); + if (cr[s4+:2] !== 2'bx1) begin + $display("Failed cr[s4+:2], expected 2'bx1, got %b", cr[s4+:2]); + passed = 1'b0; + end + + $display("dr[s4+:2]: %b", dr[s4+:2]); + if (dr[s4+:2] !== 2'bx0) begin + $display("Failed dr[s4+:2], expected 2'bx0, got %b", dr[s4+:2]); + passed = 1'b0; + end + + // Check continuous assignment R-value variable index up selects. + + if (res_a0 !== 2'b0x) begin + $display("Failed res_a0, expected 2'b0x, got %b", res_a0); + passed = 1'b0; + end + + if (res_b0 !== 2'b1x) begin + $display("Failed res_b0, expected 2'b1x, got %b", res_b0); + passed = 1'b0; + end + + if (res_a1 !== 2'b0x) begin + $display("Failed res_a1, expected 2'b0x, got %b", res_a1); + passed = 1'b0; + end + + if (res_b1 !== 2'b1x) begin + $display("Failed res_b1, expected 2'b1x, got %b", res_b1); + passed = 1'b0; + end + + if (res_a2 !== 2'b0x) begin + $display("Failed res_a2, expected 2'b0x, got %b", res_a2); + passed = 1'b0; + end + + if (res_b2 !== 2'b1x) begin + $display("Failed res_b2, expected 2'b1x, got %b", res_b2); + passed = 1'b0; + end + + if (res_c3 !== 2'bx1) begin + $display("Failed res_c3, expected 2'bx1, got %b", res_c3); + passed = 1'b0; + end + + if (res_d3 !== 2'bx0) begin + $display("Failed res_d3, expected 2'bx0, got %b", res_d3); + passed = 1'b0; + end + + if (res_c4 !== 2'bx1) begin + $display("Failed res_c4, expected 2'bx1, got %b", res_c4); + passed = 1'b0; + end + + if (res_d4 !== 2'bx0) begin + $display("Failed res_d4, expected 2'bx0, got %b", res_d4); + passed = 1'b0; + end + + // Check procedural L-value variable index up selects. + + res_ab = 4'bxxxx; + res_ab[s0+:2] = 2'b00; + if (res_ab !== 4'bxxx0) begin + $display("Failed res_ab[s0], expected 4'bxxx0, got %b", res_ab); + passed = 1'b0; + end + + res_ab = 4'bxxxx; + res_ab[s1+:2] = 2'b00; + if (res_ab !== 4'bxxx0) begin + $display("Failed res_ab[s1], expected 4'bxxx0, got %b", res_ab); + passed = 1'b0; + end + + res_ab = 4'bxxxx; + res_ab[s2+:2] = 2'b00; + if (res_ab !== 4'bxxx0) begin + $display("Failed res_ab[s2], expected 4'bxxx0, got %b", res_ab); + passed = 1'b0; + end + + res_cd = 4'bxxxx; + res_cd[s3+:2] = 2'b00; + if (res_cd !== 4'b0xxx) begin + $display("Failed res_cd[s3], expected 4'b0xxx, got %b", res_cd); + passed = 1'b0; + end + + res_cd = 4'bxxxx; + res_cd[s4+:2] = 2'b00; + if (res_cd !== 4'b0xxx) begin + $display("Failed res_cd[s4], expected 4'b0xxx, got %b", res_cd); + passed = 1'b0; + end + + if (passed) $display("Compare tests passed"); + end +endmodule diff --git a/ivtest/ivltests/pr3054101d.v b/ivtest/ivltests/pr3054101d.v new file mode 100644 index 000000000..662f4dbb9 --- /dev/null +++ b/ivtest/ivltests/pr3054101d.v @@ -0,0 +1,321 @@ +// Check the various variable indexed up selects (LSB > MSB). +module top; + parameter [-4:-1] ap = 4'he; + parameter [-4:-1] bp = 4'h1; + parameter [1:4] cp = 4'he; + parameter [1:4] dp = 4'h1; + + reg passed; + + wire [-4:-1] a = 4'he; + wire [-4:-1] b = 4'h1; + wire signed [0:0] s0 = -1; + wire signed [1:0] s1 = -1; + wire signed [2:0] s2 = -1; + reg [-4:-1] ar = 4'he; + reg [-4:-1] br = 4'h1; + + wire [1:4] c = 4'he; + wire [1:4] d = 4'h1; + wire [0:0] s3 = 0; + wire [1:0] s4 = 0; + reg [1:4] cr = 4'he; + reg [1:4] dr = 4'h1; + + wire [1:0] res_a0 = a[s0+:2]; + wire [1:0] res_b0 = b[s0+:2]; + wire [1:0] res_a1 = a[s1+:2]; + wire [1:0] res_b1 = b[s1+:2]; + wire [1:0] res_a2 = a[s2+:2]; + wire [1:0] res_b2 = b[s2+:2]; + + wire [1:0] res_c3 = c[s3+:2]; + wire [1:0] res_d3 = d[s3+:2]; + wire [1:0] res_c4 = c[s4+:2]; + wire [1:0] res_d4 = d[s4+:2]; + + reg [-4:-1] res_ab; + reg [1:4] res_cd; + + initial begin + #1; + passed = 1'b1; + + // Check procedural R-value variable index up selects of a net. + + $display("a[s0+:2]: %b", a[s0+:2]); + if (a[s0+:2] !== 2'b0x) begin + $display("Failed a[s0+:2], expected 2'b0x, got %b", a[s0+:2]); + passed = 1'b0; + end + + $display("b[s0+:2]: %b", b[s0+:2]); + if (b[s0+:2] !== 2'b1x) begin + $display("Failed b[s0+:2], expected 2'b1x, got %b", b[s0+:2]); + passed = 1'b0; + end + + $display("a[s1+:2]: %b", a[s1+:2]); + if (a[s1+:2] !== 2'b0x) begin + $display("Failed a[s1+:2], expected 2'b0x, got %b", a[s1+:2]); + passed = 1'b0; + end + + $display("b[s1+:2]: %b", b[s1+:2]); + if (b[s1+:2] !== 2'b1x) begin + $display("Failed b[s1+:2], expected 2'b1x, got %b", b[s1+:2]); + passed = 1'b0; + end + + $display("a[s2+:2]: %b", a[s2+:2]); + if (a[s2+:2] !== 2'b0x) begin + $display("Failed a[s2+:2], expected 2'b0x, got %b", a[s2+:2]); + passed = 1'b0; + end + + $display("b[s2+:2]: %b", b[s2+:2]); + if (b[s2+:2] !== 2'b1x) begin + $display("Failed b[s2+:2], expected 2'b1x, got %b", b[s2+:2]); + passed = 1'b0; + end + + $display("c[s3+:2]: %b", c[s3+:2]); + if (c[s3+:2] !== 2'bx1) begin + $display("Failed c[s3+:2], expected 2'bx1, got %b", c[s3+:2]); + passed = 1'b0; + end + + $display("d[s3+:2]: %b", d[s3+:2]); + if (d[s3+:2] !== 2'bx0) begin + $display("Failed d[s3+:2], expected 2'bx0, got %b", d[s3+:2]); + passed = 1'b0; + end + + $display("c[s4+:2]: %b", c[s4+:2]); + if (c[s4+:2] !== 2'bx1) begin + $display("Failed c[s4+:2], expected 2'bx1, got %b", c[s4+:2]); + passed = 1'b0; + end + + $display("d[s4+:2]: %b", d[s4+:2]); + if (d[s4+:2] !== 2'bx0) begin + $display("Failed d[s4+:2], expected 2'bx0, got %b", d[s4+:2]); + passed = 1'b0; + end + + // Check procedural R-value variable index up selects of a parameter. + + $display("ap[s0+:2]: %b", ap[s0+:2]); + if (ap[s0+:2] !== 2'b0x) begin + $display("Failed ap[s0+:2], expected 2'b0x, got %b", ap[s0+:2]); + passed = 1'b0; + end + + $display("bp[s0+:2]: %b", bp[s0+:2]); + if (bp[s0+:2] !== 2'b1x) begin + $display("Failed bp[s0+:2], expected 2'b1x, got %b", bp[s0+:2]); + passed = 1'b0; + end + + $display("ap[s1+:2]: %b", ap[s1+:2]); + if (ap[s1+:2] !== 2'b0x) begin + $display("Failed ap[s1+:2], expected 2'b0x, got %b", ap[s1+:2]); + passed = 1'b0; + end + + $display("bp[s1+:2]: %b", bp[s1+:2]); + if (bp[s1+:2] !== 2'b1x) begin + $display("Failed bp[s1+:2], expected 2'b1x, got %b", bp[s1+:2]); + passed = 1'b0; + end + + $display("ap[s2+:2]: %b", ap[s2+:2]); + if (ap[s2+:2] !== 2'b0x) begin + $display("Failed ap[s2+:2], expected 2'b0x, got %b", ap[s2+:2]); + passed = 1'b0; + end + + $display("bp[s2+:2]: %b", bp[s2+:2]); + if (bp[s2+:2] !== 2'b1x) begin + $display("Failed bp[s2+:2], expected 2'b1x, got %b", bp[s2+:2]); + passed = 1'b0; + end + + $display("cp[s3+:2]: %b", cp[s3+:2]); + if (cp[s3+:2] !== 2'bx1) begin + $display("Failed cp[s3+:2], expected 2'bx1, got %b", cp[s3+:2]); + passed = 1'b0; + end + + $display("dp[s3+:2]: %b", dp[s3+:2]); + if (dp[s3+:2] !== 2'bx0) begin + $display("Failed dp[s3+:2], expected 2'bx0, got %b", dp[s3+:2]); + passed = 1'b0; + end + + $display("cp[s4+:2]: %b", cp[s4+:2]); + if (cp[s4+:2] !== 2'bx1) begin + $display("Failed cp[s4+:2], expected 2'bx1, got %b", cp[s4+:2]); + passed = 1'b0; + end + + $display("dp[s4+:2]: %b", dp[s4+:2]); + if (dp[s4+:2] !== 2'bx0) begin + $display("Failed dp[s4+:2], expected 2'bx0, got %b", dp[s4+:2]); + passed = 1'b0; + end + + // Check procedural R-value variable index up selects of a reg. + + $display("ar[s0+:2]: %b", ar[s0+:2]); + if (ar[s0+:2] !== 2'b0x) begin + $display("Failed ar[s0+:2], expected 2'b0x, got %b", ar[s0+:2]); + passed = 1'b0; + end + + $display("br[s0+:2]: %b", br[s0+:2]); + if (br[s0+:2] !== 2'b1x) begin + $display("Failed br[s0+:2], expected 2'b1x, got %b", br[s0+:2]); + passed = 1'b0; + end + + $display("ar[s1+:2]: %b", ar[s1+:2]); + if (ar[s1+:2] !== 2'b0x) begin + $display("Failed ar[s1+:2], expected 2'b0x, got %b", ar[s1+:2]); + passed = 1'b0; + end + + $display("br[s1+:2]: %b", br[s1+:2]); + if (br[s1+:2] !== 2'b1x) begin + $display("Failed br[s1+:2], expected 2'b1x, got %b", br[s1+:2]); + passed = 1'b0; + end + + $display("ar[s2+:2]: %b", ar[s2+:2]); + if (ar[s2+:2] !== 2'b0x) begin + $display("Failed ar[s2+:2], expected 2'b0x, got %b", ar[s2+:2]); + passed = 1'b0; + end + + $display("br[s2+:2]: %b", br[s2+:2]); + if (br[s2+:2] !== 2'b1x) begin + $display("Failed br[s2+:2], expected 2'b1x, got %b", br[s2+:2]); + passed = 1'b0; + end + + $display("cr[s3+:2]: %b", cr[s3+:2]); + if (cr[s3+:2] !== 2'bx1) begin + $display("Failed cr[s3+:2], expected 2'bx1, got %b", cr[s3+:2]); + passed = 1'b0; + end + + $display("dr[s3+:2]: %b", dr[s3+:2]); + if (dr[s3+:2] !== 2'bx0) begin + $display("Failed dr[s3+:2], expected 2'bx0, got %b", dr[s3+:2]); + passed = 1'b0; + end + + $display("cr[s4+:2]: %b", cr[s4+:2]); + if (cr[s4+:2] !== 2'bx1) begin + $display("Failed cr[s4+:2], expected 2'bx1, got %b", cr[s4+:2]); + passed = 1'b0; + end + + $display("dr[s4+:2]: %b", dr[s4+:2]); + if (dr[s4+:2] !== 2'bx0) begin + $display("Failed dr[s4+:2], expected 2'bx0, got %b", dr[s4+:2]); + passed = 1'b0; + end + + // Check continuous assignment R-value variable index up selects. + + if (res_a0 !== 2'b0x) begin + $display("Failed res_a0, expected 2'b0x, got %b", res_a0); + passed = 1'b0; + end + + if (res_b0 !== 2'b1x) begin + $display("Failed res_b0, expected 2'b1x, got %b", res_b0); + passed = 1'b0; + end + + if (res_a1 !== 2'b0x) begin + $display("Failed res_a1, expected 2'b0x, got %b", res_a1); + passed = 1'b0; + end + + if (res_b1 !== 2'b1x) begin + $display("Failed res_b1, expected 2'b1x, got %b", res_b1); + passed = 1'b0; + end + + if (res_a2 !== 2'b0x) begin + $display("Failed res_a2, expected 2'b0x, got %b", res_a2); + passed = 1'b0; + end + + if (res_b2 !== 2'b1x) begin + $display("Failed res_b2, expected 2'b1x, got %b", res_b2); + passed = 1'b0; + end + + if (res_c3 !== 2'bx1) begin + $display("Failed res_c3, expected 2'bx1, got %b", res_c3); + passed = 1'b0; + end + + if (res_d3 !== 2'bx0) begin + $display("Failed res_d3, expected 2'bx0, got %b", res_d3); + passed = 1'b0; + end + + if (res_c4 !== 2'bx1) begin + $display("Failed res_c4, expected 2'bx1, got %b", res_c4); + passed = 1'b0; + end + + if (res_d4 !== 2'bx0) begin + $display("Failed res_d4, expected 2'bx0, got %b", res_d4); + passed = 1'b0; + end + + // Check procedural L-value variable index up selects. + + res_ab = 4'bxxxx; + res_ab[s0+:2] = 2'b00; + if (res_ab !== 4'bxxx0) begin + $display("Failed res_ab[s0], expected 4'bxxx0, got %b", res_ab); + passed = 1'b0; + end + + res_ab = 4'bxxxx; + res_ab[s1+:2] = 2'b00; + if (res_ab !== 4'bxxx0) begin + $display("Failed res_ab[s1], expected 4'bxxx0, got %b", res_ab); + passed = 1'b0; + end + + res_ab = 4'bxxxx; + res_ab[s2+:2] = 2'b00; + if (res_ab !== 4'bxxx0) begin + $display("Failed res_ab[s2], expected 4'bxxx0, got %b", res_ab); + passed = 1'b0; + end + + res_cd = 4'bxxxx; + res_cd[s3+:2] = 2'b00; + if (res_cd !== 4'b0xxx) begin + $display("Failed res_cd[s3], expected 4'b0xxx, got %b", res_cd); + passed = 1'b0; + end + + res_cd = 4'bxxxx; + res_cd[s4+:2] = 2'b00; + if (res_cd !== 4'b0xxx) begin + $display("Failed res_cd[s4], expected 4'b0xxx, got %b", res_cd); + passed = 1'b0; + end + + if (passed) $display("Compare tests passed"); + end +endmodule diff --git a/ivtest/ivltests/pr3054101e.v b/ivtest/ivltests/pr3054101e.v new file mode 100644 index 000000000..e50474f7d --- /dev/null +++ b/ivtest/ivltests/pr3054101e.v @@ -0,0 +1,321 @@ +// Check the various variable indexed down selects (MSB > LSB). +module top; + parameter [4:1] ap = 4'h8; + parameter [4:1] bp = 4'h7; + parameter [0:-3] cp = 4'h8; + parameter [0:-3] dp = 4'h7; + + reg passed; + + wire [4:1] a = 4'h8; + wire [4:1] b = 4'h7; + wire [0:0] s0 = 1; + wire [1:0] s1 = 1; + wire [2:0] s2 = 1; + reg [4:1] ar = 4'h8; + reg [4:1] br = 4'h7; + + wire [0:-3] c = 4'h8; + wire [0:-3] d = 4'h7; + wire [0:0] s3 = 1; + wire [1:0] s4 = 1; + reg [0:-3] cr = 4'h8; + reg [0:-3] dr = 4'h7; + + wire [1:0] res_a0 = a[s0-:2]; + wire [1:0] res_b0 = b[s0-:2]; + wire [1:0] res_a1 = a[s1-:2]; + wire [1:0] res_b1 = b[s1-:2]; + wire [1:0] res_a2 = a[s2-:2]; + wire [1:0] res_b2 = b[s2-:2]; + + wire [1:0] res_c3 = c[s3-:2]; + wire [1:0] res_d3 = d[s3-:2]; + wire [1:0] res_c4 = c[s4-:2]; + wire [1:0] res_d4 = d[s4-:2]; + + reg [4:1] res_ab; + reg [0:-3] res_cd; + + initial begin + #1; + passed = 1'b1; + + // Check procedural R-value variable index down selects of a net. + + $display("a[s0-:2]: %b", a[s1-:2]); + if (a[s0-:2] !== 2'b0x) begin + $display("Failed a[s0-:2], expected 2'b0x, got %b", a[s0-:2]); + passed = 1'b0; + end + + $display("b[s0-:2]: %b", b[s1-:2]); + if (b[s0-:2] !== 2'b1x) begin + $display("Failed b[s0-:2], expected 2'b1x, got %b", b[s0-:2]); + passed = 1'b0; + end + + $display("a[s1-:2]: %b", a[s1-:2]); + if (a[s1-:2] !== 2'b0x) begin + $display("Failed a[s1-:2], expected 2'b0x, got %b", a[s1-:2]); + passed = 1'b0; + end + + $display("b[s1-:2]: %b", b[s1-:2]); + if (b[s1-:2] !== 2'b1x) begin + $display("Failed b[s1-:2], expected 2'b1x, got %b", b[s1-:2]); + passed = 1'b0; + end + + $display("a[s2-:2]: %b", a[s2-:2]); + if (a[s2-:2] !== 2'b0x) begin + $display("Failed a[s2-:2], expected 2'b0x, got %b", a[s2-:2]); + passed = 1'b0; + end + + $display("b[s2-:2]: %b", b[s2-:2]); + if (b[s2-:2] !== 2'b1x) begin + $display("Failed b[s2-:2], expected 2'b1x, got %b", b[s2-:2]); + passed = 1'b0; + end + + $display("c[s3-:2]: %b", c[s3-:2]); + if (c[s3-:2] !== 2'bx1) begin + $display("Failed c[s3-:2], expected 2'bx1, got %b", c[s3-:2]); + passed = 1'b0; + end + + $display("d[s3-:2]: %b", d[s3-:2]); + if (d[s3-:2] !== 2'bx0) begin + $display("Failed d[s3-:2], expected 2'bx0, got %b", d[s3-:2]); + passed = 1'b0; + end + + $display("c[s4-:2]: %b", c[s4-:2]); + if (c[s4-:2] !== 2'bx1) begin + $display("Failed c[s4-:2], expected 2'bx1, got %b", c[s4-:2]); + passed = 1'b0; + end + + $display("d[s4-:2]: %b", d[s4-:2]); + if (d[s4-:2] !== 2'bx0) begin + $display("Failed d[s4-:2], expected 2'bx0, got %b", d[s4-:2]); + passed = 1'b0; + end + + // Check procedural R-value variable index down selects of a parameter. + + $display("ap[s0-:2]: %b", ap[s0-:2]); + if (ap[s0-:2] !== 2'b0x) begin + $display("Failed ap[s0-:2], expected 2'b0x, got %b", ap[s0-:2]); + passed = 1'b0; + end + + $display("bp[s0-:2]: %b", bp[s0-:2]); + if (bp[s0-:2] !== 2'b1x) begin + $display("Failed bp[s0-:2], expected 2'b1x, got %b", bp[s0-:2]); + passed = 1'b0; + end + + $display("ap[s1-:2]: %b", ap[s1-:2]); + if (ap[s1-:2] !== 2'b0x) begin + $display("Failed ap[s1-:2], expected 2'b0x, got %b", ap[s1-:2]); + passed = 1'b0; + end + + $display("bp[s1-:2]: %b", bp[s1-:2]); + if (bp[s1-:2] !== 2'b1x) begin + $display("Failed bp[s1-:2], expected 2'b1x, got %b", bp[s1-:2]); + passed = 1'b0; + end + + $display("ap[s2-:2]: %b", ap[s2-:2]); + if (ap[s2-:2] !== 2'b0x) begin + $display("Failed ap[s2-:2], expected 2'b0x, got %b", ap[s2-:2]); + passed = 1'b0; + end + + $display("bp[s2-:2]: %b", bp[s2-:2]); + if (bp[s2-:2] !== 2'b1x) begin + $display("Failed bp[s2-:2], expected 2'b1x, got %b", bp[s2-:2]); + passed = 1'b0; + end + + $display("cp[s3-:2]: %b", cp[s3-:2]); + if (cp[s3-:2] !== 2'bx1) begin + $display("Failed cp[s3-:2], expected 2'bx1, got %b", cp[s3-:2]); + passed = 1'b0; + end + + $display("dp[s3-:2]: %b", dp[s3-:2]); + if (dp[s3-:2] !== 2'bx0) begin + $display("Failed dp[s3-:2], expected 2'bx0, got %b", dp[s3-:2]); + passed = 1'b0; + end + + $display("cp[s4-:2]: %b", cp[s4-:2]); + if (cp[s4-:2] !== 2'bx1) begin + $display("Failed cp[s4-:2], expected 2'bx1, got %b", cp[s4-:2]); + passed = 1'b0; + end + + $display("dp[s4-:2]: %b", dp[s4-:2]); + if (dp[s4-:2] !== 2'bx0) begin + $display("Failed dp[s4-:2], expected 2'bx0, got %b", dp[s4-:2]); + passed = 1'b0; + end + + // Check procedural R-value variable index down selects of a reg. + + $display("ar[s0-:2]: %b", ar[s0-:2]); + if (ar[s0-:2] !== 2'b0x) begin + $display("Failed ar[s0-:2], expected 2'b0x, got %b", ar[s0-:2]); + passed = 1'b0; + end + + $display("br[s0-:2]: %b", br[s0-:2]); + if (br[s0-:2] !== 2'b1x) begin + $display("Failed br[s0-:2], expected 2'b1x, got %b", br[s0-:2]); + passed = 1'b0; + end + + $display("ar[s1-:2]: %b", ar[s1-:2]); + if (ar[s1-:2] !== 2'b0x) begin + $display("Failed ar[s1-:2], expected 2'b0x, got %b", ar[s1-:2]); + passed = 1'b0; + end + + $display("br[s1-:2]: %b", br[s1-:2]); + if (br[s1-:2] !== 2'b1x) begin + $display("Failed br[s1-:2], expected 2'b1x, got %b", br[s1-:2]); + passed = 1'b0; + end + + $display("ar[s2-:2]: %b", ar[s2-:2]); + if (ar[s2-:2] !== 2'b0x) begin + $display("Failed ar[s2-:2], expected 2'b0x, got %b", ar[s2-:2]); + passed = 1'b0; + end + + $display("br[s2-:2]: %b", br[s2-:2]); + if (br[s2-:2] !== 2'b1x) begin + $display("Failed br[s2-:2], expected 2'b1x, got %b", br[s2-:2]); + passed = 1'b0; + end + + $display("cr[s3-:2]: %b", cr[s3-:2]); + if (cr[s3-:2] !== 2'bx1) begin + $display("Failed cr[s3-:2], expected 2'bx1, got %b", cr[s3-:2]); + passed = 1'b0; + end + + $display("dr[s3-:2]: %b", dr[s3-:2]); + if (dr[s3-:2] !== 2'bx0) begin + $display("Failed dr[s3-:2], expected 2'bx0, got %b", dr[s3-:2]); + passed = 1'b0; + end + + $display("cr[s4-:2]: %b", cr[s4-:2]); + if (cr[s4-:2] !== 2'bx1) begin + $display("Failed cr[s4-:2], expected 2'bx1, got %b", cr[s4-:2]); + passed = 1'b0; + end + + $display("dr[s4-:2]: %b", dr[s4-:2]); + if (dr[s4-:2] !== 2'bx0) begin + $display("Failed dr[s4-:2], expected 2'bx0, got %b", dr[s4-:2]); + passed = 1'b0; + end + + // Check continuous assignment R-value variable index down selects. + + if (res_a0 !== 2'b0x) begin + $display("Failed res_a0, expected 2'b0x, got %b", res_a0); + passed = 1'b0; + end + + if (res_b0 !== 2'b1x) begin + $display("Failed res_b0, expected 2'b1x, got %b", res_b0); + passed = 1'b0; + end + + if (res_a1 !== 2'b0x) begin + $display("Failed res_a1, expected 2'b0x, got %b", res_a1); + passed = 1'b0; + end + + if (res_b1 !== 2'b1x) begin + $display("Failed res_b1, expected 2'b1x, got %b", res_b1); + passed = 1'b0; + end + + if (res_a2 !== 2'b0x) begin + $display("Failed res_a2, expected 2'b0x, got %b", res_a2); + passed = 1'b0; + end + + if (res_b2 !== 2'b1x) begin + $display("Failed res_b2, expected 2'b1x, got %b", res_b2); + passed = 1'b0; + end + + if (res_c3 !== 2'bx1) begin + $display("Failed res_c3, expected 2'bx1, got %b", res_c3); + passed = 1'b0; + end + + if (res_d3 !== 2'bx0) begin + $display("Failed res_d3, expected 2'bx0, got %b", res_d3); + passed = 1'b0; + end + + if (res_c4 !== 2'bx1) begin + $display("Failed res_c4, expected 2'bx1, got %b", res_c4); + passed = 1'b0; + end + + if (res_d4 !== 2'bx0) begin + $display("Failed res_d4, expected 2'bx0, got %b", res_d4); + passed = 1'b0; + end + + // Check procedural L-value variable index down selects. + + res_ab = 4'bxxxx; + res_ab[s0-:2] = 2'b00; + if (res_ab !== 4'bxxx0) begin + $display("Failed res_ab[s0], expected 4'bxxx0, got %b", res_ab); + passed = 1'b0; + end + + res_ab = 4'bxxxx; + res_ab[s1-:2] = 2'b00; + if (res_ab !== 4'bxxx0) begin + $display("Failed res_ab[s1], expected 4'bxxx0, got %b", res_ab); + passed = 1'b0; + end + + res_ab = 4'bxxxx; + res_ab[s2-:2] = 2'b00; + if (res_ab !== 4'bxxx0) begin + $display("Failed res_ab[s2], expected 4'bxxx0, got %b", res_ab); + passed = 1'b0; + end + + res_cd = 4'bxxxx; + res_cd[s3-:2] = 2'b00; + if (res_cd !== 4'b0xxx) begin + $display("Failed res_cd[s3], expected 4'b0xxx, got %b", res_cd); + passed = 1'b0; + end + + res_cd = 4'bxxxx; + res_cd[s4-:2] = 2'b00; + if (res_cd !== 4'b0xxx) begin + $display("Failed res_cd[s4], expected 4'b0xxx, got %b", res_cd); + passed = 1'b0; + end + + if (passed) $display("Compare tests passed"); + end +endmodule diff --git a/ivtest/ivltests/pr3054101f.v b/ivtest/ivltests/pr3054101f.v new file mode 100644 index 000000000..b23661103 --- /dev/null +++ b/ivtest/ivltests/pr3054101f.v @@ -0,0 +1,321 @@ +// Check the various variable indexed down selects (LSB > MSB). +module top; + parameter [-4:-1] ap = 4'he; + parameter [-4:-1] bp = 4'h1; + parameter [1:4] cp = 4'he; + parameter [1:4] dp = 4'h1; + + reg passed; + + wire [-4:-1] a = 4'he; + wire [-4:-1] b = 4'h1; + wire [0:0] s0 = 0; + wire [1:0] s1 = 0; + wire [2:0] s2 = 0; + reg [-4:-1] ar = 4'he; + reg [-4:-1] br = 4'h1; + + wire [1:4] c = 4'he; + wire [1:4] d = 4'h1; + wire [0:0] s3 = 1; + wire [1:0] s4 = 1; + reg [1:4] cr = 4'he; + reg [1:4] dr = 4'h1; + + wire [1:0] res_a0 = a[s0-:2]; + wire [1:0] res_b0 = b[s0-:2]; + wire [1:0] res_a1 = a[s1-:2]; + wire [1:0] res_b1 = b[s1-:2]; + wire [1:0] res_a2 = a[s2-:2]; + wire [1:0] res_b2 = b[s2-:2]; + + wire [1:0] res_c3 = c[s3-:2]; + wire [1:0] res_d3 = d[s3-:2]; + wire [1:0] res_c4 = c[s4-:2]; + wire [1:0] res_d4 = d[s4-:2]; + + reg [-4:-1] res_ab; + reg [1:4] res_cd; + + initial begin + #1; + passed = 1'b1; + + // Check procedural R-value variable index down selects of a net. + + $display("a[s0-:2]: %b", a[s1-:2]); + if (a[s0-:2] !== 2'b0x) begin + $display("Failed a[s0-:2], expected 2'b0x, got %b", a[s0-:2]); + passed = 1'b0; + end + + $display("b[s0-:2]: %b", b[s1-:2]); + if (b[s0-:2] !== 2'b1x) begin + $display("Failed b[s0-:2], expected 2'b1x, got %b", b[s0-:2]); + passed = 1'b0; + end + + $display("a[s1-:2]: %b", a[s1-:2]); + if (a[s1-:2] !== 2'b0x) begin + $display("Failed a[s1-:2], expected 2'b0x, got %b", a[s1-:2]); + passed = 1'b0; + end + + $display("b[s1-:2]: %b", b[s1-:2]); + if (b[s1-:2] !== 2'b1x) begin + $display("Failed b[s1-:2], expected 2'b1x, got %b", b[s1-:2]); + passed = 1'b0; + end + + $display("a[s2-:2]: %b", a[s2-:2]); + if (a[s2-:2] !== 2'b0x) begin + $display("Failed a[s2-:2], expected 2'b0x, got %b", a[s2-:2]); + passed = 1'b0; + end + + $display("b[s2-:2]: %b", b[s2-:2]); + if (b[s2-:2] !== 2'b1x) begin + $display("Failed b[s2-:2], expected 2'b1x, got %b", b[s2-:2]); + passed = 1'b0; + end + + $display("c[s3-:2]: %b", c[s3-:2]); + if (c[s3-:2] !== 2'bx1) begin + $display("Failed c[s3-:2], expected 2'bx1, got %b", c[s3-:2]); + passed = 1'b0; + end + + $display("d[s3-:2]: %b", d[s3-:2]); + if (d[s3-:2] !== 2'bx0) begin + $display("Failed d[s3-:2], expected 2'bx0, got %b", d[s3-:2]); + passed = 1'b0; + end + + $display("c[s4-:2]: %b", c[s4-:2]); + if (c[s4-:2] !== 2'bx1) begin + $display("Failed c[s4-:2], expected 2'bx1, got %b", c[s4-:2]); + passed = 1'b0; + end + + $display("d[s4-:2]: %b", d[s4-:2]); + if (d[s4-:2] !== 2'bx0) begin + $display("Failed d[s4-:2], expected 2'bx0, got %b", d[s4-:2]); + passed = 1'b0; + end + + // Check procedural R-value variable index down selects of a parameter. + + $display("ap[s0-:2]: %b", ap[s0-:2]); + if (ap[s0-:2] !== 2'b0x) begin + $display("Failed ap[s0-:2], expected 2'b0x, got %b", ap[s0-:2]); + passed = 1'b0; + end + + $display("bp[s0-:2]: %b", bp[s0-:2]); + if (bp[s0-:2] !== 2'b1x) begin + $display("Failed bp[s0-:2], expected 2'b1x, got %b", bp[s0-:2]); + passed = 1'b0; + end + + $display("ap[s1-:2]: %b", ap[s1-:2]); + if (ap[s1-:2] !== 2'b0x) begin + $display("Failed ap[s1-:2], expected 2'b0x, got %b", ap[s1-:2]); + passed = 1'b0; + end + + $display("bp[s1-:2]: %b", bp[s1-:2]); + if (bp[s1-:2] !== 2'b1x) begin + $display("Failed bp[s1-:2], expected 2'b1x, got %b", bp[s1-:2]); + passed = 1'b0; + end + + $display("ap[s2-:2]: %b", ap[s2-:2]); + if (ap[s2-:2] !== 2'b0x) begin + $display("Failed ap[s2-:2], expected 2'b0x, got %b", ap[s2-:2]); + passed = 1'b0; + end + + $display("bp[s2-:2]: %b", bp[s2-:2]); + if (bp[s2-:2] !== 2'b1x) begin + $display("Failed bp[s2-:2], expected 2'b1x, got %b", bp[s2-:2]); + passed = 1'b0; + end + + $display("cp[s3-:2]: %b", cp[s3-:2]); + if (cp[s3-:2] !== 2'bx1) begin + $display("Failed cp[s3-:2], expected 2'bx1, got %b", cp[s3-:2]); + passed = 1'b0; + end + + $display("dp[s3-:2]: %b", dp[s3-:2]); + if (dp[s3-:2] !== 2'bx0) begin + $display("Failed dp[s3-:2], expected 2'bx0, got %b", dp[s3-:2]); + passed = 1'b0; + end + + $display("cp[s4-:2]: %b", cp[s4-:2]); + if (cp[s4-:2] !== 2'bx1) begin + $display("Failed cp[s4-:2], expected 2'bx1, got %b", cp[s4-:2]); + passed = 1'b0; + end + + $display("dp[s4-:2]: %b", dp[s4-:2]); + if (dp[s4-:2] !== 2'bx0) begin + $display("Failed dp[s4-:2], expected 2'bx0, got %b", dp[s4-:2]); + passed = 1'b0; + end + + // Check procedural R-value variable index down selects of a reg. + + $display("ar[s0-:2]: %b", ar[s0-:2]); + if (ar[s0-:2] !== 2'b0x) begin + $display("Failed ar[s0-:2], expected 2'b0x, got %b", ar[s0-:2]); + passed = 1'b0; + end + + $display("br[s0-:2]: %b", br[s0-:2]); + if (br[s0-:2] !== 2'b1x) begin + $display("Failed br[s0-:2], expected 2'b1x, got %b", br[s0-:2]); + passed = 1'b0; + end + + $display("ar[s1-:2]: %b", ar[s1-:2]); + if (ar[s1-:2] !== 2'b0x) begin + $display("Failed ar[s1-:2], expected 2'b0x, got %b", ar[s1-:2]); + passed = 1'b0; + end + + $display("br[s1-:2]: %b", br[s1-:2]); + if (br[s1-:2] !== 2'b1x) begin + $display("Failed br[s1-:2], expected 2'b1x, got %b", br[s1-:2]); + passed = 1'b0; + end + + $display("ar[s2-:2]: %b", ar[s2-:2]); + if (ar[s2-:2] !== 2'b0x) begin + $display("Failed ar[s2-:2], expected 2'b0x, got %b", ar[s2-:2]); + passed = 1'b0; + end + + $display("br[s2-:2]: %b", br[s2-:2]); + if (br[s2-:2] !== 2'b1x) begin + $display("Failed br[s2-:2], expected 2'b1x, got %b", br[s2-:2]); + passed = 1'b0; + end + + $display("cr[s3-:2]: %b", cr[s3-:2]); + if (cr[s3-:2] !== 2'bx1) begin + $display("Failed cr[s3-:2], expected 2'bx1, got %b", cr[s3-:2]); + passed = 1'b0; + end + + $display("dr[s3-:2]: %b", dr[s3-:2]); + if (dr[s3-:2] !== 2'bx0) begin + $display("Failed dr[s3-:2], expected 2'bx0, got %b", dr[s3-:2]); + passed = 1'b0; + end + + $display("cr[s4-:2]: %b", cr[s4-:2]); + if (cr[s4-:2] !== 2'bx1) begin + $display("Failed cr[s4-:2], expected 2'bx1, got %b", cr[s4-:2]); + passed = 1'b0; + end + + $display("dr[s4-:2]: %b", dr[s4-:2]); + if (dr[s4-:2] !== 2'bx0) begin + $display("Failed dr[s4-:2], expected 2'bx0, got %b", dr[s4-:2]); + passed = 1'b0; + end + + // Check continuous assignment R-value variable index down selects. + + if (res_a0 !== 2'b0x) begin + $display("Failed res_a0, expected 2'b0x, got %b", res_a0); + passed = 1'b0; + end + + if (res_b0 !== 2'b1x) begin + $display("Failed res_b0, expected 2'b1x, got %b", res_b0); + passed = 1'b0; + end + + if (res_a1 !== 2'b0x) begin + $display("Failed res_a1, expected 2'b0x, got %b", res_a1); + passed = 1'b0; + end + + if (res_b1 !== 2'b1x) begin + $display("Failed res_b1, expected 2'b1x, got %b", res_b1); + passed = 1'b0; + end + + if (res_a2 !== 2'b0x) begin + $display("Failed res_a2, expected 2'b0x, got %b", res_a2); + passed = 1'b0; + end + + if (res_b2 !== 2'b1x) begin + $display("Failed res_b2, expected 2'b1x, got %b", res_b2); + passed = 1'b0; + end + + if (res_c3 !== 2'bx1) begin + $display("Failed res_c3, expected 2'bx1, got %b", res_c3); + passed = 1'b0; + end + + if (res_d3 !== 2'bx0) begin + $display("Failed res_d3, expected 2'bx0, got %b", res_d3); + passed = 1'b0; + end + + if (res_c4 !== 2'bx1) begin + $display("Failed res_c4, expected 2'bx1, got %b", res_c4); + passed = 1'b0; + end + + if (res_d4 !== 2'bx0) begin + $display("Failed res_d4, expected 2'bx0, got %b", res_d4); + passed = 1'b0; + end + + // Check procedural L-value variable index down selects. + + res_ab = 4'bxxxx; + res_ab[s0-:2] = 2'b00; + if (res_ab !== 4'bxxx0) begin + $display("Failed res_ab[s0], expected 4'bxxx0, got %b", res_ab); + passed = 1'b0; + end + + res_ab = 4'bxxxx; + res_ab[s1-:2] = 2'b00; + if (res_ab !== 4'bxxx0) begin + $display("Failed res_ab[s1], expected 4'bxxx0, got %b", res_ab); + passed = 1'b0; + end + + res_ab = 4'bxxxx; + res_ab[s2-:2] = 2'b00; + if (res_ab !== 4'bxxx0) begin + $display("Failed res_ab[s2], expected 4'bxxx0, got %b", res_ab); + passed = 1'b0; + end + + res_cd = 4'bxxxx; + res_cd[s3-:2] = 2'b00; + if (res_cd !== 4'b0xxx) begin + $display("Failed res_cd[s3], expected 4'b0xxx, got %b", res_cd); + passed = 1'b0; + end + + res_cd = 4'bxxxx; + res_cd[s4-:2] = 2'b00; + if (res_cd !== 4'b0xxx) begin + $display("Failed res_cd[s4], expected 4'b0xxx, got %b", res_cd); + passed = 1'b0; + end + + if (passed) $display("Compare tests passed"); + end +endmodule diff --git a/ivtest/ivltests/pr3054101g.v b/ivtest/ivltests/pr3054101g.v new file mode 100644 index 000000000..75ee041c8 --- /dev/null +++ b/ivtest/ivltests/pr3054101g.v @@ -0,0 +1,255 @@ +// Check the various variable array selects (small to large). +module top; + reg passed; + + wire [1:0] a [1:4]; + wire [0:0] s0 = 0; + wire [1:0] s1 = 0; + wire [2:0] s2 = 0; + reg [1:0] ar [1:4]; + + wire [1:0] c [-3:0]; + wire [0:0] s3 = 0; + wire [1:0] s4 = 0; + reg [1:0] cr [-3:0]; + + wire [1:0] res_a0 = a[s0]; + wire [1:0] res_a1 = a[s1]; + wire [1:0] res_a2 = a[s2]; + + wire [1:0] res_c3 = c[s3]; + wire [1:0] res_c4 = c[s4]; + + reg res_a [1:4]; + reg res_c [-3:0]; + + assign a[1] = 2'd0; + assign a[2] = 2'b1; + assign a[3] = 2'd2; + assign a[4] = 2'd3; + + assign c[-3] = 2'd0; + assign c[-2] = 2'b1; + assign c[-1] = 2'd2; + assign c[0] = 2'd3; + + initial begin + #1; + passed = 1'b1; + + ar[1] = 2'd0; + ar[2] = 2'b1; + ar[3] = 2'd2; + ar[4] = 2'd3; + + cr[-3] = 2'd0; + cr[-2] = 2'b1; + cr[-1] = 2'd2; + cr[0] = 2'd3; + + // Check procedural R-value variable bit selects of a net. + + $display("a[s0]: %b", a[s0]); + if (a[s0] !== 2'bxx) begin + $display("Failed a[s0], expected 2'bxx, got %b", a[s0]); + passed = 1'b0; + end + + $display("a[s1]: %b", a[s1]); + if (a[s1] !== 2'bxx) begin + $display("Failed a[s1], expected 2'bxx, got %b", a[s1]); + passed = 1'b0; + end + + $display("a[s2]: %b", a[s2]); + if (a[s2] !== 2'bxx) begin + $display("Failed a[s2], expected 2'bxx, got %b", a[s2]); + passed = 1'b0; + end + + $display("c[s3]: %b", c[s3]); + if (c[s3] !== 2'b11) begin + $display("Failed c[s3], expected 2'b11, got %b", c[s3]); + passed = 1'b0; + end + + $display("c[s4]: %b", c[s4]); + if (c[s4] !== 2'b11) begin + $display("Failed c[s4], expected 2'b11, got %b", c[s4]); + passed = 1'b0; + end + + // Check procedural R-value variable bit selects of a reg. + + $display("ar[s0]: %b", ar[s0]); + if (ar[s0] !== 2'bxx) begin + $display("Failed ar[s0], expected 2'bxx, got %b", ar[s0]); + passed = 1'b0; + end + + $display("ar[s1]: %b", ar[s1]); + if (ar[s1] !== 2'bxx) begin + $display("Failed ar[s1], expected 2'bxx, got %b", ar[s1]); + passed = 1'b0; + end + + $display("ar[s2]: %b", ar[s2]); + if (ar[s2] !== 2'bxx) begin + $display("Failed ar[s2], expected 2'bxx, got %b", ar[s2]); + passed = 1'b0; + end + + $display("cr[s3]: %b", cr[s3]); + if (cr[s3] !== 2'b11) begin + $display("Failed cr[s3], expected 2'b11, got %b", cr[s3]); + passed = 1'b0; + end + + $display("cr[s4]: %b", cr[s4]); + if (cr[s4] !== 2'b11) begin + $display("Failed cr[s4], expected 2'b11, got %b", cr[s4]); + passed = 1'b0; + end + + // Check continuous assignment R-value variable bit selects. + + if (res_a0 !== 2'bxx) begin + $display("Failed res_a0, expected 2'bxx, got %b", res_a0); + passed = 1'b0; + end + + if (res_a1 !== 2'bxx) begin + $display("Failed res_a1, expected 2'bxx, got %b", res_a1); + passed = 1'b0; + end + + if (res_a2 !== 2'bxx) begin + $display("Failed res_a2, expected 2'bxx, got %b", res_a2); + passed = 1'b0; + end + + if (res_c3 !== 2'b11) begin + $display("Failed res_c3, expected 2'b11, got %b", res_c3); + passed = 1'b0; + end + + if (res_c4 !== 2'b11) begin + $display("Failed res_c4, expected 2'b11, got %b", res_c4); + passed = 1'b0; + end + + // Check procedural L-value variable bit selects. + + res_a[1] = 1'bx; + res_a[2] = 1'bx; + res_a[3] = 1'bx; + res_a[4] = 1'bx; + res_a[s0] = 1'b0; + if (res_a[1] !== 1'bx) begin + $display("Failed res_a[s0], expected 1'bx for [1], got %b", res_a[1]); + passed = 1'b0; + end + if (res_a[2] !== 1'bx) begin + $display("Failed res_a[s0], expected 1'bx for [2], got %b", res_a[2]); + passed = 1'b0; + end + if (res_a[3] !== 1'bx) begin + $display("Failed res_a[s0], expected 1'bx for [3], got %b", res_a[3]); + passed = 1'b0; + end + if (res_a[4] !== 1'bx) begin + $display("Failed res_a[s0], expected 1'bx for [4], got %b", res_a[4]); + passed = 1'b0; + end + + res_a[1] = 1'bx; + res_a[2] = 1'bx; + res_a[3] = 1'bx; + res_a[4] = 1'bx; + res_a[s1] = 1'b0; + if (res_a[1] !== 1'bx) begin + $display("Failed res_a[s1], expected 1'bx for [1], got %b", res_a[1]); + passed = 1'b0; + end + if (res_a[2] !== 1'bx) begin + $display("Failed res_a[s1], expected 1'bx for [2], got %b", res_a[2]); + passed = 1'b0; + end + if (res_a[3] !== 1'bx) begin + $display("Failed res_a[s1], expected 1'bx for [3], got %b", res_a[3]); + passed = 1'b0; + end + if (res_a[4] !== 1'bx) begin + $display("Failed res_a[s1], expected 1'bx for [4], got %b", res_a[4]); + passed = 1'b0; + end + + res_a[1] = 1'bx; + res_a[2] = 1'bx; + res_a[3] = 1'bx; + res_a[4] = 1'bx; + res_a[s2] = 1'b0; + if (res_a[1] !== 1'bx) begin + $display("Failed res_a[s2], expected 1'bx for [1], got %b", res_a[1]); + passed = 1'b0; + end + if (res_a[2] !== 1'bx) begin + $display("Failed res_a[s2], expected 1'bx for [2], got %b", res_a[2]); + passed = 1'b0; + end + if (res_a[3] !== 1'bx) begin + $display("Failed res_a[s2], expected 1'bx for [3], got %b", res_a[3]); + passed = 1'b0; + end + if (res_a[4] !== 1'bx) begin + $display("Failed res_a[s2], expected 1'bx for [4], got %b", res_a[4]); + passed = 1'b0; + end + + res_c[-3] = 1'bx; + res_c[-2] = 1'bx; + res_c[-1] = 1'bx; + res_c[0] = 1'bx; + res_c[s3] = 1'b0; + if (res_c[-3] !== 1'bx) begin + $display("Failed res_c[s3], expected 1'bx for [-3], got %b", res_c[-3]); + passed = 1'b0; + end + if (res_c[-2] !== 1'bx) begin + $display("Failed res_c[s3], expected 1'bx for [-2], got %b", res_c[-2]); + passed = 1'b0; + end + if (res_c[-1] !== 1'bx) begin + $display("Failed res_c[s3], expected 1'bx for [-1], got %b", res_c[-1]); + passed = 1'b0; + end + if (res_c[0] !== 1'b0) begin + $display("Failed res_c[s3], expected 1'b0 for [0], got %b", res_c[0]); + passed = 1'b0; + end + + res_c[-3] = 1'bx; + res_c[-2] = 1'bx; + res_c[-1] = 1'bx; + res_c[0] = 1'bx; + res_c[s4] = 1'b0; + if (res_c[-3] !== 1'bx) begin + $display("Failed res_c[s4], expected 1'bx for [-3], got %b", res_c[-3]); + passed = 1'b0; + end + if (res_c[-2] !== 1'bx) begin + $display("Failed res_c[s4], expected 1'bx for [-2], got %b", res_c[-2]); + passed = 1'b0; + end + if (res_c[-1] !== 1'bx) begin + $display("Failed res_c[s4], expected 1'bx for [-1], got %b", res_c[-1]); + passed = 1'b0; + end + if (res_c[0] !== 1'b0) begin + $display("Failed res_c[s4], expected 1'b0 for [0], got %b", res_c[0]); + passed = 1'b0; + end + + if (passed) $display("Compare tests passed"); + end +endmodule diff --git a/ivtest/ivltests/pr3054101h.v b/ivtest/ivltests/pr3054101h.v new file mode 100644 index 000000000..f37a4b7cc --- /dev/null +++ b/ivtest/ivltests/pr3054101h.v @@ -0,0 +1,255 @@ +// Check the various variable array selects (large to small). +module top; + reg passed; + + wire [1:0] a [4:1]; + wire [0:0] s0 = 0; + wire [1:0] s1 = 0; + wire [2:0] s2 = 0; + reg [1:0] ar [4:1]; + + wire [1:0] c [0:-3]; + wire [0:0] s3 = 0; + wire [1:0] s4 = 0; + reg [1:0] cr [0:-3]; + + wire [1:0] res_a0 = a[s0]; + wire [1:0] res_a1 = a[s1]; + wire [1:0] res_a2 = a[s2]; + + wire [1:0] res_c3 = c[s3]; + wire [1:0] res_c4 = c[s4]; + + reg res_a [4:1]; + reg res_c [0:-3]; + + assign a[1] = 2'd0; + assign a[2] = 2'b1; + assign a[3] = 2'd2; + assign a[4] = 2'd3; + + assign c[-3] = 2'd0; + assign c[-2] = 2'b1; + assign c[-1] = 2'd2; + assign c[0] = 2'd3; + + initial begin + #1; + passed = 1'b1; + + ar[1] = 2'd0; + ar[2] = 2'b1; + ar[3] = 2'd2; + ar[4] = 2'd3; + + cr[-3] = 2'd0; + cr[-2] = 2'b1; + cr[-1] = 2'd2; + cr[0] = 2'd3; + + // Check procedural R-value variable bit selects of a net. + + $display("a[s0]: %b", a[s0]); + if (a[s0] !== 2'bxx) begin + $display("Failed a[s0], expected 2'bxx, got %b", a[s0]); + passed = 1'b0; + end + + $display("a[s1]: %b", a[s1]); + if (a[s1] !== 2'bxx) begin + $display("Failed a[s1], expected 2'bxx, got %b", a[s1]); + passed = 1'b0; + end + + $display("a[s2]: %b", a[s2]); + if (a[s2] !== 2'bxx) begin + $display("Failed a[s2], expected 2'bxx, got %b", a[s2]); + passed = 1'b0; + end + + $display("c[s3]: %b", c[s3]); + if (c[s3] !== 2'b11) begin + $display("Failed c[s3], expected 2'b11, got %b", c[s3]); + passed = 1'b0; + end + + $display("c[s4]: %b", c[s4]); + if (c[s4] !== 2'b11) begin + $display("Failed c[s4], expected 2'b11, got %b", c[s4]); + passed = 1'b0; + end + + // Check procedural R-value variable bit selects of a reg. + + $display("ar[s0]: %b", ar[s0]); + if (ar[s0] !== 2'bxx) begin + $display("Failed ar[s0], expected 2'bxx, got %b", ar[s0]); + passed = 1'b0; + end + + $display("ar[s1]: %b", ar[s1]); + if (ar[s1] !== 2'bxx) begin + $display("Failed ar[s1], expected 2'bxx, got %b", ar[s1]); + passed = 1'b0; + end + + $display("ar[s2]: %b", ar[s2]); + if (ar[s2] !== 2'bxx) begin + $display("Failed ar[s2], expected 2'bxx, got %b", ar[s2]); + passed = 1'b0; + end + + $display("cr[s3]: %b", cr[s3]); + if (cr[s3] !== 2'b11) begin + $display("Failed cr[s3], expected 2'b11, got %b", cr[s3]); + passed = 1'b0; + end + + $display("cr[s4]: %b", cr[s4]); + if (cr[s4] !== 2'b11) begin + $display("Failed cr[s4], expected 2'b11, got %b", cr[s4]); + passed = 1'b0; + end + + // Check continuous assignment R-value variable bit selects. + + if (res_a0 !== 2'bxx) begin + $display("Failed res_a0, expected 2'bxx, got %b", res_a0); + passed = 1'b0; + end + + if (res_a1 !== 2'bxx) begin + $display("Failed res_a1, expected 2'bxx, got %b", res_a1); + passed = 1'b0; + end + + if (res_a2 !== 2'bxx) begin + $display("Failed res_a2, expected 2'bxx, got %b", res_a2); + passed = 1'b0; + end + + if (res_c3 !== 2'b11) begin + $display("Failed res_c3, expected 2'b11, got %b", res_c3); + passed = 1'b0; + end + + if (res_c4 !== 2'b11) begin + $display("Failed res_c4, expected 2'b11, got %b", res_c4); + passed = 1'b0; + end + + // Check procedural L-value variable bit selects. + + res_a[1] = 1'bx; + res_a[2] = 1'bx; + res_a[3] = 1'bx; + res_a[4] = 1'bx; + res_a[s0] = 1'b0; + if (res_a[1] !== 1'bx) begin + $display("Failed res_a[s0], expected 1'bx for [1], got %b", res_a[1]); + passed = 1'b0; + end + if (res_a[2] !== 1'bx) begin + $display("Failed res_a[s0], expected 1'bx for [2], got %b", res_a[2]); + passed = 1'b0; + end + if (res_a[3] !== 1'bx) begin + $display("Failed res_a[s0], expected 1'bx for [3], got %b", res_a[3]); + passed = 1'b0; + end + if (res_a[4] !== 1'bx) begin + $display("Failed res_a[s0], expected 1'bx for [4], got %b", res_a[4]); + passed = 1'b0; + end + + res_a[1] = 1'bx; + res_a[2] = 1'bx; + res_a[3] = 1'bx; + res_a[4] = 1'bx; + res_a[s1] = 1'b0; + if (res_a[1] !== 1'bx) begin + $display("Failed res_a[s1], expected 1'bx for [1], got %b", res_a[1]); + passed = 1'b0; + end + if (res_a[2] !== 1'bx) begin + $display("Failed res_a[s1], expected 1'bx for [2], got %b", res_a[2]); + passed = 1'b0; + end + if (res_a[3] !== 1'bx) begin + $display("Failed res_a[s1], expected 1'bx for [3], got %b", res_a[3]); + passed = 1'b0; + end + if (res_a[4] !== 1'bx) begin + $display("Failed res_a[s1], expected 1'bx for [4], got %b", res_a[4]); + passed = 1'b0; + end + + res_a[1] = 1'bx; + res_a[2] = 1'bx; + res_a[3] = 1'bx; + res_a[4] = 1'bx; + res_a[s2] = 1'b0; + if (res_a[1] !== 1'bx) begin + $display("Failed res_a[s2], expected 1'bx for [1], got %b", res_a[1]); + passed = 1'b0; + end + if (res_a[2] !== 1'bx) begin + $display("Failed res_a[s2], expected 1'bx for [2], got %b", res_a[2]); + passed = 1'b0; + end + if (res_a[3] !== 1'bx) begin + $display("Failed res_a[s2], expected 1'bx for [3], got %b", res_a[3]); + passed = 1'b0; + end + if (res_a[4] !== 1'bx) begin + $display("Failed res_a[s2], expected 1'bx for [4], got %b", res_a[4]); + passed = 1'b0; + end + + res_c[-3] = 1'bx; + res_c[-2] = 1'bx; + res_c[-1] = 1'bx; + res_c[0] = 1'bx; + res_c[s3] = 1'b0; + if (res_c[-3] !== 1'bx) begin + $display("Failed res_c[s3], expected 1'bx for [-3], got %b", res_c[-3]); + passed = 1'b0; + end + if (res_c[-2] !== 1'bx) begin + $display("Failed res_c[s3], expected 1'bx for [-2], got %b", res_c[-2]); + passed = 1'b0; + end + if (res_c[-1] !== 1'bx) begin + $display("Failed res_c[s3], expected 1'bx for [-1], got %b", res_c[-1]); + passed = 1'b0; + end + if (res_c[0] !== 1'b0) begin + $display("Failed res_c[s3], expected 1'b0 for [0], got %b", res_c[0]); + passed = 1'b0; + end + + res_c[-3] = 1'bx; + res_c[-2] = 1'bx; + res_c[-1] = 1'bx; + res_c[0] = 1'bx; + res_c[s4] = 1'b0; + if (res_c[-3] !== 1'bx) begin + $display("Failed res_c[s4], expected 1'bx for [-3], got %b", res_c[-3]); + passed = 1'b0; + end + if (res_c[-2] !== 1'bx) begin + $display("Failed res_c[s4], expected 1'bx for [-2], got %b", res_c[-2]); + passed = 1'b0; + end + if (res_c[-1] !== 1'bx) begin + $display("Failed res_c[s4], expected 1'bx for [-1], got %b", res_c[-1]); + passed = 1'b0; + end + if (res_c[0] !== 1'b0) begin + $display("Failed res_c[s4], expected 1'b0 for [0], got %b", res_c[0]); + passed = 1'b0; + end + + if (passed) $display("Compare tests passed"); + end +endmodule diff --git a/ivtest/ivltests/pr3061015a.v b/ivtest/ivltests/pr3061015a.v new file mode 100644 index 000000000..4fcd1f3ed --- /dev/null +++ b/ivtest/ivltests/pr3061015a.v @@ -0,0 +1,6 @@ +module top; + // This should be a compilation error. + parameter PARAMB = PARAMB + 6; + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/pr3061015b.v b/ivtest/ivltests/pr3061015b.v new file mode 100644 index 000000000..333e33fe4 --- /dev/null +++ b/ivtest/ivltests/pr3061015b.v @@ -0,0 +1,7 @@ +module top; + // This should be a compilation error. + parameter PARAMB = PARAMA; + parameter PARAMA = PARAMB; + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/pr3061015c.v b/ivtest/ivltests/pr3061015c.v new file mode 100644 index 000000000..0cd76eca3 --- /dev/null +++ b/ivtest/ivltests/pr3061015c.v @@ -0,0 +1,6 @@ +module top; + // This should be a compilation error. + parameter real PARAMB = PARAMB + 1.0; + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/pr3064375.v b/ivtest/ivltests/pr3064375.v new file mode 100644 index 000000000..472690db7 --- /dev/null +++ b/ivtest/ivltests/pr3064375.v @@ -0,0 +1,43 @@ +module pr3064375; + +reg CLK; +reg RST; + +reg Reg1; +reg Reg2; + +initial begin + CLK = 0; + forever begin + #5 CLK = 1; + #5 CLK = 0; + end +end + +initial begin + RST = 1; + #20; + RST = 0; + #101; + $finish(0); +end + +always @(posedge CLK or posedge RST) begin + if (RST) + Reg1 <= 0; + else + Reg1 <= !Reg1; +end + +always @(negedge CLK or posedge RST) begin + if (RST) + Reg2 <= 0; + else + Reg2 <= Reg1; +end + +initial begin + $monitor("CLK %b RST %b Reg1 %b Reg2 %b", CLK, RST, Reg1, Reg2); +end + +endmodule diff --git a/ivtest/ivltests/pr3064511.v b/ivtest/ivltests/pr3064511.v new file mode 100644 index 000000000..87c1007d6 --- /dev/null +++ b/ivtest/ivltests/pr3064511.v @@ -0,0 +1,28 @@ +module top; + parameter param = -1; + + reg passed; + wire [3:0] val = 11; + wire [3:0] res = val + param; + + reg [3:0] rgval = 11; + reg [3:0] rgres; + + initial begin + passed = 1'b1; + #1; + + if (res !== 10) begin + $display("FAILED wire result, expected 10, got %d", res); + passed = 1'b0; + end + + rgres = rgval + param; + if (rgres !== 10) begin + $display("FAILED reg result, expected 10, got %d", rgres); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr307.v b/ivtest/ivltests/pr307.v new file mode 100644 index 000000000..0667d20f5 --- /dev/null +++ b/ivtest/ivltests/pr307.v @@ -0,0 +1,17 @@ +// (c) 2001 Kenji KISE ivl-bugs PR#307 + +module top; + reg [63:0] in1,in2; + reg [63:0] out; + + initial begin + in1 = 64'hffffffffffffffff; + in2 = 64'hfffffffffffffff7; + out = in1 + in2; + $display("%h + %h = %h", in1,in2,out); + if (out === 64'hfffffffffffffff6) + $display("PASSED"); + else + $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/pr3077640.v b/ivtest/ivltests/pr3077640.v new file mode 100644 index 000000000..d188b2192 --- /dev/null +++ b/ivtest/ivltests/pr3077640.v @@ -0,0 +1,30 @@ +module top; + reg pass; + reg [7:0] val; + reg signed [7:0] sval; + + initial begin + pass = 1'b1; + + // An unsized number has an implicit width of integer width. + val = $unsigned(-4); + if (val !== 8'hfc) begin + $display("Failed unsigned, expected 8'hfc, got %h", val); + pass = 1'b0; + end + + val = $unsigned(-4'sd4); + if (val !== 8'h0c) begin + $display("Failed sized unsigned, expected 8'h0c, got %h", val); + pass = 1'b0; + end + + sval = $signed(4'hc); + if (sval !== -4) begin + $display("Failed signed, expected -4, got %d", sval); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3078759.v b/ivtest/ivltests/pr3078759.v new file mode 100644 index 000000000..458d047da --- /dev/null +++ b/ivtest/ivltests/pr3078759.v @@ -0,0 +1,6 @@ +module top; + specify + specparam s_int = -1; + specparam s_real = -1.0; + endspecify +endmodule diff --git a/ivtest/ivltests/pr307a.v b/ivtest/ivltests/pr307a.v new file mode 100644 index 000000000..965cfb230 --- /dev/null +++ b/ivtest/ivltests/pr307a.v @@ -0,0 +1,79 @@ +// ivl-bugs PR#307 + +module top; + reg [127:0] in1; + reg [127:0] in2; + wire [128:0] out1; + reg [128:0] out2; + + assign out1 = in1 + in2; + + + task r; + integer errors; + begin + out2 = in1 + in2; + $display("\n %h\n+ %h", in1,in2); + $display("= %h", out1); + $display("= %h", out2); + if (out1 != out2) + begin + $display("MISMATCH"); + errors = errors + 1; + end + end + endtask + + initial begin + r.errors = 0; + + in1 = 128'hffffffffffffffffffffffffffffffff; + in2 = 128'hfffffffffffffffffffffffffffffff7; + r; + + in1 = 128'hffffffffffffffffffffffffffffffff; + in2 = 128'h00000000000000000000000000000001; + r; + + in1 = 128'h00000000000000000000000000000001; + in2 = 128'hffffffffffffffffffffffffffffffff; + r; + + in1 = 128'h00000000000000000000000000000000; + in2 = 128'hffffffffffffffffffffffffffffffff; + r; + + in1 = 128'hffffffffffffffffffffffffffffffff; + in2 = 128'hffffffffffffffffffffffffffffffff; + r; + + in1 = 128'h00000000000000000000000000000000; + in2 = 128'h00000000000000000000000000000000; + r; + + in1 = 128'h80000000000000000000000000000000; + in2 = 128'h80000000000000000000000000000000; + r; + + in1 = 128'h08000000000000000000000000000000; + in2 = 128'h08000000000000000000000000000000; + r; + + in1 = 128'h00000000000000008000000000000000; + in2 = 128'h00000000000000008000000000000000; + r; + + in1 = 128'h55555555555555555555555555555555; + in2 = 128'h55555555555555555555555555555555; + r; + + in1 = 128'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa; + in2 = 128'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa; + r; + + if (r.errors) + $display("FAILED: %d errors", r.errors); + else + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3098439.v b/ivtest/ivltests/pr3098439.v new file mode 100644 index 000000000..2b3078ff0 --- /dev/null +++ b/ivtest/ivltests/pr3098439.v @@ -0,0 +1,107 @@ +module test; + reg pass; + reg [8*40:1] str; + integer s; + reg [31:0] su; + integer res; + + initial begin + pass = 1'b1; + s = 2000; + su = 2000; + + res = s + (1 << 3) - 1; + if (res !== 2007) begin + $display("FAILED first term << (s), expected 2007, got %d", res); + pass = 1'b0; + end + res = su + (1 << 3) - 1; + if (res !== 2007) begin + $display("FAILED first term << (su), expected 2007, got %d", res); + pass = 1'b0; + end + + res = s + (16 >> 1) - 1; + if (res !== 2007) begin + $display("FAILED first term >> (s), expected 2007, got %d", res); + pass = 1'b0; + end + res = su + (16 >> 1) - 1; + if (res !== 2007) begin + $display("FAILED first term >> (su), expected 2007, got %d", res); + pass = 1'b0; + end + + res = (s + (1 << 3) - 1) * 16000; + if (res !== 32112000) begin + $display("FAILED second term << (s), expected 32112000, got %d", res); + pass = 1'b0; + end + res = (su + (1 << 3) - 1) * 16000; + if (res !== 32112000) begin + $display("FAILED second term << (su), expected 32112000, got %d", res); + pass = 1'b0; + end + + res = (s + (16 >> 1) - 1) * 16000; + if (res !== 32112000) begin + $display("FAILED second term >> (s), expected 32112000, got %d", res); + pass = 1'b0; + end + res = (su + (16 >> 1) - 1) * 16000; + if (res !== 32112000) begin + $display("FAILED second term >> (su), expected 32112000, got %d", res); + pass = 1'b0; + end + + $sformat(str, "%0d", s + (1 << 3) - 1); + if (str[8*4:1] !== "2007" || str[8*40:8*4+1] !== 0) begin + $display("FAILED first string << (s), expected \"2007\", got %s", str); + pass = 1'b0; + end + $sformat(str, "%0d", su + (1 << 3) - 1); + if (str[8*4:1] !== "2007" || str[8*40:8*4+1] !== 0) begin + $display("FAILED first string << (su), expected \"2007\", got %s", str); + pass = 1'b0; + end + + $sformat(str, "%0d", s + (16 >> 1) - 1); + if (str[8*4:1] !== "2007" || str[8*40:8*4+1] !== 0) begin + $display("FAILED first string >> (s), expected \"2007\", got %s", str); + pass = 1'b0; + end + $sformat(str, "%0d", su + (16 >> 1) - 1); + if (str[8*4:1] !== "2007" || str[8*40:8*4+1] !== 0) begin + $display("FAILED first string >> (su), expected \"2007\", got %s", str); + pass = 1'b0; + end + + $sformat(str, "%0d", (s + (1 << 3) - 1) * 16000); + if (str[8*8:1] !== "32112000" || str[8*40:8*8+1] !== 0) begin + $display("FAILED second string << (s), expected \"32112000\", got %s", + str); + pass = 1'b0; + end + $sformat(str, "%0d", (su + (1 << 3) - 1) * 16000); + if (str[8*8:1] !== "32112000" || str[8*40:8*8+1] !== 0) begin + $display("FAILED second string << (su), expected \"32112000\", got %s", + str); + pass = 1'b0; + end + + $sformat(str, "%0d", (s + (16 >> 1) - 1) * 16000); + if (str[8*8:1] !== "32112000" || str[8*40:8*8+1] !== 0) begin + $display("FAILED second string >> (s), expected \"32112000\", got %s", + str); + pass = 1'b0; + end + $sformat(str, "%0d", (su + (16 >> 1) -1) * 16000); + if (str[8*8:1] !== "32112000" || str[8*40:8*8+1] !== 0) begin + $display("FAILED second string >> (su), expected \"32112000\", got %s", + str); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3098439a.v b/ivtest/ivltests/pr3098439a.v new file mode 100644 index 000000000..46c573c10 --- /dev/null +++ b/ivtest/ivltests/pr3098439a.v @@ -0,0 +1,50 @@ +// This file extends the original bug test case to explore all the +// forms of a signed left shift that are treated as special cases. +module test; + reg pass; + reg [8*40:1] str; + integer s; + + initial begin + pass = 1'b1; + s = 1; + + $sformat(str, "%0d", ((0 << 1) + 1) * -1); + if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin + $display("FAILED 1st test, expected \"-1\", got %s", str); + pass = 1'b0; + end + + $sformat(str, "%0d", ((1 << 1) + 1) * -1); + if (str[8*2:1] !== "-3" || str[8*40:8*2+1] !== 0) begin + $display("FAILED 2nd test, expected \"-3\", got %s", str); + pass = 1'b0; + end + + $sformat(str, "%0d", ((1 << s) + 1) * -1); + if (str[8*2:1] !== "-3" || str[8*40:8*2+1] !== 0) begin + $display("FAILED 3rd test, expected \"-3\", got %s", str); + pass = 1'b0; + end + + $sformat(str, "%0d", ((s << 1) + 1) * -1); + if (str[8*2:1] !== "-3" || str[8*40:8*2+1] !== 0) begin + $display("FAILED 4th test, expected \"-3\", got %s", str); + pass = 1'b0; + end + + $sformat(str, "%0d", ((s << 0) + 1) * -1); + if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin + $display("FAILED 5th test, expected \"-2\", got %s", str); + pass = 1'b0; + end + + $sformat(str, "%0d", ((s << 64) + 1'sd1) * -1'sd1); + if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin + $display("FAILED 6th test, expected \"-1\", got %s", str); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3098439b.v b/ivtest/ivltests/pr3098439b.v new file mode 100644 index 000000000..3eeebcc67 --- /dev/null +++ b/ivtest/ivltests/pr3098439b.v @@ -0,0 +1,50 @@ +// This file extends the original bug test case to explore all the +// forms of a signed right shift that are treated as special cases. +module test; + reg pass; + reg [8*40:1] str; + integer s; + + initial begin + pass = 1'b1; + s = 1; + + $sformat(str, "%0d", ((0 >> 1) + 1) * -1); + if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin + $display("FAILED 1st test, expected \"-1\", got %s", str); + pass = 1'b0; + end + + $sformat(str, "%0d", ((2 >> 1) + 1) * -1); + if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin + $display("FAILED 2nd test, expected \"-2\", got %s", str); + pass = 1'b0; + end + + $sformat(str, "%0d", ((2 >> s) + 1) * -1); + if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin + $display("FAILED 3rd test, expected \"-2\", got %s", str); + pass = 1'b0; + end + + $sformat(str, "%0d", ((s >> 1) + 1) * -1); + if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin + $display("FAILED 4th test, expected \"-1\", got %s", str); + pass = 1'b0; + end + + $sformat(str, "%0d", ((s >> 0) + 1) * -1); + if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin + $display("FAILED 5th test, expected \"-2\", got %s", str); + pass = 1'b0; + end + + $sformat(str, "%0d", ((s >> 64) + 1) * -1); + if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin + $display("FAILED 6th test, expected \"-1\", got %s", str); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3103880.v b/ivtest/ivltests/pr3103880.v new file mode 100644 index 000000000..f8b568a66 --- /dev/null +++ b/ivtest/ivltests/pr3103880.v @@ -0,0 +1,30 @@ +module test; + reg pass; + reg [8*40:1] str; + reg [15:0] v; + + initial begin + pass = 1'b1; + v = 2; + + $sformat(str, "%0d", (v + 2 - 1) * 1); + if (str[8*1:1] !== "3" || str[8*40:8*1+1] !== 0) begin + $display("FAILED 1st test, expected \"3\", got %s", str); + pass = 1'b0; + end + + $sformat(str, "%0d", 'd1 - 'd2 + v); + if (str[8*1:1] !== "1" || str[8*40:8*1+1] !== 0) begin + $display("FAILED 2nd test, expected \"1\", got %s", str); + pass = 1'b0; + end + + $sformat(str, "%0d", v + (-1)); + if (str[8*1:1] !== "1" || str[8*40:8*1+1] !== 0) begin + $display("FAILED 3rd test, expected \"1\", got %s", str); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3104254.v b/ivtest/ivltests/pr3104254.v new file mode 100644 index 000000000..b130fe532 --- /dev/null +++ b/ivtest/ivltests/pr3104254.v @@ -0,0 +1,50 @@ +module test; + +reg signed [3:0] a; +reg signed [3:0] b; +reg [3:0] u; +reg [3:0] r; + +reg fail; + +initial begin + fail = 0; + a = 4'b1000; + b = 4'b0010; + u = 4'b0001; + + r = ((a >>> 1) | b ) | u; + $display("step 1 expected '0111', got '%b'", r); + if (r !== 4'b0111) fail = 1; + + r = ((4'b1000 >>> 1) | b ) | u; + $display("step 2 expected '0111', got '%b'", r); + if (r !== 4'b0111) fail = 1; + + r = ((a >>> 1) | 4'b0010) | u; + $display("step 3 expected '0111', got '%b'", r); + if (r !== 4'b0111) fail = 1; + + r = ((a >>> 1) | b ) | 4'b0001; + $display("step 4 expected '0111', got '%b'", r); + if (r !== 4'b0111) fail = 1; + + r = ((4'b1000 >>> 1) | 4'b0010) | u; + $display("step 5 expected '0111', got '%b'", r); + if (r !== 4'b0111) fail = 1; + + r = ((a >>> 1) | 4'b0010) | 4'b0001; + $display("step 6 expected '0111', got '%b'", r); + if (r !== 4'b0111) fail = 1; + + r = ((4'b1000 >>> 1) | 4'b0010) | 4'b0001; + $display("step 7 expected '0111', got '%b'", r); + if (r !== 4'b0111) fail = 1; + + if (fail) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr3112073a.v b/ivtest/ivltests/pr3112073a.v new file mode 100644 index 000000000..326b3e2dd --- /dev/null +++ b/ivtest/ivltests/pr3112073a.v @@ -0,0 +1,9 @@ +module top; + reg real [1:0] a; + + initial begin + a[0] = 0.3; + a[1] = 0.4; + $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/pr312.v b/ivtest/ivltests/pr312.v new file mode 100644 index 000000000..28bdc74e2 --- /dev/null +++ b/ivtest/ivltests/pr312.v @@ -0,0 +1,24 @@ +module main; + + reg [1:0] x; + reg [2:0] y; + + initial begin + x = 1; + y = {1'b0, x << 1}; + + if (y !== 3'b010) begin + $display("FAILED -- y (%b) != 3'b010", y); + $finish; + end + + y = {1'b0, x << 2}; + if (y !== 3'b000) begin + $display("FAILED -- y (%b) != 3'b000", y); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/pr3149494.v b/ivtest/ivltests/pr3149494.v new file mode 100644 index 000000000..3e5c74d94 --- /dev/null +++ b/ivtest/ivltests/pr3149494.v @@ -0,0 +1,13 @@ +module m; + + reg [4'b1111 + 4'b0001 >> 1:0] x; + reg [4'b1111 + 1 >> 1:0] y; + + initial + begin + x = -1; + y = -1; + $display("x = %b", x); + $display("y = %b", y); + end +endmodule diff --git a/ivtest/ivltests/pr3190941.v b/ivtest/ivltests/pr3190941.v new file mode 100644 index 000000000..e7cc513a6 --- /dev/null +++ b/ivtest/ivltests/pr3190941.v @@ -0,0 +1,11 @@ +module m1(output reg [7:0] x); +endmodule + +module m2(input [3:0] y); +endmodule + +module tb; + wire [3:0] y; + m1 foo({4'hx, y}); + m2 bar(.y(y)); +endmodule diff --git a/ivtest/ivltests/pr3190948.v b/ivtest/ivltests/pr3190948.v new file mode 100644 index 000000000..2eb5aeaff --- /dev/null +++ b/ivtest/ivltests/pr3190948.v @@ -0,0 +1,3 @@ +(* foo, bar=1 *) (* baz=1 *) module foo; + initial $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/pr3194155.v b/ivtest/ivltests/pr3194155.v new file mode 100644 index 000000000..c456692b0 --- /dev/null +++ b/ivtest/ivltests/pr3194155.v @@ -0,0 +1,17 @@ +module foo(input x); +parameter n = 0; +pulldown p1(x); +initial #n $display("x(%0d) : %b", n, x); +endmodule + +module tb; +wire y; +wire z; +foo #1 bar1(1'b0); +foo #2 bar2(1'b1); +foo #3 bar3(1'bz); +foo #4 bar4(y); +foo #5 bar5({z}); +initial #6 $display("y : ", y); +initial #7 $display("z : ", z); +endmodule diff --git a/ivtest/ivltests/pr3197861.v b/ivtest/ivltests/pr3197861.v new file mode 100644 index 000000000..9c18778bf --- /dev/null +++ b/ivtest/ivltests/pr3197861.v @@ -0,0 +1,15 @@ +`begin_keywords "1364-2005" +module top; + reg [5:0] ivar; + real var; + + initial begin + ivar = 0; + var = 157.0; + // The following line is not being calculated correctly! + var = var - 180*ivar[5]; + if (var != 157.0) $display("Failed: This should be 157.0: ", var); + else $display("PASSED"); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr3197917.v b/ivtest/ivltests/pr3197917.v new file mode 100644 index 000000000..67d40539a --- /dev/null +++ b/ivtest/ivltests/pr3197917.v @@ -0,0 +1,19 @@ +module top; + reg [23:0] in1; + reg [54:0] in2; + + initial begin + in1 = 24'b111111000000111111000000; + in2 = 55'b0000011111000001111100000111110000011111000001111100000; + #1; + if (dut.arg !== 96'b111111000000111111000000zzzzzzzzzzzzzzzzz0000011111000001111100000111110000011111000001111100000) begin + $display("FAILED"); + end else $display("PASSED"); + end + test dut(in1, in2); +endmodule + +module test(arg[119:96], arg[78:24]); + input [119:24] arg; + +endmodule diff --git a/ivtest/ivltests/pr3270320.v b/ivtest/ivltests/pr3270320.v new file mode 100644 index 000000000..e93a1a851 --- /dev/null +++ b/ivtest/ivltests/pr3270320.v @@ -0,0 +1,17 @@ +module bug(); + +function [7:0] dup; + +input [7:0] i; + +begin + dup = i; +end + +endfunction + +wire [7:0] a; + +assign a = dup(missing); + +endmodule diff --git a/ivtest/ivltests/pr3270320_ams.v b/ivtest/ivltests/pr3270320_ams.v new file mode 100644 index 000000000..d306f8ba3 --- /dev/null +++ b/ivtest/ivltests/pr3270320_ams.v @@ -0,0 +1,7 @@ +module bug(); + +wire [7:0] b; + +assign b = $abs(missing); + +endmodule diff --git a/ivtest/ivltests/pr3284821.v b/ivtest/ivltests/pr3284821.v new file mode 100644 index 000000000..bdb2298c3 --- /dev/null +++ b/ivtest/ivltests/pr3284821.v @@ -0,0 +1,20 @@ +// Test that expression width calculation correctly treats right operand +// of shift as unsigned regardless of its actual type. +module test; + reg pass; + reg [8*20:1] str; + reg signed [3:0] N; + + initial begin + pass = 1'b1; + + N = -1; + $sformat(str, "%0d", 1 << N); + if (str[8*5:1] !== "32768" || str[8*20:8*5+1] !== 0) begin + $display("FAILED test, expected \"32768\", got \"%0s\"", str); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3292735.v b/ivtest/ivltests/pr3292735.v new file mode 100644 index 000000000..5915a6d6a --- /dev/null +++ b/ivtest/ivltests/pr3292735.v @@ -0,0 +1,15 @@ +module table_out( + input [1:0] a, + (* rom_style = "distributed" *) output reg signed [9:0] phase +); + +always @(*) case (a) + 2'd 0: phase = 0; + 2'd 1: phase = 90; + 2'd 2: phase = 180; + 2'd 3: phase = 270; +endcase + +initial $display("PASSED"); + +endmodule diff --git a/ivtest/ivltests/pr3296466a.v b/ivtest/ivltests/pr3296466a.v new file mode 100644 index 000000000..0a1a062f0 --- /dev/null +++ b/ivtest/ivltests/pr3296466a.v @@ -0,0 +1,20 @@ +module top(); + +reg foo; + +tri [1:0] a; + +assign a[0] = foo; + +tran(a[0], a[1]); + +initial begin + foo = 1'b1; + #1 $display("%b", a); + if (a === 2'b11) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/pr3296466b.v b/ivtest/ivltests/pr3296466b.v new file mode 100644 index 000000000..4a572b6f4 --- /dev/null +++ b/ivtest/ivltests/pr3296466b.v @@ -0,0 +1,36 @@ +module connect(inout [1:0] c); + +tran(c[0], c[1]); + +endmodule + +module top(); + +tri [3:0] a; + +reg dir; + +connect connect1(a[1:0]); +connect connect2(a[2:1]); +connect connect3(a[3:2]); + +assign a[0] = dir ? 1'bz : 1'b0; +assign a[3] = dir ? 1'b1 : 1'bz; + +reg pass = 1; + +initial begin + dir = 1'b0; + #1 $display("%b", a); + if (a !== 4'b0000) pass = 0; + dir = 1'b1; + #1 $display("%b", a); + if (a !== 4'b1111) pass = 0; + + if (pass) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/pr3296466c.v b/ivtest/ivltests/pr3296466c.v new file mode 100644 index 000000000..a8d595505 --- /dev/null +++ b/ivtest/ivltests/pr3296466c.v @@ -0,0 +1,24 @@ +module top(); + +reg foo; +reg bar; + +tri [1:0] a; +tri [1:0] b; + +assign a[0] = foo; +assign b[1] = bar; + +tran t[1:0](a, b); + +initial begin + foo = 1'b1; + bar = 1'b0; + #1 $display("%b %b", a, b); + if ((a === 2'b01) && (b === 2'b01)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/pr3296466d.v b/ivtest/ivltests/pr3296466d.v new file mode 100644 index 000000000..6327a90d5 --- /dev/null +++ b/ivtest/ivltests/pr3296466d.v @@ -0,0 +1,28 @@ +module top(); + +reg foo; + +tri [1:0] a; +tri [1:0] b; +tri [3:0] c; + +assign a[0] = foo; + +tran t1(a[0], a[1]); +tran t2(b[0], b[1]); + +tran t3[1:0](a, c[1:0]); +tran t4[1:0](b, c[3:2]); + +tran t5(c[1], c[3]); + +initial begin + foo = 1'b1; + #1 $display("%b %b %b", a, b, c); + if ((a === 2'b11) && (b === 2'b11) && (c === 4'b1111)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/pr3306516.v b/ivtest/ivltests/pr3306516.v new file mode 100644 index 000000000..197e393cf --- /dev/null +++ b/ivtest/ivltests/pr3306516.v @@ -0,0 +1,45 @@ +// Must be run with -gspecify +module top; + reg passed; + reg a, b; + wire y; + + initial begin + passed = 1'b1; + a = 0; + b = 1; + #2 if (y !== 1'bx && y !== 1'bz) begin + $display("Failed: Initial value, expected 1'bx, got %b", y); + passed = 1'b0; + end + #2 if (y !== 1'b0) begin + $display("Failed: Initial value propagation, expected 1'b0, got %b", y); + passed = 1'b0; + end + a = 1; + #2 if (y !== 1'b0) begin + $display("Failed: to hold initial value, expected 1'b0, got %b", y); + passed = 1'b0; + end + #2 if (y !== 1'b1) begin + $display("Failed: Final value propagation, expected 1'b1, got %b", y); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end + + my_and dut(y, a, b); +endmodule + +module my_and(output wire y, input wire a, b); + specify + specparam ta = 1; + specparam tb = 2; + endspecify + // A specparam is just like a parameter in this context. In reality + // they can be overridden at run-time so the following should really + // be an expression instead of just a constant 3, but for now 3 would + // be acceptable. Specparams and the specify block need a major rework. + assign #(ta+tb) y = a & b; +endmodule diff --git a/ivtest/ivltests/pr3309391.v b/ivtest/ivltests/pr3309391.v new file mode 100644 index 000000000..f92dcf36b --- /dev/null +++ b/ivtest/ivltests/pr3309391.v @@ -0,0 +1,8 @@ +module top; + specify + specparam Tdelay = 1.0; + endspecify + + initial if (Tdelay != 1.0) $display("FAILED:, got %f", Tdelay); + else $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/pr3366114.v b/ivtest/ivltests/pr3366114.v new file mode 100644 index 000000000..4b588197f --- /dev/null +++ b/ivtest/ivltests/pr3366114.v @@ -0,0 +1,45 @@ +/* +* Author: Oswaldo Cadenas +* +* The test checks that an unspecified output type is elaborated as Net. +* If an intial value is given to an unspecified ouput type it does +* not compile. +*/ + +module clkgen(output logic clk); + + logic iclk = 'x; + assign clk = iclk; + + initial begin + #100; + disable checking; + disable gen; + $display ("PASSED"); + $finish; + end + + initial begin + fork + checking; + gen; + join + end + + task gen; + begin + iclk = 0; + forever #10 iclk = ~iclk; + end + endtask + + task checking; + forever begin + #1; + if (clk === 1'bx ) begin + $display ("FAILED!"); + $finish; + end + end + endtask +endmodule diff --git a/ivtest/ivltests/pr3366217a.v b/ivtest/ivltests/pr3366217a.v new file mode 100644 index 000000000..5e860c22f --- /dev/null +++ b/ivtest/ivltests/pr3366217a.v @@ -0,0 +1,6 @@ +module top; + // You can't have an over range value (compile time error). + enum bit[4:0] {some[4] = 100} val; + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/pr3366217b.v b/ivtest/ivltests/pr3366217b.v new file mode 100644 index 000000000..e77d095b0 --- /dev/null +++ b/ivtest/ivltests/pr3366217b.v @@ -0,0 +1,6 @@ +module top; + // You can't have an under range value (compile time error). + enum bit[1:0] {nega = -1, b , c} val; + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/pr3366217c.v b/ivtest/ivltests/pr3366217c.v new file mode 100644 index 000000000..86566941b --- /dev/null +++ b/ivtest/ivltests/pr3366217c.v @@ -0,0 +1,6 @@ +module top; + // An implicit value cannot be over range (compile time error). + enum bit[1:0] {a = 3, b , c} val; + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/pr3366217d.v b/ivtest/ivltests/pr3366217d.v new file mode 100644 index 000000000..36bab99b8 --- /dev/null +++ b/ivtest/ivltests/pr3366217d.v @@ -0,0 +1,27 @@ +module top; + // An undefined sequence value is an error. + enum {udef[1'bx]} udef1; + enum {udef1[1'bx:1]} udef2; + enum {udef2[1:1'bx]} udef3; + enum {udefb[1'bx:1'bx]} udef4; + enum {uval[1'bx] = 1} uval1; + enum {uval1[1'bx:1] = 1} uval2; + enum {uval2[1:1'bx] = 1} uval3; + enum {uvalb[1'bx:1'bx] = 1} uval4; + + // A zero sequence value is an error. + enum {zdef[0]} zdef1; + enum {zval[0] = 1} zval1; + + // A negative sequence value is an error. + enum {ndef[-1]} ndef1; + enum {ndef1[-1:0]} ndef2; + enum {ndef2[0:-1]} ndef3; + enum {ndefb[-1:-1]} ndef4; + enum {nval[-1] = 1} nval1; + enum {nval1[-1:0] = 1} nval2; + enum {nval2[0:-1] = 1} nval3; + enum {nvalb[-1:-1] = 1} nval4; + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/pr3366217e.v b/ivtest/ivltests/pr3366217e.v new file mode 100644 index 000000000..2b735db00 --- /dev/null +++ b/ivtest/ivltests/pr3366217e.v @@ -0,0 +1,42 @@ +module top; + reg passed; + // These should be OK + enum {zdef1_[0:1]} zdef1; + enum {zdef2_[1:0]} zdef2; + enum {zdefb_[0:0]} zdef3; + enum {zvalb_[0:0] = 1} zval1; + + initial begin + passed = 1'b1; + + if (zdef1_0 !== 0) begin + $display("FAILED: expected zdef1_0 to be 0, got %0d", zdef1_0); + passed = 1'b0; + end + if (zdef1_1 !== 1) begin + $display("FAILED: expected zdef1_1 to be 1, got %0d", zdef1_1); + passed = 1'b0; + end + + if (zdef2_1 !== 0) begin + $display("FAILED: expected zdef2_1 to be 0, got %0d", zdef2_1); + passed = 1'b0; + end + if (zdef2_0 !== 1) begin + $display("FAILED: expected zdef2_0 to be 1, got %0d", zdef2_0); + passed = 1'b0; + end + + if (zdefb_0 !== 0) begin + $display("FAILED: expected zdefb_0 to be 0, got %0d", zdefb_0); + passed = 1'b0; + end + + if (zvalb_0 !== 1) begin + $display("FAILED: expected zvalb_0 to be 1, got %0d", zvalb_0); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3366217f.v b/ivtest/ivltests/pr3366217f.v new file mode 100644 index 000000000..cc325244c --- /dev/null +++ b/ivtest/ivltests/pr3366217f.v @@ -0,0 +1,25 @@ +module top; + // This should be valid. The Icarus compiler keeps these as negatives, but + // the run time doesn't support negative values. + enum bit signed [7:0] {rn = -1, yn = -2, gn = -3} nl; + integer val; + + initial begin + nl = rn; + $display("First: %d", nl); + nl = nl.next; + $display("Second: %d", nl); + nl = nl.next; + $display("Third: %d", nl); + nl = nl.next; + $display("Wrapped: %d", nl); + nl = nl.prev; + $display("Wrapped: %d", nl); + val = nl; + $display("As integer: %d", val); + end + + // This should be a signed value! + initial #1 $display("Compile: ", rn); + +endmodule diff --git a/ivtest/ivltests/pr3366217g.v b/ivtest/ivltests/pr3366217g.v new file mode 100644 index 000000000..8a401c222 --- /dev/null +++ b/ivtest/ivltests/pr3366217g.v @@ -0,0 +1,7 @@ +module top; + // You can't have duplicate values! + enum {red = 1, green, blue = 2} light; + enum {first = 2, second = 1, third} nums; + + initial $display("FAILED"); +endmodule diff --git a/ivtest/ivltests/pr3366217h.v b/ivtest/ivltests/pr3366217h.v new file mode 100644 index 000000000..406885567 --- /dev/null +++ b/ivtest/ivltests/pr3366217h.v @@ -0,0 +1,68 @@ +module top; + reg pass; + enum bit signed [7:0] {a = 1, b = 2, c = 3, d = 4} enum_var; + + initial begin + pass = 1'b1; + +// Add another test that a negative value is not valid. +// Also an out of range value stays out of range. + enum_var = a; + if (enum_var !== enum_var.first) begin + $display("FAILED: initialization, expected %d, got %d", a, enum_var); + pass = 1'b0; + end + + enum_var = enum_var.next; + enum_var = enum_var.prev; + enum_var = enum_var.next(); + if (enum_var !== b) begin + $display("FAILED: next(), expected %d, got %d", b, enum_var); + pass = 1'b0; + end + + enum_var = enum_var.next(0); + if (enum_var !== b) begin + $display("FAILED: next(0), expected %d, got %d", b, enum_var); + pass = 1'b0; + end + + enum_var = enum_var.next(1); + if (enum_var !== c) begin + $display("FAILED: next(1), expected %d, got %d", c, enum_var); + pass = 1'b0; + end + + enum_var = enum_var.next(2); + if (enum_var !== a) begin + $display("FAILED: next(2), expected %d, got %d", a, enum_var); + pass = 1'b0; + end + + enum_var = enum_var.prev(); + if (enum_var !== d) begin + $display("FAILED: prev(), expected %d, got %d", d, enum_var); + pass = 1'b0; + end + + enum_var = enum_var.prev(0); + if (enum_var !== d) begin + $display("FAILED: prev(0), expected %d, got %d", d, enum_var); + pass = 1'b0; + end + + enum_var = enum_var.prev(1); + if (enum_var !== c) begin + $display("FAILED: prev(1), expected %d, got %d", c, enum_var); + pass = 1'b0; + end + + enum_var = enum_var.prev(2); + if (enum_var !== a) begin + $display("FAILED: prev(2), expected %d, got %d", a, enum_var); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3366217i.v b/ivtest/ivltests/pr3366217i.v new file mode 100644 index 000000000..84066401a --- /dev/null +++ b/ivtest/ivltests/pr3366217i.v @@ -0,0 +1,46 @@ +/* + * Check that the initial value can be out of range and that the next()/prev() + * enumeration methods do not change to a defined state. + */ +module top; + reg pass; + enum bit [3:0] {a2 = 1, b2 = 2, c2 = 3, d2 = 4} evar2; + enum reg [3:0] {a4 = 1, b4 = 2, c4 = 3, d4 = 4} evar4; + + initial begin + pass = 1'b1; + + if (evar2 !== 0) begin + $display("Failed initial/2 value should be 0, got %d", evar2); + pass = 1'b0; + end + if (evar4 !== 4'bx) begin + $display("Failed initial/4 value should be 'bx, got %d", evar4); + pass = 1'b0; + end + + evar2 = evar2.next; + if (evar2 !== 0) begin + $display("Failed next/2 of an invalid value should be 0, got %d", evar2); + pass = 1'b0; + end + evar4 = evar4.next; + if (evar4 !== 4'bx) begin + $display("Failed next/4 of an invalid value should be 0, got %d", evar4); + pass = 1'b0; + end + + evar2 = evar2.prev; + if (evar2 !== 0) begin + $display("Failed prev/2 of an invalid value should be 0, got %d", evar2); + pass = 1'b0; + end + evar4 = evar4.prev; + if (evar4 !== 4'bx) begin + $display("Failed prev/4 of an invalid value should be 0, got %d", evar4); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3368642.v b/ivtest/ivltests/pr3368642.v new file mode 100644 index 000000000..18230119a --- /dev/null +++ b/ivtest/ivltests/pr3368642.v @@ -0,0 +1,35 @@ +module bug; + +reg [3:0] r1; +wire [3:0] w1; +wire [3:0] w2; + +assign w1 = r1; +assign w2 = w1; + +reg fail = 0; + +initial begin + r1 = 0; + #1 $display("%b %b %b", r1, w1, w2); + if ((r1 !== 4'b0000) || (w1 !== 4'b0000) || (w2 !== 4'b0000)) fail = 1; + force w1 = 4'bz; + #1 $display("%b %b %b", r1, w1, w2); + if ((r1 !== 4'b0000) || (w1 !== 4'bzzzz) || (w2 !== 4'bzzzz)) fail = 1; + r1 = 1; + #1 $display("%b %b %b", r1, w1, w2); + if ((r1 !== 4'b0001) || (w1 !== 4'bzzzz) || (w2 !== 4'bzzzz)) fail = 1; + release w1; + #1 $display("%b %b %b", r1, w1, w2); + if ((r1 !== 4'b0001) || (w1 !== 4'b0001) || (w2 !== 4'b0001)) fail = 1; + r1 = 2; + #1 $display("%b %b %b", r1, w1, w2); + if ((r1 !== 4'b0010) || (w1 !== 4'b0010) || (w2 !== 4'b0010)) fail = 1; + + if (fail) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr338.v b/ivtest/ivltests/pr338.v new file mode 100644 index 000000000..ac890db25 --- /dev/null +++ b/ivtest/ivltests/pr338.v @@ -0,0 +1,26 @@ +// +// Copyright (c) 2001 Stephan Gehring (stephan.gehring@@ieee.org) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Has a constant 'hzz that blows up icarus + +module Bug; + reg [7:0] x; + initial begin + x = 'h4000 + 'hzz; // iverilog doesn't like 'hzz + end +endmodule diff --git a/ivtest/ivltests/pr3390385.v b/ivtest/ivltests/pr3390385.v new file mode 100644 index 000000000..11778a04b --- /dev/null +++ b/ivtest/ivltests/pr3390385.v @@ -0,0 +1,40 @@ +module tb; + +reg [1:0] i, j; +reg [3:0] x[0:2]; +reg error; + +initial begin + error = 0; + + i = 0; + j = i++; + if (i !== 2'b01 || j !== 2'b00) begin + $display("FAILED j = i++ --> j=%b, i=%b", j, i); + error = 1; + end + + i = 0; + x[0] = 4'dx; + x[1] = 4'dx; + x[i++] = 0; + if (x[0] !== 4'd0 || x[1] !== 4'dx) begin + $display("FAILED x[i++] = 0 --> x[0]=%b, x[1]=%b, i=%b", x[0], x[1], i); + error = 1; + end + + i = 0; + x[0] = 1; + x[i++] += 2; + if (x[0] !== 4'd3) begin + $display("FAILED x[0] should be 3, but it is %d.", x[0]); + error = 1; + end + if (i !== 2'd1) begin + $display("FAILED i should be 1, but it is %d.", i); + error = 1; + end + if (error == 0) + $display("PASSED"); +end +endmodule // tb diff --git a/ivtest/ivltests/pr3390385b.v b/ivtest/ivltests/pr3390385b.v new file mode 100644 index 000000000..324e8c1ca --- /dev/null +++ b/ivtest/ivltests/pr3390385b.v @@ -0,0 +1,40 @@ +module tb; + +reg [1:0] i, j; +reg [3:0] x[0:2]; +reg error; + +initial begin + error = 0; + + i = 0; + j = i++; + if (i !== 2'b01 || j !== 2'b00) begin + $display("FAILED j = i++ --> j=%b, i=%b", j, i); + error = 1; + end + + i = 0; + x[0] = 4'dx; + x[1] = 4'dx; + x[0] = 0; + if (x[0] !== 4'd0 || x[1] !== 4'dx) begin + $display("FAILED x[i++] = 0 --> x[0]=%b, x[1]=%b, i=%b", x[0], x[1], i); + error = 1; + end + + i = 0; + x[0] = 1; + x[0] += 2; + if (x[0] !== 4'd3) begin + $display("FAILED x[0] should be 3, but it is %d.", x[0]); + error = 1; + end + if (i !== 2'd0) begin + $display("FAILED i should be 1, but it is %d.", i); + error = 1; + end + if (error == 0) + $display("PASSED"); +end +endmodule // tb diff --git a/ivtest/ivltests/pr3390385c.v b/ivtest/ivltests/pr3390385c.v new file mode 100644 index 000000000..5852a1221 --- /dev/null +++ b/ivtest/ivltests/pr3390385c.v @@ -0,0 +1,40 @@ +module tb; + +reg [1:0] i, j; +reg [3:0] x; +reg error; + +initial begin + error = 0; + + i = 0; + j = i++; + if (i !== 2'b01 || j !== 2'b00) begin + $display("FAILED j = i++ --> j=%b, i=%b", j, i); + error = 1; + end + + i = 0; + x[0] = 1'bx; + x[1] = 1'bx; + x[i++] = 1'b0; + if (x[0] !== 1'b0 || x[1] !== 1'bx) begin + $display("FAILED x[i++] = 0 --> x[0]=%b, x[1]=%b, i=%b", x[0], x[1], i); + error = 1; + end + + i = 0; + x[0] = 1'b1; + x[i++] += 1'b1; + if (x[0] !== 1'b0) begin + $display("FAILED x[0] should be 0, but it is %b.", x[0]); + error = 1; + end + if (i !== 2'd1) begin + $display("FAILED i should be 1, but it is %d.", i); + error = 1; + end + if (error == 0) + $display("PASSED"); +end +endmodule // tb diff --git a/ivtest/ivltests/pr3390385d.v b/ivtest/ivltests/pr3390385d.v new file mode 100644 index 000000000..32043c880 --- /dev/null +++ b/ivtest/ivltests/pr3390385d.v @@ -0,0 +1,40 @@ +module tb; + +reg [1:0] i, j; +reg [3:0] x; +reg error; + +initial begin + error = 0; + + i = 0; + j = i++; + if (i !== 2'b01 || j !== 2'b00) begin + $display("FAILED j = i++ --> j=%b, i=%b", j, i); + error = 1; + end + + i = 0; + x[0] = 1'bx; + x[1] = 1'bx; + x[0] = 1'b0; + if (x[0] !== 1'b0 || x[1] !== 1'bx) begin + $display("FAILED x[i++] = 0 --> x[0]=%b, x[1]=%b, i=%b", x[0], x[1], i); + error = 1; + end + + i = 0; + x[0] = 1'b1; + x[0] += 1'b1; + if (x[0] !== 1'b0) begin + $display("FAILED x[0] should be 0, but it is %b.", x[0]); + error = 1; + end + if (i !== 2'd0) begin + $display("FAILED i should be 1, but it is %d.", i); + error = 1; + end + if (error == 0) + $display("PASSED"); +end +endmodule // tb diff --git a/ivtest/ivltests/pr3409749.v b/ivtest/ivltests/pr3409749.v new file mode 100644 index 000000000..7f16950b6 --- /dev/null +++ b/ivtest/ivltests/pr3409749.v @@ -0,0 +1,49 @@ +module top; + reg pass = 1'b1; + + genvar lp; + for (lp=1; lp <= 128; lp = lp + 1) begin: loop + test #(lp) dut(); + end + + initial #1000 if (pass) $display("PASSED"); +endmodule + +module test; + parameter wid = 62; + + localparam X = {4'b1000, {wid{1'b0}}}; + localparam Y = {1'b1, {wid{1'b0}}}; + + reg [wid:0] y = Y; + reg [wid+3:0] x = X; + reg [3:0] res; + + initial begin + #wid; // Wait for the x and y values to get assigned. + res = X/Y; + if (res !== 4'b1000) begin + $display("Failed const. division for %3d, expected 4'b1000, got %b", + wid, res); + top.pass = 1'b0; + end + res = X/y; + if (res !== 4'b1000) begin + $display("Failed const. numerator for %3d, expected 4'b1000, got %b", + wid, res); + top.pass = 1'b0; + end + res = x/Y; + if (res !== 4'b1000) begin + $display("Failed const. denominator for %3d, expected 4'b1000, got %b", + wid, res); + top.pass = 1'b0; + end + res = x/y; + if (res !== 4'b1000) begin + $display("Failed variable division for %3d, expected 4'b1000, got %b", + wid, res); + top.pass = 1'b0; + end + end +endmodule diff --git a/ivtest/ivltests/pr3437290a.v b/ivtest/ivltests/pr3437290a.v new file mode 100644 index 000000000..c29561cbe --- /dev/null +++ b/ivtest/ivltests/pr3437290a.v @@ -0,0 +1,21 @@ +module top; + reg a, b, c, d, e; + wor out; + + assign out = a; + assign out = b; + assign out = c; + assign out = d; + assign out = e; + + initial begin + a = 1'b0; + b = 1'b0; + c = 1'b1; + d = 1'b0; + e = 1'b0; + #1; + if (out !== 1'b1) $display("FAILED: expected 1'b1, got %b", out); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3437290b.v b/ivtest/ivltests/pr3437290b.v new file mode 100644 index 000000000..c9f468cdd --- /dev/null +++ b/ivtest/ivltests/pr3437290b.v @@ -0,0 +1,31 @@ +module top; + localparam wid = 7; + localparam vec_wid = $clog2(wid+1)-1; + reg pass; + reg [vec_wid:0] mem [wid:0]; + reg [wid:0] sel; + wor [vec_wid:0] out; + integer lp; + genvar i; + + for (i = 0; i <= wid; i = i + 1) assign out = sel[i] ? mem[i] : {wid{1'b0}}; + + initial begin + pass = 1'b1; + + for (lp = 0; lp <= wid; lp = lp + 1) begin + mem[lp] = lp; + end + + for (lp = 0; lp <= wid; lp = lp + 1) begin + sel = 2**lp; + #1; + if (out !== mem[lp]) begin + $display("FAILED: mem[%0d] %b != %b (%b)", lp, mem[lp], out, sel); + pass = 1'b0; + end else $display("OK: mem[%0d] %b (%b)", lp, out, sel); + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3437290c.v b/ivtest/ivltests/pr3437290c.v new file mode 100644 index 000000000..b8a021c42 --- /dev/null +++ b/ivtest/ivltests/pr3437290c.v @@ -0,0 +1,21 @@ +module top; + reg a, b, c, d, e; + wand out; + + assign out = a; + assign out = b; + assign out = c; + assign out = d; + assign out = e; + + initial begin + a = 1'b1; + b = 1'b0; + c = 1'b1; + d = 1'b1; + e = 1'b1; + #1; + if (out !== 1'b0) $display("FAILED: expected 1'b1, got %b", out); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3441576.v b/ivtest/ivltests/pr3441576.v new file mode 100644 index 000000000..ed90ce00c --- /dev/null +++ b/ivtest/ivltests/pr3441576.v @@ -0,0 +1,5 @@ +module top; + reg foo; + always @* foo <= 0; + initial #1 $display("foo is %b", foo); +endmodule diff --git a/ivtest/ivltests/pr3445452.v b/ivtest/ivltests/pr3445452.v new file mode 100644 index 000000000..6330e3f60 --- /dev/null +++ b/ivtest/ivltests/pr3445452.v @@ -0,0 +1,42 @@ +module task_time_arg; + reg pass; + integer result; + + task test_it1; + realtime tmp; + begin + tmp = $realtime; + go_busy(tmp); + end + endtask + + task test_it2; + go_busy($realtime); + endtask + + task go_busy; + input delay; + integer delay; + result = delay; + endtask // go_busy + + initial begin + pass = 1'b1; + #6 + test_it1; + if (result !== 6) begin + $display("Failed: testit1, expected 6, got %d", result); + pass = 1'b0; + end + + #1 + test_it2; + if (result !== 7) begin + $display("Failed: testit2, expected 7, got %d", result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr3452808.v b/ivtest/ivltests/pr3452808.v new file mode 100644 index 000000000..37f297d07 --- /dev/null +++ b/ivtest/ivltests/pr3452808.v @@ -0,0 +1,110 @@ +/*********************************************************************** + * + * Copyright (C) 2011 Adrian Wise + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + *********************************************************************** + * + * This is a testbench exercising gate-level modelling of DTL gates, + * distilled down (as a test-case) from a much larger design. + * The gates can only pull down strongly to ground and have a weak + * pull-up. + * + **********************************************************************/ + +`timescale 1 ns / 100 ps + +module dtl_inv (op, in1); + output op; + input in1; + not (strong0, pull1) #16 not1 (op, in1); +endmodule // dtl_inv + +module sr_latch (p, n); + + inout p; + inout n; + + dtl_inv u_p1 + ( .in1 ( n ) , + .op ( p ) ); + + dtl_inv u_n1 + ( .in1 ( p ) , + .op ( n ) ); + +endmodule // sr_latch + +module dut (pp, nn); + + inout [1:0] pp; + inout [1:0] nn; + + sr_latch u_l1 (pp[0], nn[0]); + +endmodule // dut + + +module top; + + reg pass; + reg x; + + wire [1:0] pp; + wire [1:0] nn; + + dtl_inv u_pp0(.in1(~x), .op(pp[0])); + dtl_inv u_nn0(.in1( x), .op(nn[0])); + + dut u_d1 (pp, nn); + + initial begin + pass = 1'b1; + x <= 2'd0; + + #100; + + $display("Expect: x = 0, pp = z0, nn = z1 p=0, n=1"); + $display("Actual: x = %b, pp = %b, nn = %b p=%b, n=%b", x, pp, nn, + u_d1.u_l1.p, u_d1.u_l1.n); + + if (x !== 1'b0) begin + $display("Failed: expected x to be 0, got %b", x); + pass = 1'b0; + end + if (pp !== 2'bz0) begin + $display("Failed: expected pp to be z0, got %b", pp); + pass = 1'b0; + end + if (nn !== 2'bz1) begin + $display("Failed: expected nn to be z0, got %b", nn); + pass = 1'b0; + end + if (u_d1.u_l1.p !== 1'b0) begin + $display("Failed: expected p to be 0, got %b", u_d1.u_l1.p); + pass = 1'b0; + end + if (u_d1.u_l1.n !== 1'b1) begin + $display("Failed: expected n to be 1, got %b", u_d1.u_l1.n); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + + end + +endmodule // top diff --git a/ivtest/ivltests/pr3462145.v b/ivtest/ivltests/pr3462145.v new file mode 100644 index 000000000..ef69a73f0 --- /dev/null +++ b/ivtest/ivltests/pr3462145.v @@ -0,0 +1,13 @@ +module tb; + + reg [1:0] i; + reg [3:0] x[0:2]; + + initial begin + x[1] = 1; + i = 1; + x[i++] += 2; + if (x[1] != 3) $display("FAILED: got %b", x[1]); + else $display("PASSED"); + end +endmodule // tb diff --git a/ivtest/ivltests/pr3465541.v b/ivtest/ivltests/pr3465541.v new file mode 100644 index 000000000..54a851ce2 --- /dev/null +++ b/ivtest/ivltests/pr3465541.v @@ -0,0 +1,81 @@ +/*********************************************************************** + * + * Copyright (C) 2011 Adrian Wise + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + *********************************************************************** + * + * This is a testbench exercising gate-level modelling of DTL gates, + * distilled down (as a test-case) from a much larger design. + * The gates can only pull down strongly to ground and have a weak + * pull-up. + * + * This illustrates a problem in the git master branch as of 24 December + * 2011, where a gate that does not pull-up strongly cannot drive a bit + * of a bus (to either logic level), but can drive a single-bit wire + * correctly. + * + * This is an extended version of the test case provided with the + * bug report, to cover part selects with a non-zero base, and to + * make the error checking a bit more robust. + **********************************************************************/ + +`timescale 1 ns / 100 ps + +module dtl_inv (op, in1); + output op; + input in1; + not (strong0, pull1) #16 not1 (op, in1); +endmodule // dtl_inv + +module top; + + reg d; + + wire w; + wire [1:0] b; + + reg pass; + + dtl_inv u_1 (.op(w), .in1(d)); + dtl_inv u_2 (.op(b[0]), .in1(d)); + dtl_inv u_3 (.op(b[1]), .in1(b[0])); + + + initial begin + + pass = 1'b1; + + d = 1'b0; + # 100; + + if ((w !== 1'b1) || (b[0] !== 1'b1) || (b[1] !== 1'b0)) begin + $display("Failed (w !== b[0]): d = %b, w = %b, b = %b", d, w, b); + pass = 1'b0; + end + + d = 1'b1; + # 100; + if ((w !== 1'b0) || (b[0] !== 1'b0) || (b[1] !== 1'b1)) begin + $display("Failed (w !== b[0]): d = %b, w = %b, b = %b", d, w, b); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + +endmodule // top diff --git a/ivtest/ivltests/pr3477107.v b/ivtest/ivltests/pr3477107.v new file mode 100644 index 000000000..21309db4c --- /dev/null +++ b/ivtest/ivltests/pr3477107.v @@ -0,0 +1,44 @@ +`begin_keywords "1364-2005" +`timescale 1ns/1ns +module test; + + reg fail = 0; + + task check; + input [10*8:1] expect; + reg [10*8:1] s; + begin + $swrite(s, "Time %t", $time); + $write("%s", s); + if (s === expect) + $display(""); + else + begin + $display(" != %s", expect); + fail = 1; + end + end + endtask + + + initial + begin + $display("Test display formatting of time values"); + $timeformat(-6, 3, " us", 20); + + fork + #0000 check(" 0.000 us"); + #0001 check(" 0.001 us"); + #0010 check(" 0.010 us"); + #0011 check(" 0.011 us"); + #0100 check(" 0.100 us"); + #0101 check(" 0.101 us"); + #1000 check(" 1.000 us"); + #1001 check(" 1.001 us"); + join + + $display("%s", fail? "FAILED" : "PASSED"); + end + +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr3499807.v b/ivtest/ivltests/pr3499807.v new file mode 100644 index 000000000..3bd90b4ee --- /dev/null +++ b/ivtest/ivltests/pr3499807.v @@ -0,0 +1,16 @@ +module pr3499807(); + +supply0 gnd; +wire net1; +wire net2; + +tranif0 #(100) sw1(gnd, net1, gnd); +tranif0 #(200) sw2(gnd, net2, gnd); + +initial begin + $monitor($time,, gnd,, net1,, net2); + #300; + $finish(0); +end + +endmodule diff --git a/ivtest/ivltests/pr3515542.v b/ivtest/ivltests/pr3515542.v new file mode 100644 index 000000000..237b942bf --- /dev/null +++ b/ivtest/ivltests/pr3515542.v @@ -0,0 +1,12 @@ +module top; + integer a; + + initial begin + a = 15'1; + a = 15'0; + a = 15'x; + a = 15'X; + a = 15'z; + a = 15'Z; + end +endmodule diff --git a/ivtest/ivltests/pr3522653.v b/ivtest/ivltests/pr3522653.v new file mode 100644 index 000000000..1af91455d --- /dev/null +++ b/ivtest/ivltests/pr3522653.v @@ -0,0 +1,14 @@ +module test(); + +initial begin + $display("%b", 'h00000001); + $display("%d", 'h00000001); + $display("%b", 'hffffffff); + $display("%d", 'hffffffff); + $display("%b", 'sh00000001); + $display("%d", 'sh00000001); + $display("%b", 'shffffffff); + $display("%d", 'shffffffff); +end + +endmodule diff --git a/ivtest/ivltests/pr3527022.v b/ivtest/ivltests/pr3527022.v new file mode 100644 index 000000000..ab044368e --- /dev/null +++ b/ivtest/ivltests/pr3527022.v @@ -0,0 +1,82 @@ +module test #( + parameter integer i1 = 1.0, i2 = 2, + parameter [7:0] v1 = 3.0, v2 = 4, + parameter real r1 = 5.0, r2 = 6, + parameter u1 = 7.0, u2 = 8'd8 +)( +); + +parameter integer i3 = 1.0, i4 = 2; +parameter [7:0] v3 = 3.0, v4 = 4; +parameter real r3 = 5.0, r4 = 6; +parameter u3 = 7.0, u4 = 8'd8; + +localparam integer i5 = 1.0, i6 = 2; +localparam [7:0] v5 = 3.0, v6 = 4; +localparam real r5 = 5.0, r6 = 6; +localparam u5 = 7.0, u6 = 8'd8; + +reg failed = 0; + +initial begin + $display("%b", i1); + $display("%b", i2); + $display("%b", v1); + $display("%b", v2); + $display("%f", r1); + $display("%f", r2); + $display("%f", u1); + $display("%b", u2); + + if (i1 !== 32'd1) failed = 1; + if (i2 !== 32'd2) failed = 1; + if (v1 !== 8'd3) failed = 1; + if (v2 !== 8'd4) failed = 1; + if (r1 != 5.0) failed = 1; + if (r2 != 6.0) failed = 1; + if (u1 != 7.0) failed = 1; + if (u2 !== 8'd8) failed = 1; + + $display("%b", i3); + $display("%b", i4); + $display("%b", v3); + $display("%b", v4); + $display("%f", r3); + $display("%f", r4); + $display("%f", u3); + $display("%b", u4); + + if (i3 !== 32'd1) failed = 1; + if (i4 !== 32'd2) failed = 1; + if (v3 !== 8'd3) failed = 1; + if (v4 !== 8'd4) failed = 1; + if (r3 != 5.0) failed = 1; + if (r4 != 6.0) failed = 1; + if (u3 != 7.0) failed = 1; + if (u4 !== 8'd8) failed = 1; + + $display("%b", i5); + $display("%b", i6); + $display("%b", v5); + $display("%b", v6); + $display("%f", r5); + $display("%f", r6); + $display("%f", u5); + $display("%b", u6); + + if (i5 !== 32'd1) failed = 1; + if (i6 !== 32'd2) failed = 1; + if (v5 !== 8'd3) failed = 1; + if (v6 !== 8'd4) failed = 1; + if (r5 != 5.0) failed = 1; + if (r6 != 6.0) failed = 1; + if (u5 != 7.0) failed = 1; + if (u6 !== 8'd8) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr3527694.v b/ivtest/ivltests/pr3527694.v new file mode 100644 index 000000000..c3ef56466 --- /dev/null +++ b/ivtest/ivltests/pr3527694.v @@ -0,0 +1,144 @@ +`timescale 1ns / 1ps + +module top; + +reg sys_clk; +reg sys_reset; + +integer cnt, lastcnt; + +initial begin + sys_clk = 1'b1; + sys_reset = 1'b1; + cnt = 0; + lastcnt = 100; + while(cnt < lastcnt) begin + #5; + sys_clk = 1'b0; + #5; + sys_clk = 1'b1; + if(cnt > 10) begin + sys_reset = 1'b0; + end + cnt = cnt + 1; + end + #20; + $dumpflush; + $finish(2); + $stop(2); +end + +test1 #( +.WIDTH1(18), +.WIDTH2(18) +) test1 ( + .sys_clk(sys_clk), + .sys_rst(sys_reset) +); + +test2 #( + .WIDTH1(18), + .WIDTH2(18) +) test2_top ( + .sys_clk(sys_clk), + .sys_rst(sys_reset) +); + +endmodule + +module test1 +#( +parameter WIDTH1 = 1, +parameter WIDTH2 = 2 +) ( +input sys_clk, +input sys_rst +); + +wire [15:0] w1 = WIDTH1; +wire [15:0] w2 = WIDTH2; + +generate +if(WIDTH1 != 1) begin: not1 + +test2 #( + .WIDTH1(18), + .WIDTH2(18) +) test2_0 ( + .sys_clk(sys_clk), + .sys_rst(sys_rst) +); + +test2 #( + .WIDTH1(18), + .WIDTH2(18) +) test2_1 ( + .sys_clk(sys_clk), + .sys_rst(sys_rst) +); + +end +endgenerate + +initial begin + #40; + $finish(0); +end + +endmodule + +module test2 +#( +parameter WIDTH1 = 3, +parameter WIDTH2 = 4 +) ( +input sys_clk, +input sys_rst +); + +localparam big_width = (WIDTH1 >= WIDTH2) ? WIDTH1 : WIDTH2; + +initial begin + $display("%m big_width: %h", big_width); +end + +wire [15:0] w1 = WIDTH1; +wire [15:0] w2 = WIDTH2; +wire [15:0] bigw = big_width; + +wire [31:0] out_data_a, out_data_b; +test3 #( + .WIDTH1(WIDTH1), + .WIDTH2(WIDTH2) +) test3_0 ( + .sys_clk(sys_clk), + .sys_rst(sys_rst) +); + +test3 test3_1 ( + .sys_clk(sys_clk), + .sys_rst(sys_rst) +); + defparam test3_1.WIDTH1 = WIDTH1; + defparam test3_1.WIDTH2 = WIDTH2; + +endmodule + +module test3 (sys_clk, sys_rst); +input sys_clk; +input sys_rst; + +parameter WIDTH1 = 0; +parameter WIDTH2 = 0; + +localparam big_width = (WIDTH1 >= WIDTH2) ? WIDTH1 : WIDTH2; + +wire [31:0] wide = big_width; +wire [31:0] width1 = WIDTH1; +wire [31:0] width2 = WIDTH2; +initial begin + $strobe("%m wide: %h, width1:%h, width2:%h", wide, width1, width2); +end + + +endmodule diff --git a/ivtest/ivltests/pr3534333.v b/ivtest/ivltests/pr3534333.v new file mode 100644 index 000000000..fd1cbb980 --- /dev/null +++ b/ivtest/ivltests/pr3534333.v @@ -0,0 +1,38 @@ +module pr3534333(); + +/* Check compiler accepts null statements in blocks */ + +integer count = 0; + +initial begin +end + +initial begin + (* my_attr = 0 *) ; +end + +initial begin + (* my_attr = 0 *) ; + #1 count = count + 1; +end + +initial begin + #2 count = count + 1; + (* my_attr = 0 *) ; +end + +initial begin + ; + #3 count = count + 1; + ; +end + +initial begin + #4;; + if (count === 3) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/pr3534422.v b/ivtest/ivltests/pr3534422.v new file mode 100644 index 000000000..225983519 --- /dev/null +++ b/ivtest/ivltests/pr3534422.v @@ -0,0 +1,25 @@ +module bug(); + +reg [3:0] flags = 4'b0000; + +generate + genvar i; + + for (i = 1; i < 4; i = i + 1) begin:loop + localparam j = i; + + if (j > 0) begin + initial #1 flags[j] = 1'b1; + end + end +endgenerate + +initial begin + #2 $display("flags = %b", flags); + if (flags === 4'b1110) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/pr3539372.v b/ivtest/ivltests/pr3539372.v new file mode 100644 index 000000000..0010c19ec --- /dev/null +++ b/ivtest/ivltests/pr3539372.v @@ -0,0 +1,9 @@ +module test; + parameter x = "String with escaped backslash at end \\"; + initial +`ifdef __ICARUS__ + $display("PASSED"); +`else + $display("Not Icarus\nPASSED"); +`endif +endmodule diff --git a/ivtest/ivltests/pr3549328.v b/ivtest/ivltests/pr3549328.v new file mode 100644 index 000000000..18bfea9a1 --- /dev/null +++ b/ivtest/ivltests/pr3549328.v @@ -0,0 +1,16 @@ +// Check compiler can handle zero widths in indexed +// part selects. +module bug(); + +localparam off1 = 1; +localparam wid1 = 0; + +integer off2 = 1; +integer wid2 = 0; + +wire [7:0] vector = 8'h55; + +wire part1 = |vector[off1 +: wid1]; +wire part2 = |vector[off2 +: wid2]; + +endmodule diff --git a/ivtest/ivltests/pr355.v b/ivtest/ivltests/pr355.v new file mode 100644 index 000000000..f5703e124 --- /dev/null +++ b/ivtest/ivltests/pr355.v @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2001 Ted Bullen + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// This code is released to Steve Williams for the Icarus Verilog compiler +// It can be used as desired ! + + +// DEFINES +`define NRBITS 4 // Number of bits in each operand + +// TOP MODULE +module testFunction(); + + // SIGNAL DECLARATIONS + reg clock; + reg [`NRBITS-1:0] a_in; + integer a_integer; + integer myint; + reg [`NRBITS:0] cycle_count; // Counts valid clock cycles + + // Initialize inputs + initial begin + clock = 1; + cycle_count = 0; + # (16*200+15) $display("PASSED"); + $finish; + end + + // Generate the clock + always #100 clock = ~clock; + + // Simulate + always @(negedge clock) begin + cycle_count = cycle_count + 1; + + // Create inputs between 0 and all 1s + a_in = cycle_count[`NRBITS-1:0]; + myint = a_in; + $display("a_in = %d, myint = %d", a_in, myint); + + // Convert the unsigned numbers to signed numbers + a_integer = short_to_int(a_in); + + + if (myint !== a_integer) + begin + $display("ERROR ! %d !== %d", myint, a_integer); + $stop; + end + end + + // Function to convert a reg of `NRBITS + // bits to a signed integer + function integer short_to_int; + + input [`NRBITS-1:0] x; + begin + short_to_int = x; + $display("\tshort_to_int(%b) = %b", x, short_to_int); + end + endfunction +endmodule diff --git a/ivtest/ivltests/pr3557493.v b/ivtest/ivltests/pr3557493.v new file mode 100644 index 000000000..843e50d91 --- /dev/null +++ b/ivtest/ivltests/pr3557493.v @@ -0,0 +1,45 @@ +module m1(); +parameter p = 0; +endmodule + +module m2(); + +generate + genvar i; + for (i = 0; i < 2; i = i + 1) begin : Loop1 + m1 m(); + defparam m.p = 1 + i; + end + for (i = 2; i < 4; i = i + 1) begin : Loop2 + m1 m(); + defparam Loop2[i].m.p = 1 + i; + end + for (i = 4; i < 6; i = i + 1) begin : Loop3 + m1 m(); + defparam m2.Loop3[i].m.p = 1 + i; + end +endgenerate + +reg failed = 0; + +initial begin + $display("Loop1[0].m.p = %0d", Loop1[0].m.p); + if (Loop1[0].m.p !== 1) failed = 1; + $display("Loop1[1].m.p = %0d", Loop1[1].m.p); + if (Loop1[1].m.p !== 2) failed = 1; + $display("Loop2[2].m.p = %0d", Loop2[2].m.p); + if (Loop2[2].m.p !== 3) failed = 1; + $display("Loop2[3].m.p = %0d", Loop2[3].m.p); + if (Loop2[3].m.p !== 4) failed = 1; + $display("Loop3[4].m.p = %0d", Loop3[4].m.p); + if (Loop3[4].m.p !== 5) failed = 1; + $display("Loop3[5].m.p = %0d", Loop3[5].m.p); + if (Loop3[5].m.p !== 6) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr3561350.v b/ivtest/ivltests/pr3561350.v new file mode 100644 index 000000000..5e10d9af9 --- /dev/null +++ b/ivtest/ivltests/pr3561350.v @@ -0,0 +1,17 @@ +module pr3561350(); + +reg [31:0] source; +reg [31:0] result; + +initial begin + source = 10; + // the following expression results in a compiler internal error + result = (source * 2) + 2 + 3 + 4; + // check we get the expected result when the bug has been fixed + if (result === 29) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/pr3563412.v b/ivtest/ivltests/pr3563412.v new file mode 100644 index 000000000..71daf959e --- /dev/null +++ b/ivtest/ivltests/pr3563412.v @@ -0,0 +1,5 @@ +module test; + initial begin + $display("Error: \"FloatTest.bsv\", line 234, column 24: (R0001)\n Mutually exclusive rules (from the ME sets [RL_action_l234c24] and\n [RL_action_l235c24, RL_action_l236c24, RL_action_l237c24, RL_action_l238c24,\n RL_action_l239c24, RL_action_l240c24, RL_action_l241c24, RL_action_l242c24,\n RL_action_l243c24, RL_action_l244c24, RL_action_l245c24, RL_action_l246c24,\n RL_action_l247c24, RL_action_l248c24, RL_action_l249c24, RL_action_l250c24,\n RL_action_l251c24, RL_action_l252c24, RL_action_l253c24, RL_action_l255c24,\n RL_action_l256c24, RL_action_l257c24, RL_action_l258c24, RL_action_l259c24,\n RL_action_l260c24, RL_action_l261c24, RL_action_l262c24, RL_action_l263c24,\n RL_action_l264c24, RL_action_l265c24, RL_action_l266c24, RL_action_l267c24,\n RL_action_l268c24, RL_action_l269c24, RL_action_l270c24, RL_action_l271c24,\n RL_action_l272c24, RL_action_l273c24, RL_action_l274c24, RL_action_l276c24,\n RL_action_l277c24, RL_action_l278c24, RL_action_l279c24, RL_action_l280c24,\n RL_action_l281c24, RL_action_l282c24, RL_action_l283c24, RL_action_l284c24,\n RL_action_l285c24, RL_action_l286c24, RL_action_l287c24, RL_action_l288c24,\n RL_action_l289c24, RL_action_l290c24, RL_action_l291c24, RL_action_l292c24,\n RL_action_l293c24, RL_action_l294c24, RL_action_l295c24, RL_action_l297c24,\n RL_action_l298c24, RL_action_l299c24, RL_action_l300c24, RL_action_l301c24,\n RL_action_l302c24, RL_action_l303c24, RL_action_l304c24, RL_action_l305c24,\n RL_action_l306c24, RL_action_l307c24, RL_action_l308c24, RL_action_l309c24,\n RL_action_l310c24, RL_action_l311c24, RL_action_l312c24, RL_action_l313c24,\n RL_action_l314c24, RL_action_l315c24, RL_action_l316c24, RL_action_l318c24,\n RL_action_l319c24, RL_action_l320c24, RL_action_l321c24, RL_action_l322c24,\n RL_action_l323c24, RL_action_l324c24, RL_action_l326c24, RL_action_l327c24,\n RL_action_l328c24, RL_action_l329c24, RL_action_l330c24, RL_action_l331c24,\n RL_action_l332c24, RL_action_l333c24, RL_action_l334c24, RL_action_l335c24,\n RL_action_l336c24, RL_action_l337c24, RL_action_l338c24, RL_action_l339c24,\n RL_action_l340c24, RL_action_l341c24, RL_action_l342c24, RL_action_l343c24,\n RL_action_l344c24, RL_action_l345c24, RL_action_l348c18, RL_action_l353c22,\n RL_action_l354c22, RL_action_l355c22, RL_action_l356c22, RL_action_l357c22,\n RL_action_l358c22, RL_action_l359c22, RL_action_l360c22, RL_action_l361c22,\n RL_action_l362c22, RL_action_l363c22, RL_action_l364c22, RL_action_l365c22,\n RL_action_l366c22, RL_action_l367c22, RL_action_l368c22, RL_action_l369c22,\n RL_action_l370c22, RL_action_l371c22, RL_action_l372c22, RL_action_l374c22,\n RL_action_l376c22, RL_action_l377c22, RL_action_l378c22, RL_action_l379c22,\n RL_action_l381c22, RL_action_l383c22, RL_action_l384c22, RL_action_l386c22,\n RL_action_l387c22, RL_action_l390c18, RL_action_l395c23, RL_action_l396c23,\n RL_action_l398c23, RL_action_l399c23, RL_action_l400c23, RL_action_l401c23,\n RL_action_l402c23, RL_action_l403c23, RL_action_l404c23, RL_action_l405c23,\n RL_action_l406c23, RL_action_l407c23, RL_action_l408c23, RL_action_l409c23,\n RL_action_l410c23, RL_action_l411c23, RL_action_l412c23, RL_action_l413c23,\n RL_action_l414c23, RL_action_l415c23, RL_action_l416c23, RL_action_l417c23,\n RL_action_l419c23, RL_action_l420c23, RL_action_l421c23, RL_action_l422c23,\n RL_action_l423c23, RL_action_l424c23, RL_action_l425c23, RL_action_l426c23,\n RL_action_l427c23, RL_action_l428c23, RL_action_l429c23, RL_action_l430c23,\n RL_action_l431c23, RL_action_l432c23, RL_action_l433c23, RL_action_l434c23,\n RL_action_l435c23, RL_action_l436c23, RL_action_l437c23, RL_action_l438c23,\n RL_action_l441c18, RL_action_l446c28, RL_action_l447c28, RL_action_l448c28,\n RL_action_l449c28, RL_action_l450c28, RL_action_l451c28, RL_action_l452c28,\n RL_action_l453c28, RL_action_l455c28, RL_action_l456c28, RL_action_l457c28,\n RL_action_l458c28, RL_action_l459c28, RL_action_l460c28, RL_action_l461c28,\n RL_action_l462c28, RL_action_l463c28, RL_action_l464c28, RL_action_l465c28,\n RL_action_l466c28, RL_action_l467c28, RL_action_l468c28, RL_action_l469c28,\n RL_action_l470c28, RL_action_l471c28, RL_action_l472c28, RL_action_l473c28,\n RL_action_l474c28, RL_action_l475c28, RL_action_l476c28, RL_action_l478c28,\n RL_action_l479c28, RL_action_l481c28, RL_action_l484c18, RL_action_l489c21,\n RL_action_l490c21, RL_action_l491c21, RL_action_l492c21, RL_action_l493c21,\n RL_action_l494c21, RL_action_l495c21, RL_action_l496c21, RL_action_l497c21,\n RL_action_l498c21, RL_action_l499c21, RL_action_l500c21, RL_action_l501c21,\n RL_action_l502c21, RL_action_l503c21, RL_action_l504c21, RL_action_l505c21,\n RL_action_l506c21, RL_action_l507c21, RL_action_l508c21, RL_action_l509c21,\n RL_action_l510c21, RL_action_l512c21, RL_action_l513c21, RL_action_l514c21,\n RL_action_l515c21, RL_action_l516c21, RL_action_l517c21, RL_action_l518c21,\n RL_action_l519c21, RL_action_l520c21, RL_action_l521c21, RL_action_l522c21,\n RL_action_l523c21, RL_action_l524c21, RL_action_l525c21, RL_action_l526c21,\n RL_action_l527c21, RL_action_l528c21, RL_action_l529c21, RL_action_l530c21,\n RL_action_l531c21, RL_action_l533c26, RL_action_l534c26, RL_action_l535c26,\n RL_action_l536c26, RL_action_l537c26, RL_action_l538c26, RL_action_l539c26,\n RL_action_l540c26, RL_action_l542c26, RL_action_l543c26, RL_action_l544c26,\n RL_action_l545c26, RL_action_l546c26, RL_action_l547c26, RL_action_l548c26,\n RL_action_l549c26, RL_action_l550c26, RL_action_l551c26, RL_action_l552c26,\n RL_action_l553c26, RL_action_l554c26, RL_action_l555c26, RL_action_l556c26,\n RL_action_l557c26, RL_action_l558c26, RL_action_l559c26, RL_action_l560c26,\n RL_action_l561c26, RL_action_l562c26, RL_action_l563c26, RL_action_l565c26,\n RL_action_l566c26, RL_action_l568c26, RL_action_l570c21, RL_action_l572c21,\n RL_action_l574c26, RL_action_l576c26, RL_action_l577c26, RL_action_l579c26,\n RL_action_l582c18, RL_action_l587c28, RL_action_l588c28, RL_action_l589c28,\n RL_action_l590c28, RL_action_l591c28, RL_action_l592c28, RL_action_l593c28,\n RL_action_l594c28, RL_action_l595c28, RL_action_l596c28, RL_action_l597c28,\n RL_action_l598c28, RL_action_l599c28, RL_action_l600c28, RL_action_l601c28,\n RL_action_l602c28, RL_action_l603c28, RL_action_l604c28, RL_action_l605c28,\n RL_action_l606c28, RL_action_l607c28, RL_action_l609c28, RL_action_l610c28,\n RL_action_l611c28, RL_action_l613c28, RL_action_l614c28, RL_action_l615c28,\n RL_action_l616c28, RL_action_l617c28, RL_action_l618c28, RL_action_l619c28,\n RL_action_l621c28, RL_action_l622c28, RL_action_l623c28, RL_action_l624c28,\n RL_action_l625c28, RL_action_l626c28, RL_action_l627c28, RL_action_l628c28,\n RL_action_l629c28, RL_action_l630c28, RL_action_l631c28, RL_action_l632c28,\n RL_action_l633c28, RL_action_l634c28, RL_action_l635c28, RL_action_l636c28,\n RL_action_l637c28, RL_action_l638c28, RL_action_l639c28, RL_action_l645c18,\n RL_action_l647c7] ) fired in the same clock cycle.\nPASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr3571573.v b/ivtest/ivltests/pr3571573.v new file mode 100644 index 000000000..d829cd30c --- /dev/null +++ b/ivtest/ivltests/pr3571573.v @@ -0,0 +1,23 @@ +module pr3571573; + +wire [6:1] top_io; + +data_test dut(.io(top_io)); + +initial begin + #1 $display("%b", top_io); +end + +endmodule + +module data_test(inout [6:1] io); + +wire [4:1] io1; +wire io2; +wire io3; + +assign io = {io3, io2, io1}; + +assign io1[3:2] = 2'b01; + +endmodule diff --git a/ivtest/ivltests/pr3576165.v b/ivtest/ivltests/pr3576165.v new file mode 100644 index 000000000..fc9b2db3b --- /dev/null +++ b/ivtest/ivltests/pr3576165.v @@ -0,0 +1,35 @@ +module top; + reg pass; + enum reg[0:0] { IDLE = 1'b0, + BUSY = 1'b1 + } state, next; + + initial begin + pass = 1'b1; + next = IDLE; + if (state !== 1'bx) begin + $display("FAILED initial state, got %b", state); + pass = 1'b0; + end + #1; + state = next; + if (state !== 1'b0) begin + $display("FAILED idle state, got %b", state); + pass = 1'b0; + end + next = BUSY; + #1; + state <= next; + if (state !== 1'b0) begin + $display("FAILED still idle state, got %b", state); + pass = 1'b0; + end + #1; + if (state !== 1'b1) begin + $display("FAILED busy state, got %b", state); + pass = 1'b0; + end + if (pass) $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr3582052.v b/ivtest/ivltests/pr3582052.v new file mode 100644 index 000000000..723a87410 --- /dev/null +++ b/ivtest/ivltests/pr3582052.v @@ -0,0 +1,65 @@ +module bug; + +reg [7:0] Data[0:3][0:15]; + +reg [7:0] Expect0; +reg [7:0] Expect1; +reg [7:0] Expect2; +reg [7:0] Expect3; + +reg [7:0] Actual0; +reg [7:0] Actual1; +reg [7:0] Actual2; +reg [7:0] Actual3; + +integer i; +integer j; + +reg Failed = 0; + +initial begin + for (i = 0; i < 4; i = i + 1) begin + for (j = 0; j < 16; j = j + 1) begin + Data[i][j] = (i << 4) + j; + end + end + // this catches the original bug + for (j = 0; j < 16; j = j + 1) begin + Expect0 = 0*16 + j; Actual0 = Data[0][j]; + Expect1 = 1*16 + j; Actual1 = Data[1][j]; + Expect2 = 2*16 + j; Actual2 = Data[2][j]; + Expect3 = 3*16 + j; Actual3 = Data[3][j]; + $display("%h %h %h %h", Actual0, Actual1, Actual2, Actual3); + if (Actual0 !== Expect0) Failed = 1; + if (Actual1 !== Expect1) Failed = 1; + if (Actual2 !== Expect2) Failed = 1; + if (Actual3 !== Expect3) Failed = 1; + end + // extended tests to check the bug fix doesn't break anything else + for (i = 0; i < 4; i = i + 1) begin + Expect0 = i*16 + 0; Actual0 = Data[i][0]; + Expect1 = i*16 + 3; Actual1 = Data[i][3]; + Expect2 = i*16 + 6; Actual2 = Data[i][6]; + Expect3 = i*16 + 9; Actual3 = Data[i][9]; + $display("%h %h %h %h", Actual0, Actual1, Actual2, Actual3); + if (Actual0 !== Expect0) Failed = 1; + if (Actual1 !== Expect1) Failed = 1; + if (Actual2 !== Expect2) Failed = 1; + if (Actual3 !== Expect3) Failed = 1; + end + Expect0 = 0*16 + 0; Actual0 = Data[0][0]; + Expect1 = 0*16 + 9; Actual1 = Data[0][9]; + Expect2 = 3*16 + 0; Actual2 = Data[3][0]; + Expect3 = 3*16 + 9; Actual3 = Data[3][9]; + $display("%h %h %h %h", Actual0, Actual1, Actual2, Actual3); + if (Actual0 !== Expect0) Failed = 1; + if (Actual1 !== Expect1) Failed = 1; + if (Actual2 !== Expect2) Failed = 1; + if (Actual3 !== Expect3) Failed = 1; + if (Failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/pr3587570.v b/ivtest/ivltests/pr3587570.v new file mode 100644 index 000000000..e16012e9d --- /dev/null +++ b/ivtest/ivltests/pr3587570.v @@ -0,0 +1,28 @@ +primitive passthrough (o, i); + input i; + output o; + table + // i : o + 1 : 1; + 0 : 0; + ? : 0; + endtable +endprimitive + +module test; + reg i; + wire o1, o1b, o2, o2b; + + initial begin + i = 1'b0; + #1; + if ((o1 !== 1'b0) && (o1b !== 1'b1) && + (o2 !== 1'b0) && (o2b !== 1'b1)) $display("FAILED"); + else $display("PASSED"); + end + + passthrough (o1, i); + passthrough (o1b, !i); + passthrough (o2, i); + passthrough (o2b, ~i); +endmodule diff --git a/ivtest/ivltests/pr3592746.v b/ivtest/ivltests/pr3592746.v new file mode 100644 index 000000000..35be628d8 --- /dev/null +++ b/ivtest/ivltests/pr3592746.v @@ -0,0 +1,31 @@ +module pr3592746(); + +reg Iteration; + +integer RepeatCount[1:0]; + +task RepeatTest; + +begin + repeat(Iteration == 1 ? 3 : 2) begin + $display("Iteration = %b", Iteration); + RepeatCount[Iteration] = RepeatCount[Iteration] + 1; + end +end + +endtask + +initial begin + RepeatCount[0] = 0; + RepeatCount[1] = 0; + Iteration = 0; + RepeatTest; + Iteration = 1; + RepeatTest; + if ((RepeatCount[0] == 2) && (RepeatCount[1] == 3)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/pr377.v b/ivtest/ivltests/pr377.v new file mode 100644 index 000000000..d80d1a48c --- /dev/null +++ b/ivtest/ivltests/pr377.v @@ -0,0 +1,19 @@ +module dummy (.B(A[2:1])); + input [2:1] A; +always @(A) + $display (A); +endmodule + +module test (); +reg [2:0] A; + +dummy dummy(A[1:0]); + +integer idx; +initial begin + for (idx = 0 ; idx <= 'h7 ; idx = idx+1) + #1 A <= idx; + + #1 $finish(0); +end +endmodule diff --git a/ivtest/ivltests/pr434.v b/ivtest/ivltests/pr434.v new file mode 100644 index 000000000..00830fd9c --- /dev/null +++ b/ivtest/ivltests/pr434.v @@ -0,0 +1,52 @@ +/* + * This tests is based on PR#434 + */ + +`define VAR1 2 +`define VAR2 5 +module mctrl( reset0, reset1, reset2, reset3, clk, por); + output reset0, reset1, reset2, reset3; + input clk,por; + + reg [7:0] cnt; + + always @ (posedge por or posedge clk) + if (por) + cnt <= 0; + else + cnt <= cnt+1; + + assign reset0 = (cnt == `VAR1); + assign reset1 = (cnt == `VAR2); + assign reset2 = (cnt == `VAR1 + `VAR2); + assign reset3 = (cnt == `VAR1 + `VAR2 + 2); + +endmodule + +`timescale 1ns/1ps + +module test(); + reg clk,por; + + wire reset0, reset1, reset2, reset3; + + mctrl m1(reset0, reset1, reset2, reset3, clk, por); + + initial + begin + clk = 0; + por = 0; + $monitor($time,, "reset0=%b, reset1=%b, reset2=%b, reset3=%b", + reset0, reset1, reset2, reset3); + #1000 $finish(0); + end + + always #15 clk = ~clk; + + + initial + begin + #10 por = 1; + #10 por = 0; + end +endmodule // test diff --git a/ivtest/ivltests/pr445.v b/ivtest/ivltests/pr445.v new file mode 100644 index 000000000..e802040a6 --- /dev/null +++ b/ivtest/ivltests/pr445.v @@ -0,0 +1,10 @@ +/* PR#445 */ +module foo (); + +initial + if (!(1'b0)) + $display("PASSED"); + else + $display("FAILED"); + +endmodule diff --git a/ivtest/ivltests/pr478.v b/ivtest/ivltests/pr478.v new file mode 100644 index 000000000..b54c140b6 --- /dev/null +++ b/ivtest/ivltests/pr478.v @@ -0,0 +1,15 @@ +/* + * This is from iverilog issue # 1313453 + * This point is that it should compile. + */ +module test `protect ( +a +); + +// Input Declarations +input a; +`endprotect + +initial $display("PASSED"); + +endmodule diff --git a/ivtest/ivltests/pr487.v b/ivtest/ivltests/pr487.v new file mode 100644 index 000000000..f225b2c08 --- /dev/null +++ b/ivtest/ivltests/pr487.v @@ -0,0 +1,17 @@ +/* + * This is the crux of PR487. + */ + +module test(); + +parameter[1:4] async_wrport = 4'b1100; +reg async_wri; +reg[1:4] async_i; + +initial begin + for(async_i=1;async_i<=4;async_i=async_i+1) begin + async_wri=async_wrport[async_i]; + $display("async_wrport[%d] --> %b", async_i, async_wri); + end +end +endmodule diff --git a/ivtest/ivltests/pr492.v b/ivtest/ivltests/pr492.v new file mode 100644 index 000000000..d6b86f106 --- /dev/null +++ b/ivtest/ivltests/pr492.v @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2002 Richard M. Myers + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + `timescale 10 ns/ 10 ns + +module top ; + + reg clk ; + reg [11:0] x_os_integ, y_os_integ; + reg [5:0] x_os, y_os; + + initial + begin + //$dumpfile("show_math.vcd"); + //$dumpvars(1, top); + clk = 1'h0 ; + x_os = 6'h01; + y_os = 6'h3f; + x_os_integ = 12'h000; + y_os_integ = 12'h000; + end + + initial + begin + #60; + forever #3 clk = ~clk ; // 16Mhz + end + + always @( posedge clk ) + begin + // Integration period set above depending on configured modem speed. + x_os_integ <= x_os_integ + {{6{x_os[5]}}, {x_os[5:0]}}; + y_os_integ <= y_os_integ + {{6{y_os[5]}}, {y_os[5:0]}}; + + $display ("%x %x", x_os_integ, y_os_integ); + end + + initial + begin + #200 $finish(0); + end + +endmodule diff --git a/ivtest/ivltests/pr498.v b/ivtest/ivltests/pr498.v new file mode 100644 index 000000000..6a943a84b --- /dev/null +++ b/ivtest/ivltests/pr498.v @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +module main; + test tt(); + defparam foo = 3; /* This should generate a warning. */ + defparam tt.foo = 4; +endmodule // main + +module test; + parameter foo = 10; + reg [foo-1:0] bar; + + initial begin + if ($bits(bar) != 4) begin + $display("FAILED -- $bits(bar) = %d", $bits(bar)); + $finish; + end + $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/pr508.v b/ivtest/ivltests/pr508.v new file mode 100644 index 000000000..2fa4e3a76 --- /dev/null +++ b/ivtest/ivltests/pr508.v @@ -0,0 +1,13 @@ +/* + * This trivial example tickled PR508, where the thread + * pointer in the event was uninitialized. This should + * in general check the case of signaling events without + * threads ever having waiting on it. + */ +module example; + event my_event; + initial -> my_event; + reg [25:0] m26; + wire [25:0] w26 = m26; + initial $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/pr509.v b/ivtest/ivltests/pr509.v new file mode 100644 index 000000000..d20a710e6 --- /dev/null +++ b/ivtest/ivltests/pr509.v @@ -0,0 +1,9 @@ +/* + * Make sure the degenerate case that a wire is linked to itself + * is handled properly. + */ +module example; + wire w; + assign w = w; + initial $display("PASSED"); +endmodule diff --git a/ivtest/ivltests/pr509b.v b/ivtest/ivltests/pr509b.v new file mode 100644 index 000000000..92fc3e798 --- /dev/null +++ b/ivtest/ivltests/pr509b.v @@ -0,0 +1,71 @@ +module whoever_wrote_this_should_be_shot ( Q, D, G ); + output Q; + input D, G; + + wire Q_int; + + assign ( pull0, pull1 ) Q_int = Q_int; + + bufif1 buf_D ( Q_int, D, G ); + buf buf_Q ( Q, Q_int ); +endmodule + +module testbench; + wire Q; + reg D, G; + + whoever_wrote_this_should_be_shot uut ( Q, D, G ); + + initial begin + D = 1'b0; + forever #5 D = ~ D; + end + + initial begin + G = 1'b0; + forever #27 G = ~ G; + end + + initial begin + $monitor( $time,,,G,,,D,,,Q ); + + // time 28: G=1, D=1, Q=1 + #28 if (Q !== 1) begin + $display("FAILED -- Q should be 1, is %b", Q); + $finish; + end + + // time 31: G=1, D=0, Q=0 + #3 if (Q !== 0) begin + $display("FAILED -- Q should be 0, is %b", Q); + $finish; + end + + // time 51: G=1, D=0, Q=0 + #20 if (Q !== 0) begin + $display("FAILED -- Q should be 0, is %b", Q); + $finish; + end + + // time 56: G=0, D=1, Q=0 + #5 if (Q !== 0) begin + $display("FAILED -- Q should be 0, is %b", Q); + $finish; + end + + // time 82: G=1, D=0, Q=0 + #26 if (Q !== 0) begin + $display("FAILED -- Q should be 0, is %b", Q); + $finish; + end + + // time 86: G=1, D=1, Q=1 + #5 if (Q !== 1) begin + $display("FAILED -- Q should be 1, is %b", Q); + $finish; + end + + #1000 $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/pr511.v b/ivtest/ivltests/pr511.v new file mode 100644 index 000000000..c518ca0ae --- /dev/null +++ b/ivtest/ivltests/pr511.v @@ -0,0 +1,296 @@ +/* + * This test is derived from bug report PR#511. Mostly what it is + * doing is checking the behavior of === and wait. + */ + +`timescale 1 ps / 1 ps + +module I54; + + initial begin + #500000 + $display( "FAILED." ); + $finish; + end + + parameter I148 = 4096; + + integer I20; + integer I57; + integer I58; + + integer I137; + + time I106; + time I95; + time I97; + + time I122; + time I142; + time I67; + time I25; + time I83; + time I128; + time I10; + time I12; + time I73; + time I159; + + reg I77; + reg I108; + reg I2; + reg I81; + reg I60; + reg I114; + reg I124; + reg I41; + + reg I151; + reg I43; + reg [1:0] I68; + reg [4*8-1:0] I138; + reg [3:0] I71; + reg [3:0] I149; + reg [3:0] I6; + reg [3:0] I76; + reg I48; + reg I61; + reg I62; + reg I49; + reg I158; + reg I85; + reg [2:0] I84; + reg [2:0] I30; + reg I94; + + wire I69; + wire I98; + + reg I115; + reg I101; + reg I14; + reg I78; + reg I131; + reg I24; + reg I52; + reg I13; + reg I132; + reg I139; + reg I107; + + wire I93; + wire [3:0] I120; + wire [3:0] I82; + wire I38; + wire I22; + wire [1:0] I46; + wire [2:0] I1; + wire [4*8-1:0] I4; + wire [3:0] I125; + wire [3:0] I36; + wire [3:0] I91; + wire [3:0] I3; + wire [3:0] I143; + wire [1:0] I72; + wire I34; + wire I150; + wire I40; + wire [1:0] I51; + + reg [1:0] I39; + reg [4-1:0] I70; + + wire I103; + wire I29; + + wire I74; + wire I144; + + reg I63; + reg I15; + reg I146; + reg I110; + reg I152; + reg I129; + reg I19; + reg I112; + reg I102; + reg I156; + reg I121; + + wire I23; + wire [3:0] I118; + wire [3:0] I86; + wire I28; + wire I65; + wire [1:0] I79; + wire [2:0] I17; + wire [4*8-1:0] I133; + wire [3:0] I27; + wire [3:0] I99; + wire [3:0] I135; + wire [3:0] I90; + wire [3:0] I35; + wire [1:0] I55; + wire I8; + wire I126; + wire I5; + wire [1:0] I140; + + reg [1:0] I116; + reg [4-1:0] I45; + + wire I105; + wire I33; + + wire I75; + wire I145; + + reg I64; + reg I16; + reg I147; + reg I111; + reg I153; + reg I130; + reg I21; + reg I113; + reg I104; + reg I157; + reg I123; + + wire I26; + wire [3:0] I119; + wire [3:0] I87; + wire I32; + wire I66; + wire [1:0] I80; + wire [2:0] I18; + wire [4*8-1:0] I134; + wire [3:0] I31; + wire [3:0] I100; + wire [3:0] I136; + wire [3:0] I92; + wire [3:0] I37; + wire [1:0] I56; + wire I9; + wire I127; + wire I7; + wire [1:0] I141; + + reg [1:0] I117; + reg [4-1:0] I47; + + wire [256:0] I59; + wire [256:0] I50; + wire [256:0] I88; + wire [256:0] I154; + wire [256:0] I89; + wire [256:0] I155; + + assign I69 = I59[I20]; + assign I98 = I50[I20]; + assign I103 = I88[I57]; + assign I29 = I154[I57]; + assign I105 = I89[I58]; + assign I33 = I155[I58]; + + wire I109 = ( ~ I94 ) & ( ~ I151 ); + wire I96 = ( ~ I94 ) & ( I151 ); + wire I42 = ( I94 ) & ( ~ I151 ); + wire I44 = ( I94 ) & ( I151 ); + + always @( I114 ) begin + I132 <= #I106 I114; + I102 <= #I95 I114; + I104 <= #I97 I114; + end + + always @( I124 ) begin + I139 <= #I106 I124; + I156 <= #I95 I124; + I157 <= #I97 I124; + end + + initial begin + I77 = 1'b0; + #0 ; + #(I142) I77 = 1'b1; + forever #(I122/2) I77 = ~ I77; + end + + initial begin + I108 = 1'b0; + #0 ; + #(I25) I108 = 1'b1; + forever #(I67/2) I108 = ~ I108; + end + + initial begin + I2 = 1'b0; + #0 ; + #(I128) I2 = 1'b1; + forever #(I83/2) I2 = ~ I2; + end + + initial begin + I81 = 1'b0; + #0 ; + #(I12) I81 = 1'b1; + forever #(I10/2) I81 = ~ I81; + end + + initial begin + I60 = 1'b0; + #0 ; + #(I159) I60 = 1'b1; + forever #(I73/2) I60 = ~ I60; + end + + initial begin + I114 = 1'b1; + #300000 ; + @( posedge I81 ) ; + @( posedge I81 ) ; + #50 I114 = 1'b0; + end + + initial begin + I124 = 1'b1; + #300000 ; + @( posedge I60 ) ; + @( posedge I60 ) ; + #50 I124 = 1'b0; + end + + initial begin : I53 + + I137 = 1600; + I20 = 40; + I57 = 0; + I58 = 80; + I106 = 150; + I95 = 300; + I97 = 0; + I151 = 1'b0; + I94 = 1'b0; + I122 = 6400; + I142 = 0; + I67 = 6270; + I25 = 0; + I83 = 6400; + I128 = 1000; + I10 = 6270; + I12 = 0; + I73 = 6400; + I159 = 1000; + + wait ( I114 === 1'b1 ); + wait ( I114 === 1'b0 ); + wait ( I124 === 1'b0 ); + + $display( "PASSED" ); + $finish; + + end + +endmodule diff --git a/ivtest/ivltests/pr513.v b/ivtest/ivltests/pr513.v new file mode 100644 index 000000000..91261d51c --- /dev/null +++ b/ivtest/ivltests/pr513.v @@ -0,0 +1,17 @@ +/* + * Derived from PR#513 + */ + +`timescale 1 ps / 1 ps + +module example; + integer fd; + + initial begin + #100 + fd = $fopen( "work/example.dump" ); + $fdisplay( fd ); + #1000 + $display( "PASSED" ); + end +endmodule diff --git a/ivtest/ivltests/pr519.v b/ivtest/ivltests/pr519.v new file mode 100644 index 000000000..e49b7827a --- /dev/null +++ b/ivtest/ivltests/pr519.v @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test is intended to be run with ``iverilog -S foo.v'', + * and tests the situation addressed by pr#519. + */ +module main; + + reg [3:0] a, b, c, t; + + (* ivl_combinational *) + always @(a, b) begin + t = a + b; + c = 4'd1 + ~t; + end + + (* ivl_synthesis_off *) + initial begin + a = 1; + for (b = 0 ; b < 4'hf ; b = b + 1) begin + #1 if (c !== -(a + b)) begin + $display("FAILED -- a=%b, b=%b, t=%b, c=%b", a, b, t, c); + $finish; + end + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/pr522.v b/ivtest/ivltests/pr522.v new file mode 100644 index 000000000..f9a5a8372 --- /dev/null +++ b/ivtest/ivltests/pr522.v @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2002 Jane Skinner + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// Icarus 0.6, snapshot 20020728 or snapshot 20010806 +// ================================================== +// -- confused by complex disables +// +// -- to run, incant +// iverilog tt.v +// vvp a.out +// +// Veriwell +// ======== +// -- OK +// +module top; + + integer loop_cntr, simple_fail, loop_fail; + reg fred, abort; + + initial begin + #1; + simple_fail = 0; + loop_fail = 0; + fred = 0; + abort = 1; + #4; + fred = 1; + #4 + if(simple_fail) $display("\n***** simple block disable FAILED *****"); + else $display("\n***** simple block disable PASSED *****"); + if(loop_fail) $display("***** complex block & loop disable FAILED *****\n"); + else $display("***** complex block & loop disable PASSED *****\n"); + $finish(0); + end + + // simple block disable + initial begin: block_name + #2; + disable block_name; + simple_fail = 1; + end + + // more complex: block disable inside for-loop + initial begin + #2; + begin: configloop + for (loop_cntr = 0; loop_cntr < 3; loop_cntr=loop_cntr+1) begin + wait (fred); + if (abort) begin + disable configloop; + end + loop_fail = 1; + end + end // configloop block + if (loop_fail) $display("\n\ttime: %0t, loop_cntr: %0d",$time,loop_cntr); + end + +endmodule diff --git a/ivtest/ivltests/pr524.v b/ivtest/ivltests/pr524.v new file mode 100644 index 000000000..ee5fc28c8 --- /dev/null +++ b/ivtest/ivltests/pr524.v @@ -0,0 +1,12 @@ +`timescale 1 ps / 1 ps + +module example; + time delay; + initial begin +// delay = 64'bx; + $display( "%T %b", $time, delay ); +// #(64'bx) + #delay + $display( "%T", $time ); + end +endmodule diff --git a/ivtest/ivltests/pr527.v b/ivtest/ivltests/pr527.v new file mode 100644 index 000000000..02dd2bbcd --- /dev/null +++ b/ivtest/ivltests/pr527.v @@ -0,0 +1,82 @@ +// Icarus 0.6 AND snapshot 20020728 +// ----------------------------- +// (1) force to nets not supported +// (2) comment the force statement and the release statement will cause +// the compiler to fail silently (no messages, no a.out) +// +// Icarus snapshot 20020817 +// ------------------------ +// Runs fine IFF the whole of a bus is set, cannot force individual bits +// (Fails with a rather incomprehensible error) +// +// To run this, incant: +// iverilog tt.v +// (adding -Wall doesn't help) +// vvp a.out (if a.out is generated!) +// +// +// Veriwell +// --------- +// Runs fine IFF the whole of a bus is set, cannot force individual bits +// & crashes if a release of an individual bit is attempted. +// +// To run this, incant: +// veridos tt.v (or use the GUI) +// + +module top (); + + reg [31:0] ii; + reg fail; + reg [1:0] a; + wire [1:0] junk = a; + wire [1:0] junkbus = a; + + initial begin + a = 2'b01; + #5; a = 2'b10; + #10; a = 2'b11; + end + + initial begin + #2; + force junk = 0; + force junkbus[0] = 0; + #10; + release junk; + #5; + release junkbus[0]; + end + + initial begin + $display(""); + $display("expecting junk,junkbus to be 1 at T=1"); + $display("then changing to 0 at T=2"); + $display("then junk is 0 from T=3 to T=11, while"); + $display("junkbus changes to 2 at T=5 and remains 2 through to T=16"); + $display("junk changes to 2 at T=12"); + $display("then 2 from T=13 to T=14"); + $display("then changing to 3 at T=15"); + $display("then 3 from T=16 on"); + $display("junkbus changes to 3 at T=17 and remains 3 from then on"); + $display(""); + for(ii = 0; ii < 20; ii = ii + 1) begin + #0; // avoid race + // junk + if((ii == 1) && (junk !== 1)) fail = 1; + if((ii > 2) && (ii < 12) && (junk !== 0)) fail = 1; + if((ii > 12) && (ii < 14) && (junk !== 2'b10)) fail = 1; + if((ii > 15) && (junk !== 2'b11)) fail = 1; + // junkbus + if((ii == 1) && (junkbus !== 2'b01)) fail = 1; + if((ii > 2) && (ii < 4) && (junkbus !== 2'b00)) fail = 1; + if((ii > 5) && (ii < 17) && (junkbus !== 2'b10)) fail = 1; + if((ii > 17) && (junkbus !== 2'b11)) fail = 1; + $display("time: %0t, a: %b, junk: %b, junkbus: %b",$time,a,junk,junkbus); + #1; + end + if(fail) $display("\n\t--------- force test failed ---------\n"); + else $display("\n\t--------- force test passed ---------\n"); + end + +endmodule diff --git a/ivtest/ivltests/pr528.v b/ivtest/ivltests/pr528.v new file mode 100644 index 000000000..6c674985e --- /dev/null +++ b/ivtest/ivltests/pr528.v @@ -0,0 +1,15 @@ +`timescale 1 ps / 1 ps + +module tester; + wire clko1, clko2; + reg clk; + + assign #50 clko1 = clk & 1'b1; + assign #50 clko2 = clk; + + initial clk = 1'b0; + always #5000 clk = ~ clk; + + initial $monitor( "%T %b %b %b", $time, clk, clko1, clko2 ); + initial #50001 $finish(0); +endmodule diff --git a/ivtest/ivltests/pr528b.v b/ivtest/ivltests/pr528b.v new file mode 100644 index 000000000..042ff9326 --- /dev/null +++ b/ivtest/ivltests/pr528b.v @@ -0,0 +1,44 @@ +`timescale 1 ps / 1 ps + +module tester; + wire clko1, clko2; + reg clk1, clk2, f1, f2; + + ckmux uut ( clko1, clk1, clk2, f1, f2 ); + + assign #50 clko2 = clk1; + + initial begin + f1 = 1'b0; + f2 = 1'b1; + end + + initial begin + clk1 = 1'b0; + forever #5000 clk1 = ~ clk1; + end + + initial begin + clk2 = 1'b0; + forever #5100 clk2 = ~ clk2; + end + + initial $monitor( "%T %b %b %b", $time, clk1, clko1, clko2 ); + initial #50001 $finish(0); +endmodule + +module ckmux ( clko1, clk1, clk2, f1, f2 ); + output clko1; + input clk1, clk2, f1, f2; + + reg dclk1ff; + wire dclk1; + + initial begin + dclk1ff = 1'b0; + forever @( negedge clk1 ) dclk1ff <= #50 ~ dclk1ff; + end + + assign #50 dclk1 = f2 ? dclk1ff : clk2; + assign #50 clko1 = f1 ? dclk1 : clk1; +endmodule diff --git a/ivtest/ivltests/pr529.v b/ivtest/ivltests/pr529.v new file mode 100644 index 000000000..494eb3661 --- /dev/null +++ b/ivtest/ivltests/pr529.v @@ -0,0 +1,150 @@ +`begin_keywords "1364-2005" +// -- test force/release of: +// a wire assigned to a reg +// a wire with no assignment +// a whole bus (assigned to a reg), +// a single bit of a bus (assigned to a reg) +// -- make sure the force/release is passed into the hierarchy +// +// -- run with +// iverilog -Wall tt.v +// vvp a.out +// -- to see debug display statements, use +// iverilog -Wall -DDISPLAY tt.v +// +module top (); + + reg [31:0] ii; + reg bitfail, bitnafail, busfail, busbitfail; + reg a; + reg [1:0] b; + wire bit = a; + wire bitna; + wire [1:0] bus = b; + wire [1:0] ibus = b; + wire subfail, subfailna; + + // call in a lower level module + subtop U1 ( + .subbit(bit), + .subbus(bus), + .subfail(subfail) + ); + subtop U2 ( + .subbit(bitna), + .subbus(bus), + .subfail(subfailna) + ); + + initial begin + a = 1'b1; + b = 2'b01; + #5; b = 2'b10; + #10; b = 2'b11; + end + + initial begin + #2; + force bit = 0; + force bitna = 0; + force bus = 0; + //$display("\n ****** force/release to ibus[0] commented; expect bit[0] failure ******* "); + force ibus[0] = 0; + #10; + release bit; + force bitna = 1; + release bus; + #5; + release ibus[0]; + end + + initial begin + bitfail = 0; bitnafail = 0; busfail = 0; busbitfail = 0; + `ifdef DISPLAY + $display(""); + $display("expecting bit, bus,ibus to be 1 at T=1"); + $display("then changing to 0 at T=2"); + $display("then bit and bus are 0 from T=3 to T=11, while"); + $display("ibus changes to 2 at T=5 and remains 2 through to T=16"); + $display("bit changes to 1 at T=12 and remains 1 from then on."); + $display("bus changes to 2 at T=12"); + $display("then 2 from T=13 to T=14"); + $display("then changing to 3 at T=15"); + $display("then 3 from T=16 on"); + $display("ibus changes to 3 at T=17 and remains 3 from then on"); + $display(""); + `endif + for(ii = 0; ii < 20; ii = ii + 1) begin + // bit + if((ii == 1) && (bit !== 1)) bitfail = 1; + if((ii > 2) && (ii < 12) && (bit !== 0)) bitfail = 1; + if((ii > 12) && (bit !== 1)) bitfail = 1; + // bitna + if((ii == 1) && (bitna !== 1'bz)) bitnafail = 1; + if((ii > 2) && (ii < 12) && (bitna !== 0)) bitnafail = 1; + if((ii > 12) && (bitna !== 1)) bitnafail = 1; + // bus + if((ii == 1) && (bus !== 1)) busfail = 1; + if((ii > 2) && (ii < 12) && (bus !== 0)) busfail = 1; + if((ii > 12) && (ii < 14) && (bus !== 2'b10)) busfail = 1; + if((ii > 15) && (bus !== 2'b11)) busfail = 1; + // ibus + if((ii == 1) && (ibus !== 2'b01)) busbitfail = 1; + if((ii > 2) && (ii < 4) && (ibus !== 2'b00)) busbitfail = 1; + if((ii > 5) && (ii < 17) && (ibus !== 2'b10)) busbitfail = 1; + if((ii > 17) && (ibus !== 2'b11)) busbitfail = 1; + `ifdef DISPLAY + $display("time: %0t, a: %b, bit: %b, bitna %b, b: %b, bus: %b, ibus: %b",$time,a,bit,bitna,b,bus,ibus); + `endif + #1; + end + if(bitfail || bitnafail || busfail || busbitfail || subfail || subfailna) begin + $display("\n\t--------- force test failed ---------"); + if(bitfail) $display("force to single wire assigned to a reg failed"); + if(bitnafail) $display("force to single unassigned wire failed"); + if(busfail) $display("force to whole of 2-bit bus failed"); + if(busbitfail) $display("force to bit[0] of 2-bit bus failed"); + if(!bitfail && !bitnafail && !busfail && !busbitfail) begin + if(subfail) $display("force did not affect U1 hierarchy"); + if(subfailna) $display("force did not affect U2 hierarchy"); + end + $display("\n"); + + end else $display("PASSED"); + end + +endmodule + +module subtop( + subbit, + subbus, + subfail + ); + + input subbit; + input [1:0] subbus; + output subfail; + + reg subfail; + reg [31:0] ii; + + initial begin + subfail = 0; + for(ii = 0; ii < 20; ii = ii + 1) begin + // subbit + if((ii == 1) && (subbit !== 1) && (subbit !== 1'bz)) subfail = 1; + if((ii > 2) && (ii < 12) && (subbit !== 0)) subfail = 1; + if((ii > 12) && (subbit !== 1)) subfail = 1; + // subbus + if((ii == 1) && (subbus !== 1)) subfail = 1; + if((ii > 2) && (ii < 12) && (subbus !== 0)) subfail = 1; + if((ii > 12) && (ii < 14) && (subbus !== 2'b10)) subfail = 1; + if((ii > 15) && (subbus !== 2'b11)) subfail = 1; + `ifdef DISPLAY + $display("\t\t\t\t\ttime: %0t, subbit: %b, subbus: %b",$time,subbit,subbus); + `endif + #1; + end + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/pr530a.v b/ivtest/ivltests/pr530a.v new file mode 100644 index 000000000..01d091502 --- /dev/null +++ b/ivtest/ivltests/pr530a.v @@ -0,0 +1,12 @@ +//`timescale 1ns/1ps +module top; + + initial begin + $timeformat(-9,6,"ns",20); + $display("here"); + $display("in top, time: %t",$time); + + $finish(0); + end + +endmodule diff --git a/ivtest/ivltests/pr530b.v b/ivtest/ivltests/pr530b.v new file mode 100644 index 000000000..1365eb61c --- /dev/null +++ b/ivtest/ivltests/pr530b.v @@ -0,0 +1,12 @@ +`timescale 1ns/1ns +module top; + + initial begin + $timeformat(-9,6,"ns",20); + $display("here"); + $display("in top, time: %t",$time); + + $finish(0); + end + +endmodule diff --git a/ivtest/ivltests/pr530c.v b/ivtest/ivltests/pr530c.v new file mode 100644 index 000000000..53ceb6c62 --- /dev/null +++ b/ivtest/ivltests/pr530c.v @@ -0,0 +1,12 @@ +`timescale 1ns/1ps +module top; + + initial begin + $timeformat(-9,6,"ns",20); + $display("here"); + $display("in top, time: %t",$time); + + $finish(0); + end + +endmodule diff --git a/ivtest/ivltests/pr531a.v b/ivtest/ivltests/pr531a.v new file mode 100644 index 000000000..646359faf --- /dev/null +++ b/ivtest/ivltests/pr531a.v @@ -0,0 +1,64 @@ +module example; + + reg [3:0] mem [0:7]; + reg [3:0] addr; + wire [3:0] m0 = mem[0]; + wire [3:0] m1 = mem[1]; + wire [3:0] m2 = mem[2]; + wire [3:0] m3 = mem[3]; + wire [3:0] m4 = mem[4]; + wire [3:0] m5 = mem[5]; + wire [3:0] m6 = mem[6]; + wire [3:0] m7 = mem[7]; + wire [3:0] maddr = mem[addr]; + + initial begin + $write( " " ); + $display( +"time addr maddr m0 m1 m2 m3 m4 m5 m6 m7" ); + $write( " " ); + $display( +"---- ---- ----- ---- ---- ---- ---- ---- ---- ---- ----" ); + $monitor( "%T %b %b %b %b %b %b %b %b %b %b", + $time, addr, maddr, + m0, m1, m2, m3, m4, m5, m6, m7 ); + mem[0] = 8; + mem[1] = 1; + mem[2] = 2; + mem[3] = 3; + mem[4] = 4; + mem[5] = 5; + mem[6] = 6; + mem[7] = 7; + addr = 0; // 0 + #100 addr = 1; // 100 + #100 addr = 2; // 200 + #100 addr = 3; // 300 + #100 addr = 4; // 400 + #100 addr = 5; // 500 + #100 addr = 6; // 600 + #100 addr = 7; // 700 + #100 addr = 8; // 800 + #100 addr = 4'b001x; // 900 + #100 addr = 4'b01x0; // 1000 + #100 addr = 4'b0x01; // 1100 + #100 addr = 0; // 1200 + #100 mem[addr] = 9; // 1300 + #100 addr = 3; // 1400 + #100 mem[addr] = 10; // 1500 + #100 addr = 6; // 1600 + #100 mem[addr] = 11; // 1700 + #100 addr = 8; // 1800 + #100 mem[addr] = 12; // 1900 + #100 addr = 4'b010x; // 2000 + #100 mem[addr] = 13; // 2100 + #100 addr = 4'b00x1; // 2200 + #100 mem[addr] = 14; // 2300 + #100 addr = 4'b0x10; // 2400 + #100 mem[addr] = 15; // 2500 + #100 addr = 4'bxxxx; // 2600 + #100 mem[addr] = 0; // 2700 + #100 $display( "Finish at time %T", $time ); + end + +endmodule diff --git a/ivtest/ivltests/pr531b.v b/ivtest/ivltests/pr531b.v new file mode 100644 index 000000000..45d2f1496 --- /dev/null +++ b/ivtest/ivltests/pr531b.v @@ -0,0 +1,64 @@ +module example; + + reg [3:0] mem [0:7]; + reg [3:0] addr; + wire [3:0] m0 = mem[0]; + wire [3:0] m1 = mem[1]; + wire [3:0] m2 = mem[2]; + wire [3:0] m3 = mem[3]; + wire [3:0] m4 = mem[4]; + wire [3:0] m5 = mem[5]; + wire [3:0] m6 = mem[6]; + wire [3:0] m7 = mem[7]; + wire [3:0] maddr = mem[addr]; + + initial begin + $write( " " ); + $display( +"time addr maddr m0 m1 m2 m3 m4 m5 m6 m7" ); + $write( " " ); + $display( +"---- ---- ----- ---- ---- ---- ---- ---- ---- ---- ----" ); + $monitor( "%T %b %b %b %b %b %b %b %b %b %b", + $time, addr, maddr, + m0, m1, m2, m3, m4, m5, m6, m7 ); + mem[0] = 8; + mem[1] = 1; + mem[2] = 2; + mem[3] = 3; + mem[4] = 4; + mem[5] = 5; + mem[6] = 6; + mem[7] = 7; + addr = 0; // 0 + #100 addr = 1; // 100 + #100 addr = 2; // 200 + #100 addr = 3; // 300 + #100 addr = 4; // 400 + #100 addr = 5; // 500 + #100 addr = 6; // 600 + #100 addr = 7; // 700 + #100 addr = 8; // 800 + #100 addr = 4'b001x; // 900 + #100 addr = 4'b01x0; // 1000 + #100 addr = 4'b0x01; // 1100 + #100 addr = 0; // 1200 + #100 mem[addr] <= 9; // 1300 + #100 addr = 3; // 1400 + #100 mem[addr] <= 10; // 1500 + #100 addr = 6; // 1600 + #100 mem[addr] <= 11; // 1700 + #100 addr = 8; // 1800 + #100 mem[addr] <= 12; // 1900 + #100 addr = 4'b010x; // 2000 + #100 mem[addr] <= 13; // 2100 + #100 addr = 4'b00x1; // 2200 + #100 mem[addr] <= 14; // 2300 + #100 addr = 4'b0x10; // 2400 + #100 mem[addr] <= 15; // 2500 + #100 addr = 4'bxxxx; // 2600 + #100 mem[addr] <= 0; // 2700 + #100 $display( "Finish at time %T", $time ); + end + +endmodule diff --git a/ivtest/ivltests/pr532.v b/ivtest/ivltests/pr532.v new file mode 100644 index 000000000..4031ebbb6 --- /dev/null +++ b/ivtest/ivltests/pr532.v @@ -0,0 +1,51 @@ +module example; + + reg [7:0] vec; + reg [3:0] ix; + wire vix = vec[ix]; + + initial begin + $display( " time ix vix vec" ); + $display( " ---- ---- --- --------" ); + $monitor( "%T %b %b %b", $time, ix, vix, vec ); + vec = 8'b00000000; + ix = 0; // 0 + #100 ix = 1; // 100 + #100 ix = 2; // 200 + #100 ix = 3; // 300 + #100 ix = 4; // 400 + #100 ix = 5; // 500 + #100 ix = 6; // 600 + #100 ix = 7; // 700 + #100 ix = 8; // 800 + #100 ix = 4'b001x; // 900 + #100 ix = 4'b01x0; // 1000 + #100 ix = 4'b0x01; // 1100 + #100 ix = 0; // 1200 + #100 vec[ix] = 1'b1; // 1300 + #100 vec[ix] = 1'b0; // 1400 + #100 ix = 3; // 1500 + #100 vec[ix] = 1'b1; // 1600 + #100 vec[ix] = 1'b0; // 1700 + #100 ix = 6; // 1800 + #100 vec[ix] = 1'b1; // 1900 + #100 vec[ix] = 1'b0; // 2000 + #100 ix = 8; // 2100 + #100 vec[ix] = 1'b1; // 2200 + #100 vec[ix] = 1'b0; // 2300 + #100 ix = 4'b010x; // 2400 + #100 vec[ix] = 1'b1; // 2500 + #100 vec[ix] = 1'b0; // 2600 + #100 ix = 4'b00x1; // 2700 + #100 vec[ix] = 1'b1; // 2800 + #100 vec[ix] = 1'b0; // 2900 + #100 ix = 4'b0x10; // 3000 + #100 vec[ix] = 1'b1; // 3100 + #100 vec[ix] = 1'b0; // 3200 + #100 ix = 4'bxxxx; // 3300 + #100 vec[ix] = 1'b1; // 3400 + #100 vec[ix] = 1'b0; // 3500 + #100 $display( "Finish at time %T", $time ); + end + +endmodule diff --git a/ivtest/ivltests/pr532b.v b/ivtest/ivltests/pr532b.v new file mode 100644 index 000000000..3663412e3 --- /dev/null +++ b/ivtest/ivltests/pr532b.v @@ -0,0 +1,51 @@ +module example; + + reg [7:0] vec; + reg [3:0] ix; + wire vix = vec[ix]; + + initial begin + $display( " time ix vix vec" ); + $display( " ---- ---- --- --------" ); + $monitor( "%T %b %b %b", $time, ix, vix, vec ); + vec = 8'b00000000; + ix = 0; // 0 + #100 ix = 1; // 100 + #100 ix = 2; // 200 + #100 ix = 3; // 300 + #100 ix = 4; // 400 + #100 ix = 5; // 500 + #100 ix = 6; // 600 + #100 ix = 7; // 700 + #100 ix = 8; // 800 + #100 ix = 4'b001x; // 900 + #100 ix = 4'b01x0; // 1000 + #100 ix = 4'b0x01; // 1100 + #100 ix = 0; // 1200 + #100 vec[ix] <= 1'b1; // 1300 + #100 vec[ix] <= 1'b0; // 1400 + #100 ix = 3; // 1500 + #100 vec[ix] <= 1'b1; // 1600 + #100 vec[ix] <= 1'b0; // 1700 + #100 ix = 6; // 1800 + #100 vec[ix] <= 1'b1; // 1900 + #100 vec[ix] <= 1'b0; // 2000 + #100 ix = 8; // 2100 + #100 vec[ix] <= 1'b1; // 2200 + #100 vec[ix] <= 1'b0; // 2300 + #100 ix = 4'b010x; // 2400 + #100 vec[ix] <= 1'b1; // 2500 + #100 vec[ix] <= 1'b0; // 2600 + #100 ix = 4'b00x1; // 2700 + #100 vec[ix] <= 1'b1; // 2800 + #100 vec[ix] <= 1'b0; // 2900 + #100 ix = 4'b0x10; // 3000 + #100 vec[ix] <= 1'b1; // 3100 + #100 vec[ix] <= 1'b0; // 3200 + #100 ix = 4'bxxxx; // 3300 + #100 vec[ix] <= 1'b1; // 3400 + #100 vec[ix] <= 1'b0; // 3500 + #100 $display( "Finish at time %T", $time ); + end + +endmodule diff --git a/ivtest/ivltests/pr533.v b/ivtest/ivltests/pr533.v new file mode 100644 index 000000000..82e8d229a --- /dev/null +++ b/ivtest/ivltests/pr533.v @@ -0,0 +1,36 @@ +module example; + reg r, c, e; + reg [4:0] a, b; + wire d; + + assign d = ( r | ( a == b ) ) ? 1'b0 : 1'b1; + + // Change inputs at time n*100 + + initial begin + #100 r = 1'bx; a = 5'bxxxxx; b = 5'bxxxxx; + #100 r = 1'b1; a = 5'bxxxxx; b = 5'bxxxxx; + #100 r = 1'b1; a = 5'b00000; b = 5'b00000; + #100 r = 1'b0; a = 5'b00000; b = 5'b00000; + #100 $finish(0); + end + + // Store c and e at time n*100 + 25. + // Note that the value assigned to c is exactly the same as + // the continuous assignment RHS for d (assigned to e). + + initial #25 forever begin + #100 + c = ( r | ( a == b ) ) ? 1'b0 : 1'b1; + e = d; + end + + // Display all values at time n*100 + 50 + + initial #50 forever begin + #100 + $display( "%b,%b,%b = ( %b | ( %b == %b ) ) ? 0 : 1", + c, d, e, r, a, b ); + end + +endmodule diff --git a/ivtest/ivltests/pr534.v b/ivtest/ivltests/pr534.v new file mode 100644 index 000000000..314dd3c1f --- /dev/null +++ b/ivtest/ivltests/pr534.v @@ -0,0 +1,81 @@ +/////////////////////////////////////////////////////////////////////////// +// +// To test: +// (a) The use & representation of time variables +// (b) The display of time variables +// +// Compile and run the program +// iverilog tt_clean.v +// vvp a.out +// +// VISUALLY INSPECT the displays. (There ain't no way to automate this) +// +/////////////////////////////////////////////////////////////////////////// +`timescale 1 ns / 10 ps + +`define PCI_CLK_PERIOD 15.0 // 66 Mhz + +module top; + reg PCI_Clk; + reg fail; + + initial PCI_Clk <= 0; + always #(`PCI_CLK_PERIOD/2) PCI_Clk <= ~PCI_Clk; + + initial begin + fail = 0; + $display("\n\t\t==> CHECK THIS DISPLAY ==>\n"); + $display("pci_clk_period:\t\t\t %0d",`PCI_CLK_PERIOD); + $display("pci_clk_period:\t\t\t %0t",`PCI_CLK_PERIOD); + if($time !== 0) fail = 1; + if (fail == 1) + $display("$time=%0d (0)", $time); + delay_pci(3); + if($simtime !== 4500) fail = 1; + if($time !== 45) fail = 1; + if (fail == 1) + $display("$time=%0d (45)", $time); + #15; + if($simtime !== 6000) fail = 1; + if($time !== 60) fail = 1; + #(`PCI_CLK_PERIOD); + if($simtime !== 7500) fail = 1; + if($time !== 75) fail = 1; + #(`PCI_CLK_PERIOD *2); + if($simtime !== 10500) fail = 1; + if($time !== 105) fail = 1; + + $timeformat(-9,2,"ns",20); + $display("after setting timeformat:"); + $display("pci_clk_period:\t\t\t %0d",`PCI_CLK_PERIOD); + $display("pci_clk_period:\t\t\t %0t",`PCI_CLK_PERIOD); + delay_pci(3); + if($simtime !== 15000) fail = 1; + if($time !== 150) fail = 1; + #15; + if($simtime !== 16500) fail = 1; + if($time !== 165) fail = 1; + #(`PCI_CLK_PERIOD); + if($simtime !== 18000) fail = 1; + if($time !== 180) fail = 1; + #(`PCI_CLK_PERIOD *2); + if($simtime !== 21000) fail = 1; + if($time !== 210) fail = 1; + + $display("\t\t**********************************************"); + if(fail) $display("\t\t****** time representation test BAD *******"); + else $display("\t\t****** time representation test OK *******"); + $display("\t\t**********************************************\n"); + $finish(0); + end + + task delay_pci; + input delta; + integer delta; + integer ii; + begin + #(`PCI_CLK_PERIOD * delta); + end + endtask + +endmodule diff --git a/ivtest/ivltests/pr538.v b/ivtest/ivltests/pr538.v new file mode 100644 index 000000000..65bdf0abe --- /dev/null +++ b/ivtest/ivltests/pr538.v @@ -0,0 +1,43 @@ +////////////////////////////////////////////////////////////////////////////// +// +// using `timescale, test rounding up to specified precision and +// scaling to specified time unit +// +// run with +// iverilog lrm_eg.v +// vvp a.out +// +// (uncomment $display statements for help in debugging) +// +////////////////////////////////////////////////////////////////////////////// +`timescale 10 ns / 1 ns + +module test; + reg set; + parameter d = 1.55; + reg fail; + reg [7:0] ii; + + initial begin + fail = 0; + #d set = 0; + //$display("time in units of 10ns: %0t, in ns: %0d, set: %0b",$time,ii,set); + if((ii < 15) || (ii > 16)) fail = 1; + #d set = 1; + //$display("time in units of 10ns: %0t, in ns: %0d, set: %0b",$time,ii,set); + if((ii < 31) || (ii > 32)) fail = 1; + end + + initial begin + //$dumpvars; + for(ii = 0; ii < 50; ii = ii + 1) begin + //$display("time in ns: %0d, set: %0b",ii,set); + #0.1; + end + $display("\n\t\t**********************************************"); + if(fail) $display("\t\t********** timescale test FAILED *************"); + else $display("\t\t********** timescale test PASSED *************"); + $display("\t\t**********************************************\n"); + $finish(0); + end +endmodule diff --git a/ivtest/ivltests/pr540.v b/ivtest/ivltests/pr540.v new file mode 100644 index 000000000..9206f3403 --- /dev/null +++ b/ivtest/ivltests/pr540.v @@ -0,0 +1,124 @@ +// Icarus 0.6, snapshot 20020907 +// ================================================== +// -- confused by disables from within a fork -- vvp fails +// +// -- to run, incant +// iverilog tt.v +// vvp a.out + +module top; + + integer simple_fail, loop_fail, fork_fail, tlp_fail, tfk_fail; + integer loop_cntr, tlp_cntr; + reg fred, abort; + + initial begin + #1; + simple_fail = 0; + loop_fail = 0; + fork_fail = 0; + tlp_fail = 0; + tfk_fail = 0; + fred = 0; + abort = 1; + #4; + fred = 1; + #4 + if(simple_fail) $display("\n***** simple block disable FAILED *****"); + else $display("\n***** simple block disable PASSED *****"); + if(loop_fail) $display("***** block with loop disable FAILED *****"); + else $display("***** block with loop disable PASSED *****"); + if(fork_fail) $display("***** forked block disable FAILED *****"); + else $display("***** forked block disable PASSED *****"); + if(tlp_fail) $display("***** task with loop disable FAILED *****"); + else $display("***** task with loop disable PASSED *****"); + if(tfk_fail) $display("***** task with forked block disable FAILED ****\n"); + else $display("***** task with forked block disable PASSED ****\n"); + $finish(0); + end + + // simple block disable + initial begin: block_name + #2; + disable block_name; + simple_fail = 1; + end + + // more complex: block disable inside for-loop + initial begin + #2; + begin: configloop + for (loop_cntr = 0; loop_cntr < 3; loop_cntr=loop_cntr+1) begin + wait (fred); + if (abort) begin + disable configloop; + end + loop_fail = 1; + end + end // configloop block + if (loop_fail) $display("\n\ttime: %0t, loop_cntr: %0d",$time,loop_cntr); + end + + // still more complex: disable from within a forked block + initial begin + #2; + begin: forked_tasks + fork + begin + #5; + fork_fail = 1; + end + begin + @(fred); + disable forked_tasks; + fork_fail = 1; + end + join + fork_fail = 1; + end //forked_tasks + end + + // disables inside tasks + initial begin + task_with_loop; + end + initial begin + task_with_fork; + end + +task task_with_loop; + begin + #2; + begin: configtlp + for (tlp_cntr = 0; tlp_cntr < 3; tlp_cntr=tlp_cntr+1) begin + wait (fred); + if (abort) begin + disable configtlp; + end + tlp_fail = 1; + end + end // configloop block + end +endtask // task_with_loop + +task task_with_fork; + begin + #2; + begin: forked_tasks_in_task + fork + begin + #5; + tfk_fail = 1; + end + begin + @(fred); + disable forked_tasks_in_task; + tfk_fail = 1; + end + join + tfk_fail = 1; + end //forked_tasks_in_task + end +endtask // task_with_fork + +endmodule diff --git a/ivtest/ivltests/pr540b.v b/ivtest/ivltests/pr540b.v new file mode 100644 index 000000000..0ec115b27 --- /dev/null +++ b/ivtest/ivltests/pr540b.v @@ -0,0 +1,192 @@ +// Icarus 0.6, snapshot 20020907 +// ================================================== +// -- confused by disables from within a fork -- vvp fails +// +// -- to run, incant +// iverilog tt.v +// vvp a.out +// +// Veriwell +// ======== +// -- OK +// +module top; + + integer simple_fail, loop_fail, fork_fail, tlp_fail; + integer tfk_fail, tfk2_fail, tfk3_fail; + integer tfk2pos, tfk2nega, tfk2negb; + integer tfk3pos, tfk3nega, tfk3negb; + integer loop_cntr, tlp_cntr; + reg fred, abort; + + initial begin + #1; + simple_fail = 0; + loop_fail = 0; + fork_fail = 0; + tlp_fail = 0; + tfk_fail = 0; + tfk2_fail = 0; + tfk2pos = 0; + tfk2nega = 1; + tfk2negb = 1; + tfk3pos = 0; + tfk3nega = 1; + tfk3negb = 1; + fred = 0; + abort = 1; + #4; + fred = 1; + #4 + $display("Check disable:"); + if(simple_fail) $display("***** simple block FAILED *****"); + else $display("***** simple block PASSED *****"); + if(loop_fail) $display("***** block with loop FAILED *****"); + else $display("***** block with loop PASSED *****"); + if(fork_fail) $display("***** forked block FAILED *****"); + else $display("***** forked block PASSED *****"); + if(tlp_fail) $display("***** task with loop FAILED *****"); + else $display("***** task with loop PASSED *****"); + if(tfk_fail) $display("***** task with forked block FAILED *****"); + else $display("***** task with forked block PASSED *****"); + if(tfk2_fail) $display("***** one forked block FAILED *****"); + else $display("***** one forked block PASSED *****"); + if(tfk3_fail) $display("***** the other forked block FAILED *****"); + else $display("***** the other forked block PASSED *****"); + $display(""); + $finish(0); + end + + // simple block disable + initial begin: block_name + #2; + disable block_name; + simple_fail = 1; + end + + // more complex: block disable inside for-loop + initial begin + #2; + begin: configloop + for (loop_cntr = 0; loop_cntr < 3; loop_cntr=loop_cntr+1) begin + wait (fred); + if (abort) begin + disable configloop; + end + loop_fail = 1; + end + end // configloop block + if (loop_fail) $display("\n\ttime: %0t, loop_cntr: %0d",$time,loop_cntr); + end + + // still more complex: disable from within a forked block + initial begin + #2; + begin: forked_tasks + fork + begin + #5; + fork_fail = 1; + end + begin + @(fred); + disable forked_tasks; + fork_fail = 1; + end + join + fork_fail = 1; + end //forked_tasks + end + + // disables inside tasks + initial begin + task_with_loop; + end + initial begin + task_with_fork; + end + initial begin + task_with_fork2; + if(tfk2pos || tfk2nega || tfk2negb) tfk2_fail = 1; + end + initial begin + task_with_fork3; + if(tfk3pos || tfk3nega || tfk3negb) tfk3_fail = 1; + end + +task task_with_loop; + begin + #2; + begin: configtlp + for (tlp_cntr = 0; tlp_cntr < 3; tlp_cntr=tlp_cntr+1) begin + wait (fred); + if (abort) begin + disable configtlp; + end + tlp_fail = 1; + end + end // configloop block + end +endtask // task_with_loop + +task task_with_fork; // disable block whick calls fork + begin + #2; + begin: forked_tasks_in_task + fork + begin: alf + #5; + tfk_fail = 1; + end + begin: bet + @(fred); + disable forked_tasks_in_task; + tfk_fail = 1; + end + join + tfk_fail = 1; + end //forked_tasks_in_task + end +endtask // task_with_fork + +task task_with_fork2; // disable *one* of the forked blocks + begin + #2; + begin: forked_tasks_in_task2 + fork + begin: gam + #5; + tfk2pos = 1; + end + begin: delt + @(fred); + disable gam; + tfk2nega = 0; + end + join + tfk2negb = 0; + end //forked_tasks_in_task + end +endtask // task_with_fork + +task task_with_fork3; // disable *one* of the forked blocks + begin + #2; + begin: forked_tasks_in_task3 + fork + begin: eps + #5; + tfk3nega = 0; + end + begin: zet + @(fred); + disable zet; + tfk3pos = 1; + end + join + tfk3negb = 0; + end //forked_tasks_in_task + end +endtask // task_with_fork + +endmodule diff --git a/ivtest/ivltests/pr540c.v b/ivtest/ivltests/pr540c.v new file mode 100644 index 000000000..1d607851e --- /dev/null +++ b/ivtest/ivltests/pr540c.v @@ -0,0 +1,42 @@ +module top; + + integer fail; + reg cmd, reset; + + initial begin + #1; + reset = 0; + fail = 0; + #1; + cmd = 0; + #2; + reset = 1; + #2; + cmd = 1; + #2; + cmd = 0; + #2; + reset = 0; + #2; + reset = 1; + #4; + if(fail) $display("***** disable test FAILED *****"); + else $display("***** disable test PASSED *****"); + $finish(0); + end + + always @(cmd) begin: command_block + fork + begin + #0; // avoid fork race + disable command_block_reset; + end + begin: command_block_reset + @(reset); + fail = 1; + disable command_block; + end + join + end + +endmodule diff --git a/ivtest/ivltests/pr541.v b/ivtest/ivltests/pr541.v new file mode 100644 index 000000000..631ab7919 --- /dev/null +++ b/ivtest/ivltests/pr541.v @@ -0,0 +1,12 @@ +module example; + reg [2:0] rhs; + wire [5:0] lhs = - rhs; + integer ix; + initial begin + $monitor( "%b[5:0] = - %b[2:0]", lhs, rhs ); + for ( ix = 0; ix <= 7; ix = ix + 1 ) begin + rhs = ix; + #100 ; + end + end +endmodule diff --git a/ivtest/ivltests/pr542.v b/ivtest/ivltests/pr542.v new file mode 100644 index 000000000..ee6e88b76 --- /dev/null +++ b/ivtest/ivltests/pr542.v @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2002 Jane Skinner + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* PR#542 */ +module top; + +parameter[3:0] DAC = 8; + +wire d_pm_in_dac_st; +reg [10:0] pm_next_st; + +assign d_pm_in_dac_st = (pm_next_st[DAC]); + +initial begin + pm_next_st = 10'h100; + #1; + $display("d_pm_in_dac_st = %0b",d_pm_in_dac_st); + $display("d_pm_in_dac_st = %0b",pm_next_st[DAC]); + $finish(0); +end + +endmodule diff --git a/ivtest/ivltests/pr544.v b/ivtest/ivltests/pr544.v new file mode 100644 index 000000000..087210dd9 --- /dev/null +++ b/ivtest/ivltests/pr544.v @@ -0,0 +1,27 @@ +module example; + wire y; + reg p01, p01g, s01, s01g; + bufif1 (pull0, pull1 ) ( y, p01, p01g ); + bufif1 (strong0, strong1) ( y, s01, s01g ); + + initial begin + $monitor( "%T Pu:%b/%b St:%b/%b Y:%b,%v", + $time, p01, p01g, s01, s01g, y, y ); + { p01, p01g, s01, s01g } = 4'b0000; + #100 { p01, p01g, s01, s01g } = 4'b0x00; + #100 { p01, p01g, s01, s01g } = 4'b000x; + #100 { p01, p01g, s01, s01g } = 4'b1x00; + #100 { p01, p01g, s01, s01g } = 4'b001x; + #100 { p01, p01g, s01, s01g } = 4'b0100; + #100 { p01, p01g, s01, s01g } = 4'b0001; + #100 { p01, p01g, s01, s01g } = 4'b1100; + #100 { p01, p01g, s01, s01g } = 4'b0011; + #100 { p01, p01g, s01, s01g } = 4'bx100; + #100 { p01, p01g, s01, s01g } = 4'b00x1; + #100 { p01, p01g, s01, s01g } = 4'b010x; + #100 { p01, p01g, s01, s01g } = 4'bx10x; + #100 { p01, p01g, s01, s01g } = 4'b111x; + #100 { p01, p01g, s01, s01g } = 4'bx11x; + #100 ; + end +endmodule diff --git a/ivtest/ivltests/pr547.v b/ivtest/ivltests/pr547.v new file mode 100644 index 000000000..0b77298b7 --- /dev/null +++ b/ivtest/ivltests/pr547.v @@ -0,0 +1,17 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif +module top; + reg [9:0] a; + reg b; + + initial begin + a = 10'h3ff; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + b = a[15]; +`else + b = 1'bx; +`endif + $display("A = %h, b = %b", a, b); + end // initial begin +endmodule // top diff --git a/ivtest/ivltests/pr556.v b/ivtest/ivltests/pr556.v new file mode 100644 index 000000000..d3a367d5a --- /dev/null +++ b/ivtest/ivltests/pr556.v @@ -0,0 +1,20 @@ +/* + * This test is from PR#556. + * + * The output should generate signed and unsigned values + * from -256 to 256. Also, since the $random sequence is + * repeatable, it should generate the *same* seqnence + * every time the program is run. + */ +module test_ran; +integer i,j; +initial + begin + for (j=0;j<256;j=j+1) + begin + i = $random % 256; + $display ("The random number is %d",i); + end + $finish(0); + end +endmodule diff --git a/ivtest/ivltests/pr564.v b/ivtest/ivltests/pr564.v new file mode 100644 index 000000000..029e8daca --- /dev/null +++ b/ivtest/ivltests/pr564.v @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* Based on PR#564 */ + +module main( ); + + + parameter [7:0] forwards = 8'b11110001; + parameter [0:7] backwards = 8'b10001111; + + integer i; + + initial begin + for (i = 0 ; i < 8 ; i = i + 1) begin + $write("forwards[%0d] === %b, ", i, forwards[i]); + $display("backwards[%0d] === %b", i, backwards[i]); + + if (forwards[i] !== backwards[i]) begin + $display("FAILED -- forwards[%0d] !== backwards[%0d]", i, i); + $finish; + end + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/pr567.v b/ivtest/ivltests/pr567.v new file mode 100644 index 000000000..c8b5ad9cd --- /dev/null +++ b/ivtest/ivltests/pr567.v @@ -0,0 +1,4 @@ +module test; + reg blah [63:0]; + initial blah = 0; // This should generate an error message. +endmodule diff --git a/ivtest/ivltests/pr569.v b/ivtest/ivltests/pr569.v new file mode 100644 index 000000000..875506a1c --- /dev/null +++ b/ivtest/ivltests/pr569.v @@ -0,0 +1,16 @@ +/* + * Derived from PR#569 + */ + +module test(); + parameter foo = 8'b01010101; + parameter bar = {foo,{2{foo}}}; // fails + // parameter tmp = {2{foo}}; // this + next line succeed + // parameter bar = {foo,tmp}; + reg[23:0] cnt; + reg CLK; + + initial $monitor("%b", cnt); + initial CLK = 0; + initial cnt = bar; +endmodule diff --git a/ivtest/ivltests/pr572.v b/ivtest/ivltests/pr572.v new file mode 100644 index 000000000..9335354f9 --- /dev/null +++ b/ivtest/ivltests/pr572.v @@ -0,0 +1,43 @@ +/* + * Hierarchical event testcase + * + * Copyright (C) 2002 Charles Lepple + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * compilation options: none necessary + */ + +`define TEST_HIERARCHICAL_EVENT +// yields parse error when defined + +module top(); + event toplevel_event; + + submodule sub(); + + initial #10 -> toplevel_event; +endmodule // top + +module submodule(); + event local_event; + + initial #25 -> local_event; + + always + begin +`ifdef TEST_HIERARCHICAL_EVENT + @top.toplevel_event + $display("at %0d: toplevel event triggered", $time); +`endif + @local_event + $display("at %0d: local event triggered", $time); + end +endmodule // submodule + +// local variables: +// verilog-simulator: "iverilog" +// end: diff --git a/ivtest/ivltests/pr572b.v b/ivtest/ivltests/pr572b.v new file mode 100644 index 000000000..be384aac3 --- /dev/null +++ b/ivtest/ivltests/pr572b.v @@ -0,0 +1,43 @@ +/* + * Hierarchical event testcase + * + * Copyright (C) 2002 Charles Lepple + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * compilation options: none necessary + */ + +`define TEST_HIERARCHICAL_EVENT +// yields parse error when defined + +module top(); + event toplevel_event; + + submodule sub(); + + initial #10 -> toplevel_event; +endmodule // top + +module submodule(); + event local_event; + + initial #25 -> local_event; + + always + begin +`ifdef TEST_HIERARCHICAL_EVENT + @(top.toplevel_event) + $display("at %0d: toplevel event triggered", $time); +`endif + @local_event + $display("at %0d: local event triggered", $time); + end +endmodule // submodule + +// local variables: +// verilog-simulator: "iverilog" +// end: diff --git a/ivtest/ivltests/pr578.v b/ivtest/ivltests/pr578.v new file mode 100644 index 000000000..92daf6fbb --- /dev/null +++ b/ivtest/ivltests/pr578.v @@ -0,0 +1,29 @@ +module main; + + function [7:0] add; + input [7:0] a, b; + + reg [8:0] tmp; + begin + tmp = a + b; + if (tmp < 9'h100) + add = tmp; + else + add = 8'hff; + end + endfunction // add + + reg[7:0] out; + initial begin + + out = 1? add(8,9) : 0; + + if (out !== 8'd17) begin + $display("FAILED -- out = %b", out); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/pr581.v b/ivtest/ivltests/pr581.v new file mode 100644 index 000000000..bc366a6bc --- /dev/null +++ b/ivtest/ivltests/pr581.v @@ -0,0 +1,28 @@ +module module1(clock,reset,result); +input clock,reset; +output result; +reg result; +always @ (posedge clock) +if (reset) result <= 0; else result <= 1; +endmodule + +// driver +module main; + reg clk,reset; + reg data[1:3]; // ILLEGAL port connection NOT detected +// to fix, use wire data_1,data_2,data_3; + module1 inst1(clk,reset,data[1]); + module1 inst2(clk,reset,data[2]); + module1 inst3(clk,reset,data[3]); + +always #50 clk = ~clk; +initial begin + +$monitor($time,"clk=%b,reset=%b,%b%b%b",clk,reset,data[1],data[2],data +[3]); + clk = 0; + reset = 1; + #200 reset = 0; + #200 $display("driver timeout"); $finish; +end +endmodule diff --git a/ivtest/ivltests/pr584.v b/ivtest/ivltests/pr584.v new file mode 100644 index 000000000..e05051a4f --- /dev/null +++ b/ivtest/ivltests/pr584.v @@ -0,0 +1,23 @@ +/* + * This example is based on PR#584 in the bugs database. + */ + +module main; + reg clk; + +always #50 clk = ~clk; + +initial begin + clk = 0; + #100 + $display("%d", 1e3*2e-2); + $display("%d", 1e2*0.2); + $display("%d", 1e1*2); // prints ok + $display("%d", 1e0*20.0); // prints ok + $display("%d", 1e-1*200.0); + // bug -- some correctly report "20" and others report "0" + // looks like implicit real2integer conversion for every factor in expression + // problem caused by partial support of reals + $finish(0); +end +endmodule diff --git a/ivtest/ivltests/pr585.v b/ivtest/ivltests/pr585.v new file mode 100644 index 000000000..5e91abcd1 --- /dev/null +++ b/ivtest/ivltests/pr585.v @@ -0,0 +1,23 @@ +/* + * Based on PR#585. + */ +module main(); + + reg [7:0] ram_temp; + reg mem; + + initial begin + ram_temp = 8'h08; + mem = (ram_temp & 8'h08) >> 3; + $write("Calculated: %b\nActually in mem: %b\n",((ram_temp & 8'h08) >> 3), +mem); + if (mem !== 1'b1) begin + $display("FAILED == mem = %b", mem); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/pr587.v b/ivtest/ivltests/pr587.v new file mode 100644 index 000000000..d31ef2a9c --- /dev/null +++ b/ivtest/ivltests/pr587.v @@ -0,0 +1,58 @@ +/* + * The x in foo and bar should always have the same value. + */ +module foo(); + wire x; + reg clk; + reg [7:0] counter; + + always #5 clk <= ~clk; + + assign x = 0; + + initial begin + clk = 0; + counter = 0; + # 2600 $display("PASSED"); + $finish; + end + + always @(negedge clk) + if (x !== u_bar.x) begin + $display("FAILED -- x != u_bar.x"); + $finish; + end + + always @(posedge clk) begin + counter <= counter + 1; + + if (counter == 32) + force x = 0; + else if (counter == 64) + force x = 1; + else if (counter == 96) + force x = 0; + else if (counter == 128) + release x; + + $display("[foo %d] x = %d",counter, x); + end + + bar u_bar( .clk(clk), .x(x)); + +endmodule + +module bar(clk, x); + input clk; + input x; + + reg [7:0] counter; + + initial counter = 0; + + always @(posedge clk) begin + counter <= counter + 1; + + $display("[bar %d] x = %d",counter, x); + end +endmodule diff --git a/ivtest/ivltests/pr590.v b/ivtest/ivltests/pr590.v new file mode 100644 index 000000000..36d790547 --- /dev/null +++ b/ivtest/ivltests/pr590.v @@ -0,0 +1,51 @@ +module ex1 +( +clk, +reset, +insig, +outsig +); +input clk; +input reset; +input [3:0] insig; +output [3:0] outsig; +reg [3:0] outsig; + +//reg [3:0] val_q; + +always @ ( insig ) begin + outsig = ~(4'hf << insig); + $display("out: %b, in: %b",outsig,insig); +end + +endmodule +module main; +reg clk; +reg reset; +reg [3:0] insig; +wire [3:0] outsig; +ex1 ex1( + .clk(clk), + .reset(reset), + .insig(insig), + .outsig(outsig)); + +initial + begin + $display ("\n starting the testbench\n"); + // set the inital value to 0 + clk = 1'b0; + reset = 1; + insig = 4'h0; + #20 insig = 4'h2; +end +initial + #71 $finish(0); + +always + #10 clk = ~clk; + +always @(posedge clk) + $display ($time, "..................clock tickling"); + +endmodule diff --git a/ivtest/ivltests/pr594.v b/ivtest/ivltests/pr594.v new file mode 100644 index 000000000..adad8709f --- /dev/null +++ b/ivtest/ivltests/pr594.v @@ -0,0 +1,14 @@ +module test; + parameter NBytes = 21; + parameter Message = "0H1d2j3i4k 5R6i7k8d9["; // Message to send + + integer J; + reg [7:0] RSData; + initial begin + for (J=(NBytes-1); J>=0; J=J-1) + begin + RSData = (Message>>(J*8)) & 8'hFF; + $display("RSData=%h", RSData); + end + end +endmodule // test diff --git a/ivtest/ivltests/pr596.v b/ivtest/ivltests/pr596.v new file mode 100644 index 000000000..09dc0a9a6 --- /dev/null +++ b/ivtest/ivltests/pr596.v @@ -0,0 +1,71 @@ +`timescale 1ns/1ns + +module lfsr_test(); + parameter SIZE = 4; + reg clk, reset, ena; + wire [SIZE-1:0] out; + + initial + begin //{ + clk = 0; + reset = 0; + ena = 1'bz; + #15 reset = 0; + #20 reset = 1; + end //} + + initial + begin //{ + //$dumpfile("lfsr_test.vcd"); // Change filename as appropriate. + //$dumpvars( 0, lfsr_test); + $monitor("out=%b", out); + end //} + + always clk = #10 ~clk; + + lfsr_counter LF( clk, reset, out ); + + initial #1000 $finish(0); +endmodule // gray_code + + + + +module lfsr_counter( clk, reset, out ); + `define W 4 + parameter WIDTH = `W; + parameter TAP = `W'b1001; + integer N; + + output [WIDTH-1:0] out; + input clk, reset; + + wire [WIDTH-1:0] gc; + reg [WIDTH-1:0] lfsr, next_lfsr; + reg fb_lsb, fb; + + always @(posedge clk or negedge reset ) + begin //{ + if( reset == 1'b0 ) + lfsr[WIDTH-1:0] <= `W'b0; + else + lfsr[WIDTH-1:0] <= next_lfsr[WIDTH-1:0]; + end //} + + always @( lfsr ) + begin //{ + fb_lsb = ~| lfsr[WIDTH-2:0]; + fb = lfsr[WIDTH-1] ^ fb_lsb; + for( N=WIDTH; N>=0; N=N-1 ) + if( TAP[N] == 1 ) + next_lfsr[N] = lfsr[N-1] ^ fb; + else + next_lfsr[N] = lfsr[N-1]; + next_lfsr[0] = fb; + end //} + assign out[WIDTH-1:0] = {1'b0, lfsr[WIDTH-1:1]}; //(1) + //assign out[WIDTH-1:0] = lfsr[WIDTH-1:0]; //(2) + //assign gc[WIDTH-1:0] = out[WIDTH-1:0] ^ {1'b0, out[WIDTH-1:1]}; +//(3) + +endmodule // gray_counter diff --git a/ivtest/ivltests/pr602.v b/ivtest/ivltests/pr602.v new file mode 100644 index 000000000..1e34dbdeb --- /dev/null +++ b/ivtest/ivltests/pr602.v @@ -0,0 +1,65 @@ +/* + * Copyright (c) 1999-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This is derived from pr602. + */ + +module main; + + reg [1:0] a [3:0], x; + + integer i; + initial begin + a[0] = 0; + a[1] = 1; + a[2] = 2; + a[3] = 3; + + // The index expressions of this parameter expression + // should be evaluated to constants. + $display("a[(1-1)+0] = %b", a[(1-1)+0]); + $display("a[(2-1)+0] = %b", a[(2-1)+0]); + x = a[(1-1)+0]; + if (x !== 2'b00) begin + $display("FAILED -- x == %b", x); + $finish; + end + + x = a[(2-1)+0]; + if (x !== 2'b01) begin + $display("FAILED -- x == %b", x); + $finish; + end + + x <= a[(1-1)+0]; + #1 if (x !== 2'b00) begin + $display("FAILED -- x == %b", x); + $finish; + end + + x <= a[(2-1)+0]; + #1 if (x !== 2'b01) begin + $display("FAILED -- x == %b", x); + $finish; + end + + $display("PASSED"); + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/pr617.v b/ivtest/ivltests/pr617.v new file mode 100644 index 000000000..9f212240e --- /dev/null +++ b/ivtest/ivltests/pr617.v @@ -0,0 +1,45 @@ +module main(); + parameter INIT_00 = 32'hffffffff; + reg [17:0] t; + reg [8:0] c; + reg error ; + initial begin + error = 0; + c = 0; + $display("%b",INIT_00[c]); + c = 1; + $display("%b",INIT_00[c]); + + t = {17'd0,INIT_00[0]}<<1; + if(t !== 17'b0_0000_0000_0000_0010) + begin + $display("FAILED - shift operation {17'd0,INIT_00[0]}<<1; %b",t); + error = 1; + end + else + $display("%b",t); + c = 0; + t = {17'd0,INIT_00[c]}<<1; + if(t !== 17'b0_0000_0000_0000_0010) + begin + $display("FAILED - shift operation {17'd0,INIT_00[c]}<<1 %b",t); + error = 1; + end + else + $display("%b",t); + c = 16; + t = {17'd0,INIT_00[c]}<<1; + if(t !== 17'b0_0000_0000_0000_0010) + begin + $display("FAILED - shift operation {17'd0,INIT_00[c]}<<1 %b",t); + error = 1; + end + else + $display("%b",t); + + if(error == 1) + $display("FAILED"); + else + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr622.v b/ivtest/ivltests/pr622.v new file mode 100644 index 000000000..c27dece63 --- /dev/null +++ b/ivtest/ivltests/pr622.v @@ -0,0 +1,6 @@ +`define FOO bar +module foo; + initial begin + $display("macro FOO = %s", ``FOO); + end +endmodule diff --git a/ivtest/ivltests/pr632.v b/ivtest/ivltests/pr632.v new file mode 100644 index 000000000..c6a3b602d --- /dev/null +++ b/ivtest/ivltests/pr632.v @@ -0,0 +1,14 @@ +`timescale 1ns/10ps +module test; + +reg [15:0] a1; + +initial + begin + $monitor ("a1[0]=%b",a1[0]); + for (a1 = 16'h01; a1 != 16'h1f; a1 = a1 + 1) + begin + #1; + end + end +endmodule diff --git a/ivtest/ivltests/pr639.v b/ivtest/ivltests/pr639.v new file mode 100644 index 000000000..40cdd4592 --- /dev/null +++ b/ivtest/ivltests/pr639.v @@ -0,0 +1,121 @@ +// Icarus 0.7, cvs files from Feb 2, 2003 +// -------------------------------------- +// +// iverilog precision.v +// or +// iverilog -D DUMP precision.v +// vvp a.out +// +// Use & display of real time periods with `timescale set to 1 ns / 10 ps +// +// $simtime keeps time in 10ps increments +// $simtime cannot be displayed (yet) +// $simtime can be used in comparisons -- compared to times in 10 ps units +// $time should be $simtime-rounded-to-ns +// $time displays according to `timescale and $timeformat +// $time can be used in comparisons -- compared to times in 1 ns units +// +// Assuming that the simulation runs on units of 10ps, a clock which is set to +// change value every (15.2 ns)/2 should change every 7.6 ns, i.e. 760*10ps. +// +// The dumpfile shows a timescale of 10ps; therefore, it should show the clock +// changing every 760*10ps. It doesn't. The clock is changing every 700*10ps. +// The checks on the clock using $simtime below verify that the dumpfile is +// seeing what the simulation is, in fact, doing. +// + +`timescale 1 ns / 10 ps + +`define PERIODI 15 +`define PERIODR 15.2 + +module top; + +reg tick,clk, fail; +reg [31:0] ii; + +`ifdef DUMP + initial begin + $dumpvars; + end +`endif + +initial begin + $timeformat(-9, 2, "ns", 20); + + $display("integer & real periods: 'd%0d 'd%0d",`PERIODI,`PERIODR); + $display("integer & real periods (15.00, 15.20): 't%0t 't%0t",`PERIODI,`PERIODR); + $display("......... %s should be displayed as 15.20 in its timeformat.", ``PERIODR); + $display("integer & real periods: 'b%0b 'b%0b",`PERIODI,`PERIODR); + $display("integer & real periods: 'h%0h 'h%0h",`PERIODI,`PERIODR); + + clk = 0; + tick = 0; + fail = 0; + #1; + if($time === 1) $display("\t$time is in ns"); + if($time === 100) $display("\t$time is in 10 ps"); + $display("\ttime (1, 1h): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); + if($simtime === 1) $display("\t$simtime is in ns"); + if($simtime === 100) $display("\t$simtime is in 10 ps"); + $display("\tsimtime (100, 64h): 'd%0d, 't%0t, 'h%0h",$simtime,$simtime,$simtime); + #(`PERIODI - 1); + tick = 1; + if($time !== 15) begin fail = 1;$display("time (15, Fh): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end + if($simtime !== 1500) begin fail=1; $display("simtime not 1500"); end + #(`PERIODR); + tick = 0; + if($time !== 30) begin fail = 1; $display("time (30, 1Eh): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end + if($simtime !== 3020) begin fail=1; $display("simtime not 3020"); end + #(`PERIODR); + tick = 1; + if($time !== 45) begin fail = 1; $display("time (45, 2Dh): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end + if($simtime !== 4540) begin fail=1; $display("simtime not 4540"); end + #(`PERIODR); + tick = 0; + if($time !== 61) begin fail = 1; $display("time (61, 3Dh): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end + if($simtime !== 6060) begin fail=1; $display("simtime not 6060"); end + #(`PERIODR); + tick = 1; + if($time !== 76) begin fail = 1; $display("time (76, 4Ch): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end + if($simtime !== 7580) begin fail=1; $display("simtime not 7580"); end + #(`PERIODR); + tick = 1; + if($time !== 91) begin fail = 1; $display("time (91, 5Bh): 'd%0d, 't%0t, 'h%0h",$time,$time,$time); end + if($simtime !== 9100) begin fail=1; $display("simtime not 9100"); end + + $display("\t\t**********************************************"); + if(fail) $display("\t\t****** time precision test FAILED *******"); + else $display("\t\t****** time precision test PASSED *******"); + $display("\t\t**********************************************\n"); + + $finish(0); +end + +initial begin + for(ii = 0; ii < 1524; ii = ii + 1) begin + #(0.01); + if(($simtime == 659) && (clk !== 0)) begin fail=1; $display("time: 659, clk wrong"); end + if(($simtime == 701) && (clk !== 0)) begin fail=1; $display("time: 701, clk wrong"); end + if(($simtime == 759) && (clk !== 0)) begin fail=1; $display("time: 759, clk wrong"); end + if(($simtime == 761) && (clk !== 1)) begin fail=1; $display("time: 761, clk wrong"); end + if(($simtime == 1399) && (clk !== 1)) begin fail=1; $display("time: 1399, clk wrong"); end + if(($simtime == 1401) && (clk !== 1)) begin fail=1; $display("time: 1401, clk wrong"); end + if(($simtime == 1519) && (clk !== 1)) begin fail=1; $display("time: 1519, clk wrong"); end + if(($simtime == 1521) && (clk !== 0)) begin fail=1; $display("time: 1521, clk wrong"); end + end +end + +always begin + #(`PERIODR/2) clk <= ~clk; + // clock should change as follows: + // T (10ps) : clk + // 0 : 0 + // 760 : 1 + // 1520 : 0 + // 2280 : 1 + // 3040 : 0 + // etc. +end + +endmodule diff --git a/ivtest/ivltests/pr673.v b/ivtest/ivltests/pr673.v new file mode 100644 index 000000000..ab56347ac --- /dev/null +++ b/ivtest/ivltests/pr673.v @@ -0,0 +1,27 @@ +module main; + +reg[63:0] period; + +initial begin + if (period !== 'hx) $display ("init wrong"); + if (period === 'hx) + $display ("init right"); + else + $display ("init wrong 2: %h", period); +end + +always @ (period) begin +// if (period == 10) $display("%t hurrah!",$time); + if (period !== 1'bx) + $display ("right %t %d", $time,period); + else + $display("wrong %t %d",$time,period); +end + +initial begin + #10 period = $time; + #30 $display("bye."); + $finish(0); +end + +endmodule diff --git a/ivtest/ivltests/pr675.v b/ivtest/ivltests/pr675.v new file mode 100644 index 000000000..1112879fc --- /dev/null +++ b/ivtest/ivltests/pr675.v @@ -0,0 +1,21 @@ +module bug; + +wire a, b, c, d; +assign c = 1'bx; +assign a = 1'b1; +assign b = 1'b0; +assign d = 1'bx; + +wire e = {c,d} == {a,b}; + +initial + begin + #2 + if ((e == 1'b1) || (e == 1'b0)) + $display("FAILED -- abcde=%b%b%b%b%b", a, b, c, d, e); + else + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/pr678.v b/ivtest/ivltests/pr678.v new file mode 100644 index 000000000..2b2534707 --- /dev/null +++ b/ivtest/ivltests/pr678.v @@ -0,0 +1,52 @@ +module main; + + real foo; + real bar; + + initial begin + foo = 1.0; + bar = 1.2; + + if (foo >= bar) begin + $display("FAILED -- foo < bar?"); + $finish; + end + + if (foo >= 1.2) begin + $display("FAILED -- foo < 1.2?"); + $finish; + end + + if (1.0 >= 1.2) begin + $display("FAILED -- 1.0 < 1.2?"); + $finish; + end + + if (1 >= 1.2) begin + $display("FAILED -- 1 < 1.2?"); + $finish; + end + + if (foo > bar) begin + $display("FAILED -- foo < bar?"); + $finish; + end + + if (foo > 1.2) begin + $display("FAILED -- foo < 1.2?"); + $finish; + end + + if (1.0 > 1.2) begin + $display("FAILED -- 1.0 < 1.2?"); + $finish; + end + + if (1 > 1.2) begin + $display("FAILED -- 1 < 1.2?"); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/pr685.v b/ivtest/ivltests/pr685.v new file mode 100644 index 000000000..9bd957abc --- /dev/null +++ b/ivtest/ivltests/pr685.v @@ -0,0 +1,44 @@ +module test (clk, in, out); + input clk; + input [15:0] in; + output [4:0] out; + + reg [4:0] out; + (* ivl_synthesis_on *) + always @(posedge clk) begin + // In PR#685, this caused an assertion with iverilog -S + out = (in >= 16) ? 16 : in; + end + +endmodule + +module main; + + reg clk; + reg [15:0] value; + wire [4:0] sat; + + test dut (clk, value, sat); + + (* ivl_synthesis_off *) + initial begin + value = 0; + clk = 1; + for (value = 0 ; value < 'h15 ; value = value+1) begin + #1 clk = 0; + #1 clk = 1; + #1 if ((value > 16) && (sat !== 5'd16)) begin + $display("FAILED -- value=%d, sat=%b", value, sat); + $finish; + end + + if ((value <= 16) && (value !== sat)) begin + $display("FAILED -- value=%d, sat=%b", value, sat); + $finish; + end + end // for (value = 0 ; value < 'h15 ; value = value+1) + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/pr690.dat b/ivtest/ivltests/pr690.dat new file mode 100644 index 000000000..0d66ea1ae --- /dev/null +++ b/ivtest/ivltests/pr690.dat @@ -0,0 +1,2 @@ +0 +1 diff --git a/ivtest/ivltests/pr690.v b/ivtest/ivltests/pr690.v new file mode 100644 index 000000000..58cd68a2e --- /dev/null +++ b/ivtest/ivltests/pr690.v @@ -0,0 +1,31 @@ +module test(CLK, OE, A, OUT); +parameter numAddr = 1; +parameter numOut = 1; +parameter wordDepth = 2; +parameter MemFile = "ivltests/pr690.dat"; + +input CLK, OE; +input [numAddr-1:0] A; +output [numOut-1:0] OUT; + +reg [numOut-1:0] memory[wordDepth-1:0]; +reg [numAddr-1:0] addr; + +initial begin + // The whole point of this regression test is to check that + // the file name argument can be a string parameter. + $readmemb(MemFile,memory, 0); + if (memory[0] !== 0) begin + $display("FAILED -- memory[0] == %b", memory[0]); + $finish; + end + if (memory[1] !== 1) begin + $display("FAILED -- memory[1] == %b", memory[1]); + $finish; + end + + $display("PASSED"); +end + + +endmodule diff --git a/ivtest/ivltests/pr693.v b/ivtest/ivltests/pr693.v new file mode 100644 index 000000000..580ce196e --- /dev/null +++ b/ivtest/ivltests/pr693.v @@ -0,0 +1,34 @@ +/* + * Notice how the port direction and type are declared + * together in each statement. + */ +module one_a(sum,co,a,b,ci); + output reg sum; + output reg co; + input wire a; + input wire b; + input wire ci; + +always@(a or b or ci) + begin + sum = a ^ b ^ ci; + co = a*b || a*ci || b*ci; + end +endmodule + + +module main; + + wire sum, co; + reg [3:0] in; + + one_a dut (sum, co, in[0], in[1], in[2]); + + initial begin + in = 0; + #1 for (in = 0 ; in[3] == 0 ; in = in + 1) begin + #1 $display("in=%b; co/sum = %b/%b", in, co, sum); + end + end + +endmodule // main diff --git a/ivtest/ivltests/pr699.v b/ivtest/ivltests/pr699.v new file mode 100644 index 000000000..4963322bd --- /dev/null +++ b/ivtest/ivltests/pr699.v @@ -0,0 +1,33 @@ +/* + * Based on Request id 1313366 in the iverilog Bugs database, or + * pr699 in the ivl-bugs database. +*/ +module bug; + +wire a, b, c, d; + +assign c = 1'b0; +assign a = 1'b0; +assign b = 1'b0; + +assign d = c ? a : b; + +initial + begin + force b = 1'b1; + #1 if (b !== 1'b1) begin + $display("FAILED -- b = %b", b); + $finish; + end + + if (d !== 1'b1) begin + $display("FAILED -- d = %b", d); + $finish; + end + + release b; + $display("PASSED"); + $finish; + end + +endmodule // bug diff --git a/ivtest/ivltests/pr699b.v b/ivtest/ivltests/pr699b.v new file mode 100644 index 000000000..46463684b --- /dev/null +++ b/ivtest/ivltests/pr699b.v @@ -0,0 +1,34 @@ +/* + * Based on Request id 1313366 in the iverilog Bugs database, or + * pr699 in the ivl-bugs database. + * Modified to force the comparison net. + */ +module bug; + +wire a, b, c, d; + +assign c = 1'b0; +assign a = 1'b1; +assign b = 1'b0; + +assign d = c ? a : b; + +initial + begin + force c = 1'b1; + #1 if (c !== 1'b1) begin + $display("FAILED -- b = %b", b); + $finish; + end + + if (d !== 1'b1) begin + $display("FAILED -- d = %b", d); + $finish; + end + + release c; + $display("PASSED"); + $finish; + end + +endmodule // bug diff --git a/ivtest/ivltests/pr704.hex b/ivtest/ivltests/pr704.hex new file mode 100644 index 000000000..153616fe3 --- /dev/null +++ b/ivtest/ivltests/pr704.hex @@ -0,0 +1,3 @@ +/* Stub data file for regression test pr704.v */ +10101010_10101010_10101010_10101010 +01010101_01010101_01010101_01010101 diff --git a/ivtest/ivltests/pr704.v b/ivtest/ivltests/pr704.v new file mode 100644 index 000000000..b335bdd5f --- /dev/null +++ b/ivtest/ivltests/pr704.v @@ -0,0 +1,27 @@ +/* PR#704 */ +module foo; + + reg [80*8:1] filename; + reg [31:0] memory[1:2048]; + + initial filename = "ivltests/pr704.hex"; + + initial begin + $display("The filename is %0s", filename); + $readmemb(filename, memory, 1); + + if (memory[1] !== 32'haa_aa_aa_aa) begin + $display("FAILED"); + $finish; + end + + if (memory[2] !== 32'h55_55_55_55) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/pr707.v b/ivtest/ivltests/pr707.v new file mode 100644 index 000000000..b535b20d9 --- /dev/null +++ b/ivtest/ivltests/pr707.v @@ -0,0 +1,30 @@ +// +// Test for PR#707, NULL UDP port connections +// +primitive mux (x, s, a, b, f); +output x; +input s, a, b, f; +table + // s a b f mux + 0 1 ? ? : 1 ; // ? = 0 1 x + 0 0 ? ? : 0 ; + 1 ? 1 ? : 1 ; + 1 ? 0 ? : 0 ; + x 0 0 ? : 0 ; + x 1 1 ? : 1 ; +endtable +endprimitive + +module test; + reg r1, r2, r3; + wire w1; + + initial begin + r1 = 1'b0; + r2 = 1'b0; + r3 = 1'b0; + // If it makes it here, the code compiled + $display("PASSED"); + end + mux udp1(w1, r1, r2, r3, /* foo */); +endmodule diff --git a/ivtest/ivltests/pr708.v b/ivtest/ivltests/pr708.v new file mode 100644 index 000000000..47617798d --- /dev/null +++ b/ivtest/ivltests/pr708.v @@ -0,0 +1,22 @@ +module test; + + parameter PARM = 1.5; + reg r; + + initial begin + case (PARM) + 1.0 : r <= 'd1; + 1.5 : r <= 'd0; + 2.0 : r <= 'd1; + default: r <= 1'bx; + endcase + + #1; + + if (r !== 'd0) + $display("FAILED %b != 0", r); + else + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr710.v b/ivtest/ivltests/pr710.v new file mode 100644 index 000000000..ec616e893 --- /dev/null +++ b/ivtest/ivltests/pr710.v @@ -0,0 +1,20 @@ +module main; + + reg [5:0] idx, mask; + wire [5:0] foo = idx & mask; + + initial begin + mask = 5'h1f; + for (idx = 0 ; idx < 5 ; idx = idx+1) + wait (foo == idx) begin + $display("foo=%d, idx=%d", foo, idx); + if (foo !== idx) begin + $display("FAILED"); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/pr718.v b/ivtest/ivltests/pr718.v new file mode 100644 index 000000000..7b7375672 --- /dev/null +++ b/ivtest/ivltests/pr718.v @@ -0,0 +1,20 @@ +// +// Verifies disable terminates a forked forever. +// +module test; + initial begin + fork: F + forever #10; + disable F; + join + $display("PASSED"); + $finish; + end + + initial begin + #20; + $display("FAILED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/pr721.v b/ivtest/ivltests/pr721.v new file mode 100644 index 000000000..056d29af4 --- /dev/null +++ b/ivtest/ivltests/pr721.v @@ -0,0 +1,28 @@ +module port_test(a); + parameter p_w=1<<5; // 32 + parameter c_w=p_w>>4;// 2 (<--- here) + output [c_w-1:0] a; + wire [c_w-1:0] a='h0; + + initial begin + $display("p_w=%b, c_w=%b", p_w, c_w); + + if (c_w !== 2) begin + $display("FAILED -- c_w == %b", c_w); + $finish; + end + + if ($bits(a) !== 2) begin + $display("FAILED -- $bits(a) == %b", $bits(a)); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule + +module main; + wire [1:0] a; + port_test m (.a(a)); +endmodule diff --git a/ivtest/ivltests/pr722.v b/ivtest/ivltests/pr722.v new file mode 100644 index 000000000..cd0d71ea2 --- /dev/null +++ b/ivtest/ivltests/pr722.v @@ -0,0 +1,19 @@ +/* From PR#722 + * If bounds checking is in a 16bit field, this will crash. + */ +module test; + + reg [65536 : 0] mem; + integer i; + + initial begin + i = 65536; + mem[i] = 1; + if (mem[i] !== 1) begin + $display ("FAILED -- bit %0d (%b)", i, mem[i]); + $finish; + end + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr729.v b/ivtest/ivltests/pr729.v new file mode 100644 index 000000000..82d29e10f --- /dev/null +++ b/ivtest/ivltests/pr729.v @@ -0,0 +1,13 @@ +module main; + parameter p_real = 1.2345 ; + parameter p_real_x2 = p_real * 2 ; // <-- here + + real v_real, v_real_x2 ; + + initial begin + v_real = p_real ; + v_real_x2 = p_real * 2 ; + $display("p_real=%f, v_real=%f, v_real_x2=%f", p_real, v_real, v_real_x2) ; + end + +endmodule diff --git a/ivtest/ivltests/pr734.v b/ivtest/ivltests/pr734.v new file mode 100644 index 000000000..f9bc60007 --- /dev/null +++ b/ivtest/ivltests/pr734.v @@ -0,0 +1,17 @@ +/* + * Test expressions with very wide reg variables. + */ + +module test; + parameter idx = 3584; // Anything lower works + reg [69119:0] mem; + reg r; + initial begin + mem[idx] = 1; + r = mem >> idx; + if (r !== 1) + $display("FAILED r = %b", r); + else + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/pr735.v b/ivtest/ivltests/pr735.v new file mode 100644 index 000000000..fd70662b3 --- /dev/null +++ b/ivtest/ivltests/pr735.v @@ -0,0 +1,16 @@ +module main; + + reg [1:-10] foo; + + initial begin + foo = 12'b0000_0000_0100; + + if (foo[-7-1] !== 1'b1) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/pr748.v b/ivtest/ivltests/pr748.v new file mode 100644 index 000000000..72420f07c --- /dev/null +++ b/ivtest/ivltests/pr748.v @@ -0,0 +1,84 @@ +module signed_multiplier_test; + + reg failed_flag = 0; + reg signed [5:0] s_prod; + + wire [2:0] u_pos_two = 3'b010; + wire signed [2:0] s_pos_two = 3'sb010; + wire signed [2:0] s_neg_two = 3'sb110; + + wire s = 1'b1; // flag to indicate signed + wire u = 1'b0; // flag to indicate unsigned + + initial begin + + // unsigned positive two as first argument of multiply + + #1 s_prod = u_pos_two * u_pos_two; + check_mult(1,u,u_pos_two,u,u_pos_two,s_prod,6'sb000100); + + #1 s_prod = u_pos_two * s_pos_two; + check_mult(2,u,u_pos_two,s,s_pos_two,s_prod,6'sb000100); + + // This makes an unsigned result. + #1 s_prod = u_pos_two * s_neg_two; + check_mult(3,u,u_pos_two,s,s_neg_two,s_prod,6'sb001100); + + // signed positive two as first argument of multiply + + #1 s_prod = s_pos_two * u_pos_two; + check_mult(4,s,s_pos_two,u,u_pos_two,s_prod,6'sb000100); + + #1 s_prod = s_pos_two * s_pos_two; + check_mult(5,s,s_pos_two,s,s_pos_two,s_prod,6'sb000100); + + #1 s_prod = s_pos_two * s_neg_two; + check_mult(6,s,s_pos_two,s,s_neg_two,s_prod,6'sb111100); + + // signed negative two as first argument of multiply + + // This makes an unsigned result. + #1 s_prod = s_neg_two * u_pos_two; + check_mult(7,s,s_neg_two,u,u_pos_two,s_prod,6'sb001100); + + #1 s_prod = s_neg_two * s_pos_two; + check_mult(8,s,s_neg_two,s,s_pos_two,s_prod,6'sb111100); + + #1 s_prod = s_neg_two * s_neg_two; + check_mult(9,s,s_neg_two,s,s_neg_two,s_prod,6'sb000100); + + if (failed_flag == 0) + $display("PASSED"); + + $finish; + end + + task check_mult; + input [31:0] idx; + input signeda; + input [ 2:0] arga; + input signedb; + input [ 2:0] argb; + input [ 5:0] result,expected; + + if (result !== expected) begin + failed_flag = 1; + $write("failed: test %0d, ",idx); + + if (signeda) + $write("3'sb%b",arga); + else + $write("3 'b%b",arga); + + $write(" * "); + + if (signedb) + $write("3'sb%b",argb); + else + $write("3 'b%b",argb); + + $write(" = 6'sb%b (expected 6'sb%b)\n",result,expected); + end + endtask + +endmodule diff --git a/ivtest/ivltests/pr751.v b/ivtest/ivltests/pr751.v new file mode 100644 index 000000000..46a0d3e72 --- /dev/null +++ b/ivtest/ivltests/pr751.v @@ -0,0 +1,19 @@ +/* + * From PR#751. + * The (*) can get tangled with a contracted (* *) + */ +module tb; +reg [1:0] sel; +reg [0:3] in; +reg out; +always @(*) + out = in[sel]; +initial +begin + $monitor($time, " %b[%b]: %b", in, sel, out); + #10 in = 4'b 0100; + #10 sel = 0; + #10 sel = 1; + #10 $finish(0); +end +endmodule diff --git a/ivtest/ivltests/pr757.v b/ivtest/ivltests/pr757.v new file mode 100644 index 000000000..c98af4f84 --- /dev/null +++ b/ivtest/ivltests/pr757.v @@ -0,0 +1,18 @@ +module main; + + reg [11:0] sum; + wire [10:0] a = 11'b111_0000_0000; + wire [10:0] b = 11'b000_0000_1111; + + initial begin + #1 sum = $signed(a) + $signed(b); + + if (sum == 12'b1111_0000_1111) + $display("PASSED"); + else + $display("failed: %b",sum); + + $finish; + end + +endmodule diff --git a/ivtest/ivltests/pr772.v b/ivtest/ivltests/pr772.v new file mode 100644 index 000000000..7279fc6bd --- /dev/null +++ b/ivtest/ivltests/pr772.v @@ -0,0 +1,38 @@ +/* + * Based on bug report pr772. + */ + +module err (); + +parameter kuku = "AAAAA"; + + +reg reset_b,clk; +initial begin + reset_b = 0; + repeat (10) @(posedge clk); + #1 reset_b = 1; +end + +initial begin + clk = 1'b1; + #3 forever #10 clk=~clk; +end + + + + + + +always @(posedge clk or negedge reset_b) + if (!reset_b) begin + end + else begin + if ((kuku=="RRRRR") || (kuku=="AAAAA") || (kuku=="BBBBB")) + $display("PASSED"); + else $display("FAILED"); + $finish; + end + + +endmodule diff --git a/ivtest/ivltests/pr809.v b/ivtest/ivltests/pr809.v new file mode 100644 index 000000000..8dd5b7e69 --- /dev/null +++ b/ivtest/ivltests/pr809.v @@ -0,0 +1,33 @@ +module main; + wire [1:0] a2, b2; + wire [2:0] a3, b3; + + target #(.WA(2), .WB(2)) u1 (a2, b2); + target #(.WA(3), .WB(3)) u2 (a3, b3); + + initial begin + $display("u1.WA=%d, $bits(u1.A)=%d", u1.WA, $bits(u1.A)); + $display("u1.WB=%d, $bits(u1.A)=%d", u1.WB, $bits(u1.B)); + + if ($bits(u1.A) != 2) begin + $display("FAILED -- $bits(u1.A) = %d", $bits(u1.A)); + $finish; + end + + if ($bits(u2.A) != 3) begin + $display("FAILED -- $bits(u2.A) = %d", $bits(u2.A)); + $finish; + end + + $display("PASSED"); + end + +endmodule // main + +module target + #(parameter WA = 4, WB = 4) + (input [WA-1:0] A, output [WB-1:0] B); + + assign B = A; + +endmodule // target diff --git a/ivtest/ivltests/pr809b.v b/ivtest/ivltests/pr809b.v new file mode 100644 index 000000000..c1a6e1861 --- /dev/null +++ b/ivtest/ivltests/pr809b.v @@ -0,0 +1,33 @@ +module main; + wire [1:0] a2, b2; + wire [2:0] a3, b3; + + target #(.WA(2), .WB(2)) u1 (a2, b2); + target #(.WA(3), .WB(3)) u2 (a3, b3); + + initial begin + $display("u1.WA=%d, $bits(u1.A)=%d", u1.WA, $bits(u1.A)); + $display("u1.WB=%d, $bits(u1.A)=%d", u1.WB, $bits(u1.B)); + + if ($bits(u1.A) != 2) begin + $display("FAILED -- $bits(u1.A) = %d", $bits(u1.A)); + $finish; + end + + if ($bits(u2.A) != 3) begin + $display("FAILED -- $bits(u2.A) = %d", $bits(u2.A)); + $finish; + end + + $display("PASSED"); + end + +endmodule // main + +module target + #(parameter WA = 4, parameter WB = 4) + (input [WA-1:0] A, output [WB-1:0] B); + + assign B = A; + +endmodule // target diff --git a/ivtest/ivltests/pr810.v b/ivtest/ivltests/pr810.v new file mode 100644 index 000000000..7e19870a4 --- /dev/null +++ b/ivtest/ivltests/pr810.v @@ -0,0 +1,38 @@ +/* + * See PR#810 in the test suite. + */ + +`timescale 1 ns / 1 ps + +module RR64X1_4LA1 (); + +parameter I_AADR_01_DOA_01_T2 = 1.167000; +parameter I_AADR_10_DOA_01_T2 = 1.176000; +parameter taaa_d1 = ( I_AADR_01_DOA_01_T2 > I_AADR_10_DOA_01_T2 ) +? I_AADR_01_DOA_01_T2 : I_AADR_10_DOA_01_T2; +parameter I_AADR_01_DOA_10_T2 = 1.276000; +parameter I_AADR_10_DOA_10_T2 = 1.267000; +parameter taaa_d0 = ( I_AADR_01_DOA_10_T2 > I_AADR_10_DOA_10_T2 ) +? I_AADR_01_DOA_10_T2 : I_AADR_10_DOA_10_T2; +parameter taaa = ( taaa_d1 > taaa_d0 ) ? taaa_d1 : taaa_d0; + + initial begin + if (taaa_d1 != I_AADR_10_DOA_01_T2) begin + $display("FAILED -- taaa_d1=%f", taaa_d1); + $finish; + end + + if (taaa_d0 != I_AADR_01_DOA_10_T2) begin + $display("FAILED -- taaa_d0=%f", taaa_d0); + $finish; + end + + if (taaa != taaa_d0) begin + $display("FAILED -- taaa=%f", taaa); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/pr812.v b/ivtest/ivltests/pr812.v new file mode 100644 index 000000000..df2e8099b --- /dev/null +++ b/ivtest/ivltests/pr812.v @@ -0,0 +1,49 @@ +//////////////////////////////////////////////////////////////////////// +// Copyright 2003 University of Kentucky +// +// This file is released into the public domain +//////////////////////////////////////////////////////////////////////// + +// +// Top level module +// +module top(); + parameter tp = 'd1; + + reg a; + wire b; + + bot b1(b, a); + + initial begin + a = 0; + $display("tp = %d in top", tp); + end +endmodule + + +// +// bottom level module +// + +`define div 0.100 + +module bot(a, b); + input b; + output a; + + real tp; // tp is overridden by tp parameter in top + real tp2; + + assign a = b; + initial begin + tp = 1 / `div; + tp2 = 1 / `div; + $display("tp = %f, tp2 = %f", tp, tp2); + if (tp != 10.0) + $display("tp != 10.0. (tp = %f)", tp); + else + $display("tp == 10, (expected)"); + #1 $display("tp = %f, tp2 = %f", tp, tp2); + end +endmodule diff --git a/ivtest/ivltests/pr820.v b/ivtest/ivltests/pr820.v new file mode 100644 index 000000000..b7cbfe8f3 --- /dev/null +++ b/ivtest/ivltests/pr820.v @@ -0,0 +1,76 @@ +/* Extracted from PR#820. */ + +module main(); + wire clk; + wire reset; + reg [3:0] waddr, raddr; + reg [7:0] wdata; + wire [7:0] rdata; + + clk_reset_gen cg(clk, reset); + + ram_rw #(8,4) r(clk, waddr, wdata, 1'b1, raddr, rdata); + + initial begin + waddr = 4'd0; + raddr = 4'd14; + wdata = 0; + #3001; + $finish(0); + end + + always @(posedge clk) begin + waddr <= #1 waddr + 1; + raddr <= #1 raddr + 1; + wdata <= #1 wdata + 3; + end + + always @(posedge clk) + $display($time,,"waddr wdata %d %d raddr rdata %d %d",waddr,wdata,raddr,rdata); + +endmodule + +module ram_rw(clk,waddr,wdata,we,raddr,rdata); + parameter WDATA = 8; + parameter WADDR = 11; + + input clk; + + input [(WADDR-1):0] waddr; + input [(WDATA-1):0] wdata; + input we; + + input [(WADDR-1):0] raddr; + output [(WDATA-1):0] rdata; + +//local + reg [(WDATA-1):0] mem[0:((1< %b", A, B, select, out); + end + end + +endmodule + + +primitive prim_mux2( output out, input in1, input in0, input select); + +table + +//in1 in0 select : out + 0 0 1 : 0; + 1 1 ? : 1; + 0 ? 1 : 0; + 1 ? 1 : 1; + ? 0 0 : 0; + ? 1 0 : 1; +endtable + +endprimitive diff --git a/ivtest/ivltests/pr938b_std.v b/ivtest/ivltests/pr938b_std.v new file mode 100644 index 000000000..70cfd8fea --- /dev/null +++ b/ivtest/ivltests/pr938b_std.v @@ -0,0 +1,41 @@ +/* + * This is derived from PR#938 in the test suite. + */ +`timescale 1ns/100ps + +module test; + + wire out; + reg A, B, select; + + prim_mux2 mux (out, B, A, select); + + reg [3:0] cnt; + initial begin + $display("A B S out"); + for (cnt = 0 ; cnt <= 'b0111 ; cnt = cnt + 1) begin + A <= cnt[0]; + B <= cnt[1]; + select <= cnt[2]; + + #1 $display("%b %b %b --> %b", A, B, select, out); + end + end + +endmodule + + +primitive prim_mux2( output out, input in1, input in0, input select); + +table + +//in1 in0 select : out + 0 0 1 : 0; + 1 1 ? : 1; + 0 ? 1 : 0; + 1 ? 1 : 1; + ? 0 0 : 0; + ? 1 0 : 1; +endtable + +endprimitive diff --git a/ivtest/ivltests/pr941.v b/ivtest/ivltests/pr941.v new file mode 100644 index 000000000..8bdde54a5 --- /dev/null +++ b/ivtest/ivltests/pr941.v @@ -0,0 +1,21 @@ +/* + * Based on PR#941. + * This tests that trivial contant expressions passed as input to + * user defined tasks will work. A possible bug would be that the + * addition expression gets useless code generated. + */ +module test; + +task foo; +input [16:0] in1; +begin + $display("%d", in1); + $display("PASSED"); +end +endtask + +initial begin + foo(16'h00 + 'h00); +end + +endmodule diff --git a/ivtest/ivltests/pr973.v b/ivtest/ivltests/pr973.v new file mode 100644 index 000000000..93834ef76 --- /dev/null +++ b/ivtest/ivltests/pr973.v @@ -0,0 +1,27 @@ +module main; + + real foo; + + initial begin + foo = 1.0; + if (foo != 1.0) begin + $display("FAILED: Simple assign works not. foo=%f", foo); + $finish; + end + + foo <= 1.5; + if (foo != 1.0) begin + $display("FAILED: nb assign works too fast. foo=%f", foo); + $finish; + end + + #1 if (foo != 1.5) begin + $display("FAILED: nb assign works not. foo=%f", foo); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/pr978.v b/ivtest/ivltests/pr978.v new file mode 100644 index 000000000..53bc46167 --- /dev/null +++ b/ivtest/ivltests/pr978.v @@ -0,0 +1,28 @@ +/* + * This test is based on PR#978. + * Check that user defined functions can have real-valued + * results, and that the result gets properly returned. + */ +module test(); + real m; + + function real dummy; + input b; + begin + dummy=2.5; + end + endfunction + + initial + begin + m=dummy(0); + + if (m != 2.5) begin + $display("FAILED: return result is %f", m); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/pr979.v b/ivtest/ivltests/pr979.v new file mode 100644 index 000000000..1cbb1ec57 --- /dev/null +++ b/ivtest/ivltests/pr979.v @@ -0,0 +1,18 @@ +module test(); +real r; + +initial +begin +r=0.25; +$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r))); +r=0.5; +$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r))); + +$display("neg reals don't work"); +r=-0.25; +$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r))); +r=-0.5; +$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r))); + +end +endmodule diff --git a/ivtest/ivltests/pr985.v b/ivtest/ivltests/pr985.v new file mode 100644 index 000000000..742faa6d7 --- /dev/null +++ b/ivtest/ivltests/pr985.v @@ -0,0 +1,45 @@ +`define ADDR_DEC_W 8 // Number of bits used to decode. +`define ADDR_DEVICE0 `ADDR_DEC_W'h10 // Device 0 located at address 20xx_xxxxh +`define ADDR_DEVICE1 `ADDR_DEC_W'h1F // Device 1 located at address 20xx_xxxxh + +module top ( ) ; + +// Instantiation of the module +// +child_module #(`ADDR_DEC_W, `ADDR_DEVICE0, `ADDR_DEVICE1) my_module ( ); + +initial begin + #1 ; +end + +endmodule + +module child_module ( ); + +// Parameters: +parameter dec_addr_w = 4 ; +parameter t0_addr = 4'd0 ; +parameter t1_addr = 4'd0 ; + +// Instantiation of the grandchild module +// +grandchild_module #(dec_addr_w, t0_addr, t1_addr) my_grandchild_module ( ); + +initial begin + $display ("CHILD parameters are: %h %h %h", dec_addr_w, t0_addr, t1_addr) ; +end + +endmodule + +module grandchild_module ( ); + +// Parameters: +parameter dec_addr_w = 4 ; +parameter t0_addr = 4'd0 ; +parameter t1_addr = 4'd0 ; + +initial begin + $display ("GRANDCHILD parameters are: %h %h %h", dec_addr_w, t0_addr, t1_addr) ; +end + +endmodule diff --git a/ivtest/ivltests/pr987.v b/ivtest/ivltests/pr987.v new file mode 100644 index 000000000..b18feb157 --- /dev/null +++ b/ivtest/ivltests/pr987.v @@ -0,0 +1,21 @@ +/* + * This test program should cause the message "Hello, World" to + * display twice. The first when the always thread runs and gets + * stuck in the wait, and the second when the block is disabled, + * and the alwas thread starts it over again. + */ + +module main; + + always begin :restartable + $display("Test thread runs."); + wait (0); + $display("FAILED: Should never get here."); + end + + initial begin + #10 disable restartable; + #10 $finish(0); + end + +endmodule // main diff --git a/ivtest/ivltests/pr990.v b/ivtest/ivltests/pr990.v new file mode 100644 index 000000000..d091915d1 --- /dev/null +++ b/ivtest/ivltests/pr990.v @@ -0,0 +1,23 @@ +/* + * This is a reuced version of PR#990, that captures the essence. + * Or at least the bug being reported. + */ +module bug(); + +reg [31:0] x; +wire y; + +assign y = x == 0; + +initial begin + $display("y: %b", y); + x = 0; + #0; + $display("y: %b", y); + if (y === 1'b1) // if x is 0, then x==0 is 1. + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule // bug diff --git a/ivtest/ivltests/pr991.v b/ivtest/ivltests/pr991.v new file mode 100644 index 000000000..c81ba1635 --- /dev/null +++ b/ivtest/ivltests/pr991.v @@ -0,0 +1,22 @@ +/* + * This test file is based on PR991. + */ + +module bug(); + wire _d1,_d2,test,test1,test2,test3; + assign _d1 = 1; + assign _d2 = 0; + assign test = (_d1 && _d2) != 0; + assign test1 = (_d1 && _d2) == 0; + assign test2 = (_d1 && _d2) !== 0; + assign test3 = (_d1 && _d2) === 0; + initial begin + #1; + $displayb(_d2); // Should be 0 + $displayb(test); // Should be 0 (1 && 0) != 0 --> 0 != 0 + $displayb(test1); // Should be 1 + $displayb(test2); // Should be 0 + $displayb(test3); // Should be 1 + end + +endmodule diff --git a/ivtest/ivltests/pr993.v b/ivtest/ivltests/pr993.v new file mode 100644 index 000000000..b04fbb9e6 --- /dev/null +++ b/ivtest/ivltests/pr993.v @@ -0,0 +1,29 @@ +/* + * This example is a distillation of the essence of PR#993. + * Or at least the essence that led to a bug report. + */ + +module main; + + integer length; + wire [31:0] length_bits = ((length * 8 )/11)+(((length * 8 )%11) != 0); + + reg [31:0] length_bits2; + + initial begin + for (length = 1 ; length < 56 ; length = length + 1) begin + length_bits2 = ((length * 8 )/11)+(((length * 8 )%11) != 0); + + #1 $display("length=%3d, length_bits=%3d (%3d)", + length, length_bits, length_bits2); + + if (length_bits != length_bits2) begin + $display("FAILED - Expressions have different results."); + $finish; + end + end // for (length = 1 ; length < 56 ; length = length + 1) + + $finish(0); + end + +endmodule // main diff --git a/ivtest/ivltests/pr995.v b/ivtest/ivltests/pr995.v new file mode 100644 index 000000000..09556fbd3 --- /dev/null +++ b/ivtest/ivltests/pr995.v @@ -0,0 +1,46 @@ +/* + * This test runs the random number generator to make sure + * it follows the standard algorithm. It is based on the bug + * report from PR#995. + */ + +module pr995 (); + integer seed; + integer i; + integer result; + + initial begin + seed = 1; + $display ("Start sequence: seed=%h", seed); + + result=$random(seed); + $display ("seed=%h result=%h", seed, result); + + for (i=0; i<30; i=i+1) begin + result=$random(seed); + $display ("seed=%h result=%h", seed, result); + end + + seed = 2; + $display ("Start sequence: seed=%h", seed); + + result=$random(seed); + $display ("seed=%h result=%h", seed, result); + + for (i=0; i<30; i=i+1) begin + result=$random(seed); + $display ("seed=%h result=%h", seed, result); + end + + seed = 1; + $display ("Start sequence: seed=%h", seed); + + result=$random(seed); + $display ("seed=%h result=%h", seed, result); + + for (i=0; i<30; i=i+1) begin + result=$random(seed); + $display ("seed=%h result=%h", seed, result); + end + end +endmodule // rand diff --git a/ivtest/ivltests/prng.v b/ivtest/ivltests/prng.v new file mode 100644 index 000000000..46f122433 --- /dev/null +++ b/ivtest/ivltests/prng.v @@ -0,0 +1,40 @@ +// +// Verifies that the PRNG seed streams are unique, well trys anyway. +// +module test; + reg [31:0] rtn; + reg [31:0] pseed, seed1, seed2; + reg [31:0] mem1[3:0], mem2[3:0]; + integer i; + + initial begin + seed1 = 32'hcafe_babe; + seed2 = 32'hdead_beef; + + // Isolated stream + for (i = 0; i < 4; i = i + 1) begin + mem1[i] = $random(seed1); + end + + // Pull from multiple streams + seed1 = 32'hcafe_babe; + seed2 = 32'hdead_beef; + for (i = 0; i < 4; i = i + 1) begin + mem2[i] = $random(seed1); + // pull more values from other pools + rtn = $random(seed2); + rtn = $random; + end + + // Verify the seed1 streams match + for (i = 0; i < 4; i = i + 1) begin + if (mem1[i] != mem2[i]) begin + $display("FAILED %0d: %x != %x", i, mem1[i], mem2[i]); + $finish; + end + end + + $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/program2.v b/ivtest/ivltests/program2.v new file mode 100644 index 000000000..d010de5df --- /dev/null +++ b/ivtest/ivltests/program2.v @@ -0,0 +1,24 @@ +// This program block demonstrates that initial and final blocks +// work, and that program variables work as well. +program main; + + int foo; + int bar; + + initial begin + bar = 1; + for (foo = 1 ; foo < 10 ; ++foo) begin + bar = bar * foo; + $display("foo = %d, bar=%d", foo, bar); + end + end + + final begin + if (foo !== 10 || bar !== 362_880) begin + $display("FAILED -- foo=%d", foo); + end else begin + $display("PASSED"); + end + end + +endprogram // main diff --git a/ivtest/ivltests/program2b.v b/ivtest/ivltests/program2b.v new file mode 100644 index 000000000..5b08f3046 --- /dev/null +++ b/ivtest/ivltests/program2b.v @@ -0,0 +1,20 @@ +program main; + + int foo; + int bar; + + initial begin + bar = 1; + for (foo = 1 ; foo < 10 ; ++foo) begin + bar <= bar * foo; + #1 $display("foo = %d, bar=%d", foo, bar); + end + end + + final begin + if (foo !== 10 || bar !== 362_880) begin + $display("FAILED -- foo=%d", foo); + end else $display("PASSED"); + end + +endprogram // main diff --git a/ivtest/ivltests/program3.v b/ivtest/ivltests/program3.v new file mode 100644 index 000000000..8c3d6f530 --- /dev/null +++ b/ivtest/ivltests/program3.v @@ -0,0 +1,31 @@ +// This test program shows how programs can be contained by +// modules, and can access variables in the context. +module main; + + reg[7:0] shared; + wire [7:0] not_shared = ~shared; + +program test1; + initial shared <= 'h55; +endprogram :test1 + +program test2; + reg [7:0] tmp; + final begin + if (shared !== 'h55) begin + $display("FAILED -- shared=%b is not correct", shared); + $finish; + end + + tmp = ~shared; + if (not_shared !== 'haa || not_shared !== tmp) begin + $display("FAILED -- not_shared is not correct", not_shared); + $finish; + end + + $display("PASSED"); + end + +endprogram :test2 + +endmodule // main diff --git a/ivtest/ivltests/program3a.v b/ivtest/ivltests/program3a.v new file mode 100644 index 000000000..b106c8bc5 --- /dev/null +++ b/ivtest/ivltests/program3a.v @@ -0,0 +1,31 @@ +// This should generate an error + +module main; + + reg[7:0] shared; + wire [7:0] not_shared = ~shared; + +program test1; + initial shared = 'h55; // ERROR: only non-blocking assign allowed here. +endprogram :test1 + +program test2; + reg [7:0] tmp; + final begin + if (shared !== 'h55) begin + $display("FAILED -- shared=%b is not correct", shared); + $finish; + end + + tmp = ~shared; + if (not_shared !== 'haa) begin + $display("FAILED == not_shared is not correct", not_shared); + $finish; + end + + $display("PASSED"); + end + +endprogram :test2 + +endmodule // main diff --git a/ivtest/ivltests/program3b.v b/ivtest/ivltests/program3b.v new file mode 100644 index 000000000..4541a8831 --- /dev/null +++ b/ivtest/ivltests/program3b.v @@ -0,0 +1,31 @@ +// This should generate an error + +module main; + + reg[7:0] shared; + wire [7:0] not_shared = ~shared; + +program test1; + initial shared <= 'h55; +endprogram :test1 + +program test2; + reg [7:0] tmp; + final begin + if (shared !== 'h55) begin + $display("FAILED -- shared=%b is not correct", shared); + $finish; + end + + tmp <= ~shared; // ERROR: only blocking assign in final block + if (not_shared !== 'haa) begin + $display("FAILED -- not_shared is not correct", not_shared); + $finish; + end + + $display("PASSED"); + end + +endprogram :test2 + +endmodule // main diff --git a/ivtest/ivltests/program4.v b/ivtest/ivltests/program4.v new file mode 100644 index 000000000..0a2a0ef8f --- /dev/null +++ b/ivtest/ivltests/program4.v @@ -0,0 +1,29 @@ +// This test program shows how programs can be instantiated +// within another module. + +program test(input [7:0] sh1, input [7:0] sh2); + + final begin + if (sh1 !== 'h55) begin + $display("FAILED -- shared=%b is not correct", sh1); + $finish; + end + + if (sh2 !== 'haa) begin + $display("FAILED -- sh2 not correct", sh2); + $finish; + end + + $display("PASSED"); + end + +endprogram :test + +module main; + + reg[7:0] shared = 'h55; + wire [7:0] not_shared = ~shared; + + test check(shared, not_shared); + +endmodule // main diff --git a/ivtest/ivltests/program5a.v b/ivtest/ivltests/program5a.v new file mode 100644 index 000000000..684d22d4e --- /dev/null +++ b/ivtest/ivltests/program5a.v @@ -0,0 +1,10 @@ +program main; + + reg foo; + +// It is NOT legal to nest modules in program blocks. +module test; + initial $display("FAILED"); +endmodule // test + +endprogram // main diff --git a/ivtest/ivltests/program5b.v b/ivtest/ivltests/program5b.v new file mode 100644 index 000000000..98b83684c --- /dev/null +++ b/ivtest/ivltests/program5b.v @@ -0,0 +1,13 @@ +module test(input wire foo); + initial $display("FAILED", foo); + final $display(foo); +endmodule // test + +program main; + + reg foo = 1; + + // It is not legal to instantiate modules in program blocks + test dut(foo); + +endprogram // main diff --git a/ivtest/ivltests/program_hello.v b/ivtest/ivltests/program_hello.v new file mode 100644 index 000000000..5d50a9b26 --- /dev/null +++ b/ivtest/ivltests/program_hello.v @@ -0,0 +1,10 @@ +// This is the most trivial example of a program block. +// It contains only an initial statement and final statement, +// and prints "PASSED" so the test bench knows that it works. + +program main (); + + initial $display("Hello, World."); + final $display("PASSED"); + +endprogram : main diff --git a/ivtest/ivltests/program_hello2.v b/ivtest/ivltests/program_hello2.v new file mode 100644 index 000000000..824a975e7 --- /dev/null +++ b/ivtest/ivltests/program_hello2.v @@ -0,0 +1,10 @@ +// This trivial program is NOT valid. "always" blocks are not +// valid in program blocks. + +program main (); + + initial $display("Hello, World."); + always #1 $finish; + final $display("FAILED"); + +endprogram : main diff --git a/ivtest/ivltests/ptest001.v b/ivtest/ivltests/ptest001.v new file mode 100644 index 000000000..932a91c88 --- /dev/null +++ b/ivtest/ivltests/ptest001.v @@ -0,0 +1,51 @@ +// +// Copyright (c) 1999 Peter Monta (pmonta@imedia.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + reg clk,reset; + wire [3:0] a,b; + + swap s(clk,reset,a,b); + + initial begin + clk = 0; + reset = 0; + #1; reset = 1; #1; reset = 0; + #1; clk = 1; #5; clk = 0; + if (a===4'd6 && b===4'd5) + $display("PASSED"); + else + $display("FAILED"); + end +endmodule + +module swap(clk,reset,a,b); + input clk,reset; + output [3:0] a,b; + reg [3:0] a,b; + + always @(posedge clk or posedge reset) + if (reset) begin + a <= #1 4'd5; + b <= #1 4'd6; + end else begin + a <= #1 b; + b <= #1 a; + end +endmodule diff --git a/ivtest/ivltests/ptest002.v b/ivtest/ivltests/ptest002.v new file mode 100644 index 000000000..ce79d7d45 --- /dev/null +++ b/ivtest/ivltests/ptest002.v @@ -0,0 +1,33 @@ +// +// Copyright (c) 1999 Peter Monta (pmonta@imedia.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + reg [3:0] b; + wire [1:0] a; + assign a = b[3:2] + 1; + + initial begin + b = 4'b1011; + #1; + if (a===2'b11) + $display("PASSED"); + else + $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/ptest003.v b/ivtest/ivltests/ptest003.v new file mode 100644 index 000000000..f7f495a46 --- /dev/null +++ b/ivtest/ivltests/ptest003.v @@ -0,0 +1,35 @@ +// +// Copyright (c) 1999 Peter Monta (pmonta@imedia.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + parameter PARM = 2; + reg [3:0] b; + wire [1:0] a; + + assign a = b[3:(3-PARM+1)] + 1; + + initial begin + b = 4'b1011; + #1; + if (a===2'b11) + $display("PASSED"); + else + $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/ptest004.v b/ivtest/ivltests/ptest004.v new file mode 100644 index 000000000..1451b4568 --- /dev/null +++ b/ivtest/ivltests/ptest004.v @@ -0,0 +1,37 @@ +// +// Copyright (c) 1999 Peter Monta (pmonta@imedia.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + wire [3:0] b; + reg [1:0] a; + reg c; + + assign b = c<>"); + + case ( sig[3:0] ) + 4'b0000: thing[0] = 1'b1; + 4'b0010: thing[2] = 1'b1; + 4'b0011: thing[9] = 1'b1; + endcase // case( sig[3:0] ) + + $display ("<< END >>\n"); + $finish; + end + + // Waves definition +// initial +// begin +// $dumpfile("out.dump"); +// $dumpvars(0, main); +// end + +endmodule // main diff --git a/ivtest/ivltests/range2.v b/ivtest/ivltests/range2.v new file mode 100644 index 000000000..97ec3d02b --- /dev/null +++ b/ivtest/ivltests/range2.v @@ -0,0 +1,10 @@ +/* + * This is frpm PR#138. It is supposed to generate an error. + */ +module bug; + wire[1:0] dout; + wire[1:0] din; + + assign dout = din[3:2]; + /* foo.vl:9: bit/part select [3:2] out of range for bug.din */ +endmodule diff --git a/ivtest/ivltests/range3.v b/ivtest/ivltests/range3.v new file mode 100644 index 000000000..586a5a417 --- /dev/null +++ b/ivtest/ivltests/range3.v @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Detect that b is declared as a scaler and a vector. + */ +module simple (a, b); +input [7:0] a; +output [7:0] b; +reg b; // Error here! + +always @(a) + begin + b = a; + end + +endmodule diff --git a/ivtest/ivltests/readmem-error.txt b/ivtest/ivltests/readmem-error.txt new file mode 100644 index 000000000..37aa72138 --- /dev/null +++ b/ivtest/ivltests/readmem-error.txt @@ -0,0 +1 @@ +uuuuuuuu diff --git a/ivtest/ivltests/readmem-error.v b/ivtest/ivltests/readmem-error.v new file mode 100644 index 000000000..aba9d36a9 --- /dev/null +++ b/ivtest/ivltests/readmem-error.v @@ -0,0 +1,226 @@ +module top; + reg [24*8-1:0] str; + real rval; + reg [7:0] array [0:7]; + reg [7:0] array2 [8:15]; + reg [7:0] array3 [-1:7]; + integer idx, istr; + + task clear_array; + for (idx = 0; idx < 8; idx = idx + 1) begin + array[idx] = 0; + array2[idx+8] = 0; + end + endtask + + initial begin + // An invalid string. + $readmemb(str, array); + $readmemb(istr, array); + + // Check a valid string. + str = "ivltests/readmemb.txt"; + $readmemb(str, array); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (array[idx] !== idx + 1) begin + $display("Failed: for index %0d of readmemb 1, expected %0d, got %0d", + idx, idx+1, array[idx]); + end + end + + // Check a string with a non-printing character. + str[7:0] = 'd2; + $readmemb(str, array); + + // This should load, but will print a warning about the real. + rval = 0.0; + clear_array; + $readmemb("ivltests/readmemb.txt", array, rval); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (array[idx] !== idx + 1) begin + $display("Failed: for index %0d of readmemb 2, expected %0d, got %0d", + idx, idx+1, array[idx]); + end + end + + // This should load, but will print a warning about the real. + rval = 7.0; + clear_array; + $readmemb("ivltests/readmemb.txt", array, 0, rval); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (array[idx] !== idx + 1) begin + $display("Failed: for index %0d of readmemb 3, expected %0d, got %0d", + idx, idx+1, array[idx]); + end + end + + // These should not load the array. + clear_array; + $readmemb("ivltests/readmemb.txt", array, -1, 7); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (array[idx] !== 0) begin + $display("Failed: for index %0d of readmemb 4, expected 0, got %0d", + idx, array[idx]); + end + end + + $readmemb("ivltests/readmemb.txt", array2, 7, 15); + for (idx = 8; idx < 16; idx = idx + 1) begin + if (array2[idx] !== 0) begin + $display("Failed: for index %0d of readmemb 5, expected 0, got %0d", + idx, array2[idx]); + end + end + + $readmemb("ivltests/readmemb.txt", array, 0, 8); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (array[idx] !== 0) begin + $display("Failed: for index %0d of readmemb 6, expected 0, got %0d", + idx, array[idx]); + end + end + + $readmemb("ivltests/readmemb.txt", array2, 8, 16); + for (idx = 8; idx < 16; idx = idx + 1) begin + if (array2[idx] !== 0) begin + $display("Failed: for index %0d of readmemb 7, expected 0, got %0d", + idx, array2[idx]); + end + end + + // Check that a warning is printed if we have the wrong number of values. + clear_array; + $readmemb("ivltests/readmemb.txt", array, 0, 6); + for (idx = 0; idx < 7; idx = idx + 1) begin + if (array[idx] !== idx + 1) begin + $display("Failed: for index %0d of readmemb 8, expected %0d, got %0d", + idx, idx+1, array[idx]); + end + end + if (array[7] !== 0) begin + $display("Failed: for index 7 of readmemb 8, expected 0, got %0d", + array[7]); + end + + $readmemb("ivltests/readmemb.txt", array3, -1, 7); + for (idx = -1; idx < 7; idx = idx + 1) begin + if ($signed(array3[idx]) !== idx + 2) begin + $display("Failed: for index %0d of readmemb 9, expected %0d, got %0d", + idx, idx+2, array3[idx]); + end + end + if (array3[7] !== 8'bx) begin + $display("Failed: for index 7 of readmemb 9, expected 'dx, got %0d", + array3[7]); + end + + // Check what an invalid token returns. + $readmemb("ivltests/readmem-error.txt", array); + + + // An invalid string. + str = 'bx; + $readmemh(str, array); + $readmemh(istr, array); + + // Check a valid string. + str = "ivltests/readmemh.txt"; + $readmemh(str, array); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (array[idx] !== idx + 1) begin + $display("Failed: for index %0d of readmemh 1, expected %0d, got %0d", + idx, idx+1, array[idx]); + end + end + + // Check a string with a non-printing character. + str[7:0] = 'd2; + $readmemh(str, array); + + // This should load, but will print a warning about the real. + rval = 0.0; + clear_array; + $readmemh("ivltests/readmemh.txt", array, rval); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (array[idx] !== idx + 1) begin + $display("Failed: for index %0d of readmemh 2, expected %0d, got %0d", + idx, idx+1, array[idx]); + end + end + + // This should load, but will print a warning about the real. + rval = 7.0; + clear_array; + $readmemh("ivltests/readmemh.txt", array, 0, rval); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (array[idx] !== idx + 1) begin + $display("Failed: for index %0d of readmemh 3, expected %0d, got %0d", + idx, idx+1, array[idx]); + end + end + + // These should not load the array. + clear_array; + $readmemh("ivltests/readmemh.txt", array, -1, 7); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (array[idx] !== 0) begin + $display("Failed: for index %0d of readmemh 4, expected 0, got %0d", + idx, array[idx]); + end + end + + $readmemh("ivltests/readmemh.txt", array2, 7, 15); + for (idx = 8; idx < 16; idx = idx + 1) begin + if (array2[idx] !== 0) begin + $display("Failed: for index %0d of readmemh 5, expected 0, got %0d", + idx, array2[idx]); + end + end + + $readmemh("ivltests/readmemh.txt", array, 0, 8); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (array[idx] !== 0) begin + $display("Failed: for index %0d of readmemh 6, expected 0, got %0d", + idx, array[idx]); + end + end + + $readmemh("ivltests/readmemh.txt", array2, 8, 16); + for (idx = 8; idx < 16; idx = idx + 1) begin + if (array2[idx] !== 0) begin + $display("Failed: for index %0d of readmemh 7, expected 0, got %0d", + idx, array2[idx]); + end + end + + // Check that a warning is printed if we have the wrong number of values. + clear_array; + $readmemh("ivltests/readmemh.txt", array, 0, 6); + for (idx = 0; idx < 7; idx = idx + 1) begin + if (array[idx] !== idx + 1) begin + $display("Failed: for index %0d of readmemh 8, expected %0d, got %0d", + idx, idx+1, array[idx]); + end + end + if (array[7] !== 0) begin + $display("Failed: for index 7 of readmemh 8, expected 0, got %0d", + array[7]); + end + + $readmemh("ivltests/readmemh.txt", array3, -1, 7); + for (idx = -1; idx < 7; idx = idx + 1) begin + if ($signed(array3[idx]) !== idx + 2) begin + $display("Failed: for index %0d of readmemh 9, expected %0d, got %0d", + idx, idx+2, array3[idx]); + end + end + if (array3[7] !== 8'bx) begin + $display("Failed: for index 7 of readmemh 9, expected 'dx, got %0d", + array3[7]); + end + + // Check what an invalid token returns. + $readmemh("ivltests/readmem-error.txt", array); + + end +endmodule diff --git a/ivtest/ivltests/readmem-invalid.v b/ivtest/ivltests/readmem-invalid.v new file mode 100644 index 000000000..4497f46f0 --- /dev/null +++ b/ivtest/ivltests/readmem-invalid.v @@ -0,0 +1,21 @@ +module top; + reg [7:0] array [7:0]; + + initial begin + $readmemb(); + $readmemb(top); + $readmemb("ivltests/readmemb.txt"); + $readmemb("ivltests/readmemb.txt", top); + $readmemb("ivltests/readmemb.txt", array, top); + $readmemb("ivltests/readmemb.txt", array, 0, top); + $readmemb("ivltests/readmemb.txt", array, 0, 7, top); + + $readmemh(); + $readmemh(top); + $readmemh("ivltests/readmemh.txt"); + $readmemh("ivltests/readmemh.txt", top); + $readmemh("ivltests/readmemh.txt", array, top); + $readmemh("ivltests/readmemh.txt", array, 0, top); + $readmemh("ivltests/readmemh.txt", array, 0, 7, top); + end +endmodule diff --git a/ivtest/ivltests/readmemb.txt b/ivtest/ivltests/readmemb.txt new file mode 100644 index 000000000..2d3da4f51 --- /dev/null +++ b/ivtest/ivltests/readmemb.txt @@ -0,0 +1,8 @@ +00000001 +00000010 +00000011 +00000100 +00000101 +00000110 +00000111 +00001000 diff --git a/ivtest/ivltests/readmemb1.dat b/ivtest/ivltests/readmemb1.dat new file mode 100644 index 000000000..c26b12d92 --- /dev/null +++ b/ivtest/ivltests/readmemb1.dat @@ -0,0 +1,8 @@ +0000_0000 +00000001 +000__0_0010 +0000_0011 +0000_0100 +0000_0101 +0000_0110 +0000_0111 diff --git a/ivtest/ivltests/readmemb1.v b/ivtest/ivltests/readmemb1.v new file mode 100644 index 000000000..ec3d34a4c --- /dev/null +++ b/ivtest/ivltests/readmemb1.v @@ -0,0 +1,48 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Initial readmemb function - length of data = array size. +// +// + +module main (); + +reg [7:0] array [0:7]; +reg error ; +reg [3:0] count; + +initial + begin + error = 0; + $readmemb("ivltests/readmemb1.dat",array); + + for(count = 0; count <= 7; count = count + 1) + begin + if(array[count[2:0]] !== count) + begin + error = 1; + $display("FAILED - array[count] == %h, s/b %h", + array[count],count); + end + end + + if(error == 0) + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/readmemb2.dat b/ivtest/ivltests/readmemb2.dat new file mode 100644 index 000000000..fb9f1c902 --- /dev/null +++ b/ivtest/ivltests/readmemb2.dat @@ -0,0 +1,4 @@ +0000_0000 +00000001 +000__0_0010 +0000_0011 diff --git a/ivtest/ivltests/readmemb2.v b/ivtest/ivltests/readmemb2.v new file mode 100644 index 000000000..0b24442d5 --- /dev/null +++ b/ivtest/ivltests/readmemb2.v @@ -0,0 +1,60 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: readmemb function - data file length less than array +// +// + +module main (); + +reg [7:0] array [0:7]; +reg error ; +reg [3:0] count; + +initial + begin + error = 0; + + /* pre init the array to all zeroes. */ + for(count = 0; count <= 7; count = count + 1) + array[count] = 8'h0; + + $readmemb("ivltests/readmemb2.dat",array); + + for(count = 0; count <= 3; count = count + 1) + begin + if(array[count[2:0]] !== count) + begin + error = 1; + $display("FAILED - array[count] == %h, s/b %h", + array[count],count); + end + end + + if(array[4] !== 8'h0) + begin + error = 1; + $display("FAILED - array[4] == %h, s/b 0", + array[count]); + end + + if(error == 0) + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/readmemb3.v b/ivtest/ivltests/readmemb3.v new file mode 100644 index 000000000..040fc9f3a --- /dev/null +++ b/ivtest/ivltests/readmemb3.v @@ -0,0 +1,60 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: readmemb function - Only read part of data file +// +// + +module main (); + +reg [7:0] array [0:7]; +reg error ; +reg [3:0] count; + +initial + begin + error = 0; + + /* pre init the array to all zeroes. */ + for(count = 0; count <= 7; count = count + 1) + array[count] = 8'h0; + + $readmemb("ivltests/readmemb1.dat",array,0,3); + + for(count = 0; count <= 3; count = count + 1) + begin + if(array[count[2:0]] !== count) + begin + error = 1; + $display("FAILED - array[count] == %h, s/b %h", + array[count],count); + end + end + + if(array[4] !== 8'h0) + begin + error = 1; + $display("FAILED - array[4] == %h, s/b 0", + array[count]); + end + + if(error == 0) + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/readmemh.txt b/ivtest/ivltests/readmemh.txt new file mode 100644 index 000000000..535d2b01d --- /dev/null +++ b/ivtest/ivltests/readmemh.txt @@ -0,0 +1,8 @@ +1 +2 +3 +4 +5 +6 +7 +8 diff --git a/ivtest/ivltests/readmemh1.dat b/ivtest/ivltests/readmemh1.dat new file mode 100644 index 000000000..95caba1b1 --- /dev/null +++ b/ivtest/ivltests/readmemh1.dat @@ -0,0 +1,8 @@ +0 +1 +2 +3 +4 +5 +6 +7 diff --git a/ivtest/ivltests/readmemh1.v b/ivtest/ivltests/readmemh1.v new file mode 100644 index 000000000..af9385fd7 --- /dev/null +++ b/ivtest/ivltests/readmemh1.v @@ -0,0 +1,48 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Initial readmemh function - length of data = array size. +// +// + +module main (); + +reg [7:0] array [0:7]; +reg error ; +reg [3:0] count; + +initial + begin + error = 0; + $readmemh("ivltests/readmemh1.dat",array); + + for(count = 0; count <= 7; count = count + 1) + begin + if(array[count[2:0]] !== count) + begin + error = 1; + $display("FAILED - array[count] == %h, s/b %h", + array[count],count); + end + end + + if(error == 0) + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/readmemh1a.dat b/ivtest/ivltests/readmemh1a.dat new file mode 100644 index 000000000..c0ebff4c9 --- /dev/null +++ b/ivtest/ivltests/readmemh1a.dat @@ -0,0 +1,11 @@ +@2 +2 +3 +@0 +0 +1 +@4 +4 +5 +6 +7 diff --git a/ivtest/ivltests/readmemh1a.v b/ivtest/ivltests/readmemh1a.v new file mode 100644 index 000000000..2f29c7992 --- /dev/null +++ b/ivtest/ivltests/readmemh1a.v @@ -0,0 +1,48 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Initial readmemh function - length of data = array size. +// +// + +module main (); + +reg [7:0] array [0:7]; +reg error ; +reg [3:0] count; + +initial + begin + error = 0; + $readmemh("ivltests/readmemh1a.dat",array); + + for(count = 0; count <= 7; count = count + 1) + begin + if(array[count[2:0]] !== count) + begin + error = 1; + $display("FAILED - array[count] == %h, s/b %h", + array[count],count); + end + end + + if(error == 0) + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/readmemh2.dat b/ivtest/ivltests/readmemh2.dat new file mode 100644 index 000000000..bc856dafa --- /dev/null +++ b/ivtest/ivltests/readmemh2.dat @@ -0,0 +1,4 @@ +0 +1 +2 +3 diff --git a/ivtest/ivltests/readmemh2.v b/ivtest/ivltests/readmemh2.v new file mode 100644 index 000000000..6ba4a79d5 --- /dev/null +++ b/ivtest/ivltests/readmemh2.v @@ -0,0 +1,60 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: readmemh function - data file length less than array +// +// + +module main (); + +reg [7:0] array [0:7]; +reg error ; +reg [3:0] count; + +initial + begin + error = 0; + + /* pre init the array to all zeroes. */ + for(count = 0; count <= 7; count = count + 1) + array[count] = 8'h0; + + $readmemh("ivltests/readmemh2.dat",array); + + for(count = 0; count <= 3; count = count + 1) + begin + if(array[count[2:0]] !== count) + begin + error = 1; + $display("FAILED - array[count] == %h, s/b %h", + array[count],count); + end + end + + if(array[4] !== 8'h0) + begin + error = 1; + $display("FAILED - array[4] == %h, s/b 0", + array[count]); + end + + if(error == 0) + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/readmemh3.v b/ivtest/ivltests/readmemh3.v new file mode 100644 index 000000000..2da4fc955 --- /dev/null +++ b/ivtest/ivltests/readmemh3.v @@ -0,0 +1,60 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: readmemh function - Read less data than length of array +// +// + +module main (); + +reg [7:0] array [0:7]; +reg error ; +reg [3:0] count; + +initial + begin + error = 0; + + /* pre init the array to all zeroes. */ + for(count = 0; count <= 7; count = count + 1) + array[count] = 8'h0; + + $readmemh("ivltests/readmemh1.dat",array,0,3); + + for(count = 0; count <= 3; count = count + 1) + begin + if(array[count[2:0]] !== count) + begin + error = 1; + $display("FAILED - array[count] == %h, s/b %h", + array[count],count); + end + end + + if(array[4] !== 8'h0) + begin + error = 1; + $display("FAILED - array[4] == %h, s/b 0", + array[count]); + end + + if(error == 0) + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/readmemh4.dat b/ivtest/ivltests/readmemh4.dat new file mode 100644 index 000000000..9d8abc515 --- /dev/null +++ b/ivtest/ivltests/readmemh4.dat @@ -0,0 +1,10 @@ +0 +1 +// Comments in the file +2 +3 +4 +5 +// And can have comments here too +6 +7 diff --git a/ivtest/ivltests/readmemh4.v b/ivtest/ivltests/readmemh4.v new file mode 100644 index 000000000..b10fb2669 --- /dev/null +++ b/ivtest/ivltests/readmemh4.v @@ -0,0 +1,48 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: readmemh function - comments in data file +// +// + +module main (); + +reg [7:0] array [0:7]; +reg error ; +reg [3:0] count; + +initial + begin + error = 0; + $readmemh("ivltests/readmemh4.dat",array); + + for(count = 0; count <= 7; count = count + 1) + begin + if(array[count[2:0]] !== count) + begin + error = 1; + $display("FAILED - array[count] == %h, s/b %h", + array[count],count); + end + end + + if(error == 0) + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/readmemh5.v b/ivtest/ivltests/readmemh5.v new file mode 100644 index 000000000..eaf10e1a2 --- /dev/null +++ b/ivtest/ivltests/readmemh5.v @@ -0,0 +1,38 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: readmemh function - Check that MEMNAME [ 0:x] caught as compile error +// +// + +module main (); + +reg [7:0] array [0:7]; +reg error ; +reg [3:0] count; + +initial + begin + error = 0; + + /* pre init the array to all zeroes. */ + + $readmemh("ivltests/readmemh1.dat",array [0:7]); + + end +endmodule diff --git a/ivtest/ivltests/real.v b/ivtest/ivltests/real.v new file mode 100644 index 000000000..628e85ca3 --- /dev/null +++ b/ivtest/ivltests/real.v @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program checks that some basics of real value support work. + */ +module main; + + realtime x; + real a3, a4; + + initial begin + a3 = 0.3; + a4 = 0.4; + + x = 2 * a4 + a3; + + $display("a3 = %f, a4 = %f, x = %f", a3, a4, x); + if (x > 1.1001) begin + $display("FAILED"); + $finish; + end + if (x < 1.0999) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/real10.v b/ivtest/ivltests/real10.v new file mode 100644 index 000000000..c6dc87b4f --- /dev/null +++ b/ivtest/ivltests/real10.v @@ -0,0 +1,16 @@ +module main; + + reg [3:0] tmp; + + initial begin + tmp = 10.7; + + if (tmp !== 4'd11) begin + $display("FAILED -- Incorrect rounding: tmp=%b", tmp); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/real11.v b/ivtest/ivltests/real11.v new file mode 100644 index 000000000..6e89f9a34 --- /dev/null +++ b/ivtest/ivltests/real11.v @@ -0,0 +1,35 @@ +/* +* This tests the case that a delay value is a calculated real value. +*/ +module main; + + real test; + + wire [3:0] Q; + reg [3:0] D; + assign #(test/2.0) Q = D; + + initial begin + test = 4.0; + + D = 1; + #(test) if (Q !== 1) begin + $display("FAILED -- %0t: Q=%d, D=%d", $time, Q, D); + $finish; + end + + D = 2; + #(test/4) if (Q !== 1) begin + $display("FAILED -- %0t: Q=%d, D=%d", $time, Q, D); + $finish; + end + + #(test/2) if (Q !== 2) begin + $display("FAILED -- %0t: Q=%d, D=%d", $time, Q, D); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/real2.v b/ivtest/ivltests/real2.v new file mode 100644 index 000000000..3743b6a3c --- /dev/null +++ b/ivtest/ivltests/real2.v @@ -0,0 +1,36 @@ +// +// Copyright (c) 2003 Steve Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + + parameter offset = 7.0; + time result; + initial begin + #9 result = $time + offset; + $display("result = %d", result); + if (result !== 64'd16) begin + $display("FAILED -- incorrect result"); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/real3.v b/ivtest/ivltests/real3.v new file mode 100644 index 000000000..1fa8bd281 --- /dev/null +++ b/ivtest/ivltests/real3.v @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2003 Michael Ruff (mruff @ chiaro.com) + * + * This source code is free software; rou can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at rour option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + * $Id: real3.v,v 1.1 2003/03/07 05:29:41 stevewilliams Exp $ + */ + +/* + * Verifies some real values to make sure the real->double conversion + * is properly handled and the values make it into vvp properly. + * + * http://babbage.cs.qc.edu/courses/cs341/IEEE-754.html + * + */ + +module main; + real r; + reg errors; + + initial begin + errors = 0; + r = 1.0; + if ($realtobits(r) != 64'h3FF0000000000000) begin + $display("%f != 'h%h", r, $realtobits(r)); + $display("FAIL"); + errors = 1; + end + + r = 1.1; + if ($realtobits(r) != 64'h3FF199999999999a) begin + $display("%f != 'h%h", r, $realtobits(r)); + $display("FAIL"); + errors = 1; + end + + r = 3.3; + if ($realtobits(r) != 64'h400A666666666666) begin + $display("%f != 'h%h", r, $realtobits(r)); + $display("FAIL"); + errors = 1; + end + + r = 5.5; + if ($realtobits(r) != 64'h4016000000000000) begin + $display("%f != 'h%h", r, $realtobits(r)); + $display("FAIL"); + errors = 1; + end + + r = 1.0000000000_0000000001; + if ($realtobits(r) != 64'h3FF0000000000000) begin + $display("%f != 'h%h", r, $realtobits(r)); + $display("FAIL"); + errors = 1; + end + + r = 3.1415926535_8979323846; + if ($realtobits(r) != 64'h400921FB54442D18) begin + $display("%f != 'h%h", r, $realtobits(r)); + $display("FAIL"); + errors = 1; + end + + r = 1234567890_1234567890.1; + if ($realtobits(r) != 64'h43E56A95319D63E1) begin + $display("%f != 'h%h", r, $realtobits(r)); + $display("FAIL"); + errors = 1; + end + + if (errors === 0) $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/real4.v b/ivtest/ivltests/real4.v new file mode 100644 index 000000000..9c8dad00b --- /dev/null +++ b/ivtest/ivltests/real4.v @@ -0,0 +1,97 @@ +// Copyright (c) 2003 Michael Ruff (mruff at chiaro.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +// +// Test basic functionality of convertion system VPI functions. +// +module test; + + integer err, i; + real r; + reg [63:0] b; + + parameter PI = 3.1415926535_8979323846_2643383279; + + initial begin + err = 0; + + // + // $rtoi() + // + i = $rtoi(0.1); + if (i != 0) begin + err = 1; + $display("$rtoi(0.1): %0d != 0", i); + end + i = $rtoi(9.6); + if (i != 9) begin + err = 1; + $display("$rtoi(9.6): %0d != 9", i); + end + + // + // $realtobits() + // + b = $realtobits(PI); + if (b != 64'h400921FB54442D18) begin + err = 1; + $display("$realtobits(PI): 'h%x != 'h400921FB54442D18", b); + end + b = $realtobits(1.1); + if (b != 64'h3ff199999999999a) begin + err = 1; + $display("$realtobits(1.1): 'h%x != 'h400921FB54442D18", b); + end + + // + // $bitstoreal() + // + r = $bitstoreal(64'h400921FB54442D18); + if (r != PI) begin + err = 1; + $display("$realtobits(PI): %20.17f != %20.17f", r, PI); + end + r = $bitstoreal(64'h3FF4CCCCCCCCCCCD); + if (r != 1.3) begin + err = 1; + $display("$realtobits(1.3): %20.17f != 1.3", r); + end + + // + // $itor() + // + r = $itor(1); + if (r != 1.0) begin + err = 1; + $display("$itor(1): %20.1f != 1.0", r); + end + r = $itor(123456789); + if (r != 123456789.0) begin + err = 1; + $display("$itor(123456789): %20.1f != 123456789.0", r); + end + + if (err) + $display("FAILED"); + else + $display("PASSED"); + + $finish; + end + +endmodule diff --git a/ivtest/ivltests/real5.v b/ivtest/ivltests/real5.v new file mode 100644 index 000000000..389649dd5 --- /dev/null +++ b/ivtest/ivltests/real5.v @@ -0,0 +1,9 @@ +module main; + +parameter MAXPERFOOCLK = 40000; +time fooclk_period; + +initial + #50 $display("max foo period( posedge FOOCLK:%0.3f", $time/1000.0, "ns, %0d", MAXPERFOOCLK, " : %0.3f", fooclk_period/1000.0, "ns );"); + +endmodule diff --git a/ivtest/ivltests/real6.v b/ivtest/ivltests/real6.v new file mode 100644 index 000000000..66d34fdd0 --- /dev/null +++ b/ivtest/ivltests/real6.v @@ -0,0 +1,27 @@ +module main; + + real rfoo; + reg [5:0] x, y; + + initial begin + rfoo = 1.0; + x = 5; + y = 2; + + rfoo = rfoo + x%y; + x = rfoo; + $display("rfoo = %f, x=%d", rfoo, x); + if (x !== 5'd2) begin + $display("FAILED"); + $finish; + end + + if (rfoo != 2.0) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/real7.v b/ivtest/ivltests/real7.v new file mode 100644 index 000000000..9b4f8afd0 --- /dev/null +++ b/ivtest/ivltests/real7.v @@ -0,0 +1,16 @@ +// Verify that icarus can handle real compare versus int constant +module test (); + +real myv; +parameter myp = 1.0; + +initial + begin + myv = 1.0; + if(myv <= 1) + $display("PASSED"); + else + $display("FAILED"); + + end +endmodule diff --git a/ivtest/ivltests/real8.v b/ivtest/ivltests/real8.v new file mode 100644 index 000000000..a5b96f81f --- /dev/null +++ b/ivtest/ivltests/real8.v @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2005 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +/* $Id: real8.v,v 1.1 2005/07/07 16:26:05 stevewilliams Exp $ */ + +/* + * This test demonstrates (and checks) the handling of real values and + * expressions in some ways that baseline IEEE1364-2001. Particularly, + * reg and wire values with types, and nets able to carry real values + * through delays. + */ +module main; + + // This is *not* valid baseline Verilog, but iverilog extensions + // support this. These statements declare a real valued variable + // and a real valued net. + reg real target; + wire real feedback; + + // The feedback should take the target value 10 time units + // after any change in the target value. + assign #(10) feedback = target; + + // The control value is calculated from the current target + // and feedback values. This is recalculated whenever either + // of the inputs change. + wire real control = (feedback - target)/2.0; + + initial begin + target = 16.0; + // The target should, after this assignment, have a well + // defined value 16, but the feedback should remain at NaN + // for a while. + #1 $display($time,,"target=%f, feedback=%f, control=%f", + target, feedback, control); + + if (target != 16.0) begin + $display("FAILED -- target value is not correct."); + $finish; + end + + // feedback is still undefined. + + // By now, the feedback as taken on a value, and the control + // should have been calcluated. + #10 $display($time,,"target=%f, feedback=%f, control=%f", + target, feedback, control); + + if (feedback != 16.0) begin + $display("FAILED -- feedback has wrong value."); + $finish; + end + + if (control != 0.0) begin + $display("FAILED -- control has wrong value."); + $finish; + end + + target = 8.0; + + #9 $display($time,,"target=%f, feedback=%f, control=%f", + target, feedback, control); + + if (feedback != 16.0) begin + $display("FAILED -- feedback has wrong value."); + $finish; + end + + if (control != 4.0) begin + $display("FAILED -- control has wrong value."); + $finish; + end + + #2 $display($time,,"target=%f, feedback=%f, control=%f", + target, feedback, control); + + if (feedback != 8.0) begin + $display("FAILED -- feedback has wrong value."); + $finish; + end + + if (control != 0.0) begin + $display("FAILED -- control has wrong value."); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/real9.v b/ivtest/ivltests/real9.v new file mode 100644 index 000000000..19639d696 --- /dev/null +++ b/ivtest/ivltests/real9.v @@ -0,0 +1,120 @@ +/* real9.v + * This tests comparison of a real variable with integer constants. + */ +module main; + + real value; + parameter param = 2; + + initial begin + value = 3.0; + + if (value < param) begin + $display("FAILED -- %f < %d", value, param); + $finish; + end + + if (value < 2) begin + $display("FAILED -- %f < 2", value); + $finish; + end + + if (value <= param) begin + $display("FAILED -- %f <= %d", value, param); + $finish; + end + + if (value <= 2) begin + $display("FAILED -- %f <= 2", value); + $finish; + end + + if (value == param) begin + $display("FAILED -- %f == %d", value, param); + $finish; + end + + if (value == 2) begin + $display("FAILED -- %f == 2", value); + $finish; + end + + if (param >= value) begin + $display("FAILED -- %d >= %f", param, value); + $finish; + end + + if (2 >= value) begin + $display("FAILED -- 2 >= %f", value); + $finish; + end + + value = 2.0; + + if (value < param) begin + $display("FAILED -- %f < %d", value, param); + $finish; + end + + if (value < 2) begin + $display("FAILED -- %f < 2", value); + $finish; + end + + if (value != param) begin + $display("FAILED -- %f != %d", value, param); + $finish; + end + + if (value != 2) begin + $display("FAILED -- %f != 2", value); + $finish; + end + + if (value > param) begin + $display("FAILED -- %f > %d", value, param); + $finish; + end + + if (value > 2) begin + $display("FAILED -- %f > 2", value); + $finish; + end + + value = 1.6; + + if (value == param) begin + $display("FAILED -- %f == %d", value, param); + $finish; + end + + if (value == 2) begin + $display("FAILED -- %f == 2", value); + $finish; + end + + if (value >= param) begin + $display("FAILED -- %f >= %d", value, param); + $finish; + end + + if (value >= 2) begin + $display("FAILED -- %f >= 2", value); + $finish; + end + + if (value > param) begin + $display("FAILED -- %f > %d", value, param); + $finish; + end + + if (value > 2) begin + $display("FAILED -- %f > 2", value); + $finish; + end + + $display("PASSED"); + end // initial begin + + +endmodule diff --git a/ivtest/ivltests/real_array.v b/ivtest/ivltests/real_array.v new file mode 100644 index 000000000..5bc76f5bd --- /dev/null +++ b/ivtest/ivltests/real_array.v @@ -0,0 +1,56 @@ +module top; + reg pass; + real rarr [1:0]; + real rat; + integer i; + wire real rmon = rarr[0]; + wire real rmonv = rarr[i]; + + always @(rarr[0]) begin + rat = rarr[0]; + end + + initial begin + pass = 1'b1; + i = 0; + + rarr[0] = 1.125; + #1; + if (rmon != 1.125) begin + $display("Failed CA at 0, expected 1.125, got %6.3f", rmon); + pass = 1'b0; + end + if (rmonv != 1.125) begin + $display("Failed CA (var) at 0, expected 1.125, got %6.3f", rmonv); + pass = 1'b0; + end + if (rat != 1.125) begin + $display("Failed @ at 0, expected 1.125, got %6.3f", rat); + pass = 1'b0; + end + + rarr[0] = 2.25; + #1; + if (rmon != 2.25) begin + $display("Failed CA at 1, expected 2.250, got %6.3f", rmon); + pass = 1'b0; + end + if (rmonv != 2.25) begin + $display("Failed CA (var) at 1, expected 2.250, got %6.3f", rmonv); + pass = 1'b0; + end + if (rat != 2.25) begin + $display("Failed @ at 1, expected 2.250, got %6.3f", rat); + pass = 1'b0; + end + + i = 1; + #1 + if (rmonv != 0.0) begin + $display("Failed CA (var) at 2, expected 0.000, got %6.3f", rmonv); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/real_array_nb.v b/ivtest/ivltests/real_array_nb.v new file mode 100644 index 000000000..1027f2bb1 --- /dev/null +++ b/ivtest/ivltests/real_array_nb.v @@ -0,0 +1,113 @@ +`timescale 1ns/100ps + +module top; + reg pass; + real rarr[0:3]; + realtime del; + reg signed [1:0] idx; + integer count; + event evt; + + initial begin + pass = 1'b1; + + // Check the initial values. + if (rarr[1] != 0.0) begin + $display("FAILED initial value, expected 0.0, got %f", rarr[1]); + pass = 1'b0; + end + + // Check a negative index value. + rarr[3] = 3.0; + idx = -1; + rarr[idx] <= 0.0; + #0.1; + if (rarr[3] != 3.0) begin + $display("FAILED negative index 1, expected 3.0, got %f", rarr[3]); + pass = 1'b0; + end + + del = 1.0; + rarr[idx] <= #(del) 0.0; + #1.1; + if (rarr[3] != 3.0) begin + $display("FAILED negative index 2, expected 3.0, got %f", rarr[3]); + pass = 1'b0; + end + + count = 0; + rarr[idx] <= repeat(count) @(evt) 0.0; + #0.1; + if (rarr[3] != 3.0) begin + $display("FAILED negative index 3, expected 3.0, got %f", rarr[3]); + pass = 1'b0; + end + + // Check a non-blocking assignment. + rarr[1] <= 2.0; + if (rarr[1] != 0.0) begin + $display("FAILED non-blocking assign 1, expected 0.0, got %f", rarr[1]); + pass = 1'b0; + end + #0.1; + if (rarr[1] != 2.0) begin + $display("FAILED non-blocking assign 2, expected 2.0, got %f", rarr[1]); + pass = 1'b0; + end + + // Check a delayed non-blocking assignment. + rarr[1] <= #2 3.0; + #1.9; + if (rarr[1] != 2.0) begin + $display("FAILED delayed NB assign 1, expected 2.0, got %f", rarr[1]); + pass = 1'b0; + end + #0.2; + if (rarr[1] != 3.0) begin + $display("FAILED delayed NB assign 2, expected 3.0, got %f", rarr[1]); + pass = 1'b0; + end + + // Check a variable delay non-blocking assignment. + del = 3.0; + rarr[1] <= #(del) 4.0; + #2.9; + if (rarr[1] != 3.0) begin + $display("FAILED var. delay NB assign 1, expected 3.0, got %f", rarr[1]); + pass = 1'b0; + end + #0.2; + if (rarr[1] != 4.0) begin + $display("FAILED var. delay NB assign 2, expected 4.0, got %f", rarr[1]); + pass = 1'b0; + end + + // Check a zero count event non-blocking assignment. + rarr[1] <= repeat(count) @(evt) 5.0; + #0.1; + if (rarr[1] != 5.0) begin + $display("FAILED NB EC count=0, expected 5.0, got %f", rarr[1]); + pass = 1'b0; + end + + // Check for an event non-blocking assignment. + rarr[1] <= @(evt) 6.0; + fork + #1 ->evt; + begin + #0.9; + if (rarr[1] != 5.0) begin + $display("FAILED NB EC initial, expected 5.0, got %f", rarr[1]); + pass = 1'b0; + end + #0.2; + if (rarr[1] != 6.0) begin + $display("FAILED NB EC final, expected 6.0, got %f", rarr[1]); + pass = 1'b0; + end + end + join + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/real_assign_deassign.v b/ivtest/ivltests/real_assign_deassign.v new file mode 100644 index 000000000..905d7685f --- /dev/null +++ b/ivtest/ivltests/real_assign_deassign.v @@ -0,0 +1,48 @@ +module test (); + reg pass = 1'b1; + reg d; + real f = 0.0; + + always @(d) assign f = 0; + + initial begin + // Verify the initial value. + #1; + if (f != 0.0) begin + $display("Failed initial value, expected 0.0, got %f", f); + pass = 1'b0; + end + + // Verify the value can change. + #1 f = 1.0; + if (f != 1.0) begin + $display("Failed value change, expected 1.0, got %f", f); + pass = 1'b0; + end + + // Verify that the assign changed the value and that a normal assign + // is blocked. + #1 d = 0; + #1 f = 1.0; + if (f != 0.0) begin + $display("Failed assign holding, expected 0.0, got %f", f); + pass = 1'b0; + end + + // Verify that the release holds the previous value. + #1 deassign f; + if (f != 0.0) begin + $display("Failed release holding, expected 0.0, got %f", f); + pass = 1'b0; + end + + // Verify that the value can be changed after a release. + #1 f = 1.0; + if (f != 1.0) begin + $display("Failed release, expected 1.0, got %f", f); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/real_concat_invalid1.v b/ivtest/ivltests/real_concat_invalid1.v new file mode 100644 index 000000000..fa2e61d07 --- /dev/null +++ b/ivtest/ivltests/real_concat_invalid1.v @@ -0,0 +1,19 @@ +module top; + real rvar1, rvar2, rtmp; + wire real wrcon3, wrcon4, wrcon5, wrcon6; + + wire real wrcon1 = {2.0, 1.0}; + wire real wrcon2 = {rvar1, rvar2}; + + assign wrcon3 = {2.0, 1.0}; + assign wrcon4 = {rvar1, rvar2}; + + assign {wrcon5, wrcon6} = 1.0; + + initial begin + rtmp = {2.0, 1.0}; + rtmp = {rvar1, rvar2}; + + {rvar1, rvar2} = rtmp; + end +endmodule diff --git a/ivtest/ivltests/real_concat_invalid2.v b/ivtest/ivltests/real_concat_invalid2.v new file mode 100644 index 000000000..d033cd975 --- /dev/null +++ b/ivtest/ivltests/real_concat_invalid2.v @@ -0,0 +1,6 @@ +module top; + parameter real rpar1 = 1.0; + parameter real rpar2 = 2.0; + parameter real rparb = {rpar1, rpar2}; + parameter real rpar = {2.0, 1.0}; +endmodule diff --git a/ivtest/ivltests/real_delay.sdf b/ivtest/ivltests/real_delay.sdf new file mode 100644 index 000000000..55d94a350 --- /dev/null +++ b/ivtest/ivltests/real_delay.sdf @@ -0,0 +1,13 @@ +(DELAYFILE + (SDFVERSION "OVI 2.1") + (TIMESCALE 1ns) + (CELL + (CELLTYPE "gate_sdf") + (INSTANCE dut_f) + (DELAY + (ABSOLUTE + (IOPATH in out (1.134) (0.0)) + ) + ) + ) +) diff --git a/ivtest/ivltests/real_delay.v b/ivtest/ivltests/real_delay.v new file mode 100644 index 000000000..8afe0ed66 --- /dev/null +++ b/ivtest/ivltests/real_delay.v @@ -0,0 +1,255 @@ +`timescale 1ns/1ps + +primitive not_u (out, in); + output out; + input in; + table + 0 : 1; + 1 : 0; + endtable +endprimitive + +// Any instance of this gate will use the small time scale that was +// in place when it was defined. +module gate_sdf(out, in); + output out; + input in; + wire out, in; + + assign out = ~in; + + specify + (in => out) = (0.5, 0.5); + endspecify +endmodule + +/* + * Icarus does not currently support UDPs with a variable delay. + * It also needs to support NULL decay delays, buf/not/etc. should + * only allow two delays maximum. + */ +module top; + initial begin + $monitor("%.3f", $realtime,, sml_const.test, sml_var.test, + sml_const.out_g, sml_const.out_u, + sml_const.out_m, sml_const.out_s, + sml_var.out_g, sml_var.out_u,, + + sml_const.out_f, med_const.out_f, + lrg_const.out_f,, + + med_const.test, med_var.test, + med_const.out_g, med_const.out_u, + med_const.out_m, med_const.out_s, + med_var.out_g, med_var.out_u,, + + lrg_const.test, lrg_var.test, + lrg_const.out_g, lrg_const.out_u, + lrg_const.out_m, lrg_const.out_s, + lrg_var.out_g, lrg_var.out_u); + #1.3 $finish(0); + end +endmodule + +/* + * These should have a positive edge at 1234 time ticks. + */ +// Check that constant delays are scaled correctly. +module sml_const; + reg test, in; + wire out_g, out_u, out_m, out_s, out_f; + not #(1.134, 0) dut_g (out_g, in); + not_u #(1.134, 0) dut_u (out_u, in); + sml_inv dut_m (out_m, in); + gate_sdf dut_f (out_f, in); + sml_sdf dut_s (out_s, in); + initial begin + $sdf_annotate("ivltests/real_delay.sdf"); + $sdf_annotate("ivltests/real_delay_sml.sdf"); + in = 1'b1; + in <= #0.1 1'b0; + test = 1'b0; + #1.234 test = 1'b1; + end +endmodule + +// Check that the specify delays are scaled correctly. +module sml_inv(out, in); + output out; + input in; + wire out, in; + + assign out = ~in; + + specify + (in => out) = (1.134, 0); + endspecify +endmodule + +// Check that the SDF delays scale correctly. +module sml_sdf(out, in); + output out; + input in; + wire out, in; + + assign out = ~in; + + specify + (in => out) = (0.5, 0.5); + endspecify +endmodule + + +// Check that variable delays are scaled correctly. +module sml_var; + reg test, in; + real dly, dly2, dly3; + wire out_g, out_u; + not #(dly2, dly3) dut_g (out_g, in); + not_u #(dly2, dly3) dut_u (out_u, in); + initial begin + in = 1'b1; + in <= #0.1 1'b0; + dly = 1.234; + dly2 = 1.134; + dly3 = 0.0; + test = 1'b0; + #(dly) test = 1'b1; + end +endmodule + +`timescale 1ns/10ps + +/* + * These should have a positive edge at 1230 time ticks. + */ +// Check that constant delays are scaled correctly. +module med_const; + reg test, in; + wire out_g, out_u, out_m, out_s, out_f; + not #(1.134, 0) dut_g (out_g, in); + not_u #(1.134, 0) dut_u (out_u, in); + med_inv dut_m (out_m, in); + gate_sdf dut_f (out_f, in); + med_sdf dut_s (out_s, in); + initial begin + $sdf_annotate("ivltests/real_delay.sdf"); + $sdf_annotate("ivltests/real_delay_med.sdf"); + in = 1'b1; + in <= #0.1 1'b0; + test = 1'b0; + #1.234 test = 1'b1; + end +endmodule + +// Check that the specify delays are scaled correctly. +module med_inv(out, in); + output out; + input in; + wire out, in; + + assign out = ~in; + + specify + (in => out) = (1.134, 0); + endspecify +endmodule + +// Check that the SDF delays scale correctly. +module med_sdf(out, in); + output out; + input in; + wire out, in; + + assign out = ~in; + + specify + (in => out) = (0.5, 0.5); + endspecify +endmodule + +// Check that variable delays are scaled correctly. +module med_var; + reg test, in; + real dly, dly2, dly3; + wire out_g, out_u; + not #(dly2, dly3) dut_g (out_g, in); + not_u #(dly2, dly3) dut_u (out_u, in); + initial begin + in = 1'b1; + in <= #0.1 1'b0; + dly = 1.234; + dly2 = 1.134; + dly3 = 0.0; + test = 1'b0; + #(dly) test = 1'b1; + end +endmodule + +`timescale 1ns/100ps + +/* + * These should have a positive edge at 1200 time ticks. + */ +// Check that constant delays are scaled correctly. +module lrg_const; + reg test, in; + wire out_g, out_u, out_m, out_s, out_f; + not #(1.134, 0) gate (out_g, in); + not_u #(1.134, 0) dut_u (out_u, in); + lrg_inv dut_m (out_m, in); + gate_sdf dut_f (out_f, in); + lrg_sdf dut_s (out_s, in); + initial begin + $sdf_annotate("ivltests/real_delay.sdf"); + $sdf_annotate("ivltests/real_delay_lrg.sdf"); + in = 1'b1; + in <= #0.1 1'b0; + test = 1'b0; + #1.234 test = 1'b1; + end +endmodule + +// Check that the specify delays are scaled correctly. +module lrg_inv(out, in); + output out; + input in; + wire out, in; + + assign out = ~in; + + specify + (in => out) = (1.134, 0); + endspecify +endmodule + +// Check that the SDF delays scale correctly. +module lrg_sdf(out, in); + output out; + input in; + wire out, in; + + assign out = ~in; + + specify + (in => out) = (0.5, 0.5); + endspecify +endmodule + +// Check that variable delays are scaled correctly. +module lrg_var; + reg test, in; + real dly, dly2, dly3; + wire out_g, out_u; + not #(dly2, dly3) dut_g (out_g, in); + not_u #(dly2, dly3) dut_u (out_u, in); + initial begin + in = 1'b1; + in <= #0.1 1'b0; + dly = 1.234; + dly2 = 1.134; + dly3 = 0.0; + test = 1'b0; + #(dly) test = 1'b1; + end +endmodule diff --git a/ivtest/ivltests/real_delay_lrg.sdf b/ivtest/ivltests/real_delay_lrg.sdf new file mode 100644 index 000000000..63573c9bf --- /dev/null +++ b/ivtest/ivltests/real_delay_lrg.sdf @@ -0,0 +1,13 @@ +(DELAYFILE + (SDFVERSION "OVI 2.1") + (TIMESCALE 1ns) + (CELL + (CELLTYPE "lrg_sdf") + (INSTANCE dut_s) + (DELAY + (ABSOLUTE + (IOPATH in out (1.134) (0.0)) + ) + ) + ) +) diff --git a/ivtest/ivltests/real_delay_med.sdf b/ivtest/ivltests/real_delay_med.sdf new file mode 100644 index 000000000..c9c936804 --- /dev/null +++ b/ivtest/ivltests/real_delay_med.sdf @@ -0,0 +1,13 @@ +(DELAYFILE + (SDFVERSION "OVI 2.1") + (TIMESCALE 1ns) + (CELL + (CELLTYPE "med_sdf") + (INSTANCE dut_s) + (DELAY + (ABSOLUTE + (IOPATH in out (1.134) (0.0)) + ) + ) + ) +) diff --git a/ivtest/ivltests/real_delay_sml.sdf b/ivtest/ivltests/real_delay_sml.sdf new file mode 100644 index 000000000..69acc422b --- /dev/null +++ b/ivtest/ivltests/real_delay_sml.sdf @@ -0,0 +1,13 @@ +(DELAYFILE + (SDFVERSION "OVI 2.1") + (TIMESCALE 1ns) + (CELL + (CELLTYPE "sml_sdf") + (INSTANCE dut_s) + (DELAY + (ABSOLUTE + (IOPATH in out (1.134) (0.0)) + ) + ) + ) +) diff --git a/ivtest/ivltests/real_events.v b/ivtest/ivltests/real_events.v new file mode 100644 index 000000000..b27ebedba --- /dev/null +++ b/ivtest/ivltests/real_events.v @@ -0,0 +1,43 @@ +module test(); + +real val; + +always @(val) begin + $display("val = %f", val); +end + +task automatic test_task(input integer delay, input real val1, input real val2); + +real val; + +fork + begin + @(val) $display("val%0d = %f", delay, val); + @(val) $display("val%0d = %f", delay, val); + end + begin + #delay; + #2 val = val1; + #2 val = val1; + #2 val = val2; + end +join + +endtask + +initial begin + #1 val = 1.0; + #1 val = 1.0; + #1 val = 2.0; + fork + test_task(1, 1.1, 2.1); + test_task(2, 1.2, 2.2); + join + fork + test_task(1, 2.1, 3.1); + test_task(2, 2.2, 3.2); + join + #1 $finish(0); +end + +endmodule diff --git a/ivtest/ivltests/real_force_rel.v b/ivtest/ivltests/real_force_rel.v new file mode 100644 index 000000000..f90d0ca7b --- /dev/null +++ b/ivtest/ivltests/real_force_rel.v @@ -0,0 +1,77 @@ +module test (); + reg pass = 1'b1; + reg d; + real f = 0.0, z = 0.0, y = 1.0; + + always @(d) force f = z; + + initial begin + // Verify the initial value. + #1; + if (f != 0.0) begin + $display("Failed initial value, expected 0.0, got %f", f); + pass = 1'b0; + end + + // Verify that the force changed the value and that a normal assign + // is blocked. + #1 d = 0; + #1 f = 1.0; + if (f != 0.0) begin + $display("Failed force holding (normal), expected 0.0, got %f", f); + pass = 1'b0; + end + + // Verify that an assign does not change the value when forced. + #1 assign f = y; + if (f != 0.0) begin + $display("Failed force holding (assign), expected 0.0, got %f", f); + pass = 1'b0; + end + + // Verify that a force will propagate. + z = 1.0; + #1; + if (f != 1.0) begin + $display("Failed force propagation, expected 1.0, got %f", f); + pass = 1'b0; + end + + // Verify that the release holds the previous value. + #1 release f; + if (f != 1.0) begin + $display("Failed release holding, expected 1.0, got %f", f); + pass = 1'b0; + end + + // Verify that a release correctly breaks the variable link. + #1 z = 0.0; + if (f != 1.0) begin + $display("Failed variable unlinking (force), expected 1.0, got %f", f); + pass = 1'b0; + end + + // Verify that a deassign holds the previous value. + #1 deassign f; + if (f != 1.0) begin + $display("Failed deassign holding, expected 1.0, got %f", f); + pass = 1'b0; + end + + // Verify that a deassign correctly breaks the variable link. + #1 y = 0.0; + if (f != 1.0) begin + $display("Failed variable unlinking (deassign), expected 1.0, got %f", f); + pass = 1'b0; + end + + // Verify that the value can be changed after a release and a deassign. + #1 f = 2.0; + if (f != 2.0) begin + $display("Failed release, expected 2.0, got %f", f); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/real_invalid_ops.v b/ivtest/ivltests/real_invalid_ops.v new file mode 100644 index 000000000..f0928d8f4 --- /dev/null +++ b/ivtest/ivltests/real_invalid_ops.v @@ -0,0 +1,69 @@ +module top; + real var1, var2; + reg [7:0] bvar; + reg result; + + wire r_a = &var1; + wire r_o = |var1; + wire r_x = ^var1; + wire r_na = ~&var1; + wire r_no = ~|var1; + wire r_xn1 = ~^var1; + wire r_xn2 = ^~var1; + + wire r_b_a = var1 & var2; + wire r_b_o = var1 | var2; + wire r_b_x = var1 ^ var2; + wire r_b_na = var1 ~& var2; + wire r_b_no = var1 ~| var2; + wire r_b_xn1 = var1 ~^ var2; + wire r_b_xn2 = var1 ^~ var2; + + wire r_eeq = var1 === var2; + wire r_neeq = var1 !== var2; + + wire r_ls = var1 << var2; + wire r_als = var1 <<< var2; + wire r_rs = var1 >> var2; + wire r_ars = var1 >>> var2; + + wire r_con = {var1}; + wire r_rep = {2.0{var1}}; + + initial begin + var1 = 1.0; + var2 = 2.0; + + #1; + + /* These should all fail in the compiler. */ + result = &var1; + result = |var1; + result = ^var1; + result = ~&var1; + result = ~|var1; + result = ~^var1; + result = ^~var1; + + result = var1 & var2; + result = var1 | var2; + result = var1 ^ var2; + result = var1 ~& var2; + result = var1 ~| var2; + result = var1 ~^ var2; + result = var1 ^~ var2; + + result = var1 === var2; + result = var1 !== var2; + + bvar = var1 << var2; + bvar = var1 <<< var2; + bvar = var1 >> var2; + bvar = var1 >>> var2; + + bvar = {var1}; + bvar = {2.0{var1}}; + + $display("Failed"); + end +endmodule diff --git a/ivtest/ivltests/real_logical.v b/ivtest/ivltests/real_logical.v new file mode 100644 index 000000000..95f7ffcad --- /dev/null +++ b/ivtest/ivltests/real_logical.v @@ -0,0 +1,221 @@ +module top; + parameter parg0 = 0.0; + parameter parg1 = 1.0; + parameter parg2 = 2.0; + parameter pargi = 1.0/0.0; // Inf. + parameter pargn = $sqrt(-1.0); // NaN. + real arg0, arg1, arg2, argi, argn; + reg result, pass; + + initial begin + pass = 1'b1; + + arg0 = 0.0; + arg1 = 1.0; + arg2 = 2.0; + argi = 1.0/0.0; // Inf. + argn = $sqrt(-1.0); // NaN. + + /* Check ! on a constant real value. */ + result = !parg0; + if (result !== 1'b1) begin + $display("Failed: constant !0.0, expected 1'b1, got %b", result); + pass = 1'b0; + end + + result = !parg1; + if (result !== 1'b0) begin + $display("Failed: constant !1.0, expected 1'b0, got %b", result); + pass = 1'b0; + end + + result = !parg2; + if (result !== 1'b0) begin + $display("Failed: constant !2.0, expected 1'b0, got %b", result); + pass = 1'b0; + end + + result = !pargi; + if (result !== 1'b0) begin + $display("Failed: constant !Inf, expected 1'b0, got %b", result); + pass = 1'b0; + end + + result = !pargn; + if (result !== 1'b0) begin + $display("Failed: constant !NaN, expected 1'b0, got %b", result); + pass = 1'b0; + end + + /* Check ! on a real variable. */ + result = !arg0; + if (result !== 1'b1) begin + $display("Failed: !0.0, expected 1'b1, got %b", result); + pass = 1'b0; + end + + result = !arg1; + if (result !== 1'b0) begin + $display("Failed: !1.0, expected 1'b0, got %b", result); + pass = 1'b0; + end + + result = !arg2; + if (result !== 1'b0) begin + $display("Failed: !2.0, expected 1'b0, got %b", result); + pass = 1'b0; + end + + result = !argi; + if (result !== 1'b0) begin + $display("Failed: !Inf, expected 1'b0, got %b", result); + pass = 1'b0; + end + + result = !argn; + if (result !== 1'b0) begin + $display("Failed: !NaN, expected 1'b0, got %b", result); + pass = 1'b0; + end + + /* Check && on a constant real value. */ + result = parg0 && parg1; + if (result !== 1'b0) begin + $display("Failed: constant 0.0 && 1.0, expected 1'b0, got %b", result); + pass = 1'b0; + end + + result = parg0 && parg2; + if (result !== 1'b0) begin + $display("Failed: constant 0.0 && 2.0, expected 1'b0, got %b", result); + pass = 1'b0; + end + + result = parg1 && parg2; + if (result !== 1'b1) begin + $display("Failed: constant 1.0 && 2.0, expected 1'b1, got %b", result); + pass = 1'b0; + end + + /* Check && on a real variable. */ + result = arg0 && arg1; + if (result !== 1'b0) begin + $display("Failed: 0.0 && 1.0, expected 1'b0, got %b", result); + pass = 1'b0; + end + + result = arg0 && arg2; + if (result !== 1'b0) begin + $display("Failed: 0.0 && 2.0, expected 1'b0, got %b", result); + pass = 1'b0; + end + + result = arg1 && arg2; + if (result !== 1'b1) begin + $display("Failed: 1.0 && 2.0, expected 1'b1, got %b", result); + pass = 1'b0; + end + + /* Check || on a constant real value. */ + result = parg0 || 0; + if (result !== 1'b0) begin + $display("Failed: constant 0.0 || 0, expected 1'b0, got %b", result); + pass = 1'b0; + end + + result = parg0 || parg1; + if (result !== 1'b1) begin + $display("Failed: constant 0.0 || 1.0, expected 1'b1, got %b", result); + pass = 1'b0; + end + + result = parg0 || parg2; + if (result !== 1'b1) begin + $display("Failed: constant 0.0 || 2.0, expected 1'b1, got %b", result); + pass = 1'b0; + end + + /* Check || on a real variable. */ + result = arg0 || 0; + if (result !== 1'b0) begin + $display("Failed: 0.0 || 0, expected 1'b0, got %b", result); + pass = 1'b0; + end + + result = arg0 || arg1; + if (result !== 1'b1) begin + $display("Failed: 0.0 || 1.0, expected 1'b1, got %b", result); + pass = 1'b0; + end + + result = arg0 || arg2; + if (result !== 1'b1) begin + $display("Failed: 0.0 || 2.0, expected 1'b1, got %b", result); + pass = 1'b0; + end + + /* Check the ternary with a constant real cond. value. */ + result = parg0 ? 1'b1 : 1'b0; + if (result !== 1'b0) begin + $display("Failed: constant 0.0 ? ..., expected 1'b0, got %b", result); + pass = 1'b0; + end + + result = parg1 ? 1'b1 : 1'b0; + if (result !== 1'b1) begin + $display("Failed: constant 1.0 ? ..., expected 1'b1, got %b", result); + pass = 1'b0; + end + + result = parg2 ? 1'b1 : 1'b0; + if (result !== 1'b1) begin + $display("Failed: constant 2.0 ? ..., expected 1'b1, got %b", result); + pass = 1'b0; + end + + result = pargi ? 1'b1 : 1'b0; + if (result !== 1'b1) begin + $display("Failed: constant Inf ? ..., expected 1'b1, got %b", result); + pass = 1'b0; + end + + result = pargn ? 1'b1 : 1'b0; + if (result !== 1'b1) begin + $display("Failed: constant NaN ? ..., expected 1'b1, got %b", result); + pass = 1'b0; + end + + /* Check the ternary with a real cond. variable. */ + result = arg0 ? 1'b1 : 1'b0; + if (result !== 1'b0) begin + $display("Failed: 0.0 ? ..., expected 1'b0, got %b", result); + pass = 1'b0; + end + + result = arg1 ? 1'b1 : 1'b0; + if (result !== 1'b1) begin + $display("Failed: 1.0 ? ..., expected 1'b1, got %b", result); + pass = 1'b0; + end + + result = arg2 ? 1'b1 : 1'b0; + if (result !== 1'b1) begin + $display("Failed: 2.0 ? ..., expected 1'b1, got %b", result); + pass = 1'b0; + end + + result = argi ? 1'b1 : 1'b0; + if (result !== 1'b1) begin + $display("Failed: Inf ? ..., expected 1'b1, got %b", result); + pass = 1'b0; + end + + result = argn ? 1'b1 : 1'b0; + if (result !== 1'b1) begin + $display("Failed: NaN ? ..., expected 1'b1, got %b", result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/real_mod_in_ca.v b/ivtest/ivltests/real_mod_in_ca.v new file mode 100644 index 000000000..9bad69072 --- /dev/null +++ b/ivtest/ivltests/real_mod_in_ca.v @@ -0,0 +1,42 @@ +`timescale 1us/100ns + +module top; + reg pass = 1'b1; + + real ra = 1.0, rb = 2.0; + wire real rmod; + + /* Real Power. */ + assign #1 rmod = ra % rb; + + initial begin + #0.9; + if (rmod == 1.0) begin + pass = 1'b0; + $display("Real: modulus value not delayed."); + end + + #0.1; + #0; + if (rmod != 1.0) begin + pass = 1'b0; + $display("Real: modulus value not correct, expected 1.0 got %g.", rmod); + end + + #1 ra = 2.0; + #2; + if (rmod != 0.0) begin + pass = 1'b0; + $display("Real: modulus value not correct, expected 0.0 got %g.", rmod); + end + + #1 rb = 4.0; + #2; + if (rmod != 2.0) begin + pass = 1'b0; + $display("Real: modulus value not correct, expected 2.0 got %g.", rmod); + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/real_op_fail.v b/ivtest/ivltests/real_op_fail.v new file mode 100644 index 000000000..888d31e0c --- /dev/null +++ b/ivtest/ivltests/real_op_fail.v @@ -0,0 +1,35 @@ +module top; + + real ra = 1.0, rb = 1.0; + wire real rdand, rdnand, rdor, rdnor, rdxor, rdxnor, + rand, rnand, ror, rnor, rxor, rxnor, + rls, rals, rrs, rars; + wire [3:0] lsbr, alsbr, rsbr, arsbr; + + /* Test the reduction operators. */ + assign rdand = &ra; + assign rdnand = ~&ra; + assign rdor = |ra; + assign rdnor = ~|ra; + assign rdxor = ^ra; + assign rdxnor = ~^ra; + + /* Test the bit-wise operators. */ + assign rand = ra & rb; + assign rnand = ra ~& rb; + assign ror = ra | rb; + assign rnor = ra ~| rb; + assign rxor = ra ^ rb; + assign rxnor = ra ~^ rb; + + /* Test the shift operators. */ + assign rls = ra << rb; + assign rals = ra <<< rb; + assign rrs = ra >> rb; + assign rars = ra >>> rb; + + assign lsbr = 4'b1010 << rb; + assign alsbr = 4'b1010 <<< rb; + assign rsbr = 4'b1010 >> rb; + assign arsbr = 4'b1010 >>> rb; +endmodule diff --git a/ivtest/ivltests/real_pulse_clean.v b/ivtest/ivltests/real_pulse_clean.v new file mode 100644 index 000000000..eefe143d9 --- /dev/null +++ b/ivtest/ivltests/real_pulse_clean.v @@ -0,0 +1,39 @@ +`timescale 1us/100ns + +module top; + reg pass = 1'b1; + real in1, in2; + wire real mult; + + /* A simple multiplier. */ + assign #0.2 mult = in1*in2; + + initial begin + #1; + in1 = 1.0; + in2 = 2.0; + #1; + if (mult != 2.0) begin + $display("FAILED (1): expected 2.0 got %g", mult); + pass = 0; + end + #1; + in1 = 2.0; + in2 = 1.0; + #1; + if (mult != 2.0) begin + $display("FAILED (2): expected 2.0 got %g", mult); + pass = 0; + end + #1; + in1 = 1.0; + in2 = 2.0; + #1; + if (mult != 2.0) begin + $display("FAILED (3): expected 2.0 got %g", mult); + pass = 0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/real_pwr_in_ca.v b/ivtest/ivltests/real_pwr_in_ca.v new file mode 100644 index 000000000..918151885 --- /dev/null +++ b/ivtest/ivltests/real_pwr_in_ca.v @@ -0,0 +1,57 @@ +`timescale 1us/100ns + +module top; + reg pass = 1'b1; + + real ra = 1.0, rb = 2.0; + wire real rpow; + + /* Real Power. */ + assign #1 rpow = ra ** rb; + + initial begin + #0.9; + if (rpow == 1.0) begin + pass = 1'b0; + $display("Real: power value not delayed."); + end + + #0.1; + #0; + if (rpow != 1.0) begin + pass = 1'b0; + $display("Real: power value not correct, expected 1.0 got %g.", rpow); + end + + #1 ra = 2.0; + #2; + if (rpow != 4.0) begin + pass = 1'b0; + $display("Real: power value not correct, expected 4.0 got %g.", rpow); + end + + #1 ra = 0.0; + #2; + if (rpow != 0.0) begin + pass = 1'b0; + $display("Real: power value not correct, expected 0.0 got %g.", rpow); + end + + #1 ra = 10.0; + #2; + if (rpow != 100.0) begin + pass = 1'b0; + $display("Real: power value not correct, expected 100.0 got %g.", rpow); + end + + #1 ra = 0.0; rb = -1.0; + #2; + $display("0.0 ** -1.0 = %g", rpow); + + #1 ra = -1.0; rb = 2.5; + #2; + $display("-1.0 ** 2.5 = %g", rpow); + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/real_reg_force_rel.v b/ivtest/ivltests/real_reg_force_rel.v new file mode 100644 index 000000000..154b4e670 --- /dev/null +++ b/ivtest/ivltests/real_reg_force_rel.v @@ -0,0 +1,48 @@ +module test (); + reg pass = 1'b1; + reg d; + real f = 0.0; + + always @(d) force f = 0.0; + + initial begin + // Verify the initial value. + #1; + if (f != 0.0) begin + $display("Failed initial value, expected 0.0, got %f", f); + pass = 1'b0; + end + + // Verify the value can change. + #1 f = 1.0; + if (f != 1.0) begin + $display("Failed value change, expected 1.0, got %f", f); + pass = 1'b0; + end + + // Verify that the force changed the value and that a normal assign + // is blocked. + #1 d = 0; + #1 f = 1.0; + if (f != 0.0) begin + $display("Failed force holding, expected 0.0, got %f", f); + pass = 1'b0; + end + + // Verify that the release holds the previous value. + #1 release f; + if (f != 0.0) begin + $display("Failed release holding, expected 0.0, got %f", f); + pass = 1'b0; + end + + // Verify that the value can be changed after a release. + #1 f = 1.0; + if (f != 1.0) begin + $display("Failed release, expected 1.0, got %f", f); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/real_select_invalid.v b/ivtest/ivltests/real_select_invalid.v new file mode 100644 index 000000000..440d25af1 --- /dev/null +++ b/ivtest/ivltests/real_select_invalid.v @@ -0,0 +1,91 @@ +module top; + parameter real rpar = 2.0; + real rvar; + real rarr [1:0]; + real rout, rtmp; + wire real wrarr [1:0]; + wire real wrbslv, wrpslv, wruplv, wrdolv; + wire real wrbstr, wrpstr, wruptr, wrdotr; + + wire real wrpbs = rpar[0]; + wire real wrpps = rpar[0:0]; + wire real wrpup = rpar[0+:1]; + wire real wrpdo = rpar[0-:1]; + + wire real wrbs = rvar[0]; + wire real wrps = rvar[0:0]; + wire real wrup = rvar[0+:1]; + wire real wrdo = rvar[0-:1]; + + wire real wrabs = rarr[0][0]; + wire real wraps = rarr[0][0:0]; + wire real wraup = rarr[0][0+:1]; + wire real wrado = rarr[0][0-:1]; + + assign wrbslv[0] = rvar; + assign wrpslv[0:0] = rvar; + assign wruplv[0+:1] = rvar; + assign wrdolv[0-:1] = rvar; + + assign wrarr[0][0] = rvar; + assign wrarr[0][0:0] = rvar; + assign wrarr[0][0+:1] = rvar; + assign wrarr[0][0-:1] = rvar; + + tran(wrbstr[0], wrarr[1]); + tran(wrpstr[0:0], wrarr[1]); + tran(wruptr[0+:1], wrarr[1]); + tran(wrdotr[0-:1], wrarr[1]); + + submod1 s1 (wrbstr[0], wrpstr[0:0], wruptr[0+:1], wrdotr[0-:1]); + submod2 s2 (wrbstr[0], wrpstr[0:0], wruptr[0+:1], wrdotr[0-:1]); + submod3 s3 (wrbstr[0], wrpstr[0:0], wruptr[0+:1], wrdotr[0-:1]); + + initial begin + rtmp = rpar[0]; + rtmp = rpar[0:0]; + rtmp = rpar[0+:1]; + rtmp = rpar[0-:1]; + + rtmp = rvar[0]; + rtmp = rvar[0:0]; + rtmp = rvar[0+:1]; + rtmp = rvar[0-:1]; + + rtmp = rarr[0][0]; + rtmp = rarr[0][0:0]; + rtmp = rarr[0][0+:1]; + rtmp = rarr[0][0-:1]; + + rout[0] = 2.0; + rout[0:0] = 2.0; + rout[0+:1] = 2.0; + rout[0-:1] = 2.0; + + rarr[0][0] = 1.0; + rarr[0][0:0] = 1.0; + rarr[0][0+:1] = 1.0; + rarr[0][0-:1] = 1.0; + end +endmodule + +module submod1(arg1, arg2, arg3, arg4); + input arg1, arg2, arg3, arg4; + wire real arg1, arg2, arg3, arg4; + + initial $display("In submod1 with %g, %g, %g, %g", arg1, arg2, arg3, arg4); +endmodule + +module submod2(arg1, arg2, arg3, arg4); + output arg1, arg2, arg3, arg4; + real arg1, arg2, arg3, arg4; + + initial $display("In submod2 with %g, %g, %g, %g", arg1, arg2, arg3, arg4); +endmodule + +module submod3(arg1, arg2, arg3, arg4); + inout arg1, arg2, arg3, arg4; + wire real arg1, arg2, arg3, arg4; + + initial $display("In submod3 with %g, %g, %g, %g", arg1, arg2, arg3, arg4); +endmodule diff --git a/ivtest/ivltests/real_wire_array.v b/ivtest/ivltests/real_wire_array.v new file mode 100644 index 000000000..304c44c4f --- /dev/null +++ b/ivtest/ivltests/real_wire_array.v @@ -0,0 +1,30 @@ +module top; + reg passed = 1'b1; + real rval = 1.0; + wire real rvar [1:0]; + + assign rvar[0] = -1.0; + assign rvar[1] = 2.0*rval; + + initial begin + #1; + if (rvar[0] != -1.0) begin + $display("Failed: real wire array[0], expected -1.0, got %g", rvar[0]); + passed = 1'b0; + end + + if (rvar[1] != 2.0) begin + $display("Failed: real wire array[1], expected 2.0, got %g", rvar[1]); + passed = 1'b0; + end + + rval = 2.0; + #1; + if (rvar[1] != 4.0) begin + $display("Failed: real wire array[1], expected 4.0, got %g", rvar[1]); + passed = 1'b0; + end + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/real_wire_force_rel.v b/ivtest/ivltests/real_wire_force_rel.v new file mode 100644 index 000000000..389a17354 --- /dev/null +++ b/ivtest/ivltests/real_wire_force_rel.v @@ -0,0 +1,48 @@ +module test (); + reg pass = 1'b1; + reg d; + real a = 0.0; + wire real f = a; + + always @(d) force f = 0.0; + + initial begin + // Verify the initial value. + #1; + if (f != 0.0) begin + $display("Failed initial value, expected 0.0, got %f", f); + pass = 1'b0; + end + + // Verify the value can change. + #1 a = 1.0; + if (f != 1.0) begin + $display("Failed value change, expected 1.0, got %f", f); + pass = 1'b0; + end + + // Verify that the force changed the value and that the CA is blocked. + #1 d = 0; + #1 a = 1.0; + if (f != 0.0) begin + $display("Failed force holding, expected 0.0, got %f", f); + pass = 1'b0; + end + + // Verify that the release propagates the CA value. + #1 release f; + if (f != 1.0) begin + $display("Failed release change, expected 1.0, got %f", f); + pass = 1'b0; + end + + // Verify that the value can be changed after a release. + #1 a = 0.0; + if (f != 0.0) begin + $display("Failed release, expected 0.0, got %f", f); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/realtobits.v b/ivtest/ivltests/realtobits.v new file mode 100644 index 000000000..506c9af79 --- /dev/null +++ b/ivtest/ivltests/realtobits.v @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +/* + * Icarus Verilog declares that $realtobits shall return a 64bit + * number that is the normalized IEEE754 encoding of the real value. + * Whatever it takes to get that, it does. It should be easy in + * general, as most modern processors think in IEEE754 floating point + * anyhow. + */ + +module main; + + real val; + + initial begin + val = 0.0; + $display("val=%f (%h)", val, $realtobits(val)); + if ($realtobits(val) !== 64'h0000000000000000) begin + $display("FAILED"); + $finish; + end + + val = 1.0; + $display("val=%f (%h)", val, $realtobits(val)); + if ($realtobits(val) !== 64'h3ff0000000000000) begin + $display("FAILED"); + $finish; + end + + val = 0.5; + $display("val=%f (%h)", val, $realtobits(val)); + if ($realtobits(val) !== 64'h3fe0000000000000) begin + $display("FAILED"); + $finish; + end + + val = 1.5; + $display("val=%f (%h)", val, $realtobits(val)); + if ($realtobits(val) !== 64'h3ff8000000000000) begin + $display("FAILED"); + $finish; + end + + val = 1.125; + $display("val=%f (%h)", val, $realtobits(val)); + if ($realtobits(val) !== 64'h3ff2000000000000) begin + $display("FAILED"); + $finish; + end + + val = 2.6; + $display("val=%f (%h)", val, $realtobits(val)); + if ($realtobits(val) !== 64'h4004cccccccccccd) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/recursive_func.v b/ivtest/ivltests/recursive_func.v new file mode 100644 index 000000000..0b765071b --- /dev/null +++ b/ivtest/ivltests/recursive_func.v @@ -0,0 +1,43 @@ +module recursive_func(); + +function automatic [15:0] factorial; + +input [15:0] n; + +begin + factorial = (n > 1) ? factorial(n - 1) * n : n; +end + +endfunction + +reg [15:0] r1; +reg [15:0] r2; +reg [15:0] r3; + +initial begin + fork + r1 = factorial(3); + r2 = factorial(4); + r3 = factorial(5); + join + $display("factorial 3 = %0d", r1); + $display("factorial 4 = %0d", r2); + $display("factorial 5 = %0d", r3); +end + +wire [15:0] r4; +wire [15:0] r5; +wire [15:0] r6; + +assign r4 = factorial(6); +assign r5 = factorial(7); +assign r6 = factorial(8); + +initial begin + #1; + $display("factorial 6 = %0d", r4); + $display("factorial 7 = %0d", r5); + $display("factorial 8 = %0d", r6); +end + +endmodule diff --git a/ivtest/ivltests/recursive_task.v b/ivtest/ivltests/recursive_task.v new file mode 100644 index 000000000..a8ad69c68 --- /dev/null +++ b/ivtest/ivltests/recursive_task.v @@ -0,0 +1,40 @@ +module recursive_task(); + +task automatic factorial; + +input integer n; +output integer f; + +integer t; + +fork + begin + if (n > 1) + factorial(n - 1, t); + else + t = 1; + #1 f = n * t; + end + begin + @f $display("intermediate value = %0d", f); + end +join + +endtask + +integer r1; +integer r2; +integer r3; + +initial begin + fork + factorial(3, r1); + factorial(4, r2); + factorial(5, r3); + join + $display("factorial 3 = %0d", r1); + $display("factorial 4 = %0d", r2); + $display("factorial 5 = %0d", r3); +end + +endmodule diff --git a/ivtest/ivltests/redef_net_error.v b/ivtest/ivltests/redef_net_error.v new file mode 100644 index 000000000..bfadf2713 --- /dev/null +++ b/ivtest/ivltests/redef_net_error.v @@ -0,0 +1,5 @@ +module test; + +wire [7:0] value, value; + +endmodule diff --git a/ivtest/ivltests/redef_reg_error.v b/ivtest/ivltests/redef_reg_error.v new file mode 100644 index 000000000..477d98069 --- /dev/null +++ b/ivtest/ivltests/redef_reg_error.v @@ -0,0 +1,5 @@ +module test; + +reg [7:0] value, value; + +endmodule diff --git a/ivtest/ivltests/repeat1.v b/ivtest/ivltests/repeat1.v new file mode 100644 index 000000000..724a3caa6 --- /dev/null +++ b/ivtest/ivltests/repeat1.v @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program demonstrates a tricky aspect of the Verilog syntax. + * The problem is with the repeat statement. In fact, there is a + * question as to whether it is a repeat statement at all, or an + * event statement with a repeat modifier. These are the possibilities: + * + * procedural_timing_control_statement ::= + * delay_or_event_control statement_or_null + * + * delay_or_event_control ::= + * event_control + * | repeat ( expression ) event_control + * + * If this interpretation is used, then ``repeat (5) @(posedge clk)'' + * should be taken as a delay_or_event_control and the thread will + * block until the 5th clk posedge. + * + * loop_statement ::= + * repeat ( expression ) statement + * + * If *this* interpretation is used, then ``repeat (5)'' is the loop + * head is used and the statement in the example is executed 5 times. + * + * These two interpretations both appear to be perfectly valid. However, + * real tools use the loop_statement, so the standard must be considered + * broken and this interpretation used. + */ + +module main; + + reg clk = 1; + always #5 clk = ~clk; + + initial #1 + repeat (5) @(posedge clk) begin + if ($time !== 10) begin + $display("FAILED -- $time = %t", $time); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/repeat2.v b/ivtest/ivltests/repeat2.v new file mode 100644 index 000000000..8dafca69d --- /dev/null +++ b/ivtest/ivltests/repeat2.v @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg [3:0] test; + + initial begin +/* A zero count repeat by it self is not allowed by the standard, + test = {0{1'b1}}; + if (test !== 4'b0000) begin + $display("FAILED -- {0{1'b1} == %b", test); + $finish; + end + + but it can be used in a valid concatenation (1364-2005). */ + test = {{0{1'b1}}, 1'b0}; + if (test !== 4'b0000) begin + $display("FAILED -- {0{1'b1} == %b", test); + $finish; + end + + test = {1{1'b1}}; + if (test !== 4'b0001) begin + $display("FAILED -- {1{1'b1} == %b", test); + $finish; + end + + test = {2{1'b1}}; + if (test !== 4'b0011) begin + $display("FAILED -- {2{1'b1} == %b", test); + $finish; + end + + test = {3{1'b1}}; + if (test !== 4'b0111) begin + $display("FAILED -- {3{1'b1} == %b", test); + $finish; + end + + test = {4{1'b1}}; + if (test !== 4'b1111) begin + $display("FAILED -- {4{1'b1} == %b", test); + $finish; + end + + test = {5{1'b1}}; + if (test !== 4'b1111) begin + $display("FAILED -- {5{1'b1} == %b", test); + $finish; + end + + $display("PASSED"); + + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/repeat_expr_probe.v b/ivtest/ivltests/repeat_expr_probe.v new file mode 100644 index 000000000..90a87ec15 --- /dev/null +++ b/ivtest/ivltests/repeat_expr_probe.v @@ -0,0 +1,14 @@ +module top; + reg [2:0] delay; + integer lp; + + initial begin + lp = 0; + delay = 3'b000; + // The delay+4 expression was failing because probe_expr_width() was + // not called before elab_and_eval() with an expression width of -1. + repeat (delay+4) lp = lp + 1; + if (lp != 4) $display("FAILED"); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/repl_zero_wid_fail.v b/ivtest/ivltests/repl_zero_wid_fail.v new file mode 100644 index 000000000..58b6bcb6a --- /dev/null +++ b/ivtest/ivltests/repl_zero_wid_fail.v @@ -0,0 +1,7 @@ +module top; + reg [7:0] result; + + initial begin + result = {0{1'b1}}; // This fails top level zero replication. + end +endmodule diff --git a/ivtest/ivltests/repl_zero_wid_pass.v b/ivtest/ivltests/repl_zero_wid_pass.v new file mode 100644 index 000000000..e81e3ee43 --- /dev/null +++ b/ivtest/ivltests/repl_zero_wid_pass.v @@ -0,0 +1,20 @@ +module top; + reg pass = 1'b1; + reg [7:0] result; + + initial begin + result = {{0{1'b1}}, 2'b11}; + if (result != 8'h03) begin + $display("FAILED: replication inside of concatenation"); + pass = 1'b0; + end + + result = {2{{0{1'b1}}, 2'b11}}; + if (result != 8'h0f) begin + $display("FAILED: replication inside of replication"); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/resetall.v b/ivtest/ivltests/resetall.v new file mode 100644 index 000000000..536737f8d --- /dev/null +++ b/ivtest/ivltests/resetall.v @@ -0,0 +1,37 @@ +module top_default; + initial begin + $printtimescale(top_default); + $printtimescale(top_timescale); + $printtimescale(top_resetall); + $printtimescale(top_timescale2); + $printtimescale(top_timescale3); + end +endmodule + +`resetall +`timescale 1ns/1ns +module top_timescale; + reg a; + initial a = 1'b1; +endmodule + +`resetall +`resetall +module top_resetall; + reg a; + initial a = 1'b0; +endmodule + +`resetall +`timescale 1ms/1ms +module top_timescale2; + reg a; + initial a = 1'b1; +endmodule + +`resetall +`timescale 1us/1us +module top_timescale3; + reg a; + initial a = 1'bz; +endmodule diff --git a/ivtest/ivltests/resetall2.v b/ivtest/ivltests/resetall2.v new file mode 100644 index 000000000..c5df051e8 --- /dev/null +++ b/ivtest/ivltests/resetall2.v @@ -0,0 +1,14 @@ +`timescale 1us/1us +module top_timescale; + initial begin + $printtimescale(top_timescale); + $printtimescale(top_timescale2); + end +endmodule + +`resetall +`timescale 1ns/1ns +module top_timescale2; + reg a; + initial a = 1'b1; +endmodule diff --git a/ivtest/ivltests/resolv1.v b/ivtest/ivltests/resolv1.v new file mode 100644 index 000000000..a5ac859c2 --- /dev/null +++ b/ivtest/ivltests/resolv1.v @@ -0,0 +1,29 @@ +module test; + +wire w; +wire q; +reg g; + +pullup(w); +bufif1(w, 1'b1, g); +pmos(q, w, 1'b0); +bufif0(q, 1'b0, g); + +initial + begin + g = 1; + #10 + $display(q, w); // should print "11" + #20 + g = 0; // w changes from St1 to Pu1 + #30 + $display(q, w); // should print "01" + if (q == 1'b0) + $display("PASSED"); + else + $display("FAILED"); + #40 + $finish; + end + +endmodule diff --git a/ivtest/ivltests/rise_fall_decay1.v b/ivtest/ivltests/rise_fall_decay1.v new file mode 100644 index 000000000..e4009cdaa --- /dev/null +++ b/ivtest/ivltests/rise_fall_decay1.v @@ -0,0 +1,66 @@ +module test(); + +localparam [7:0] dly1 = 4; +wire [7:0] dly2 = 3; +reg [7:0] dly3 = 2; + +reg i; +wire [6:1] o; + +assign #(dly1, dly2, dly3) o[1] = i; +assign #(dly2, dly3, dly1) o[2] = i; +assign #(dly3, dly1, dly2) o[3] = i; +assign #(dly2-1, dly2-2, dly2-3) o[4] = i; +assign #(dly3+1, dly3+2, dly3+3) o[5] = i; +assign #(4, 3, 2) o[6] = i; + +function check(input o1, input o2, input o3, input o4, input o5, input o6); + +begin + check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3) + && (o[4] == o4) && (o[5] == o5) && (o[6] == o6); +end + +endfunction + +reg failed = 0; + +initial begin + #1 $monitor($time,,i,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]); + + i = 1'b1; + #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bx, 1'bx, 1'b1, 1'b1, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bx, 1'b1, 1'b1, 1'b1, 1'b1, 1'bx)) failed = 1; + #1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1; + + i = 1'b0; + #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1; + #1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b1)) failed = 1; + #1; #0 if (!check(1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1)) failed = 1; + #1; #0 if (!check(1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0)) failed = 1; + #1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0)) failed = 1; + + i = 1'bx; + #0 if (!check(1'b0, 1'b0, 1'b0, 1'bx, 1'b0, 1'b0)) failed = 1; + #1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'bx, 1'b0, 1'b0)) failed = 1; + #1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'b0, 1'bx)) failed = 1; + #1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1; + + i = 1'bz; + #0 if (!check(1'bx, 1'bx, 1'bx, 1'bz, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bz, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bz, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bz, 1'bx, 1'bx, 1'bz, 1'bx, 1'bz)) failed = 1; + #1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bx, 1'bz)) failed = 1; + #1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz)) failed = 1; + + #1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/rise_fall_decay2.v b/ivtest/ivltests/rise_fall_decay2.v new file mode 100644 index 000000000..784ab3bd1 --- /dev/null +++ b/ivtest/ivltests/rise_fall_decay2.v @@ -0,0 +1,66 @@ +module test(); + +localparam [7:0] dly1 = 4; +wire [7:0] dly2 = 3; +reg [7:0] dly3 = 2; + +reg i; +wire [6:1] o; + +nmos #(dly1, dly2, dly3) buf1(o[1], i, 1'b1); +nmos #(dly2, dly3, dly1) buf2(o[2], i, 1'b1); +nmos #(dly3, dly1, dly2) buf3(o[3], i, 1'b1); +nmos #(dly2-1, dly2-2, dly2-3) buf4(o[4], i, 1'b1); +nmos #(dly3+1, dly3+2, dly3+3) buf5(o[5], i, 1'b1); +nmos #(4, 3, 2) buf6(o[6], i, 1'b1); + +function check(input o1, input o2, input o3, input o4, input o5, input o6); + +begin + check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3) + && (o[4] == o4) && (o[5] == o5) && (o[6] == o6); +end + +endfunction + +reg failed = 0; + +initial begin + #1 $monitor($time,,i,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]); + + i = 1'b1; + #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bx, 1'bx, 1'b1, 1'b1, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bx, 1'b1, 1'b1, 1'b1, 1'b1, 1'bx)) failed = 1; + #1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1; + + i = 1'b0; + #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1; + #1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b1)) failed = 1; + #1; #0 if (!check(1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1)) failed = 1; + #1; #0 if (!check(1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0)) failed = 1; + #1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0)) failed = 1; + + i = 1'bx; + #0 if (!check(1'b0, 1'b0, 1'b0, 1'bx, 1'b0, 1'b0)) failed = 1; + #1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'bx, 1'b0, 1'b0)) failed = 1; + #1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'b0, 1'bx)) failed = 1; + #1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1; + + i = 1'bz; + #0 if (!check(1'bx, 1'bx, 1'bx, 1'bz, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bz, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bz, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bz, 1'bx, 1'bx, 1'bz, 1'bx, 1'bz)) failed = 1; + #1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bx, 1'bz)) failed = 1; + #1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz)) failed = 1; + + #1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/rise_fall_delay1.v b/ivtest/ivltests/rise_fall_delay1.v new file mode 100644 index 000000000..87145cb62 --- /dev/null +++ b/ivtest/ivltests/rise_fall_delay1.v @@ -0,0 +1,62 @@ +module test(); + +localparam [7:0] dly1 = 1; +wire [7:0] dly2 = 2; +reg [7:0] dly3 = 3; + +reg i; +wire [6:1] o; + +assign #(dly1, dly2) o[1] = i; +assign #(dly2, dly1) o[2] = i; +assign #(dly1, dly3) o[3] = i; +assign #(dly3, dly1) o[4] = i; +assign #(dly2, dly3+1) o[5] = i; +assign #(4, 2) o[6] = i; + +function check(input o1, input o2, input o3, input o4, input o5, input o6); + +begin + check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3) + && (o[4] == o4) && (o[5] == o5) && (o[6] == o6); +end + +endfunction + +reg failed = 0; + +initial begin + #1 $monitor($time,,i,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]); + + i = 1'b1; + #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'b1, 1'bx, 1'b1, 1'bx, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'bx, 1'b1, 1'bx)) failed = 1; + #1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'bx)) failed = 1; + #1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1; + + i = 1'b0; + #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1; + #1; #0 if (!check(1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1)) failed = 1; + #1; #0 if (!check(1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0)) failed = 1; + #1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0)) failed = 1; + #1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0)) failed = 1; + + i = 1'bx; + #0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0)) failed = 1; + #1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'b0, 1'b0)) failed = 1; + #1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1; + + i = 1'bz; + #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz)) failed = 1; + + #1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/rise_fall_delay2.v b/ivtest/ivltests/rise_fall_delay2.v new file mode 100644 index 000000000..800539969 --- /dev/null +++ b/ivtest/ivltests/rise_fall_delay2.v @@ -0,0 +1,62 @@ +module test(); + +localparam [7:0] dly1 = 1; +wire [7:0] dly2 = 2; +reg [7:0] dly3 = 3; + +reg i; +wire [6:1] o; + +buf #(dly1, dly2) buf1(o[1], i); +buf #(dly2, dly1) buf2(o[2], i); +buf #(dly1, dly3) buf3(o[3], i); +buf #(dly3, dly1) buf4(o[4], i); +buf #(dly2, dly3+1) buf5(o[5], i); +buf #(4, 2) buf6(o[6], i); + +function check(input o1, input o2, input o3, input o4, input o5, input o6); + +begin + check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3) + && (o[4] == o4) && (o[5] == o5) && (o[6] == o6); +end + +endfunction + +reg failed = 0; + +initial begin + #1 $monitor($time,,i,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]); + + i = 1'b1; + #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'b1, 1'bx, 1'b1, 1'bx, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'bx, 1'b1, 1'bx)) failed = 1; + #1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'bx)) failed = 1; + #1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1; + + i = 1'b0; + #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1; + #1; #0 if (!check(1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1)) failed = 1; + #1; #0 if (!check(1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0)) failed = 1; + #1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0)) failed = 1; + #1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0)) failed = 1; + + i = 1'bx; + #0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0)) failed = 1; + #1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'b0, 1'b0)) failed = 1; + #1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1; + + i = 1'bz; + #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz)) failed = 1; + + #1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/rise_fall_delay3.v b/ivtest/ivltests/rise_fall_delay3.v new file mode 100644 index 000000000..f5f239037 --- /dev/null +++ b/ivtest/ivltests/rise_fall_delay3.v @@ -0,0 +1,53 @@ +module test(); + +localparam [7:0] dly1 = 1; +wire [7:0] dly2 = 2; +reg [7:0] dly3 = 3; + +reg en; +wire i = 1; +wire [6:1] o; + +tranif1 #(dly1, dly2) buf1(o[1], i, en); +tranif1 #(dly2, dly1) buf2(o[2], i, en); +tranif1 #(dly1, dly3) buf3(o[3], i, en); +tranif1 #(dly3, dly1) buf4(o[4], i, en); +tranif1 #(dly2, dly3+1) buf5(o[5], i, en); +tranif1 #(4, 2) buf6(o[6], i, en); + +function check(input o1, input o2, input o3, input o4, input o5, input o6); + +begin + check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3) + && (o[4] == o4) && (o[5] == o5) && (o[6] == o6); +end + +endfunction + +reg failed = 0; + +initial begin + #1 $monitor($time,,en,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]); + + en = 1'b1; + #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'b1, 1'bx, 1'b1, 1'bx, 1'bx, 1'bx)) failed = 1; + #1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'bx, 1'b1, 1'bx)) failed = 1; + #1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'bx)) failed = 1; + #1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1; + + en = 1'b0; + #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1; + #1; #0 if (!check(1'b1, 1'bz, 1'b1, 1'bz, 1'b1, 1'b1)) failed = 1; + #1; #0 if (!check(1'bz, 1'bz, 1'b1, 1'bz, 1'b1, 1'bz)) failed = 1; + #1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'b1, 1'bz)) failed = 1; + #1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz)) failed = 1; + + #1; + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/rl_pow.v b/ivtest/ivltests/rl_pow.v new file mode 100644 index 000000000..8af03118b --- /dev/null +++ b/ivtest/ivltests/rl_pow.v @@ -0,0 +1,47 @@ +`timescale 1us/100ns + +module top; + reg pass = 1'b1; + + real ra, rb, rpow; + + initial begin + ra = 1.0; rb = 2.0; + rpow = ra ** rb; + if (rpow != 1.0) begin + pass = 1'b0; + $display("Real: power value not correct, expected 1.0 got %g.", rpow); + end + + ra = 2.0; + rpow = ra ** rb; + if (rpow != 4.0) begin + pass = 1'b0; + $display("Real: power value not correct, expected 4.0 got %g.", rpow); + end + + ra = 0.0; + rpow = ra ** rb; + if (rpow != 0.0) begin + pass = 1'b0; + $display("Real: power value not correct, expected 0.0 got %g.", rpow); + end + + ra = 10.0; + rpow = ra ** rb; + if (rpow != 100.0) begin + pass = 1'b0; + $display("Real: power value not correct, expected 100.0 got %g.", rpow); + end + + ra = 0.0; rb = -1.0; + rpow = ra ** rb; + $display("0.0 ** -1.0 = %g", rpow); + + ra = -1.0; rb = 2.5; + rpow = ra ** rb; + $display("-1.0 ** 2.5 = %g", rpow); + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/rnpmos.v b/ivtest/ivltests/rnpmos.v new file mode 100644 index 000000000..d833e27c9 --- /dev/null +++ b/ivtest/ivltests/rnpmos.v @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + wire no, po; + reg d, c; + + rnmos n (no, d, c); + rpmos p (po, d, c); + + initial begin + c = 0; + d = 0; + + #1 if (no !== 1'bz) begin + $display("FAILED -- n (%b, %b, %b)", no, d, c); + $finish; + end + + if (po !== 1'b0) begin + $display("FAILED -- p (%b, %b, %b)", po, d, c); + $finish; + end + + d = 1; + + #1 if (no !== 1'bz) begin + $display("FAILED -- n (%b, %b, %b)", no, d, c); + $finish; + end + + if (po !== 1'b1) begin + $display("FAILED -- p (%b, %b, %b)", po, d, c); + $finish; + end + + c = 1; + + #1 if (no !== 1'b1) begin + $display("FAILED -- n (%b, %b, %b)", no, d, c); + $finish; + end + + if (po !== 1'bz) begin + $display("FAILED -- p (%b, %b, %b)", po, d, c); + $finish; + end + + d = 0; + + #1 if (no !== 1'b0) begin + $display("FAILED -- n (%b, %b, %b)", no, d, c); + $finish; + end + + if (po !== 1'bz) begin + $display("FAILED -- p (%b, %b, %b)", po, d, c); + $finish; + end + + $display("PASSED"); + + end + +endmodule // main diff --git a/ivtest/ivltests/rnpmos2.v b/ivtest/ivltests/rnpmos2.v new file mode 100644 index 000000000..b71f97657 --- /dev/null +++ b/ivtest/ivltests/rnpmos2.v @@ -0,0 +1,91 @@ +// Copyright (c) 2001 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + + +/* + * This module implements what essentially amounts to an array of DFF + * devices with output enable. This test checks the operation of the + * pmos and nmos devices. + */ +module grayGap (ad, clk, read, write); + + output [31:0] ad; + input clk, read, write; + + reg [15:0] regff; + + rpmos ad_drv [31:0] (ad, {16'b0, regff}, read); + + always @(posedge clk) + if (write) regff = ad[15:0]; + + +endmodule + + +module main; + + wire [31:0] ad; + reg clk, read, write; + + reg [31:0] ad_val; + reg ad_en; + + rnmos ad_drv[31:0] (ad, ad_val, ad_en); + + grayGap test (ad, clk, read, write); + + always #10 clk = ~clk; + + initial begin + clk = 1; + read = 1; + write = 0; + $monitor($time, "ad=%b", ad); + + // Set up to write a value into the grayGap register. + @(negedge clk) + ad_val = 32'haaaa_aaaa; + read = 1; + write = 1; + ad_en = 1; + + // The posedge has passed, now set up to read that value + // out. Turn all the drivers off for a moment, to see that the + // line becomes tri-state... + @(negedge clk) + ad_en = 0; + write = 0; + + // Now read the value. + #1 read = 0; + + #1 $display("Wrote %h, got %h", ad_val, ad); + + if (ad !== 32'b0000_0000_0000_0000_1010_1010_1010_1010) begin + $display("FAILED -- ad is %b", ad); + $finish; + end + + #2 read = 1; + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/rop.v b/ivtest/ivltests/rop.v new file mode 100644 index 000000000..16437e596 --- /dev/null +++ b/ivtest/ivltests/rop.v @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// $Id: rop.v,v 1.2 2001/06/20 00:04:09 ka6s Exp $ +// $Log: rop.v,v $ +// Revision 1.2 2001/06/20 00:04:09 ka6s +// Updated the code to print out "PASSED" when appropriate. +// +// Revision 1.1 2001/06/19 13:52:13 ka6s +// Added 4 tests from Stephan Boettcher +// +// +// Test of === operator + +module rop; + + reg [2:0] a; + reg b; + reg error; + + initial + begin + error = 0; + a = 3'b 10z; + b = & a; + $display(" & 3'b%b === %b", a, b); + if (b !== 1'b0) + begin + $display("FAILED"); + error = 1; + end + b = | a; + $display(" | 3'b%b === %b", a, b); + if (b !== 1'b1) + begin + error = 1; + $display("FAILED"); + end + b = ^ a; + $display(" ^ 3'b%b === %b", a, b); + if (b !== 1'bx) + begin + $display("FAILED"); + error = 1; + end + b = ~& a; + $display("~& 3'b%b === %b", a, b); + if (b !== 1'b1) + begin + $display("FAILED"); + error = 1; + end + b = ~| a; + $display("~| 3'b%b === %b", a, b); + if (b !== 1'b0) + begin + $display("FAILED"); + error = 1; + end + b = ~^ a; + $display("~^ 3'b%b === %b", a, b); + if (b !== 1'bx) + begin + $display("FAILED"); + error = 1; + end + a = 3'b 0xz; + b = & a; + $display(" & 3'b%b === %b", a, b); + if (b !== 1'b0) + begin + $display("FAILED"); + error = 1; + end + b = | a; + $display(" | 3'b%b === %b", a, b); + if (b !== 1'bx) + begin + $display("FAILED"); + error = 1; + end + b = ^ a; + $display(" ^ 3'b%b === %b", a, b); + if (b !== 1'bx) + begin + $display("FAILED"); + error = 1; + end + b = ~& a; + $display("~& 3'b%b === %b", a, b); + if (b !== 1'b1) + begin + $display("FAILED"); + error = 1; + end + b = ~| a; + $display("~| 3'b%b === %b", a, b); + if (b !== 1'bx) + begin + $display("FAILED"); + error = 1; + end + b = ~^ a; + $display("~^ 3'b%b === %b", a, b); + if (b !== 1'bx) + begin + $display("FAILED"); + error = 1; + end + a = 3'b 1xz; + b = & a; + $display(" & 3'b%b === %b", a, b); + if (b !== 1'bx) + begin + $display("FAILED"); + error = 1; + end + b = | a; + $display(" | 3'b%b === %b", a, b); + if (b !== 1'b1) + begin + $display("FAILED"); + error = 1; + end + b = ^ a; + $display(" ^ 3'b%b === %b", a, b); + if (b !== 1'bx) + begin + $display("FAILED"); + error = 1; + end + b = ~& a; + $display("~& 3'b%b === %b", a, b); + if (b !== 1'bx) + begin + $display("FAILED"); + error = 1; + end + b = ~| a; + $display("~| 3'b%b === %b", a, b); + if (b !== 1'b0) + begin + $display("FAILED"); + error = 1; + end + b = ~^ a; + $display("~^ 3'b%b === %b", a, b); + if (b !== 1'bx) + begin + $display("FAILED"); + error = 1; + end + a = 3'b 000; + b = & a; + $display(" & 3'b%b === %b", a, b); + if (b !== 1'b0) + begin + $display("FAILED"); + error = 1; + end + b = | a; + $display(" | 3'b%b === %b", a, b); + if (b !== 1'b0) + begin + $display("FAILED"); + error = 1; + end + b = ^ a; + $display(" ^ 3'b%b === %b", a, b); + if (b !== 1'b0) + begin + $display("FAILED"); + error = 1; + end + b = ~& a; + $display("~& 3'b%b === %b", a, b); + if (b !== 1'b1) + begin + $display("FAILED"); + error = 1; + end + b = ~| a; + $display("~| 3'b%b === %b", a, b); + if (b !== 1'b1) + begin + $display("FAILED"); + error = 1; + end + b = ~^ a; + $display("~^ 3'b%b === %b", a, b); + if (b !== 1'b1) + begin + $display("FAILED"); + error = 1; + end + a = 3'b 111; + b = & a; + $display(" & 3'b%b === %b", a, b); + if (b !== 1'b1) + begin + $display("FAILED"); + error = 1; + end + b = | a; + $display(" | 3'b%b === %b", a, b); + if (b !== 1'b1) + begin + $display("FAILED"); + error = 1; + end + b = ^ a; + $display(" ^ 3'b%b === %b", a, b); + if (b !== 1'b1) + begin + $display("FAILED"); + error = 1; + end + b = ~& a; + $display("~& 3'b%b === %b", a, b); + if (b !== 1'b0) + begin + $display("FAILED"); + error = 1; + end + b = ~| a; + $display("~| 3'b%b === %b", a, b); + if (b !== 1'b0) + begin + $display("FAILED"); + error = 1; + end + b = ~^ a; + $display("~^ 3'b%b === %b", a, b); + if (b !== 1'b0) + begin + $display("FAILED"); + error = 1; + end + if(error === 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/rptconcat.v b/ivtest/ivltests/rptconcat.v new file mode 100644 index 000000000..ec0e6ac7e --- /dev/null +++ b/ivtest/ivltests/rptconcat.v @@ -0,0 +1,36 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate repeat concatenation literal behavior. +// +module test (); + +wire [7:0] result; + +assign result = {2{4'b1011}}; + +initial + begin + #1; + if(result === 8'b10111011) + $display("PASSED"); + else + $display("FAILED - {2{4'b1011}} s/b 8'b10111011 - is %b",result); + end + +endmodule diff --git a/ivtest/ivltests/rptconcat2.v b/ivtest/ivltests/rptconcat2.v new file mode 100644 index 000000000..bf00df5ee --- /dev/null +++ b/ivtest/ivltests/rptconcat2.v @@ -0,0 +1,15 @@ +module main(); + reg [3:0] d, e; + initial begin + d <= {4{1'b1}}; + e = {4{1'b1}}; + #1; + $display("%b %b",d,e); + if (d !== e) begin + $display("FAILED -- %b !== %b", d, e); + $finish; + end + $display("PASSED"); + + end +endmodule diff --git a/ivtest/ivltests/rtran.v b/ivtest/ivltests/rtran.v new file mode 100644 index 000000000..3088ee3fb --- /dev/null +++ b/ivtest/ivltests/rtran.v @@ -0,0 +1,122 @@ +module test(); + +reg a, b; + +wire a1, a2, a3, a4, a5, a6, a7; + +assign (supply1, supply0) a1 = a; + +rtran t1(a1, a2); +rtran t2(a2, a3); +rtran t3(a3, a4); +rtran t4(a4, a5); +rtran t5(a5, a6); +rtran t6(a6, a7); + +wire a11, a12, a13, a14, a15, b11, b12, b13, b14, b15; +wire a21, a22, a23, a24, a25, b21, b22, b23, b24, b25; +wire a31, a32, a33, a34, a35, b31, b32, b33, b34, b35; +wire a41, a42, a43, a44, a45, b41, b42, b43, b44, b45; +wire a51, a52, a53, a54, a55, b51, b52, b53, b54, b55; + +assign (supply1, supply0) a11 = a, b11 = b; +assign (supply1, strong0) a12 = a, b12 = b; +assign (supply1, pull0) a13 = a, b13 = b; +assign (supply1, weak0) a14 = a, b14 = b; +assign (supply1, highz0) a15 = a, b15 = b; + +assign (strong1, supply0) a21 = a, b21 = b; +assign (strong1, strong0) a22 = a, b22 = b; +assign (strong1, pull0) a23 = a, b23 = b; +assign (strong1, weak0) a24 = a, b24 = b; +assign (strong1, highz0) a25 = a, b25 = b; + +assign ( pull1, supply0) a31 = a, b31 = b; +assign ( pull1, strong0) a32 = a, b32 = b; +assign ( pull1, pull0) a33 = a, b33 = b; +assign ( pull1, weak0) a34 = a, b34 = b; +assign ( pull1, highz0) a35 = a, b35 = b; + +assign ( weak1, supply0) a41 = a, b41 = b; +assign ( weak1, strong0) a42 = a, b42 = b; +assign ( weak1, pull0) a43 = a, b43 = b; +assign ( weak1, weak0) a44 = a, b44 = b; +assign ( weak1, highz0) a45 = a, b45 = b; + +assign ( highz1, supply0) a51 = a, b51 = b; +assign ( highz1, strong0) a52 = a, b52 = b; +assign ( highz1, pull0) a53 = a, b53 = b; +assign ( highz1, weak0) a54 = a, b54 = b; + +rtran t11(a11, b11); +rtran t12(a12, b12); +rtran t13(a13, b13); +rtran t14(a14, b14); +rtran t15(a15, b15); + +rtran t21(a21, b21); +rtran t22(a22, b22); +rtran t23(a23, b23); +rtran t24(a24, b24); +rtran t25(a25, b25); + +rtran t31(a31, b31); +rtran t32(a32, b32); +rtran t33(a33, b33); +rtran t34(a34, b34); +rtran t35(a35, b35); + +rtran t41(a41, b41); +rtran t42(a42, b42); +rtran t43(a43, b43); +rtran t44(a44, b44); +rtran t45(a45, b45); + +rtran t51(a51, b51); +rtran t52(a52, b52); +rtran t53(a53, b53); +rtran t54(a54, b54); +rtran t55(a55, b55); + +task display_strengths; + +input ta, tb; + +begin + a = ta; + b = tb; + #1; + $display("a = %b b = %b", a, b); + $display("a1(%v) a2(%v) a3(%v) a4(%v) a5(%v) a6(%v) a7(%v)", a1, a2, a3, a4, a5, a6, a7); + $display("t11(%v %v) t12(%v %v) t13(%v %v) t14(%v %v) t15(%v %v)", a11, b11, a12, b12, a13, b13, a14, b14, a15, b15); + $display("t21(%v %v) t22(%v %v) t23(%v %v) t24(%v %v) t25(%v %v)", a21, b21, a22, b22, a23, b23, a24, b24, a25, b25); + $display("t31(%v %v) t32(%v %v) t33(%v %v) t34(%v %v) t35(%v %v)", a31, b31, a32, b32, a33, b33, a34, b34, a35, b35); + $display("t41(%v %v) t42(%v %v) t43(%v %v) t44(%v %v) t45(%v %v)", a41, b41, a42, b42, a43, b43, a44, b44, a45, b45); + $display("t51(%v %v) t52(%v %v) t53(%v %v) t54(%v %v) t55(%v %v)", a51, b51, a52, b52, a53, b53, a54, b54, a55, b55); +end + +endtask + +initial begin + display_strengths(1'bz, 1'bz); + display_strengths(1'bx, 1'bz); + display_strengths(1'b0, 1'bz); + display_strengths(1'b1, 1'bz); + + display_strengths(1'bz, 1'bx); + display_strengths(1'bx, 1'bx); + display_strengths(1'b0, 1'bx); + display_strengths(1'b1, 1'bx); + + display_strengths(1'bz, 1'b0); + display_strengths(1'bx, 1'b0); + display_strengths(1'b0, 1'b0); + display_strengths(1'b1, 1'b0); + + display_strengths(1'bz, 1'b1); + display_strengths(1'bx, 1'b1); + display_strengths(1'b0, 1'b1); + display_strengths(1'b1, 1'b1); +end + +endmodule diff --git a/ivtest/ivltests/rtranif0.v b/ivtest/ivltests/rtranif0.v new file mode 100644 index 000000000..e025257ad --- /dev/null +++ b/ivtest/ivltests/rtranif0.v @@ -0,0 +1,183 @@ +module test(); + +reg a, b, en; + +wire a1, a2, a3, a4, a5, a6, a7; + +assign (supply1, supply0) a1 = a; + +rtranif0 t1(a1, a2, en); +rtranif0 t2(a2, a3, en); +rtranif0 t3(a3, a4, en); +rtranif0 t4(a4, a5, en); +rtranif0 t5(a5, a6, en); +rtranif0 t6(a6, a7, en); + +wire a11, a12, a13, a14, a15, b11, b12, b13, b14, b15; +wire a21, a22, a23, a24, a25, b21, b22, b23, b24, b25; +wire a31, a32, a33, a34, a35, b31, b32, b33, b34, b35; +wire a41, a42, a43, a44, a45, b41, b42, b43, b44, b45; +wire a51, a52, a53, a54, a55, b51, b52, b53, b54, b55; + +assign (supply1, supply0) a11 = a, b11 = b; +assign (supply1, strong0) a12 = a, b12 = b; +assign (supply1, pull0) a13 = a, b13 = b; +assign (supply1, weak0) a14 = a, b14 = b; +assign (supply1, highz0) a15 = a, b15 = b; + +assign (strong1, supply0) a21 = a, b21 = b; +assign (strong1, strong0) a22 = a, b22 = b; +assign (strong1, pull0) a23 = a, b23 = b; +assign (strong1, weak0) a24 = a, b24 = b; +assign (strong1, highz0) a25 = a, b25 = b; + +assign ( pull1, supply0) a31 = a, b31 = b; +assign ( pull1, strong0) a32 = a, b32 = b; +assign ( pull1, pull0) a33 = a, b33 = b; +assign ( pull1, weak0) a34 = a, b34 = b; +assign ( pull1, highz0) a35 = a, b35 = b; + +assign ( weak1, supply0) a41 = a, b41 = b; +assign ( weak1, strong0) a42 = a, b42 = b; +assign ( weak1, pull0) a43 = a, b43 = b; +assign ( weak1, weak0) a44 = a, b44 = b; +assign ( weak1, highz0) a45 = a, b45 = b; + +assign ( highz1, supply0) a51 = a, b51 = b; +assign ( highz1, strong0) a52 = a, b52 = b; +assign ( highz1, pull0) a53 = a, b53 = b; +assign ( highz1, weak0) a54 = a, b54 = b; + +rtranif0 t11(a11, b11, en); +rtranif0 t12(a12, b12, en); +rtranif0 t13(a13, b13, en); +rtranif0 t14(a14, b14, en); +rtranif0 t15(a15, b15, en); + +rtranif0 t21(a21, b21, en); +rtranif0 t22(a22, b22, en); +rtranif0 t23(a23, b23, en); +rtranif0 t24(a24, b24, en); +rtranif0 t25(a25, b25, en); + +rtranif0 t31(a31, b31, en); +rtranif0 t32(a32, b32, en); +rtranif0 t33(a33, b33, en); +rtranif0 t34(a34, b34, en); +rtranif0 t35(a35, b35, en); + +rtranif0 t41(a41, b41, en); +rtranif0 t42(a42, b42, en); +rtranif0 t43(a43, b43, en); +rtranif0 t44(a44, b44, en); +rtranif0 t45(a45, b45, en); + +rtranif0 t51(a51, b51, en); +rtranif0 t52(a52, b52, en); +rtranif0 t53(a53, b53, en); +rtranif0 t54(a54, b54, en); +rtranif0 t55(a55, b55, en); + +task display_strengths; + +input ta, tb, ten; + +begin + a = ta; + b = tb; + en = ten; + #1; + $display("a = %b b = %b en = %b", a, b, en); + $display("a1(%v) a2(%v) a3(%v) a4(%v) a5(%v) a6(%v) a7(%v)", a1, a2, a3, a4, a5, a6, a7); + $display("t11(%v %v) t12(%v %v) t13(%v %v) t14(%v %v) t15(%v %v)", a11, b11, a12, b12, a13, b13, a14, b14, a15, b15); + $display("t21(%v %v) t22(%v %v) t23(%v %v) t24(%v %v) t25(%v %v)", a21, b21, a22, b22, a23, b23, a24, b24, a25, b25); + $display("t31(%v %v) t32(%v %v) t33(%v %v) t34(%v %v) t35(%v %v)", a31, b31, a32, b32, a33, b33, a34, b34, a35, b35); + $display("t41(%v %v) t42(%v %v) t43(%v %v) t44(%v %v) t45(%v %v)", a41, b41, a42, b42, a43, b43, a44, b44, a45, b45); + $display("t51(%v %v) t52(%v %v) t53(%v %v) t54(%v %v) t55(%v %v)", a51, b51, a52, b52, a53, b53, a54, b54, a55, b55); +end + +endtask + +initial begin + display_strengths(1'bz, 1'bz, 1'bz); + display_strengths(1'bz, 1'bz, 1'bx); + display_strengths(1'bz, 1'bz, 1'b0); + display_strengths(1'bz, 1'bz, 1'b1); + + display_strengths(1'bx, 1'bz, 1'bz); + display_strengths(1'bx, 1'bz, 1'bx); + display_strengths(1'bx, 1'bz, 1'b0); + display_strengths(1'bx, 1'bz, 1'b1); + + display_strengths(1'b0, 1'bz, 1'bz); + display_strengths(1'b0, 1'bz, 1'bx); + display_strengths(1'b0, 1'bz, 1'b0); + display_strengths(1'b0, 1'bz, 1'b1); + + display_strengths(1'b1, 1'bz, 1'bz); + display_strengths(1'b1, 1'bz, 1'bx); + display_strengths(1'b1, 1'bz, 1'b0); + display_strengths(1'b1, 1'bz, 1'b1); + + display_strengths(1'bz, 1'bx, 1'bz); + display_strengths(1'bz, 1'bx, 1'bx); + display_strengths(1'bz, 1'bx, 1'b0); + display_strengths(1'bz, 1'bx, 1'b1); + + display_strengths(1'bx, 1'bx, 1'bz); + display_strengths(1'bx, 1'bx, 1'bx); + display_strengths(1'bx, 1'bx, 1'b0); + display_strengths(1'bx, 1'bx, 1'b1); + + display_strengths(1'b0, 1'bx, 1'bz); + display_strengths(1'b0, 1'bx, 1'bx); + display_strengths(1'b0, 1'bx, 1'b0); + display_strengths(1'b0, 1'bx, 1'b1); + + display_strengths(1'b1, 1'bx, 1'bz); + display_strengths(1'b1, 1'bx, 1'bx); + display_strengths(1'b1, 1'bx, 1'b0); + display_strengths(1'b1, 1'bx, 1'b1); + + display_strengths(1'bz, 1'b0, 1'bz); + display_strengths(1'bz, 1'b0, 1'bx); + display_strengths(1'bz, 1'b0, 1'b0); + display_strengths(1'bz, 1'b0, 1'b1); + + display_strengths(1'bx, 1'b0, 1'bz); + display_strengths(1'bx, 1'b0, 1'bx); + display_strengths(1'bx, 1'b0, 1'b0); + display_strengths(1'bx, 1'b0, 1'b1); + + display_strengths(1'b0, 1'b0, 1'bz); + display_strengths(1'b0, 1'b0, 1'bx); + display_strengths(1'b0, 1'b0, 1'b0); + display_strengths(1'b0, 1'b0, 1'b1); + + display_strengths(1'b1, 1'b0, 1'bz); + display_strengths(1'b1, 1'b0, 1'bx); + display_strengths(1'b1, 1'b0, 1'b0); + display_strengths(1'b1, 1'b0, 1'b1); + + display_strengths(1'bz, 1'b1, 1'bz); + display_strengths(1'bz, 1'b1, 1'bx); + display_strengths(1'bz, 1'b1, 1'b0); + display_strengths(1'bz, 1'b1, 1'b1); + + display_strengths(1'bx, 1'b1, 1'bz); + display_strengths(1'bx, 1'b1, 1'bx); + display_strengths(1'bx, 1'b1, 1'b0); + display_strengths(1'bx, 1'b1, 1'b1); + + display_strengths(1'b0, 1'b1, 1'bz); + display_strengths(1'b0, 1'b1, 1'bx); + display_strengths(1'b0, 1'b1, 1'b0); + display_strengths(1'b0, 1'b1, 1'b1); + + display_strengths(1'b1, 1'b1, 1'bz); + display_strengths(1'b1, 1'b1, 1'bx); + display_strengths(1'b1, 1'b1, 1'b0); + display_strengths(1'b1, 1'b1, 1'b1); +end + +endmodule diff --git a/ivtest/ivltests/rtranif1.v b/ivtest/ivltests/rtranif1.v new file mode 100644 index 000000000..8f011a5a8 --- /dev/null +++ b/ivtest/ivltests/rtranif1.v @@ -0,0 +1,183 @@ +module test(); + +reg a, b, en; + +wire a1, a2, a3, a4, a5, a6, a7; + +assign (supply1, supply0) a1 = a; + +rtranif1 t1(a1, a2, en); +rtranif1 t2(a2, a3, en); +rtranif1 t3(a3, a4, en); +rtranif1 t4(a4, a5, en); +rtranif1 t5(a5, a6, en); +rtranif1 t6(a6, a7, en); + +wire a11, a12, a13, a14, a15, b11, b12, b13, b14, b15; +wire a21, a22, a23, a24, a25, b21, b22, b23, b24, b25; +wire a31, a32, a33, a34, a35, b31, b32, b33, b34, b35; +wire a41, a42, a43, a44, a45, b41, b42, b43, b44, b45; +wire a51, a52, a53, a54, a55, b51, b52, b53, b54, b55; + +assign (supply1, supply0) a11 = a, b11 = b; +assign (supply1, strong0) a12 = a, b12 = b; +assign (supply1, pull0) a13 = a, b13 = b; +assign (supply1, weak0) a14 = a, b14 = b; +assign (supply1, highz0) a15 = a, b15 = b; + +assign (strong1, supply0) a21 = a, b21 = b; +assign (strong1, strong0) a22 = a, b22 = b; +assign (strong1, pull0) a23 = a, b23 = b; +assign (strong1, weak0) a24 = a, b24 = b; +assign (strong1, highz0) a25 = a, b25 = b; + +assign ( pull1, supply0) a31 = a, b31 = b; +assign ( pull1, strong0) a32 = a, b32 = b; +assign ( pull1, pull0) a33 = a, b33 = b; +assign ( pull1, weak0) a34 = a, b34 = b; +assign ( pull1, highz0) a35 = a, b35 = b; + +assign ( weak1, supply0) a41 = a, b41 = b; +assign ( weak1, strong0) a42 = a, b42 = b; +assign ( weak1, pull0) a43 = a, b43 = b; +assign ( weak1, weak0) a44 = a, b44 = b; +assign ( weak1, highz0) a45 = a, b45 = b; + +assign ( highz1, supply0) a51 = a, b51 = b; +assign ( highz1, strong0) a52 = a, b52 = b; +assign ( highz1, pull0) a53 = a, b53 = b; +assign ( highz1, weak0) a54 = a, b54 = b; + +rtranif1 t11(a11, b11, en); +rtranif1 t12(a12, b12, en); +rtranif1 t13(a13, b13, en); +rtranif1 t14(a14, b14, en); +rtranif1 t15(a15, b15, en); + +rtranif1 t21(a21, b21, en); +rtranif1 t22(a22, b22, en); +rtranif1 t23(a23, b23, en); +rtranif1 t24(a24, b24, en); +rtranif1 t25(a25, b25, en); + +rtranif1 t31(a31, b31, en); +rtranif1 t32(a32, b32, en); +rtranif1 t33(a33, b33, en); +rtranif1 t34(a34, b34, en); +rtranif1 t35(a35, b35, en); + +rtranif1 t41(a41, b41, en); +rtranif1 t42(a42, b42, en); +rtranif1 t43(a43, b43, en); +rtranif1 t44(a44, b44, en); +rtranif1 t45(a45, b45, en); + +rtranif1 t51(a51, b51, en); +rtranif1 t52(a52, b52, en); +rtranif1 t53(a53, b53, en); +rtranif1 t54(a54, b54, en); +rtranif1 t55(a55, b55, en); + +task display_strengths; + +input ta, tb, ten; + +begin + a = ta; + b = tb; + en = ten; + #1; + $display("a = %b b = %b en = %b", a, b, en); + $display("a1(%v) a2(%v) a3(%v) a4(%v) a5(%v) a6(%v) a7(%v)", a1, a2, a3, a4, a5, a6, a7); + $display("t11(%v %v) t12(%v %v) t13(%v %v) t14(%v %v) t15(%v %v)", a11, b11, a12, b12, a13, b13, a14, b14, a15, b15); + $display("t21(%v %v) t22(%v %v) t23(%v %v) t24(%v %v) t25(%v %v)", a21, b21, a22, b22, a23, b23, a24, b24, a25, b25); + $display("t31(%v %v) t32(%v %v) t33(%v %v) t34(%v %v) t35(%v %v)", a31, b31, a32, b32, a33, b33, a34, b34, a35, b35); + $display("t41(%v %v) t42(%v %v) t43(%v %v) t44(%v %v) t45(%v %v)", a41, b41, a42, b42, a43, b43, a44, b44, a45, b45); + $display("t51(%v %v) t52(%v %v) t53(%v %v) t54(%v %v) t55(%v %v)", a51, b51, a52, b52, a53, b53, a54, b54, a55, b55); +end + +endtask + +initial begin + display_strengths(1'bz, 1'bz, 1'bz); + display_strengths(1'bz, 1'bz, 1'bx); + display_strengths(1'bz, 1'bz, 1'b0); + display_strengths(1'bz, 1'bz, 1'b1); + + display_strengths(1'bx, 1'bz, 1'bz); + display_strengths(1'bx, 1'bz, 1'bx); + display_strengths(1'bx, 1'bz, 1'b0); + display_strengths(1'bx, 1'bz, 1'b1); + + display_strengths(1'b0, 1'bz, 1'bz); + display_strengths(1'b0, 1'bz, 1'bx); + display_strengths(1'b0, 1'bz, 1'b0); + display_strengths(1'b0, 1'bz, 1'b1); + + display_strengths(1'b1, 1'bz, 1'bz); + display_strengths(1'b1, 1'bz, 1'bx); + display_strengths(1'b1, 1'bz, 1'b0); + display_strengths(1'b1, 1'bz, 1'b1); + + display_strengths(1'bz, 1'bx, 1'bz); + display_strengths(1'bz, 1'bx, 1'bx); + display_strengths(1'bz, 1'bx, 1'b0); + display_strengths(1'bz, 1'bx, 1'b1); + + display_strengths(1'bx, 1'bx, 1'bz); + display_strengths(1'bx, 1'bx, 1'bx); + display_strengths(1'bx, 1'bx, 1'b0); + display_strengths(1'bx, 1'bx, 1'b1); + + display_strengths(1'b0, 1'bx, 1'bz); + display_strengths(1'b0, 1'bx, 1'bx); + display_strengths(1'b0, 1'bx, 1'b0); + display_strengths(1'b0, 1'bx, 1'b1); + + display_strengths(1'b1, 1'bx, 1'bz); + display_strengths(1'b1, 1'bx, 1'bx); + display_strengths(1'b1, 1'bx, 1'b0); + display_strengths(1'b1, 1'bx, 1'b1); + + display_strengths(1'bz, 1'b0, 1'bz); + display_strengths(1'bz, 1'b0, 1'bx); + display_strengths(1'bz, 1'b0, 1'b0); + display_strengths(1'bz, 1'b0, 1'b1); + + display_strengths(1'bx, 1'b0, 1'bz); + display_strengths(1'bx, 1'b0, 1'bx); + display_strengths(1'bx, 1'b0, 1'b0); + display_strengths(1'bx, 1'b0, 1'b1); + + display_strengths(1'b0, 1'b0, 1'bz); + display_strengths(1'b0, 1'b0, 1'bx); + display_strengths(1'b0, 1'b0, 1'b0); + display_strengths(1'b0, 1'b0, 1'b1); + + display_strengths(1'b1, 1'b0, 1'bz); + display_strengths(1'b1, 1'b0, 1'bx); + display_strengths(1'b1, 1'b0, 1'b0); + display_strengths(1'b1, 1'b0, 1'b1); + + display_strengths(1'bz, 1'b1, 1'bz); + display_strengths(1'bz, 1'b1, 1'bx); + display_strengths(1'bz, 1'b1, 1'b0); + display_strengths(1'bz, 1'b1, 1'b1); + + display_strengths(1'bx, 1'b1, 1'bz); + display_strengths(1'bx, 1'b1, 1'bx); + display_strengths(1'bx, 1'b1, 1'b0); + display_strengths(1'bx, 1'b1, 1'b1); + + display_strengths(1'b0, 1'b1, 1'bz); + display_strengths(1'b0, 1'b1, 1'bx); + display_strengths(1'b0, 1'b1, 1'b0); + display_strengths(1'b0, 1'b1, 1'b1); + + display_strengths(1'b1, 1'b1, 1'bz); + display_strengths(1'b1, 1'b1, 1'bx); + display_strengths(1'b1, 1'b1, 1'b0); + display_strengths(1'b1, 1'b1, 1'b1); +end + +endmodule diff --git a/ivtest/ivltests/sbyte_test.v b/ivtest/ivltests/sbyte_test.v new file mode 100644 index 000000000..4386ac903 --- /dev/null +++ b/ivtest/ivltests/sbyte_test.v @@ -0,0 +1,321 @@ +// Ten basic tests in here: +// 1. byte must be initialised before any initial or always block +// 2. assignments to (signed) bytes with random numbers +// 3. assignments to (signed) bytes with random values including X and Z +// 4. converting unsigned integers to signed bytes +// 5. converting signed integers to signed bytes +// 6. converting integers including X and Z states to signed bytes +// 7. trying signed sums (procedural, function, task and module) +// 8. trying signed mults (procedural, function and task) +// 9. trying relational operators +// 10. smaller signed numbers to signed bytes (sign extension) + +module ms_add (input byte signed a, b, output byte signed sc, ss); + assign sc = a + b; + always @(a, b) ss = a + b; +endmodule + +module main; + parameter N_REPS = 500; // repetition with random numbers + parameter XZ_REPS = 500; // repetition with 'x 'z values + parameter MAX = 'h7f; + parameter LEN = 8; + // variables used as golden references + reg signed [LEN-1:0] ar; // holds numbers + reg signed [LEN-1:0] ar_xz; // holds 'x and/or 'z in random positions + reg signed [LEN-1:0] ar_expected; + integer unsigned ui; + integer signed si; + reg signed [LEN/2-1:0] slice; + // types to be tested + byte signed bu; // holds numbers + byte signed bu_xz; // 'x and 'z are attempted on this + byte signed bresult; // hold results from sums and mults + byte signed mcaresult; // this is permanently wired to a module + byte signed mabresult; // this is permanently wired to a module + + integer i; + + // continuous assigments + // type LHS type RHS + // --------- --------- + // byte 4-value logic + assign bu = ar; + assign bu_xz = ar_xz; + // module instantiation + + ms_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) ); + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 8'b0 || bu_xz != 8'b0 || bresult !== 8'b0) + begin + $display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz); + $finish; + end + // driving byte type with signed random numbers from a variable + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = $random % MAX; + #1; + if (bu !== ar) + begin + $display ("FAILED - incorrect assigment to byte: %b", bu); + $finish; + end + end + # 1; + // attempting to drive variables having 'x 'z values into type unsigned bytes + // 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + ar = $random % MAX; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect assigment to byte (when 'x 'z): %b", bu); + $finish; + end + end + // converting unsigned integers to signed bytes + // truncation expected (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ui = {$random} % 2*(MAX+1); // full range as unsigned + #1; + force bu = ui; + #1; + if (bu !== ui[LEN-1:0]) + begin + $display ("FAILED - incorrect truncation from unsigned integer to byte: %b", bu); + $finish; + end + end + release bu; + // converting signed integers to signed bytes + // truncation expected (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + si = $random % MAX; + #1; + force bu = si; + #1; + if (bu !== si[LEN-1:0]) + begin + $display ("FAILED - incorrect truncation from signed integer to byte: %b mismatchs %b", bu, si[LEN-1:0]); + $finish; + end + end + release bu; + // converting signed integers having 'x 'z values into type signed bytes + // 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM) + // truncation and coercion to zero expected + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + si = $random; + ar_xz = xz_inject (si[LEN-1:0]); + si = {si[31:LEN], ar_xz}; + ar_expected = xz_expected (ar_xz); + #1; + force bu_xz = si; + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect conversion from integer (with 'x 'z) to byte: %b mismatchs %b", bu_xz, ar_expected); + $finish; + end + end + release bu_xz; + // trying signed sums + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = $random % MAX; + ar_xz = $random % MAX; + #1; + bresult = bu + bu_xz; + #1; + if ( bresult !== s_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of signed bytes: %0d mismatchs %0d", bresult, s_sum(ar, ar_xz)); + $finish; + end + // invoking byte sum function + if ( fs_sum (bu, bu_xz) !== s_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of signed bytes in function"); + $finish; + end + // invoking byte sum task + ts_sum (bu, bu_xz, bresult); + if ( bresult !== s_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of signed bytes in task: %0d mismatchs %0d", bresult, s_sum(ar, ar_xz)); + $finish; + end + // checking byte sum from module + if ( mcaresult !== s_sum(ar, ar_xz) || mabresult !== s_sum(ar, ar_xz)) + begin + $display ("FAILED - incorrect addition of signed bytes from module"); + $finish; + end + end + + // trying signed mults, forcing truncation + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = ($random % MAX) << LEN/2; + ar_xz = ($random % MAX) << (LEN/2 - 1); + #1; + bresult = bu * bu_xz; + #1; + if ( bresult !== s_mul(ar, ar_xz) ) + begin + $display ("FAILED - incorrect product of signed bytes: %0d mismatchs %0d", bresult, s_mul(ar, ar_xz)); + $finish; + end + // invoking byte mult function + if ( fs_mul (bu, bu_xz) !== s_mul(ar, ar_xz) ) + begin + $display ("FAILED - incorrect product of signed bytes in function"); + $finish; + end + // invoking byte mult task + ts_mul (bu, bu_xz, bresult); + if ( bresult !== s_mul(ar, ar_xz) ) + begin + $display ("FAILED - incorrect product of signed bytes in task: %0d mismatchs %0d", bresult, s_mul(ar, ar_xz)); + $finish; + end + end + // trying relational operators + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = $random % MAX; + ar_xz = $random % MAX; + #1; + if ( (bu < bu_xz ) !== (ar < ar_xz) ) + begin + $display ("FAILED - incorrect 'less than' on signed bytes"); + $finish; + end + if ( (bu <= bu_xz ) !== (ar <= ar_xz) ) + begin + $display ("FAILED - incorrect 'less than or equal' on signed bytes"); + $finish; + end + if ( (bu > bu_xz ) !== (ar > ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than' on signed bytes"); + $finish; + end + if ( (bu >= bu_xz ) !== (ar >= ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than or equal' than on signed bytes"); + $finish; + end + if ( (bu == bu_xz ) !== (ar == ar_xz) ) + begin + $display ("FAILED - incorrect 'equal to' on signed bytes"); + $finish; + end + if ( (bu != bu_xz ) !== (ar != ar_xz) ) + begin + $display ("FAILED - incorrect 'not equal to' on signed bytes"); + $finish; + end + end + // signed small number to signed byte + for (i = 0; i < (1<sub.gen_block[0].trigger; + #1 ->sub.gen_block[1].trigger; + #1 ->sub.gen_block[2].trigger; + #1 ->sub.gen_block[3].trigger; + #1 ->sub.my_block.trigger; + #1 ->sub.my_task.trigger; + #1 $finish(0); +end + +endmodule diff --git a/ivtest/ivltests/sdf1.sdf b/ivtest/ivltests/sdf1.sdf new file mode 100644 index 000000000..ef429dedf --- /dev/null +++ b/ivtest/ivltests/sdf1.sdf @@ -0,0 +1,27 @@ + /* C-style comments. */ + +(DELAYFILE +(SDFVERSION "OVI 2.1") +(DESIGN "xor_rtl") +(DATE "Sun Apr 1 11:57:01 2007") +(VENDOR "Icarus Test") +(PROGRAM "Hand Coded") +(VERSION "0.0") +(DIVIDER /) +(VOLTAGE 3.30:3.30:3.30) +(PROCESS "nom_pvt") +(TEMPERATURE 25.00:25.00:25.00) +(TIMESCALE 1ns) + +(CELL // C++ style comment + (CELLTYPE "XOR20") + (INSTANCE dut) + (DELAY + (ABSOLUTE + (IOPATH A Q (3.0:3.0:3.0) (3.0:3.0:3.0)) + (IOPATH B Q (3.0:3.0:3.0) (3.0:3.0:3.0)) + ) + ) +) + +) diff --git a/ivtest/ivltests/sdf1.v b/ivtest/ivltests/sdf1.v new file mode 100644 index 000000000..ba6954706 --- /dev/null +++ b/ivtest/ivltests/sdf1.v @@ -0,0 +1,37 @@ +`celldefine +//`timescale 1ns / 1ps + +// Description : 2 input XOR + +module XOR20 (input A, input B, output Q); + + xor (Q,B,A); + + specify + (A => Q) = (1,1); + (B => Q) = (1,1); + endspecify + +endmodule + +`endcelldefine + +module tb; + + reg a, b; + wire q; + XOR20 dut(.A(a), .B(b), .Q(q)); + + initial begin + $monitor($time,, "A=%b, B=%b, Q=%b", a, b, q); + $sdf_annotate("ivltests/sdf1.sdf"); + + #10 ; + a = 1; + b = 1; + #10 ; + b = 0; + #10 $finish(0); + end + +endmodule // tb diff --git a/ivtest/ivltests/sdf2.sdf b/ivtest/ivltests/sdf2.sdf new file mode 100644 index 000000000..c87e56b32 --- /dev/null +++ b/ivtest/ivltests/sdf2.sdf @@ -0,0 +1,27 @@ + /* C-style comments. */ + +(DELAYFILE +(SDFVERSION "OVI 2.1") +(DESIGN "xor_rtl") +(DATE "Sun Apr 1 11:57:01 2007") +(VENDOR "Icarus Test") +(PROGRAM "Hand Coded") +(VERSION "0.0") +(DIVIDER /) +(VOLTAGE 3.30:3.30:3.30) +(PROCESS "nom_pvt") +(TEMPERATURE 25.00:25.00:25.00) +(TIMESCALE 1ns) + +(CELL // C++ style comment + (CELLTYPE "XOR20") + (INSTANCE dut/U1) + (DELAY + (ABSOLUTE + (IOPATH A Q (3.0:3.0:3.0) (3.0:3.0:3.0)) + (IOPATH B Q (3.0:3.0:3.0) (3.0:3.0:3.0)) + ) + ) +) + +) diff --git a/ivtest/ivltests/sdf2.v b/ivtest/ivltests/sdf2.v new file mode 100644 index 000000000..10aa21e35 --- /dev/null +++ b/ivtest/ivltests/sdf2.v @@ -0,0 +1,43 @@ +`celldefine +//`timescale 1ns / 1ps + +// Description : 2 input XOR + +module XOR20 (input A, input B, output Q); + + xor (Q,B,A); + + specify + (A => Q) = (1,1); + (B => Q) = (1,1); + endspecify + +endmodule + +`endcelldefine + +module plug(input A, input B, output Q); + + XOR20 U1(.A(A), .B(B), .Q(Q)); + +endmodule // plug + +module tb; + + reg a, b; + wire q; + plug dut(.A(a), .B(b), .Q(q)); + + initial begin + $monitor($time,, "A=%b, B=%b, Q=%b", a, b, q); + $sdf_annotate("ivltests/sdf2.sdf"); + + #10 ; + a = 1; + b = 1; + #10 ; + b = 0; + #10 $finish(0); + end + +endmodule // tb diff --git a/ivtest/ivltests/sdf3.sdf b/ivtest/ivltests/sdf3.sdf new file mode 100644 index 000000000..f62de8991 --- /dev/null +++ b/ivtest/ivltests/sdf3.sdf @@ -0,0 +1,27 @@ + /* C-style comments. */ + +(DELAYFILE +(SDFVERSION "OVI 2.1") +(DESIGN "xor_rtl") +(DATE "Sun Apr 1 11:57:01 2007") +(VENDOR "Icarus Test") +(PROGRAM "Hand Coded") +(VERSION "0.0") +(DIVIDER /) +(VOLTAGE 3.30:3.30:3.30) +(PROCESS "nom_pvt") +(TEMPERATURE 25.00:25.00:25.00) +(TIMESCALE 1ns) + +(CELL // C++ style comment + (CELLTYPE "XOR20") + (INSTANCE) + (DELAY + (ABSOLUTE + (IOPATH A Q (3.0:3.0:3.0) (3.0:3.0:3.0)) + (IOPATH B Q (3.0:3.0:3.0) (3.0:3.0:3.0)) + ) + ) +) + +) diff --git a/ivtest/ivltests/sdf3.v b/ivtest/ivltests/sdf3.v new file mode 100644 index 000000000..aa9849ce0 --- /dev/null +++ b/ivtest/ivltests/sdf3.v @@ -0,0 +1,38 @@ +`celldefine +//`timescale 1ns / 1ps + +// Description : 2 input XOR + +module XOR20 (input A, input B, output Q); + + xor (Q,B,A); + + initial $sdf_annotate("ivltests/sdf3.sdf"); + + specify + (A => Q) = (1,1); + (B => Q) = (1,1); + endspecify + +endmodule + +`endcelldefine + +module tb; + + reg a, b; + wire q; + XOR20 dut(.A(a), .B(b), .Q(q)); + + initial begin + $monitor($time,, "A=%b, B=%b, Q=%b", a, b, q); + + #10 ; + a = 1; + b = 1; + #10 ; + b = 0; + #10 $finish(0); + end + +endmodule // tb diff --git a/ivtest/ivltests/sdf4.sdf b/ivtest/ivltests/sdf4.sdf new file mode 100644 index 000000000..f62de8991 --- /dev/null +++ b/ivtest/ivltests/sdf4.sdf @@ -0,0 +1,27 @@ + /* C-style comments. */ + +(DELAYFILE +(SDFVERSION "OVI 2.1") +(DESIGN "xor_rtl") +(DATE "Sun Apr 1 11:57:01 2007") +(VENDOR "Icarus Test") +(PROGRAM "Hand Coded") +(VERSION "0.0") +(DIVIDER /) +(VOLTAGE 3.30:3.30:3.30) +(PROCESS "nom_pvt") +(TEMPERATURE 25.00:25.00:25.00) +(TIMESCALE 1ns) + +(CELL // C++ style comment + (CELLTYPE "XOR20") + (INSTANCE) + (DELAY + (ABSOLUTE + (IOPATH A Q (3.0:3.0:3.0) (3.0:3.0:3.0)) + (IOPATH B Q (3.0:3.0:3.0) (3.0:3.0:3.0)) + ) + ) +) + +) diff --git a/ivtest/ivltests/sdf4.v b/ivtest/ivltests/sdf4.v new file mode 100644 index 000000000..f22c83a7b --- /dev/null +++ b/ivtest/ivltests/sdf4.v @@ -0,0 +1,37 @@ +`celldefine +//`timescale 1ns / 1ps + +// Description : 2 input XOR + +module XOR20 (input A, input B, output Q); + + xor (Q,B,A); + + specify + (A => Q) = (1,1); + (B => Q) = (1,1); + endspecify + +endmodule + +`endcelldefine + +module tb; + + reg a, b; + wire q; + XOR20 dut(.A(a), .B(b), .Q(q)); + + initial begin + $monitor($time,, "A=%b, B=%b, Q=%b", a, b, q); + $sdf_annotate("ivltests/sdf4.sdf", dut); + + #10 ; + a = 1; + b = 1; + #10 ; + b = 0; + #10 $finish(0); + end + +endmodule // tb diff --git a/ivtest/ivltests/sdf5.sdf b/ivtest/ivltests/sdf5.sdf new file mode 100644 index 000000000..50a8d475a --- /dev/null +++ b/ivtest/ivltests/sdf5.sdf @@ -0,0 +1,22 @@ + /* C-style comments. */ + +(DELAYFILE + (SDFVERSION "OVI 2.1") + (DESIGN "sdf5") + (DATE "Sun Apr 1 11:57:01 2007") + (VENDOR "Icarus Test") + (PROGRAM "Hand Coded") + (VERSION "0.0") + (DIVIDER /) + (VOLTAGE 3.30:3.30:3.30) + (PROCESS "nom_pvt") + (TEMPERATURE 25.00:25.00:25.00) + (TIMESCALE 1ns) + + (CELL // C++ style comment + (CELLTYPE "DFF") + (INSTANCE dut) + (DELAY + (ABSOLUTE + (IOPATH (posedge C) Q (3.0:3.0:3.0) (3.0:3.0:3.0)) ) ) ) + ) diff --git a/ivtest/ivltests/sdf5.v b/ivtest/ivltests/sdf5.v new file mode 100644 index 000000000..c4dfb32d0 --- /dev/null +++ b/ivtest/ivltests/sdf5.v @@ -0,0 +1,34 @@ +module DFF (input D, input C, output reg Q); + + always @(posedge C) + Q <= D; + + specify + (posedge C => (Q +: D)) = (1,1); + endspecify + +endmodule + +`endcelldefine + +module tb; + + reg clk, d; + wire q; + DFF dut(.D(d), .C(clk), .Q(q)); + + initial begin + clk = 0; + d = 0; + $monitor($time,, "D=%b, Q=%b, clk=%b", d, q, clk); + $sdf_annotate("ivltests/sdf5.sdf"); + + #10 clk = 1; + #10 clk = 0; + d = 1; + #10 clk = 1; + #10 clk = 0; + #10 $finish(0); + end + +endmodule // tb diff --git a/ivtest/ivltests/sdf6.sdf b/ivtest/ivltests/sdf6.sdf new file mode 100644 index 000000000..b60e86eea --- /dev/null +++ b/ivtest/ivltests/sdf6.sdf @@ -0,0 +1,25 @@ +(DELAYFILE + (SDFVERSION "OVI 2.1") + (DESIGN "dff") + (DATE "Today") + (VENDOR "Icarus") + (PROGRAM "Cary") + (VERSION "1.0") + (DIVIDER /) + (VOLTAGE 2.7:2.7:2.7) + (PROCESS "nom") + (TEMPERATURE 27.0:27.0:27.0) + (TIMESCALE 1ns) + + (CELL + (CELLTYPE "dff") + (INSTANCE dut) + (DELAY + (ABSOLUTE + (IOPATH cdn q (2.0:2.0:2.0) (3.0:3.0:3.0)) + (IOPATH sdn q (4.0:4.0:4.0) (5.0:5.0:5.0)) + (IOPATH (posedge cp) q (6.0:6.0:6.0) (7.0:7.0:7.0)) + ) + ) + ) +) diff --git a/ivtest/ivltests/sdf6.v b/ivtest/ivltests/sdf6.v new file mode 100644 index 000000000..9d50a8168 --- /dev/null +++ b/ivtest/ivltests/sdf6.v @@ -0,0 +1,41 @@ +module dff (q, d, cp, sdn, cdn); + output q; + input cp; + input d; + input sdn; + input cdn; + + reg q; + + always @(posedge cp or negedge sdn or negedge cdn) begin + if (~sdn) q <= 1; + else if (~cdn) q <= 0; + else q <= d; + end + + specify + if (sdn && cdn) (posedge cp => (q +: d)) = (1, 1); + (negedge cdn => (q +: 1'b0)) = (1, 1); + (negedge sdn => (q -: 1'b1)) = (1, 1); + endspecify +endmodule + +module test; + reg d, clk, set, clr; + + dff dut(q, d, clk, ~set, ~clr); + + initial begin + d=0; clk=0; set=0; clr=0; + $monitor($time,, "d=%b, clk=%b, set=%b, clr=%b, q=%b", + d, clk, set, clr, q); + $sdf_annotate("ivltests/sdf6.sdf"); + #10 d = 1; + #10 set = 1; + #10 set = 0; + #10 clr = 1; + #10 clr = 0; + #10 clk = 1; + #10 d = 0; + end +endmodule diff --git a/ivtest/ivltests/sdf7.sdf b/ivtest/ivltests/sdf7.sdf new file mode 100644 index 000000000..7d615cc28 --- /dev/null +++ b/ivtest/ivltests/sdf7.sdf @@ -0,0 +1,27 @@ + /* C-style comments. */ + +(DELAYFILE +(SDFVERSION "OVI 2.1") +(DESIGN "xor_rtl") +(DATE "Mon Feb 9 17:54:11 2009") +(VENDOR "Icarus Test") +(PROGRAM "Hand Coded") +(VERSION "0.0") +(DIVIDER /) +(VOLTAGE 3.30:3.30:3.30) +(PROCESS "nom_pvt") +(TEMPERATURE 25.00:25.00:25.00) +(TIMESCALE 1ns) + +(CELL // C++ style comment + (CELLTYPE "XOR20") + (INSTANCE dut) + (DELAY + (ABSOLUTE + (IOPATH A Q () (3.0:3.0:3.0)) + (IOPATH B Q () (3.0:3.0:3.0)) + ) + ) +) + +) diff --git a/ivtest/ivltests/sdf7.v b/ivtest/ivltests/sdf7.v new file mode 100644 index 000000000..11ad70ff5 --- /dev/null +++ b/ivtest/ivltests/sdf7.v @@ -0,0 +1,41 @@ +`celldefine +//`timescale 1ns / 1ps + +// Description : 2 input XOR + +module XOR20 (input A, input B, output Q); + + xor (Q,B,A); + + specify + (A => Q) = (1,1); + (B => Q) = (1,1); + endspecify + +endmodule + +`endcelldefine + +module tb; + + reg a, b; + wire q; + XOR20 dut(.A(a), .B(b), .Q(q)); + + initial begin + $monitor($time,, "A=%b, B=%b, Q=%b", a, b, q); + $sdf_annotate("ivltests/sdf7.sdf"); + + #10 ; + a = 1; + b = 1; + #10 ; + b = 0; + #10 ; + b = 1; + #10 ; + a = 0; + #10 $finish(0); + end + +endmodule // tb diff --git a/ivtest/ivltests/sdf8.sdf b/ivtest/ivltests/sdf8.sdf new file mode 100644 index 000000000..8fe6bdef8 --- /dev/null +++ b/ivtest/ivltests/sdf8.sdf @@ -0,0 +1,27 @@ +(DELAYFILE + (SDFVERSION "OVI 2.1") + (DESIGN "xor_rtl") + (DATE "Tue Mar 30 13:04:55 PDT 2010") + (VENDOR "Icarus Test") + (PROGRAM "Hand Coded") + (VERSION "0.0") + (DIVIDER /) + (VOLTAGE 3.30) + (PROCESS "nom_pvt") + (TEMPERATURE 25.00) + (TIMESCALE 1ns) + (CELL + (CELLTYPE "XOR20") + (INSTANCE dut) + (DELAY + (ABSOLUTE + (IOPATH A Q (2.0) (3.0)) + (IOPATH B Q () ()) + ) + ) + ) + (CELL + (CELLTYPE "TIE_HIGH") + (INSTANCE src) + ) +) diff --git a/ivtest/ivltests/sdf8.v b/ivtest/ivltests/sdf8.v new file mode 100644 index 000000000..7ae5d5d48 --- /dev/null +++ b/ivtest/ivltests/sdf8.v @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps + +`celldefine +// Description : 2 input XOR +module XOR20 (input A, input B, output Q); + + xor (Q,B,A); + + specify + (A => Q) = (1,1); + (B => Q) = (1,1); + endspecify + +endmodule +`endcelldefine + +`celldefine +module TIE_HIGH (output Q); + buf(Q, 1'b1); +endmodule +`endcelldefine + +module tb; + + reg a; + wire b, q; + XOR20 dut(.A(a), .B(b), .Q(q)); + TIE_HIGH src(.Q(b)); + + initial begin + $monitor($time,, "A=%b, B=%b, Q=%b", a, b, q); + $sdf_annotate("ivltests/sdf8.sdf"); + + #10 ; + a = 1; + #10 ; + a = 0; + #10 $finish(0); + end + +endmodule // tb diff --git a/ivtest/ivltests/sdf_del.sdf b/ivtest/ivltests/sdf_del.sdf new file mode 100644 index 000000000..72e599dfd --- /dev/null +++ b/ivtest/ivltests/sdf_del.sdf @@ -0,0 +1,18 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "test") + (VOLTAGE 3.70:3.30:3.00) + (PROCESS "fast:typ:slow") + (TEMPERATURE 25.00:55.00:100.00) + (TIMESCALE 1ns) + + (CELL + (CELLTYPE "my_buf") + (INSTANCE dut) + (DELAY + (ABSOLUTE + (IOPATH a z (1.0:2.0:3.0) (2.0:3.0:4.0)) + ) + ) + ) +) diff --git a/ivtest/ivltests/sdf_del_max.v b/ivtest/ivltests/sdf_del_max.v new file mode 100644 index 000000000..79c03ef5c --- /dev/null +++ b/ivtest/ivltests/sdf_del_max.v @@ -0,0 +1,39 @@ +`timescale 1ns/10ps + +module top; + reg a, pass; + wire z; + time edge_time; + + always @(z) begin + if ((z === 0) && (($time - edge_time) != 4)) begin + $display("Falling took %d, expected 4", $time - edge_time); + pass = 1'b0; + end + if ((z === 1) && (($time - edge_time) != 3)) begin + $display("Rising took %d, expected 3", $time - edge_time); + pass = 1'b0; + end + end + + initial begin + pass = 1'b1; + $sdf_annotate("ivltests/sdf_del.sdf", top); + #10; + edge_time = $time; + a = 1'b0; + #10; + edge_time = $time; + a = 1'b1; + #10 if (pass) $display("PASSED"); + end + + my_buf dut(z, a); +endmodule + +module my_buf (output z, input a); + buf (z, a); + specify + (a => z) = (0, 0); + endspecify +endmodule diff --git a/ivtest/ivltests/sdf_del_min.v b/ivtest/ivltests/sdf_del_min.v new file mode 100644 index 000000000..6fe76ac2a --- /dev/null +++ b/ivtest/ivltests/sdf_del_min.v @@ -0,0 +1,39 @@ +`timescale 1ns/10ps + +module top; + reg a, pass; + wire z; + time edge_time; + + always @(z) begin + if ((z === 0) && (($time - edge_time) != 2)) begin + $display("Falling took %d, expected 2", $time - edge_time); + pass = 1'b0; + end + if ((z === 1) && (($time - edge_time) != 1)) begin + $display("Rising took %d, expected 1", $time - edge_time); + pass = 1'b0; + end + end + + initial begin + pass = 1'b1; + $sdf_annotate("ivltests/sdf_del.sdf", top); + #10; + edge_time = $time; + a = 1'b0; + #10; + edge_time = $time; + a = 1'b1; + #10 if (pass) $display("PASSED"); + end + + my_buf dut(z, a); +endmodule + +module my_buf (output z, input a); + buf (z, a); + specify + (a => z) = (0, 0); + endspecify +endmodule diff --git a/ivtest/ivltests/sdf_del_typ.v b/ivtest/ivltests/sdf_del_typ.v new file mode 100644 index 000000000..f52a1b60b --- /dev/null +++ b/ivtest/ivltests/sdf_del_typ.v @@ -0,0 +1,39 @@ +`timescale 1ns/10ps + +module top; + reg a, pass; + wire z; + time edge_time; + + always @(z) begin + if ((z === 0) && (($time - edge_time) != 3)) begin + $display("Falling took %d, expected 3", $time - edge_time); + pass = 1'b0; + end + if ((z === 1) && (($time - edge_time) != 2)) begin + $display("Rising took %d, expected 2", $time - edge_time); + pass = 1'b0; + end + end + + initial begin + pass = 1'b1; + $sdf_annotate("ivltests/sdf_del.sdf", top); + #10; + edge_time = $time; + a = 1'b0; + #10; + edge_time = $time; + a = 1'b1; + #10 if (pass) $display("PASSED"); + end + + my_buf dut(z, a); +endmodule + +module my_buf (output z, input a); + buf (z, a); + specify + (a => z) = (0, 0); + endspecify +endmodule diff --git a/ivtest/ivltests/sdf_esc_id.sdf b/ivtest/ivltests/sdf_esc_id.sdf new file mode 100644 index 000000000..6ed073665 --- /dev/null +++ b/ivtest/ivltests/sdf_esc_id.sdf @@ -0,0 +1,27 @@ + /* C-style comments. */ + +(DELAYFILE +(SDFVERSION "OVI 2.1") +(DESIGN "xor_rtl") +(DATE "Sun Apr 1 11:57:01 2007") +(VENDOR "Icarus Test") +(PROGRAM "Hand Coded") +(VERSION "0.0") +(DIVIDER /) +(VOLTAGE 3.30:3.30:3.30) +(PROCESS "nom_pvt") +(TEMPERATURE 25.00:25.00:25.00) +(TIMESCALE 1ns) + +(CELL + (CELLTYPE "XOR20") + (INSTANCE \&dut\[0\]) + (DELAY + (ABSOLUTE + (IOPATH A Q (3.0:3.0:3.0) (3.0:3.0:3.0)) + (IOPATH B Q (3.0:3.0:3.0) (3.0:3.0:3.0)) + ) + ) +) + +) diff --git a/ivtest/ivltests/sdf_esc_id.v b/ivtest/ivltests/sdf_esc_id.v new file mode 100644 index 000000000..2c7737f18 --- /dev/null +++ b/ivtest/ivltests/sdf_esc_id.v @@ -0,0 +1,38 @@ +`timescale 1ns / 1ps + +`celldefine + +// Description : 2 input XOR + +module XOR20 (input A, input B, output Q); + + xor (Q,B,A); + + specify + (A => Q) = (1,1); + (B => Q) = (1,1); + endspecify + +endmodule + +`endcelldefine + +module tb; + + reg a, b; + wire q; + XOR20 \&dut[0] (.A(a), .B(b), .Q(q)); + + initial begin + $monitor($time,, "A=%b, B=%b, Q=%b", a, b, q); + $sdf_annotate("ivltests/sdf_esc_id.sdf"); + + #10 ; + a = 1; + b = 1; + #10 ; + b = 0; + #10 $finish(0); + end + +endmodule // tb diff --git a/ivtest/ivltests/sdw_always1.v b/ivtest/ivltests/sdw_always1.v new file mode 100644 index 000000000..0c2aafea0 --- /dev/null +++ b/ivtest/ivltests/sdw_always1.v @@ -0,0 +1,78 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate always block instantiation. +// +// D: Test validate others versions of always block +// D: including posedge, negedge. +// +// + +module main (); +reg working; +reg clock ; + +initial // Used to generate timing of events + begin + working = 0; + clock = 0; + #4 ; + working = 0; + #1 ; + clock = 1; // 1ns between setting working and clock edge. + #4 ; + working = 0; + #1 ; + clock = 0; // 1ns between setting working and clock edge. + #5 ; + end + +always #2 + working = 1 ; + +initial // This is the validation block + begin + # 3; // Check #2 always at 3ns + if(!working) + begin + $display("FAILED - delayed always\n"); + $finish ; + end + # 3; // Check posedge at 6 ns + if(!working) + begin + $display("FAILED - posedge always\n"); + $finish ; + end + # 7; // Check negedge at 11ns + if(!working) + begin + $display("FAILED - posedge always\n"); + $finish ; + end + $display("PASSED\n"); + $finish; + end + +always @ (posedge clock) + working = 1; + +always @ (negedge clock) + working = 1; + +endmodule diff --git a/ivtest/ivltests/sdw_always2.v b/ivtest/ivltests/sdw_always2.v new file mode 100644 index 000000000..bc965f4d2 --- /dev/null +++ b/ivtest/ivltests/sdw_always2.v @@ -0,0 +1,115 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - Validate always with OR, posedge constructs. +// +// D: New test used to validate always @(value), and +// D: always @(val1 or val2), and always @(posedge val1 or negedge val2) +// D: statements. +// +// + +module main (); +reg working; +reg val1, val2, val3, val4, val5; +reg clock ; +reg test_var; + +initial // Used to generate timing of events + begin + val2 = 0; + val3 = 0; + val4 = 1; + # 1; + test_var = 1; + # 1; + val1 = 1; // Cause a change in val1 -> test_var to 0. + # 2 ; // 4ns + test_var = 1; + # 1 ; // 5ns + val2 = 1; // Cause posedge on val2 -> test_var to 0 + # 2; // 7ns + test_var = 1; + # 1; // 8ns + val4 = 0; // Cause negedge on val4 -> test_var to 0 + # 2; // 10ns + test_var = 1; + # 1; // 11 ns + val3 = 1; // Cause val3 change for always @(a or b) + # 2; // 13 ns + test_var = 1; + # 1; // 14 ns + val5 = 1; // Cause val5 cahnge for always @(a or b) + # 2; // 16 ns + end + +always @(val1) // Val1 changing clears test_var + test_var = 0; + +always @(posedge val2 or negedge val4) + test_var = 0; + +always @(val3 or val5) + test_var = 0; + + +initial // This is the validation block + begin + # 3; // 3 ns Check always @(val) + if(test_var) + begin + $display("FAILED - always @(val) wrong \n"); + $finish ; + end + # 3; // 6 ns Check posedge of always @(posedge val or negedge) + if(test_var) + begin + $display("FAILED - posedge of always @(posedge or negedge) wrong \n"); + $finish ; + end + # 3; // 9 ns Check negedge of always @(posedge val or negedge) + if(test_var) + begin + $display("FAILED - negedge of always @(posedge or negedge) wrong \n"); + $finish ; + end + # 3; // 12 ns Check a of always @(a or b) + if(test_var) + begin + $display("FAILED - a of always @(a or b) wrong \n"); + $finish ; + end + # 3; // 15 ns Check b of always @(a or b) + if(test_var) + begin + $display("FAILED - b of always @(a or b) wrong \n"); + $finish ; + end + + $display("PASSED\n"); + $finish; + end + +always @ (posedge clock) + working = 1; + +always @ (negedge clock) + working = 1; + +endmodule diff --git a/ivtest/ivltests/sdw_always3.v b/ivtest/ivltests/sdw_always3.v new file mode 100644 index 000000000..f5965660e --- /dev/null +++ b/ivtest/ivltests/sdw_always3.v @@ -0,0 +1,121 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - always block with @(value) and (posedge OR negedge) +// +// D: New test used to validate always @(value), and +// D: always @(val1 or val2), and always @(posedge val1 or negedge val2) +// D: statements. +// +// + +module main (); +reg working; +reg reset; +reg clock ; +reg test_var; + +initial // Used to generate timing of events + begin + clock = 0; + reset = 0; + + // Nothing sent yet... + + #5 ; + $display("time=%d, c=%b, r=%b, reg=%b",$time,clock,reset,test_var); + reset = 1; // 5 ns + + #5 ; + $display("time=%d, c=%b, r=%b, reg=%b",$time,clock,reset,test_var); + reset = 0; // 10ns + + #5 ; + $display("time=%d, c=%b, r=%b, reg=%b",$time,clock,reset,test_var); + clock = 1; // 15 ns + + #5 ; + $display("time=%d, c=%b, r=%b, reg=%b",$time,clock,reset,test_var); + clock = 0; // 20 ns + + #5 ; // 25 ns + $display("time=%d, c=%b, r=%b, reg=%b",$time,clock,reset,test_var); + end + +// +// This is the statement being verified... +// +// This LOOKS like a race between the posedge and the reset value +// but is a standard method for reseting f/f's. +// + +always @(posedge clock or posedge reset) + if(reset) + test_var = 0; + else + test_var = ~test_var; + +initial // This is the validation block + begin + # 3; // 3 ns Check always @(val) + if(test_var != 1'bx) + begin + $display("FAILED - initial condition of reg variable not x\n"); + $finish ; + end + # 5; // 8 ns Check posedge of always @(posedge val or negedge) + if(test_var == 1'bx) + begin + $display("FAILED - Reset didn't reset var \n"); + $finish ; + end + if(test_var == 1'b1) + begin + $display("FAILED - Reset set it to 1?? \n"); + $finish ; + end + + # 5; // 12 ns + if(test_var == 1'bx) + begin + $display("FAILED - Reset didn't reset var \n"); + $finish ; + end + if(test_var == 1'b1) + begin + $display("FAILED - Reset set it to 1?? \n"); + $finish ; + end + # 5; // 17 ns - have received the clock by now + if(test_var == 1'bx) + begin + $display("FAILED - The clock caused an x??\n"); + $finish ; + end + if(test_var == 1'b0) + begin + $display("FAILED - The clock didn't have any effect?? \n"); + $finish ; + end + # 30; + + $display("PASSED\n"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/sdw_array.v b/ivtest/ivltests/sdw_array.v new file mode 100644 index 000000000..dfbd8846a --- /dev/null +++ b/ivtest/ivltests/sdw_array.v @@ -0,0 +1,109 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - Memory array instantiation, validation +// +// D: First do the declaration, and assignment of bit wide arrays +// D: and 16 bit wide 4 deep arrays. Then assign values and validate +// D: the assignment worked. + +module main(); + +reg mem_1 [1:0]; // Define 2 locations, each 1 bit in depth +reg [15:0] mem_2 [3:0]; // Define a 16 bit wide array - 4 in depth +reg [15:0] work16; +reg work1; + +initial // Excitation block + begin + mem_1 [0] = 0; // Do the initial assignment of values + mem_1 [1] = 1; + mem_2 [0] = 16'h0; + mem_2 [1] = 16'h1; + mem_2 [2] = 16'h2; + mem_2 [3] = 16'h3; + + #5 ; + mem_1 [1] = mem_1 [0] ; // use the mem array on the rhs + mem_2 [3] = mem_2 [0] ; + + #5; + + end + +initial // Validation block + begin + #1 ; + // Validate initialization + work1 = mem_1[0]; + if(work1 != 0) + begin + $display("FAILED - mem_1 [0] init failed\n"); + $finish ; + end + work1 = mem_1[1]; + if(work1 != 1) + begin + $display("FAILED - mem_1 [1] init failed\n"); + $finish ; + end + work16 = mem_2 [0]; + if(work16 != 16'h0) + begin + $display("FAILED - mem_2 [0] init failed\n"); + $finish ; + end + work16 = mem_2 [1]; + if(work16 != 16'h1) + begin + $display("FAILED - mem_2 [1] init failed\n"); + $finish ; + end + work16 = mem_2 [2]; + if(work16 != 16'h2) + begin + $display("FAILED - mem_2 [2] init failed\n"); + $finish ; + end + work16 = mem_2 [3]; + if(work16 != 16'h3) + begin + $display("FAILED - mem_2 [3] init failed\n"); + $finish ; + end + + #5 ; + work1 = mem_1[1]; + if(work1 != 0) + begin + $display("FAILED - mem_1 [1] rhs assignment \n"); + $finish ; + end + work16 = mem_2 [3]; + if(work16 != 16'h0) + begin + $display("FAILED - mem_2 [3] rhs assignment\n"); + $finish ; + end + + $display("PASSED\n"); + $finish ; + end + +endmodule diff --git a/ivtest/ivltests/sdw_assign.v b/ivtest/ivltests/sdw_assign.v new file mode 100644 index 000000000..645577903 --- /dev/null +++ b/ivtest/ivltests/sdw_assign.v @@ -0,0 +1,72 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - Validation of assign construct +// +// D: Create a 32 bit vector and assign succesive values to +// D: the Right hand side expression. Verify the result is +// D: correct. +// + +module main (); + +wire [31:0] result; +reg [31:0] a,b ; + +assign result = a | b; + +initial // Excitation block + begin + a = 0; + b = 0; + # 5; + a = 32'haaaaaaaa ; + # 5; + b = 32'h55555555 ; + # 5 ; + end + +initial // Validation block + begin + # 1; + if(result != 32'h0) + begin + $display("FAILED - result not initialized\n"); + $finish ; + end + + # 5; + if(result != 32'haaaaaaaa) + begin + $display("FAILED - result not updated\n"); + $finish ; + end + + # 5; + if(result != 32'hffffffff) + begin + $display("FAILED - result not updated\n"); + $finish ; + end + + $display("PASSED\n"); + $finish ; + end + +endmodule diff --git a/ivtest/ivltests/sdw_dsbl.v b/ivtest/ivltests/sdw_dsbl.v new file mode 100644 index 000000000..44080fe13 --- /dev/null +++ b/ivtest/ivltests/sdw_dsbl.v @@ -0,0 +1,57 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - validate named blocks/disable stmt +// +// D: This code verifies both named blocks and the disable statement +// D: It is intended to be self checking. +// + +module main (); + +reg working; +reg timer; + +initial + begin:my_block + working = 1; + #5; + working = 1; + #5; + working = 1; + #5; + working = 0; + #5; + end + +initial + begin + #15; + disable my_block; + end + +initial + begin + #20; + if(!working) + $display("FAILED"); + else + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/sdw_force.v b/ivtest/ivltests/sdw_force.v new file mode 100644 index 000000000..c9dc76373 --- /dev/null +++ b/ivtest/ivltests/sdw_force.v @@ -0,0 +1,60 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Force stmt validation +// +// D: This code verifies the force statement +// D: It is intended to be self checking. +// + +module main (); + +reg working; +reg timer; + +initial +begin + timer = 1; + # 5; + timer = 0; + # 5 ; + timer = 1; + # 5 ; +end + + +initial + begin + working = 1; + #2 ; // Validate that force occurs + force timer = 0; + if( timer == 1) working = 0; + #10 ; // Validate that force stays in effect + if( timer == 1) working = 0; + end + +initial + begin + #20; + if(!working) + $display("FAILED\n"); + else + $display("PASSED\n"); + end + +endmodule diff --git a/ivtest/ivltests/sdw_function1.v b/ivtest/ivltests/sdw_function1.v new file mode 100644 index 000000000..b225ab5d3 --- /dev/null +++ b/ivtest/ivltests/sdw_function1.v @@ -0,0 +1,50 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Initial Function testing +// +// D: Instantiate a simple module that takes 1 input and doubles it. +// + +module main (); + +reg [3:0] global_var; +reg [3:0] result; + +function [3:0] my_func ; +input [3:0] a; +begin + my_func = a + a; +end +endfunction + +initial + begin + global_var = 2; + result = my_func(global_var); + + if(result !== 4) + begin + $display("FAILED - function didn't function!\n"); + $finish ; + end + + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/sdw_function2.v b/ivtest/ivltests/sdw_function2.v new file mode 100644 index 000000000..6d8147c17 --- /dev/null +++ b/ivtest/ivltests/sdw_function2.v @@ -0,0 +1,58 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Function scope handling +// +// D: Validate scope handling of variables +// + +module main (); + +reg [3:0] global_reg; +reg [3:0] result; + +function [3:0] my_func ; +input [3:0] a; +reg [3:0] global_reg; +begin + global_reg = a + a; + my_func = a + a; +end +endfunction + +initial + begin + global_reg = 2; + result = my_func(global_reg); + + if(result != 4) + begin + $display("FAILED - function didn't function!\n"); + $finish ; + end + + if(global_reg != 2) + begin + $display("FAILED - function scope problem!\n"); + $finish ; + end + + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/sdw_function3.v b/ivtest/ivltests/sdw_function3.v new file mode 100644 index 000000000..028073d0e --- /dev/null +++ b/ivtest/ivltests/sdw_function3.v @@ -0,0 +1,60 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: function calling function validated +// +// D: Instantiate a 2 functions, with the 2nd calling +// D: the first. Validate the results are correct. +// + +module main (); + +reg [3:0] global_reg; +reg [3:0] result; + +// Instantiate the function to be called +function [3:0] my_func_2; +input [3:0] a; +begin + my_func_2 = a; +end +endfunction + +// This is the calling function +function [3:0] my_func_1 ; +input [3:0] a; +begin + my_func_1 = my_func_2(a) + my_func_2(a); // So call it twice! +end +endfunction + +initial + begin + global_reg = 2; + result = my_func_1(global_reg); + + if(result != 4) + begin + $display("FAILED - function didn't function!\n"); + $finish ; + end + + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/sdw_function4.v b/ivtest/ivltests/sdw_function4.v new file mode 100644 index 000000000..ef328e38e --- /dev/null +++ b/ivtest/ivltests/sdw_function4.v @@ -0,0 +1,53 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Function with if clause +// +// D: +// + +module main (); + +reg [3:0] global_var; +reg [3:0] result; +// Interesting because 2 * 0 is 0 ;-) +function [3:0] my_func ; +input [3:0] a; +begin + if(a == 4'b0) + my_func = 4'b0; + else + my_func = a + a; +end +endfunction + +initial + begin + global_var = 2; + result = my_func(global_var); + + if(result != 4) + begin + $display("FAILED - function didn't function!\n"); + $finish ; + end + + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/sdw_function5.v b/ivtest/ivltests/sdw_function5.v new file mode 100644 index 000000000..36faf1d5d --- /dev/null +++ b/ivtest/ivltests/sdw_function5.v @@ -0,0 +1,53 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Function with case +// +// D: +// + +module main (); + +reg [3:0] global_var; +reg [3:0] result; +// Interesting because 2 * 0 is 0 ;-) +function [3:0] my_func ; +input [3:0] a; +begin + case(a) + 4'b000: my_func = 4'b0; + default: my_func = a + a; + endcase +end +endfunction + +initial + begin + global_var = 2; + result = my_func(global_var); + + if(result != 4) + begin + $display("FAILED - function didn't function!\n"); + $finish ; + end + + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/sdw_instmod1.v b/ivtest/ivltests/sdw_instmod1.v new file mode 100644 index 000000000..6c099a55c --- /dev/null +++ b/ivtest/ivltests/sdw_instmod1.v @@ -0,0 +1,115 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW: Instantiation of Modules: +// +// D: Instantiate two versions of a module containing a single +// D: resetable f/f. Reset both - then feed 1 module with a clock +// D: and validate that the output toggles. Feed the 2nd module +// D: with a clock and validate that the 2nd output toggles. +// +// + +module test_mod (reset,clka,out); +input reset; +input clka; +output out; + +reg out; + +always @(posedge clka or posedge reset) + if(reset) + out = 0; + else + begin + out = ~out; + $display("saw a clk at %d, out is %b\n",$time,out); + end + +endmodule + +module main(); + +reg reset,clk_0,clk_1; +wire out_0,out_1; + +test_mod module_1 (reset,clk_0,out_0); +test_mod module_2 (reset,clk_1,out_1); + +initial + begin + clk_0 = 0; + clk_1 = 0; + #1 reset = 1; + # 2; + $display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0, + clk_1,out_0,out_1); + // Validate that both out_0 and out_1 are reset + if(out_0) + begin + $display("FAILED - out_0 not reset\n"); + $finish ; + end + + if(out_1) + begin + $display("FAILED - out_1 not reset\n"); + $finish ; + end + reset = 0; + $display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0, + clk_1,out_0,out_1); + # 2; + clk_0 = 1; + # 2; // Wait so we don't worry about races. + $display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0, + clk_1,out_0,out_1); + if(!out_0) + begin + $display("FAILED - out_0 didn't set on clk_0\n"); + $finish ; + end + + if(out_1) + begin + $display("FAILED - out_1 set on wrong clk!\n"); + $finish ; + end + + clk_1 = 1; + # 2; // Wait so we don't worry about races. + $display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0, + clk_1,out_0,out_1); + if(!out_1) + begin + $display("FAILED - out_1 didn't set on clk_1\n"); + $finish ; + end + + if(!out_0) + begin + $display("FAILED - out_0 changed due to clk_0\n"); + $finish ; + end + + + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/sdw_instmod2.v b/ivtest/ivltests/sdw_instmod2.v new file mode 100644 index 000000000..1013284b4 --- /dev/null +++ b/ivtest/ivltests/sdw_instmod2.v @@ -0,0 +1,108 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW: Module instantiation with non-ordered port assignment +// +// D: Same as sdw_inst1 except using .net(net) port convention. +// + +module test_mod (reset,clka,out); +input reset; +input clka; +output out; + +reg out; + +always @(posedge clka or posedge reset) + if(reset) + out = 0; + else + out = ~out; + +endmodule + +module main(); + +reg reset,clk_0,clk_1; +wire out_0,out_1; + +test_mod module_1 (.reset(reset),.clka(clk_0),.out(out_0)); +test_mod module_2 (.reset(reset),.clka(clk_1),.out(out_1)); + +initial + begin + clk_0 = 0; + clk_1 = 0; + #1 reset = 1; + # 2; + $display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0, + clk_1,out_0,out_1); + // Validate that both out_0 and out_1 are reset + if(out_0) + begin + $display("FAILED - out_0 not reset\n"); + $finish ; + end + + if(out_1) + begin + $display("FAILED - out_1 not reset\n"); + $finish ; + end + reset = 0; + $display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0, + clk_1,out_0,out_1); + # 2; + clk_0 = 1; + # 2; // Wait so we don't worry about races. + $display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0, + clk_1,out_0,out_1); + if(!out_0) + begin + $display("FAILED - out_0 didn't set on clk_0\n"); + $finish ; + end + + if(out_1) + begin + $display("FAILED - out_1 set on wrong clk!\n"); + $finish ; + end + + clk_1 = 1; + # 2; // Wait so we don't worry about races. + $display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0, + clk_1,out_0,out_1); + if(!out_1) + begin + $display("FAILED - out_1 didn't set on clk_1\n"); + $finish ; + end + + if(!out_0) + begin + $display("FAILED - out_0 changed due to clk_0\n"); + $finish ; + end + + + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/sdw_int.v b/ivtest/ivltests/sdw_int.v new file mode 100644 index 000000000..6fcc89e4a --- /dev/null +++ b/ivtest/ivltests/sdw_int.v @@ -0,0 +1,94 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - Int type declaration/validation +// +// D: Assign a 16 bit vector to an int and observe the 0 extension. +// D: Assign a 32 bit vector to an int and observer same value. +// D: Add -1 + 1. Add 0 and -1...and observer correct values. + +module main(); + +reg [15:0] a; +reg [31:0] b; + +integer result; +integer int_a; +integer int_b; + +initial // Excitation block + begin + a = 0; + b = 0; + result = 0; + # 5; // Assign a shorter value + a = 16'h1234; // should see 0 extension in result + result = a; + + # 5; // Assign a 32 bit vector + b = 32'h12345678 ; + result = b; + + # 5; // Validate sum basic integer arithmetic + int_a = -1 ; // pun intended! + int_b = 1; + result = int_a + int_b; + + # 5; + int_a = 0; + int_b = -1; + result = int_a + int_b; + + end + +initial // Validation block + begin + #1 ; + #5 ; + if(result != 32'h00001234) + begin + $display("FAILED - Bit extend wrong\n"); + $finish ; + end + + #5 ; + if(result != 32'h12345678) + begin + $display("FAILED - 32 bit assign wrong\n"); + $finish ; + end + + #5 ; + if(result != 32'h00000000) + begin + $display("FAILED - -1 + 1 = %h\n",result); + $finish ; + end + + #5 ; + if(result != 32'hffffffff) + begin + $display("FAILED - 0 - 1 = %h\n",result); + $finish ; + end + $display("PASSED\n"); + $finish ; + end + +endmodule diff --git a/ivtest/ivltests/sdw_lvalconcat.v b/ivtest/ivltests/sdw_lvalconcat.v new file mode 100644 index 000000000..ca8e4d5d4 --- /dev/null +++ b/ivtest/ivltests/sdw_lvalconcat.v @@ -0,0 +1,69 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate that an lvalue concat can receive an assignment. +// +// D: Validate that an lvalue can be a concatenation. +// + +module main (); +reg a; +reg b; +reg working; + +initial +begin + working = 1; + {a,b} = 2'b00 ; + + if( (a != 0) & (b != 0)) + begin + $display("FAILED {a,b} Expected 2'b00 - received %b%b",a,b); + working = 0; + end + + {a,b} = 2'b01 ; + + if( (a != 0) & (b != 1)) + begin + $display("FAILED {a,b} Expected 2'b01 - received %b%b",a,b); + working = 0; + end + + {a,b} = 2'b10 ; + + if( (a != 1) & (b != 0)) + begin + $display("FAILED {a,b} Expected 2'b10 - received %b%b",a,b); + working = 0; + end + + {a,b} = 2'b11 ; + + if( (a != 1) & (b != 1)) + begin + $display("FAILED {a,b} Expected 2'b11 - received %b%b",a,b); + working = 0; + end + + if(working) + $display("PASSED\n"); + +end + +endmodule diff --git a/ivtest/ivltests/sdw_lvalconcat2.v b/ivtest/ivltests/sdw_lvalconcat2.v new file mode 100644 index 000000000..d54002fd7 --- /dev/null +++ b/ivtest/ivltests/sdw_lvalconcat2.v @@ -0,0 +1,71 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate a lval concat in a continuous assignment +// +// D: Validate that an lvalue can be a concatenation. +// + +module main (); +wire a, b; +reg [1:0] c; +reg working; + +assign {a,b} = c; + +initial +begin + working = 1; + c = 2'b00 ; + + #1 if( (a !== 0) & (b !== 0)) + begin + $display("FAILED - {a,b} Expected 2'b00 - received %b%b",a,b); + working = 0; + end + + c = 2'b01 ; + + #1 if( (a !== 0) & (b !== 1)) + begin + $display("FAILED {a,b} Expected 2'b01 - received %b%b",a,b); + working = 0; + end + + c = 2'b10 ; + + #1 if( (a !== 1) & (b !== 0)) + begin + $display("FAILED {a,b} Expected 2'b10 - received %b%b",a,b); + working = 0; + end + + c = 2'b11 ; + + #1 if( (a !== 1) & (b !== 1)) + begin + $display("FAILED {a,b} Expected 2'b11 - received %b%b",a,b); + working = 0; + end + + #1 if(working) + $display("PASSED\n"); + +end + +endmodule diff --git a/ivtest/ivltests/sdw_param1.v b/ivtest/ivltests/sdw_param1.v new file mode 100644 index 000000000..25f3358f7 --- /dev/null +++ b/ivtest/ivltests/sdw_param1.v @@ -0,0 +1,62 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - Simple parameter declaration +// +// D: Declare a parameter value, then assign it to a variable. +// D: Check the value of the variable. +// + +module main(); + +parameter VAL_1 = 16'h0001; +parameter VAL_2 = 16'h5432; + +reg [15:0] test_var; + +initial // Excitation block + begin + test_var = VAL_1 ; + #5 ; + test_var = VAL_2 ; + #5 ; + end + +initial // Validation block + begin + + #1 ; + if(test_var != 16'h0001) + begin + $display("FAILED - param 1st assign didn't work\n"); + $finish ; + end + + #5 ; + if(test_var != 16'h5432) + begin + $display("FAILED - param 2nd assign didn't work\n"); + $finish ; + end + + $display("PASSED\n"); + $finish ; + end + +endmodule diff --git a/ivtest/ivltests/sdw_param2.v b/ivtest/ivltests/sdw_param2.v new file mode 100644 index 000000000..38525f341 --- /dev/null +++ b/ivtest/ivltests/sdw_param2.v @@ -0,0 +1,54 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - Comma separated parameter def used as a width subscript +// +// +// D: This validates that parameters can be used as literals +// D: in the width subscript. +// + +module main(); + +parameter VAL_1 = 5, + VAL_2 = 0; + +reg [VAL_1: VAL_2] temp_var; + +initial // Excitation block + begin + temp_var = 6'h11; + #5 ; + end + +initial // Validation block + begin + #1 ; + if(temp_var != 6'h11) + begin + $display("FAILED - parameter assignment didn't work\n"); + $finish ; + end + + + $display("PASSED\n"); + $finish ; + end + +endmodule diff --git a/ivtest/ivltests/sdw_release.v b/ivtest/ivltests/sdw_release.v new file mode 100644 index 000000000..7ffe025d7 --- /dev/null +++ b/ivtest/ivltests/sdw_release.v @@ -0,0 +1,61 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate release statement +// +// D: This code verifies the release statement. +// D: It depends on the force statement being +// D: functional! (Kinda have to - no way to +// D: release if you haven't forced the issue. +// D: It is intended to be self checking. +// +// By: Steve Wilson +// + +module main (); + +reg working; +reg timer; + +initial + working = 1; + +initial + begin + #5 ; + force working = 0; + end + +initial + begin + #10; + release working; // This releases the force + #2 ; + working = 1; // This allows a new value onto the reg. + end + +initial + begin + #20; + if(!working) + $display("FAILED\n"); + else + $display("PASSED\n"); + end + +endmodule diff --git a/ivtest/ivltests/sdw_stmt002.v b/ivtest/ivltests/sdw_stmt002.v new file mode 100644 index 000000000..95c9e0e4b --- /dev/null +++ b/ivtest/ivltests/sdw_stmt002.v @@ -0,0 +1,154 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Rewrite of stmt002_bassign.v from vbs test suite. +// +module main; + +reg [0:7] var1, var2; // Note the obtuse bit ordering. +reg [3:0] var3; // A more sane ordering on a nibble boundary... +reg var4; // Single bit. +reg [2:9] var5; // Use a non-alligned, reversed bit - still 8 bits +reg error; + +initial + begin + // First verify that all the defined variables are x's. + error = 0; + if(var1 !== 8'hxx) + begin + $display("FAILED - sdw_stmt002 - var1 not 8'hxx"); + error = 1; + end + if(var2 !== 8'hxx) + begin + $display("FAILED - sdw_stmt002 -var2 not 8'hxx"); + error = 1; + end + if(var3 !== 4'bx_xxx) + begin + $display("FAILED - sdw_stmt002 -var3 not 4'hx"); + error = 1; + end + if(var4 !== 1'bx) + begin + $display("FAILED - sdw_stmt002 -var4 not 1'bx"); + error = 1; + end + if(var5 !== 8'hxx) + begin + $display("FAILED - sdw_stmt002 -var5 not 8'hxx"); + error = 1; + end + + var1 = 8'b1001_0010; // Do some binary bits + var2 = 255; // Fill it with decimal version of ff + var3 = 4'hf; // hex + var4 = 0; + var5 = 8'h99; // Still 8 bits + + if(var1 != 8'h92) + begin + $display("FAILED - sdw_stmt002 - var1 not 8'h96"); + error = 1; + end + if(var2 != 8'hff) + begin + $display("FAILED - sdw_stmt002 -var2 not 8'hff"); + error = 1; + end + if(var3 != 4'b1111) + begin + $display("FAILED - sdw_stmt002 -var3 not 4'hf"); + error = 1; + end + if(var4 != 1'b0) + begin + $display("FAILED - sdw_stmt002 -var4 not 1'b0"); + error = 1; + end + if(var5 != 8'h99) + begin + $display("FAILED - sdw_stmt002 -var5 not 8'h99"); + error = 1; + end + + // Next - assign sub-portion of vector + var1 [3:6] = var3; + + if(var1 != 8'h9e) + begin + $display("FAILED - sdw_stmt002 - subfield assign failed"); + error = 1; + end + + var3 = 4'o11; // Lets try octal now + var4 = 1'b1; // And set that bit to 1, it WAS 0 + var5 = 8'h66; // Invert it + + if(var3 != 4'b1001) + begin + $display("FAILED - sdw_stmt002 -var3 octal assign"); + error = 1; + end + if(var4 != 1'b1) + begin + $display("FAILED - sdw_stmt002 -var4 not 1'b1"); + error = 1; + end + if(var5 != 8'h66) + begin + $display("FAILED - sdw_stmt002 -var5 not 8'h66"); + error = 1; + end + + // 9e, 9 + + var3 = var1[4:7]; // Should be an 4'he + var1[0:3] = var3[3:2]; // Now should give 8'hce + + if(var1 != 8'h3e) + begin + $display("FAILED - sdw_stmt002 - subfield assign(1) w/ 0 extension"); + error = 1; + end + if(var3 != 4'b1110) + begin + $display("FAILED - sdw_stmt002 -subfield assign(2)"); + error = 1; + end + + var3 = var5; // 4 bit from 8 bit(4'h6) + var5[5] = var4; // Set var5 to 8'h76 + + if(var3 != 4'h6) + begin + $display("FAILED - sdw_stmt002 - 4bit from 8 bit assign"); + error = 1; + end + if(var5 != 8'h76) + begin + $display("FAILED - sdw_stmt002 - single sub-bit assign "); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/sdw_task1.v b/ivtest/ivltests/sdw_task1.v new file mode 100644 index 000000000..1684f0863 --- /dev/null +++ b/ivtest/ivltests/sdw_task1.v @@ -0,0 +1,50 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - Verify task basic function with no values passed. +// +// D: Task validation. Notice that there are no values passed to this task. +// +// + +module main(); + +reg [3:0] global_reg; + +task dec_glob; +begin + global_reg = global_reg -1; +end +endtask + +initial +begin + global_reg = 2; + dec_glob; + + if(global_reg != 1) + begin + $display("FAILED - task didn't modify global_reg\n"); + $finish ; + end + $display("PASSED\n"); + $finish ; +end + +endmodule diff --git a/ivtest/ivltests/sdw_task2.v b/ivtest/ivltests/sdw_task2.v new file mode 100644 index 000000000..ce0b6097c --- /dev/null +++ b/ivtest/ivltests/sdw_task2.v @@ -0,0 +1,52 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - Verify task with I/O. +// +// D: Pass a task two values and modify a global variable. +// + +module main(); + +reg [3:0] global_reg; + +task inc_glob; +input [3:0] in_1; +input [3:0] in_2; +begin + global_reg = in_1 + in_2 ; +end +endtask + +initial +begin + global_reg = 2; + inc_glob(global_reg,global_reg); + + if(global_reg != 4) + begin + $display("FAILED - task didn't modify global_reg\n"); + $finish ; + end + + $display("PASSED\n"); + $finish ; +end + +endmodule diff --git a/ivtest/ivltests/sel_rval_bit_ob.v b/ivtest/ivltests/sel_rval_bit_ob.v new file mode 100644 index 000000000..2123f8fc4 --- /dev/null +++ b/ivtest/ivltests/sel_rval_bit_ob.v @@ -0,0 +1,414 @@ +`begin_keywords "1364-2005" +// Module to test the messages/results for out of bound R-value constant +// bit selects. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + reg big_param; + reg bit; + + integer idx; + + parameter pvar0 = 0; + parameter pvar1 = 1; + parameter pvar2 = -1; + parameter pvar3 = 4'b0001; + parameter [4:1] pvar4 = 4'b0001; + parameter [1:4] pvar5 = 4'b0001; + reg [4:1] rvar = 4'b0010; + reg [1:4] rvar2 = 4'b0010; + reg [4:1] ravar [2:1]; + reg [1:4] ravar2 [2:1]; + wire [4:1] wvar = 4'b0100; + wire [1:4] wvar2 = 4'b0100; + wire [4:1] wavar [2:1]; + wire [1:4] wavar2 [2:1]; + + assign wavar[1] = 4'b1001; + assign wavar[2] = 4'b1010; + assign wavar2[1] = 4'b1001; + assign wavar2[2] = 4'b1010; + + initial begin + pass = 1'b1; + ravar[1] = 4'b1101; + ravar[2] = 4'b1110; + ravar2[1] = 4'b1101; + ravar2[2] = 4'b1110; + #1; + + // Icarus supports an unlimited size for unsized parameters. The + // following checks the 33rd bit to see if it is 1'bx. If so we + // assume that the simulator only support 32 bit, otherwise we + // modify our after check for unsized parameters to work (pass) + // with a larger constant. + big_param = 1'b1; + idx = 32; + if (pvar0[idx] === 1'bx) big_param = 1'b0; + + // Check a parameter with default size equal to 0. + bit = pvar0[31]; // At end + if (bit !== 1'b0) begin + $display("Failed at end bit select of a parameter (0), got %b", bit); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = pvar0[32]; // May be after + if (bit !== (big_param ? 1'b0: 1'bx)) begin + $display("Failed after bit select of a parameter (0), got %b", bit); + pass = 1'b0; + end + bit = pvar0[-1]; // Before + if (bit !== 1'bx) begin + $display("Failed before bit select of a parameter (0), got %b", bit); + pass = 1'b0; + end + bit = pvar0[1'bx]; // Undefined + if (bit !== 1'bx) begin + $display("Failed undefined bit select of a parameter (0), got %b", bit); + pass = 1'b0; + end + bit = pvar0[1'bz]; // High-Z + if (bit !== 1'bx) begin + $display("Failed high-Z bit select of a parameter (0), got %b", bit); + pass = 1'b0; + end +`endif + + // Check a parameter with default size equal to 1. + bit = pvar1[31]; // At end + if (bit !== 1'b0) begin + $display("Failed at end bit select of a parameter (1), got %b", bit); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = pvar1[32]; // May be after + if (bit !== (big_param ? 1'b0: 1'bx)) begin + $display("Failed after bit select of a parameter (1), got %b", bit); + pass = 1'b0; + end + bit = pvar1[-1]; // Before + if (bit !== 1'bx) begin + $display("Failed before bit select of a parameter (1), got %b", bit); + pass = 1'b0; + end + bit = pvar1[1'bx]; // Undefined + if (bit !== 1'bx) begin + $display("Failed undefined bit select of a parameter (1), got %b", bit); + pass = 1'b0; + end + bit = pvar1[1'bz]; // High-Z + if (bit !== 1'bx) begin + $display("Failed high-Z bit select of a parameter (1), got %b", bit); + pass = 1'b0; + end +`endif + + // Check a parameter with default size equal to -1. + bit = pvar2[31]; // At end + if (bit !== 1'b1) begin + $display("Failed at end bit select of a parameter (-1), got %b", bit); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = pvar2[32]; // May be after + if (bit !== (big_param ? 1'b1: 1'bx)) begin + $display("Failed after bit select of a parameter (-1), got %b", bit); + pass = 1'b0; + end + bit = pvar2[-1]; // Before + if (bit !== 1'bx) begin + $display("Failed before bit select of a parameter (-1), got %b", bit); + pass = 1'b0; + end + bit = pvar2[1'bx]; // Undefined + if (bit !== 1'bx) begin + $display("Failed undefined bit select of a parameter (-1), got %b", bit); + pass = 1'b0; + end + bit = pvar2[1'bz]; // High-Z + if (bit !== 1'bx) begin + $display("Failed high-Z bit select of a parameter (-1), got %b", bit); + pass = 1'b0; + end +`endif + + // Check a parameter with size four from the value. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = pvar3[4]; // After + if (bit !== 1'bx) begin + $display("Failed after bit select of a parameter (3), got %b", bit); + pass = 1'b0; + end + bit = pvar3[-1]; // Before + if (bit !== 1'bx) begin + $display("Failed before bit select of a parameter (3), got %b", bit); + pass = 1'b0; + end + bit = pvar3[1'bx]; // Undefined + if (bit !== 1'bx) begin + $display("Failed undefined bit select of a parameter (3), got %b", bit); + pass = 1'b0; + end + bit = pvar3[1'bz]; // High-Z + if (bit !== 1'bx) begin + $display("Failed high-Z bit select of a parameter (3), got %b", bit); + pass = 1'b0; + end +`endif + + // Check a parameter with size four from the range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = pvar4[5]; // After + if (bit !== 1'bx) begin + $display("Failed after bit select of a parameter (4), got %b", bit); + pass = 1'b0; + end + bit = pvar4[0]; // Before + if (bit !== 1'bx) begin + $display("Failed before bit select of a parameter (4), got %b", bit); + pass = 1'b0; + end + bit = pvar4[1'bx]; // Undefined + if (bit !== 1'bx) begin + $display("Failed undefined bit select of a parameter (4), got %b", bit); + pass = 1'b0; + end + bit = pvar4[1'bz]; // High-Z + if (bit !== 1'bx) begin + $display("Failed high-Z bit select of a parameter (4), got %b", bit); + pass = 1'b0; + end +`endif + + // Check a parameter with size four from the range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = pvar5[0]; // After + if (bit !== 1'bx) begin + $display("Failed after bit select of a parameter (5), got %b", bit); + pass = 1'b0; + end + bit = pvar5[5]; // Before + if (bit !== 1'bx) begin + $display("Failed before bit select of a parameter (5), got %b", bit); + pass = 1'b0; + end + bit = pvar5[1'bx]; // Undefined + if (bit !== 1'bx) begin + $display("Failed undefined bit select of a parameter (5), got %b", bit); + pass = 1'b0; + end + bit = pvar5[1'bz]; // High-Z + if (bit !== 1'bx) begin + $display("Failed high-Z bit select of a parameter (5), got %b", bit); + pass = 1'b0; + end +`endif + + + // Check a register with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = rvar[5]; // After + if (bit !== 1'bx) begin + $display("Failed after bit select of a register, got %b", bit); + pass = 1'b0; + end + bit = rvar[0]; // Before + if (bit !== 1'bx) begin + $display("Failed before bit select of a register, got %b", bit); + pass = 1'b0; + end + bit = rvar[1'bx]; // Undefined + if (bit !== 1'bx) begin + $display("Failed undefined bit select of a register, got %b", bit); + pass = 1'b0; + end + bit = rvar[1'bz]; // High-Z + if (bit !== 1'bx) begin + $display("Failed high-Z bit select of a register, got %b", bit); + pass = 1'b0; + end +`endif + + // Check a register with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = rvar2[0]; // After + if (bit !== 1'bx) begin + $display("Failed after bit select of a register (2), got %b", bit); + pass = 1'b0; + end + bit = rvar2[5]; // Before + if (bit !== 1'bx) begin + $display("Failed before bit select of a register (2), got %b", bit); + pass = 1'b0; + end + bit = rvar2[1'bx]; // Undefined + if (bit !== 1'bx) begin + $display("Failed undefined bit select of a register (2), got %b", bit); + pass = 1'b0; + end + bit = rvar2[1'bz]; // High-Z + if (bit !== 1'bx) begin + $display("Failed high-Z bit select of a register (2), got %b", bit); + pass = 1'b0; + end +`endif + + + // Check an array word with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = ravar[1][5]; // After + if (bit !== 1'bx) begin + $display("Failed after bit select of an array word, got %b", bit); + pass = 1'b0; + end + bit = ravar[1][0]; // Before + if (bit !== 1'bx) begin + $display("Failed before bit select of an array word, got %b", bit); + pass = 1'b0; + end + bit = ravar[1][1'bx]; // Undefined + if (bit !== 1'bx) begin + $display("Failed undefined bit select of an array word, got %b", bit); + pass = 1'b0; + end + bit = ravar[1][1'bz]; // High-Z + if (bit !== 1'bx) begin + $display("Failed high-Z bit select of an array word, got %b", bit); + pass = 1'b0; + end +`endif + + // Check an array word with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = ravar2[1][0]; // After + if (bit !== 1'bx) begin + $display("Failed after bit select of an array word (2), got %b", bit); + pass = 1'b0; + end + bit = ravar2[1][5]; // Before + if (bit !== 1'bx) begin + $display("Failed before bit select of an array word (2), got %b", bit); + pass = 1'b0; + end + bit = ravar2[1][1'bx]; // Undefined + if (bit !== 1'bx) begin + $display("Failed undefined bit select of an array word (2), got %b", bit); + pass = 1'b0; + end + bit = ravar2[1][1'bz]; // High-Z + if (bit !== 1'bx) begin + $display("Failed high-Z bit select of an array word (2), got %b", bit); + pass = 1'b0; + end +`endif + + + // Check a wire with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = wvar[5]; // After + if (bit !== 1'bx) begin + $display("Failed after bit select of a wire, got %b", bit); + pass = 1'b0; + end + bit = wvar[0]; // Before + if (bit !== 1'bx) begin + $display("Failed before bit select of a wire, got %b", bit); + pass = 1'b0; + end + bit = wvar[1'bx]; // Undefined + if (bit !== 1'bx) begin + $display("Failed undefined bit select of a wire, got %b", bit); + pass = 1'b0; + end + bit = wvar[1'bz]; // High-Z + if (bit !== 1'bx) begin + $display("Failed high-Z bit select of a wire, got %b", bit); + pass = 1'b0; + end +`endif + + // Check a wire with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = wvar2[0]; // After + if (bit !== 1'bx) begin + $display("Failed after bit select of a wire (2), got %b", bit); + pass = 1'b0; + end + bit = wvar2[5]; // Before + if (bit !== 1'bx) begin + $display("Failed before bit select of a wire (2), got %b", bit); + pass = 1'b0; + end + bit = wvar2[1'bx]; // Undefined + if (bit !== 1'bx) begin + $display("Failed undefined bit select of a wire (2), got %b", bit); + pass = 1'b0; + end + bit = wvar2[1'bz]; // High-Z + if (bit !== 1'bx) begin + $display("Failed high-Z bit select of a wire (2), got %b", bit); + pass = 1'b0; + end +`endif + + + // Check a wire array word with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = wavar[1][5]; // After + if (bit !== 1'bx) begin + $display("Failed after bit select of a wire array word, got %b", bit); + pass = 1'b0; + end + bit = wavar[1][0]; // Before + if (bit !== 1'bx) begin + $display("Failed before bit select of a wire array word, got %b", bit); + pass = 1'b0; + end + bit = wavar[1][1'bx]; // Undefined + if (bit !== 1'bx) begin + $display("Failed undefined bit select of a wire array word, got %b", bit); + pass = 1'b0; + end + bit = wavar[1][1'bz]; // High-Z + if (bit !== 1'bx) begin + $display("Failed high-Z bit select of a wire array word, got %b", bit); + pass = 1'b0; + end +`endif + + // Check a wire array word with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + bit = wavar2[1][0]; // After + if (bit !== 1'bx) begin + $display("Failed after bit select of a wire array word (2), got %b", bit); + pass = 1'b0; + end + bit = wavar2[1][5]; // Before + if (bit !== 1'bx) begin + $display("Failed before bit select of a wire array word (2), got %b", + bit); + pass = 1'b0; + end + bit = wavar2[1][1'bx]; // Undefined + if (bit !== 1'bx) begin + $display("Failed undefined bit select of a wire array word (2), got %b", + bit); + pass = 1'b0; + end + bit = wavar2[1][1'bz]; // High-Z + if (bit !== 1'bx) begin + $display("Failed high-Z bit select of a wire array word (2), got %b", + bit); + pass = 1'b0; + end +`endif + + if (pass) $display("PASSED"); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/sel_rval_part_ob.v b/ivtest/ivltests/sel_rval_part_ob.v new file mode 100644 index 000000000..36b1f2f5a --- /dev/null +++ b/ivtest/ivltests/sel_rval_part_ob.v @@ -0,0 +1,751 @@ +// Module to test the messages for out of bound R-value part selects. + +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + reg big_param; + reg [1:0] part; + integer idx; + + parameter pvar0 = 0; + parameter pvar1 = 1; + parameter pvar2 = -1; + parameter pvar3 = 4'b0001; + parameter [4:1] pvar4 = 4'b0001; + parameter [1:4] pvar5 = 4'b0001; + reg [4:1] rvar = 4'b1000; + reg [1:4] rvar2 = 4'b1000; + reg [4:1] ravar [2:1]; + reg [1:4] ravar2 [2:1]; + wire [4:1] wvar = 4'b1010; + wire [1:4] wvar2 = 4'b1010; + wire [4:1] wavar [2:1]; + wire [1:4] wavar2 [2:1]; + + assign wavar[1] = 4'b0111; + assign wavar[2] = 4'b1110; + assign wavar2[1] = 4'b0111; + assign wavar2[2] = 4'b1110; + + initial begin + pass = 1'b1; + ravar[1] = 4'b0111; + ravar[2] = 4'b1110; + ravar2[1] = 4'b0111; + ravar2[2] = 4'b1110; + #1; + + // Icarus supports an unlimited size for unsized parameters. The + // following checks the 33rd bit to see if it is 1'bx. If so we + // assume that the simulator only support 32 bit, otherwise we + // modify our after check for unsized parameters to work (pass) + // with a larger constant. + big_param = 1'b1; + idx = 32; + if (pvar0[idx] === 1'bx) big_param = 1'b0; + + // Check a parameter with default size equal to 0. + part = pvar0[31:30]; // At end + if (part !== 2'b00) begin + $display("Failed at end part select of a parameter (0), got %b", part); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = pvar0[33:32]; // May be after all + if (part !== (big_param ? 2'b00: 2'bxx)) begin + $display("Failed after part select of a parameter (0), got %b", part); + pass = 1'b0; + end + part = pvar0[32:31]; // May be partial after + if (part !== (big_param ? 2'b00 : 2'bx0)) begin + $display("Failed partial after part select of a parameter (0), got %b", + part); + pass = 1'b0; + end + part = pvar0[-1:-2]; // Before all + if (part !== 2'bxx) begin + $display("Failed before part select of a parameter (0), got %b", part); + pass = 1'b0; + end + part = pvar0[0:-1]; // Partial before + if (part !== 2'b0x) begin + $display("Failed partial before part select of a parameter (0), got %b", + part); + pass = 1'b0; + end + part = pvar0[1'bx:1]; // Undefined 1st + if (part !== 2'bxx) begin + $display("Failed undefined 1st part select of a parameter (0), got %b", + part); + pass = 1'b0; + end + part = pvar0[1:1'bx]; // Undefined 2nd + if (part !== 2'bxx) begin + $display("Failed undefined 2nd part select of a parameter (0), got %b", + part); + pass = 1'b0; + end + part = pvar0[1'bz:1]; // High-Z 1st + if (part !== 2'bxx) begin + $display("Failed high-Z 1st part select of a parameter (0), got %b", + part); + pass = 1'b0; + end + part = pvar0[1:1'bz]; // High-Z 2nd + if (part !== 2'bxx) begin + $display("Failed high-Z 2nd part select of a parameter (0), got %b", + part); + pass = 1'b0; + end +`endif + + // Check a parameter with default size equal to 1. + part = pvar1[31:30]; // At end + if (part !== 2'b00) begin + $display("Failed at end part select of a parameter (1), got %b", part); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = pvar1[33:32]; // May be after all + if (part !== (big_param ? 2'b00: 2'bxx)) begin + $display("Failed after part select of a parameter (1), got %b", part); + pass = 1'b0; + end + part = pvar1[32:31]; // May be partial after + if (part !== (big_param ? 2'b00 : 2'bx0)) begin + $display("Failed partial after part select of a parameter (1), got %b", + part); + pass = 1'b0; + end + part = pvar1[-1:-2]; // Before all + if (part !== 2'bxx) begin + $display("Failed before part select of a parameter (1), got %b", part); + pass = 1'b0; + end + part = pvar1[0:-1]; // Partial before + if (part !== 2'b1x) begin + $display("Failed partial before part select of a parameter (1), got %b", + part); + pass = 1'b0; + end + part = pvar1[1'bx:1]; // Undefined 1st + if (part !== 2'bxx) begin + $display("Failed undefined 1st part select of a parameter (1), got %b", + part); + pass = 1'b0; + end + part = pvar1[1:1'bx]; // Undefined 2nd + if (part !== 2'bxx) begin + $display("Failed undefined 2nd part select of a parameter (1), got %b", + part); + pass = 1'b0; + end + part = pvar1[1'bz:1]; // High-Z 1st + if (part !== 2'bxx) begin + $display("Failed high-Z 1st part select of a parameter (1), got %b", + part); + pass = 1'b0; + end + part = pvar1[1:1'bz]; // High-Z 2nd + if (part !== 2'bxx) begin + $display("Failed high-Z 2nd part select of a parameter (1), got %b", + part); + pass = 1'b0; + end +`endif + + // Check a parameter with default size equal to -1. + part = pvar2[31:30]; // At end + if (part !== 2'b11) begin + $display("Failed at end part select of a parameter (2), got %b", part); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = pvar2[33:32]; // May be after all + if (part !== (big_param ? 2'b11: 2'bxx)) begin + $display("Failed after part select of a parameter (2), got %b", part); + pass = 1'b0; + end + part = pvar2[32:31]; // May be partial after + if (part !== (big_param ? 2'b11 : 2'bx1)) begin + $display("Failed partial after part select of a parameter (2), got %b", + part); + pass = 1'b0; + end + part = pvar2[-1:-2]; // Before all + if (part !== 2'bxx) begin + $display("Failed before part select of a parameter (2), got %b", part); + pass = 1'b0; + end + part = pvar2[0:-1]; // Partial before + if (part !== 2'b1x) begin + $display("Failed partial before part select of a parameter (2), got %b", + part); + pass = 1'b0; + end + part = pvar2[1'bx:1]; // Undefined 1st + if (part !== 2'bxx) begin + $display("Failed undefined 1st part select of a parameter (2), got %b", + part); + pass = 1'b0; + end + part = pvar2[1:1'bx]; // Undefined 2nd + if (part !== 2'bxx) begin + $display("Failed undefined 2nd part select of a parameter (2), got %b", + part); + pass = 1'b0; + end + part = pvar2[1'bz:1]; // High-Z 1st + if (part !== 2'bxx) begin + $display("Failed high-Z 1st part select of a parameter (2), got %b", + part); + pass = 1'b0; + end + part = pvar2[1:1'bz]; // High-Z 2nd + if (part !== 2'bxx) begin + $display("Failed high-Z 2nd part select of a parameter (2), got %b", + part); + pass = 1'b0; + end +`endif + + // Check a parameter with size four from the value. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = pvar3[5:4]; // After all + if (part !== 2'bxx) begin + $display("Failed after part select of a parameter (3), got %b", part); + pass = 1'b0; + end + part = pvar3[4:3]; // Partial after + if (part !== 2'bx0) begin + $display("Failed partial after part select of a parameter (3), got %b", + part); + pass = 1'b0; + end + part = pvar3[-1:-2]; // Before all + if (part !== 2'bxx) begin + $display("Failed before part select of a parameter (3), got %b", part); + pass = 1'b0; + end + part = pvar3[0:-1]; // Partial before + if (part !== 2'b1x) begin + $display("Failed partial before part select of a parameter (3), got %b", + part); + pass = 1'b0; + end + part = pvar3[1'bx:1]; // Undefined 1st + if (part !== 2'bxx) begin + $display("Failed undefined 1st part select of a parameter (3), got %b", + part); + pass = 1'b0; + end + part = pvar3[1:1'bx]; // Undefined 2nd + if (part !== 2'bxx) begin + $display("Failed undefined 2nd part select of a parameter (3), got %b", + part); + pass = 1'b0; + end + part = pvar3[1'bz:1]; // High-Z 1st + if (part !== 2'bxx) begin + $display("Failed high-Z 1st part select of a parameter (3), got %b", + part); + pass = 1'b0; + end + part = pvar3[1:1'bz]; // High-Z 2nd + if (part !== 2'bxx) begin + $display("Failed high-Z 2nd part select of a parameter (3), got %b", + part); + pass = 1'b0; + end +`endif + + // Check a parameter with size four from the range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = pvar4[6:5]; // After all + if (part !== 2'bxx) begin + $display("Failed after part select of a parameter (4), got %b", part); + pass = 1'b0; + end + part = pvar4[5:4]; // Partial after + if (part !== 2'bx0) begin + $display("Failed partial after part select of a parameter (4), got %b", + part); + pass = 1'b0; + end + part = pvar4[0:-1]; // Before all + if (part !== 2'bxx) begin + $display("Failed before part select of a parameter (4), got %b", part); + pass = 1'b0; + end + part = pvar4[1:0]; // Partial before + if (part !== 2'b1x) begin + $display("Failed partial before part select of a parameter (4), got %b", + part); + pass = 1'b0; + end + part = pvar4[1'bx:1]; // Undefined 1st + if (part !== 2'bxx) begin + $display("Failed undefined 1st part select of a parameter (4), got %b", + part); + pass = 1'b0; + end + part = pvar4[1:1'bx]; // Undefined 2nd + if (part !== 2'bxx) begin + $display("Failed undefined 2nd part select of a parameter (4), got %b", + part); + pass = 1'b0; + end + part = pvar4[1'bz:1]; // High-Z 1st + if (part !== 2'bxx) begin + $display("Failed high-Z 1st part select of a parameter (4), got %b", + part); + pass = 1'b0; + end + part = pvar4[1:1'bz]; // High-Z 2nd + if (part !== 2'bxx) begin + $display("Failed high-Z 2nd part select of a parameter (4), got %b", + part); + pass = 1'b0; + end +`endif + + // Check a parameter with size four from the range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = pvar5[-1:0]; // After all + if (part !== 2'bxx) begin + $display("Failed after part select of a parameter (5), got %b", part); + pass = 1'b0; + end + part = pvar5[0:1]; // Partial after + if (part !== 2'bx0) begin + $display("Failed partial after part select of a parameter (5), got %b", + part); + pass = 1'b0; + end + part = pvar5[5:6]; // Before all + if (part !== 2'bxx) begin + $display("Failed before part select of a parameter (5), got %b", part); + pass = 1'b0; + end + part = pvar5[4:5]; // Partial before + if (part !== 2'b1x) begin + $display("Failed partial before part select of a parameter (5), got %b", + part); + pass = 1'b0; + end + part = pvar5[1'bx:1]; // Undefined 1st + if (part !== 2'bxx) begin + $display("Failed undefined 1st part select of a parameter (5), got %b", + part); + pass = 1'b0; + end + part = pvar5[1:1'bx]; // Undefined 2nd + if (part !== 2'bxx) begin + $display("Failed undefined 2nd part select of a parameter (5), got %b", + part); + pass = 1'b0; + end + part = pvar5[1'bz:1]; // High-Z 1st + if (part !== 2'bxx) begin + $display("Failed high-Z 1st part select of a parameter (5), got %b", + part); + pass = 1'b0; + end + part = pvar5[1:1'bz]; // High-Z 2nd + if (part !== 2'bxx) begin + $display("Failed high-Z 2nd part select of a parameter (5), got %b", + part); + pass = 1'b0; + end +`endif + + + // Check a register with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = rvar[6:5]; // After all + if (part !== 2'bxx) begin + $display("Failed after part select of a register, got %b", part); + pass = 1'b0; + end + part = rvar[5:4]; // Partial after + if (part !== 2'bx1) begin + $display("Failed partial after part select of a register, got %b", part); + pass = 1'b0; + end + part = rvar[0:-1]; // Before all + if (part !== 2'bxx) begin + $display("Failed before part select of a register, got %b", part); + pass = 1'b0; + end + part = rvar[1:0]; // Partial before + if (part !== 2'b0x) begin + $display("Failed partial before part select of a register, got %b", part); + pass = 1'b0; + end + part = rvar[1'bx:1]; // Undefined 1st + if (part !== 2'bxx) begin + $display("Failed undefined 1st part select of a register, got %b", part); + pass = 1'b0; + end + part = rvar[1:1'bx]; // Undefined 2nd + if (part !== 2'bxx) begin + $display("Failed undefined 2nd part select of a register, got %b", part); + pass = 1'b0; + end + part = rvar[1'bz:1]; // High-Z 1st + if (part !== 2'bxx) begin + $display("Failed high-Z 1st part select of a register, got %b", part); + pass = 1'b0; + end + part = rvar[1:1'bz]; // High-Z 2nd + if (part !== 2'bxx) begin + $display("Failed high-Z 2nd part select of a register, got %b", part); + pass = 1'b0; + end +`endif + + // Check a register with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = rvar2[-1:0]; // After all + if (part !== 2'bxx) begin + $display("Failed after part select of a register (2), got %b", part); + pass = 1'b0; + end + part = rvar2[0:1]; // Partial after + if (part !== 2'bx1) begin + $display("Failed partial after part select of a register (2), got %b", + part); + pass = 1'b0; + end + part = rvar2[5:6]; // Before all + if (part !== 2'bxx) begin + $display("Failed before part select of a register (2), got %b", part); + pass = 1'b0; + end + part = rvar2[4:5]; // Partial before + if (part !== 2'b0x) begin + $display("Failed partial before part select of a register (2), got %b", + part); + pass = 1'b0; + end + part = rvar2[1'bx:1]; // Undefined 1st + if (part !== 2'bxx) begin + $display("Failed undefined 1st part select of a register (2), got %b", + part); + pass = 1'b0; + end + part = rvar2[1:1'bx]; // Undefined 2nd + if (part !== 2'bxx) begin + $display("Failed undefined 2nd part select of a register (2), got %b", + part); + pass = 1'b0; + end + part = rvar2[1'bz:1]; // High-Z 1st + if (part !== 2'bxx) begin + $display("Failed high-Z 1st part select of a register (2), got %b", part); + pass = 1'b0; + end + part = rvar2[1:1'bz]; // High-Z 2nd + if (part !== 2'bxx) begin + $display("Failed high-Z 2nd part select of a register (2), got %b", part); + pass = 1'b0; + end +`endif + + + // Check an array word with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = ravar[1][6:5]; // After all + if (part !== 2'bxx) begin + $display("Failed after part select of an array word, got %b", part); + pass = 1'b0; + end + part = ravar[1][5:4]; // Partial after + if (part !== 2'bx0) begin + $display("Failed partial after part select of an array word, got %b", + part); + pass = 1'b0; + end + part = ravar[1][0:-1]; // Before all + if (part !== 2'bxx) begin + $display("Failed before part select of an array word, got %b", part); + pass = 1'b0; + end + part = ravar[1][1:0]; // Partial before + if (part !== 2'b1x) begin + $display("Failed partial before part select of an array word, got %b", + part); + pass = 1'b0; + end + part = ravar[1][1'bx:1]; // Undefined 1st + if (part !== 2'bxx) begin + $display("Failed undefined 1st part select of an array word, got %b", + part); + pass = 1'b0; + end + part = ravar[1][1:1'bx]; // Undefined 2nd + if (part !== 2'bxx) begin + $display("Failed undefined 2nd part select of an array word, got %b", + part); + pass = 1'b0; + end + part = ravar[1][1'bz:1]; // High-Z 1st + if (part !== 2'bxx) begin + $display("Failed high-Z 1st part select of an array word, got %b", part); + pass = 1'b0; + end + part = ravar[1][1:1'bz]; // High-Z 2nd + if (part !== 2'bxx) begin + $display("Failed high-Z 2nd part select of an array word, got %b", part); + pass = 1'b0; + end +`endif + + // Check an array word with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = ravar2[1][-1:0]; // After all + if (part !== 2'bxx) begin + $display("Failed after part select of an array word (2), got %b", part); + pass = 1'b0; + end + part = ravar2[1][0:1]; // Partial after + if (part !== 2'bx0) begin + $display("Failed partial after part select of an array word (2), got %b", + part); + pass = 1'b0; + end + part = ravar2[1][5:6]; // Before all + if (part !== 2'bxx) begin + $display("Failed before part select of an array word (2), got %b", part); + pass = 1'b0; + end + part = ravar2[1][4:5]; // Partial before + if (part !== 2'b1x) begin + $display("Failed partial before part select of an array word (2), got %b", + part); + pass = 1'b0; + end + part = ravar2[1][1'bx:1]; // Undefined 1st + if (part !== 2'bxx) begin + $display("Failed undefined 1st part select of an array word (2), got %b", + part); + pass = 1'b0; + end + part = ravar2[1][1:1'bx]; // Undefined 2nd + if (part !== 2'bxx) begin + $display("Failed undefined 2nd part select of an array word (2), got %b", + part); + pass = 1'b0; + end + part = ravar2[1][1'bz:1]; // High-Z 1st + if (part !== 2'bxx) begin + $display("Failed high-Z 1st part select of an array word (2), got %b", + part); + pass = 1'b0; + end + part = ravar2[1][1:1'bz]; // High-Z 2nd + if (part !== 2'bxx) begin + $display("Failed high-Z 2nd part select of an array word (2), got %b", + part); + pass = 1'b0; + end +`endif + + + // Check a wire with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = wvar[6:5]; // After all + if (part !== 2'bxx) begin + $display("Failed after part select of a wire, got %b", part); + pass = 1'b0; + end + part = wvar[5:4]; // Partial after + if (part !== 2'bx1) begin + $display("Failed partial after part select of a wire, got %b", part); + pass = 1'b0; + end + part = wvar[0:-1]; // Before all + if (part !== 2'bxx) begin + $display("Failed before part select of a wire, got %b", part); + pass = 1'b0; + end + part = wvar[1:0]; // Partial before + if (part !== 2'b0x) begin + $display("Failed partial before part select of a wire, got %b", part); + pass = 1'b0; + end + part = wvar[1'bx:1]; // Undefined 1st + if (part !== 2'bxx) begin + $display("Failed undefined 1st part select of a wire, got %b", part); + pass = 1'b0; + end + part = wvar[1:1'bx]; // Undefined 2nd + if (part !== 2'bxx) begin + $display("Failed undefined 2nd part select of a wire, got %b", part); + pass = 1'b0; + end + part = wvar[1'bz:1]; // High-Z 1st + if (part !== 2'bxx) begin + $display("Failed high-Z 1st part select of a wire, got %b", part); + pass = 1'b0; + end + part = wvar[1:1'bz]; // High-Z 2nd + if (part !== 2'bxx) begin + $display("Failed high-Z 2nd part select of a wire, got %b", part); + pass = 1'b0; + end +`endif + + // Check a wire with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = wvar2[-1:0]; // After all + if (part !== 2'bxx) begin + $display("Failed after part select of a wire (2), got %b", part); + pass = 1'b0; + end + part = wvar2[0:1]; // Partial after + if (part !== 2'bx1) begin + $display("Failed partial after part select of a wire (2), got %b", part); + pass = 1'b0; + end + part = wvar2[5:6]; // Before all + if (part !== 2'bxx) begin + $display("Failed before part select of a wire (2), got %b", part); + pass = 1'b0; + end + part = wvar2[4:5]; // Partial before + if (part !== 2'b0x) begin + $display("Failed partial before part select of a wire (2), got %b", part); + pass = 1'b0; + end + part = wvar2[1'bx:1]; // Undefined 1st + if (part !== 2'bxx) begin + $display("Failed undefined 1st part select of a wire (2), got %b", part); + pass = 1'b0; + end + part = wvar2[1:1'bx]; // Undefined 2nd + if (part !== 2'bxx) begin + $display("Failed undefined 2nd part select of a wire (2), got %b", part); + pass = 1'b0; + end + part = wvar2[1'bz:1]; // High-Z 1st + if (part !== 2'bxx) begin + $display("Failed high-Z 1st part select of a wire (2), got %b", part); + pass = 1'b0; + end + part = wvar2[1:1'bz]; // High-Z 2nd + if (part !== 2'bxx) begin + $display("Failed high-Z 2nd part select of a wire (2), got %b", part); + pass = 1'b0; + end +`endif + + + // Check a wire array word with range [4:1]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = wavar[1][6:5]; // After all + if (part !== 2'bxx) begin + $display("Failed after part select of a wire array word, got %b", part); + pass = 1'b0; + end + part = wavar[1][5:4]; // Partial after + if (part !== 2'bx0) begin + $display("Failed partial after part select of a wire array word, got %b", + part); + pass = 1'b0; + end + part = wavar[1][0:-1]; // Before all + if (part !== 2'bxx) begin + $display("Failed before part select of a wire array word, got %b", part); + pass = 1'b0; + end + part = wavar[1][1:0]; // Partial before + if (part !== 2'b1x) begin + $display("Failed partial before part select of a wire array word, got %b", + part); + pass = 1'b0; + end + part = wavar[1][1'bx:1]; // Undefined 1st + if (part !== 2'bxx) begin + $display("Failed undefined 1st part select of a wire array word, got %b", + part); + pass = 1'b0; + end + part = wavar[1][1:1'bx]; // Undefined 2nd + if (part !== 2'bxx) begin + $display("Failed undefined 2nd part select of a wire array word, got %b", + part); + pass = 1'b0; + end + part = wavar[1][1'bz:1]; // High-Z 1st + if (part !== 2'bxx) begin + $display("Failed high-Z 1st part select of a wire array word, got %b", + part); + pass = 1'b0; + end + part = wavar[1][1:1'bz]; // High-Z 2nd + if (part !== 2'bxx) begin + $display("Failed high-Z 2nd part select of a wire array word, got %b", + part); + pass = 1'b0; + end +`endif + + // Check a wire array word with range [1:4]. +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + part = wavar2[1][-1:0]; // After all + if (part !== 2'bxx) begin + $display("Failed after part select of a wire array word (2), got %b", + part); + pass = 1'b0; + end + part = wavar2[1][0:1]; // Partial after + if (part !== 2'bx0) begin + $display("Failed partial after part select of a wire array word (2),", + " got %b", part); + pass = 1'b0; + end + part = wavar2[1][5:6]; // Before all + if (part !== 2'bxx) begin + $display("Failed before part select of a wire array word (2), got %b", + part); + pass = 1'b0; + end + part = wavar2[1][4:5]; // Partial before + if (part !== 2'b1x) begin + $display("Failed partial before part select of a wire array word (2),", + " got %b", part); + pass = 1'b0; + end + part = wavar2[1][1'bx:1]; // Undefined 1st + if (part !== 2'bxx) begin + $display("Failed undefined 1st part select of a wire array word (2),", + " got %b", part); + pass = 1'b0; + end + part = wavar2[1][1:1'bx]; // Undefined 2nd + if (part !== 2'bxx) begin + $display("Failed undefined 2nd part select of a wire array word (2),", + " got %b", part); + pass = 1'b0; + end + part = wavar2[1][1'bz:1]; // High-Z 1st + if (part !== 2'bxx) begin + $display("Failed high-Z 1st part select of a wire array word (2), got %b", + part); + pass = 1'b0; + end + part = wavar2[1][1:1'bz]; // High-Z 2nd + if (part !== 2'bxx) begin + $display("Failed high-Z 2nd part select of a wire array word (2), got %b", + part); + pass = 1'b0; + end +`endif + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/select.v b/ivtest/ivltests/select.v new file mode 100644 index 000000000..c9f5f7585 --- /dev/null +++ b/ivtest/ivltests/select.v @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test the select of a memory word in a continuous assignment. + */ + +module main; + + reg [1:0] a [3:0]; + reg [1:0] s = 0; + + wire [1:0] b = a[s]; + + initial begin + a[0] = 3; + a[1] = 2; + a[2] = 1; + a[3] = 0; + end + + initial begin + #1 if (b !== 3) begin + $display("FAILED -- s=%b, b=%b", s, b); + $finish; + end + + s = 1; + + #1 if (b !== 2) begin + $display("FAILED -- s=%b, b=%b", s, b); + $finish; + end + + s = 2; + + #1 if (b !== 1) begin + $display("FAILED -- s=%b, b=%b", s, b); + $finish; + end + + s = 3; + + #1 if (b !== 0) begin + $display("FAILED -- s=%b, b=%b", s, b); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/select2.v b/ivtest/ivltests/select2.v new file mode 100644 index 000000000..046874a0c --- /dev/null +++ b/ivtest/ivltests/select2.v @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test the select of a bit from a vector. + */ + +module main; + + reg [3:0] a = 4'b0110; + reg [1:0] s = 0; + + wire b = a[s]; + + initial begin + #1 if (b !== 0) begin + $display("FAILED -- a=%b, s=%b, b=%b", a, s, b); + $finish; + end + + s = 1; + + #1 if (b !== 1) begin + $display("FAILED -- a=%b, s=%b, b=%b", a, s, b); + $finish; + end + + s = 2; + + #1 if (b !== 1) begin + $display("FAILED -- a=%b, s=%b, b=%b", a, s, b); + $finish; + end + + s = 3; + + #1 if (b !== 0) begin + $display("FAILED -- a=%b, s=%b, b=%b", a, s, b); + $finish; + end + + s = 2'bxx; + #1 if (b !== 1'bx) begin + $display("FAILED -- a=%b, s=%b, b=%b", a, s, b); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/select3.v b/ivtest/ivltests/select3.v new file mode 100644 index 000000000..0387bdbb0 --- /dev/null +++ b/ivtest/ivltests/select3.v @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test the select of a bit from a parameter. + */ +module test; + + reg [4:0] a; + wire o; + + RAM dut(o, a[3:0]); + defparam test.dut.INIT = 16'h55aa; + + initial begin + for (a = 0 ; a[4] == 0 ; a = a + 1) begin + #1 $display("dut[%h] = %b", a, o); + end + end + +endmodule // test + +module RAM (O, A); + + parameter INIT = 16'h0000; + + output O; + + input [3:0] A; + + reg mem [15:0]; + reg [4:0] count; + wire [3:0] adr; + + buf (O, mem[A]); + + initial + begin + for (count = 0; count < 16; count = count + 1) + mem[count] <= INIT[count]; + end + +endmodule diff --git a/ivtest/ivltests/select4.v b/ivtest/ivltests/select4.v new file mode 100644 index 000000000..97d7fd252 --- /dev/null +++ b/ivtest/ivltests/select4.v @@ -0,0 +1,23 @@ +/* + * part select in continuous assignment. + */ + +`timescale 1ns/1ns + +module main; + reg [3:0] src; + wire foo = src[3:1] == 3'b101; + + integer idx; + initial + begin + for (idx = 0 ; idx < 16 ; idx = idx+1) begin + src = idx; + #1 if (foo !== (src[3:1] == 3'b101)) begin + $display("FAILED -- src=%b, foo=%b", src, foo); + $finish; + end + end + $display("PASSED"); + end // initial begin +endmodule diff --git a/ivtest/ivltests/select5.v b/ivtest/ivltests/select5.v new file mode 100644 index 000000000..5963b3301 --- /dev/null +++ b/ivtest/ivltests/select5.v @@ -0,0 +1,56 @@ +/* + * This program demonstrates non-constant part selects + * applied to a signal value. + */ +module main; + + wire [31:0] foo = 32'h76543210; + + reg [3:0] tmp; + reg [3:0] idx; + + initial begin + #1 /* Wait for initial assignments to settle. */ ; + + if (foo[0 +: 4] !== 4'h0) begin + $display("FAILED -- %b !== 0", foo[0 +: 4]); + $finish; + end + + if (foo[4 +: 4] !== 4'h1) begin + $display("FAILED -- %b !== 1", foo[4 +: 4]); + $finish; + end + + if (foo[8 +: 4] !== 4'h2) begin + $display("FAILED -- %b !== 2", foo[8 +: 4]); + $finish; + end + + if (foo[12+: 4] !== 4'h3) begin + $display("FAILED -- %b !== 3", foo[12 +: 4]); + $finish; + end + + for (idx = 0 ; idx < 8 ; idx = idx + 1) begin + tmp = foo[(idx*4) +: 4]; + if (tmp !== idx) begin + $display("FAILED -- %b !== %b", idx, tmp); + $finish; + end + + end + + for (idx = 0 ; idx < 8 ; idx = idx + 1) begin + tmp = foo[(idx*4+3) -: 4]; + if (tmp !== idx) begin + $display("FAILED -- %b !== %b", idx, tmp); + $finish; + end + + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/select6.v b/ivtest/ivltests/select6.v new file mode 100644 index 000000000..2c332940b --- /dev/null +++ b/ivtest/ivltests/select6.v @@ -0,0 +1,47 @@ +module main; + + reg [7:0] mem [0:1]; + + initial begin + mem[0] = 8'ha5; + mem[1] = 8'hf0; + + if (mem[0] !== 8'ha5) begin + $display("FAILED"); + $finish; + end + + if (mem[1] !== 8'hf0) begin + $display("FAILED"); + $finish; + end + + if (mem[0][4+:4] !== 5'ha) begin + $display("FAILED"); + $finish; + end + + if (mem[1][4+:4] !== 5'hf) begin + $display("FAILED"); + $finish; + end + + mem[0][4 +: 4] <= 4'hc; + + #1 if (mem[0] !== 8'hc5) begin + $display("FAILED"); + $finish; + end + + mem[1][4 +: 4] <= 4'h3; + + #1 if (mem[1] !== 8'h30) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/select7.v b/ivtest/ivltests/select7.v new file mode 100644 index 000000000..d7a968214 --- /dev/null +++ b/ivtest/ivltests/select7.v @@ -0,0 +1,47 @@ +module main; + + reg [7:0] mem [0:1]; + + initial begin + mem[0] = 8'ha5; + mem[1] = 8'hf0; + + if (mem[0] !== 8'ha5) begin + $display("FAILED"); + $finish; + end + + if (mem[1] !== 8'hf0) begin + $display("FAILED"); + $finish; + end + + if (mem[0][4+:4] !== 5'ha) begin + $display("FAILED"); + $finish; + end + + if (mem[1][4+:4] !== 5'hf) begin + $display("FAILED"); + $finish; + end + + mem[0][4 +: 4] = 4'hc; + + #1 if (mem[0] !== 8'hc5) begin + $display("FAILED"); + $finish; + end + + mem[1][4 +: 4] = 4'h3; + + #1 if (mem[1] !== 8'h30) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/select8.v b/ivtest/ivltests/select8.v new file mode 100644 index 000000000..b6f9c6afa --- /dev/null +++ b/ivtest/ivltests/select8.v @@ -0,0 +1,49 @@ +module main; + + reg [7:0] mem [0:1]; + integer off; + + initial begin + mem[0] = 8'ha5; + mem[1] = 8'hf0; + off = 4; + + if (mem[0] !== 8'ha5) begin + $display("FAILED"); + $finish; + end + + if (mem[1] !== 8'hf0) begin + $display("FAILED"); + $finish; + end + + if (mem[0][off+:4] !== 5'ha) begin + $display("FAILED"); + $finish; + end + + if (mem[1][off+:4] !== 5'hf) begin + $display("FAILED"); + $finish; + end + + mem[0][off +: 4] = 4'hc; + + #1 if (mem[0] !== 8'hc5) begin + $display("FAILED"); + $finish; + end + + mem[1][off +: 4] = 4'h3; + + #1 if (mem[1] !== 8'h30) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/select_padding.v b/ivtest/ivltests/select_padding.v new file mode 100644 index 000000000..37415535b --- /dev/null +++ b/ivtest/ivltests/select_padding.v @@ -0,0 +1,45 @@ +module top; + reg pass; + reg [7:0] in; + reg [1:0] res; + integer lp; + + initial begin + pass = 1'b1; + in = 8'b11100100; + lp = 3; + + // lp[1:0] is being sign extended and that fails when the value mod 4 + // is either 2 or 3! A bit/part select is always unsigned unless we use + // The $signed function to cast it to signed! + res = in[lp[1:0]*2 +: 2]; + if (res !== 2'b11) begin + $display("Failed expected 2'b11, got %b (%b:%d)", res, in, lp[1:0]*2); + pass = 1'b0; + end + + // This should give -2 for the index. + res = in[$signed(lp[1:0])*2 +: 2]; + if (res !== 2'bxx) begin + $display("Failed expected 2'bxx, got %b (%b:%d)", res, in, + $signed(lp[1:0])*2); + pass = 1'b0; + end + + lp = 6; + // The same as above, but not at the start of the signal. + res = in[lp[2:1]*2 +: 2]; + if (res !== 2'b11) begin + $display("Failed expected 2'b11, got %b (%b:%d)", res, in, lp[2:1]*2); + pass = 1'b0; + end + res = in[$signed(lp[2:1])*2 +: 2]; + if (res !== 2'bxx) begin + $display("Failed expected 2'bxx, got %b (%b:%d)", res, in, + $signed(lp[2:1])*2); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/sf1289.v b/ivtest/ivltests/sf1289.v new file mode 100644 index 000000000..cc8512a30 --- /dev/null +++ b/ivtest/ivltests/sf1289.v @@ -0,0 +1,31 @@ +module test1(); // bad + initial begin + reg a; + for (int i=0;i<1;i++) a=1; + end +endmodule + + +module test2(); // bad + initial begin : block_name + for (int i=0;i<1;i++) ; + end +endmodule + +module test3(); // bad + reg a [1:0]; + initial begin : block_name + foreach (a[i]) ; + end +endmodule + + +module test4(); // ok + initial begin + for (int i=0;i<1;i++) ; + end +endmodule + +module stub; + initial #100 $display("PASSED"); +endmodule // stub diff --git a/ivtest/ivltests/sf_countbits.v b/ivtest/ivltests/sf_countbits.v new file mode 100644 index 000000000..ac924a954 --- /dev/null +++ b/ivtest/ivltests/sf_countbits.v @@ -0,0 +1,70 @@ +module top; + reg pass; + integer result; + reg [3:0] expr; + reg bval; + + initial begin + pass = 1'b1; + + result = $countbits(1'bx, 1'bx); + if (result != 1) begin + $display("FAILED: for 1'bx/x expected a count of 1, got %d", result); + pass = 1'b0; + end + + result = $countbits(2'bxx, 1'bx); + if (result != 2) begin + $display("FAILED: for 2'bxx/x expected a count of 2, got %d", result); + pass = 1'b0; + end + + result = $countbits(2'bxz, 1'bz, 1'bx); + if (result != 2) begin + $display("FAILED: for 2'bxz/zx expected a count of 2, got %d", result); + pass = 1'b0; + end + + result = $countbits(4'b01zx, 1'bz, 1'bx); + if (result != 2) begin + $display("FAILED: for 4'b01zx/zx expected a count of 2, got %d", result); + pass = 1'b0; + end + + result = $countbits(4'b01zx, 1'b0, 1'b1); + if (result != 2) begin + $display("FAILED: for 4'b01zx/01 expected a count of 2, got %d", result); + pass = 1'b0; + end + + bval = 1'b0; + expr = 4'b1001; + result = $countbits(expr, bval); + if (result != 2) begin + $display("FAILED: for 4'b1001/0 expected a count of 2, got %d", result); + pass = 1'b0; + end + + bval = 1'b1; + result = $countbits(expr, bval); + if (result != 2) begin + $display("FAILED: for 4'b1001/1 expected a count of 2, got %d", result); + pass = 1'b0; + end + + result = $countbits(34'bzx00000000000000000000000000000000, 1'bz, 1'bx); + if (result != 2) begin + $display("FAILED: for 34'zx00000000000000000000000000000000/zx expected a count of 2, got %d", result); + pass = 1'b0; + end + + result = $countbits(34'bzxxz000000xz000000xz000000xz000000, 1'bz, 1'bx); + if (result != 10) begin + $display("FAILED: for 34'zxxz000000xz000000xz000000xz000000/zx expected a count of 10, got %d", result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/sf_countbits_fail.v b/ivtest/ivltests/sf_countbits_fail.v new file mode 100644 index 000000000..21f52d507 --- /dev/null +++ b/ivtest/ivltests/sf_countbits_fail.v @@ -0,0 +1,15 @@ +module top; + integer result; + + initial begin + + result = $countbits(top); + result = $countbits("a string"); + result = $countbits(1'bx); + result = $countbits("a string", 1'bx); + result = $countbits(1'bx, "a string"); + result = $countbits(1'bx, 1'bx, "a string"); + + end + +endmodule diff --git a/ivtest/ivltests/sf_countones.v b/ivtest/ivltests/sf_countones.v new file mode 100644 index 000000000..15ff5e490 --- /dev/null +++ b/ivtest/ivltests/sf_countones.v @@ -0,0 +1,55 @@ +module top; + reg pass; + integer result; + reg [3:0] expr; + + initial begin + pass = 1'b1; + + result = $countones(1'b0); + if (result != 0) begin + $display("FAILED: for 1'b0 expected a count of 0, got %d", result); + pass = 1'b0; + end + + result = $countones(1'b1); + if (result != 1) begin + $display("FAILED: for 1'b1 expected a count of 1, got %d", result); + pass = 1'b0; + end + + result = $countones(2'b01); + if (result != 1) begin + $display("FAILED: for 2'b01 expected a count of 1, got %d", result); + pass = 1'b0; + end + + result = $countones(4'b0111); + if (result != 3) begin + $display("FAILED: for 4'b0111 expected a count of 3, got %d", result); + pass = 1'b0; + end + + expr = 4'b1100; + result = $countones(expr); + if (result != 2) begin + $display("FAILED: for 4'b1100 expected a count of 2, got %d", result); + pass = 1'b0; + end + + result = $countones(34'b1100000000000000000000000000000001); + if (result != 3) begin + $display("FAILED: for 34'1100000000000000000000000000000001 expected a count of 3, got %d", result); + pass = 1'b0; + end + + result = $countones(34'b1111000000110000001100000011000000); + if (result != 10) begin + $display("FAILED: for 34'1111000000110000001100000011000000 expected a count of 10, got %d", result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/sf_countones_fail.v b/ivtest/ivltests/sf_countones_fail.v new file mode 100644 index 000000000..50b04eb37 --- /dev/null +++ b/ivtest/ivltests/sf_countones_fail.v @@ -0,0 +1,12 @@ +module top; + integer result; + + initial begin + + result = $countones(top); + result = $countones("a string"); + result = $countones(4'b001, 1'b0); + + end + +endmodule diff --git a/ivtest/ivltests/sf_isunknown.v b/ivtest/ivltests/sf_isunknown.v new file mode 100644 index 000000000..c416c9dd3 --- /dev/null +++ b/ivtest/ivltests/sf_isunknown.v @@ -0,0 +1,61 @@ +module top; + reg pass; + reg result; + reg [3:0] expr; + + initial begin + pass = 1'b1; + + result = $isunknown(1'b0); + if (result != 0) begin + $display("FAILED: for 1'b0 expected 0, got %b", result); + pass = 1'b0; + end + + result = $isunknown(1'b1); + if (result != 0) begin + $display("FAILED: for 1'b1 expected 0, got %b", result); + pass = 1'b0; + end + + result = $isunknown(2'b01); + if (result != 0) begin + $display("FAILED: for 2'b01 expected 0, got %b", result); + pass = 1'b0; + end + + result = $isunknown(4'b0x11); + if (result != 1) begin + $display("FAILED: for 4'b0x11 expected 1, got %b", result); + pass = 1'b0; + end + + expr = 4'b110x; + result = $isunknown(expr); + if (result != 1) begin + $display("FAILED: for 4'b110x expected 1, got %b", result); + pass = 1'b0; + end + + result = $isunknown(34'bx100000000000000000000000000000001); + if (result != 1) begin + $display("FAILED: for 34'x100000000000000000000000000000001 expected 1, got %b", result); + pass = 1'b0; + end + + result = $isunknown(34'b100000000000000000000000000000000x); + if (result != 1) begin + $display("FAILED: for 34'100000000000000000000000000000000x expected 1, got %b", result); + pass = 1'b0; + end + + result = $isunknown(34'b1000000000000000000000000000000000); + if (result != 0) begin + $display("FAILED: for 34'1000000000000000000000000000000000 expected 0, got %b", result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/sf_isunknown_fail.v b/ivtest/ivltests/sf_isunknown_fail.v new file mode 100644 index 000000000..319b18c39 --- /dev/null +++ b/ivtest/ivltests/sf_isunknown_fail.v @@ -0,0 +1,12 @@ +module top; + reg result; + + initial begin + + result = $isunknown(top); + result = $isunknown("a string"); + result = $isunknown(4'b001, 1'b0); + + end + +endmodule diff --git a/ivtest/ivltests/sf_onehot.v b/ivtest/ivltests/sf_onehot.v new file mode 100644 index 000000000..3bae68b74 --- /dev/null +++ b/ivtest/ivltests/sf_onehot.v @@ -0,0 +1,55 @@ +module top; + reg pass; + reg result; + reg [3:0] expr; + + initial begin + pass = 1'b1; + + result = $onehot(1'b0); + if (result != 0) begin + $display("FAILED: for 1'b0 expected 0, got %b", result); + pass = 1'b0; + end + + result = $onehot(1'b1); + if (result != 1) begin + $display("FAILED: for 1'b1 expected 1, got %b", result); + pass = 1'b0; + end + + result = $onehot(2'b01); + if (result != 1) begin + $display("FAILED: for 2'b01 expected 1, got %b", result); + pass = 1'b0; + end + + result = $onehot(4'b0x11); + if (result != 0) begin + $display("FAILED: for 4'b0x11 expected 0, got %b", result); + pass = 1'b0; + end + + expr = 4'b1100; + result = $onehot(expr); + if (result != 0) begin + $display("FAILED: for 4'b1100 expected 0, got %b", result); + pass = 1'b0; + end + + result = $onehot(34'b1100000000000000000000000000000001); + if (result != 0) begin + $display("FAILED: for 34'1100000000000000000000000000000001 expected 0, got %b", result); + pass = 1'b0; + end + + result = $onehot(34'b1000000000000000000000000000000000); + if (result != 1) begin + $display("FAILED: for 34'1000000000000000000000000000000000 expected 1, got %b", result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/sf_onehot0.v b/ivtest/ivltests/sf_onehot0.v new file mode 100644 index 000000000..dc73e3244 --- /dev/null +++ b/ivtest/ivltests/sf_onehot0.v @@ -0,0 +1,55 @@ +module top; + reg pass; + reg result; + reg [3:0] expr; + + initial begin + pass = 1'b1; + + result = $onehot0(1'b0); + if (result != 1) begin + $display("FAILED: for 1'b0 expected 1, got %b", result); + pass = 1'b0; + end + + result = $onehot0(1'b1); + if (result != 1) begin + $display("FAILED: for 1'b1 expected 1, got %b", result); + pass = 1'b0; + end + + result = $onehot0(2'b01); + if (result != 1) begin + $display("FAILED: for 2'b01 expected 1, got %b", result); + pass = 1'b0; + end + + result = $onehot0(4'b0x11); + if (result != 0) begin + $display("FAILED: for 4'b0x11 expected 0, got %b", result); + pass = 1'b0; + end + + expr = 4'b1100; + result = $onehot0(expr); + if (result != 0) begin + $display("FAILED: for 4'b1100 expected 0, got %b", result); + pass = 1'b0; + end + + result = $onehot0(34'b1100000000000000000000000000000001); + if (result != 0) begin + $display("FAILED: for 34'1100000000000000000000000000000001 expected 0, got %b", result); + pass = 1'b0; + end + + result = $onehot0(34'b1000000000000000000000000000000000); + if (result != 1) begin + $display("FAILED: for 34'1000000000000000000000000000000000 expected 1, got %b", result); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/sf_onehot0_fail.v b/ivtest/ivltests/sf_onehot0_fail.v new file mode 100644 index 000000000..f04012fe7 --- /dev/null +++ b/ivtest/ivltests/sf_onehot0_fail.v @@ -0,0 +1,12 @@ +module top; + reg result; + + initial begin + + result = $onehot0(top); + result = $onehot0("a string"); + result = $onehot0(4'b001, 1'b0); + + end + +endmodule diff --git a/ivtest/ivltests/sf_onehot_fail.v b/ivtest/ivltests/sf_onehot_fail.v new file mode 100644 index 000000000..d148015c3 --- /dev/null +++ b/ivtest/ivltests/sf_onehot_fail.v @@ -0,0 +1,12 @@ +module top; + reg result; + + initial begin + + result = $onehot(top); + result = $onehot("a string"); + result = $onehot(4'b001, 1'b0); + + end + +endmodule diff --git a/ivtest/ivltests/sformatf.v b/ivtest/ivltests/sformatf.v new file mode 100644 index 000000000..b5c5a1006 --- /dev/null +++ b/ivtest/ivltests/sformatf.v @@ -0,0 +1,69 @@ +// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +// Test for $sformatf system function. + +module ivl_sformatf_test; +wire test_net; +assign (pull1, strong0) test_net = 1'b1; + +struct packed { + logic [15:0] high; + logic [15:0] low; +} word; + +initial begin + string f; + word = 32'b0101_0101_0101_0101_0101_0101_0101_0101; + + // Test constant values + // Integers + f = $sformatf("sformatf test 1: %b %d %o %x", 8'd120, -12, 331, 120, 97); + if(f != "sformatf test 1: 01111000 -12 00000000513 00000078 97") begin + $display(f); + $display("FAILED 1"); + $finish(); + end + + // Floats + f = $sformatf("sformatf test 2: %e %f %g", 123.45, 100e12, 100e12); + if(f != "sformatf test 2: 1.234500e+02 100000000000000.000000 1e+14") begin + $display(f); + $display("FAILED 2"); + $finish(); + end + + // Strings + f = $sformatf("sformatf test 3: %s %c", "'string test'", 97); + if(f != "sformatf test 3: 'string test' a") begin + $display(f); + $display("FAILED 3"); + $finish(); + end + + // Other stuff + f = $sformatf("sformatf test 4: %t %v %u %z", 120s, test_net, word, word); + if(f != "sformatf test 4: 120 Pu1 UUUU UUUU") begin + $display(f); + $display("FAILED 4"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/shellho1.v b/ivtest/ivltests/shellho1.v new file mode 100644 index 000000000..2b84028b4 --- /dev/null +++ b/ivtest/ivltests/shellho1.v @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2000 Mark Schellhorn + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/**************************************************************************** + + The following code illustrates an apparent bug in the VCS v5.2 simulator. + The check for whether or not the memory[0] array element was set correctly + fails; yet the $display statement immediately after the check shows the + memory[0] element actually has been set correctly. + + I've noted that if the $display and the check are reversed, the $display + is incorrect but the check passes. + + This appears to be a problem with the simulator's internal scheduler. + +***************************************************************************/ + + +module bug_test; + +reg [1:0] temp; + +initial begin + + /********** First test. */ + + $display("Running first test.\n"); + + // Try setting memory array in other module using hierarchical + // references & concatenation. + temp = 2'h3; + top.memory.memory[0] = {2'h0,temp}; + top.memory.memory[0] = {top.memory.memory[0],temp}; + + // Check that setting was made correctly + if (top.memory.memory[0] != {2{temp}}) begin + $display("ERROR! top.memory.memory[0] failed to get"); + $display("set correctly!"); + end else begin + $display("PASS! top.memory.memory[0] set correctly."); + end + + // Display the value that was checked + $display("top.memory.memory[0] = %h",top.memory.memory[0]); + + + + /********** Second test. */ + + $display("\nRunning second test.\n"); + + // Try setting memory array in other module using hierarchical + // references & concatenation. + temp = 2'h3; + top.memory.memory[1] = {2'h0,temp}; + top.memory.memory[1] = {top.memory.memory[1],temp}; + + // Display the value that will be checked + $display("top.memory.memory[1] = %h",top.memory.memory[1]); + + // Check that setting was made correctly + if (top.memory.memory[1] != {2{temp}}) begin + $display("ERROR! top.memory.memory[1] failed to get"); + $display("set correctly!"); + end else begin + $display("PASS! top.memory.memory[1] set correctly."); + end + + // Display the value that was checked + $display("top.memory.memory[1] = %h",top.memory.memory[1]); + + $finish(0); + +end + +endmodule + +// Module containing a memory array +module memory; + +reg [3:0] memory [0:1]; + +endmodule + +// Module to instantiate test and memory modules +module top; + + bug_test bug_test(); + memory memory(); + +endmodule diff --git a/ivtest/ivltests/shift1.v b/ivtest/ivltests/shift1.v new file mode 100644 index 000000000..85d6bf0be --- /dev/null +++ b/ivtest/ivltests/shift1.v @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2001 Stephen Rowland + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module dummy; + +reg [7:0] decode_vec; +wire [7:0] data1; +wire [7:0] data2; + +// icarus cant handle this statement +assign data1 = (decode_vec[8'h02>>1] ) ? 8'h55 : 8'h00; + +assign data2 = (decode_vec[8'h01 ] ) ? 8'h55 : 8'h00; + +initial +begin +#0; +$monitor("%h %h %h", decode_vec, data1, data2); +decode_vec = 8'h02; +#10; +decode_vec = 8'h80; +#10; +decode_vec = 8'h02; +#10; +$finish(0); +end + +endmodule diff --git a/ivtest/ivltests/shift2.v b/ivtest/ivltests/shift2.v new file mode 100644 index 000000000..8db2d7e2f --- /dev/null +++ b/ivtest/ivltests/shift2.v @@ -0,0 +1,26 @@ +module main; + + reg [7:0] xu; + reg signed [7:0] xs; + + initial begin + xu = 8'b1100_0000; + xs = 8'b1100_0000; + + xu = xu >>> 3; + xs = xs >>> 3; + + if (xu !== 8'b0001_1000) begin + $display("FAILED -- Unsigned >>> failed. xu=%b", xu); + $finish; + end + + if (xs !== 8'b1111_1000) begin + $display("FAILED -- Signed >>> failed. xs=%b", xs); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/shift3.v b/ivtest/ivltests/shift3.v new file mode 100644 index 000000000..7e0d51891 --- /dev/null +++ b/ivtest/ivltests/shift3.v @@ -0,0 +1,29 @@ +module main; + + reg [7:0] xu; + reg signed [7:0] xs; + + initial begin + xu = 8'b1100_0000; + xs = 8'b1100_0000; + + xu = xs >>> 3; + xs = xu >>> 3; + + // IEEE1364-2005 Secion 5.5.1 Rules for Expression Types + // "Expression type depends only on the operands. It does not depend + // on the left-hand side (if any)." + if (xu !== 8'b1111_1000) begin + $display("FAILED -- xu = xs >>> 3 failed. xu=%b", xu); + $finish; + end + + if (xs !== 8'b0001_1111) begin + $display("FAILED -- xs = xu >>> 3 failed. xs=%b", xs); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/shift4.v b/ivtest/ivltests/shift4.v new file mode 100644 index 000000000..a74806ffe --- /dev/null +++ b/ivtest/ivltests/shift4.v @@ -0,0 +1,45 @@ +module main; + reg signed [7:0] a; + reg [7:0] b; + initial begin + // Make sure the arithmetic right shift sign extends + $display("simple arithmetic right shift"); + a = 8'b11001001; + $display("before: a = %b", a); + a = a>>>1; + $display("after: a = %b", a); + if (a !== 8'b11100100) begin + $display("FAILED"); + $finish; + end + + // The concatenation operator is always unsigned, so + // it must turn off sign extension. + $display("concatenated arithmetic right shift"); + a = 8'b11001001; + b = 0; + $display("before: a = %b", a); + {a,b} = {a,b}>>>1; + $display("after: a = %b", a); + if (a !== 8'b01100100) begin + $display("FAILED"); + $finish; + end + + + // The concatenation operator is always unsigned, but + // we can turn on signed behavior with $signed. + $display("concatenated arithmetic right shift with $signed"); + a = 8'b11001001; + b = 0; + $display("before: a = %b", a); + {a,b} = $signed({a,b})>>>1; + $display("after: a = %b", a); + if (a !== 8'b11100100) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/shift5.v b/ivtest/ivltests/shift5.v new file mode 100644 index 000000000..3cf2cb086 --- /dev/null +++ b/ivtest/ivltests/shift5.v @@ -0,0 +1,31 @@ +/* + * This example pulled from comp.lang.verilog. It was written + * by Russell Fredrickson to test + * arithmetic shift for other compilers, and caught mine. + */ + +module ArithmeticShiftTest; + reg signed [31:0] in; + reg [5:0] shift; + reg signed [31:0] out; + + //calculate arithmetic barrel shift right + always@(*) out = in >>> shift; + + initial begin + //set up inputs for always block + in = 32'sh80000000;//set to highest value negative number(-2147483648) + shift = 6'd32; //shift the entire width of the word + + #1; //allow time for inputs to propagate + + //check output + if(out === (32'sh80000000 >>> 6'd32)) begin + $display("PASS: 32'sh80000000 >>> 6'd32 = 0x%h", out); + end + else begin + $display("FAIL: 32'sh80000000 >>> 6'd32 != 0x%h,", + (32'sh80000000 >>> 6'd32), " actual = 0x%h.", out); + end + end // initial begin +endmodule // ArithmeticShiftTest diff --git a/ivtest/ivltests/shift_pad.v b/ivtest/ivltests/shift_pad.v new file mode 100644 index 000000000..64969050f --- /dev/null +++ b/ivtest/ivltests/shift_pad.v @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg [1:0] out; + reg in; + + initial begin + in = 1; + out = in << 1; + if (out !== 2'b10) begin + $display("FAILED (1) -- out == %b", out); + $finish; + end + + out <= in << 1; + + #1 if (out !== 2'b10) begin + $display("FAILED (2) -- out == %b", out); + $finish; + end + + $display("PASSED"); + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/shiftl.v b/ivtest/ivltests/shiftl.v new file mode 100644 index 000000000..11d9260d6 --- /dev/null +++ b/ivtest/ivltests/shiftl.v @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This tests the primitive synthesis of a simple left shift. + */ + +module test (clk,c,a,b); +input clk; +input a, b; +output [1:0] c; +reg [1:0] c; + +(* ivl_synthesis_on *) +always @(posedge clk) + c <= (a << 1) | b; + +endmodule + +module main; + + reg a, b, clk; + wire [1:0] c; + test dut (.clk(clk), .c(c), .a(a), .b(b)); + + integer x; + (* ivl_synthesis_off *) + initial begin + clk = 0; + for (x = 0 ; x < 4 ; x = x+1) begin + a = x[1]; + b = x[0]; + #1 clk = 1; + #1 clk = 0; + if (c !== x[1:0]) begin + $display("FAILED == x=%0d (ab=%b%b), c=%b", x, a, b, c); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/signal_init_assign.vhd b/ivtest/ivltests/signal_init_assign.vhd new file mode 100644 index 000000000..6bb589c22 --- /dev/null +++ b/ivtest/ivltests/signal_init_assign.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + +-- This is a simple test of the initialization assignment for +-- signals. We also let a generic into the test. + +entity test is + generic (PARM : std_logic := '0'); + port (clk : in std_logic; + src : in std_logic; + dst : out std_logic); +end test; + +architecture operation of test is + signal tmp : std_logic := PARM; +begin + step: process (clk) + begin -- process step + if clk'event and clk = '1' then -- rising clock edge + dst <= tmp xor src; + end if; + end process step; +end operation; diff --git a/ivtest/ivltests/signed1.v b/ivtest/ivltests/signed1.v new file mode 100644 index 000000000..b208c6480 --- /dev/null +++ b/ivtest/ivltests/signed1.v @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program tests that signed registers are compared using signed + * arithmetic. + */ +module main; + + reg signed [7:0] vala; + reg signed [7:0] valb; + reg [7:0] valc; + + initial begin + vala = -1; + valb = +1; + valc = -1; + + if (vala >= valb) begin + $display("FAILED -- vala(%b) is >= valb(%b)", vala, valb); + $finish; + end + + if (vala > valb) begin + $display("FAILED -- vala(%b) is > valb(%b)", vala, valb); + $finish; + end + + if (valb <= vala) begin + $display("FAILED -- valb(%b) is <= vala(%b)", valb, vala); + $finish; + end + + if (valb < vala) begin + $display("FAILED -- valb(%b) is < vala(%b)", valb, vala); + $finish; + end + + if (valc <= valb) begin + $display("FAILED -- valc(%b) is not > valb(%b)", valc, valb); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/signed10.v b/ivtest/ivltests/signed10.v new file mode 100644 index 000000000..9d2dce00f --- /dev/null +++ b/ivtest/ivltests/signed10.v @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module displaysigned(); + +reg signed [7:0] foo; +reg [7:0] bar; + +initial begin + foo = -8'sd2; + bar = foo; + + $display("foo=%0d bar=%0d $signed(bar)=%0d", + foo, bar, $signed(bar)); + + $finish(0); +end + +endmodule diff --git a/ivtest/ivltests/signed11.v b/ivtest/ivltests/signed11.v new file mode 100644 index 000000000..ff1889006 --- /dev/null +++ b/ivtest/ivltests/signed11.v @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2005 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version.will need a Picture Elements Binary Software + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program catches some glitches in the MUXZ that Icarus Verilog + * uses to implement the ?: in structural cases. + */ +module main; + + parameter FOO = 0; + + initial begin + if ((FOO < -255) || (FOO > 255)) begin + $display("FAILED -- foo=%d does not fall in the range?", FOO); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/signed12.v b/ivtest/ivltests/signed12.v new file mode 100644 index 000000000..466a17635 --- /dev/null +++ b/ivtest/ivltests/signed12.v @@ -0,0 +1,10 @@ +module top; + // Does this have to be signed? + wire signed [7:0] out; + + // Either of these will not expand correctly. +// assign out = 'sh1f; + assign out = 5'sh1f; + + initial #1 $displayb(out); +endmodule diff --git a/ivtest/ivltests/signed13.v b/ivtest/ivltests/signed13.v new file mode 100644 index 000000000..751dc45f6 --- /dev/null +++ b/ivtest/ivltests/signed13.v @@ -0,0 +1,22 @@ +`begin_keywords "1364-2005" +module top; + reg pass; + reg [3:0] var; + integer lp; + + initial begin + pass = 1'b1; + for (lp = 0; lp < 16; lp = lp + 1) begin + var = lp; + // This should bit extend var as unsigned and then + // convert it into a signed value. + if (lp !== $signed(var+5'b0)) begin + $display("FAILED: expected %2d, got %2d", lp, $signed(var+5'b0)); + pass = 1'b0; + end + end + + if (pass) $display("PASSED"); + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/signed2.v b/ivtest/ivltests/signed2.v new file mode 100644 index 000000000..e3546db85 --- /dev/null +++ b/ivtest/ivltests/signed2.v @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2000 Steve Wilson (stevew@home.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Verify signed constant assignment to an integer. + */ +module test; + +integer I0,I1; +reg [15:0] R0,R1; +reg [3:0] error; + +initial + begin + error = 0; + I0 = -4'd12; + I1 = -32'd12; + if(I0 !== 32'hfffffff4) + begin + $display("FAILED - negative decimal assignment failed. I0 s/b fffffff4, is %h", + I0); + error =1; + end + if(I1 !== 32'hfffffff4) + begin + $display("FAILED - negative decimal assignment failed. I1 s/b fffffff4, is %h", + I1); + error = 1; + end + if(error === 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/signed3.v b/ivtest/ivltests/signed3.v new file mode 100644 index 000000000..a2b7a38d9 --- /dev/null +++ b/ivtest/ivltests/signed3.v @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2000 Steve Wilson (stevew@home.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Verify signed constant assignment to an reg. + */ +module test; + +integer I0,I1; +reg [15:0] R0,R1; +reg [3:0] error; + +initial + begin + R0 = -4'd12; + R1 = -16'd12; + error = 0; + if(R0 !== 16'hfff4) + begin + $display("FAILED - negative decimal assignment failed. R0 s/b fff4, is %h", + R0); + error = 1; + end + + if(R1 !== 16'hfff4) + begin + $display("FAILED - negative decimal assignment failed. R1 s/b fff4, is %h", + R1); + error = 1; + end + if(error === 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/signed4.v b/ivtest/ivltests/signed4.v new file mode 100644 index 000000000..e61f843d6 --- /dev/null +++ b/ivtest/ivltests/signed4.v @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2001 Steve Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* Check that display prints the right signed value. */ + +module signed1(); + + reg [7:0] x; + reg signed [7:0] y; + + initial + begin + x = 8'b0000_0011; + y = 8'b1111_1101; + + $display("x = %0d (should be 3)",x); + $display("y = %0d (should be -3)",y); + + x = y; + $display("x = %0d (should be 253)",x); + + + end + +endmodule diff --git a/ivtest/ivltests/signed5.v b/ivtest/ivltests/signed5.v new file mode 100644 index 000000000..95db0d466 --- /dev/null +++ b/ivtest/ivltests/signed5.v @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program tests the magic $signed system function. + */ + +module main; + + reg [3:0] a; + + initial begin + a = 4'd12; + + // The expression should not change the bit pattern in any way + if ($signed(a) !== 4'b1100) begin + $display("FAILED -- $signed(%b) === %b", a, $signed(a)); + $finish; + end + + if ($signed(a) == 4) begin + $display("FAILED -- $signed(%b) == 4", a); + $finish; + end + + // The >= should do a signed comparison here. + if ($signed(a) >= 0) begin + $display("FAILED -- $signed(%b) > 0", a); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/signed6.v b/ivtest/ivltests/signed6.v new file mode 100644 index 000000000..4de1e86f8 --- /dev/null +++ b/ivtest/ivltests/signed6.v @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * test the signedness of wires. + */ +module main; + + reg signed [7:0] val_rs = -5; + wire [7:0] val_w = val_rs + 1; + wire signed [7:0] val_ws = val_rs + 1; + + initial begin + #1 /* Let assignments settle. */ + $display("val_w=%d, val_ws=%d", val_w, val_ws); + + if (val_w !== 8'd252) begin + $display("FAILED -- val_w is wrong: %b", val_w); + $finish; + end + + if (val_ws !== -8'sd4) begin + $display("FAILED == val_ws is wrong: %b", val_ws); + $finish; + end + + if (val_ws > 0) begin + $display("FAILED -- signed test of val_ws failed"); + $finish; + end + + if (val_w < 0) begin + $display("FAILED -- signed test of val_w failed"); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/signed7.v b/ivtest/ivltests/signed7.v new file mode 100644 index 000000000..a0d3d2f4b --- /dev/null +++ b/ivtest/ivltests/signed7.v @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * test the signedness of wires. + */ +module main; + + reg signed [7:0] val_rs = -5; + wire [7:0] val_w = val_rs + 1; + wire signed [7:0] val_ws = val_rs + 1; + + sub dut(val_w, val_ws); +endmodule // main + +module sub(val_w, val_ws); + input [7:0] val_w; + input signed [7:0] val_ws; + + wire [7:0] val_w; + wire signed [7:0] val_ws; + + initial begin + #1 /* Let assignments settle. */ + $display("val_w=%d, val_ws=%d", val_w, val_ws); + + if (val_w !== 8'd252) begin + $display("FAILED -- val_w is wrong: %b", val_w); + $finish; + end + + if (val_ws !== -8'sd4) begin + $display("FAILED == val_ws is wrong: %b", val_ws); + $finish; + end + + if (val_ws > 0) begin + $display("FAILED -- signed test of val_ws failed"); + $finish; + end + + if (val_w < 0) begin + $display("FAILED -- signed test of val_w failed"); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/signed8.v b/ivtest/ivltests/signed8.v new file mode 100644 index 000000000..9aa78402a --- /dev/null +++ b/ivtest/ivltests/signed8.v @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2003 The ASIC Group (www.asicgroup.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module mult58s(input [4:0] a, input signed [7:0] b, output signed [15:0] p); + +wire signed [12:0] pt; + +wire signed [5:0] ta; + +assign ta = a; +assign pt = b * ta; + +assign p=pt; + +endmodule + + +module test_mult; + +integer a,b, prod; + +wire [15:0] p; +mult58s dut(a[4:0], b[7:0], p); + +initial begin + for(a = 0; a < (1<<5); a=a+1 ) + for(b=-127; b<128; b=b+1) + begin + prod = a * b; + #1 if(p !== prod[15:0]) begin + $display("Error Miscompare with a=%h, b=%h expect = %0d (%h) acutal = %h", + a[4:0], b[7:0], prod, prod[15:0], p); + $finish; + end + + end + + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/signed9.v b/ivtest/ivltests/signed9.v new file mode 100644 index 000000000..0a339ed78 --- /dev/null +++ b/ivtest/ivltests/signed9.v @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module assignsigned(); + parameter foo = 10; + reg signed [15:0] bar = -1; + wire baz; + assign baz = (bar < $signed(foo)); + + initial begin + #1 $display("bar=%h(%0d), foo=%0d, baz = %b", bar, bar, foo, baz); + if (baz !== 1'b1) begin + $display("FAILED -- Compare returns %b instead of 1.", baz); + $finish; + end + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/signed_a.v b/ivtest/ivltests/signed_a.v new file mode 100644 index 000000000..1cdd5b1de --- /dev/null +++ b/ivtest/ivltests/signed_a.v @@ -0,0 +1,30 @@ +module top; + reg pass; + reg [3:0] array [1:8]; + reg signed [2:0] a; + reg signed [127:0] b; + reg [4*8:1] res; + + initial begin + array [7] = 4'b1001; + pass = 1'b1; + /* If this fails it is likely because the index width is less + * than an integer width. */ + a = -1; + $sformat(res, "%b", array[a]); + if (res !== "xxxx") begin + $display("Failed: &A<> negative, expected 4'bxxxx, got %s.", res); + pass = 1'b0; + end + + b = 7; + b[120] = 1'b1; // This should be stripped! + $sformat(res, "%b", array[b]); + if (res !== "1001") begin + $display("Failed: &A<> large, expected 4'b1001, got %s.", res); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/signed_equality.v b/ivtest/ivltests/signed_equality.v new file mode 100644 index 000000000..fbefd4581 --- /dev/null +++ b/ivtest/ivltests/signed_equality.v @@ -0,0 +1,45 @@ +module top; + parameter seeq1 = 6'sb111000 === 4'sb1000; + parameter seeqx = 6'sbxxx000 === 4'sbx000; + parameter seeqz = 6'sbzzz000 === 4'sbz000; + parameter seq1 = 6'sb111000 == 4'sb1000; + parameter seqx = 6'sbxxx000 == 4'sbx000; + parameter seqz = 6'sbzzz000 == 4'sbz000; + reg pass; + + initial begin + pass = 1'b1; + + if (seeq1 !== 1'b1) begin + $display("FAILED: signed === (1), got %b", seeq1); + pass = 1'b0; + end + + if (seeqx !== 1'b1) begin + $display("FAILED: signed === (x), got %b", seeqx); + pass = 1'b0; + end + + if (seeqz !== 1'b1) begin + $display("FAILED: signed === (z), got %b", seeqz); + pass = 1'b0; + end + + if (seq1 !== 1'b1) begin + $display("FAILED: signed == (1), got %b", seq1); + pass = 1'b0; + end + + if (seqx !== 1'bx) begin + $display("FAILED: signed == (x), got %b", seqx); + pass = 1'b0; + end + + if (seqz !== 1'bx) begin + $display("FAILED: signed == (z), got %b", seqz); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/signed_net_display.v b/ivtest/ivltests/signed_net_display.v new file mode 100644 index 000000000..9bb594c16 --- /dev/null +++ b/ivtest/ivltests/signed_net_display.v @@ -0,0 +1,44 @@ +`begin_keywords "1364-2005" +module signed_net_display; + +wire signed [3:0] value[-7:7]; + +genvar i; + +for (i = 7; i >= -7; i = i - 1) begin:genloop + assign value[i] = i; +end + +reg [2*8-1:0] result; +reg [2*8-1:0] expect; + +integer j; + +reg fail = 0; + +initial begin + #0; + for (j = -7; j <= 7; j = j + 1) begin + $swrite(result, "%d", value[j]); + if (j < 0) + begin + expect[1*8 +: 8] = "-"; + expect[0*8 +: 8] = "0" - j; + end + else + begin + expect[1*8 +: 8] = " "; + expect[0*8 +: 8] = "0" + j; + end + $display("%s : %s", expect, result); + if (result !== expect) fail = 1; + end + + if (fail) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule +`end_keywords diff --git a/ivtest/ivltests/signed_part.v b/ivtest/ivltests/signed_part.v new file mode 100644 index 000000000..6bdae551b --- /dev/null +++ b/ivtest/ivltests/signed_part.v @@ -0,0 +1,23 @@ +module top; + reg pass = 1'b1; + reg [14:-1] big = 16'h0123; + + reg signed [15:0] a; + + wire [3:0] w_big = big[a+:4]; + + initial begin + #1; // Wait for the assigns above to happen. + + /* If this fails it is likely because the index width is less + * than an int width. */ + a = -2; + #1; + if (w_big !== 4'b011x) begin + $display("Failed: .part/v check, expected 4'b011x, got %b.", w_big); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/signed_pv.v b/ivtest/ivltests/signed_pv.v new file mode 100644 index 000000000..54288707c --- /dev/null +++ b/ivtest/ivltests/signed_pv.v @@ -0,0 +1,56 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + parameter pval = -2; + reg pass = 1'b1; + reg [14:-1] big = 16'h0123; + reg [15:0] big_0 = 16'h0123; + reg signed [15:0] idxs [0:1]; + + reg signed [15:0] a; + + reg [4*8:1] res; + + initial begin + + /* If this fails it is likely because the index width is less + * than an integer width. */ + a = -2; + $sformat(res, "%b", big[a+:4]); + if (res !== "011x") begin + $display("Failed: &PV<> check 1, expected 4'b011x, got %s.", res); + pass = 1'b0; + end + + a = 0; + idxs[0] = -1; + $sformat(res, "%b", big_0[idxs[a]+:4]); + if (res !== "011x") begin + $display("Failed: &PV<> check 2, expected 4'b011x, got %s.", res); + pass = 1'b0; + end + + /* This should work since it is a constant value. */ +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + $sformat(res, "%b", big[pval+:4]); +`else + $sformat(res, "%bx", big[(pval+1)+:3]); +`endif + if (res !== "011x") begin + $display("Failed: &PV<> check 3, expected 4'b011x, got %s.", res); + pass = 1'b0; + end + + /* This should always work since it uses the index directly. */ + a = -1; + $sformat(res, "%b", big_0[a+:4]); + if (res !== "011x") begin + $display("Failed: &PV<> check 4, expected 4'b011x, got %s.", res); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/simparam.v b/ivtest/ivltests/simparam.v new file mode 100644 index 000000000..e752b9e90 --- /dev/null +++ b/ivtest/ivltests/simparam.v @@ -0,0 +1,157 @@ +`timescale 1ns/1ps + +module top; + lower dut(); +endmodule + +module lower; + parameter bad_name = "this_is_a_bad_name"; + reg [15:0] def = "OK"; + reg pass = 1'b1; + reg [1023:0] result; + real rl_res; + + initial begin + + #1; + + /* Display the version and other information. */ + $display("Testing with Icarus Verilog version: %g, subversion: %g", + $simparam("simulatorVersion"), $simparam("simulatorSubversion")); + $display("Using a CPU word size of %g bits.", $simparam("CPUWordSize")); + $display("Running in directory: %0s\n", $simparam$str("cwd")); + + /* + * Check the time units and precision. + * + * Since this is double math check that the result is within a + * factor of 1e-10 of the correct value. + */ + rl_res = $simparam("timeUnit") - 1e-9; + rl_res = (rl_res < 0) ? -rl_res : rl_res; + if (rl_res > 1e-9*1e-10) begin + $display("$simparam(\"timeUnit\") failed, got %g.", rl_res); + pass = 1'b0; + end + + rl_res = $simparam("timePrecision") - 1e-12; + rl_res = (rl_res < 0) ? -rl_res : rl_res; + if (rl_res >= 1e-12*1e-10) begin + $display("$simparam(\"timePrecision\") failed, got %g.", rl_res); + pass = 1'b0; + end + + /* Check the string routines, see below for why this is a task. */ + check_string; + + /* Check that a bad parameter name with a default works. */ + if ($simparam(bad_name, 1.0) != 1.0) begin + $display("$simparam with a bad name and a default value failed."); + pass = 1'b0; + end + + result = $simparam$str(bad_name, def); + if (result[15:0] != "OK") begin + $display("$simparam$str with a bad name and a default value failed."); + pass = 1'b0; + end + + /* These should also print an error message. */ + if ($simparam(bad_name) != 0.0) begin + $display("$simparam with a bad name failed."); + pass = 1'b0; + end + + result = $simparam$str(bad_name); + if (result[55:0] != "") begin + $display("$simparam$str with a bad name failed."); + pass = 1'b0; + end + + + /* All these are currently unimplemented and just return 0.0 or N/A. */ + if ($simparam("gdev") != 0.0) begin + $display("$simparam(\"gdev\") failed."); + pass = 1'b0; + end + + if ($simparam("gmin") != 0.0) begin + $display("$simparam(\"gmin\") failed."); + pass = 1'b0; + end + + if ($simparam("imax") != 0.0) begin + $display("$simparam(\"imax\") failed."); + pass = 1'b0; + end + + if ($simparam("imelt") != 0.0) begin + $display("$simparam(\"imelt\") failed."); + pass = 1'b0; + end + + if ($simparam("iteration") != 0.0) begin + $display("$simparam(\"iteration\") failed."); + pass = 1'b0; + end + + if ($simparam("scale") != 0.0) begin + $display("$simparam(\"scale\") failed."); + pass = 1'b0; + end + + if ($simparam("shrink") != 0.0) begin + $display("$simparam(\"shrink\") failed."); + pass = 1'b0; + end + + if ($simparam("sourceScaleFactor") != 0.0) begin + $display("$simparam(\"sourceScaleFactor\") failed."); + pass = 1'b0; + end + + if ($simparam("tnom") != 0.0) begin + $display("$simparam(\"tnom\") failed."); + pass = 1'b0; + end + + result = $simparam$str("analysis_name"); + if (result[23:0] != "N/A") begin + $display("$simparam$str(\"analysis_name\") failed."); + pass = 1'b0; + end + + result = $simparam$str("analysis_type"); + if (result[23:0] != "N/A") begin + $display("$simparam$str(\"analysis_type\") failed."); + pass = 1'b0; + end + + if (pass) $display("\nPASSED"); + + end + + /* We need this to make instance and path different. */ + task check_string; + begin + result = $simparam$str("module"); + if (result[39:0] != "lower") begin + $display("$simparam$str(\"module\") failed, got %0s.", result); + pass = 1'b0; + end + + result = $simparam$str("instance"); + if (result[55:0] != "top.dut") begin + $display("$simparam$str(\"instance\") failed, got %0s.", result); + pass = 1'b0; + end + + result = $simparam$str("path"); + if (result[159:0] != "top.dut.check_string") begin + $display("$simparam$str(\"instance\") failed, got %0s.", result); + pass = 1'b0; + end + end + endtask + +endmodule diff --git a/ivtest/ivltests/simple_byte.v b/ivtest/ivltests/simple_byte.v new file mode 100644 index 000000000..975fb45eb --- /dev/null +++ b/ivtest/ivltests/simple_byte.v @@ -0,0 +1,34 @@ +module main; + + byte foo, bar = 10; + + byte wire_res; + byte var_res; + + assign wire_res = foo*bar; + initial begin + foo = 9; + var_res = foo * bar; + $display("%0d * %0d = %0d %0d", foo, bar, foo * bar, var_res); + + if ((foo * bar) !== 90) begin + $display("FAILED"); + $finish; + end + + if (var_res !== 90) begin + $display("FAILED"); + $finish; + end + + #0; // allow CA to propagate + $display("%0d * %0d = %0d", foo, bar, wire_res); + if (wire_res !== 90) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/simple_int.v b/ivtest/ivltests/simple_int.v new file mode 100644 index 000000000..3e0400e8b --- /dev/null +++ b/ivtest/ivltests/simple_int.v @@ -0,0 +1,34 @@ +module main; + + int foo, bar = 10; + + int wire_res; + int var_res; + + assign wire_res = foo*bar; + initial begin + foo = 9; + var_res = foo * bar; + $display("%0d * %0d = %0d %0d", foo, bar, foo * bar, var_res); + + if ((foo * bar) !== 90) begin + $display("FAILED"); + $finish; + end + + if (var_res !== 90) begin + $display("FAILED"); + $finish; + end + + #0; // allow CA to propagate + $display("%0d * %0d = %0d", foo, bar, wire_res); + if (wire_res !== 90) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/simple_longint.v b/ivtest/ivltests/simple_longint.v new file mode 100644 index 000000000..6bd9e20a0 --- /dev/null +++ b/ivtest/ivltests/simple_longint.v @@ -0,0 +1,34 @@ +module main; + + longint foo, bar = 10; + + longint wire_res; + longint var_res; + + assign wire_res = foo*bar; + initial begin + foo = 9; + var_res = foo * bar; + $display("%0d * %0d = %0d %0d", foo, bar, foo * bar, var_res); + + if ((foo * bar) !== 90) begin + $display("FAILED"); + $finish; + end + + if (var_res !== 90) begin + $display("FAILED"); + $finish; + end + + #0; // allow CA to propagate + $display("%0d * %0d = %0d", foo, bar, wire_res); + if (wire_res !== 90) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/simple_shortint.v b/ivtest/ivltests/simple_shortint.v new file mode 100644 index 000000000..03f5f65b6 --- /dev/null +++ b/ivtest/ivltests/simple_shortint.v @@ -0,0 +1,34 @@ +module main; + + shortint foo, bar = 10; + + shortint wire_res; + shortint var_res; + + assign wire_res = foo*bar; + initial begin + foo = 9; + var_res = foo * bar; + $display("%0d * %0d = %0d %0d", foo, bar, foo * bar, var_res); + + if ((foo * bar) !== 90) begin + $display("FAILED"); + $finish; + end + + if (var_res !== 90) begin + $display("FAILED"); + $finish; + end + + #0; // allow CA to propagate + $display("%0d * %0d = %0d", foo, bar, wire_res); + if (wire_res !== 90) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sint_test.v b/ivtest/ivltests/sint_test.v new file mode 100644 index 000000000..7079e18bd --- /dev/null +++ b/ivtest/ivltests/sint_test.v @@ -0,0 +1,372 @@ +// Eleven basic tests in here: +// 1. int must be initialised before any initial or always block +// 2. assignments to (signed) int with random numbers +// 3. assignments to (signed) int with random values including X and Z +// 4. converting unsigned integers to signed int +// 5. converting signed integers to signed int +// 6. converting integers including X and Z states to signed int +// 7. trying signed sums (procedural, function, task and module) +// 8. trying signed mults (procedural, function and task) +// 9. trying relational operators +// 10. smaller signed numbers to signed int (signed extension) +// 11. trying some concatenations from bytes, shortints to ints + +module ms_add (input int signed a, b, output int signed sc, ss); + assign sc = a + b; + always @(a, b) ss = a + b; +endmodule + +module main; + parameter N_REPS = 500; // repetition with random numbers + parameter XZ_REPS = 500; // repetition with 'x 'z values + parameter UMAX = 'h7fff_ffff; + parameter MAX8 = 'h7f; + parameter MAX16 = 'h7fff; + parameter LEN = 32; + // variables used as golden references + reg signed [LEN-1:0] ar; // holds numbers + reg signed [LEN-1:0] ar_xz; // holds 'x and/or 'z in random positions + reg signed [LEN-1:0] ar_expected; + integer unsigned ui; + integer signed si; + reg signed [LEN/2-1:0] slice; + + // type assumed tested before + byte signed pt1, pt2; + shortint signed ps1, ps2; + + // types to be tested + int signed bu; // holds numbers + int signed bu_xz; // 'x and 'z are attempted on this + int signed bresult; // hold results from sums and mults + int signed mcaresult; // wired to a module instance + int signed mabresult; // also wired to a module instance + + + integer i; + + // continuous assigments + // type LHS type RHS + // --------- --------- + // int 4-value logic + assign bu = ar; + assign bu_xz = ar_xz; + + // module instantiation + ms_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) ); + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 32'b0 || bu_xz !== 32'b0 || bresult !== 32'b0 || mcaresult !== 32'b0 || mabresult !== 32'b0) + begin + $display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz); + $finish; + end + // driving int type with signed random numbers from a variable + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = $random; + #1; + if (bu !== ar) + begin + $display ("FAILED - incorrect assigment to int: %b", bu); + $finish; + end + end + # 1; + // attempting to drive variables having 'x 'z values into type signed int + // 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + ar = $random; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect assigment to int (when 'x 'z): %b", bu); + $finish; + end + end + // converting unsigned integers to signed int + // maintaining bit representation is expected + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ui = {$random}; + #1; + force bu = ui; + #1; + if (bu !== ui) + begin + $display ("FAILED - incorrect truncation from unsigned integer to int: %b", bu); + $finish; + end + end + release bu; + // converting signed integers to signed ints + // bit representation should be maintained + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + si = $random; + #1; + force bu = si; + #1; + if (bu !== si) + begin + $display ("FAILED - incorrect assignment from signed integer to int: %b mismatchs %b", bu, si); + $finish; + end + end + release bu; + // converting integers having 'x 'z values into type signed int + // 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM) + // coercion to zero expected + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + si = $random; + ar_xz = xz_inject (si); + si = ar_xz; + ar_expected = xz_expected (ar_xz); + #1; + force bu_xz = si; + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect conversion from integer (with 'x 'z) to int: %b mismatchs %b", bu_xz, ar_expected); + $finish; + end + end + release bu_xz; + // trying signed sums + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = $random; + ar_xz = $random; + #1; + bresult = bu + bu_xz; + #1; + if ( bresult !== s_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of signed ints: %0d mismatchs %0d", bresult, s_sum(ar, ar_xz)); + $finish; + end + // invoking shortint sum function + if ( fs_sum (bu, bu_xz) !== s_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of signed int in function"); + $finish; + end + // invoking byte sum task + ts_sum (bu, bu_xz, bresult); + if ( bresult !== s_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of signed int in task: %0d mismatchs %0d", bresult, s_sum(ar, ar_xz)); + $finish; + end + // checking byte sum from module + if ( mcaresult !== s_sum(ar, ar_xz) || mabresult !== s_sum(ar, ar_xz)) + begin + $display ("FAILED - incorrect addition of signed int from module"); + $finish; + end + end + // trying signed mults + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = ($random % UMAX) << (LEN/2); + ar_xz = ($random % UMAX) << (LEN/2 - 1); + #1; + bresult = bu * bu_xz; // truncated multiplication + #1; + if ( bresult !== sh_mul(ar, ar_xz) ) + begin + $display ("FAILED - incorrect multiplication of signed ints (truncated)"); + $finish; + end + #1; + ps1 = $random % 'h7fff; + ps2 = $random % 'h7fff; + #1; + bresult = ps1 * ps2; // int = shorint x shortint + #1; + if ( bresult !== s_mul(ps1, ps2) ) + begin + $display ("FAILED - incorrect multiplication of signed shortints"); + $finish; + end + // invoking int mult function (shortint*shortint) + if ( fs_mul (ps1, ps2) !== s_mul(ps1, ps2) ) + begin + $display ("FAILED - incorrect product of signed shortint for a function returning signed int"); + $finish; + end + // invoking int mult task (shortint*shortint) + ts_mul (ps1, ps2, bresult); + if ( bresult !== s_mul(ps1, ps2) ) + begin + $display ("FAILED - incorrect product of signed shortint in task returning signed int"); + $finish; + end + end + // trying relational operators + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = $random; + ar_xz = $random; + #1; + if ( (bu < bu_xz ) !== (ar < ar_xz) ) + begin + $display ("FAILED - incorrect 'less than' on signed ints"); + $finish; + end + if ( (bu <= bu_xz ) !== (ar <= ar_xz) ) + begin + $display ("FAILED - incorrect 'less than or equal' on signed ints"); + $finish; + end + if ( (bu > bu_xz ) !== (ar > ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than' on signed ints"); + $finish; + end + if ( (bu >= bu_xz ) !== (ar >= ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than or equal' than on signed ints"); + $finish; + end + if ( (bu == bu_xz ) !== (ar == ar_xz) ) + begin + $display ("FAILED - incorrect 'equal to' on signed ints"); + $finish; + end + if ( (bu != bu_xz ) !== (ar != ar_xz) ) + begin + $display ("FAILED - incorrect 'not equal to' on signed ints"); + $finish; + end + end + # 1; + // signed small number to signed int + for (i = 0; i < (1< +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Tests size casting of complex expressions. + +module resize(output wire logic [4:0] result); + logic [6:0] a; + assign result = (5'(a + 2)); + + initial begin + a = 7'd39; + end +endmodule + +module resize_test(); + logic [4:0] result; + resize dut(result); + + initial begin + #1; + + if(result !== 5'd9) begin + $display("FAILED"); + $finish(); + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/size_cast3.v b/ivtest/ivltests/size_cast3.v new file mode 100644 index 000000000..f4cf921d8 --- /dev/null +++ b/ivtest/ivltests/size_cast3.v @@ -0,0 +1,69 @@ +module test(); + +localparam size1 = 4; +localparam size2 = 6; +localparam size3 = 8; + +localparam [5:0] value1 = 6'h3f; +localparam signed [5:0] value2 = 6'h3f; + +reg [31:0] result; + +reg failed = 0; + +initial begin + result = size1'(value1) + 'd0; + $display("%h", result); + if (result !== 32'h0000000f) failed = 1; + + result = size1'(value1) + 'sd0; + $display("%h", result); + if (result !== 32'h0000000f) failed = 1; + + result = size1'(value2) + 'd0; + $display("%h", result); + if (result !== 32'h0000000f) failed = 1; + + result = size1'(value2) + 'sd0; + $display("%h", result); + if (result !== 32'hffffffff) failed = 1; + + result = size2'(value1) + 'd0; + $display("%h", result); + if (result !== 32'h0000003f) failed = 1; + + result = size2'(value1) + 'sd0; + $display("%h", result); + if (result !== 32'h0000003f) failed = 1; + + result = size2'(value2) + 'd0; + $display("%h", result); + if (result !== 32'h0000003f) failed = 1; + + result = size2'(value2) + 'sd0; + $display("%h", result); + if (result !== 32'hffffffff) failed = 1; + + result = size3'(value1) + 'd0; + $display("%h", result); + if (result !== 32'h0000003f) failed = 1; + + result = size3'(value1) + 'sd0; + $display("%h", result); + if (result !== 32'h0000003f) failed = 1; + + result = size3'(value2) + 'd0; + $display("%h", result); + if (result !== 32'h000000ff) failed = 1; + + result = size3'(value2) + 'sd0; + $display("%h", result); + if (result !== 32'hffffffff) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule // main diff --git a/ivtest/ivltests/size_cast4.v b/ivtest/ivltests/size_cast4.v new file mode 100644 index 000000000..6d06e5ee3 --- /dev/null +++ b/ivtest/ivltests/size_cast4.v @@ -0,0 +1,69 @@ +module test(); + +localparam size1 = 4; +localparam size2 = 6; +localparam size3 = 8; + +reg [5:0] value1 = 6'h3f; +reg signed [5:0] value2 = 6'h3f; + +reg [31:0] result; + +reg failed = 0; + +initial begin + result = size1'(value1) + 'd0; + $display("%h", result); + if (result !== 32'h0000000f) failed = 1; + + result = size1'(value1) + 'sd0; + $display("%h", result); + if (result !== 32'h0000000f) failed = 1; + + result = size1'(value2) + 'd0; + $display("%h", result); + if (result !== 32'h0000000f) failed = 1; + + result = size1'(value2) + 'sd0; + $display("%h", result); + if (result !== 32'hffffffff) failed = 1; + + result = size2'(value1) + 'd0; + $display("%h", result); + if (result !== 32'h0000003f) failed = 1; + + result = size2'(value1) + 'sd0; + $display("%h", result); + if (result !== 32'h0000003f) failed = 1; + + result = size2'(value2) + 'd0; + $display("%h", result); + if (result !== 32'h0000003f) failed = 1; + + result = size2'(value2) + 'sd0; + $display("%h", result); + if (result !== 32'hffffffff) failed = 1; + + result = size3'(value1) + 'd0; + $display("%h", result); + if (result !== 32'h0000003f) failed = 1; + + result = size3'(value1) + 'sd0; + $display("%h", result); + if (result !== 32'h0000003f) failed = 1; + + result = size3'(value2) + 'd0; + $display("%h", result); + if (result !== 32'h000000ff) failed = 1; + + result = size3'(value2) + 'sd0; + $display("%h", result); + if (result !== 32'hffffffff) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule // main diff --git a/ivtest/ivltests/size_cast5.v b/ivtest/ivltests/size_cast5.v new file mode 100644 index 000000000..b8166b9b4 --- /dev/null +++ b/ivtest/ivltests/size_cast5.v @@ -0,0 +1,111 @@ +module test(); + +function [31:0] cast_4uu(input [5:0] value); + cast_4uu = 4'(value) + 'd0; +endfunction + +function [31:0] cast_4us(input [5:0] value); + cast_4us = 4'(value) + 'sd0; +endfunction + +function [31:0] cast_4su(input signed [5:0] value); + cast_4su = 4'(value) + 'd0; +endfunction + +function [31:0] cast_4ss(input signed [5:0] value); + cast_4ss= 4'(value) + 'sd0; +endfunction + +function [31:0] cast_6uu(input [5:0] value); + cast_6uu = 6'(value) + 'd0; +endfunction + +function [31:0] cast_6us(input [5:0] value); + cast_6us = 6'(value) + 'sd0; +endfunction + +function [31:0] cast_6su(input signed [5:0] value); + cast_6su = 6'(value) + 'd0; +endfunction + +function [31:0] cast_6ss(input signed [5:0] value); + cast_6ss= 6'(value) + 'sd0; +endfunction + +function [31:0] cast_8uu(input [5:0] value); + cast_8uu = 8'(value) + 'd0; +endfunction + +function [31:0] cast_8us(input [5:0] value); + cast_8us = 8'(value) + 'sd0; +endfunction + +function [31:0] cast_8su(input signed [5:0] value); + cast_8su = 8'(value) + 'd0; +endfunction + +function [31:0] cast_8ss(input signed [5:0] value); + cast_8ss= 8'(value) + 'sd0; +endfunction + +localparam [31:0] result1a = cast_4uu(6'h3f); +localparam [31:0] result1b = cast_4us(6'h3f); +localparam [31:0] result1c = cast_4su(6'h3f); +localparam [31:0] result1d = cast_4ss(6'h3f); + +localparam [31:0] result2a = cast_6uu(6'h3f); +localparam [31:0] result2b = cast_6us(6'h3f); +localparam [31:0] result2c = cast_6su(6'h3f); +localparam [31:0] result2d = cast_6ss(6'h3f); + +localparam [31:0] result3a = cast_8uu(6'h3f); +localparam [31:0] result3b = cast_8us(6'h3f); +localparam [31:0] result3c = cast_8su(6'h3f); +localparam [31:0] result3d = cast_8ss(6'h3f); + +reg failed = 0; + +initial begin + $display("%h", result1a); + if (result1a !== 32'h0000000f) failed = 1; + + $display("%h", result1b); + if (result1b !== 32'h0000000f) failed = 1; + + $display("%h", result1c); + if (result1c !== 32'h0000000f) failed = 1; + + $display("%h", result1d); + if (result1d !== 32'hffffffff) failed = 1; + + $display("%h", result2a); + if (result2a !== 32'h0000003f) failed = 1; + + $display("%h", result2b); + if (result2b !== 32'h0000003f) failed = 1; + + $display("%h", result2c); + if (result2c !== 32'h0000003f) failed = 1; + + $display("%h", result2d); + if (result2d !== 32'hffffffff) failed = 1; + + $display("%h", result3a); + if (result3a !== 32'h0000003f) failed = 1; + + $display("%h", result3b); + if (result3b !== 32'h0000003f) failed = 1; + + $display("%h", result3c); + if (result3c !== 32'h000000ff) failed = 1; + + $display("%h", result3d); + if (result3d !== 32'hffffffff) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule // main diff --git a/ivtest/ivltests/slongint_test.v b/ivtest/ivltests/slongint_test.v new file mode 100644 index 000000000..bdb51c6d7 --- /dev/null +++ b/ivtest/ivltests/slongint_test.v @@ -0,0 +1,386 @@ +// Eleven basic tests in here: +// 1. longint must be initialised before any initial or always block +// 2. assignments to (signed) longint with random numbers +// 3. assignments to (signed) longint with random values including X and Z +// 4. converting unsigned 64-bit integer time to signed longint +// 5. converting signed integers to signed longint +// 6. converting 64-bit integers including X and Z states to unsigned longint +// 7. trying unsigned sums (procedural, function, task and module) +// 8. trying unsigned mults (procedural, function and task) +// 9. trying relational operators +// 10. smaller signed numbers to unsigned longint (signed extension) +// 11. trying some concatenations from bytes, shortints, ints to longints + +module ms_add (input longint signed a, b, output longint signed sc, ss); + assign sc = a + b; + always @(a, b) ss = a + b; +endmodule + +module main; + parameter N_REPS = 500; // repetition with random numbers + parameter XZ_REPS = 500; // repetition with 'x 'z values + parameter MAX8 = 'h7f; + parameter MAX16 = 'h7fff; + parameter LEN = 64; + // variables used as golden references + reg signed [LEN-1:0] ar; // holds numbers + reg signed [LEN-1:0] ar_xz; // holds 'x and/or 'z in random positions + reg signed [LEN-1:0] ar_expected; + reg unsigned [LEN-1:0] ui; // unsigned 64-bit integer + reg signed [LEN-1:0] si; // signed 64-bit integer + reg signed [LEN/2-1:0] slice; + + // type assumed to be tested before hand + byte signed pt1, pt2; + shortint signed ps1, ps2; + int signed pv1, pv2; + + // types to be tested + longint signed bu; // holds numbers + longint signed bu_xz; // 'x and 'z are attempted on this + longint signed bresult; // hold results from sums and mults + longint signed mcaresult; // wired to a module instance + longint signed mabresult; // also wired to a module instance + + + integer i; + + // continuous assigments + // type LHS type RHS + // --------- --------- + // longint 4-value logic + assign bu = ar; + assign bu_xz = ar_xz; + + // module instantiation + ms_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) ); + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 64'b0 || bu_xz != 64'b0 || bresult !== 64'b0 || mcaresult !== 64'b0 || mabresult !== 64'b0) + begin + $display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz); + $finish; + end + // driving longint type with signed random numbers from a variable + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = { $random, $random }; + #1; + if (bu !== ar) + begin + $display ("FAILED - incorrect assigment to int: %b", bu); + $finish; + end + end + # 1; + // attempting to drive variables having 'x 'z values into type unsigned longint + // 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + ar = { $random, $random }; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect assigment to longint (when 'x 'z): %b", bu); + $finish; + end + end + // converting unsigned 64-bit integers (time) to unsigned longint + // this should pass trivially + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ui = { {$random}, {$random} }; + #1; + force bu = ui; + #1; + if (bu !== ui) + begin + $display ("FAILED - incorrect assignment from 64-bit integer to longint: %b", bu); + $finish; + end + end + release bu; + // converting signed 64-bit integers to unsigned longints + // keeping the same bit representation is expected + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + si = { {$random}, {$random} }; + #1; + force bu = si; + #1; + if (bu !== si) + begin + $display ("FAILED - incorrect assignment from 64-bit signed integer to longint: %d mismatchs %d", bu, -ui); + $finish; + end + end + release bu; + // converting integers having 'x 'z values into type unsigned longint + // 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM) + // coercion to zero expected + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + ui = { {$random}, {$random} }; + ar_xz = xz_inject (ui); + ui = ar_xz; + ar_expected = xz_expected (ar_xz); + #1; + force bu_xz = ui; + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect conversion from 64-bit integer (with 'x 'z) to longint: %b mismatchs %b", bu_xz, ar_expected); + $finish; + end + end + release bu_xz; + // trying signed sums + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = { $random, $random }; + ar_xz = { $random, $random }; + #1; + bresult = bu + bu_xz; + #1; + if ( bresult !== s_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of signed longints: %0d mismatchs %0d", bresult, s_sum(ar, ar_xz)); + $finish; + end + // invoking longint sum function + if ( fs_sum (bu, bu_xz) !== s_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of unsigned longint in function"); + $finish; + end + // invoking longint sum task + ts_sum (bu, bu_xz, bresult); + if ( bresult !== s_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of unsigned longint in task: %0d mismatchs %0d", bresult, s_sum(ar, ar_xz)); + $finish; + end + // checking longint sum from module + if ( mcaresult !== s_sum(ar, ar_xz) || mabresult !== s_sum(ar, ar_xz)) + begin + $display ("FAILED - incorrect addition of signed longtint from module"); + $finish; + end + end + // trying signed mults + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = { $random % 32'd32768, $random % 32'd16384 }; + ar_xz = { $random % 32'd16384, $random % 32'd32768 }; + #1; + bresult = bu * bu_xz; // truncated mult + #1; + if ( bresult !== sh_mul(ar, ar_xz) ) + begin + $display ("FAILED - incorrect multiplication of signed longints: %0d mismatchs %0d", bresult, sh_mul(ar, ar_xz)); + $finish; + end + #1; + pv1 = $random; + pv2 = $random; + #1; + bresult = pv1 * pv2; // longint = int x int + #1; + if ( bresult !== s_mul(pv1, pv2) ) + begin + $display ("FAILED - incorrect multiplication of signed longints for int inputs"); + $finish; + end + // invoking longint mult function (int*int) + if ( fs_mul (pv1, pv2) !== s_mul(pv1, pv2) ) + begin + $display ("FAILED - incorrect product of signed ints for a function returning signed longint"); + $finish; + end + // invoking longint mult task (int*int) + ts_mul (pv1, pv2, bresult); + if ( bresult !== s_mul(pv1, pv2) ) + begin + $display ("FAILED - incorrect product of signed int in task returning signed longint"); + $finish; + end + end + // trying relational operators + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = { $random, $random }; + ar_xz = { $random, $random }; + #1; + if ( (bu < bu_xz ) != (ar < ar_xz) ) + begin + $display ("FAILED - incorrect 'less than' on signed longints"); + $finish; + end + if ( (bu <= bu_xz ) != (ar <= ar_xz) ) + begin + $display ("FAILED - incorrect 'less than or equal' on signed longints"); + $finish; + end + if ( (bu > bu_xz ) != (ar > ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than' on signed longints"); + $finish; + end + if ( (bu >= bu_xz ) != (ar >= ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than or equal' than on signed longints"); + $finish; + end + if ( (bu == bu_xz ) != (ar == ar_xz) ) + begin + $display ("FAILED - incorrect 'equal to' on signed longints"); + $finish; + end + if ( (bu != bu_xz ) != (ar != ar_xz) ) + begin + $display ("FAILED - incorrect 'not equal to' on signed ints"); + $finish; + end + end + # 1; + // signed small number to unsigned shorint + for (i = 0; i < N_REPS; i = i+1) + begin + #1; + slice = $random % 'h7fff_ffff; + force bu = slice; + ar = slice; + #1; + if (bu !== ar) + begin + $display ("FAILED - incorrect signed extend to signed longint"); + $finish; + end + end + release bu; + // trying concatenations (and replication) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + pt1 = $random % MAX8; + pt2 = $random % MAX8; + #1; + bresult = { {4{pt1}}, {4{pt2}} }; + #1; + if ( bresult[63:56] !== pt1 || bresult[55:48] !== pt1 || bresult[47:40] !== pt1 || bresult[39:32] !== pt1 || + bresult[31:24] !== pt2 || bresult[23:16] !== pt2 || bresult[15:8] !== pt2 || bresult[7:0] !== pt2) + begin + $display ("FAILED - incorrect concatenation and replication of bytes into signed longints"); + $finish; + end + #1; + ps1 = $random % MAX16; + ps2 = $random % MAX16; + #1; + bresult = { {2{ps1}}, {2{ps2}} }; + #1; + if ( bresult[63:48] !== ps1 || bresult[47:32] !== ps1 || bresult[31:16] !== ps2 || bresult[15:0] !== ps2) + begin + $display ("FAILED - incorrect concatenation and replication of shortint into signed long ints"); + $finish; + end + #1; + pv1 = $random; + pv2 = $random; + #1; + bresult = { pv1, pv2 }; + #1; + if ( bresult[63:32] !== pv1 || bresult[31:0] !== pv2) + begin + $display ("FAILED - incorrect concatenation and replication of int into signed longints"); + $finish; + end + end + #1; + $display("PASSED"); + end + + // this returns X and Z states into bit random positions for a value + function [LEN-1:0] xz_inject (input signed [LEN-1:0] value); + integer i, k; + time temp; + begin + temp = {$random, $random}; + for (i=0; i P) = (td, td, th, 0, th, 0); + endspecify + + +endmodule +`endcelldefine diff --git a/ivtest/ivltests/specify2.v b/ivtest/ivltests/specify2.v new file mode 100644 index 000000000..af785360a --- /dev/null +++ b/ivtest/ivltests/specify2.v @@ -0,0 +1,51 @@ +module main; + + wire dst; + reg src; + + spec_buf dut(dst, src); + + initial begin + src = 0; + #10 if (dst !== 0) begin + $display("FAILED -- setup failed: src=%b, dst=%b", src, dst); + $finish; + end + + src = 1; + + #5 if (dst !== 0) begin + $display("FAILED -- dst changed too fast. src=%b, dst=%b", src, dst); + $finish; + end + + #5 if (dst !== 1) begin + $display("FAILED -- dst failed to change. src=%b, dst=%b", src, dst); + $finish; + end + + src = 0; + + #5 if (dst !== 1) begin + $display("FAILED -- dst changed too fast. src=%b, dst=%b", src, dst); + $finish; + end + + #5 if (dst !== 0) begin + $display("FAILED -- dst failed to change. src=%b, dst=%b", src, dst); + $finish; + end + + $display("PASSED"); + end +endmodule // main + +module spec_buf(output wire O, input wire I); + + buf (O, I); + + specify + (I => O) = (7); + endspecify + +endmodule // sec_buf diff --git a/ivtest/ivltests/specify3.v b/ivtest/ivltests/specify3.v new file mode 100644 index 000000000..fb09ae7f0 --- /dev/null +++ b/ivtest/ivltests/specify3.v @@ -0,0 +1,42 @@ +// specify3.v + +module top; + reg a, b, fast; + wire q; + + initial begin + a = 0; + b = 0; + fast = 0; + #10 $monitor($time,,"a=%b, b=%b, fast=%b, q=%b", a, b, fast, q); + #10 a = 1; + #10 a = 0; + #10 b = 1; + #10 b = 0; + #10 a = 1; + #10 fast = 1; + #10 b = 1; + #10 b = 0; + #10 a = 0; + #10 a = 1; + + #10 $finish(0); + end + + myxor g1 (q, a, b, fast); + +endmodule + +module myxor (q, a, b, fast); + output q; + input a, b, fast; + + xor g1 (q, a, b); + + specify + if (fast) (b => q) = 1; + if (fast) (a => q) = 1; + if (~fast) (b => q) = 4; + if (~fast) (a => q) = 4; + endspecify +endmodule diff --git a/ivtest/ivltests/specify4.v b/ivtest/ivltests/specify4.v new file mode 100644 index 000000000..4860ef744 --- /dev/null +++ b/ivtest/ivltests/specify4.v @@ -0,0 +1,30 @@ +// specify4.v + +module top; + reg d, c; + wire q; + + initial begin + d = 0; + c = 1; + #10 $monitor($time,,"q=%b, d=%b, c=%b", q, d, c); + #5 c = 0; + #5 c = 1; + #5 c = 0; d = 1; + #5 c = 1; + #5 c = 0; d = 0; + #5 c = 1; + #10 $finish(0); + end + + mydff g1 (q, d, c); + +endmodule + +module mydff (output reg q, input d, input c); + + always @(posedge c) q <= d; + specify + (posedge c => (q +: d)) = (3, 2); + endspecify +endmodule diff --git a/ivtest/ivltests/specify5.v b/ivtest/ivltests/specify5.v new file mode 100644 index 000000000..fa580e521 --- /dev/null +++ b/ivtest/ivltests/specify5.v @@ -0,0 +1,86 @@ +`timescale 100 ps / 10 ps + +module test; + reg cdn, cp, d; + wire qr, qp; + + initial begin + $timeformat(-9, 2, " ns", 9); + $monitor("%t - cdn=%b, cp=%b, d=%b, qr=%b, qp=%b",$time,cdn,cp,d,qr,qp); + // Reset the FF. + cp = 0; d = 1; + #100 cdn = 0; + #100 cdn = 1; + // Toggle in some data. + #100 cp = 1; + #100 cp = 0; d = 0; + #100 cp = 1; + #100 cp = 0; d = 1; + #100 cp = 1; + end + + dff_rtl dutr(qr, d, cp, cdn); // This one works fine. + dff_prm dutp(qp, d, cp, cdn); // This one has no delay. +endmodule + +// The RTL version appears to work fine. +module dff_rtl (q, d, cp, cdn); + output q; + input d; + input cp; + input cdn; + + reg qi; + + always @(posedge cp or negedge cdn) begin + if (~cdn) qi <= 1'b0; + else qi <= d; + end + buf (q, qi); + + specify + specparam tpd_cp_q_lh = 6; + specparam tpd_cp_q_hl = 7; + specparam tpd_cdn_q_lh = 0; + specparam tpd_cdn_q_hl = 3; + + if (cdn) (posedge cp => (q +: d)) = (tpd_cp_q_lh, tpd_cp_q_hl); + (negedge cdn => (q +: 1'b0)) = (tpd_cdn_q_lh, tpd_cdn_q_hl); + endspecify +endmodule + +// The primitive version has no delay. +module dff_prm (q, d, cp, cdn); + output q; + input d, cp, cdn; + + UDP_DFF G3(q, d, cp, cdn); + + specify + specparam tpd_cp_q_lh = 6; + specparam tpd_cp_q_hl = 7; + specparam tpd_cdn_q_lh = 0; + specparam tpd_cdn_q_hl = 3; + + if (cdn) (posedge cp => (q +: d)) = (tpd_cp_q_lh, tpd_cp_q_hl); + (negedge cdn => (q +: 1'b0)) = (tpd_cdn_q_lh, tpd_cdn_q_hl); + endspecify + +endmodule + +// This is overly simplistic, but it works for this example. +primitive UDP_DFF(q, d, cp, cdn); + output q; + reg q; + input d, cp, cdn; + + table + // d cp cdn q0 q + * ? ? : ? : - ; + ? n ? : ? : - ; + 0 r 1 : ? : 0 ; + 1 r 1 : ? : 1 ; + ? ? 0 : ? : 0 ; + ? ? p : ? : - ; + endtable +endprimitive diff --git a/ivtest/ivltests/specify_01.v b/ivtest/ivltests/specify_01.v new file mode 100644 index 000000000..0d058a68e --- /dev/null +++ b/ivtest/ivltests/specify_01.v @@ -0,0 +1,72 @@ +module dff (clk, d, q) ; + +input d,clk; +output q; + +reg q_out; +wire q; + +specify + specparam tR_clk_q = 100, + tF_clk_q = 150; + + (clk,d => q) = (tR_clk_q,tF_clk_q); +endspecify + +always @(posedge clk) + q_out <= d; + +buf u_buf (q,q_out); + +endmodule + +module test; + +reg clk, d; +reg err; +time pos_lvl,neg_lvl; + +dff u_dff (clk,d,q); + +initial + begin +// $dumpfile("test.vcd"); +// $dumpvars(0,test); + + err = 0; + d = 0; + clk = 0; + #200; + clk = 1; + #200; + clk = 0; + #200; + clk = 1; + #200; + clk = 0; + #200; + clk = 1; + $display("pos_lvl=%t neg_lvl=%t",pos_lvl,neg_lvl); + if((pos_lvl != 700) && (neg_lvl != 350)) + $display("FAILED"); + else + $display("PASSED"); + end + +always @(posedge q) + pos_lvl = $time; + +always @(negedge q) + neg_lvl = $time; + +initial + begin + #250; + d = 1; + #450; + d = 0; + end + + + +endmodule diff --git a/ivtest/ivltests/specparam1.v b/ivtest/ivltests/specparam1.v new file mode 100644 index 000000000..7fe626589 --- /dev/null +++ b/ivtest/ivltests/specparam1.v @@ -0,0 +1,36 @@ +module test(); + +specparam sp1 = 2'd1; +specparam [1:0] sp2 = 2; +specparam sp3 = 3.5; + +specify + specparam sp4 = sp1; + specparam [1:0] sp5 = sp2 + 1; + specparam sp6 = sp3 + 1.0; +endspecify + +reg pass = 1; + +initial begin + $display("%b", sp1); + if (($bits(sp1) != 2) || (sp1 !== 2'd1)) pass = 0; + $display("%b", sp2); + if (($bits(sp2) != 2) || (sp2 !== 2'd2)) pass = 0; + $display("%f", sp3); + if (sp3 != 3.5) pass = 0; + + $display("%b", sp4); + if (($bits(sp4) != 2) || (sp4 !== 2'd1)) pass = 0; + $display("%b", sp5); + if (($bits(sp5) != 2) || (sp5 !== 2'd3)) pass = 0; + $display("%f", sp6); + if (sp6 != 4.5) pass = 0; + + if (pass) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/specparam2.v b/ivtest/ivltests/specparam2.v new file mode 100644 index 000000000..c71264901 --- /dev/null +++ b/ivtest/ivltests/specparam2.v @@ -0,0 +1,24 @@ +module test(); + +specparam sp1 = 1; +specparam sp2 = 2; +specparam [3:0] sp3 = 4'b0101; + +localparam lp1 = {sp2{1'b1}}; +localparam lp2 = sp3[sp1 +: sp2]; + +reg pass = 1; + +initial begin + $display("%b", lp1); + if (($bits(lp1) != 2) || (lp1 !== 2'b11)) pass = 0; + $display("%b", lp2); + if (($bits(lp2) != 2) || (lp2 !== 2'b10)) pass = 0; + + if (pass) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/sqrt32.v b/ivtest/ivltests/sqrt32.v new file mode 100644 index 000000000..26ed7cb36 --- /dev/null +++ b/ivtest/ivltests/sqrt32.v @@ -0,0 +1,244 @@ +`begin_keywords "1364-2005" +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + * $Id: sqrt32.v,v 1.2 2007/08/30 01:25:29 stevewilliams Exp $" + */ + + + /* + * This module approximates the square root of an unsigned 32bit + * number. The algorithm works by doing a bit-wise binary search. + * Starting from the most significant bit, the accumulated value + * tries to put a 1 in the bit position. If that makes the square + * too big for the input, the bit is left zero, otherwise it is set + * in the result. This continues for each bit, decreasing in + * significance, until all the bits are calculated or all the + * remaining bits are zero. + * + * Since the result is an integer, this function really calculates + * value of the expression: + * + * x = floor(sqrt(y)) + * + * where sqrt(y) is the exact square root of y and floor(N) is the + * largest integer <= N. + * + * For 32bit numbers, this will never run more then 16 iterations, + * which amounts to 16 clocks. + */ + +module sqrt + (input clk, + output wire rdy, + input reset, + input [31:0] x, + output reg [15:0] acc); + + + //32 + parameter ss=5; localparam w=1<= ((z + 1)*(z + 1))) + begin + $display("test=%d x=%d, y=%d ERROR: y is too small", idx, A, Z); + $display("FAILED"); + $finish; + end + end + else + begin + $display ("Could not verify above number"); + end + + end + + $display ("Running tests Amax=%d random input numbers", Amax); + + for (idx = 0 ; idx < Amax; idx = 1+ idx) begin + A = $random; + // A = A - ((A / Amax) * Amax); //this is needed only if <32 bit + + //A = idx; //sequential -- comment out to get random tests + + if (A < 1<<(w-1)) begin + + reset_dut; + run_dut; + + //$display("%d: x=%d, y=%d", idx, A, Z); + + a = A; + z = Z; + + if (a < (z *z)) begin + $display("test=%d x=%d, y=%d ERROR:y is too big", idx, A, Z); + $display("FAILED"); + $finish; + end + + if (z<65535) // at this number y*y overflows, so cannot test this way + begin + if (a >= ((z + 1)*(z + 1))) + begin + $display("test=%d x=%d, y=%d ERROR: y is too small", idx, A, Z); + $display("FAILED"); + $finish; + end + end + else + begin + $display ("Could not verify above number"); + end + + + //$display("%d: x=%d, y=%d", idx, A, Z); + if (idx%1000 == 0) $display("Finished %d tests", idx); + end // if (A < Amax) begin + end + $display ("PASSED"); + $finish; + + end + +endmodule +`end_keywords diff --git a/ivtest/ivltests/sqrt32synth.v b/ivtest/ivltests/sqrt32synth.v new file mode 100644 index 000000000..0b81965f5 --- /dev/null +++ b/ivtest/ivltests/sqrt32synth.v @@ -0,0 +1,244 @@ +`begin_keywords "1364-2005" +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + * $Id: sqrt32synth.v,v 1.2 2007/08/30 01:25:29 stevewilliams Exp $" + */ + + + /* + * This module approximates the square root of an unsigned 32bit + * number. The algorithm works by doing a bit-wise binary search. + * Starting from the most significant bit, the accumulated value + * tries to put a 1 in the bit position. If that makes the square + * too big for the input, the bit is left zero, otherwise it is set + * in the result. This continues for each bit, decreasing in + * significance, until all the bits are calculated or all the + * remaining bits are zero. + * + * Since the result is an integer, this function really calculates + * value of the expression: + * + * x = floor(sqrt(y)) + * + * where sqrt(y) is the exact square root of y and floor(N) is the + * largest integer <= N. + * + * For 32bit numbers, this will never run more then 16 iterations, + * which amounts to 16 clocks. + */ + +module sqrt + (input clk, + output wire rdy, + input reset, + input [31:0] x, + output reg [15:0] acc); + + + //32 + parameter ss=5; localparam w=1<= ((z + 1)*(z + 1))) + begin + $display("test=%d x=%d, y=%d ERROR: y is too small", idx, A, Z); + $display("FAILED"); + $finish; + end + end + else + begin + $display ("Could not verify above number"); + end + + end + + $display ("Running tests Amax=%d random input numbers", Amax); + + for (idx = 0 ; idx < Amax; idx = 1+ idx) begin + A = $random; + // A = A - ((A / Amax) * Amax); //this is needed only if <32 bit + + //A = idx; //sequential -- comment out to get random tests + + if (A < 1<<(w-1)) begin + + reset_dut; + run_dut; + + //$display("%d: x=%d, y=%d", idx, A, Z); + + a = A; + z = Z; + + if (a < (z *z)) begin + $display("test=%d x=%d, y=%d ERROR:y is too big", idx, A, Z); + $display("FAILED"); + $finish; + end + + if (z<65535) // at this number y*y overflows, so cannot test this way + begin + if (a >= ((z + 1)*(z + 1))) + begin + $display("test=%d x=%d, y=%d ERROR: y is too small", idx, A, Z); + $display("FAILED"); + $finish; + end + end + else + begin + $display ("Could not verify above number"); + end + + + //$display("%d: x=%d, y=%d", idx, A, Z); + if (idx%1000 == 0) $display("Finished %d tests", idx); + end // if (A < Amax) begin + end + $display ("PASSED"); + $finish; + + end + +endmodule +`end_keywords diff --git a/ivtest/ivltests/sscanf_u.v b/ivtest/ivltests/sscanf_u.v new file mode 100644 index 000000000..d0b432fb3 --- /dev/null +++ b/ivtest/ivltests/sscanf_u.v @@ -0,0 +1,16 @@ +module top; + reg [63:0] str; + reg [31:0] in, ck, out; + integer res; + + initial begin + // To avoid embedded NULL bytes each byte must have a 1. + in = 32'b000x100z_001z000x_101xxxzz_100z111x; + ck = 32'b00001000_00100000_10100000_10001110; + $sformat(str, "%u", in); + res = $sscanf(str, "%u", out); + if (res !== 1) $display("FAILED: $sscanf() returned %d", res); + else if (ck !== out) $display("FAILED: %b !== %b", in, out); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/sscanf_z.v b/ivtest/ivltests/sscanf_z.v new file mode 100644 index 000000000..6cb7b4644 --- /dev/null +++ b/ivtest/ivltests/sscanf_z.v @@ -0,0 +1,15 @@ +module top; + reg [63:0] str; + reg [31:0] in, out; + integer res; + + initial begin + // To avoid embedded NULL bytes each byte must have an x or a 1 and a z. + in = 32'b000x100z_001z000x_101xxxzz_100z111x; + $sformat(str, "%z", in); + res = $sscanf(str, "%z", out); + if (res !== 1) $display("FAILED: $sscanf() returned %d", res); + else if (in !== out) $display("FAILED: %b !== %b", in, out); + else $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/ssetclr1.v b/ivtest/ivltests/ssetclr1.v new file mode 100644 index 000000000..9e6ef4b2e --- /dev/null +++ b/ivtest/ivltests/ssetclr1.v @@ -0,0 +1,107 @@ +/* + * In this example, the set and clr are both synchronous. This checks + * that this complex case is handled correctly. + */ +module main; + + + reg Q, clk, rst, set, clr; + (* ivl_synthesis_on *) + always@(posedge clk or posedge rst) + begin + if (rst) + Q <= 1'b0; + else if (clr) + Q <= 1'b0; + else if (set) + Q <= 1'b1; + else + Q <= Q; + end + + (* ivl_synthesis_off *) + initial begin + clk = 0; + rst = 0; + set = 0; + clr = 0; + + #1 rst = 1; + #1 rst = 0; + + if (Q !== 0) begin + $display("FAILED -- rst"); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin + $display("FAILED -- 1 clk"); + $finish; + end + + #1 set = 1; + #1 ; + + if (Q !== 0) begin + $display("FAILED -- 1 set (no clk)"); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1) begin + $display("FAILED -- 1 set"); + $finish; + end + + #1 clr = 1; + #1 ; + + if (Q !== 1) begin + $display("FAILED -- 1 clr+set (no clk)"); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin + $display("FAILED -- 1 clr+set"); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin + $display("FAILED -- 2 clr+set"); + $finish; + end + + #1 set = 1; + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin + $display("FAILED -- 1 set+clr"); + $finish; + end + + #1 clr = 0; + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1) begin + $display("FAILED -- 1 set-clr"); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/ssetclr2.v b/ivtest/ivltests/ssetclr2.v new file mode 100644 index 000000000..2d7e7ccfb --- /dev/null +++ b/ivtest/ivltests/ssetclr2.v @@ -0,0 +1,107 @@ +/* + * In this example, the set and clr are both synchronous. This checks + * that this complex case is handled correctly. + */ +module main; + + + reg Q, clk, rst, set, clr; + (* ivl_synthesis_on *) + always@(posedge clk or posedge rst) + begin + if (rst) + Q <= 1'b0; + else if (set) + Q <= 1'b1; + else if (clr) + Q <= 1'b0; + else + Q <= Q; + end + + (* ivl_synthesis_off *) + initial begin + clk = 0; + rst = 0; + set = 0; + clr = 0; + + #1 rst = 1; + #1 rst = 0; + + if (Q !== 0) begin + $display("FAILED -- rst"); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin + $display("FAILED -- 1 clk"); + $finish; + end + + #1 set = 1; + #1 ; + + if (Q !== 0) begin + $display("FAILED -- 1 set (no clk)"); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1) begin + $display("FAILED -- 1 set"); + $finish; + end + + #1 clr = 1; + #1 ; + + if (Q !== 1) begin + $display("FAILED -- 1 clr+set (no clk)"); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1) begin + $display("FAILED -- 1 clr+set"); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1) begin + $display("FAILED -- 2 clr+set"); + $finish; + end + + #1 set = 0; + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin + $display("FAILED -- 1 clr-set"); + $finish; + end + + #1 clr = 0; + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin + $display("FAILED -- 1 set-clr"); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/ssetclr3.v b/ivtest/ivltests/ssetclr3.v new file mode 100644 index 000000000..6d1899dde --- /dev/null +++ b/ivtest/ivltests/ssetclr3.v @@ -0,0 +1,105 @@ +/* + * In this example, the set and clr are both synchronous. This checks + * that this complex case is handled correctly. + */ +module main; + + + reg Q, clk, rst, set, clr; + (* ivl_synthesis_on *) + always@(posedge clk or posedge rst) + begin + if (rst) + Q <= 1'b0; + else if (set) + Q <= 1'b1; + else if (clr) + Q <= 1'b0; + end + + (* ivl_synthesis_off *) + initial begin + clk = 0; + rst = 0; + set = 0; + clr = 0; + + #1 rst = 1; + #1 rst = 0; + + if (Q !== 0) begin + $display("FAILED -- rst"); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin + $display("FAILED -- 1 clk"); + $finish; + end + + #1 set = 1; + #1 ; + + if (Q !== 0) begin + $display("FAILED -- 1 set (no clk)"); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1) begin + $display("FAILED -- 1 set"); + $finish; + end + + #1 clr = 1; + #1 ; + + if (Q !== 1) begin + $display("FAILED -- 1 clr+set (no clk)"); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1) begin + $display("FAILED -- 1 clr+set"); + $finish; + end + + #1 clk = 1; + #1 clk = 0; + + if (Q !== 1) begin + $display("FAILED -- 2 clr+set"); + $finish; + end + + #1 set = 0; + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin + $display("FAILED -- 1 clr-set"); + $finish; + end + + #1 clr = 0; + #1 clk = 1; + #1 clk = 0; + + if (Q !== 0) begin + $display("FAILED -- 1 set-clr"); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/sshortint_test.v b/ivtest/ivltests/sshortint_test.v new file mode 100644 index 000000000..e52130177 --- /dev/null +++ b/ivtest/ivltests/sshortint_test.v @@ -0,0 +1,357 @@ +// Eleven basic tests in here: +// 1. shortint must be initialised before any initial or always block +// 2. assignments to (signed) shortint with random numbers +// 3. assignments to (signed) shortint with random values including X and Z +// 4. converting unsigned integers to signed shortint +// 5. converting signed integers to signed shortint +// 6. converting integers including X and Z states to signed shortint +// 7. trying signed sums (procedural, function, task and module) +// 8. trying signed mults (procedural, function and task) +// 9. trying relational operators +// 10. smaller signed numbers to signed shortint (signed extension) +// 11. trying some concatenations from bytes to shortints + +module ms_add (input shortint signed a, b, output shortint signed sc, ss); + assign sc = a + b; + always @(a, b) ss = a + b; +endmodule + +module main; + parameter N_REPS = 500; // repetition with random numbers + parameter XZ_REPS = 500; // repetition with 'x 'z values + parameter UMAX = 'h7fff; + parameter MAX8 = 256; + parameter LEN = 16; + // variables used as golden references + reg signed [LEN-1:0] ar; // holds numbers + reg signed [LEN-1:0] ar_xz; // holds 'x and/or 'z in random positions + reg signed [LEN-1:0] ar_expected; + integer unsigned ui; + integer signed si; + reg signed [LEN/2-1:0] slice; + + // type assumed to be tested before hand + byte signed pt1, pt2; + + // types to be tested + shortint signed bu; // holds numbers + shortint signed bu_xz; // 'x and 'z are attempted on this + shortint signed bresult; // hold results from sums and mults + shortint signed mcaresult; // wired to a module instance + shortint signed mabresult; // also wired to a module instance + + integer i; + + // continuous assigments + // type LHS type RHS + // --------- --------- + // shortint 4-value logic + assign bu = ar; + assign bu_xz = ar_xz; + + // module instantiation + ms_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) ); + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 16'b0 || bu_xz != 16'b0 || mcaresult !== 16'b0 || mabresult !== 16'b0) + begin + $display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz); + $finish; + end + // driving shortint type with signed random numbers from a variable + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = $random % UMAX; + #1; + if (bu !== ar) + begin + $display ("FAILED - incorrect assigment to shortint: %b", bu); + $finish; + end + end + # 1; + // attempting to drive variables having 'x 'z values into type signed shortint + // 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + ar = $random % UMAX; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect assigment to shortint (when 'x 'z): %b", bu); + $finish; + end + end + // converting unsigned integers to signed shortint + // truncation expected (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ui = {$random} % 2*(UMAX+1); // full range as unsigned + #1; + force bu = ui; + #1; + if (bu !== ui[LEN-1:0]) + begin + $display ("FAILED - incorrect truncation from unsigned integer to shortint: %b", bu); + $finish; + end + end + release bu; + // converting signed integers to signed shortints + // truncation expected (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + si = $random % UMAX; + #1; + force bu = si; + #1; + if (bu !== si[LEN-1:0]) + begin + $display ("FAILED - incorrect truncation from signed integer to shortint: %b mismatchs %b", bu, si[LEN-1:0]); + $finish; + end + end + release bu; + // converting signed integers having 'x 'z values into type signed shortint + // 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM) + // truncation and coercion to zero expected + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + si = $random; + ar_xz = xz_inject (si[LEN-1:0]); + si = {si[31:LEN], ar_xz}; + ar_expected = xz_expected (ar_xz); + #1; + force bu_xz = si; + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect conversion from integer (with 'x 'z) to shortint: %b mismatchs %b", bu_xz, ar_expected); + $finish; + end + end + release bu_xz; + // trying signed sums + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = $random % UMAX; + ar_xz = $random % UMAX; + #1; + bresult = bu + bu_xz; + #1; + if ( bresult !== s_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of signed shortints: %0d mismatchs %0d", bresult, s_sum(ar, ar_xz)); + $finish; + end + // invoking shortint sum function + if ( fs_sum (bu, bu_xz) !== s_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of signed shortint in function"); + $finish; + end + // invoking shortint sum task + ts_sum (bu, bu_xz, bresult); + if ( bresult !== s_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of signed shortint in task: %0d mismatchs %0d", bresult, s_sum(ar, ar_xz)); + $finish; + end + // checking shortint sum from module + if ( mcaresult !== s_sum(ar, ar_xz) || mabresult !== s_sum(ar, ar_xz)) + begin + $display ("FAILED - incorrect addition of signed shortint from module"); + $finish; + end + end + // trying signed mults + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = ($random % UMAX) << LEN/2; + ar_xz = ($random % UMAX) << (LEN/2 - 1); + #1; + bresult = bu * bu_xz; // truncated multiplication + #1; + if ( bresult !== sh_mul(ar, ar_xz) ) + begin + $display ("FAILED - incorrect multiplication of signed shortints (truncated)"); + $finish; + end + #1; + pt1 = $random; + pt2 = $random; + #1; + bresult = pt1 * pt2; // shortint = byte x byte + #1; + if ( bresult !== s_mul(pt1, pt2) ) + begin + $display ("FAILED - incorrect multiplication of signed shortints for input bytes"); + $finish; + end + // invoking shortint mult function (byte*byte) + if ( fs_mul (pt1, pt2) !== s_mul(pt1, pt2) ) + begin + $display ("FAILED - incorrect product of signed bytes for a function returning signed shortint"); + $finish; + end + // invoking shortint mult task (byte*byte) + ts_mul (pt1, pt2, bresult); + if ( bresult !== s_mul(pt1, pt2) ) + begin + $display ("FAILED - incorrect product of signed bytes in task returning signed shortint"); + $finish; + end + end + // trying relational operators + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = $random % UMAX; + ar_xz = $random % UMAX; + #1; + if ( (bu < bu_xz ) !== (ar < ar_xz) ) + begin + $display ("FAILED - incorrect 'less than' on signed shortints"); + $finish; + end + if ( (bu <= bu_xz ) !== (ar <= ar_xz) ) + begin + $display ("FAILED - incorrect 'less than or equal' on signed shortints"); + $finish; + end + if ( (bu > bu_xz ) !== (ar > ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than' on signed shortints"); + $finish; + end + if ( (bu >= bu_xz ) !== (ar >= ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than or equal' than on signed shortints"); + $finish; + end + if ( (bu == bu_xz ) !== (ar == ar_xz) ) + begin + $display ("FAILED - incorrect 'equal to' on signed shortints"); + $finish; + end + if ( (bu != bu_xz ) !== (ar != ar_xz) ) + begin + $display ("FAILED - incorrect 'not equal to' on signed shortints"); + $finish; + end + end + # 1; + // signed small number to signed shorint + for (i = 0; i < (1<|This is a test|"); + $display("*|%s|", "This is a test"); + $display("*|", "This is a test", "|"); + + $display(">| 65|"); + $display("*|%d|", "A"); + $display(">|16706|"); + $display("*|%d|", "AB"); + $display(">| 4276803|"); + $display("*|%d|", "ABC"); + $display(">|1094861636|"); + $display("*|%d|", "ABCD"); + + $display(">|01000001|"); + $display("*|%b|", "A"); + $display(">|01000001010000100100001101000100|"); + $display("*|%b|", "ABCD"); + $display(">|01000001010000100100001101000100010010000100100101001010010010110100110001001101010011100100111101010000010100010101001001010011|"); + $display("*|%b|", "ABCDHIJKLMNOPQRS"); + + $display(">|41|"); + $display("*|%h|", "A"); + $display(">|41424344|"); + $display("*|%h|", "ABCD"); + $display(">|4142434448494a4b4c4d4e4f50515253|"); + $display("*|%h|", "ABCDHIJKLMNOPQRS"); + end +endmodule diff --git a/ivtest/ivltests/string11.v b/ivtest/ivltests/string11.v new file mode 100644 index 000000000..573b97a97 --- /dev/null +++ b/ivtest/ivltests/string11.v @@ -0,0 +1,10 @@ +module main; + + reg [31:0] bytes; + + initial begin + bytes = "\101\102\103\n"; + $write("bytes=%h\n", bytes); + $finish(0); + end +endmodule // main diff --git a/ivtest/ivltests/string12.v b/ivtest/ivltests/string12.v new file mode 100644 index 000000000..70409546f --- /dev/null +++ b/ivtest/ivltests/string12.v @@ -0,0 +1,9 @@ +module top; + + initial begin + if ("this matches" == "this\ + matches") $display("PASSED"); + else $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/string2.v b/ivtest/ivltests/string2.v new file mode 100644 index 000000000..88bb98c1e --- /dev/null +++ b/ivtest/ivltests/string2.v @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* This tests the printing of a string stored in a reg. */ + +module main; + + reg [8*6:1] foo; + + initial + begin + foo = "PASSED"; + $display("%s", foo); + end + +endmodule // main diff --git a/ivtest/ivltests/string3.v b/ivtest/ivltests/string3.v new file mode 100644 index 000000000..fdb908f54 --- /dev/null +++ b/ivtest/ivltests/string3.v @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* This tests the printing of a string stored in a reg, with leading blanks. */ + +module main; + + reg [8*7:1] foo; + reg [7:0] tmp; + + + initial + begin + foo = "PASSED"; + tmp = foo[8*7:8*6+1]; + + if (tmp !== 8'h00) begin + $display("FAILED -- high bits are %b", tmp); + $finish; + end + $display("%s", foo); + end + +endmodule // main diff --git a/ivtest/ivltests/string4.v b/ivtest/ivltests/string4.v new file mode 100644 index 000000000..bc859b7a8 --- /dev/null +++ b/ivtest/ivltests/string4.v @@ -0,0 +1,49 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - assign a string in a function +// +// This test was contributed via forwarding on the geda netlist. I don't +// know who actually wrote it - that isn't obvious from the copy of email +// I eventually received - SDW +// + +module test(); +wire [31:0] A; +reg [31:0] B; + +function [31:0] message; + input [1:0] reg_num; + begin + message = (reg_num == 2'b00) ? "Mes0": + (reg_num == 2'b01) ? "Mes1": + (reg_num == 2'b10) ? "Mes2": + "Mes3"; + end +endfunction + +assign A = "hi"; +initial + begin + B = "ho"; + #1; + $display ("%s", A); + $display ("%s", message(1)); + $finish(0); + end +endmodule diff --git a/ivtest/ivltests/string5.v b/ivtest/ivltests/string5.v new file mode 100644 index 000000000..a87ee8955 --- /dev/null +++ b/ivtest/ivltests/string5.v @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2001 Philip Blundell + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module m; + +task t; + input [255:0] s; + begin + $display("%s", s); + end +endtask + +initial + begin + t("Hello world of Verilog"); + end + +endmodule diff --git a/ivtest/ivltests/string7.v b/ivtest/ivltests/string7.v new file mode 100644 index 000000000..34aa6b8f6 --- /dev/null +++ b/ivtest/ivltests/string7.v @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2002 Tom Verbeure + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + integer myInt; + reg [39:0] myReg40; + reg [0:39] myReg40r; + reg [0:38] myReg39r; + reg [13:0] myReg14; + reg [7:0] myReg8; + + initial begin + $display("============================ myReg8 = 65"); + myReg8 = 65; + $display(">|A|"); + $display("*|%s|", myReg8); + + $display("============================ myReg40 = \"12345\""); + myReg40 = "12345"; + + $display(">|12345|"); + $display("*|%s|", myReg40); + $display(">|5|"); + $display("*|%s|", myReg40[7:0]); + + $display("============================ myReg40r = \"12345\""); + myReg40r = "12345"; + + $display(">|12345|"); + $display("*|%s|", myReg40r); + $display(">|1|"); + $display("*|%s|", myReg40r[0:7]); + + $display("============================ myReg39r = \"12345\""); + myReg39r = "12345"; + + $display(">|12345|"); + $display("*|%s|", myReg39r); + $display(">|b|"); + $display("*|%s|", myReg39r[0:7]); + + $display("============================ myReg14 = 65"); + myReg14 = 65; + + $display(">| A|"); + $display("*|%s|", myReg14); + + $display("============================ myReg14 = 33*356+65"); + myReg14 = 33*256 + 65; + $display(">|!A|"); + $display("*|%s|", myReg14); + + $display("============================ myInt = 65"); + myInt = 65; + + $display(">| A|"); + $display("*|%s|", myInt); + end +endmodule diff --git a/ivtest/ivltests/string8.v b/ivtest/ivltests/string8.v new file mode 100644 index 000000000..db24af4d0 --- /dev/null +++ b/ivtest/ivltests/string8.v @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2002 Tom Verbeure + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg [13:0] myReg14; + reg [15:0] myReg16; + + initial begin + $display("============================ myReg14 = 33*256+65"); + myReg14 = 33*256 + 65; + $display(">|!A|"); + $display("*|%s|", myReg14); + $display(">|!|"); + $display("*|%s|", myReg14[13:8]); + $display("============================ myReg16 = 33*512+65*2"); + myReg16 = 33*512 + 65*2; + $display(">|!A|"); + $display("*|%s|", myReg16[14:1]); + end +endmodule diff --git a/ivtest/ivltests/string9.v b/ivtest/ivltests/string9.v new file mode 100644 index 000000000..1db613e01 --- /dev/null +++ b/ivtest/ivltests/string9.v @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2002 Tom Verbeure + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + integer myInt; + reg [39:0] myReg40; + reg [0:39] myReg40r; + reg [0:38] myReg39r; + reg [13:0] myReg14; + reg [7:0] myReg8; + + initial begin + $display("============================ myReg8 = 65"); + myReg8 = 65; + $display(">|A|"); + $display("*|%c|", myReg8); + + $display("============================ myReg40 = \"12345\""); + myReg40 = "12345"; + + $display(">|5|"); + $display("*|%c|", myReg40); + $display(">|5|"); + $display("*|%s|", myReg40[7:0]); + + $display("============================ myReg40r = \"12345\""); + myReg40r = "12345"; + + $display(">|5|"); + $display("*|%c|", myReg40r); + $display(">|1|"); + $display("*|%c|", myReg40r[0:7]); + + $display("============================ myReg39r = \"12345\""); + myReg39r = "12345"; + + $display(">|5|"); + $display("*|%c|", myReg39r); + $display(">|b|"); + $display("*|%c|", myReg39r[0:7]); + + $display("============================ myReg14 = 33*256+65"); + myReg14 = 33*256 + 65; + $display(">|A|"); + $display("*|%c|", myReg14); + $display(">|!|"); + $display("*|%c|", myReg14[13:8]); + + $display("============================ myInt = 66*256 + 65"); + myInt = 66*256 + 65; + + $display(">|A|"); + $display("*|%c|", myInt); + end +endmodule diff --git a/ivtest/ivltests/string_events.v b/ivtest/ivltests/string_events.v new file mode 100644 index 000000000..d0a62aed9 --- /dev/null +++ b/ivtest/ivltests/string_events.v @@ -0,0 +1,43 @@ +module test(); + +string str; + +always @(str) begin + $display("str = %s", str); +end + +task automatic test_task(input integer delay, input string str1, input string str2); + +string str; + +fork + begin + @(str) $display("str%0d = %s", delay, str); + @(str) $display("str%0d = %s", delay, str); + end + begin + #delay; + #2 str = str1; + #2 str = str1; + #2 str = str2; + end +join + +endtask + +initial begin + #1 str = "hello"; + #1 str = "hello"; + #1 str = "world"; + fork + test_task(1, "hello1", "world1"); + test_task(2, "hello2", "world2"); + join + fork + test_task(1, "world1", "hello1"); + test_task(2, "world2", "hello2"); + join + #1 $finish(0); +end + +endmodule diff --git a/ivtest/ivltests/string_index.v b/ivtest/ivltests/string_index.v new file mode 100644 index 000000000..6077e518a --- /dev/null +++ b/ivtest/ivltests/string_index.v @@ -0,0 +1,44 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Tests accessing individual characters in a string + +module string_index(); + +initial begin + int i; + string str = "that is a test string"; + + for(i = 0; i < $size(str); ++i) + begin + if(str[i] == "t") + str[i] = "w"; + end + + if(str != "whaw is a wesw swring") + begin + $display("FAILED"); + $finish(); + end + + $display("PASSED"); +end + +endmodule + diff --git a/ivtest/ivltests/struct1.v b/ivtest/ivltests/struct1.v new file mode 100644 index 000000000..617026280 --- /dev/null +++ b/ivtest/ivltests/struct1.v @@ -0,0 +1,26 @@ +module main; + + struct packed { + logic [7:0] high; + logic [7:0] low; + } word1, word2; + + initial begin + word1 = 16'haa_55; + if (word1.high !== 8'haa || word1.low !== 8'h55) begin + $display("FAILED: word1 = %h, word1.high = %h, word1.low = %h", + word1, word1.high, word1.low); + $finish; + end + + word2 = word1; + if (word2.high !== 8'haa || word2.low !== 8'h55) begin + $display("FAILED: word2 = %h, word2.high = %h, word2.low = %h", + word1, word2.high, word2.low); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/struct2.v b/ivtest/ivltests/struct2.v new file mode 100644 index 000000000..d9e403113 --- /dev/null +++ b/ivtest/ivltests/struct2.v @@ -0,0 +1,36 @@ +module main; + + // Declare word1 as a VARIABLE + struct packed { + logic [7:0] high; + logic [7:0] low; + } word1; + + // Declare word2 as a NET + wire struct packed { + logic [7:0] high; + logic [7:0] low; + } word2; + + assign word2 = word1; + + initial begin + word1 = 16'haa_55; + if (word1.high !== 8'haa || word1.low !== 8'h55) begin + $display("FAILED: word1 = %h, word1.high = %h, word1.low = %h", + word1, word1.high, word1.low); + $finish; + end + + #1 /* Make sure word2 assign propagates */; + + if (word2.high !== 8'haa || word2.low !== 8'h55) begin + $display("FAILED: word2 = %h, word2.high = %h, word2.low = %h", + word1, word2.high, word2.low); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/struct3.v b/ivtest/ivltests/struct3.v new file mode 100644 index 000000000..5255d94de --- /dev/null +++ b/ivtest/ivltests/struct3.v @@ -0,0 +1,37 @@ +module main; + + // Declare word1 as a VARIABLE + struct packed { + logic [7:0] high; + logic [7:0] low; + } word1; + + // Declare word2 as a NET + wire struct packed { + logic [7:0] high; + logic [7:0] low; + } word2; + + assign word2.high = word1.high; + assign word2.low = word1.low; + + initial begin + word1 = 16'haa_55; + if (word1.high !== 8'haa || word1.low !== 8'h55) begin + $display("FAILED: word1 = %h, word1.high = %h, word1.low = %h", + word1, word1.high, word1.low); + $finish; + end + + #1 /* Make sure word2 assign propagates */; + + if (word2.high !== 8'haa || word2.low !== 8'h55) begin + $display("FAILED: word2 = %h, word2.high = %h, word2.low = %h", + word1, word2.high, word2.low); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/struct3b.v b/ivtest/ivltests/struct3b.v new file mode 100644 index 000000000..1a1be5b72 --- /dev/null +++ b/ivtest/ivltests/struct3b.v @@ -0,0 +1,45 @@ +module main; + + // Declare word1 as a VARIABLE + struct packed { + logic [7:0] high; + logic [7:0] low; + } word1; + + // Declare word2, word3 as a NET + wire struct packed { + logic [7:0] high; + logic [7:0] low; + } word2, word3; + + assign word2.high = word1.high; + assign word2.low = word1.low; + assign {word3.high, word3.low} = {word1.low, word1.high}; + + initial begin + word1 = 16'haa_55; + if (word1.high !== 8'haa || word1.low !== 8'h55) begin + $display("FAILED: word1 = %h, word1.high = %h, word1.low = %h", + word1, word1.high, word1.low); + $finish; + end + + #1 /* Make sure word2 assign propagates */; + + if (word2.high !== 8'haa || word2.low !== 8'h55) begin + $display("FAILED: word2 = %h, word2.high = %h, word2.low = %h", + word1, word2.high, word2.low); + $finish; + end + + /* and also for word3 */ + if (word3.low !== 8'haa || word3.high !== 8'h55) begin + $display("FAILED: word3 = %h, word3.high = %h, word3.low = %h (should be reverse)", + word1, word3.high, word3.low); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/struct4.v b/ivtest/ivltests/struct4.v new file mode 100644 index 000000000..47b315e61 --- /dev/null +++ b/ivtest/ivltests/struct4.v @@ -0,0 +1,39 @@ +module main; + + // Declare word1 as a VARIABLE + struct packed { + logic [7:0] high; + logic [7:0] low; + } word1; + + // Declare word2 as a VARIABLE + struct packed { + logic [7:0] high; + logic [7:0] low; + } word2; + + always @(word1) begin + word2.high = word1.high; + word2.low = word1.low; + end + + initial begin + word1 = 16'haa_55; + if (word1.high !== 8'haa || word1.low !== 8'h55) begin + $display("FAILED: word1 = %h, word1.high = %h, word1.low = %h", + word1, word1.high, word1.low); + $finish; + end + + #1 /* Make sure word2 assign propagates */; + + if (word2.high !== 8'haa || word2.low !== 8'h55) begin + $display("FAILED: word2 = %h, word2.high = %h, word2.low = %h", + word1, word2.high, word2.low); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/struct5.v b/ivtest/ivltests/struct5.v new file mode 100644 index 000000000..90efe7ccc --- /dev/null +++ b/ivtest/ivltests/struct5.v @@ -0,0 +1,38 @@ +module main; + + typedef struct packed { + logic [7:0] high; + logic [7:0] low; + } word_t; + + // Declare word1 as a VARIABLE + word_t word1; + + // Declare word2 as a VARIABLE + word_t word2; + + always @(word1) begin + word2.high = word1.high; + word2.low = word1.low; + end + + initial begin + word1 = 16'haa_55; + if (word1.high !== 8'haa || word1.low !== 8'h55) begin + $display("FAILED: word1 = %h, word1.high = %h, word1.low = %h", + word1, word1.high, word1.low); + $finish; + end + + #1 /* Make sure word2 assign propagates */; + + if (word2.high !== 8'haa || word2.low !== 8'h55) begin + $display("FAILED: word2 = %h, word2.high = %h, word2.low = %h", + word1, word2.high, word2.low); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/struct6.v b/ivtest/ivltests/struct6.v new file mode 100644 index 000000000..fc750ab86 --- /dev/null +++ b/ivtest/ivltests/struct6.v @@ -0,0 +1,23 @@ +// This tests that the individual bits of a uwire are checked for +// double-driving individually. The code below uses a packed struct +// to represent individual bits. +module test; + + struct packed { + logic [15:0] hig; + logic [15:0] low; + } foo; + + assign foo.low = 'haaaa; + assign foo.hig = 'h5555; + + initial begin + #1 if (foo !== 'h5555aaaa) begin + $display("FAILED -- foo=%h", foo); + $finish; + end + + $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/struct7.v b/ivtest/ivltests/struct7.v new file mode 100644 index 000000000..8d85a1d76 --- /dev/null +++ b/ivtest/ivltests/struct7.v @@ -0,0 +1,52 @@ +module main; + + struct packed { + logic [1:0][7:0] p; + } val; + + logic [1:0][7:0] arr; + + initial begin + arr[0] = 'haa; + arr[1] = 'h55; + $display("arr = %h", arr); + if (arr !== 'h55_aa) begin + $display("FAILED"); + $finish; + end + + if (arr[0] !== 'haa) begin + $display("FAILED -- arr[0]=%h", arr[0]); + $finish; + end + if (arr[1] !== 'h55) begin + $display("FAILED -- arr[1]=%h", arr[1]); + $finish; + end + + val.p[0] = 'haa; + val.p[1] = 'h55; + $display("val.p = %h", val.p); + $display("val = %h", val); + if (val !== 'h55_aa) begin + $display("FAILED"); + $finish; + end + if (val.p !== 'h55_aa) begin + $display("FAILED"); + $finish; + end + + if (val.p[0] !== 'haa) begin + $display("FAILED -- val.p[0]=%h", val.p[0]); + $finish; + end + if (val.p[1] !== 'h55) begin + $display("FAILED -- val.p[1]=%h", val.p[1]); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/struct8.v b/ivtest/ivltests/struct8.v new file mode 100644 index 000000000..a664149ac --- /dev/null +++ b/ivtest/ivltests/struct8.v @@ -0,0 +1,31 @@ +module main; + + wire struct packed { + logic m1; + logic [7:0] m8; + } foo; + + assign foo = {1'b1, 8'ha5}; + + struct packed { + logic [3:0] m4; + logic [7:0] m8; + } bar; + + initial begin + #1 /* wait for logic to settle. */; + bar.m8 <= foo.m8[7:0]; + bar.m4 <= foo.m8[7:4]; + #1 $display("bar8=%h, bar4=%h", bar.m8, bar.m4); + if (bar.m8 !== 8'ha5) begin + $display("FAILED"); + $finish; + end + if (bar.m4 !== 4'ha) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/struct9.v b/ivtest/ivltests/struct9.v new file mode 100644 index 000000000..52be60904 --- /dev/null +++ b/ivtest/ivltests/struct9.v @@ -0,0 +1,27 @@ + +module main; + + wire [4:0] foo; + struct packed { + logic [3:0] bar4; + logic [3:0] bar0; + } bar; + + assign foo = bar.bar0; + + initial begin + bar = 'h5a; + #1 if (bar.bar0 !== 4'ha || bar.bar4 != 4'h5) begin + $display("FAILED -- bar.bar0=%b, bar.bar4=%b", bar.bar0, bar.bar4); + $finish; + end + + if (foo !== 5'h0a) begin + $display("FAILED -- foo=%b", foo); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/struct_packed_array.v b/ivtest/ivltests/struct_packed_array.v new file mode 100644 index 000000000..bbee4fae0 --- /dev/null +++ b/ivtest/ivltests/struct_packed_array.v @@ -0,0 +1,78 @@ +module main; + + typedef struct packed { + logic [3:0] high; + logic [3:0] low; + } word; + + typedef word [1:0] dword; + + dword foo; + int idx; + + initial begin + foo[0].low = 1; + foo[0].high = 2; + foo[1].low = 3; + foo[1].high = 4; + $display("foo = %h", foo); + + if (foo !== 16'h4321) begin + $display("FAILED -- foo=%h", foo); + $finish; + end + + $display("foo[0] = %h", foo[0]); + if (foo[0] !== 8'h21) begin + $display("FAILED -- foo[0]=%h", foo[0]); + $finish; + end + + $display("foo[1] = %h", foo[1]); + if (foo[1] !== 8'h43) begin + $display("FAILED -- foo[1]=%h", foo[1]); + $finish; + end + + $display("foo[0].low = %h", foo[0].low); + if (foo[0].low !== 4'h1) begin + $display("FAILED -- foo[0].low=%h", foo[0].low); + $finish; + end + + $display("foo[0].high = %h", foo[0].high); + if (foo[0].high !== 4'h2) begin + $display("FAILED -- foo[0].high=%h", foo[0].high); + $finish; + end + + $display("foo[1].low = %h", foo[1].low); + if (foo[1].low !== 4'h3) begin + $display("FAILED -- foo[1].low=%h", foo[1].low); + $finish; + end + + $display("foo[1].high = %h", foo[1].high); + if (foo[1].high !== 4'h4) begin + $display("FAILED -- foo[1].high=%h", foo[1].high); + $finish; + end + + idx = 0; + $display("foo[idx=0].low = %h", foo[idx].low); + if (foo[idx].low !== 4'h1) begin + $display("FAILED -- foo[0].low=%h", foo[idx].low); + $finish; + end + + idx = 1; + $display("foo[idx=1].high = %h", foo[idx].high); + if (foo[idx].high !== 8'h4) begin + $display("FAILED -- foo[1].high=%h", foo[idx].high); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/struct_packed_array2.v b/ivtest/ivltests/struct_packed_array2.v new file mode 100644 index 000000000..360b28a19 --- /dev/null +++ b/ivtest/ivltests/struct_packed_array2.v @@ -0,0 +1,79 @@ +module main; + + typedef struct packed { + logic [3:0] high; + logic [3:0] low; + } word; + + typedef word [1:0] dword; + + wire dword foo; + int idx; + + assign foo[0].low = 1; + assign foo[0].high = 2; + assign foo[1].low = 3; + assign foo[1].high = 4; + + initial begin + #1 $display("foo = %h", foo); + + if (foo !== 16'h4321) begin + $display("FAILED -- foo=%h", foo); + $finish; + end + + $display("foo[0] = %h", foo[0]); + if (foo[0] !== 8'h21) begin + $display("FAILED -- foo[0]=%h", foo[0]); + $finish; + end + + $display("foo[1] = %h", foo[1]); + if (foo[1] !== 8'h43) begin + $display("FAILED -- foo[1]=%h", foo[1]); + $finish; + end + + $display("foo[0].low = %h", foo[0].low); + if (foo[0].low !== 4'h1) begin + $display("FAILED -- foo[0].low=%h", foo[0].low); + $finish; + end + + $display("foo[0].high = %h", foo[0].high); + if (foo[0].high !== 4'h2) begin + $display("FAILED -- foo[0].high=%h", foo[0].high); + $finish; + end + + $display("foo[1].low = %h", foo[1].low); + if (foo[1].low !== 4'h3) begin + $display("FAILED -- foo[1].low=%h", foo[1].low); + $finish; + end + + $display("foo[1].high = %h", foo[1].high); + if (foo[1].high !== 4'h4) begin + $display("FAILED -- foo[1].high=%h", foo[1].high); + $finish; + end + + idx = 0; + $display("foo[idx=0].low = %h", foo[idx].low); + if (foo[idx].low !== 4'h1) begin + $display("FAILED -- foo[0].low=%h", foo[idx].low); + $finish; + end + + idx = 1; + $display("foo[idx=1].high = %h", foo[idx].high); + if (foo[idx].high !== 8'h4) begin + $display("FAILED -- foo[1].high=%h", foo[idx].high); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/struct_packed_sysfunct.v b/ivtest/ivltests/struct_packed_sysfunct.v new file mode 100644 index 000000000..3664dc1df --- /dev/null +++ b/ivtest/ivltests/struct_packed_sysfunct.v @@ -0,0 +1,27 @@ +// This tests system functions available for packed structures +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test; + + typedef struct packed { + logic [7:0] high; + logic [7:0] low; + } word_t; + + // Declare word0 as a VARIABLE + word_t word0; + + // error counter + bit err = 0; + + initial begin + if ($bits(word0 ) !== 16) begin $display("FAILED -- $bits(word0 ) = %d", $bits(word0 )); err=1; end + if ($bits(word0.high) !== 8) begin $display("FAILED -- $bits(word0.high) = %d", $bits(word0.high)); err=1; end + if ($bits(word0.low ) !== 8) begin $display("FAILED -- $bits(word0.low ) = %d", $bits(word0.low )); err=1; end + + if (!err) $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/struct_packed_value_list.v b/ivtest/ivltests/struct_packed_value_list.v new file mode 100644 index 000000000..84eae8c9a --- /dev/null +++ b/ivtest/ivltests/struct_packed_value_list.v @@ -0,0 +1,40 @@ +// This tests assigning value lists to packed structures +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test; + + typedef struct packed { + logic [7:0] high; + logic [7:0] low; + } word_t; + + // Declare word* as a VARIABLE + word_t word0, word1, word2, word3, word4, word5; + + // error counter + bit err = 0; + + // access to structure elements + assign word0 = '{2, 3}; + assign word1 = '{high:5, low:6}; + assign word2 = '{low:7, high:8}; + assign word3 = '{default:13}; + assign word4 = '{high:8'haa, default:1}; + assign word5 = '{high:9'h000, low:9'h1ff}; + + initial begin + #1; + // check for correctness + if (word0 !== 16'b00000010_00000011) begin $display("FAILED -- word0 = 'b%b", word0); err=1; end + if (word1 !== 16'b00000101_00000110) begin $display("FAILED -- word1 = 'b%b", word1); err=1; end + if (word2 !== 16'b00001000_00000111) begin $display("FAILED -- word2 = 'b%b", word2); err=1; end + if (word3 !== 16'b00001101_00001101) begin $display("FAILED -- word3 = 'b%b", word3); err=1; end + if (word4 !== 16'b10101010_00000001) begin $display("FAILED -- word4 = 'b%b", word4); err=1; end + if (word5 !== 16'b00000000_11111111) begin $display("FAILED -- word5 = 'b%b", word5); err=1; end + + if (!err) $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/struct_packed_write_read.v b/ivtest/ivltests/struct_packed_write_read.v new file mode 100644 index 000000000..435d20020 --- /dev/null +++ b/ivtest/ivltests/struct_packed_write_read.v @@ -0,0 +1,83 @@ +// This tests unalligned write/read access to packed structures +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test; + + typedef struct packed { + logic [7:0] high; + logic [7:0] low; + } word_t; + + // Declare word* as a VARIABLE + word_t word_se0, word_se1, word_se2, word_se3; + word_t word_sw0, word_sw1, word_sw2, word_sw3; + word_t word_sp0, word_sp1, word_sp2, word_sp3; + word_t word_ep0, word_ep1, word_ep2, word_ep3; + + // error counter + bit err = 0; + + // access to structure elements + assign word_se1.high = {8+0{1'b1}}; + assign word_se1.low = {8+0{1'b0}}; + assign word_se2.high = {8+1{1'b1}}; + assign word_se2.low = {8+1{1'b0}}; + assign word_se3.high = {8-1{1'b1}}; + assign word_se3.low = {8-1{1'b0}}; + // access to whole structure + assign word_sw1 = {16+0{1'b1}}; + assign word_sw2 = {16+1{1'b1}}; + assign word_sw3 = {16-1{1'b1}}; + // access to parts of structure elements + assign word_ep1.high [3:0] = {4+0{1'b1}}; + assign word_ep1.low [3:0] = {4+0{1'b0}}; + assign word_ep2.high [3:0] = {4+1{1'b1}}; + assign word_ep2.low [3:0] = {4+1{1'b0}}; + assign word_ep3.high [3:0] = {4-1{1'b1}}; + assign word_ep3.low [3:0] = {4-1{1'b0}}; + // access to parts of the whole structure + assign word_sp1 [11:4] = {8+0{1'b1}}; + assign word_sp2 [11:4] = {8+1{1'b1}}; + assign word_sp3 [11:4] = {8-1{1'b1}}; + + initial begin + #1; + // access to structure elements + if (word_se0 !== 16'bxxxxxxxx_xxxxxxxx) begin $display("FAILED -- word_se0 = 'b%b", word_se0 ); err=1; end + if (word_se1 !== 16'b11111111_00000000) begin $display("FAILED -- word_se1 = 'b%b", word_se1 ); err=1; end + if (word_se1.high !== 8'b11111111 ) begin $display("FAILED -- word_se1.high = 'b%b", word_se1.high); err=1; end + if (word_se1.low !== 8'b00000000 ) begin $display("FAILED -- word_se1.low = 'b%b", word_se1.low ); err=1; end + if (word_se2 !== 16'b11111111_00000000) begin $display("FAILED -- word_se2 = 'b%b", word_se2 ); err=1; end + if (word_se2.high !== 8'b11111111 ) begin $display("FAILED -- word_se2.high = 'b%b", word_se2.high); err=1; end + if (word_se2.low !== 8'b00000000 ) begin $display("FAILED -- word_se2.low = 'b%b", word_se2.low ); err=1; end + if (word_se3 !== 16'b01111111_00000000) begin $display("FAILED -- word_se3 = 'b%b", word_se3 ); err=1; end + if (word_se3.high !== 8'b01111111 ) begin $display("FAILED -- word_se3.high = 'b%b", word_se3.high); err=1; end + if (word_se3.low !== 8'b00000000 ) begin $display("FAILED -- word_se3.low = 'b%b", word_se3.low ); err=1; end + // access to whole structure + if (word_sw0 !== 16'bxxxxxxxx_xxxxxxxx) begin $display("FAILED -- word_sw0 = 'b%b", word_sw0 ); err=1; end + if (word_sw1 !== 16'b11111111_11111111) begin $display("FAILED -- word_sw1 = 'b%b", word_sw1 ); err=1; end + if (word_sw2 !== 16'b11111111_11111111) begin $display("FAILED -- word_sw2 = 'b%b", word_sw2 ); err=1; end + if (word_sw3 !== 16'b01111111_11111111) begin $display("FAILED -- word_sw3 = 'b%b", word_sw3 ); err=1; end + // access to parts of structure elements + if (word_ep0 !== 16'bxxxxxxxx_xxxxxxxx) begin $display("FAILED -- word_ep0 = 'b%b", word_ep0 ); err=1; end + if (word_ep1 !== 16'bxxxx1111_xxxx0000) begin $display("FAILED -- word_ep1 = 'b%b", word_ep1 ); err=1; end + if (word_ep1.high !== 8'bxxxx1111 ) begin $display("FAILED -- word_ep1.high = 'b%b", word_ep1.high); err=1; end + if (word_ep1.low !== 8'bxxxx0000 ) begin $display("FAILED -- word_ep1.low = 'b%b", word_ep1.low ); err=1; end + if (word_ep2 !== 16'bxxxx1111_xxxx0000) begin $display("FAILED -- word_ep2 = 'b%b", word_ep2 ); err=1; end + if (word_ep2.high !== 8'bxxxx1111 ) begin $display("FAILED -- word_ep2.high = 'b%b", word_ep2.high); err=1; end + if (word_ep2.low !== 8'bxxxx0000 ) begin $display("FAILED -- word_ep2.low = 'b%b", word_ep2.low ); err=1; end + if (word_ep3 !== 16'bxxxx0111_xxxx0000) begin $display("FAILED -- word_ep3 = 'b%b", word_ep3 ); err=1; end + if (word_ep3.high !== 8'bxxxx0111 ) begin $display("FAILED -- word_ep3.high = 'b%b", word_ep3.high); err=1; end + if (word_ep3.low !== 8'bxxxx0000 ) begin $display("FAILED -- word_ep3.low = 'b%b", word_ep3.low ); err=1; end + // access to parts of the whole structure + if (word_sp0 !== 16'bxxxxxxxx_xxxxxxxx) begin $display("FAILED -- word_sp0 = 'b%b", word_sp0 ); err=1; end + if (word_sp1 !== 16'bxxxx1111_1111xxxx) begin $display("FAILED -- word_sp1 = 'b%b", word_sp1 ); err=1; end + if (word_sp2 !== 16'bxxxx1111_1111xxxx) begin $display("FAILED -- word_sp2 = 'b%b", word_sp2 ); err=1; end + if (word_sp3 !== 16'bxxxx0111_1111xxxx) begin $display("FAILED -- word_sp3 = 'b%b", word_sp3 ); err=1; end + + if (!err) $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/struct_packed_write_read2.v b/ivtest/ivltests/struct_packed_write_read2.v new file mode 100644 index 000000000..2e42e4752 --- /dev/null +++ b/ivtest/ivltests/struct_packed_write_read2.v @@ -0,0 +1,83 @@ +// This tests unalligned write/read access to packed structures +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test; + + typedef struct packed { + logic [7:0] high; + logic [7:0] low; + } word_t; + + // Declare word* as a VARIABLE + wire word_t word_se0, word_se1, word_se2, word_se3; + wire word_t word_sw0, word_sw1, word_sw2, word_sw3; + wire word_t word_sp0, word_sp1, word_sp2, word_sp3; + wire word_t word_ep0, word_ep1, word_ep2, word_ep3; + + // error counter + bit err = 0; + + // access to structure elements + assign word_se1.high = {8+0{1'b1}}; + assign word_se1.low = {8+0{1'b0}}; + assign word_se2.high = {8+1{1'b1}}; + assign word_se2.low = {8+1{1'b0}}; + assign word_se3.high = {8-1{1'b1}}; + assign word_se3.low = {8-1{1'b0}}; + // access to whole structure + assign word_sw1 = {16+0{1'b1}}; + assign word_sw2 = {16+1{1'b1}}; + assign word_sw3 = {16-1{1'b1}}; + // access to parts of structure elements + assign word_ep1.high [3:0] = {4+0{1'b1}}; + assign word_ep1.low [3:0] = {4+0{1'b0}}; + assign word_ep2.high [3:0] = {4+1{1'b1}}; + assign word_ep2.low [3:0] = {4+1{1'b0}}; + assign word_ep3.high [3:0] = {4-1{1'b1}}; + assign word_ep3.low [3:0] = {4-1{1'b0}}; + // access to parts of the whole structure + assign word_sp1 [11:4] = {8+0{1'b1}}; + assign word_sp2 [11:4] = {8+1{1'b1}}; + assign word_sp3 [11:4] = {8-1{1'b1}}; + + initial begin + #1; + // access to structure elements + if (word_se0 !== 16'bzzzzzzzz_zzzzzzzz) begin $display("FAILED -- word_se0 = 'b%b", word_se0 ); err=1; end + if (word_se1 !== 16'b11111111_00000000) begin $display("FAILED -- word_se1 = 'b%b", word_se1 ); err=1; end + if (word_se1.high !== 8'b11111111 ) begin $display("FAILED -- word_se1.high = 'b%b", word_se1.high); err=1; end + if (word_se1.low !== 8'b00000000 ) begin $display("FAILED -- word_se1.low = 'b%b", word_se1.low ); err=1; end + if (word_se2 !== 16'b11111111_00000000) begin $display("FAILED -- word_se2 = 'b%b", word_se2 ); err=1; end + if (word_se2.high !== 8'b11111111 ) begin $display("FAILED -- word_se2.high = 'b%b", word_se2.high); err=1; end + if (word_se2.low !== 8'b00000000 ) begin $display("FAILED -- word_se2.low = 'b%b", word_se2.low ); err=1; end + if (word_se3 !== 16'b01111111_00000000) begin $display("FAILED -- word_se3 = 'b%b", word_se3 ); err=1; end + if (word_se3.high !== 8'b01111111 ) begin $display("FAILED -- word_se3.high = 'b%b", word_se3.high); err=1; end + if (word_se3.low !== 8'b00000000 ) begin $display("FAILED -- word_se3.low = 'b%b", word_se3.low ); err=1; end + // access to whole structure + if (word_sw0 !== 16'bzzzzzzzz_zzzzzzzz) begin $display("FAILED -- word_sw0 = 'b%b", word_sw0 ); err=1; end + if (word_sw1 !== 16'b11111111_11111111) begin $display("FAILED -- word_sw1 = 'b%b", word_sw1 ); err=1; end + if (word_sw2 !== 16'b11111111_11111111) begin $display("FAILED -- word_sw2 = 'b%b", word_sw2 ); err=1; end + if (word_sw3 !== 16'b01111111_11111111) begin $display("FAILED -- word_sw3 = 'b%b", word_sw3 ); err=1; end + // access to parts of structure elements + if (word_ep0 !== 16'bzzzzzzzz_zzzzzzzz) begin $display("FAILED -- word_ep0 = 'b%b", word_ep0 ); err=1; end + if (word_ep1 !== 16'bzzzz1111_zzzz0000) begin $display("FAILED -- word_ep1 = 'b%b", word_ep1 ); err=1; end + if (word_ep1.high !== 8'bzzzz1111 ) begin $display("FAILED -- word_ep1.high = 'b%b", word_ep1.high); err=1; end + if (word_ep1.low !== 8'bzzzz0000 ) begin $display("FAILED -- word_ep1.low = 'b%b", word_ep1.low ); err=1; end + if (word_ep2 !== 16'bzzzz1111_zzzz0000) begin $display("FAILED -- word_ep2 = 'b%b", word_ep2 ); err=1; end + if (word_ep2.high !== 8'bzzzz1111 ) begin $display("FAILED -- word_ep2.high = 'b%b", word_ep2.high); err=1; end + if (word_ep2.low !== 8'bzzzz0000 ) begin $display("FAILED -- word_ep2.low = 'b%b", word_ep2.low ); err=1; end + if (word_ep3 !== 16'bzzzz0111_zzzz0000) begin $display("FAILED -- word_ep3 = 'b%b", word_ep3 ); err=1; end + if (word_ep3.high !== 8'bzzzz0111 ) begin $display("FAILED -- word_ep3.high = 'b%b", word_ep3.high); err=1; end + if (word_ep3.low !== 8'bzzzz0000 ) begin $display("FAILED -- word_ep3.low = 'b%b", word_ep3.low ); err=1; end + // access to parts of the whole structure + if (word_sp0 !== 16'bzzzzzzzz_zzzzzzzz) begin $display("FAILED -- word_sp0 = 'b%b", word_sp0 ); err=1; end + if (word_sp1 !== 16'bzzzz1111_1111zzzz) begin $display("FAILED -- word_sp1 = 'b%b", word_sp1 ); err=1; end + if (word_sp2 !== 16'bzzzz1111_1111zzzz) begin $display("FAILED -- word_sp2 = 'b%b", word_sp2 ); err=1; end + if (word_sp3 !== 16'bzzzz0111_1111zzzz) begin $display("FAILED -- word_sp3 = 'b%b", word_sp3 ); err=1; end + + if (!err) $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/supply1.v b/ivtest/ivltests/supply1.v new file mode 100644 index 000000000..271afb1d2 --- /dev/null +++ b/ivtest/ivltests/supply1.v @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This sample tests that the supply0 and supply1 nets take on + * the proper initial value. + */ + +module test; + + supply0 gnd; + supply1 vdd; + + initial begin + #1; + if (gnd !== 0) begin + $display("FAILED -- gnd == %b", gnd); + $finish; + end + + if (vdd !== 1) begin + $display("FAILED -- vdd == %b", vdd); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/supply2.v b/ivtest/ivltests/supply2.v new file mode 100644 index 000000000..82b5d3038 --- /dev/null +++ b/ivtest/ivltests/supply2.v @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This sample tests that the supply0 and supply1 nets take on + * the proper initial value. This adds to the supply1 test some + * constant drivers that could tickle constant propagation bugs. + */ + +module test; + + supply0 gnd; + supply1 vdd; + + // These should drop away as meaningless. + assign gnd = 1; + assign vdd = 0; + + initial begin #1 + if (gnd !== 0) begin + $display("FAILED -- gnd == %b", gnd); + $finish; + end + + if (vdd !== 1) begin + $display("FAILED -- vdd == %b", vdd); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/sv-2val-nets.v b/ivtest/ivltests/sv-2val-nets.v new file mode 100644 index 000000000..0569ca9bc --- /dev/null +++ b/ivtest/ivltests/sv-2val-nets.v @@ -0,0 +1,40 @@ +// This tests part selects of 2-value logic vectors through +// module ports. This is not supported in SystemVerilog, but +// we expect it to work as an Icarus Verilog extension, as +// long as all the bits of the 2-value are singly driven. + +module main; + + bit [5:0] a, b; + wire bit [6:0] sum; + wire bit c2, c4; + + sub b10 (.c_i(1'b0), .a(a[1:0]), .b(b[1:0]), .out(sum[1:0]), .c_o(c2)); + sub b32 (.c_i(c2), .a(a[3:2]), .b(b[3:2]), .out(sum[3:2]), .c_o(c4)); + sub b54 (.c_i(c4), .a(a[5:4]), .b(b[5:4]), .out(sum[5:4]), .c_o(sum[6])); + + bit [6:0] idxa, idxb; + initial begin + for (idxa = 0 ; idxa < 'b1_000000 ; idxa = idxa+1) begin + for (idxb = 0 ; idxb < 'b1_000000 ; idxb = idxb+1) begin + a = idxa; + b = idxb; + #1 /* wait for devices to settle */; + if (idxa + idxb != sum) begin + $display("FAILED: %0d + %0d --> %0d", a, b, sum); + $stop; + end + end + end // for (idxa = 0 ; idxa < 'b1_000000 ; idxa = idxa+1) + $display("PASSED"); + $finish; + end // initial begin + +endmodule // main + +module sub (input wire bit c_i, input wire bit[1:0] a, b, + output wire bit [1:0] out, output wire bit c_o); + + assign {c_o, out} = {1'b0, a} + {1'b0, b} + {2'b00, c_i}; + +endmodule // sub diff --git a/ivtest/ivltests/sv-constants.v b/ivtest/ivltests/sv-constants.v new file mode 100644 index 000000000..417f14db1 --- /dev/null +++ b/ivtest/ivltests/sv-constants.v @@ -0,0 +1,81 @@ +module tb; +parameter P = '1; +parameter W = 82; +wire [W-1:0] one = '1; +wire [W-1:0] zero = '0; +wire [W-1:0] x = 'x; +wire [W-1:0] z = 'z; +wire [15:0] expr_add = 16'h0 + '1; +wire [15:0] expr_xor = 16'haaaa ^ '1; +wire [3:0] bitsel = 4'h2; +wire [3:0] bitsel_lv; +wire [3:0] param = P; + +assign bitsel_lv['1] = 1'b1; + +initial begin + #5; + if (4'hf !== '1) begin + $display("FAILED, 4'hf !== '1"); + $finish; + end + + if (one !== '1) begin + $display("FAILED, one !== '1"); + $finish; + end + + if (one !== {W{1'b1}}) begin + $display("FAILED, one = %b", one); + $finish; + end + + if (zero !== {W{1'b0}}) begin + $display("FAILED, zero = %b", zero); + $finish; + end + + if (x !== {W{1'bx}}) begin + $display("FAILED, x = %b", x); + $finish; + end + + if (z !== {W{1'bz}}) begin + $display("FAILED, z = %b", z); + $finish; + end + + if (expr_add !== 16'hffff) begin + $display("FAILED, expr_add = %b", expr_add); + $finish; + end + + if (expr_xor !== 16'h5555) begin + $display("FAILED, expr_xor = %b", expr_xor); + $finish; + end + + if (bitsel_lv[1] !== 1'b1) begin + $display("FAILED, bitsel_lv[1] = %b", bitsel_lv[1]); + $finish; + end + + if (bitsel['1] !== 1'b1) begin + $display("FAILED, bitsel['1] = %b", bitsel['1]); + $finish; + end + + if (bitsel['1:'0] !== 2'b10) begin + $display("FAILED, bitsel['1:'0] = %b", bitsel['1:'0]); + $finish; + end + + if (param !== 4'h1) begin + $display("FAILED, param = %b, %b", param, P); + $finish; + end + + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/sv_array_assign_pattern2.v b/ivtest/ivltests/sv_array_assign_pattern2.v new file mode 100644 index 000000000..5c6fd22b9 --- /dev/null +++ b/ivtest/ivltests/sv_array_assign_pattern2.v @@ -0,0 +1,38 @@ + +program main; + + function int sum_array(bit[7:0] array[]); + int idx; + sum_array = 0; + for (idx = 0 ; idx < array.size() ; idx = idx+1) + sum_array += array[idx]; + endfunction // sum_array + + bit [7:0] obj[]; + int foo; + initial begin + foo = sum_array('{}); + if (foo !== 0) begin + $display("FAILED -- sum of empty array returns %0d", foo); + $finish; + end + + obj = new[3]; + obj = '{1,2,3}; + foo = sum_array(obj); + if (foo !== 6) begin + $display("FAILED -- sum of '{1,2,3} is %0d", foo); + $finish; + end + + obj = new[3] ('{4,5,6}); + foo = sum_array(obj); + if (foo !== 15) begin + $display("FAILED -- sum of '{4,5,6} is %0d", foo); + $finish; + end + + $display("PASSED"); + end // initial begin + +endprogram // main diff --git a/ivtest/ivltests/sv_cast_darray-v10.v b/ivtest/ivltests/sv_cast_darray-v10.v new file mode 100644 index 000000000..4ae8de25a --- /dev/null +++ b/ivtest/ivltests/sv_cast_darray-v10.v @@ -0,0 +1,74 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for casting a dynamic array to vector type +// using Icarus specific VPI functions + +module sv_cast_string(); + bit [7:0] darr []; + bit [63:0] darr_64 []; + bit [7*8 - 1:0] arr; + bit [127:0] arr_128; + +initial begin + darr_64 = new[2]; + darr_64[0] = "ABCDEFGH"; + darr_64[1] = "IJKLMNOP"; + + darr = new[7]; + // Set darr to '{"a","b","c","d","e","f","g"} + foreach(darr[i]) + darr[i] = "a" + i; + + // Casting dynamic array to vector + $ivl_darray_method$to_vec(darr, arr); + if(arr !== "abcdefg") begin + $display("FAILED 1"); + $finish(); + end + + $ivl_darray_method$to_vec(darr_64, arr_128); + if(arr_128 !== "ABCDEFGHIJKLMNOP") begin + $display("FAILED 2"); + $finish(); + end + + // Reset the stored data to perform reverse casting test + arr = "0123456"; + arr_128 = "cafedeadbeefc0de"; + + // Casting vector to dynamic array + $ivl_darray_method$from_vec(darr, arr); + foreach(darr[i]) begin + if(darr[i] != "0" + i) begin + $display("FAILED 3"); + $finish(); + end + end + + $ivl_darray_method$from_vec(darr_64, arr_128); + if(darr_64[0] !== "cafedead" || darr_64[1] !== "beefc0de") begin + $display("FAILED 4"); + $finish(); + end + + $display("PASSED"); +end +endmodule + diff --git a/ivtest/ivltests/sv_cast_darray.v b/ivtest/ivltests/sv_cast_darray.v new file mode 100644 index 000000000..30191e806 --- /dev/null +++ b/ivtest/ivltests/sv_cast_darray.v @@ -0,0 +1,68 @@ +module test(); + +typedef bit [63:0] bit64; +typedef logic [63:0] vec64; + +byte byte_array []; +bit [15:0] bit_array []; +logic [31:0] vec_array []; +real real_array []; + +bit64 bit_result; +vec64 vec_result; + +reg failed = 0; + +initial begin + byte_array = new [8]; + foreach (byte_array[i]) byte_array[i] = i*16 + i; + + bit_result = bit64'(byte_array); + $display("%h", bit_result); + if (bit_result !== 64'h0011223344556677) failed = 1; + + vec_result = vec64'(byte_array); + $display("%h", vec_result); + if (vec_result !== 64'h0011223344556677) failed = 1; + + bit_array = new [4]; + foreach (bit_array[i]) bit_array[i] = i*4096 + i*256 + i*16 + i; + + bit_result = bit64'(bit_array); + $display("%h", bit_result); + if (bit_result !== 64'h0000111122223333) failed = 1; + + vec_result = vec64'(bit_array); + $display("%h", vec_result); + if (vec_result !== 64'h0000111122223333) failed = 1; + + vec_array = new [2]; + vec_array[0] = 32'b01xz_0001_0010_0011_0100_0101_0110_0111; + vec_array[1] = 32'b1000_1001_1010_1011_1100_1101_1110_1111; + + bit_result = bit64'(vec_array); + $display("%h", bit_result); + if (bit_result !== 64'b0100_0001_0010_0011_0100_0101_0110_0111_1000_1001_1010_1011_1100_1101_1110_1111) failed = 1; + + vec_result = vec64'(vec_array); + $display("%h", vec_result); + if (vec_result !== 64'b01xz_0001_0010_0011_0100_0101_0110_0111_1000_1001_1010_1011_1100_1101_1110_1111) failed = 1; + + real_array = new [1]; + real_array[0] = 1.2345678; + + bit_result = bit64'(real_array); + $display("%h", bit_result); + if (bit_result !== $realtobits(1.2345678)) failed = 1; + + vec_result = vec64'(real_array); + $display("%h", vec_result); + if (vec_result !== $realtobits(1.2345678)) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/sv_cast_integer.v b/ivtest/ivltests/sv_cast_integer.v new file mode 100644 index 000000000..bf768f871 --- /dev/null +++ b/ivtest/ivltests/sv_cast_integer.v @@ -0,0 +1,39 @@ +// This tests SystemVerilog casting support +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. +// Extended by Maciej Suminski +// Extended by Martin Whitaker + +module test(); + + // variables used in casting + byte var_08; + shortint var_16; + int var_32; + longint var_64; + real var_real; + + // error counter + bit err = 0; + + initial begin + var_08 = byte'(4'sh5); if (var_08 !== 8'sh05) begin $display("FAILED -- var_08 = 'h%0h != 8'h05", var_08); err=1; end + var_16 = shortint'(var_08); if (var_16 !== 16'sh05) begin $display("FAILED -- var_16 = 'h%0h != 16'h05", var_16); err=1; end + var_32 = int'(var_16); if (var_32 !== 32'sh05) begin $display("FAILED -- var_32 = 'h%0h != 32'h05", var_32); err=1; end + var_64 = longint'(var_32); if (var_64 !== 64'sh05) begin $display("FAILED -- var_64 = 'h%0h != 64'h05", var_64); err=1; end + + var_real = 13.4; var_08 = byte'(var_real); if (var_08 !== 13) begin $display("FAILED -- var_08 = %d != 13", var_08); err=1; end + var_real = 14.5; var_16 = shortint'(var_real); if (var_16 !== 15) begin $display("FAILED -- var_16 = %d != 15", var_16); err=1; end + var_real = 15.6; var_32 = int'(var_real); if (var_32 !== 16) begin $display("FAILED -- var_32 = %d != 16", var_32); err=1; end + var_real = -15.6; var_64 = longint'(var_real); if (var_64 !== -16) begin $display("FAILED -- var_64 = %d != -16", var_64); err=1; end + + var_08 = byte'(4'hf); if (var_08 !== 8'sh0f) begin $display("FAILED -- var_08 = 'h%0h != 8'h0f", var_08); err=1; end + var_08 = byte'(4'shf); if (var_08 !== 8'shff) begin $display("FAILED -- var_08 = 'h%0h != 8'hff", var_08); err=1; end + var_16 = byte'(16'h0f0f); if (var_16 !== 16'sh0f) begin $display("FAILED -- var_16 = 'h%0h != 16'h0f", var_16); err=1; end + var_16 = byte'(4'shf) + 'd0; if (var_16 !== 16'shff) begin $display("FAILED -- var_16 = 'h%0h != 16'hff", var_16); err=1; end + + if (!err) $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/sv_cast_integer2.v b/ivtest/ivltests/sv_cast_integer2.v new file mode 100644 index 000000000..ef1753b26 --- /dev/null +++ b/ivtest/ivltests/sv_cast_integer2.v @@ -0,0 +1,44 @@ +// This tests SystemVerilog casting support +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. +// Extended by Maciej Suminski +// Copied and modified by Martin Whitaker + +module test(); + + typedef logic signed [7:0] reg08; + typedef logic signed [15:0] reg16; + typedef logic signed [31:0] reg32; + typedef logic signed [63:0] reg64; + + // variables used in casting + reg08 var_08; + reg16 var_16; + reg32 var_32; + reg64 var_64; + real var_real; + + // error counter + bit err = 0; + + initial begin + var_08 = reg08'(4'sh5); if (var_08 !== 8'sh05) begin $display("FAILED -- var_08 = 'h%0h != 8'h05", var_08); err=1; end + var_16 = reg16'(var_08); if (var_16 !== 16'sh05) begin $display("FAILED -- var_16 = 'h%0h != 16'h05", var_16); err=1; end + var_32 = reg32'(var_16); if (var_32 !== 32'sh05) begin $display("FAILED -- var_32 = 'h%0h != 32'h05", var_32); err=1; end + var_64 = reg64'(var_32); if (var_64 !== 64'sh05) begin $display("FAILED -- var_64 = 'h%0h != 64'h05", var_64); err=1; end + + var_real = 13.4; var_08 = reg08'(var_real); if (var_08 !== 13) begin $display("FAILED -- var_08 = %d != 13", var_08); err=1; end + var_real = 14.5; var_16 = reg16'(var_real); if (var_16 !== 15) begin $display("FAILED -- var_16 = %d != 15", var_16); err=1; end + var_real = 15.6; var_32 = reg32'(var_real); if (var_32 !== 16) begin $display("FAILED -- var_32 = %d != 16", var_32); err=1; end + var_real = -15.6; var_64 = reg64'(var_real); if (var_64 !== -16) begin $display("FAILED -- var_64 = %d != -16", var_64); err=1; end + + var_08 = reg08'(4'hf); if (var_08 !== 8'sh0f) begin $display("FAILED -- var_08 = 'h%0h != 8'h0f", var_08); err=1; end + var_08 = reg08'(4'shf); if (var_08 !== 8'shff) begin $display("FAILED -- var_08 = 'h%0h != 8'hff", var_08); err=1; end + var_16 = reg08'(16'h0f0f); if (var_16 !== 16'sh0f) begin $display("FAILED -- var_16 = 'h%0h != 16'h0f", var_16); err=1; end + var_16 = reg08'(4'shf) + 'd0; if (var_16 !== 16'shff) begin $display("FAILED -- var_16 = 'h%0h != 16'hff", var_16); err=1; end + + if (!err) $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/sv_cast_string.v b/ivtest/ivltests/sv_cast_string.v new file mode 100644 index 000000000..bcc94d157 --- /dev/null +++ b/ivtest/ivltests/sv_cast_string.v @@ -0,0 +1,56 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for casting a string to a vector type. + +module sv_cast_string(); + string str; + typedef logic [55:0] strbits; + strbits chars; + + initial begin + int i; + str = "0123456"; + chars = strbits'(str); + if(chars != 56'h30313233343536) + begin + $display("FAILED 1 chars = %x", chars); + $finish(); + end + + str = "6543210"; + chars = strbits'(str); + if(chars != "6543210") + begin + $display("FAILED 2 chars = %x", chars); + $finish(); + end + + str = "wrong string"; + // Vector to string casting + str = string'(chars); + if(str != "6543210") + begin + $display("FAILED 3 str = %s", str); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/sv_class1.v b/ivtest/ivltests/sv_class1.v new file mode 100644 index 000000000..0417e4e01 --- /dev/null +++ b/ivtest/ivltests/sv_class1.v @@ -0,0 +1,69 @@ + +/* + * This tests a trivial class. In SystemVerilong, classes are garbage + * collected dynamic objects, so this tests the creation of class objects, + * some simple manipulations, copying (by reference) and cleanup. + */ +program main; + + // Trivial example of a class + class foo_t ; + int a; + int b; + endclass : foo_t // foo_t + + foo_t obj, copy; + + initial begin + if (obj != null) begin + $display("FAILED -- objects must start out null."); + $finish; + end + + obj = new; + if (obj == null) begin + $display("FAILED -- After allocation, object is NOT null."); + $finish; + end + + // This is the most trivial assignment of class properties. + obj.a = 10; + obj.b = 11; + + if (obj.a != 10 || obj.b != 11) begin + $display("FAILED -- assign to object: obj.a=%0d, obj.b=%0d", obj.a, obj.b); + $finish; + end + + // This actually makes a shared link to the same object. This + // will make a link to the object. + copy = obj; + + if (copy.a != 10 || copy.b != 11) begin + $display("FAILED -- copy object: copy.a=%0d, copy.b=%0d", copy.a, copy.b); + $finish; + end + + copy.a = 7; + copy.b = 8; + + if (obj.a != 7 || obj.b != 8) begin + $display("FAILED -- check shared-ness: obj.a=%0d, obj.b=%0d", obj.a, obj.b); + $finish; + end + + // Clear the copy pointer. obj still exists, though. + copy = null; + if (obj.a != 7 || obj.b != 8) begin + $display("FAILED -- clear copy preserved link: obj.a=%0d, obj.b=%0d", obj.a, obj.b); + $finish; + end + + // This is the last reference to the class, so it should cause + // the object to be destroyed. How to test that? + obj = null; + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class10.v b/ivtest/ivltests/sv_class10.v new file mode 100644 index 000000000..1aae7f090 --- /dev/null +++ b/ivtest/ivltests/sv_class10.v @@ -0,0 +1,46 @@ + +/* + * This tests a trivial class. This tests that properties can be + * given types, and that the types behave properly. + */ +program main; + + class bar_t; + int a; + int b; + endclass // bar_t + + // Trivial example of a class + class foo_t ; + byte a; + bar_t b; + endclass : foo_t // foo_t + + foo_t obj; + bar_t tmp; + + initial begin + obj = new; + + // This is the most trivial assignment of class properties. + obj.a = 'hf_ff; + obj.b = new; + + tmp = obj.b; + tmp.a = 0; + tmp.b = 1; + + if (obj.a != -1) begin + $display("FAILED -- assign to object: obj.a=%0d", obj.a); + $finish; + end + + if (tmp.a != 0 || tmp.b != 1) begin + $display("FAILED -- obj.b.a=%0d, obj.b.b=%0d", tmp.a, tmp.b); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class11.v b/ivtest/ivltests/sv_class11.v new file mode 100644 index 000000000..20185d4df --- /dev/null +++ b/ivtest/ivltests/sv_class11.v @@ -0,0 +1,75 @@ + +/* + * This tests a trivial class. This tests that simple user defined + * methods work. + */ +program main; + + // Trivial example of a class + class foo_t ; + int value_; + + task clear(); + value_ = 0; + endtask // clear + + task add(int x); + this.value_ = this.value_ + x; + endtask // add + + function int peek(); + peek = value_; + endfunction // peek + + function int is_multiple(int x); + if (value_ % x == 0) + is_multiple = 1; + else + is_multiple = 0; + endfunction // is_multiple + + endclass : foo_t // foo_t + + foo_t obj; + + initial begin + obj = new; + + obj.clear(); + if (obj.peek() != 0) begin + $display("FAILED -- obj.value_=%0d after clear.", obj.value_); + $finish; + end + + obj.add(5); + if (obj.peek() != 5) begin + $display("FAILED -- obj.value_=%0d after add(5).", obj.value_); + $finish; + end + + if (obj.is_multiple(2) != 0) begin + $display("FAILED -- obj.is_multipe(2) incorrect result. (5/2)"); + $finish; + end + + obj.add(3); + if (obj.peek() != 8) begin + $display("FAILED -- obj.value_=%0d after add(3).", obj.value_); + $finish; + end + + if (obj.is_multiple(2) == 0) begin + $display("FAILED -- obj.is_multipe(2) incorrect result. (8/2)"); + $finish; + end + + obj.clear(); + if (obj.peek() != 0) begin + $display("FAILED -- obj.value_=%0d after second clear.", obj.value_); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class12.v b/ivtest/ivltests/sv_class12.v new file mode 100644 index 000000000..595ae31ca --- /dev/null +++ b/ivtest/ivltests/sv_class12.v @@ -0,0 +1,46 @@ + +/* + * This tests a trivial class. This tests that simple user defined + * constructors work. + */ +program main; + + // Trivial examples of classes. + class foo_t ; + int value; + + function new(); + value = 42; + endfunction // new + + endclass : foo_t // foo_t + + class bar_t ; + int value; + + function new (int init); + value = init; + endfunction // new + + endclass : bar_t // foo_t + + foo_t obj1; + bar_t obj2; + + initial begin + obj1 = new; + if (obj1.value !== 42) begin + $display("FAILED -- Default constructor left value=%0d.", obj1.value); + $finish; + end + + obj2 = new(53); + if (obj2.value !== 53) begin + $display("FAILED -- new(53) constructure left value=%0d.", obj2.value); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class13.v b/ivtest/ivltests/sv_class13.v new file mode 100644 index 000000000..23d566886 --- /dev/null +++ b/ivtest/ivltests/sv_class13.v @@ -0,0 +1,60 @@ + +/* + * This tests a trivial class. This tests that simple user defined + * constructors work, and also tests shallow copoy "new". + */ +program main; + + // Trivial examples of classes. + class foo_t ; + int value; + + function new(); + value = 42; + endfunction // new + + endclass : foo_t // foo_t + + class bar_t ; + int value; + + function new (int init); + value = init; + endfunction // new + + endclass : bar_t // foo_t + + foo_t obj1; + bar_t obj2; + foo_t obj1b; + + initial begin + obj1 = new; + if (obj1.value !== 42) begin + $display("FAILED -- Default constructor left value=%0d.", obj1.value); + $finish; + end + + obj2 = new(53); + if (obj2.value !== 53) begin + $display("FAILED -- new(53) constructure left value=%0d.", obj2.value); + $finish; + end + + // Shallow object copy + obj1b = new obj1; + if (obj1b.value !== 42) begin + $display("FAILED -- Shallow copy constructor left value=%0d.", obj1b.value); + $finish; + end + + obj1.value = 85; + if (obj1b.value !== 42) begin + $display("FAILED -- Shallow copied value changed to %0d.", obj1b.value); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class14.v b/ivtest/ivltests/sv_class14.v new file mode 100644 index 000000000..ef270b92e --- /dev/null +++ b/ivtest/ivltests/sv_class14.v @@ -0,0 +1,88 @@ + +/* + * This tests a trivial class. This tests that simple user defined + * constructors work, and also tests shallow copoy "new". + */ +program main; + + class share_t; + int value; + endclass // share_t + + // Trivial examples of classes. + class foo_t ; + int value; + string text; + share_t common; + endclass : foo_t // foo_t + + foo_t obj1; + foo_t obj2; + share_t tmp; + + initial begin + obj1 = new; + obj1.common = new; + obj1.value = 42; + obj1.text = "text"; + tmp = obj1.common; + tmp.value = 54; + + if (obj1.value !== 42) begin + $display("FAILED -- obj1.value=%0d.", obj1.value); + $finish; + end + + if (obj1.text != "text") begin + $display("FAILED -- obj1.text=%s", obj1.text); + $finish; + end + + tmp = obj1.common; + if (tmp.value !== 54) begin + $display("FAILED -- obj1.common.value=%0d.", tmp.value); + $finish; + end + + obj2 = new obj1; + obj1.value = 43; + obj1.text = "new text"; + tmp = obj1.common; + tmp.value = 53; + + if (obj1.value !== 43) begin + $display("FAILED -- obj1.value=%0d.", obj1.value); + $finish; + end + + if (obj2.value !== 42) begin + $display("FAILED -- obj2.value=%0d.", obj2.value); + $finish; + end + + if (obj1.text != "new text") begin + $display("FAILED -- obj1.text=%s", obj1.text); + $finish; + end + + if (obj2.text != "text") begin + $display("FAILED -- obj2.text=%s", obj2.text); + $finish; + end + + tmp = obj1.common; + if (tmp.value !== 53) begin + $display("FAILED -- obj1.common.value=%0d.", tmp.value); + $finish; + end + + tmp = obj2.common; + if (tmp.value !== 53) begin + $display("FAILED -- obj2.common.value=%0d.", tmp.value); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class15.v b/ivtest/ivltests/sv_class15.v new file mode 100644 index 000000000..224040bc6 --- /dev/null +++ b/ivtest/ivltests/sv_class15.v @@ -0,0 +1,46 @@ + +/* + * This tests a trivial class. This tests that simple property + * initializers work, but are overridden by an constructor. + */ +program main; + + // Trivial examples of classes. + class foo_t ; + int int_value = 42; + bit [3:0] bit_value = 5; + string txt_value = "text"; + + function new(); + // The declaration assignments happen before the constructor + // is called, so we can refer to them. + int_value = int_value + 1; // s.b. 43 + bit_value = bit_value * 2; // s.b. 10 + txt_value = "fluf"; + endfunction + endclass : foo_t // foo_t + + foo_t obj1; + + initial begin + obj1 = new; + + if (obj1.int_value !== 43) begin + $display("FAILED -- obj1.int_value=%0d.", obj1.int_value); + $finish; + end + + if (obj1.bit_value !== 4'd10) begin + $display("FAILED -- obj1.bit_value=%0b.", obj1.bit_value); + $finish; + end + + if (obj1.txt_value != "fluf") begin + $display("FAILED -- obj1.txt_value=%s", obj1.txt_value); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class16.v b/ivtest/ivltests/sv_class16.v new file mode 100644 index 000000000..224040bc6 --- /dev/null +++ b/ivtest/ivltests/sv_class16.v @@ -0,0 +1,46 @@ + +/* + * This tests a trivial class. This tests that simple property + * initializers work, but are overridden by an constructor. + */ +program main; + + // Trivial examples of classes. + class foo_t ; + int int_value = 42; + bit [3:0] bit_value = 5; + string txt_value = "text"; + + function new(); + // The declaration assignments happen before the constructor + // is called, so we can refer to them. + int_value = int_value + 1; // s.b. 43 + bit_value = bit_value * 2; // s.b. 10 + txt_value = "fluf"; + endfunction + endclass : foo_t // foo_t + + foo_t obj1; + + initial begin + obj1 = new; + + if (obj1.int_value !== 43) begin + $display("FAILED -- obj1.int_value=%0d.", obj1.int_value); + $finish; + end + + if (obj1.bit_value !== 4'd10) begin + $display("FAILED -- obj1.bit_value=%0b.", obj1.bit_value); + $finish; + end + + if (obj1.txt_value != "fluf") begin + $display("FAILED -- obj1.txt_value=%s", obj1.txt_value); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class17.v b/ivtest/ivltests/sv_class17.v new file mode 100644 index 000000000..d3cb36e6c --- /dev/null +++ b/ivtest/ivltests/sv_class17.v @@ -0,0 +1,47 @@ + +/* + * This tests a trivial class. This tests that simple property + * initializers work. + */ +program main; + + // Trivial examples of classes. + class foo_t ; + int int_value = 42; + bit [3:0] bit_value = 5; + string txt_value = "text"; + endclass : foo_t // foo_t + + foo_t obj1; + foo_t obj2; + + initial begin + obj1 = new; + + // The shallow copy constructor bypasses (or at least overrides) + // property declaration assignments, so obj2 should hold the + // updated values and not the constructed values. + obj1.int_value = 43; + obj1.bit_value = 10; + obj1.txt_value = "fluf"; + obj2 = new obj1; + + if (obj2.int_value !== 43) begin + $display("FAILED -- obj2.int_value=%0d.", obj2.int_value); + $finish; + end + + if (obj2.bit_value !== 4'd10) begin + $display("FAILED -- obj2.bit_value=%0b.", obj2.bit_value); + $finish; + end + + if (obj2.txt_value != "fluf") begin + $display("FAILED -- obj2.txt_value=%s", obj2.txt_value); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class18.v b/ivtest/ivltests/sv_class18.v new file mode 100644 index 000000000..166d0680d --- /dev/null +++ b/ivtest/ivltests/sv_class18.v @@ -0,0 +1,52 @@ + +/* + * This tests a trivial class. This tests that simple property + * initializers work, but are overridden by an constructor. It + * also tests the global const property. + */ +program main; + + // Trivial examples of classes. + class foo_t ; + const int int_incr = 1; + int int_value = 42; + + function new(); + // The declaration assignments happen before the constructor + // is called, so we can refer to them. + int_value = int_value + int_incr; // s.b. 43 + endfunction + endclass : foo_t // foo_t + + foo_t obj1; + foo_t obj2; + + initial begin + obj1 = new; + + if (obj1.int_incr !== 1) begin + $display("FAILED == obj1.int_incr=%0d.", obj1.int_incr); + $finish; + end + + if (obj1.int_value !== 43) begin + $display("FAILED -- obj1.int_value=%0d.", obj1.int_value); + $finish; + end + + // Try a shallow copy to see that the const propery is handled. + obj2 = new obj1; + if (obj2.int_incr !== 1) begin + $display("FAILED == obj2.int_incr=%0d.", obj2.int_incr); + $finish; + end + + if (obj2.int_value !== 43) begin + $display("FAILED -- obj2.int_value=%0d.", obj2.int_value); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class19.v b/ivtest/ivltests/sv_class19.v new file mode 100644 index 000000000..6b2605fb8 --- /dev/null +++ b/ivtest/ivltests/sv_class19.v @@ -0,0 +1,60 @@ + +/* + * This tests a trivial class. This tests that simple property + * initializers work, but are overridden by an constructor. It + * also tests the global const property. + */ +program main; + + // Trivial examples of classes. + class foo_t ; + static int int_incr = 1; + int int_value = 42; + + function new(); + // The declaration assignments happen before the constructor + // is called, so we can refer to them. + int_value = int_value + int_incr; // s.b. 43 + endfunction + endclass : foo_t // foo_t + + foo_t obj1; + foo_t obj2; + + initial begin + + // Static properties do not actually look at the instance, so + // we do not need to create an instance to access them. + if (obj1.int_incr !== 1) begin + $display("FAILED == obj1.int_incr=%0d.", obj1.int_incr); + $finish; + end + + obj1 = new; + + if (obj1.int_value !== 43) begin + $display("FAILED -- obj1.int_value=%0d.", obj1.int_value); + $finish; + end + + // Try a shallow copy to see that the const propery is handled. + obj2 = new obj1; + if (obj2.int_value !== 43) begin + $display("FAILED -- obj2.int_value=%0d.", obj2.int_value); + $finish; + end + + obj1.int_incr = 2; + if (obj1.int_incr !== 2) begin + $display("FAILED == obj1.int_incr=%0d", obj1.int_incr); + $finish; + end + if (obj2.int_incr !== 2) begin + $display("FAILED == obj2.int_incr=%0d", obj2.int_incr); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class2.v b/ivtest/ivltests/sv_class2.v new file mode 100644 index 000000000..a6ae83743 --- /dev/null +++ b/ivtest/ivltests/sv_class2.v @@ -0,0 +1,38 @@ + +/* + * This tests a trivial class. This tests that properties can be + * given types, and that the types behave properly. + */ +program main; + + // Trivial example of a class + class foo_t ; + byte signed a; + byte unsigned b; + endclass : foo_t // foo_t + + foo_t obj; + + initial begin + obj = new; + + // This is the most trivial assignment of class properties. + obj.a = 'hfff; + obj.b = 'hfff; + + if (obj.a != -1 || obj.b != 255) begin + $display("FAILED -- assign to object: obj.a=%0d, obj.b=%0d", obj.a, obj.b); + $finish; + end + + obj.a = obj.a + 1; + obj.b = obj.b + 1; + if (obj.a != 0 || obj.b != 0) begin + $display("FAILED -- increment properties: obj.a=%0d, obj.b=%0d", obj.a, obj.b); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class20.v b/ivtest/ivltests/sv_class20.v new file mode 100644 index 000000000..404799d45 --- /dev/null +++ b/ivtest/ivltests/sv_class20.v @@ -0,0 +1,37 @@ + +program main; + + class base_t ; + int int_value; + function new(); + int_value = 42; + endfunction // new + endclass : base_t + + class foo_t extends base_t ; + string str_value; + function new(); + str_value = "42"; + endfunction + endclass : foo_t + + foo_t obj1; + + initial begin + obj1 = new; + + if (obj1.int_value !== 42) begin + $display("FAILED -- obj1.int_value = %0d", obj1.int_value); + $finish; + end + + if (obj1.str_value != "42") begin + $display("FAILED -- obj1.str_value = %0s", obj1.str_value); + $finish; + end + + $display("PASSED"); + $finish; + end + +endprogram // main diff --git a/ivtest/ivltests/sv_class21.v b/ivtest/ivltests/sv_class21.v new file mode 100644 index 000000000..4e5b65ba0 --- /dev/null +++ b/ivtest/ivltests/sv_class21.v @@ -0,0 +1,38 @@ + +program main; + + class base_t ; + int int_value; + function new(int val); + int_value = val; + endfunction // new + endclass : base_t + + class foo_t extends base_t ; + string str_value; + function new(); + super.new(42); + str_value = "42"; + endfunction + endclass : foo_t + + foo_t obj1; + + initial begin + obj1 = new; + + if (obj1.int_value !== 42) begin + $display("FAILED -- obj1.int_value = %0d", obj1.int_value); + $finish; + end + + if (obj1.str_value != "42") begin + $display("FAILED -- obj1.str_value = %0s", obj1.str_value); + $finish; + end + + $display("PASSED"); + $finish; + end + +endprogram // main diff --git a/ivtest/ivltests/sv_class22.v b/ivtest/ivltests/sv_class22.v new file mode 100644 index 000000000..1a6ee8680 --- /dev/null +++ b/ivtest/ivltests/sv_class22.v @@ -0,0 +1,37 @@ + +program main; + + class base_t ; + int int_value; + function new(int val); + int_value = val; + endfunction // new + endclass : base_t + + class foo_t extends base_t(42) ; + string str_value; + function new(); + str_value = "42"; + endfunction + endclass : foo_t + + foo_t obj1; + + initial begin + obj1 = new; + + if (obj1.int_value !== 42) begin + $display("FAILED -- obj1.int_value = %0d", obj1.int_value); + $finish; + end + + if (obj1.str_value != "42") begin + $display("FAILED -- obj1.str_value = %0s", obj1.str_value); + $finish; + end + + $display("PASSED"); + $finish; + end + +endprogram // main diff --git a/ivtest/ivltests/sv_class23.v b/ivtest/ivltests/sv_class23.v new file mode 100644 index 000000000..a7ab512e5 --- /dev/null +++ b/ivtest/ivltests/sv_class23.v @@ -0,0 +1,38 @@ + +program main; + + class base_t ; + int int_value; + function new(int val); + int_value = val; + endfunction // new + endclass : base_t + + class foo_t extends base_t ; + string str_value; + function new(int eval); + super.new(eval); + str_value = "42"; + endfunction + endclass : foo_t + + foo_t obj1; + + initial begin + obj1 = new (42); + + if (obj1.int_value !== 42) begin + $display("FAILED -- obj1.int_value = %0d", obj1.int_value); + $finish; + end + + if (obj1.str_value != "42") begin + $display("FAILED -- obj1.str_value = %0s", obj1.str_value); + $finish; + end + + $display("PASSED"); + $finish; + end + +endprogram // main diff --git a/ivtest/ivltests/sv_class24.v b/ivtest/ivltests/sv_class24.v new file mode 100644 index 000000000..33ddc04f0 --- /dev/null +++ b/ivtest/ivltests/sv_class24.v @@ -0,0 +1,75 @@ + +/* + * This tests a trivial class. In SystemVerilong, classes are garbage + * collected dynamic objects, so this tests the creation of class objects, + * some simple manipulations, copying (by reference) and cleanup. + */ + +// Trivial example of a class + +program main; + + class base_t; + int x; + int y; + endclass : base_t + + class foo_t; + int a; + int b; + base_t base = new ( ); + endclass : foo_t + + foo_t obj, copy; + + initial begin + obj = new; + + if (obj == null) begin + $display("FAILED -- After allocation, object is NOT null."); + $finish; + end + + // This is the most trivial assignment of class properties. + obj.a = 10; + obj.b = 11; + obj.base.x = 12; + obj.base.y = 13; + + if (obj.a != 10 || obj.b != 11) begin + $display("FAILED -- assign to object: obj.a=%0d, obj.b=%0d", obj.a, obj.b); + $finish; + end + + // This actually makes a shared link to the same object. This + // will make a link to the object. + copy = obj; + + if (copy.a != 10 || copy.b != 11) begin + $display("FAILED -- copy object: copy.a=%0d, copy.b=%0d", copy.a, copy.b); + $finish; + end + + copy.a = 7; + copy.b = 8; + + if (obj.a != 7 || obj.b != 8) begin + $display("FAILED -- check shared-ness: obj.a=%0d, obj.b=%0d", obj.a, obj.b); + $finish; + end + + // Clear the copy pointer. obj still exists, though. + copy = null; + if (obj.a != 7 || obj.b != 8) begin + $display("FAILED -- clear copy preserved link: obj.a=%0d, obj.b=%0d", obj.a, obj.b); + $finish; + end + + // This is the last reference to the class, so it should cause + // the object to be destroyed. How to test that? + obj = null; + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class3.v b/ivtest/ivltests/sv_class3.v new file mode 100644 index 000000000..f56de8b9a --- /dev/null +++ b/ivtest/ivltests/sv_class3.v @@ -0,0 +1,38 @@ + +/* + * This tests a trivial class. This tests that properties can be + * given types, and that the types behave properly. + */ +program main; + + // Trivial example of a class + class foo_t ; + shortint signed a; + shortint unsigned b; + endclass : foo_t // foo_t + + foo_t obj; + + initial begin + obj = new; + + // This is the most trivial assignment of class properties. + obj.a = 'hf_ffff; + obj.b = 'hf_ffff; + + if (obj.a != -1 || obj.b != 65535) begin + $display("FAILED -- assign to object: obj.a=%0d, obj.b=%0d", obj.a, obj.b); + $finish; + end + + obj.a = obj.a + 1; + obj.b = obj.b + 1; + if (obj.a != 0 || obj.b != 0) begin + $display("FAILED -- increment properties: obj.a=%0d, obj.b=%0d", obj.a, obj.b); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class4.v b/ivtest/ivltests/sv_class4.v new file mode 100644 index 000000000..e28e273cf --- /dev/null +++ b/ivtest/ivltests/sv_class4.v @@ -0,0 +1,38 @@ + +/* + * This tests a trivial class. This tests that properties can be + * given types, and that the types behave properly. + */ +program main; + + // Trivial example of a class + class foo_t ; + int signed a; + int unsigned b; + endclass : foo_t // foo_t + + foo_t obj; + + initial begin + obj = new; + + // This is the most trivial assignment of class properties. + obj.a = 'hf_ffffffff; + obj.b = 'hf_ffffffff; + + if (obj.a != -1 || obj.b != 'd4_294_967_295) begin + $display("FAILED -- assign to object: obj.a=%0d, obj.b=%0d", obj.a, obj.b); + $finish; + end + + obj.a = obj.a + 1; + obj.b = obj.b + 1; + if (obj.a != 0 || obj.b != 0) begin + $display("FAILED -- increment properties: obj.a=%0d, obj.b=%0d", obj.a, obj.b); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class5.v b/ivtest/ivltests/sv_class5.v new file mode 100644 index 000000000..2e107f0af --- /dev/null +++ b/ivtest/ivltests/sv_class5.v @@ -0,0 +1,38 @@ + +/* + * This tests a trivial class. This tests that properties can be + * given types, and that the types behave properly. + */ +program main; + + // Trivial example of a class + class foo_t ; + longint signed a; + longint unsigned b; + endclass : foo_t // foo_t + + foo_t obj; + + initial begin + obj = new; + + // This is the most trivial assignment of class properties. + obj.a = 68'hf_ffffffff_ffffffff; + obj.b = 68'hf_ffffffff_ffffffff; + + if (obj.a != -1 || obj.b != 64'hffffffff_ffffffff) begin + $display("FAILED -- assign to object: obj.a=%0d, obj.b=%0d", obj.a, obj.b); + $finish; + end + + obj.a = obj.a + 1; + obj.b = obj.b + 1; + if (obj.a != 0 || obj.b != 0) begin + $display("FAILED -- increment properties: obj.a=%0d, obj.b=%0d", obj.a, obj.b); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class6.v b/ivtest/ivltests/sv_class6.v new file mode 100644 index 000000000..f23734c08 --- /dev/null +++ b/ivtest/ivltests/sv_class6.v @@ -0,0 +1,38 @@ + +/* + * This tests a trivial class. This tests that properties can be + * given types, and that the types behave properly. + */ +program main; + + // Trivial example of a class + class foo_t ; + real a; + real b; + endclass : foo_t // foo_t + + foo_t obj; + + initial begin + obj = new; + + // This is the most trivial assignment of class properties. + obj.a = 0.5; + obj.b = -1.5; + + if (obj.a != 0.5 || obj.b != -1.5) begin + $display("FAILED -- assign to object: obj.a=%f, obj.b=%f", obj.a, obj.b); + $finish; + end + + obj.a = obj.a - 0.5; + obj.b = obj.b + 1.5; + if (obj.a != 0.0 || obj.b != 0.0) begin + $display("FAILED -- increment properties: obj.a=%f, obj.b=%f", obj.a, obj.b); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class7.v b/ivtest/ivltests/sv_class7.v new file mode 100644 index 000000000..1722acd04 --- /dev/null +++ b/ivtest/ivltests/sv_class7.v @@ -0,0 +1,38 @@ + +/* + * This tests a trivial class. This tests that properties can be + * given types, and that the types behave properly. + */ +program main; + + // Trivial example of a class + class foo_t ; + string a; + string b; + endclass : foo_t // foo_t + + foo_t obj; + + initial begin + obj = new; + + // Absent any other constructor, strings get initialized as nil. + if (obj.a != "" || obj.b != "") begin + $display("FAILED -- String property not initialized."); + $finish; + end + + // This is the most trivial assignment of class properties. + obj.a = "Hello"; + obj.b = "World"; + + $display("obj = {%0s, %0s}", obj.a, obj.b); + if (obj.a != "Hello" || obj.b != "World") begin + $display("FAILED -- assign to object: obj.a=%0s, obj.b=%0s", obj.a, obj.b); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class8.v b/ivtest/ivltests/sv_class8.v new file mode 100644 index 000000000..7bbf53cdf --- /dev/null +++ b/ivtest/ivltests/sv_class8.v @@ -0,0 +1,43 @@ + +/* + * This tests a trivial class. This tests that properties can be + * given types, and that the types behave properly. + */ +program main; + + // Trivial example of a class + class foo_t ; + byte a; + int b; + real c; + string d; + endclass : foo_t // foo_t + + foo_t obj; + + initial begin + obj = new; + + // This is the most trivial assignment of class properties. + obj.a = 'hf_ff; + obj.b = 'hf_ffffffff; + obj.c = -1.5; + obj.d = "-1"; + + if (obj.a != -1 || obj.b != -1 || obj.c != -1.5 || obj.d != "-1") begin + $display("FAILED -- assign to object: obj.a=%0d, obj.b=%0d, obj.c=%f, obj.d=%0s", obj.a, obj.b, obj.c, obj.d); + $finish; + end + + obj.a = obj.a + 1; + obj.b = obj.b + 1; + obj.c = obj.c + 1.5; + if (obj.a != 0 || obj.b != 0 || obj.c != 0.0) begin + $display("FAILED -- increment properties: obj.a=%0d, obj.b=%0d, obj.c=%f", obj.a, obj.b, obj.c); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_class9.v b/ivtest/ivltests/sv_class9.v new file mode 100644 index 000000000..dc27c2a26 --- /dev/null +++ b/ivtest/ivltests/sv_class9.v @@ -0,0 +1,47 @@ + +/* + * This tests a trivial class. This tests that properties can be + * given types, and that the types behave properly. + */ +program main; + + // Trivial example of a class + class foo_t ; + byte a; + int b[]; + endclass : foo_t // foo_t + + foo_t obj; + int tmp[]; + + initial begin + obj = new; + + // This is the most trivial assignment of class properties. + obj.a = 'hf_ff; + obj.b = new[2]; + + tmp = obj.b; + tmp[0] = 0; + tmp[1] = 1; + + if (obj.a != -1) begin + $display("FAILED -- assign to object: obj.a=%0d", obj.a); + $finish; + end + + tmp = obj.b; + + if (tmp.size() != 2) begin + $display("FAILED -- obj.b.size() = %0d", tmp.size()); + $finish; + end + if (tmp[0] != 0 || tmp[1] != 1) begin + $display("FAILED -- obj.b[0]=%0d, obj.b[1]=%0d", tmp[0], tmp[1]); + $finish; + end + + $display("PASSED"); + $finish; + end +endprogram // main diff --git a/ivtest/ivltests/sv_darray1.v b/ivtest/ivltests/sv_darray1.v new file mode 100644 index 000000000..d32d3fe01 --- /dev/null +++ b/ivtest/ivltests/sv_darray1.v @@ -0,0 +1,52 @@ +/* + * This demonstrates a basic dynamic array + */ +module main; + + int foo[]; + int idx; + + initial begin + if (foo.size() != 0) begin + $display("FAILED -- foo.size()=%0d, s.b. 0", foo.size()); + $finish; + end + + foo = new[10]; + if (foo.size() != 10) begin + $display("FAILED -- foo.size()=%0d, s.b. 10", foo.size()); + $finish; + end + + for (idx = 0 ; idx < foo.size() ; idx += 1) begin + foo[idx] = idx; + end + + $display("foo[7] = %d", foo[7]); + if (foo[7] != 7) begin + $display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]); + $finish; + end + + $display("foo[9] = %d", foo[9]); + if (foo[9] != 9) begin + $display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]); + $finish; + end + + for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin + if (foo[idx%10] != (idx%10)) begin + $display("FAILED -- foo[%0d%%10] = %0d", idx, foo[idx%10]); + $finish; + end + end + + foo.delete(); + if (foo.size() != 0) begin + $display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size()); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/sv_darray2.v b/ivtest/ivltests/sv_darray2.v new file mode 100644 index 000000000..20bcd1499 --- /dev/null +++ b/ivtest/ivltests/sv_darray2.v @@ -0,0 +1,53 @@ + +/* + * This demonstrates a basic dynamic array + */ +module main; + + byte foo[]; + int idx; + + initial begin + if (foo.size() != 0) begin + $display("FAILED -- foo.size()=%0d, s.b. 0", foo.size()); + $finish; + end + + foo = new[10]; + if (foo.size() != 10) begin + $display("FAILED -- foo.size()=%0d, s.b. 10", foo.size()); + $finish; + end + + for (idx = 0 ; idx < foo.size() ; idx += 1) begin + foo[idx] = idx; + end + + $display("foo[7] = %d", foo[7]); + if (foo[7] != 7) begin + $display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]); + $finish; + end + + $display("foo[9] = %d", foo[9]); + if (foo[9] != 9) begin + $display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]); + $finish; + end + + for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin + if (foo[idx%10] != (idx%10)) begin + $display("FAILED -- foo[%0d%%10] = %0d", idx, foo[idx%10]); + $finish; + end + end + + foo.delete(); + if (foo.size() != 0) begin + $display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size()); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/sv_darray3.v b/ivtest/ivltests/sv_darray3.v new file mode 100644 index 000000000..44454c9d8 --- /dev/null +++ b/ivtest/ivltests/sv_darray3.v @@ -0,0 +1,53 @@ + +/* + * This demonstrates a basic dynamic array + */ +module main; + + shortint foo[]; + int idx; + + initial begin + if (foo.size() != 0) begin + $display("FAILED -- foo.size()=%0d, s.b. 0", foo.size()); + $finish; + end + + foo = new[10]; + if (foo.size() != 10) begin + $display("FAILED -- foo.size()=%0d, s.b. 10", foo.size()); + $finish; + end + + for (idx = 0 ; idx < foo.size() ; idx += 1) begin + foo[idx] = idx; + end + + $display("foo[7] = %d", foo[7]); + if (foo[7] != 7) begin + $display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]); + $finish; + end + + $display("foo[9] = %d", foo[9]); + if (foo[9] != 9) begin + $display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]); + $finish; + end + + for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin + if (foo[idx%10] != (idx%10)) begin + $display("FAILED -- foo[%0d%%10] = %0d", idx, foo[idx%10]); + $finish; + end + end + + foo.delete(); + if (foo.size() != 0) begin + $display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size()); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/sv_darray4.v b/ivtest/ivltests/sv_darray4.v new file mode 100644 index 000000000..02b1fbae9 --- /dev/null +++ b/ivtest/ivltests/sv_darray4.v @@ -0,0 +1,53 @@ + +/* + * This demonstrates a basic dynamic array + */ +module main; + + longint foo[]; + int idx; + + initial begin + if (foo.size() != 0) begin + $display("FAILED -- foo.size()=%0d, s.b. 0", foo.size()); + $finish; + end + + foo = new[10]; + if (foo.size() != 10) begin + $display("FAILED -- foo.size()=%0d, s.b. 10", foo.size()); + $finish; + end + + for (idx = 0 ; idx < foo.size() ; idx += 1) begin + foo[idx] = idx; + end + + $display("foo[7] = %d", foo[7]); + if (foo[7] != 7) begin + $display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]); + $finish; + end + + $display("foo[9] = %d", foo[9]); + if (foo[9] != 9) begin + $display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]); + $finish; + end + + for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin + if (foo[idx%10] != (idx%10)) begin + $display("FAILED -- foo[%0d%%10] = %0d", idx, foo[idx%10]); + $finish; + end + end + + foo.delete(); + if (foo.size() != 0) begin + $display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size()); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/sv_darray5.v b/ivtest/ivltests/sv_darray5.v new file mode 100644 index 000000000..eada6e2ed --- /dev/null +++ b/ivtest/ivltests/sv_darray5.v @@ -0,0 +1,53 @@ + +/* + * This demonstrates a basic dynamic array + */ +module main; + + real foo[]; + int idx; + + initial begin + if (foo.size() != 0) begin + $display("FAILED -- foo.size()=%0d, s.b. 0", foo.size()); + $finish; + end + + foo = new[10]; + if (foo.size() != 10) begin + $display("FAILED -- foo.size()=%0d, s.b. 10", foo.size()); + $finish; + end + + for (idx = 0 ; idx < foo.size() ; idx += 1) begin + foo[idx] = idx; + end + + $display("foo[7] = %d", foo[7]); + if (foo[7] != 7) begin + $display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]); + $finish; + end + + $display("foo[9] = %d", foo[9]); + if (foo[9] != 9) begin + $display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]); + $finish; + end + + for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin + if (foo[idx%10] != (idx%10)) begin + $display("FAILED -- foo[%0d%%10] = %0d", idx, foo[idx%10]); + $finish; + end + end + + foo.delete(); + if (foo.size() != 0) begin + $display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size()); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/sv_darray5b.v b/ivtest/ivltests/sv_darray5b.v new file mode 100644 index 000000000..47c7e50d6 --- /dev/null +++ b/ivtest/ivltests/sv_darray5b.v @@ -0,0 +1,53 @@ + +/* + * This demonstrates a basic dynamic array + */ +module main; + + shortreal foo[]; + int idx; + + initial begin + if (foo.size() != 0) begin + $display("FAILED -- foo.size()=%0d, s.b. 0", foo.size()); + $finish; + end + + foo = new[10]; + if (foo.size() != 10) begin + $display("FAILED -- foo.size()=%0d, s.b. 10", foo.size()); + $finish; + end + + for (idx = 0 ; idx < foo.size() ; idx += 1) begin + foo[idx] = idx; + end + + $display("foo[7] = %d", foo[7]); + if (foo[7] != 7) begin + $display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]); + $finish; + end + + $display("foo[9] = %d", foo[9]); + if (foo[9] != 9) begin + $display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]); + $finish; + end + + for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin + if (foo[idx%10] != (idx%10)) begin + $display("FAILED -- foo[%0d%%10] = %0d", idx, foo[idx%10]); + $finish; + end + end + + foo.delete(); + if (foo.size() != 0) begin + $display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size()); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/sv_darray6.v b/ivtest/ivltests/sv_darray6.v new file mode 100644 index 000000000..01b8f0d4b --- /dev/null +++ b/ivtest/ivltests/sv_darray6.v @@ -0,0 +1,57 @@ + +/* + * This demonstrates a basic dynamic array + */ +module main; + + string foo[]; + int idx; + + string tmp; + initial begin + if (foo.size() != 0) begin + $display("FAILED -- foo.size()=%0d, s.b. 0", foo.size()); + $finish; + end + + foo = new[10]; + if (foo.size() != 10) begin + $display("FAILED -- foo.size()=%0d, s.b. 10", foo.size()); + $finish; + end + + tmp = "fooa"; + for (idx = 0 ; idx < foo.size() ; idx += 1) begin + tmp[3] = 'h41 + idx; + foo[idx] = tmp; + end + + $display("foo[7] = %0s", foo[7]); + if (foo[7] != "fooH") begin + $display("FAILED -- foo[7] = %0s (s.b. fooH)", foo[7]); + $finish; + end + + $display("foo[9] = %0s", foo[9]); + if (foo[9] != "fooJ") begin + $display("FAILED -- foo[9] = %0s (s.b. fooJ)", foo[9]); + $finish; + end + + for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin + tmp[3] = 'h41 + (idx%10); + if (foo[idx%10] != tmp) begin + $display("FAILED -- foo[%0d%%10] = %0s", idx, foo[idx%10]); + $finish; + end + end + + foo.delete(); + if (foo.size() != 0) begin + $display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size()); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/sv_darray_args1.v b/ivtest/ivltests/sv_darray_args1.v new file mode 100644 index 000000000..2437697bb --- /dev/null +++ b/ivtest/ivltests/sv_darray_args1.v @@ -0,0 +1,33 @@ + +program main; + + function int sum_array(bit[7:0] array[]); + int idx; + sum_array = 0; + for (idx = 0 ; idx < array.size() ; idx = idx+1) + sum_array += array[idx]; + endfunction // sum_array + + bit [7:0] obj[]; + int foo; + initial begin + foo = sum_array('{}); + if (foo !== 0) begin + $display("FAILED -- sum of empty array returns %0d", foo); + $finish; + end + + obj = new[3]; + obj[0] = 1; + obj[1] = 2; + obj[2] = 3; + foo = sum_array(obj); + if (foo !== 6) begin + $display("FAILED -- sum of '{1,2,3} is %0d", foo); + $finish; + end + + $display("PASSED"); + end // initial begin + +endprogram // main diff --git a/ivtest/ivltests/sv_darray_args2.v b/ivtest/ivltests/sv_darray_args2.v new file mode 100644 index 000000000..fbc38b548 --- /dev/null +++ b/ivtest/ivltests/sv_darray_args2.v @@ -0,0 +1,38 @@ + +program main; + + function real sum_array(real array[]); + int idx; + sum_array = 0.0; + for (idx = 0 ; idx < array.size() ; idx = idx+1) + sum_array = sum_array + array[idx]; + endfunction // sum_array + + real obj[]; + real foo; + initial begin + foo = sum_array('{}); + if (foo != 0.0) begin + $display("FAILED -- sum of empty array returns %0d", foo); + $finish; + end + + obj = new[3]; + obj = '{1.0,2.0,3.0}; + foo = sum_array(obj); + if (foo != 6.0) begin + $display("FAILED -- sum of '{%f,%f,%f} is %0d", obj[0], obj[1], obj[2], foo); + $finish; + end + + obj = new[3] ('{4.0,5.0,6.0}); + foo = sum_array(obj); + if (foo != 15.0) begin + $display("FAILED -- sum of '{4,5,6} is %0d", foo); + $finish; + end + + $display("PASSED"); + end // initial begin + +endprogram // main diff --git a/ivtest/ivltests/sv_darray_args2b.v b/ivtest/ivltests/sv_darray_args2b.v new file mode 100644 index 000000000..2b53e4e9a --- /dev/null +++ b/ivtest/ivltests/sv_darray_args2b.v @@ -0,0 +1,38 @@ + +program main; + + function real sum_array(real array[]); + int idx; + sum_array = 0.0; + for (idx = 0 ; idx < array.size() ; idx = idx+1) + sum_array = sum_array + array[idx]; + endfunction // sum_array + + real obj[]; + real foo; + initial begin + foo = sum_array('{}); + if (foo != 0.0) begin + $display("FAILED -- sum of empty array returns %0d", foo); + $finish; + end + + obj = new[3]; + obj = '{1,2,3}; + foo = sum_array(obj); + if (foo != 6.0) begin + $display("FAILED -- sum of '{%f,%f,%f} is %0d", obj[0], obj[1], obj[2], foo); + $finish; + end + + obj = new[3] ('{4,5,6}); + foo = sum_array(obj); + if (foo != 15.0) begin + $display("FAILED -- sum of '{4,5,6} is %0d", foo); + $finish; + end + + $display("PASSED"); + end // initial begin + +endprogram // main diff --git a/ivtest/ivltests/sv_darray_args3.v b/ivtest/ivltests/sv_darray_args3.v new file mode 100644 index 000000000..b11445318 --- /dev/null +++ b/ivtest/ivltests/sv_darray_args3.v @@ -0,0 +1,30 @@ + +program main; + + function real sum_array(real array[]); + int idx; + sum_array = 0.0; + for (idx = 0 ; idx < array.size() ; idx = idx+1) + sum_array = sum_array + array[idx]; + endfunction // sum_array + + real obj[]; + real foo; + initial begin + foo = sum_array('{}); + if (foo != 0.0) begin + $display("FAILED -- sum of empty array returns %0d", foo); + $finish; + end + + obj = new[3] (3.0); + foo = sum_array(obj); + if (foo != 9.0) begin + $display("FAILED -- sum of '{3.3.3} is %0d", foo); + $finish; + end + + $display("PASSED"); + end // initial begin + +endprogram // main diff --git a/ivtest/ivltests/sv_darray_args4.v b/ivtest/ivltests/sv_darray_args4.v new file mode 100644 index 000000000..2730f8c2d --- /dev/null +++ b/ivtest/ivltests/sv_darray_args4.v @@ -0,0 +1,45 @@ + +program main; + + function string sum_array(string array[]); + int idx; + sum_array = ""; + for (idx = 0 ; idx < array.size() ; idx = idx+1) + sum_array = {sum_array, array[idx]}; + endfunction // sum_array + + string obj[]; + string foo; + initial begin + foo = sum_array('{}); + if (foo != "") begin + $display("FAILED -- sum of empty array returns %0s", foo); + $finish; + end + + obj = new[3]; + obj = '{"1", "2", "3"}; + foo = sum_array(obj); + if (foo != "123") begin + $display("FAILED -- sum of '{\"1\",\"2\",\"3\"} is %0s", foo); + $finish; + end + + obj = new[3] ('{"A", "B", "C"}); + foo = sum_array(obj); + if (foo != "ABC") begin + $display("FAILED -- sum of '{\"A\",\"B\",\"C\"} is %0s", foo); + $finish; + end + + obj = new[3] ("A"); + foo = sum_array(obj); + if (foo != "AAA") begin + $display("FAILED -- sum of \"AAA\" is %0s", foo); + $finish; + end + + $display("PASSED"); + end // initial begin + +endprogram // main diff --git a/ivtest/ivltests/sv_darray_decl_assign.v b/ivtest/ivltests/sv_darray_decl_assign.v new file mode 100644 index 000000000..cad5d0943 --- /dev/null +++ b/ivtest/ivltests/sv_darray_decl_assign.v @@ -0,0 +1,46 @@ +package mypackage; + +logic [1:0] array1[] = new[4]; +logic [1:0] array2[] = new[4]('{0,1,2,3}); + +endpackage + +module test(); + +import mypackage::*; + +logic [1:0] array3[] = new[4]; +logic [1:0] array4[] = new[4]('{0,1,2,3}); + +reg failed = 0; + +initial begin + foreach (array1[i]) begin + array1[i] = i; + end + foreach (array1[i]) begin + $display(array1[i]); + if (array1[i] !== i) failed = 1; + end + foreach (array2[i]) begin + $display(array2[i]); + if (array2[i] !== i) failed = 1; + end + foreach (array3[i]) begin + array3[i] = i; + end + foreach (array3[i]) begin + $display(array3[i]); + if (array3[i] !== i) failed = 1; + end + foreach (array4[i]) begin + $display(array4[i]); + if (array4[i] !== i) failed = 1; + end + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/sv_darray_function.v b/ivtest/ivltests/sv_darray_function.v new file mode 100644 index 000000000..098058ce9 --- /dev/null +++ b/ivtest/ivltests/sv_darray_function.v @@ -0,0 +1,67 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for dynamic arrays used as the function parameters and return type. + +module sv_darray_function(); +typedef logic[7:0] byte_array []; +typedef logic[3*8-1:0] byte_vector; + +function byte_array inc_array(byte_array inp); + byte_array tmp; + tmp = new[$size(inp)]; + + for(int i = 0; i < $size(inp); ++i) + begin + tmp[i] = inp[i] + 1; + end + + return tmp; +endfunction + +initial begin + byte_array a, b; + byte_vector c; + + a = new[3]; + a[0] = 10; + a[1] = 11; + a[2] = 12; + b = inc_array(a); + + if($size(a) != 3 || a[0] !== 10 || a[1] !== 11 || a[2] !== 12) begin + $display("FAILED 1"); + $finish(); + end + + if($size(b) != 3 || b[0] !== 11 || b[1] !== 12 || b[2] !== 13) begin + $display("FAILED 2"); + $finish(); + end + + // Cast dynamic array returned by function to logic vector + c = byte_vector'(inc_array(b)); + if(c !== 24'h0c0d0e) begin + $display("FAILED 3"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/sv_darray_signed.v b/ivtest/ivltests/sv_darray_signed.v new file mode 100644 index 000000000..f8e38818a --- /dev/null +++ b/ivtest/ivltests/sv_darray_signed.v @@ -0,0 +1,32 @@ +module main; + + bit pass; + bit signed [7:0] s8[]; + bit [7:0] u8[]; + string res, fmt; + + initial begin + pass = 1'b1; + s8 = new[2]; + u8 = new[2]; + s8[0] = -1; + u8[0] = -1; + + fmt = "%0d"; + $display(fmt, s8[0]); + $sformat(res, fmt, s8[0]); + if (res != "-1") begin + $display("Failed: expected '-1', got '%s'", res); + pass = 1'b0; + end + + $display(fmt, u8[0]); + $swrite(res, u8[0]); + if (res != "255") begin + $display("Failed: expected '255', got '%s'", res); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/sv_darray_word_size.v b/ivtest/ivltests/sv_darray_word_size.v new file mode 100644 index 000000000..ec6a41dbf --- /dev/null +++ b/ivtest/ivltests/sv_darray_word_size.v @@ -0,0 +1,61 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Tests if dynamic array words are of appropriate size. + +module sv_cast_string(); + bit [6:1] darr []; + bit [63:0] darr_64 []; + logic [4:10] darr_rev []; + +initial begin + darr = new[4]; + darr_64 = new[8]; + darr_rev = new[3]; + + if($size(darr[0]) != 6 || $size(darr_64[2]) != 64 || $size(darr_rev[1]) != 7 || + $size(darr) != 4 || $size(darr_64) != 8 || $size(darr_rev) != 3) + begin + $display("FAILED"); + $finish(); + end + + darr[0] = 6'b110011; + darr[1] = 6'b000011; + darr[2] = darr[0] + darr[1]; + + darr_64[0] = 64'hcafe0000dead0000; + darr_64[1] = 64'h0000bad00000d00d; + darr_64[2] = darr_64[0] + darr_64[1]; + + darr_rev[0] = 7'b1111000; + darr_rev[1] = 7'b0000011; + darr_rev[2] = darr_rev[0] + darr_rev[1]; + + if(darr[2] !== 6'b110110 || darr_64[2] !== 64'hcafebad0deadd00d || + darr_rev[2] !== 7'b1111011) + begin + $display("FAILED"); + $finish(); + end + + $display("PASSED"); +end +endmodule + diff --git a/ivtest/ivltests/sv_default_port_value1.v b/ivtest/ivltests/sv_default_port_value1.v new file mode 100644 index 000000000..65832c04a --- /dev/null +++ b/ivtest/ivltests/sv_default_port_value1.v @@ -0,0 +1,21 @@ +module dut(input wire [7:0] i = 8'd10, output wire [7:0] o); + +assign o = i; + +endmodule + +module tb(); + +wire [7:0] result; + +dut dut(,result); + +initial begin + #1; + if (result === 10) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/sv_default_port_value2.v b/ivtest/ivltests/sv_default_port_value2.v new file mode 100644 index 000000000..c3f948579 --- /dev/null +++ b/ivtest/ivltests/sv_default_port_value2.v @@ -0,0 +1,21 @@ +module dut(input wire [7:0] i = 8'd10, output wire [7:0] o); + +assign o = i; + +endmodule + +module tb(); + +wire [7:0] result; + +dut dut(.o(result)); + +initial begin + #1; + if (result === 10) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/sv_default_port_value3.v b/ivtest/ivltests/sv_default_port_value3.v new file mode 100644 index 000000000..a5189ec59 --- /dev/null +++ b/ivtest/ivltests/sv_default_port_value3.v @@ -0,0 +1,23 @@ +reg [7:0] v; + +module dut(input wire [7:0] i = v, output wire [7:0] o); + +assign o = i; + +endmodule + +module tb(); + +wire [7:0] result; + +dut dut(,result); + +initial begin + #1; + if (result === 10) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/sv_deferred_assert1.v b/ivtest/ivltests/sv_deferred_assert1.v new file mode 100644 index 000000000..49e7a6d0f --- /dev/null +++ b/ivtest/ivltests/sv_deferred_assert1.v @@ -0,0 +1,20 @@ +// This just tests the compiler accepts the syntax. It needs to be improved +// when deferred assertions are supported. +module test(); + +integer i = 1; + +initial begin + assert #0 (i == 1); + assert #0 (i == 0); + assert #0 (i == 1) else $display("Check 3 : this shouldn't be displayed"); + assert #0 (i == 0) else $display("Check 4 : this should be displayed"); + assert #0 (i == 1) $display("Check 5 : this should be displayed"); + assert #0 (i == 0) $display("Check 6 : this shouldn't be displayed"); + assert #0 (i == 1) $display("Check 7 : this should be displayed"); + else $display("Check 7 : this shouldn't be displayed"); + assert #0 (i == 0) $display("Check 8 : this shouldn't be displayed"); + else $display("Check 8 : this should be displayed"); +end + +endmodule diff --git a/ivtest/ivltests/sv_deferred_assert2.v b/ivtest/ivltests/sv_deferred_assert2.v new file mode 100644 index 000000000..4c8f01b25 --- /dev/null +++ b/ivtest/ivltests/sv_deferred_assert2.v @@ -0,0 +1,20 @@ +// This just tests the compiler accepts the syntax. It needs to be improved +// when deferred assertions are supported. +module test(); + +integer i = 1; + +initial begin + assert final (i == 1); + assert final (i == 0); + assert final (i == 1) else $display("Check 3 : this shouldn't be displayed"); + assert final (i == 0) else $display("Check 4 : this should be displayed"); + assert final (i == 1) $display("Check 5 : this should be displayed"); + assert final (i == 0) $display("Check 6 : this shouldn't be displayed"); + assert final (i == 1) $display("Check 7 : this should be displayed"); + else $display("Check 7 : this shouldn't be displayed"); + assert final (i == 0) $display("Check 8 : this shouldn't be displayed"); + else $display("Check 8 : this should be displayed"); +end + +endmodule diff --git a/ivtest/ivltests/sv_deferred_assume1.v b/ivtest/ivltests/sv_deferred_assume1.v new file mode 100644 index 000000000..2b981f459 --- /dev/null +++ b/ivtest/ivltests/sv_deferred_assume1.v @@ -0,0 +1,20 @@ +// This just tests the compiler accepts the syntax. It needs to be improved +// when deferred assumeions are supported. +module test(); + +integer i = 1; + +initial begin + assume #0 (i == 1); + assume #0 (i == 0); + assume #0 (i == 1) else $display("Check 3 : this shouldn't be displayed"); + assume #0 (i == 0) else $display("Check 4 : this should be displayed"); + assume #0 (i == 1) $display("Check 5 : this should be displayed"); + assume #0 (i == 0) $display("Check 6 : this shouldn't be displayed"); + assume #0 (i == 1) $display("Check 7 : this should be displayed"); + else $display("Check 7 : this shouldn't be displayed"); + assume #0 (i == 0) $display("Check 8 : this shouldn't be displayed"); + else $display("Check 8 : this should be displayed"); +end + +endmodule diff --git a/ivtest/ivltests/sv_deferred_assume2.v b/ivtest/ivltests/sv_deferred_assume2.v new file mode 100644 index 000000000..63c5071e7 --- /dev/null +++ b/ivtest/ivltests/sv_deferred_assume2.v @@ -0,0 +1,20 @@ +// This just tests the compiler accepts the syntax. It needs to be improved +// when deferred assumeions are supported. +module test(); + +integer i = 1; + +initial begin + assume final (i == 1); + assume final (i == 0); + assume final (i == 1) else $display("Check 3 : this shouldn't be displayed"); + assume final (i == 0) else $display("Check 4 : this should be displayed"); + assume final (i == 1) $display("Check 5 : this should be displayed"); + assume final (i == 0) $display("Check 6 : this shouldn't be displayed"); + assume final (i == 1) $display("Check 7 : this should be displayed"); + else $display("Check 7 : this shouldn't be displayed"); + assume final (i == 0) $display("Check 8 : this shouldn't be displayed"); + else $display("Check 8 : this should be displayed"); +end + +endmodule diff --git a/ivtest/ivltests/sv_end_label.v b/ivtest/ivltests/sv_end_label.v new file mode 100644 index 000000000..aeddc9d74 --- /dev/null +++ b/ivtest/ivltests/sv_end_label.v @@ -0,0 +1,64 @@ +module top; + initial begin: b_label + $display("PASSED"); + end: b_label + + initial fork:fj_label + join:fj_label + + initial fork:fja_label + join_any:fja_label + + initial fork:fjn_label + join_none:fjn_label + + task t_label; + endtask: t_label + + task twa_label(input arg); + endtask: twa_label + + function fn_label; + input arg; + endfunction: fn_label + + function fa_label(input in); + endfunction: fa_label + +endmodule:top + +macromodule extra; + parameter add_inv = 1; + reg a; + wire y, yb; + pbuf dut(y, a); + + if (add_inv) begin: g_label + pinv dut2(yb, y); + end: g_label + +endmodule: extra + +package pkg; +endpackage: pkg + +program pgm; + class foo; + endclass: foo +endprogram: pgm + +primitive pbuf (out, in); + output out; + input in; + table + 0 : 0; + 1 : 1; + endtable +endprimitive: pbuf + +primitive pinv (output out, input in); + table + 0 : 1; + 1 : 0; + endtable +endprimitive: pinv diff --git a/ivtest/ivltests/sv_end_label_fail.v b/ivtest/ivltests/sv_end_label_fail.v new file mode 100644 index 000000000..57c736825 --- /dev/null +++ b/ivtest/ivltests/sv_end_label_fail.v @@ -0,0 +1,64 @@ +module top; + initial begin: b_label + $display("FAILED"); + end: b_label_f + + initial fork:fj_label + join:fj_label_f + + initial fork:fja_label + join_any:fja_label_f + + initial fork:fjn_label + join_none:fjn_label_f + + task t_label; + endtask: t_label_f + + task twa_label(input arg); + endtask: twa_label_f + + function fn_label; + input arg; + endfunction: fn_label_f + + function fa_label(input in); + endfunction: fa_label_f + +endmodule:top_f + +macromodule extra; + parameter add_inv = 1; + reg a; + wire y, yb; + pbuf dut(y, a); + + if (add_inv) begin: g_label + pinv dut2(yb, y); + end: g_label_f + +endmodule: extra_f + +package pkg; +endpackage: pkg_f + +program pgm; + class foo; + endclass: foo_f +endprogram: pgm_f + +primitive pbuf (out, in); + output out; + input in; + table + 0 : 0; + 1 : 1; + endtable +endprimitive: pbuf + +primitive pinv (output out, input in); + table + 0 : 1; + 1 : 0; + endtable +endprimitive: pinv_f diff --git a/ivtest/ivltests/sv_end_labels.v b/ivtest/ivltests/sv_end_labels.v new file mode 100644 index 000000000..bae3adcca --- /dev/null +++ b/ivtest/ivltests/sv_end_labels.v @@ -0,0 +1,16 @@ +// This tests end labes (test should pass compilation) +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test (); + + // error counter + bit err = 0; + + initial + begin : dummy_label + if (!err) $display("PASSED"); + end : dummy_label + +endmodule : test diff --git a/ivtest/ivltests/sv_end_labels_bad.v b/ivtest/ivltests/sv_end_labels_bad.v new file mode 100644 index 000000000..d5dfe6bac --- /dev/null +++ b/ivtest/ivltests/sv_end_labels_bad.v @@ -0,0 +1,16 @@ +// This tests end labes (should fail compilation) +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test (); + + // error counter + bit err = 0; + + initial + begin : dummy_label + if (!err) $display("PASSED"); + end : dummy_label_bad + +endmodule : test_bad diff --git a/ivtest/ivltests/sv_enum1.v b/ivtest/ivltests/sv_enum1.v new file mode 100644 index 000000000..7386f13a5 --- /dev/null +++ b/ivtest/ivltests/sv_enum1.v @@ -0,0 +1,42 @@ + +module foo_mod(output reg pass_flag, input wire go_flag); + + typedef enum logic [1:0] { W0, W1, W2 } foo_t; + foo_t foo; + + always @(posedge go_flag) begin + + pass_flag = 0; + + if ($bits(foo) !== 2) begin + $display("FAILED -- $bits(foo)=%0d", $bits(foo)); + $finish; + end + + if ($bits(foo_t) !== 2) begin + $display("FAILED -- $bits(foo_t)=%0d", $bits(foo_t)); + $finish; + end + + pass_flag = 1; + end + +endmodule + +module main; + logic go_flag = 0; + wire [1:0] pass_flag; + + foo_mod dut[1:0] (.pass_flag(pass_flag), .go_flag(go_flag)); + + initial begin + #1 go_flag = 1; + #1 if (pass_flag !== 2'b11) begin + $display("FAILED -- pass_flag=%b", pass_flag); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sv_for_variable.v b/ivtest/ivltests/sv_for_variable.v new file mode 100644 index 000000000..f7cdb1887 --- /dev/null +++ b/ivtest/ivltests/sv_for_variable.v @@ -0,0 +1,26 @@ + +program main; + + int sum; + logic idx; // Use this to test scope; + initial begin + sum = 0; + idx = 1'bx; + for (int idx = 0 ; idx < 8 ; idx += 1) begin + sum += idx; + end + + if (sum != 28) begin + $display("FAILED -- sum=%0d", sum); + $finish; + end + + if (idx !== 1'bx) begin + $display("FAILED -- idx in upper scope became %b", idx); + $finish; + end + + $display("PASSED"); + end // initial begin + +endprogram diff --git a/ivtest/ivltests/sv_foreach1.v b/ivtest/ivltests/sv_foreach1.v new file mode 100644 index 000000000..274112513 --- /dev/null +++ b/ivtest/ivltests/sv_foreach1.v @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2014 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +`default_nettype none + +module main; + + reg [4:0] foo [0:3][0:7]; + bit [3:0] idx1, idx2; + + initial begin + for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin + for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1) + foo[idx1][idx2] = {idx1[1:0], idx2[2:0]}; + end + + foreach (foo[ia,ib]) begin + if (ia > 3 || ib > 7) begin + $display("FAILED -- index out of range: ia=%0d, ib=%0d", ia, ib); + $finish; + end + + if (foo[ia][ib] !== {ia[1:0], ib[2:0]}) begin + $display("FAILED -- foo[%0d][%0d] == %b", ia, ib, foo[ia][ib]); + $finish; + end + + foo[ia][ib] = 5'bzzzz; + end + + for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin + for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1) + if (foo[idx1][idx2] !== 5'bzzzz) begin + $display("FAILED -- foreach failed to visit foo[%0d][%0d]", idx1,idx2); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sv_foreach2.v b/ivtest/ivltests/sv_foreach2.v new file mode 100644 index 000000000..0531df565 --- /dev/null +++ b/ivtest/ivltests/sv_foreach2.v @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2014 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +`default_nettype none + +module main; + + class test_t; + reg [1:0] a; + reg [2:0] b; + + function new (int ax, int bx); + begin + a = ax; + b = bx; + end + endfunction // new + + endclass // test_t + + test_t foo [0:3][0:7], tmp; + bit [3:0] idx1, idx2; + + initial begin + for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin + for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1) + foo[idx1][idx2] = new(idx1,idx2); + end + + foreach (foo[ia,ib]) begin + if (ia > 3 || ib > 7) begin + $display("FAILED -- index out of range: ia=%0d, ib=%0d", ia, ib); + $finish; + end + + tmp = foo[ia][ib]; + if (tmp.a !== ia[1:0] || tmp.b !== ib[2:0]) begin + $display("FAILED -- foo[%0d][%0d] == %b", ia, ib, {tmp.a, tmp.b}); + $finish; + end + + foo[ia][ib] = null; + end + + for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin + for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1) + if (foo[idx1][idx2] != null) begin + $display("FAILED -- foreach failed to visit foo[%0d][%0d]", idx1,idx2); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sv_foreach3.v b/ivtest/ivltests/sv_foreach3.v new file mode 100644 index 000000000..380752c9c --- /dev/null +++ b/ivtest/ivltests/sv_foreach3.v @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2014 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +`default_nettype none + +module main; + + class test_t; + reg [1:0] a; + reg [2:0] b; + + function new (int ax, int bx); + begin + a = ax; + b = bx; + end + endfunction // new + + endclass // test_t + + class container_t; + test_t foo [0:3][0:7]; + + function new(); + bit [3:0] idx1, idx2; + begin + for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin + for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1) + foo[idx1][idx2] = new(idx1,idx2); + end + end + endfunction // new + + task run(); + bit [3:0] idx1, idx2; + test_t tmp; + foreach (foo[ia,ib]) begin + if (ia > 3 || ib > 7) begin + $display("FAILED -- index out of range: ia=%0d, ib=%0d", ia, ib); + $finish; + end + + tmp = foo[ia][ib]; + if (tmp.a !== ia[1:0] || tmp.b !== ib[2:0]) begin + $display("FAILED -- foo[%0d][%0d] == %b", ia, ib, {tmp.a, tmp.b}); + $finish; + end + + foo[ia][ib] = null; + end + + for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin + for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1) + if (foo[idx1][idx2] != null) begin + $display("FAILED -- foreach failed to visit foo[%0d][%0d]", idx1,idx2); + $finish; + end + end + endtask // run + + endclass + + container_t dut; + initial begin + dut = new; + dut.run; + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sv_foreach4.v b/ivtest/ivltests/sv_foreach4.v new file mode 100644 index 000000000..b10c4fd5d --- /dev/null +++ b/ivtest/ivltests/sv_foreach4.v @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2014 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +`default_nettype none + +class test_t; + reg [1:0] a; + reg [2:0] b; + + function new (int ax, int bx); + begin + a = ax; + b = bx; + end + endfunction // new + +endclass // test_t + +module main; + + class container_t; + test_t foo [0:3][0:7]; + + function new(); + bit [3:0] idx1, idx2; + begin + for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin + for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1) + foo[idx1][idx2] = new(idx1,idx2); + end + end + endfunction // new + + task run(); + bit [3:0] idx1, idx2; + test_t tmp; + foreach (foo[ia,ib]) begin + if (ia > 3 || ib > 7) begin + $display("FAILED -- index out of range: ia=%0d, ib=%0d", ia, ib); + $finish; + end + + tmp = foo[ia][ib]; + if (tmp.a !== ia[1:0] || tmp.b !== ib[2:0]) begin + $display("FAILED -- foo[%0d][%0d] == %b", ia, ib, {tmp.a, tmp.b}); + $finish; + end + + foo[ia][ib] = null; + end + + for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin + for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1) + if (foo[idx1][idx2] != null) begin + $display("FAILED -- foreach failed to visit foo[%0d][%0d]", idx1,idx2); + $finish; + end + end + endtask // run + + endclass + + container_t dut; + initial begin + dut = new; + dut.run; + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sv_foreach5.v b/ivtest/ivltests/sv_foreach5.v new file mode 100644 index 000000000..d090d3514 --- /dev/null +++ b/ivtest/ivltests/sv_foreach5.v @@ -0,0 +1,36 @@ +module test(); + +reg [3:0] array[0:1][0:2]; + +reg [3:0] expected; + +reg failed = 0; + +initial begin + for (int i = 0; i < 2; i++) begin + for (int j = 0; j < 3; j++) begin + array[i][j] = i * 4 + j; + end + end + foreach (array[i,j,k]) begin + expected = i * 4 + j; + $display("Value of array[%0d][%0d][%0d]=%b", i, j, k, array[i][j][k]); + if (array[i][j][k] !== expected[k]) failed = 1; + end + foreach (array[i,j]) begin + expected = i * 4 + j; + $display("Value of array[%0d][%0d]=%h", i, j, array[i][j]); + if (array[i][j] !== expected) failed = 1; + end + foreach (array[i]) begin + expected = i * 4; + $display("Value of array[%0d][0]=%h", i, array[i][0]); + if (array[i][0] !== expected) failed = 1; + end + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/sv_immediate_assert.v b/ivtest/ivltests/sv_immediate_assert.v new file mode 100644 index 000000000..0470d8583 --- /dev/null +++ b/ivtest/ivltests/sv_immediate_assert.v @@ -0,0 +1,18 @@ +module test(); + +integer i = 1; + +initial begin + assert(i == 1); + assert(i == 0); + assert(i == 1) else $display("Check 3 : this shouldn't be displayed"); + assert(i == 0) else $display("Check 4 : this should be displayed"); + assert(i == 1) $display("Check 5 : this should be displayed"); + assert(i == 0) $display("Check 6 : this shouldn't be displayed"); + assert(i == 1) $display("Check 7 : this should be displayed"); + else $display("Check 7 : this shouldn't be displayed"); + assert(i == 0) $display("Check 8 : this shouldn't be displayed"); + else $display("Check 8 : this should be displayed"); +end + +endmodule diff --git a/ivtest/ivltests/sv_immediate_assume.v b/ivtest/ivltests/sv_immediate_assume.v new file mode 100644 index 000000000..1e4514f56 --- /dev/null +++ b/ivtest/ivltests/sv_immediate_assume.v @@ -0,0 +1,18 @@ +module test(); + +integer i = 1; + +initial begin + assume(i == 1); + assume(i == 0); + assume(i == 1) else $display("Check 3 : this shouldn't be displayed"); + assume(i == 0) else $display("Check 4 : this should be displayed"); + assume(i == 1) $display("Check 5 : this should be displayed"); + assume(i == 0) $display("Check 6 : this shouldn't be displayed"); + assume(i == 1) $display("Check 7 : this should be displayed"); + else $display("Check 7 : this shouldn't be displayed"); + assume(i == 0) $display("Check 8 : this shouldn't be displayed"); + else $display("Check 8 : this should be displayed"); +end + +endmodule diff --git a/ivtest/ivltests/sv_interface.v b/ivtest/ivltests/sv_interface.v new file mode 100644 index 000000000..cd9dddbd7 --- /dev/null +++ b/ivtest/ivltests/sv_interface.v @@ -0,0 +1,171 @@ +// This tests SystemVerilog interfaces +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test (); + + // error counter + bit err = 0; + + logic clk = 1'b1; + logic rst = 1'b1; // reset + integer rst_cnt = 0; + + // clock generator + always #5 clk = ~clk; + + // reset is removed after a delay + always @ (posedge clk) + begin + rst_cnt <= rst_cnt + 1; + rst <= rst_cnt <= 3; + end + + // counters + int cnt; + int cnt_src; + int cnt_drn; + + // add all counters + assign cnt = cnt_src + cnt_drn + inf.cnt; + + // finish report + initial begin + wait (cnt == 3*16); + if (!err) $display("PASSED"); + $finish; + end + + // interface instance + handshake inf ( + .clk (clk), + .rst (rst) + ); + + // source instance + source #( + .RW (8), + .RP (8'b11100001) + ) source ( + .clk (clk), + .rst (rst), + .inf (inf), + .cnt (cnt_src) + ); + + // drain instance + drain #( + .RW (8), + .RP (8'b11010100) + ) drain ( + .clk (clk), + .rst (rst), + .inf (inf), + .cnt (cnt_drn) + ); + +endmodule + + +// interface definition +interface handshake #( + parameter int unsigned WC = 32 +)( + input logic clk, + input logic rst +); + + // modport signals + logic req; // request + logic grt; // grant + logic inc; // increment + + // local signals + integer cnt; // counter + + // source + modport src ( + output req, + input grt + ); + + // drain + modport drn ( + input req, + output grt + ); + + // incremet condition + assign inc = req & grt; + + // local logic (counter) + always @ (posedge clk, posedge rst) + if (rst) cnt <= '0; + else cnt <= cnt + inc; + +endinterface + + +// source module +module source #( + // random generator parameters + parameter int unsigned RW=1, // LFSR width + parameter bit [RW-1:0] RP='0, // LFSR polinom + parameter bit [RW-1:0] RR='1 // LFSR reset state +)( + input logic clk, + input logic rst, + handshake.src inf, + output integer cnt +); + + // LFSR + logic [RW-1:0] rnd; + + // LFSR in Galois form + always @ (posedge clk, posedge rst) + if (rst) rnd <= RR; + else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP); + + // counter + always @ (posedge clk, posedge rst) + if (rst) cnt <= 32'd0; + else cnt <= cnt + (inf.req & inf.grt); + + // request signal + assign inf.req = rnd[0]; + +endmodule + + +// drain module +module drain #( + // random generator parameters + parameter int unsigned RW=1, // LFSR width + parameter bit [RW-1:0] RP='0, // LFSR polinom + parameter bit [RW-1:0] RR='1 // LFSR reset state +)( + input logic clk, + input logic rst, + handshake.drn inf, + output integer cnt +); + + // LFSR + logic [RW-1:0] rnd; + + // LFSR in Galois form + always @ (posedge clk, posedge rst) + if (rst) rnd <= RR; + else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP); + + // counter + always @ (posedge clk, posedge rst) + if (rst) cnt <= 32'd0; + else cnt <= cnt + (inf.req & inf.grt); + + // grant signal + assign inf.grt = rnd[0]; + +endmodule diff --git a/ivtest/ivltests/sv_literals.v b/ivtest/ivltests/sv_literals.v new file mode 100644 index 000000000..60c4cec38 --- /dev/null +++ b/ivtest/ivltests/sv_literals.v @@ -0,0 +1,254 @@ +// This tests literal values, from verilog 2001 and SystemVerilog +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test (); + + // logic vector + logic unsigned [15:0] luv; // logic unsigned vector + logic signed [15:0] lsv; // logic signed vector + + // error counter + bit err = 0; + + initial begin + // unsized literals without base + luv = '0; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != '0", luv); err=1; end + luv = '1; if (luv !== 16'b1111_1111_1111_1111) begin $display("FAILED -- luv = 'b%b != '1", luv); err=1; end + luv = 'x; if (luv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 'x", luv); err=1; end + luv = 'z; if (luv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 'z", luv); err=1; end + + // unsized binary literals single character + luv = 'b0; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 'b0", luv); err=1; end + luv = 'b1; if (luv !== 16'b0000_0000_0000_0001) begin $display("FAILED -- luv = 'b%b != 'b1", luv); err=1; end + luv = 'bx; if (luv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 'bx", luv); err=1; end + luv = 'bz; if (luv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 'bz", luv); err=1; end + // unsized binary literals two characters + luv = 'b00; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 'b00", luv); err=1; end + luv = 'b11; if (luv !== 16'b0000_0000_0000_0011) begin $display("FAILED -- luv = 'b%b != 'b11", luv); err=1; end + luv = 'bxx; if (luv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 'bxx", luv); err=1; end + luv = 'bzz; if (luv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 'bzz", luv); err=1; end + luv = 'b1x; if (luv !== 16'b0000_0000_0000_001x) begin $display("FAILED -- luv = 'b%b != 'b1x", luv); err=1; end + luv = 'b1z; if (luv !== 16'b0000_0000_0000_001z) begin $display("FAILED -- luv = 'b%b != 'b1z", luv); err=1; end + luv = 'bx1; if (luv !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- luv = 'b%b != 'bx1", luv); err=1; end + luv = 'bz1; if (luv !== 16'bzzzz_zzzz_zzzz_zzz1) begin $display("FAILED -- luv = 'b%b != 'bz1", luv); err=1; end + + // unsized binary literals single character + luv = 'o0; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 'o0", luv); err=1; end + luv = 'o5; if (luv !== 16'b0000_0000_0000_0101) begin $display("FAILED -- luv = 'b%b != 'o5", luv); err=1; end + luv = 'ox; if (luv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 'ox", luv); err=1; end + luv = 'oz; if (luv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 'oz", luv); err=1; end + // unsized binary literals two characters + luv = 'o00; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 'o00", luv); err=1; end + luv = 'o55; if (luv !== 16'b0000_0000_0010_1101) begin $display("FAILED -- luv = 'b%b != 'o55", luv); err=1; end + luv = 'oxx; if (luv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 'oxx", luv); err=1; end + luv = 'ozz; if (luv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 'ozz", luv); err=1; end + luv = 'o5x; if (luv !== 16'b0000_0000_0010_1xxx) begin $display("FAILED -- luv = 'b%b != 'o5x", luv); err=1; end + luv = 'o5z; if (luv !== 16'b0000_0000_0010_1zzz) begin $display("FAILED -- luv = 'b%b != 'o5z", luv); err=1; end + luv = 'ox5; if (luv !== 16'bxxxx_xxxx_xxxx_x101) begin $display("FAILED -- luv = 'b%b != 'ox5", luv); err=1; end + luv = 'oz5; if (luv !== 16'bzzzz_zzzz_zzzz_z101) begin $display("FAILED -- luv = 'b%b != 'oz5", luv); err=1; end + + // unsized binary literals single character + luv = 'h0; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 'h0", luv); err=1; end + luv = 'h9; if (luv !== 16'b0000_0000_0000_1001) begin $display("FAILED -- luv = 'b%b != 'h9", luv); err=1; end + luv = 'hx; if (luv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 'hx", luv); err=1; end + luv = 'hz; if (luv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 'hz", luv); err=1; end + // unsized binary literals two characters + luv = 'h00; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 'h00", luv); err=1; end + luv = 'h99; if (luv !== 16'b0000_0000_1001_1001) begin $display("FAILED -- luv = 'b%b != 'h99", luv); err=1; end + luv = 'hxx; if (luv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 'hxx", luv); err=1; end + luv = 'hzz; if (luv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 'hzz", luv); err=1; end + luv = 'h9x; if (luv !== 16'b0000_0000_1001_xxxx) begin $display("FAILED -- luv = 'b%b != 'h9x", luv); err=1; end + luv = 'h9z; if (luv !== 16'b0000_0000_1001_zzzz) begin $display("FAILED -- luv = 'b%b != 'h9z", luv); err=1; end + luv = 'hx9; if (luv !== 16'bxxxx_xxxx_xxxx_1001) begin $display("FAILED -- luv = 'b%b != 'hx9", luv); err=1; end + luv = 'hz9; if (luv !== 16'bzzzz_zzzz_zzzz_1001) begin $display("FAILED -- luv = 'b%b != 'hz9", luv); err=1; end + + // unsized binary literals single character + luv = 'd0; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 'd0", luv); err=1; end + luv = 'd9; if (luv !== 16'b0000_0000_0000_1001) begin $display("FAILED -- luv = 'b%b != 'd9", luv); err=1; end + luv = 'dx; if (luv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 'dx", luv); err=1; end + luv = 'dz; if (luv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 'dz", luv); err=1; end + // unsized binary literals two characters + luv = 'd00; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 'd00", luv); err=1; end + luv = 'd99; if (luv !== 16'b0000_0000_0110_0011) begin $display("FAILED -- luv = 'b%b != 'd99", luv); err=1; end +// luv = 'dxx; if (luv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 'dxx", luv); err=1; end +// luv = 'dzz; if (luv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 'dzz", luv); err=1; end + + + // unsized binary literals single character + luv = 15'b0; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 15'b0", luv); err=1; end + luv = 15'b1; if (luv !== 16'b0000_0000_0000_0001) begin $display("FAILED -- luv = 'b%b != 15'b1", luv); err=1; end + luv = 15'bx; if (luv !== 16'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 15'bx", luv); err=1; end + luv = 15'bz; if (luv !== 16'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 15'bz", luv); err=1; end + // unsized binary literals two characters + luv = 15'b00; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 15'b00", luv); err=1; end + luv = 15'b11; if (luv !== 16'b0000_0000_0000_0011) begin $display("FAILED -- luv = 'b%b != 15'b11", luv); err=1; end + luv = 15'bxx; if (luv !== 16'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 15'bxx", luv); err=1; end + luv = 15'bzz; if (luv !== 16'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 15'bzz", luv); err=1; end + luv = 15'b1x; if (luv !== 16'b0000_0000_0000_001x) begin $display("FAILED -- luv = 'b%b != 15'b1x", luv); err=1; end + luv = 15'b1z; if (luv !== 16'b0000_0000_0000_001z) begin $display("FAILED -- luv = 'b%b != 15'b1z", luv); err=1; end + luv = 15'bx1; if (luv !== 16'b0xxx_xxxx_xxxx_xxx1) begin $display("FAILED -- luv = 'b%b != 15'bx1", luv); err=1; end + luv = 15'bz1; if (luv !== 16'b0zzz_zzzz_zzzz_zzz1) begin $display("FAILED -- luv = 'b%b != 15'bz1", luv); err=1; end + + // unsized binary literals single character + luv = 15'o0; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 15'o0", luv); err=1; end + luv = 15'o5; if (luv !== 16'b0000_0000_0000_0101) begin $display("FAILED -- luv = 'b%b != 15'o5", luv); err=1; end + luv = 15'ox; if (luv !== 16'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 15'ox", luv); err=1; end + luv = 15'oz; if (luv !== 16'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 15'oz", luv); err=1; end + // unsized binary literals two characters + luv = 15'o00; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 15'o00", luv); err=1; end + luv = 15'o55; if (luv !== 16'b0000_0000_0010_1101) begin $display("FAILED -- luv = 'b%b != 15'o55", luv); err=1; end + luv = 15'oxx; if (luv !== 16'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 15'oxx", luv); err=1; end + luv = 15'ozz; if (luv !== 16'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 15'ozz", luv); err=1; end + luv = 15'o5x; if (luv !== 16'b0000_0000_0010_1xxx) begin $display("FAILED -- luv = 'b%b != 15'o5x", luv); err=1; end + luv = 15'o5z; if (luv !== 16'b0000_0000_0010_1zzz) begin $display("FAILED -- luv = 'b%b != 15'o5z", luv); err=1; end + luv = 15'ox5; if (luv !== 16'b0xxx_xxxx_xxxx_x101) begin $display("FAILED -- luv = 'b%b != 15'ox5", luv); err=1; end + luv = 15'oz5; if (luv !== 16'b0zzz_zzzz_zzzz_z101) begin $display("FAILED -- luv = 'b%b != 15'oz5", luv); err=1; end + + // unsized binary literals single character + luv = 15'h0; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 15'h0", luv); err=1; end + luv = 15'h9; if (luv !== 16'b0000_0000_0000_1001) begin $display("FAILED -- luv = 'b%b != 15'h9", luv); err=1; end + luv = 15'hx; if (luv !== 16'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 15'hx", luv); err=1; end + luv = 15'hz; if (luv !== 16'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 15'hz", luv); err=1; end + // unsized binary literals two characters + luv = 15'h00; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 15'h00", luv); err=1; end + luv = 15'h99; if (luv !== 16'b0000_0000_1001_1001) begin $display("FAILED -- luv = 'b%b != 15'h99", luv); err=1; end + luv = 15'hxx; if (luv !== 16'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 15'hxx", luv); err=1; end + luv = 15'hzz; if (luv !== 16'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 15'hzz", luv); err=1; end + luv = 15'h9x; if (luv !== 16'b0000_0000_1001_xxxx) begin $display("FAILED -- luv = 'b%b != 15'h9x", luv); err=1; end + luv = 15'h9z; if (luv !== 16'b0000_0000_1001_zzzz) begin $display("FAILED -- luv = 'b%b != 15'h9z", luv); err=1; end + luv = 15'hx9; if (luv !== 16'b0xxx_xxxx_xxxx_1001) begin $display("FAILED -- luv = 'b%b != 15'hx9", luv); err=1; end + luv = 15'hz9; if (luv !== 16'b0zzz_zzzz_zzzz_1001) begin $display("FAILED -- luv = 'b%b != 15'hz9", luv); err=1; end + + // unsized binary literals single character + luv = 15'd0; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 15'd0", luv); err=1; end + luv = 15'd9; if (luv !== 16'b0000_0000_0000_1001) begin $display("FAILED -- luv = 'b%b != 15'd9", luv); err=1; end + luv = 15'dx; if (luv !== 16'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 15'dx", luv); err=1; end + luv = 15'dz; if (luv !== 16'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 15'dz", luv); err=1; end + // unsized binary literals two characters + luv = 15'd00; if (luv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- luv = 'b%b != 15'd00", luv); err=1; end + luv = 15'd99; if (luv !== 16'b0000_0000_0110_0011) begin $display("FAILED -- luv = 'b%b != 15'd99", luv); err=1; end +// luv = 15'dxx; if (luv !== 16'b0xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- luv = 'b%b != 15'dxx", luv); err=1; end +// luv = 15'dzz; if (luv !== 16'b0zzz_zzzz_zzzz_zzzz) begin $display("FAILED -- luv = 'b%b != 15'dzz", luv); err=1; end + + + + + // unsized binary literals single character + lsv = 'sb0; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 'sb0", lsv); err=1; end + lsv = 'sb1; if (lsv !== 16'b0000_0000_0000_0001) begin $display("FAILED -- lsv = 'b%b != 'sb1", lsv); err=1; end + lsv = 'sbx; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 'sbx", lsv); err=1; end + lsv = 'sbz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 'sbz", lsv); err=1; end + // unsized binary literals two characters + lsv = 'sb00; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 'sb00", lsv); err=1; end + lsv = 'sb11; if (lsv !== 16'b0000_0000_0000_0011) begin $display("FAILED -- lsv = 'b%b != 'sb11", lsv); err=1; end + lsv = 'sbxx; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 'sbxx", lsv); err=1; end + lsv = 'sbzz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 'sbzz", lsv); err=1; end + lsv = 'sb1x; if (lsv !== 16'b0000_0000_0000_001x) begin $display("FAILED -- lsv = 'b%b != 'sb1x", lsv); err=1; end + lsv = 'sb1z; if (lsv !== 16'b0000_0000_0000_001z) begin $display("FAILED -- lsv = 'b%b != 'sb1z", lsv); err=1; end + lsv = 'sbx1; if (lsv !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- lsv = 'b%b != 'sbx1", lsv); err=1; end + lsv = 'sbz1; if (lsv !== 16'bzzzz_zzzz_zzzz_zzz1) begin $display("FAILED -- lsv = 'b%b != 'sbz1", lsv); err=1; end + + // unsized binary literals single character + lsv = 'so0; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 'so0", lsv); err=1; end + lsv = 'so5; if (lsv !== 16'b0000_0000_0000_0101) begin $display("FAILED -- lsv = 'b%b != 'so5", lsv); err=1; end + lsv = 'sox; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 'sox", lsv); err=1; end + lsv = 'soz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 'soz", lsv); err=1; end + // unsized binary literals two characters + lsv = 'so00; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 'so00", lsv); err=1; end + lsv = 'so55; if (lsv !== 16'b0000_0000_0010_1101) begin $display("FAILED -- lsv = 'b%b != 'so55", lsv); err=1; end + lsv = 'soxx; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 'soxx", lsv); err=1; end + lsv = 'sozz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 'sozz", lsv); err=1; end + lsv = 'so5x; if (lsv !== 16'b0000_0000_0010_1xxx) begin $display("FAILED -- lsv = 'b%b != 'so5x", lsv); err=1; end + lsv = 'so5z; if (lsv !== 16'b0000_0000_0010_1zzz) begin $display("FAILED -- lsv = 'b%b != 'so5z", lsv); err=1; end + lsv = 'sox5; if (lsv !== 16'bxxxx_xxxx_xxxx_x101) begin $display("FAILED -- lsv = 'b%b != 'sox5", lsv); err=1; end + lsv = 'soz5; if (lsv !== 16'bzzzz_zzzz_zzzz_z101) begin $display("FAILED -- lsv = 'b%b != 'soz5", lsv); err=1; end + + // unsized binary literals single character + lsv = 'sh0; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 'sh0", lsv); err=1; end + lsv = 'sh9; if (lsv !== 16'b0000_0000_0000_1001) begin $display("FAILED -- lsv = 'b%b != 'sh9", lsv); err=1; end + lsv = 'shx; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 'shx", lsv); err=1; end + lsv = 'shz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 'shz", lsv); err=1; end + // unsized binary literals two characters + lsv = 'sh00; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 'sh00", lsv); err=1; end + lsv = 'sh99; if (lsv !== 16'b0000_0000_1001_1001) begin $display("FAILED -- lsv = 'b%b != 'sh99", lsv); err=1; end + lsv = 'shxx; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 'shxx", lsv); err=1; end + lsv = 'shzz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 'shzz", lsv); err=1; end + lsv = 'sh9x; if (lsv !== 16'b0000_0000_1001_xxxx) begin $display("FAILED -- lsv = 'b%b != 'sh9x", lsv); err=1; end + lsv = 'sh9z; if (lsv !== 16'b0000_0000_1001_zzzz) begin $display("FAILED -- lsv = 'b%b != 'sh9z", lsv); err=1; end + lsv = 'shx9; if (lsv !== 16'bxxxx_xxxx_xxxx_1001) begin $display("FAILED -- lsv = 'b%b != 'shx9", lsv); err=1; end + lsv = 'shz9; if (lsv !== 16'bzzzz_zzzz_zzzz_1001) begin $display("FAILED -- lsv = 'b%b != 'shz9", lsv); err=1; end + + // unsized binary literals single character + lsv = 'sd0; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 'sd0", lsv); err=1; end + lsv = 'sd9; if (lsv !== 16'b0000_0000_0000_1001) begin $display("FAILED -- lsv = 'b%b != 'sd9", lsv); err=1; end + lsv = 'sdx; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 'sdx", lsv); err=1; end + lsv = 'sdz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 'sdz", lsv); err=1; end + // unsized binary literals two characters + lsv = 'sd00; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 'sd00", lsv); err=1; end + lsv = 'sd99; if (lsv !== 16'b0000_0000_0110_0011) begin $display("FAILED -- lsv = 'b%b != 'sd99", lsv); err=1; end +// lsv = 'sdxx; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 'sdxx", lsv); err=1; end +// lsv = 'sdzz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 'sdzz", lsv); err=1; end + + + // unsized binary literals single character + lsv = 15'sb0; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 15'sb0", lsv); err=1; end + lsv = 15'sb1; if (lsv !== 16'b0000_0000_0000_0001) begin $display("FAILED -- lsv = 'b%b != 15'sb1", lsv); err=1; end + lsv = 15'sbx; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 15'sbx", lsv); err=1; end + lsv = 15'sbz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 15'sbz", lsv); err=1; end + // unsized binary literals two characters + lsv = 15'sb00; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 15'sb00", lsv); err=1; end + lsv = 15'sb11; if (lsv !== 16'b0000_0000_0000_0011) begin $display("FAILED -- lsv = 'b%b != 15'sb11", lsv); err=1; end + lsv = 15'sbxx; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 15'sbxx", lsv); err=1; end + lsv = 15'sbzz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 15'sbzz", lsv); err=1; end + lsv = 15'sb1x; if (lsv !== 16'b0000_0000_0000_001x) begin $display("FAILED -- lsv = 'b%b != 15'sb1x", lsv); err=1; end + lsv = 15'sb1z; if (lsv !== 16'b0000_0000_0000_001z) begin $display("FAILED -- lsv = 'b%b != 15'sb1z", lsv); err=1; end + lsv = 15'sbx1; if (lsv !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- lsv = 'b%b != 15'sbx1", lsv); err=1; end + lsv = 15'sbz1; if (lsv !== 16'bzzzz_zzzz_zzzz_zzz1) begin $display("FAILED -- lsv = 'b%b != 15'sbz1", lsv); err=1; end + + // unsized binary literals single character + lsv = 15'so0; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 15'so0", lsv); err=1; end + lsv = 15'so5; if (lsv !== 16'b0000_0000_0000_0101) begin $display("FAILED -- lsv = 'b%b != 15'so5", lsv); err=1; end + lsv = 15'sox; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 15'sox", lsv); err=1; end + lsv = 15'soz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 15'soz", lsv); err=1; end + // unsized binary literals two characters + lsv = 15'so00; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 15'so00", lsv); err=1; end + lsv = 15'so55; if (lsv !== 16'b0000_0000_0010_1101) begin $display("FAILED -- lsv = 'b%b != 15'so55", lsv); err=1; end + lsv = 15'soxx; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 15'soxx", lsv); err=1; end + lsv = 15'sozz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 15'sozz", lsv); err=1; end + lsv = 15'so5x; if (lsv !== 16'b0000_0000_0010_1xxx) begin $display("FAILED -- lsv = 'b%b != 15'so5x", lsv); err=1; end + lsv = 15'so5z; if (lsv !== 16'b0000_0000_0010_1zzz) begin $display("FAILED -- lsv = 'b%b != 15'so5z", lsv); err=1; end + lsv = 15'sox5; if (lsv !== 16'bxxxx_xxxx_xxxx_x101) begin $display("FAILED -- lsv = 'b%b != 15'sox5", lsv); err=1; end + lsv = 15'soz5; if (lsv !== 16'bzzzz_zzzz_zzzz_z101) begin $display("FAILED -- lsv = 'b%b != 15'soz5", lsv); err=1; end + + // unsized binary literals single character + lsv = 15'sh0; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 15'sh0", lsv); err=1; end + lsv = 15'sh9; if (lsv !== 16'b0000_0000_0000_1001) begin $display("FAILED -- lsv = 'b%b != 15'sh9", lsv); err=1; end + lsv = 15'shx; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 15'shx", lsv); err=1; end + lsv = 15'shz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 15'shz", lsv); err=1; end + // unsized binary literals two characters + lsv = 15'sh00; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 15'sh00", lsv); err=1; end + lsv = 15'sh99; if (lsv !== 16'b0000_0000_1001_1001) begin $display("FAILED -- lsv = 'b%b != 15'sh99", lsv); err=1; end + lsv = 15'shxx; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 15'shxx", lsv); err=1; end + lsv = 15'shzz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 15'shzz", lsv); err=1; end + lsv = 15'sh9x; if (lsv !== 16'b0000_0000_1001_xxxx) begin $display("FAILED -- lsv = 'b%b != 15'sh9x", lsv); err=1; end + lsv = 15'sh9z; if (lsv !== 16'b0000_0000_1001_zzzz) begin $display("FAILED -- lsv = 'b%b != 15'sh9z", lsv); err=1; end + lsv = 15'shx9; if (lsv !== 16'bxxxx_xxxx_xxxx_1001) begin $display("FAILED -- lsv = 'b%b != 15'shx9", lsv); err=1; end + lsv = 15'shz9; if (lsv !== 16'bzzzz_zzzz_zzzz_1001) begin $display("FAILED -- lsv = 'b%b != 15'shz9", lsv); err=1; end + + // unsized binary literals single character + lsv = 15'sd0; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 15'sd0", lsv); err=1; end + lsv = 15'sd9; if (lsv !== 16'b0000_0000_0000_1001) begin $display("FAILED -- lsv = 'b%b != 15'sd9", lsv); err=1; end + lsv = 15'sdx; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 15'sdx", lsv); err=1; end + lsv = 15'sdz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 15'sdz", lsv); err=1; end + // unsized binary literals two characters + lsv = 15'sd00; if (lsv !== 16'b0000_0000_0000_0000) begin $display("FAILED -- lsv = 'b%b != 15'sd00", lsv); err=1; end + lsv = 15'sd99; if (lsv !== 16'b0000_0000_0110_0011) begin $display("FAILED -- lsv = 'b%b != 15'sd99", lsv); err=1; end +// lsv = 15'sdxx; if (lsv !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- lsv = 'b%b != 15'sdxx", lsv); err=1; end +// lsv = 15'sdzz; if (lsv !== 16'bzzzz_zzzz_zzzz_zzzz) begin $display("FAILED -- lsv = 'b%b != 15'sdzz", lsv); err=1; end + + if (!err) $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/sv_macro.v b/ivtest/ivltests/sv_macro.v new file mode 100644 index 000000000..f05ca7903 --- /dev/null +++ b/ivtest/ivltests/sv_macro.v @@ -0,0 +1,37 @@ + + +`define FOO(val=42, text="42") do_foo(val, text) + +module main; + + int ref_val; + string ref_text; + task do_foo(int val, string text); + if (val!=ref_val || text!=ref_text) begin + $display("FAILED -- val=%d (expect %d), text=%0s, (expect %0s)", + val, ref_val, text, ref_text); + $finish; + end + endtask // do_foo + + initial begin + ref_val = 42; + ref_text = "42"; + `FOO(,); + + ref_val = 42; + ref_text = "41"; + `FOO(,"41"); + + ref_val = 41; + ref_text = "42"; + `FOO(41,); + + ref_val = 41; + ref_text = "41"; + `FOO(41,"41"); + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/sv_macro2.v b/ivtest/ivltests/sv_macro2.v new file mode 100644 index 000000000..b3a9878a1 --- /dev/null +++ b/ivtest/ivltests/sv_macro2.v @@ -0,0 +1,9 @@ +`define msg(x,y) `"x: `\`"y`\`"`" + +module test(); + +initial begin + $display(`msg(left side,right side)); +end + +endmodule diff --git a/ivtest/ivltests/sv_macro3a.v b/ivtest/ivltests/sv_macro3a.v new file mode 100644 index 000000000..9f362d0d5 --- /dev/null +++ b/ivtest/ivltests/sv_macro3a.v @@ -0,0 +1,19 @@ +`define PREFIX my_prefix +`define SUFFIX my_suffix + +`define BACKTICK "`" + +`define name1 `PREFIX``_```SUFFIX +`define name2(p,s) p``_``s + +`define stringify(text) `"text`" + +module test(); + +initial begin + $display(`BACKTICK); + $display(`stringify(`name1)); + $display(`stringify(`name2(`PREFIX, `SUFFIX))); +end + +endmodule diff --git a/ivtest/ivltests/sv_macro3b.v b/ivtest/ivltests/sv_macro3b.v new file mode 100644 index 000000000..f8a0a14af --- /dev/null +++ b/ivtest/ivltests/sv_macro3b.v @@ -0,0 +1,19 @@ +`define PREFIX_ my_prefix_ +`define SUFFIX my_suffix + +`define BACKTICK "`" + +`define name1 `PREFIX``_```SUFFIX +`define name2(p,s) p``_``s + +`define stringify(text) `"text`" + +module test(); + +initial begin + $display(`BACKTICK); + $display(`stringify(`name1)); + $display(`stringify(`name2(`PREFIX, `SUFFIX))); +end + +endmodule diff --git a/ivtest/ivltests/sv_new_array_error.v b/ivtest/ivltests/sv_new_array_error.v new file mode 100644 index 000000000..eeca3c8e2 --- /dev/null +++ b/ivtest/ivltests/sv_new_array_error.v @@ -0,0 +1,5 @@ +module test(); + +logic [1:0] array = new[4]; + +endmodule diff --git a/ivtest/ivltests/sv_package.v b/ivtest/ivltests/sv_package.v new file mode 100644 index 000000000..f9c3ef12b --- /dev/null +++ b/ivtest/ivltests/sv_package.v @@ -0,0 +1,84 @@ +// This tests SystemVerilog packages +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +package p1; + localparam int p1_prmt = 100+10+1; + typedef bit [10+1-1:0] p1_type; + function int p1_func (int x); + p1_func = x+10+1; + endfunction +endpackage + +package p2; + localparam int p1_prmt = 100+20+1; + typedef bit [20+1-1:0] p1_type; + function int p1_func (int x); + p1_func = x+20+1; + endfunction + + localparam int p2_prmt = 100+20+2; + typedef bit [20+2-1:0] p2_type; + function int p2_func (int x); + p2_func = x+20+2; + endfunction +endpackage + +package p3; + localparam int p1_prmt = 100+30+1; + typedef bit [30+1-1:0] p1_type; + function int p1_func (int x); + p1_func = x+30+1; + endfunction + + localparam int p2_prmt = 100+30+2; + typedef bit [30+2-1:0] p2_type; + function int p2_func (int x); + p2_func = x+30+2; + endfunction + + localparam int p3_prmt = 100+30+3; + typedef bit [30+3-1:0] p3_type; + function int p3_func (int x); + p3_func = x+30+3; + endfunction +endpackage + + +module test (); + + // import all from p1 + import p1::*; + // import only p2_* from p2 + import p2::p2_prmt; + import p2::p2_type; + import p2::p2_func; + // import nothing from p3 + + // declare a set of variables + p1_type p1_var; + p2_type p2_var; + p3::p3_type p3_var; + + // error counter + bit err = 0; + + initial begin + // test parameters + if ( p1_prmt !== 100+10+1) begin $display("FAILED -- p1_prmt = %d != 100+10+1", p1_prmt); err=1; end + if ( p2_prmt !== 100+20+2) begin $display("FAILED -- p2_prmt = %d != 100+20+2", p2_prmt); err=1; end + if (p3::p3_prmt !== 100+30+3) begin $display("FAILED -- p3::p3_prmt = %d != 100+30+3", p3::p3_prmt); err=1; end + // test variable bit sizes + if ($bits(p1_var) !== 10+1) begin $display("FAILED -- lv = %d != 10+1", $bits(p1_var)); err=1; end + if ($bits(p2_var) !== 20+2) begin $display("FAILED -- lv = %d != 20+2", $bits(p2_var)); err=1; end + if ($bits(p3_var) !== 30+3) begin $display("FAILED -- lv = %d != 30+3", $bits(p3_var)); err=1; end + // test functions + if ( p1_func(1000) !== 1000+10+1) begin $display("FAILED -- p1_func(1000) = %d != 1000+10+1", p1_func(1000)); err=1; end + if ( p2_func(1000) !== 1000+20+2) begin $display("FAILED -- p2_func(1000) = %d != 1000+20+2", p2_func(1000)); err=1; end + if (p3::p3_func(1000) !== 1000+30+3) begin $display("FAILED -- p3::p3_func(1000) = %d != 1000+30+3", p3::p3_func(1000)); err=1; end + + if (!err) $display("PASSED"); + end + +endmodule // test diff --git a/ivtest/ivltests/sv_package2.v b/ivtest/ivltests/sv_package2.v new file mode 100644 index 000000000..1269be002 --- /dev/null +++ b/ivtest/ivltests/sv_package2.v @@ -0,0 +1,47 @@ + +// This tests SystemVerilog packages. Make sure that names that +// are the same is different packages can be references properly +// in the various packages. + +package p1; + localparam step = 1; + function int next_step(int x); + next_step = x + step; + endfunction // next_step +endpackage // p1 + +package p2; + localparam step = 2; + function int next_step(int x); + next_step = x + step; + endfunction // next_step +endpackage // p2 + +program main; + int x; + initial begin + if (p1::step != 1) begin + $display("FAILED -- p1::step == %0d", p1::step); + $finish; + end + + if (p2::step != 2) begin + $display("FAILED -- p2::step == %0d", p1::step); + $finish; + end + + x = p1::next_step(0); + if (x != 1) begin + $display("FAILED -- p1::next_step(0) --> %0d", x); + $finish; + end + + x = p2::next_step(0); + if (x != 2) begin + $display("FAILED -- p2::next_step(0) --> %0d", x); + $finish; + end + + $display("PASSED"); + end +endprogram // main diff --git a/ivtest/ivltests/sv_package3.v b/ivtest/ivltests/sv_package3.v new file mode 100644 index 000000000..ef6d0a005 --- /dev/null +++ b/ivtest/ivltests/sv_package3.v @@ -0,0 +1,34 @@ + +// This tests SystemVerilog packages. Make sure that typedef +// names work. + +package p1; + typedef struct packed { + bit [7:0] high; + bit [7:0] low; + } word_t; +endpackage + +program main; + + import p1::word_t; + word_t word; + + initial begin + if ($bits(word) != 16) begin + $display("FAILED -- $bits(word) == %0d", $bits(word)); + $finish; + end + + word.low = 'h55; + word.high = 'haa; + + if (word != 'haa55) begin + $display("FAILED -- word = %h", word); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin +endprogram // main diff --git a/ivtest/ivltests/sv_package4.v b/ivtest/ivltests/sv_package4.v new file mode 100644 index 000000000..c776acdc3 --- /dev/null +++ b/ivtest/ivltests/sv_package4.v @@ -0,0 +1,41 @@ + +// This tests SystemVerilog packages. Make sure that typedef +// names work. + +package p1; + typedef struct packed { + bit [7:0] high; + bit [7:0] low; + } word_t; + + word_t word; +endpackage + +module main; + + import p1::word; + + initial begin + if ($bits(word) != 16) begin + $display("FAILED -- $bits(p1::word) == %0d", $bits(p1::word)); + $finish; + end + + word = 'haa55; + + if (word != 'haa55) begin + $display("FAILED -- p1::word = %h", word); + $finish; + end + + word.low = 'h66; + word.high = 'hbb; + if (word != 'hbb66 || word.low != 8'h66) begin + $display("FAILED -- p1::word = %h", word); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/sv_package5.v b/ivtest/ivltests/sv_package5.v new file mode 100644 index 000000000..baa6dea58 --- /dev/null +++ b/ivtest/ivltests/sv_package5.v @@ -0,0 +1,29 @@ + +// This tests SystemVerilog packages. Make sure that typedef +// names work. + +package p1; + localparam step = 5; + task foo(output int y, input int x); + y = x + step; + endtask // foo +endpackage + +module main; + + import p1::foo; + int y, x; + + initial begin + x = 5; + foo(y, x); + + if (y != 10) begin + $display("FAILED -- x=%0d, y=%0d", x, y); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/sv_packed_port1.v b/ivtest/ivltests/sv_packed_port1.v new file mode 100644 index 000000000..ab3a4027e --- /dev/null +++ b/ivtest/ivltests/sv_packed_port1.v @@ -0,0 +1,33 @@ + +module main; + + typedef struct packed { + logic [3:0] adr; + logic [3:0] val; + } foo_s; + + foo_s [1:0][3:0] ival; + foo_s [1:0][3:0] oval; + + genvar g; + for (g = 0 ; g < 4 ; g = g+1) begin:loop + TEST dut(.in(ival[0][g]), + .out(oval[0][g])); + end + + initial begin + ival = 'hx3x2x1x0; + #1 $display("ival = %h, oval = %h", ival, oval); + if (oval !== 64'hzzzzzzzzxcxdxexf) begin + $display("FAILED -- oval=%h", oval); + $finish; + end + $display("PASSED"); + $finish; + end + +endmodule // main + +module TEST (input wire [7:0] in, output wire [7:0] out); + assign out = ~in; +endmodule // TEST diff --git a/ivtest/ivltests/sv_packed_port2.v b/ivtest/ivltests/sv_packed_port2.v new file mode 100644 index 000000000..90137b1ac --- /dev/null +++ b/ivtest/ivltests/sv_packed_port2.v @@ -0,0 +1,33 @@ + +module main; + + typedef struct packed { + logic [3:0] adr; + logic [3:0] val; + } foo_s; + + foo_s [3:0][1:0] ival; + foo_s [3:0][1:0] oval; + + genvar g; + for (g = 0 ; g < 4 ; g = g+1) begin:loop + TEST dut(.in(ival[g][0]), + .out(oval[g][0])); + end + + initial begin + ival = 'hx3x2x1x0; + #1 $display("ival = %h, oval = %h", ival, oval); + if (oval !== 64'hzzxxzzxxzzxdzzxf) begin + $display("FAILED -- oval=%h", oval); + $finish; + end + $display("PASSED"); + $finish; + end + +endmodule // main + +module TEST (input wire [7:0] in, output wire [7:0] out); + assign out = ~in; +endmodule // TEST diff --git a/ivtest/ivltests/sv_param_port_list.v b/ivtest/ivltests/sv_param_port_list.v new file mode 100644 index 000000000..8920d42cf --- /dev/null +++ b/ivtest/ivltests/sv_param_port_list.v @@ -0,0 +1,32 @@ +module mod #( + parameter A = 1, + localparam B = A + 1, + parameter C = B - 1 +) ( + input [A-1:0] a, + input [B-1:0] b, + input [C-1:0] c +); + +endmodule + +module top(); + +reg [3:0] a = 'ha; +reg [4:0] b = 'hb; +reg [5:0] c = 'hc; + +mod #(4, 6) m(a, b, c); + +initial begin + $display("%0d %0d %0d", m.A, m.B, m.C); + $display("%0d %0d %0d", $bits(m.a), $bits(m.b), $bits(m.c)); + if (m.A === 4 && $bits(m.a) === 4 + && m.B === 5 && $bits(m.b) === 5 + && m.C === 6 && $bits(m.c) === 6) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/sv_parameter_type.v b/ivtest/ivltests/sv_parameter_type.v new file mode 100644 index 000000000..c4d6c82bd --- /dev/null +++ b/ivtest/ivltests/sv_parameter_type.v @@ -0,0 +1,76 @@ +// SystemVerilog parameter type test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module test (); + + // logic vector + logic [15:0] lv; + + // error counter + bit err = 0; + + // system clock (does not have any real function in the test) + logic clk = 1; + + always #5 clk = ~clk; + + // counters + int cnt; + int cnt_bit ; + int cnt_byte; + int cnt_int ; + int cnt_ar1d; + int cnt_ar2d; + + // sizes + int siz_bit ; + int siz_byte; + int siz_int ; + int siz_ar1d; + int siz_ar2d; + + // add all counters + assign cnt = cnt_bit + cnt_byte + cnt_int + cnt_ar1d + cnt_ar2d; + + // finish report + initial begin + // some unnecessary delay + wait (cnt); + + // check if variable sizes are correct + if (siz_bit != 1) begin $display("FAILED -- siz_bit = %0d", siz_bit ); err=1; end + if (siz_byte != 8) begin $display("FAILED -- siz_byte = %0d", siz_byte); err=1; end + if (siz_int != 32) begin $display("FAILED -- siz_int = %0d", siz_int ); err=1; end + if (siz_ar1d != 24) begin $display("FAILED -- siz_ar1d = %0d", siz_ar1d); err=1; end + if (siz_ar2d != 16) begin $display("FAILED -- siz_ar2d = %0d", siz_ar2d); err=1; end + + if (!err) $display("PASSED"); + $finish(); + end + + // instances with various types + mod_typ #(.TYP (bit )) mod_bit (clk, cnt_bit [ 1-1:0], siz_bit ); + mod_typ #(.TYP (byte )) mod_byte (clk, cnt_byte[ 8-1:0], siz_byte); + mod_typ #(.TYP (int )) mod_int (clk, cnt_int [32-1:0], siz_int ); + mod_typ #(.TYP (bit [23:0] )) mod_ar1d (clk, cnt_ar1d[24-1:0], siz_ar1d); + mod_typ #(.TYP (bit [3:0][3:0])) mod_ar2d (clk, cnt_ar2d[16-1:0], siz_ar2d); + +endmodule // test + + +module mod_typ #( + parameter type TYP = byte +)( + input logic clk, + output TYP cnt = 0, + output int siz +); + + always @ (posedge clk) + cnt <= cnt + 1; + + assign siz = $bits (cnt); + +endmodule diff --git a/ivtest/ivltests/sv_pkg_class.v b/ivtest/ivltests/sv_pkg_class.v new file mode 100644 index 000000000..7bd6337f8 --- /dev/null +++ b/ivtest/ivltests/sv_pkg_class.v @@ -0,0 +1,31 @@ +package p_defs; + class a_class; + int id_; + + function new(int id); + id_ = id; + endfunction + + task display(); + $display("This is class %0d.", id_); + endtask + + endclass + +endpackage + +// This should print the following: +// This is class 2. +// This is class 1. +module top; + import p_defs::a_class; + + a_class ac1; + a_class ac2; + initial begin + ac1 = new(1); + ac2 = new(2); + ac2.display(); + ac1.display(); + end +endmodule diff --git a/ivtest/ivltests/sv_port_default1.v b/ivtest/ivltests/sv_port_default1.v new file mode 100644 index 000000000..266f11ef9 --- /dev/null +++ b/ivtest/ivltests/sv_port_default1.v @@ -0,0 +1,38 @@ + +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + class foo_t; + int int_val; + string text_val; + + function new (int int_init, string text_init = "default text"); + int_val = int_init; + text_val = text_init; + endfunction : new + + endclass : foo_t + + + foo_t obj1; + + initial begin + obj1 = new (5, "new text"); + if (obj1.int_val != 5 || obj1.text_val != "new text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.text_val=%0s", obj1.int_val, obj1.text_val); + $finish; + end + + obj1 = new (7); + if (obj1.int_val != 7 || obj1.text_val != "default text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.text_val=%0s", obj1.int_val, obj1.text_val); + $finish; + end + + $display("PASSED"); + end + +endprogram // main diff --git a/ivtest/ivltests/sv_port_default10.v b/ivtest/ivltests/sv_port_default10.v new file mode 100644 index 000000000..5cc42a184 --- /dev/null +++ b/ivtest/ivltests/sv_port_default10.v @@ -0,0 +1,31 @@ + +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + function int increment(int val, int step = 1, int flag = 1); + increment = val + step*flag; + endfunction // increment + + initial begin + + if (increment(5) !== 6) begin + $display("FAILED -- increment(5) --> %0d", increment(5)); + $finish; + end + + if (increment(5,2) !== 7) begin + $display("FAILED -- increment(5,2) --> %0d", increment(5,2)); + $finish; + end + + if (increment(5,,3) !== 8) begin + $display("FAILED -- increment(5,,3) --> %0d", increment(5,,3)); + $finish; + end + $display("PASSED"); + end + +endprogram // main diff --git a/ivtest/ivltests/sv_port_default11.v b/ivtest/ivltests/sv_port_default11.v new file mode 100644 index 000000000..8a9880112 --- /dev/null +++ b/ivtest/ivltests/sv_port_default11.v @@ -0,0 +1,35 @@ + +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + task increment(output int res, input int val, input int step = 1, input int flag = 1); + res = val + step*flag; + endtask // increment + + int res; + initial begin + + increment(res,5); + if (res !== 6) begin + $display("FAILED -- increment(5) --> %0d", res); + $finish; + end + + increment(res,5,2); + if (res !== 7) begin + $display("FAILED -- increment(5,2) --> %0d", res); + $finish; + end + + increment(res,5,,3); + if (res !== 8) begin + $display("FAILED -- increment(5,,3) --> %0d", res); + $finish; + end + $display("PASSED"); + end + +endprogram // main diff --git a/ivtest/ivltests/sv_port_default12.v b/ivtest/ivltests/sv_port_default12.v new file mode 100644 index 000000000..85e96d3c6 --- /dev/null +++ b/ivtest/ivltests/sv_port_default12.v @@ -0,0 +1,47 @@ +// Test non-constant port default value. + +module test(); + +integer a; +integer b; + +function integer k(integer i, integer j = a+b); + k = i + j; +endfunction + +wire [31:0] x = k(1); +wire [31:0] y = k(2); + +integer result; + +reg fail = 0; + +initial begin + a = 1; + b = 2; + + #0; + + result = x; + $display(result); + if (result !== 4) fail = 1; + + result = y; + $display(result); + if (result !== 5) fail = 1; + + result = k(3); + $display(result); + if (result !== 6) fail = 1; + + result = k(3,4); + $display(result); + if (result !== 7) fail = 1; + + if (fail) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/sv_port_default13.v b/ivtest/ivltests/sv_port_default13.v new file mode 100644 index 000000000..efac9bf05 --- /dev/null +++ b/ivtest/ivltests/sv_port_default13.v @@ -0,0 +1,15 @@ +// Check non-constant port default value is rejected +// in constant context. + +module test(); + +integer a; +integer b; + +function integer k(integer i, integer j = a+b); + k = i + j; +endfunction + +localparam integer result = k(3); + +endmodule diff --git a/ivtest/ivltests/sv_port_default14.v b/ivtest/ivltests/sv_port_default14.v new file mode 100644 index 000000000..249cefdc5 --- /dev/null +++ b/ivtest/ivltests/sv_port_default14.v @@ -0,0 +1,44 @@ +// Test default value for output port +// This should work, but isn't supported yet + +module test(); + +integer a; +integer b; +integer c; + +task k(input integer i = a, output integer j = b); + j = i; +endtask + +integer result; + +reg fail = 0; + +initial begin + a = 1; + b = 2; + + k(3,c); + $display(a,,b,,c); + if (a !== 1 || b !== 2 || c !== 3) fail = 1; + + k(,c); + $display(a,,b,,c); + if (a !== 1 || b !== 2 || c !== 1) fail = 1; + + k(4,); + $display(a,,b,,c); + if (a !== 1 || b !== 4 || c !== 1) fail = 1; + + k(); + $display(a,,b,,c); + if (a !== 1 || b !== 1 || c !== 1) fail = 1; + + if (fail) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/sv_port_default2.v b/ivtest/ivltests/sv_port_default2.v new file mode 100644 index 000000000..039abe7b0 --- /dev/null +++ b/ivtest/ivltests/sv_port_default2.v @@ -0,0 +1,40 @@ + +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + class foo_t; + int int_val; + string text_val; + + task init (int int_init, string text_init = "default text"); + int_val = int_init; + text_val = text_init; + endtask + + endclass : foo_t + + + foo_t obj1; + + initial begin + obj1 = new; + obj1.init(5, "new text"); + if (obj1.int_val != 5 || obj1.text_val != "new text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.text_val=%0s", obj1.int_val, obj1.text_val); + $finish; + end + + obj1 = new; + obj1.init(7); + if (obj1.int_val != 7 || obj1.text_val != "default text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.text_val=%0s", obj1.int_val, obj1.text_val); + $finish; + end + + $display("PASSED"); + end + +endprogram // main diff --git a/ivtest/ivltests/sv_port_default3.v b/ivtest/ivltests/sv_port_default3.v new file mode 100644 index 000000000..bad44aba7 --- /dev/null +++ b/ivtest/ivltests/sv_port_default3.v @@ -0,0 +1,38 @@ + +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + class foo_t; + int int_val; + logic[3:0]log_val; + + function new (int int_init, logic[3:0] log_init = 4'bzzzz); + int_val = int_init; + log_val = log_init; + endfunction : new + + endclass : foo_t + + + foo_t obj1; + + initial begin + obj1 = new (5, 4'b1010); + if (obj1.int_val != 5 || obj1.log_val !== 4'b1010) begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%0s", obj1.int_val, obj1.log_val); + $finish; + end + + obj1 = new (7); + if (obj1.int_val != 7 || obj1.log_val !== 4'bzzzz) begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%0s", obj1.int_val, obj1.log_val); + $finish; + end + + $display("PASSED"); + end + +endprogram // main diff --git a/ivtest/ivltests/sv_port_default4.v b/ivtest/ivltests/sv_port_default4.v new file mode 100644 index 000000000..24337e8fe --- /dev/null +++ b/ivtest/ivltests/sv_port_default4.v @@ -0,0 +1,40 @@ + +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + class foo_t; + int int_val; + logic [3:0] log_val; + + task init (int int_init, logic[3:0] log_init = 4'bzzzz); + int_val = int_init; + log_val = log_init; + endtask + + endclass : foo_t + + + foo_t obj1; + + initial begin + obj1 = new; + obj1.init(5, 4'b1111); + if (obj1.int_val != 5 || obj1.log_val !== 4'b1111) begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b", obj1.int_val, obj1.log_val); + $finish; + end + + obj1 = new; + obj1.init(7); + if (obj1.int_val != 7 || obj1.log_val !== 4'bzzzz) begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%0s", obj1.int_val, obj1.log_val); + $finish; + end + + $display("PASSED"); + end + +endprogram // main diff --git a/ivtest/ivltests/sv_port_default5.v b/ivtest/ivltests/sv_port_default5.v new file mode 100644 index 000000000..5bab5bae9 --- /dev/null +++ b/ivtest/ivltests/sv_port_default5.v @@ -0,0 +1,52 @@ + +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + class foo_t; + int int_val; + logic[3:0] log_val; + string text_val; + + function new (int int_init, logic[3:0]log_init = 4'bzzzz, string text_init = "default text"); + int_val = int_init; + log_val = log_init; + text_val = text_init; + endfunction : new + + endclass : foo_t + + + foo_t obj1; + + initial begin + obj1 = new (4, 4'b0101, "new text"); + if (obj1.int_val != 4 || obj1.log_val !== 4'b0101 || obj1.text_val != "new text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val); + $finish; + end + + obj1 = new (5, , "new text"); + if (obj1.int_val != 5 || obj1.log_val !== 4'bzzzz || obj1.text_val != "new text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val); + $finish; + end + + obj1 = new (6, 4'b1010); + if (obj1.int_val != 6 || obj1.log_val !== 4'b1010 || obj1.text_val != "default text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val); + $finish; + end + + obj1 = new (7); + if (obj1.int_val != 7 || obj1.text_val != "default text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.text_val=%0s", obj1.int_val, obj1.text_val); + $finish; + end + + $display("PASSED"); + end + +endprogram // main diff --git a/ivtest/ivltests/sv_port_default6.v b/ivtest/ivltests/sv_port_default6.v new file mode 100644 index 000000000..d12628d6a --- /dev/null +++ b/ivtest/ivltests/sv_port_default6.v @@ -0,0 +1,56 @@ + +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + class foo_t; + int int_val; + logic[3:0] log_val; + string text_val; + + task init (int int_init, logic[3:0]log_init = 4'bzzzz, string text_init = "default text"); + int_val = int_init; + log_val = log_init; + text_val = text_init; + endtask : init + + endclass : foo_t + + + foo_t obj1; + + initial begin + obj1 = new; + obj1.init(4, 4'b0101, "new text"); + if (obj1.int_val != 4 || obj1.log_val !== 4'b0101 || obj1.text_val != "new text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val); + $finish; + end + + obj1 = new; + obj1.init(5, , "new text"); + if (obj1.int_val != 5 || obj1.log_val !== 4'bzzzz || obj1.text_val != "new text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val); + $finish; + end + + obj1 = new; + obj1.init(6, 4'b1010); + if (obj1.int_val != 6 || obj1.log_val !== 4'b1010 || obj1.text_val != "default text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val); + $finish; + end + + obj1 = new; + obj1.init(7); + if (obj1.int_val != 7 || obj1.text_val != "default text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.text_val=%0s", obj1.int_val, obj1.text_val); + $finish; + end + + $display("PASSED"); + end + +endprogram // main diff --git a/ivtest/ivltests/sv_port_default7.v b/ivtest/ivltests/sv_port_default7.v new file mode 100644 index 000000000..d150f8243 --- /dev/null +++ b/ivtest/ivltests/sv_port_default7.v @@ -0,0 +1,60 @@ + +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + class foo_t; + int int_val; + logic[3:0] log_val; + string text_val; + + task init (int int_init, logic[3:0]log_init = 4'bzzzz, string text_init = "default text"); + this.init2(int_init, log_init, text_init); + endtask : init + + task init2 (int int_init, logic[3:0]log_init, string text_init); + int_val = int_init; + log_val = log_init; + text_val = text_init; + endtask : init2 + + endclass : foo_t + + + foo_t obj1; + + initial begin + obj1 = new; + obj1.init(4, 4'b0101, "new text"); + if (obj1.int_val != 4 || obj1.log_val !== 4'b0101 || obj1.text_val != "new text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val); + $finish; + end + + obj1 = new; + obj1.init(5, , "new text"); + if (obj1.int_val != 5 || obj1.log_val !== 4'bzzzz || obj1.text_val != "new text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val); + $finish; + end + + obj1 = new; + obj1.init(6, 4'b1010); + if (obj1.int_val != 6 || obj1.log_val !== 4'b1010 || obj1.text_val != "default text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val); + $finish; + end + + obj1 = new; + obj1.init(7); + if (obj1.int_val != 7 || obj1.text_val != "default text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.text_val=%0s", obj1.int_val, obj1.text_val); + $finish; + end + + $display("PASSED"); + end + +endprogram // main diff --git a/ivtest/ivltests/sv_port_default8.v b/ivtest/ivltests/sv_port_default8.v new file mode 100644 index 000000000..47b440408 --- /dev/null +++ b/ivtest/ivltests/sv_port_default8.v @@ -0,0 +1,60 @@ + +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + class foo_t; + int int_val; + logic[3:0] log_val; + string text_val; + + task init (int int_init, logic[3:0]log_init = 4'bzzzz, string text_init = "default text"); + this.init2(int_init, log_init, text_init); + endtask : init + + function void init2 (int int_init, logic[3:0]log_init, string text_init); + int_val = int_init; + log_val = log_init; + text_val = text_init; + endfunction : init2 + + endclass : foo_t + + + foo_t obj1; + + initial begin + obj1 = new; + obj1.init(4, 4'b0101, "new text"); + if (obj1.int_val != 4 || obj1.log_val !== 4'b0101 || obj1.text_val != "new text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val); + $finish; + end + + obj1 = new; + obj1.init(5, , "new text"); + if (obj1.int_val != 5 || obj1.log_val !== 4'bzzzz || obj1.text_val != "new text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val); + $finish; + end + + obj1 = new; + obj1.init(6, 4'b1010); + if (obj1.int_val != 6 || obj1.log_val !== 4'b1010 || obj1.text_val != "default text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val); + $finish; + end + + obj1 = new; + obj1.init(7); + if (obj1.int_val != 7 || obj1.text_val != "default text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.text_val=%0s", obj1.int_val, obj1.text_val); + $finish; + end + + $display("PASSED"); + end + +endprogram // main diff --git a/ivtest/ivltests/sv_port_default9.v b/ivtest/ivltests/sv_port_default9.v new file mode 100644 index 000000000..6944f7312 --- /dev/null +++ b/ivtest/ivltests/sv_port_default9.v @@ -0,0 +1,56 @@ + +// This tests the basic support for default arguments to task/function +// ports. The default port syntax gives SystemVerilog a limited form +// of variable argument lists. + +program main; + + class foo_t; + int int_val; + logic[3:0] log_val; + string text_val; + + function new (int int_init, logic[3:0]log_init = 4'bzzzz, string text_init = "default text"); + this.init2(int_init, log_init, text_init); + endfunction : new + + function void init2 (int int_init, logic[3:0]log_init, string text_init); + int_val = int_init; + log_val = log_init; + text_val = text_init; + endfunction : init2 + + endclass : foo_t + + + foo_t obj1; + + initial begin + obj1 = new(4, 4'b0101, "new text"); + if (obj1.int_val != 4 || obj1.log_val !== 4'b0101 || obj1.text_val != "new text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val); + $finish; + end + + obj1 = new(5, , "new text"); + if (obj1.int_val != 5 || obj1.log_val !== 4'bzzzz || obj1.text_val != "new text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val); + $finish; + end + + obj1 = new(6, 4'b1010); + if (obj1.int_val != 6 || obj1.log_val !== 4'b1010 || obj1.text_val != "default text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.log_val=%b obj1.text_val=%0s", obj1.int_val, obj1.log_val, obj1.text_val); + $finish; + end + + obj1 = new(7); + if (obj1.int_val != 7 || obj1.text_val != "default text") begin + $display("FAILED -- obj1.int_val=%0d, obj1.text_val=%0s", obj1.int_val, obj1.text_val); + $finish; + end + + $display("PASSED"); + end + +endprogram // main diff --git a/ivtest/ivltests/sv_queue1.v b/ivtest/ivltests/sv_queue1.v new file mode 100644 index 000000000..a945e23dc --- /dev/null +++ b/ivtest/ivltests/sv_queue1.v @@ -0,0 +1,95 @@ + +module main; + + string words [$], tmp_word; + int nums [$], tmp_num; + + initial begin + + words.push_back("Hello"); + words.push_back("World"); + + if (words.size != 2) begin + $display("FAILED -- words.size=%0d", words.size); + $finish; + end + + if (words[0] != "Hello") begin + $display("FAILED -- words[0] = %s", words[0]); + $finish; + end + + if (words[$] != "World") begin + $display("FAILED -- words[$] = %s", words[$]); + $finish; + end + + tmp_word = words.pop_front(); + if (tmp_word != "Hello") begin + $display("FAILED -- words.pop_front()=%s", tmp_word); + $finish; + end + + if (words[0] != words[$]) begin + $display("FAILED -- words[0](=%s) !== words[$](=%s)", words[0], words[$]); + $finish; + end + + nums.push_back(2); + nums.push_back(3); + nums.push_front(1); + + if (nums.size != 3) begin + $display("FAILED -- nums.size=%0d", nums.size); + $finish; + end + + if (nums[0] !== 1) begin + $display("FAILED -- nums[0] = %0d", nums[0]); + $finish; + end + + if (nums[$] !== 3) begin + $display("FAILED -- nums[$] = %0d", nums[$]); + $finish; + end + + tmp_num = nums.pop_back(); + if (tmp_num !== 3) begin + $display("FAILED -- tmp_num=%0d (from back)", tmp_num); + $finish; + end + + if (nums.size !== 2) begin + $display("FAILED -- nums.size after pop_back = %0d", nums.size); + $finish; + end + + if (nums[0] !== 1) begin + $display("FAILED -- nums[0] = %0d", nums[0]); + $finish; + end + + if (nums[1] !== 2) begin + $display("FAILED -- nums[1] = %0d", nums[1]); + $finish; + end + + tmp_num = nums.pop_front(); + if (tmp_num !== 1) begin + $display("FAILED == tmp_num=%0d (fron front)", tmp_num); + $finish; + end + if (nums.size !== 1) begin + $display("FAILED -- nums.size after pop_front = %0d", nums.size); + $finish; + end + + if (nums[0] !== 2) begin + $display("FAILED -- nums[0] = %0d after pop_front", nums[0]); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/sv_queue2.v b/ivtest/ivltests/sv_queue2.v new file mode 100644 index 000000000..ff352c221 --- /dev/null +++ b/ivtest/ivltests/sv_queue2.v @@ -0,0 +1,45 @@ + +module main; + + string words [$]; + int nums [$]; + + initial begin + + words.push_back("Hello"); + words.push_back("World"); + + nums.push_back(1); + nums.push_back(2); + nums.push_front(0); + + foreach (words[widx]) begin + case (widx) + 0: if (words[widx] != "Hello") begin + $display("FAILED -- words[%0d] == %s", widx, words[widx]); + $finish; + end + + 1: if (words[widx] != "World") begin + $display("FAILED -- words[%0d] == %s", widx, words[widx]); + $finish; + end + + default: + begin + $display("FAILED -- widx = %0d", widx); + $finish; + end + endcase + end + + foreach (nums[nidx]) begin + if (nidx !== nums[nidx]) begin + $display("FAILED -- nums[%0d] == %0d", nidx, nums[nidx]); + $finish; + end + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/sv_queue3.v b/ivtest/ivltests/sv_queue3.v new file mode 100644 index 000000000..77d24575d --- /dev/null +++ b/ivtest/ivltests/sv_queue3.v @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2014 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +`default_nettype none + +module main; + + string words [$]; + int nums[$]; + + initial begin + words.push_back("Hello, World!"); + nums.push_back(42); + + words = {}; + if (words.size != 0) begin + $display("FAILED -- words.size=%0d after clear", words.size); + $finish; + end + + nums = {}; + if (nums.size != 0) begin + $display("FAILED -- nums.size=%0d after clear", nums.size); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sv_queue_real.v b/ivtest/ivltests/sv_queue_real.v new file mode 100644 index 000000000..255a6e468 --- /dev/null +++ b/ivtest/ivltests/sv_queue_real.v @@ -0,0 +1,192 @@ +module top; + real q_tst [$]; + real q_tmp [$]; + real elem; + integer idx; + bit passed; + + task automatic check_size(integer size, + string fname, + integer lineno); + if (q_tst.size !== size) begin + $display("%s:%0d: Failed: queue size != %0d (%0d)", + fname, lineno, size, q_tst.size); + passed = 1'b0; + end + endtask + + task automatic check_idx_value(integer idx, + real expected, + string fname, + integer lineno); + if (q_tst[idx] != expected) begin + $display("%s:%0d: Failed: element [%0d] != %.1f (%.1f)", + fname, lineno, idx, expected, q_tst[idx]); + passed = 1'b0; + end + endtask + + initial begin + passed = 1'b1; + + q_tst.delete(0); // Warning: skip delete on an empty queue + check_size(0, `__FILE__, `__LINE__); + check_idx_value(0, 0.0, `__FILE__, `__LINE__); + + elem = q_tst.pop_front(); // Warning: cannot pop_front() an empty queue + if (elem != 0.0) begin + $display("Failed: pop_front() != 0.0 (%.1f)", elem); + passed = 1'b0; + end + + elem = q_tst.pop_back(); // Warning: cannot pop_back() an empty queue + if (elem != 0.0) begin + $display("Failed: pop_back() != 0.0 (%.1f)", elem); + passed = 1'b0; + end + + q_tst.push_back(2.0); + q_tst.push_front(1.0); + q_tst.push_back(3.0); + q_tst.push_back(100.0); + q_tst.delete(3); // Should $ work here? + q_tst.delete(3); // Warning: skip an out of range delete() + q_tst.delete(-1); // Warning: skip delete with negative index + q_tst.delete('X); // Warning: skip delete with undefined index + + check_size(3, `__FILE__, `__LINE__); + + if (q_tst[0] != 1.0) begin + $display("Failed: element [0] != 1.0 (%.1f)", q_tst[0]); + passed = 1'b0; + end + + if (q_tst[1] != 2.0) begin + $display("Failed: element [1] != 2.0 (%.1f)", q_tst[1]); + passed = 1'b0; + end + + if (q_tst[2] != 3.0) begin + $display("Failed: element [2] != 3.0 (%.1f)", q_tst[2]); + passed = 1'b0; + end + + if (q_tst[3] != 0.0) begin + $display("Failed: element [3] != 0.0 (%.1f)", q_tst[3]); + passed = 1'b0; + end + + if (q_tst[-1] != 0.0) begin + $display("Failed: element [-1] != 0.0 (%.1f)", q_tst[-1]); + passed = 1'b0; + end + + if (q_tst['X] != 0.0) begin + $display("Failed: element ['X] != 0.0 (%.1f)", q_tst['X]); + passed = 1'b0; + end + + check_idx_value(-1, 0.0, `__FILE__, `__LINE__); + check_idx_value('X, 0.0, `__FILE__, `__LINE__); + + elem = q_tst.pop_front(); + if (elem != 1.0) begin + $display("Failed: element pop_front() != 1.0 (%.1f)", elem); + passed = 1'b0; + end + + elem = q_tst.pop_back(); + if (elem != 3.0) begin + $display("Failed: element pop_back() != 3.0 (%.1f)", elem); + passed = 1'b0; + end + + check_size(1, `__FILE__, `__LINE__); + + if ((q_tst[0] != q_tst[$]) || (q_tst[0] != 2.0)) begin + $display("Failed: q_tst[0](%.1f) != q_tst[$](%.1f) != 2.0", + q_tst[0], q_tst[$]); + passed = 1'b0; + end + + q_tst.delete(); + + check_size(0, `__FILE__, `__LINE__); + + q_tst.push_front(5.0); + q_tst.push_front(100.0); + q_tst.push_back(100.0); + elem = q_tst.pop_back; + elem = q_tst.pop_front; + + check_size(1, `__FILE__, `__LINE__); + check_idx_value(0, 5.0, `__FILE__, `__LINE__); + + q_tst[0] = 1.0; + q_tst[1] = 2.5; + q_tst[1] = 2.0; + q_tst[2] = 3.0; + q_tst[-1] = 10.0; // Warning: will not be added (negative index) + q_tst['X] = 10.0; // Warning: will not be added (undefined index) + q_tst[4] = 10.0; // Warning: will not be added (out of range index) + + idx = -1; + q_tst[idx] = 10.0; // Warning: will not be added (negative index) + idx = 3'b0x1; + q_tst[idx] = 10.0; // Warning: will not be added (undefined index) + idx = 4; + q_tst[idx] = 10.0; // Warning: will not be added (out of range index) + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 1.0, `__FILE__, `__LINE__); + check_idx_value(1, 2.0, `__FILE__, `__LINE__); + check_idx_value(2, 3.0, `__FILE__, `__LINE__); + + q_tst.delete(); + q_tst[0] = 2.0; + q_tst.insert(1, 4.0); + q_tst.insert(0, 1.0); + q_tst.insert(2, 3.0); + q_tst.insert(-1, 10.0); // Warning: will not be added (negative index) + q_tst.insert('X, 10.0); // Warning: will not be added (undefined index) + q_tst.insert(5, 10.0); // Warning: will not be added (out of range index) + + check_size(4, `__FILE__, `__LINE__); + check_idx_value(0, 1.0, `__FILE__, `__LINE__); + check_idx_value(1, 2.0, `__FILE__, `__LINE__); + check_idx_value(2, 3.0, `__FILE__, `__LINE__); + check_idx_value(3, 4.0, `__FILE__, `__LINE__); + + q_tst = '{3.0, 2.0, 1.0}; + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 3.0, `__FILE__, `__LINE__); + check_idx_value(1, 2.0, `__FILE__, `__LINE__); + check_idx_value(2, 1.0, `__FILE__, `__LINE__); + + q_tmp = '{1.0, 2.0}; + q_tst = q_tmp; + q_tmp[0] = 3.0; + q_tmp[2] = 1.0; + + check_size(2, `__FILE__, `__LINE__); + check_idx_value(0, 1.0, `__FILE__, `__LINE__); + check_idx_value(1, 2.0, `__FILE__, `__LINE__); + + q_tst[2] = 3.0; + check_size(3, `__FILE__, `__LINE__); + check_idx_value(2, 3.0, `__FILE__, `__LINE__); + + q_tst = {1.0, 2.0}; + check_size(2, `__FILE__, `__LINE__); + check_idx_value(0, 1.0, `__FILE__, `__LINE__); + check_idx_value(1, 2.0, `__FILE__, `__LINE__); + + q_tst = '{}; + + check_size(0, `__FILE__, `__LINE__); + + if (passed) $display("PASSED"); + + end +endmodule : top diff --git a/ivtest/ivltests/sv_queue_real_bounded.v b/ivtest/ivltests/sv_queue_real_bounded.v new file mode 100644 index 000000000..38ebfdf27 --- /dev/null +++ b/ivtest/ivltests/sv_queue_real_bounded.v @@ -0,0 +1,77 @@ +module top; + real q_tst [$:2]; + real q_tmp [$]; + bit passed; + + task automatic check_size(integer size, + string fname, + integer lineno); + if (q_tst.size !== size) begin + $display("%s:%0d: Failed: queue size != %0d (%0d)", + fname, lineno, size, q_tst.size); + passed = 1'b0; + end + endtask + + task automatic check_idx_value(integer idx, + real expected, + string fname, + integer lineno); + if (q_tst[idx] != expected) begin + $display("%s:%0d: Failed: element [%0d] != %.1f (%.1f)", + fname, lineno, idx, expected, q_tst[idx]); + passed = 1'b0; + end + endtask + + initial begin + passed = 1'b1; + + check_size(0, `__FILE__, `__LINE__); + + q_tst.push_back(2.0); + q_tst.push_front(1.0); + q_tst.push_back(3.0); + q_tst.push_back(100.0); // Warning: item not added. + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 1.0, `__FILE__, `__LINE__); + check_idx_value(1, 2.0, `__FILE__, `__LINE__); + check_idx_value(2, 3.0, `__FILE__, `__LINE__); + + q_tst.push_front(0.5); // Warning: back item removed. + q_tst[3] = 3.0; // Warning: item not added. + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 0.5, `__FILE__, `__LINE__); + check_idx_value(1, 1.0, `__FILE__, `__LINE__); + check_idx_value(2, 2.0, `__FILE__, `__LINE__); + + q_tst.insert(3, 10.0); // Warning: item not added. + q_tst.insert(1, 2.0); // Warning: back item removed. + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 0.5, `__FILE__, `__LINE__); + check_idx_value(1, 2.0, `__FILE__, `__LINE__); + check_idx_value(2, 1.0, `__FILE__, `__LINE__); + + q_tst = '{1.0, 2.0, 3.0, 4.0}; // Warning: items not added. + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 1.0, `__FILE__, `__LINE__); + check_idx_value(1, 2.0, `__FILE__, `__LINE__); + check_idx_value(2, 3.0, `__FILE__, `__LINE__); + + q_tmp = '{4.0, 3.0, 2.0, 1.0}; + q_tst = q_tmp; // Warning not all items copied + q_tmp[0] = 5.0; + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 4.0, `__FILE__, `__LINE__); + check_idx_value(1, 3.0, `__FILE__, `__LINE__); + check_idx_value(2, 2.0, `__FILE__, `__LINE__); + + if (passed) $display("PASSED"); + + end +endmodule : top diff --git a/ivtest/ivltests/sv_queue_real_fail.v b/ivtest/ivltests/sv_queue_real_fail.v new file mode 100644 index 000000000..f51f55fcb --- /dev/null +++ b/ivtest/ivltests/sv_queue_real_fail.v @@ -0,0 +1,16 @@ +module top; + int bound = 2; + real q_real [$]; + real q_real1 [$:-1]; + real q_real2 [$:'X]; + real q_real3 [$:bound]; + + initial begin + $display(q_real.size(1.0)); + $display(q_real.pop_front(1.0)); + $display(q_real.pop_back(1.0)); + q_real.push_front(1.0, 2.0); + q_real.push_back(1.0, 2.0); + $display("FAILED"); + end +endmodule : top diff --git a/ivtest/ivltests/sv_queue_string.v b/ivtest/ivltests/sv_queue_string.v new file mode 100644 index 000000000..84665633e --- /dev/null +++ b/ivtest/ivltests/sv_queue_string.v @@ -0,0 +1,192 @@ +module top; + string q_tst [$]; + string q_tmp [$]; + string elem; + integer idx; + bit passed; + + task automatic check_size(integer size, + string fname, + integer lineno); + if (q_tst.size !== size) begin + $display("%s:%0d: Failed: queue initial size != %0d (%0d)", + fname, lineno, size, q_tst.size); + passed = 1'b0; + end + endtask + + task automatic check_idx_value(integer idx, + string expected, + string fname, + integer lineno); + if (q_tst[idx] != expected) begin + $display("%s:%0d: Failed: element [%0d] != '%s' ('%s')", + fname, lineno, idx, expected, q_tst[idx]); + passed = 1'b0; + end + endtask + + initial begin + passed = 1'b1; + + q_tst.delete(0); // Warning: skip delete on an empty queue + check_size(0, `__FILE__, `__LINE__); + check_idx_value(0, "", `__FILE__, `__LINE__); + + elem = q_tst.pop_front(); // Warning: cannot pop_front() an empty queue + if (elem != "") begin + $display("Failed: pop_front() != '' ('%s')", elem); + passed = 1'b0; + end + + elem = q_tst.pop_back(); // Warning: cannot pop_back() an empty queue + if (elem != "") begin + $display("Failed: pop_back() != '' ('%s')", elem); + passed = 1'b0; + end + + q_tst.push_back("World"); + q_tst.push_front("Hello"); + q_tst.push_back("!"); + q_tst.push_back("This should get deleted"); + q_tst.delete(3); + q_tst.delete(3); // Warning: skip an out of range delete() + q_tst.delete(-1); // Warning: skip delete with negative index + q_tst.delete('X); // Warning: skip delete with undefined index + + check_size(3, `__FILE__, `__LINE__); + + if (q_tst[0] != "Hello") begin + $display("Failed: element [0] != 'Hello' ('%s')", q_tst[0]); + passed = 1'b0; + end + + if (q_tst[1] != "World") begin + $display("Failed: element [1] != 'World' ('%s')", q_tst[1]); + passed = 1'b0; + end + + if (q_tst[2] != "!") begin + $display("Failed: element [2] != '!' ('%s')", q_tst[2]); + passed = 1'b0; + end + + if (q_tst[3] != "") begin + $display("Failed: element [3] != '' ('%s')", q_tst[3]); + passed = 1'b0; + end + + if (q_tst[-1] != "") begin + $display("Failed: element [-1] != '' ('%s')", q_tst[-1]); + passed = 1'b0; + end + + if (q_tst['X] != "") begin + $display("Failed: element ['X] != '' ('%s')", q_tst['X]); + passed = 1'b0; + end + + check_idx_value(-1, "", `__FILE__, `__LINE__); + check_idx_value('X, "", `__FILE__, `__LINE__); + + elem = q_tst.pop_front(); + if (elem != "Hello") begin + $display("Failed: element pop_front() != 'Hello' ('%s')", elem); + passed = 1'b0; + end + + elem = q_tst.pop_back(); + if (elem != "!") begin + $display("Failed: element pop_back() != '!' ('%s')", elem); + passed = 1'b0; + end + + check_size(1, `__FILE__, `__LINE__); + + if ((q_tst[0] != q_tst[$]) || (q_tst[0] != "World")) begin + $display("Failed: q_tst[0]('%s') != q_tst[$]('%s') != 'World'", + q_tst[0], q_tst[$]); + passed = 1'b0; + end + + q_tst.delete(); + + check_size(0, `__FILE__, `__LINE__); + + q_tst.push_front("hello"); + q_tst.push_front("Will be removed"); + q_tst.push_back("Will also be removed"); + elem = q_tst.pop_back; + elem = q_tst.pop_front; + + check_size(1, `__FILE__, `__LINE__); + check_idx_value(0, "hello", `__FILE__, `__LINE__); + + q_tst[0] = "Hello"; + q_tst[1] = "world"; + q_tst[1] = "World"; + q_tst[2] = "!"; + q_tst[-1] = "Will not write"; // Warning: will not be added (negative index) + q_tst['X] = "Will not write"; // Warning: will not be added (undefined index) + q_tst[4] = "Will not write"; // Warning: will not be added (out of range index) + + idx = -1; + q_tst[idx] = "Will not write"; // Warning: will not be added (negative index) + idx = 3'b0x1; + q_tst[idx] = "Will not write"; // Warning: will not be added (undefined index) + idx = 4; + q_tst[idx] = "Will not write"; // Warning: will not be added (out of range index) + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, "Hello", `__FILE__, `__LINE__); + check_idx_value(1, "World", `__FILE__, `__LINE__); + check_idx_value(2, "!", `__FILE__, `__LINE__); + + q_tst.delete(); + q_tst[0] = "World"; + q_tst.insert(1, "Again"); + q_tst.insert(0, "Hello"); + q_tst.insert(2, "!"); + q_tst.insert(-1, "Will not be added"); // Warning: will not be added (negative index) + q_tst.insert('X, "Will not be added"); // Warning: will not be added (undefined index) + q_tst.insert(5, "Will not be added"); // Warning: will not be added (out of range index) + + check_size(4, `__FILE__, `__LINE__); + check_idx_value(0, "Hello", `__FILE__, `__LINE__); + check_idx_value(1, "World", `__FILE__, `__LINE__); + check_idx_value(2, "!", `__FILE__, `__LINE__); + check_idx_value(3, "Again", `__FILE__, `__LINE__); + + q_tst = '{"!", "World", "Hello"}; + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, "!", `__FILE__, `__LINE__); + check_idx_value(1, "World", `__FILE__, `__LINE__); + check_idx_value(2, "Hello", `__FILE__, `__LINE__); + + q_tmp = '{"Hello", "World"}; + q_tst = q_tmp; + q_tmp[0] = "Goodbye"; + q_tmp[2] = "Not seen"; + + check_size(2, `__FILE__, `__LINE__); + check_idx_value(0, "Hello", `__FILE__, `__LINE__); + check_idx_value(1, "World", `__FILE__, `__LINE__); + + q_tst[2] = "Added, but removed"; + check_size(3, `__FILE__, `__LINE__); + check_idx_value(2, "Added, but removed", `__FILE__, `__LINE__); + + q_tst = {"Hello", "World"}; + check_size(2, `__FILE__, `__LINE__); + check_idx_value(0, "Hello", `__FILE__, `__LINE__); + check_idx_value(1, "World", `__FILE__, `__LINE__); + + q_tst = '{}; + + check_size(0, `__FILE__, `__LINE__); + + if (passed) $display("PASSED"); + + end +endmodule : top diff --git a/ivtest/ivltests/sv_queue_string_bounded.v b/ivtest/ivltests/sv_queue_string_bounded.v new file mode 100644 index 000000000..a037dc3c5 --- /dev/null +++ b/ivtest/ivltests/sv_queue_string_bounded.v @@ -0,0 +1,78 @@ +module top; + string q_tst [$:2]; + string q_tmp [$]; + bit passed; + + task automatic check_size(integer size, + string fname, + integer lineno); + if (q_tst.size() !== size) begin + $display("%s:%0d: Failed: queue initial size != %0d (%0d)", + fname, lineno, size, q_tst.size); + passed = 1'b0; + end + endtask + + task automatic check_idx_value(integer idx, + string expected, + string fname, + integer lineno); + if (q_tst[idx] != expected) begin + $display("%s:%0d: Failed: element [%0d] != '%s' ('%s')", + fname, lineno, idx, expected, q_tst[idx]); + passed = 1'b0; + end + endtask + + initial begin + passed = 1'b1; + + check_size(0, `__FILE__, `__LINE__); + + q_tst.push_back("World"); + q_tst.push_front("Hello"); + q_tst.push_back("!"); + q_tst.push_back("This will not be added"); // Warning: item not added. + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, "Hello", `__FILE__, `__LINE__); + check_idx_value(1, "World", `__FILE__, `__LINE__); + check_idx_value(2, "!", `__FILE__, `__LINE__); + + q_tst.push_front("I say,"); // Warning: sback item removed. + q_tst[3] = "Will not be added"; // Warning: item not added. + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, "I say,", `__FILE__, `__LINE__); + check_idx_value(1, "Hello", `__FILE__, `__LINE__); + check_idx_value(2, "World", `__FILE__, `__LINE__); + + q_tst.insert(3, "Will not be added"); // Warning: item not added. + q_tst.insert(1, "to you"); // Warning: back item removed. + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, "I say,", `__FILE__, `__LINE__); + check_idx_value(1, "to you", `__FILE__, `__LINE__); + check_idx_value(2, "Hello", `__FILE__, `__LINE__); + + q_tst = '{"Hello", "World", "!", "Will not be added"}; // Warning: items not added. + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, "Hello", `__FILE__, `__LINE__); + check_idx_value(1, "World", `__FILE__, `__LINE__); + check_idx_value(2, "!", `__FILE__, `__LINE__); + + + q_tmp = '{"Again,", "Hello", "World", "!"}; + q_tst = q_tmp; // Warning not all items copied + q_tmp[0] = "Will not change anything"; + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, "Again,", `__FILE__, `__LINE__); + check_idx_value(1, "Hello", `__FILE__, `__LINE__); + check_idx_value(2, "World", `__FILE__, `__LINE__); + + if (passed) $display("PASSED"); + + end +endmodule : top diff --git a/ivtest/ivltests/sv_queue_string_fail.v b/ivtest/ivltests/sv_queue_string_fail.v new file mode 100644 index 000000000..8f5a7ec89 --- /dev/null +++ b/ivtest/ivltests/sv_queue_string_fail.v @@ -0,0 +1,16 @@ +module top; + int bound = 2; + string q_str [$]; + string q_str1 [$:-1]; + string q_str2 [$:'X]; + string q_str3 [$:bound]; + + initial begin + $display(q_str.size("a")); + $display(q_str.pop_front("a")); + $display(q_str.pop_back("a")); + q_str.push_front("a", "b"); + q_str.push_back("a", "b"); + $display("FAILED"); + end +endmodule : top diff --git a/ivtest/ivltests/sv_queue_vec.v b/ivtest/ivltests/sv_queue_vec.v new file mode 100644 index 000000000..e422ccfba --- /dev/null +++ b/ivtest/ivltests/sv_queue_vec.v @@ -0,0 +1,192 @@ +module top; + int q_tst [$]; + int q_tmp [$]; + int elem; + integer idx; + bit passed; + + task automatic check_size(integer size, + string fname, + integer lineno); + if (q_tst.size !== size) begin + $display("%s:%0d: Failed: queue size != %0d (%0d)", + fname, lineno, size, q_tst.size); + passed = 1'b0; + end + endtask + + task automatic check_idx_value(integer idx, + int expected, + string fname, + integer lineno); + if (q_tst[idx] != expected) begin + $display("%s:%0d: Failed: element [%0d] != %0d (%0d)", + fname, lineno, idx, expected, q_tst[idx]); + passed = 1'b0; + end + endtask + + initial begin + passed = 1'b1; + + q_tst.delete(0); // Warning: skip delete on an empty queue + check_size(0, `__FILE__, `__LINE__); + check_idx_value(0, 0, `__FILE__, `__LINE__); + + elem = q_tst.pop_front(); // Warning: cannot pop_front() an empty queue + if (elem !== 'X) begin + $display("Failed: pop_front() != 'X (%0d)", elem); + passed = 1'b0; + end + + elem = q_tst.pop_back(); // Warning: cannot pop_back() an empty queue + if (elem !== 'X) begin + $display("Failed: pop_back() != 'X (%0d)", elem); + passed = 1'b0; + end + + q_tst.push_back(2); + q_tst.push_front(1); + q_tst.push_back(3); + q_tst.push_back(100); + q_tst.delete(3); // Should $ work here? + q_tst.delete(3); // Warning: skip an out of range delete() + q_tst.delete(-1); // Warning: skip delete with negative index + q_tst.delete('X); // Warning: skip delete with undefined index + + check_size(3, `__FILE__, `__LINE__); + + if (q_tst[0] !== 1) begin + $display("Failed: element [0] != 1 (%0d)", q_tst[0]); + passed = 1'b0; + end + + if (q_tst[1] !== 2) begin + $display("Failed: element [1] != 2 (%0d)", q_tst[1]); + passed = 1'b0; + end + + if (q_tst[2] !== 3) begin + $display("Failed: element [2] != 3 (%0d)", q_tst[2]); + passed = 1'b0; + end + + if (q_tst[3] !== 'X) begin + $display("Failed: element [3] != 'X (%0d)", q_tst[3]); + passed = 1'b0; + end + + if (q_tst[-1] !== 'X) begin + $display("Failed: element [-1] != 'X (%0d)", q_tst[-1]); + passed = 1'b0; + end + + if (q_tst['X] !== 'X) begin + $display("Failed: element ['X] != 'X (%0d)", q_tst['X]); + passed = 1'b0; + end + + check_idx_value(-1, 0.0, `__FILE__, `__LINE__); + check_idx_value('X, 0.0, `__FILE__, `__LINE__); + + elem = q_tst.pop_front(); + if (elem !== 1) begin + $display("Failed: element pop_front() != 1 (%0d)", elem); + passed = 1'b0; + end + + elem = q_tst.pop_back(); + if (elem !== 3) begin + $display("Failed: element pop_back() != 3 (%0d)", elem); + passed = 1'b0; + end + + check_size(1, `__FILE__, `__LINE__); + + if ((q_tst[0] !== q_tst[$]) || (q_tst[0] !== 2)) begin + $display("Failed: q_tst[0](%0d) != q_tst[$](%0d) != 2", + q_tst[0], q_tst[$]); + passed = 1'b0; + end + + q_tst.delete(); + + check_size(0, `__FILE__, `__LINE__); + + q_tst.push_front(5); + q_tst.push_front(100); + q_tst.push_back(100); + elem = q_tst.pop_back; + elem = q_tst.pop_front; + + check_size(1, `__FILE__, `__LINE__); + check_idx_value(0, 5, `__FILE__, `__LINE__); + + q_tst[0] = 1; + q_tst[1] = 3; + q_tst[1] = 2; + q_tst[2] = 3; + q_tst[-1] = 10; // Warning: will not be added (negative index) + q_tst['X] = 10; // Warning: will not be added (undefined index) + q_tst[4] = 10; // Warning: will not be added (out of range index) + + idx = -1; + q_tst[idx] = 10; // Warning: will not be added (negative index) + idx = 3'b0x1; + q_tst[idx] = 10; // Warning: will not be added (undefined index) + idx = 4; + q_tst[idx] = 10; // Warning: will not be added (out of range index) + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 1, `__FILE__, `__LINE__); + check_idx_value(1, 2, `__FILE__, `__LINE__); + check_idx_value(2, 3, `__FILE__, `__LINE__); + + q_tst.delete(); + q_tst[0] = 2; + q_tst.insert(1, 4); + q_tst.insert(0, 1); + q_tst.insert(2, 3); + q_tst.insert(-1, 10); // Warning: will not be added (negative index) + q_tst.insert('X, 10); // Warning: will not be added (undefined index) + q_tst.insert(5, 10); // Warning: will not be added (out of range index) + + check_size(4, `__FILE__, `__LINE__); + check_idx_value(0, 1, `__FILE__, `__LINE__); + check_idx_value(1, 2, `__FILE__, `__LINE__); + check_idx_value(2, 3, `__FILE__, `__LINE__); + check_idx_value(3, 4, `__FILE__, `__LINE__); + + q_tst = '{3, 2, 1}; + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 3, `__FILE__, `__LINE__); + check_idx_value(1, 2, `__FILE__, `__LINE__); + check_idx_value(2, 1, `__FILE__, `__LINE__); + + q_tmp = '{1, 2}; + q_tst = q_tmp; + q_tmp[0] = 3; + q_tmp[2] = 1; + + check_size(2, `__FILE__, `__LINE__); + check_idx_value(0, 1.0, `__FILE__, `__LINE__); + check_idx_value(1, 2.0, `__FILE__, `__LINE__); + + q_tst[2] = 3; + check_size(3, `__FILE__, `__LINE__); + check_idx_value(2, 3, `__FILE__, `__LINE__); + + q_tst = {1, 2}; + check_size(2, `__FILE__, `__LINE__); + check_idx_value(0, 1, `__FILE__, `__LINE__); + check_idx_value(1, 2, `__FILE__, `__LINE__); + + q_tst = '{}; + + check_size(0, `__FILE__, `__LINE__); + + if (passed) $display("PASSED"); + + end +endmodule : top diff --git a/ivtest/ivltests/sv_queue_vec_bounded.v b/ivtest/ivltests/sv_queue_vec_bounded.v new file mode 100644 index 000000000..717e86017 --- /dev/null +++ b/ivtest/ivltests/sv_queue_vec_bounded.v @@ -0,0 +1,77 @@ +module top; + int q_tst [$:2]; + int q_tmp [$]; + bit passed; + + task automatic check_size(integer size, + string fname, + integer lineno); + if (q_tst.size !== size) begin + $display("%s:%0d: Failed: queue size != %0d (%0d)", + fname, lineno, size, q_tst.size); + passed = 1'b0; + end + endtask + + task automatic check_idx_value(integer idx, + int expected, + string fname, + integer lineno); + if (q_tst[idx] != expected) begin + $display("%s:%0d: Failed: element [%0d] != %0d (%0d)", + fname, lineno, idx, expected, q_tst[idx]); + passed = 1'b0; + end + endtask + + initial begin + passed = 1'b1; + + check_size(0, `__FILE__, `__LINE__); + + q_tst.push_back(2); + q_tst.push_front(1); + q_tst.push_back(3); + q_tst.push_back(100); // Warning: item not added. + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 1, `__FILE__, `__LINE__); + check_idx_value(1, 2, `__FILE__, `__LINE__); + check_idx_value(2, 3, `__FILE__, `__LINE__); + + q_tst.push_front(5); // Warning: back item removed. + q_tst[3] = 3; // Warning: item not added. + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 5, `__FILE__, `__LINE__); + check_idx_value(1, 1, `__FILE__, `__LINE__); + check_idx_value(2, 2, `__FILE__, `__LINE__); + + q_tst.insert(3, 10); // Warning: item not added. + q_tst.insert(1, 2); // Warning: back item removed. + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 5, `__FILE__, `__LINE__); + check_idx_value(1, 2, `__FILE__, `__LINE__); + check_idx_value(2, 1, `__FILE__, `__LINE__); + + q_tst = '{1, 2, 3, 4}; // Warning: items not added. + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 1, `__FILE__, `__LINE__); + check_idx_value(1, 2, `__FILE__, `__LINE__); + check_idx_value(2, 3, `__FILE__, `__LINE__); + + q_tmp = '{4, 3, 2, 1}; + q_tst = q_tmp; // Warning not all items copied + q_tmp[0] = 5; + + check_size(3, `__FILE__, `__LINE__); + check_idx_value(0, 4, `__FILE__, `__LINE__); + check_idx_value(1, 3, `__FILE__, `__LINE__); + check_idx_value(2, 2, `__FILE__, `__LINE__); + + if (passed) $display("PASSED"); + + end +endmodule : top diff --git a/ivtest/ivltests/sv_queue_vec_fail.v b/ivtest/ivltests/sv_queue_vec_fail.v new file mode 100644 index 000000000..475e23d06 --- /dev/null +++ b/ivtest/ivltests/sv_queue_vec_fail.v @@ -0,0 +1,16 @@ +module top; + int bound = 2; + int q_vec [$]; + int q_vec1 [$:-1]; + int q_vec2 [$:'X]; + int q_vec3 [$:bound]; + + initial begin + $display(q_vec.size(1)); + $display(q_vec.pop_front(1)); + $display(q_vec.pop_back(1)); + q_vec.push_front(1, 2); + q_vec.push_back(1, 2); + $display("FAILED"); + end +endmodule : top diff --git a/ivtest/ivltests/sv_root_class.v b/ivtest/ivltests/sv_root_class.v new file mode 100644 index 000000000..591fd069a --- /dev/null +++ b/ivtest/ivltests/sv_root_class.v @@ -0,0 +1,26 @@ +class a_class; + int id_; + + function new(int id); + id_ = id; + endfunction + + task display(); + $display("This is class %0d.", id_); + endtask + +endclass + +// This should print the following: +// This is class 2. +// This is class 1. +module top; + a_class ac1; + a_class ac2; + initial begin + ac1 = new(1); + ac2 = new(2); + ac2.display(); + ac1.display(); + end +endmodule diff --git a/ivtest/ivltests/sv_root_func.v b/ivtest/ivltests/sv_root_func.v new file mode 100644 index 000000000..9ad7756b1 --- /dev/null +++ b/ivtest/ivltests/sv_root_func.v @@ -0,0 +1,13 @@ +function int a_func (input int id); + a_func = id; +endfunction + +// This should print the following: +// This is func 2. +// This is func 1. +module top; + initial begin + $display("this is func %0d.", a_func(2)); + $display("this is func %0d.", a_func(1)); + end +endmodule diff --git a/ivtest/ivltests/sv_root_task.v b/ivtest/ivltests/sv_root_task.v new file mode 100644 index 000000000..72630a4ec --- /dev/null +++ b/ivtest/ivltests/sv_root_task.v @@ -0,0 +1,13 @@ +task a_task (input int id); + $display("This is task %0d.", id); +endtask + +// This should print the following: +// This is task 2. +// This is task 1. +module top; + initial begin + a_task(2); + a_task(1); + end +endmodule diff --git a/ivtest/ivltests/sv_string1.v b/ivtest/ivltests/sv_string1.v new file mode 100644 index 000000000..1c9eefe98 --- /dev/null +++ b/ivtest/ivltests/sv_string1.v @@ -0,0 +1,12 @@ +/* + * This is the most basic test of string variables. + */ +module main; + + string foo = "PASSED"; + + initial begin + $display(foo); + $finish; + end +endmodule // main diff --git a/ivtest/ivltests/sv_string2.v b/ivtest/ivltests/sv_string2.v new file mode 100644 index 000000000..97230aa98 --- /dev/null +++ b/ivtest/ivltests/sv_string2.v @@ -0,0 +1,87 @@ +/* + * This is the most basic test of string variables. + */ +module main; + + string foo; + string bar; + + initial begin + foo = "foo"; + bar = "bar"; + + if (foo != "foo") begin + $display("FAILED -- foo=%0s (1)", foo); + $finish; + end + + if (bar != "bar") begin + $display("FAILED -- bar=%0s (2)", bar); + $finish; + end + + if (foo == bar) begin + $display("FAILED -- %0s == %0s (3)", foo, bar); + $finish; + end + + if (! (foo != bar)) begin + $display("FAILED -- ! (%0s != %0s) (4)", foo, bar); + $finish; + end + + if (bar > foo) begin + $display("FAILED -- %s > %s (5)", bar, foo); + $finish; + end + + if (bar >= foo) begin + $display("FAILED -- %s >= %s (6)", bar, foo); + $finish; + end + + if (foo < bar) begin + $display("FAILED -- %s < %s (7)", foo, bar); + $finish; + end + + if (foo <= bar) begin + $display("FAILED -- %s <= %s (8)", foo, bar); + $finish; + end + + bar = foo; + if (foo != bar) begin + $display("FAILED -- %0s != %0s (9)", foo, bar); + $finish; + end + + if (foo > bar) begin + $display("FAILED -- %0s > %0s (10)", foo, bar); + $finish; + end + + if (foo < bar) begin + $display("FAILED -- %0s < %0s (11)", foo, bar); + $finish; + end + + if (! (foo == bar)) begin + $display("FAILED -- ! (%0s == %0s) (12)", foo, bar); + $finish; + end + + if (! (foo <= bar)) begin + $display("FAILED -- ! (%0s <= %0s) (13)", foo, bar); + $finish; + end + + if (! (foo >= bar)) begin + $display("FAILED -- ! (%0s >= %0s) (14)", foo, bar); + $finish; + end + + $display("PASSED"); + $finish; + end +endmodule // main diff --git a/ivtest/ivltests/sv_string3.v b/ivtest/ivltests/sv_string3.v new file mode 100644 index 000000000..38ddfa951 --- /dev/null +++ b/ivtest/ivltests/sv_string3.v @@ -0,0 +1,17 @@ +/* + * This demonstrates that strings can be used as + * constructed formats in $display et al. + */ +module main; + + string foo; + string bar; + + initial begin + foo = "%0s"; + bar = "PASSED"; + + $display(foo, bar); + $finish; + end +endmodule // main diff --git a/ivtest/ivltests/sv_string4.v b/ivtest/ivltests/sv_string4.v new file mode 100644 index 000000000..2fc3e041a --- /dev/null +++ b/ivtest/ivltests/sv_string4.v @@ -0,0 +1,24 @@ +/* + * This demonstrates that strings can be used as + * constructed formats in $display et al. + */ +module main; + + string foo; + string bar; + + initial begin + bar = "PAS"; + foo = {bar, "SED"}; + if (foo != "PASSED") begin + $display("FAILED (1)"); + $finish; + end + + foo = "PAS"; + bar = "SED"; + + $display({foo,bar}); + $finish; + end +endmodule // main diff --git a/ivtest/ivltests/sv_string5.v b/ivtest/ivltests/sv_string5.v new file mode 100644 index 000000000..082c8a548 --- /dev/null +++ b/ivtest/ivltests/sv_string5.v @@ -0,0 +1,46 @@ +/* + * This demonstrates that strings can be used as + * constructed formats in $display et al. + */ +module main; + + string foo; + + initial begin + foo = "PAXXED"; + $display("foo.len()=%0d (s.b. 6)", foo.len()); + if (foo.len() != 6) begin + $display("FAILED -- foo.len() = %0d", foo.len()); + $finish; + end + + $display("foo[-1]=%b (s.b. 00000000)", foo[-1]); + if (foo[-1] != 'h00) begin + $display("FAILED -- foo[-1]=%h", foo[-1]); + $finish; + end + + $display("foo[7]=%b (s.b. 00000000)", foo[7]); + if (foo[7] != 'h00) begin + $display("FAILED -- foo[7]=%h", foo[7]); + $finish; + end + + $display("foo[4]=%b (s.b. 01000101)", foo[4]); + if (foo[4] != 'h45) begin + $display("FAILED -- foo[4]=%h", foo[4]); + $finish; + end + + foo[2] = 'h00; + if (foo != "PAXXED") begin + $display("FAILED -- foo=%0s (1)", foo); + $finish; + end + + foo[2]='h53; + foo[3]='h53; + + $display(foo); + end +endmodule // main diff --git a/ivtest/ivltests/sv_timeunit_prec1.v b/ivtest/ivltests/sv_timeunit_prec1.v new file mode 100644 index 000000000..8202598fb --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec1.v @@ -0,0 +1,157 @@ +timeunit 10us; +timeprecision 10us; + +module fast_g (out); + output out; + reg out; + + initial begin + #0 out = 0; + #1 out = 1; // 10us + end + +endmodule // fast_g + +`timescale 100us / 1us + +// These will be ignored since a `timescale was already given. +timeunit 10us; +timeprecision 10us; + +module slow (out); + output out; + reg out; + + initial begin + #0 out = 0; + #1 out = 1; // 100us + end + +endmodule // slow + + +module fast (out); + timeunit 10us; + timeprecision 1us; + output out; + reg out; + + initial begin + #0 out = 0; + #1 out = 1; // 10us + end + +endmodule // fast + + +module saf(out); + output out; + reg out; + + initial begin + #0 out = 0; + #1 out = 1; // 100us + end + +endmodule // saf + +`timescale 1us / 1us +module main; + reg pass; + wire slow, fast, fast_g, saf; + + slow m1 (slow); + fast_g m2 (fast_g); + fast m3 (fast); + saf m4 (saf); + + initial begin + pass = 1'b1; + #9; + if (slow !== 1'b0) begin + $display("FAILED: slow at 9us, expected 1'b0, got %b.", slow); + pass = 1'b0; + end + + if (saf !== 1'b0) begin + $display("FAILED: saf at 9us, expected 1'b0, got %b.", saf); + pass = 1'b0; + end + + if (fast !== 1'b0) begin + $display("FAILED: fast at 9us, expected 1'b0, got %b.", fast); + pass = 1'b0; + end + + if (fast_g !== 1'b0) begin + $display("FAILED: fast_g at 9us, expected 1'b0, got %b.", fast_g); + pass = 1'b0; + end + + #2 // 11us + if (slow !== 1'b0) begin + $display("FAILED: slow at 11us, expected 1'b0, got %b.", slow); + pass = 1'b0; + end + + if (saf !== 1'b0) begin + $display("FAILED: saf at 11us, expected 1'b0, got %b.", saf); + pass = 1'b0; + end + + if (fast !== 1'b1) begin + $display("FAILED: fast at 11us, expected 1'b1, got %b.", fast); + pass = 1'b0; + end + + if (fast_g !== 1'b1) begin + $display("FAILED: fast_g at 11us, expected 1'b1, got %b.", fast_g); + pass = 1'b0; + end + + #88 // 99 us + if (slow !== 1'b0) begin + $display("FAILED: slow at 99us, expected 1'b0, got %b.", slow); + pass = 1'b0; + end + + if (saf !== 1'b0) begin + $display("FAILED: saf at 99us, expected 1'b0, got %b.", saf); + pass = 1'b0; + end + + if (fast !== 1'b1) begin + $display("FAILED: fast at 99us, expected 1'b1, got %b.", fast); + pass = 1'b0; + end + + if (fast_g !== 1'b1) begin + $display("FAILED: fast_g at 99us, expected 1'b1, got %b.", fast_g); + pass = 1'b0; + end + + #2 // 101 us + if (slow !== 1'b1) begin + $display("FAILED: slow at 101us, expected 1'b1, got %b.", slow); + pass = 1'b0; + end + + if (saf !== 1'b1) begin + $display("FAILED: saf at 101us, expected 1'b1, got %b.", saf); + pass = 1'b0; + end + + if (fast !== 1'b1) begin + $display("FAILED: fast at 101us, expected 1'b1, got %b.", fast); + pass = 1'b0; + end + + if (fast_g !== 1'b1) begin + $display("FAILED: fast_g at 101us, expected 1'b1, got %b.", fast_g); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/sv_timeunit_prec2.v b/ivtest/ivltests/sv_timeunit_prec2.v new file mode 100644 index 000000000..3da01c36e --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec2.v @@ -0,0 +1,154 @@ +timeunit 10us / 10us; + +module fast_g (out); + output out; + reg out; + + initial begin + #0 out = 0; + #1 out = 1; // 10us + end + +endmodule // fast_g + +`timescale 100us / 1us + +// These will be ignored since a `timescale was already given. +timeunit 10us/10us; + +module slow (out); + output out; + reg out; + + initial begin + #0 out = 0; + #1 out = 1; // 100us + end + +endmodule // slow + + +module fast (out); + timeunit 10us/1us; + output out; + reg out; + + initial begin + #0 out = 0; + #1 out = 1; // 10us + end + +endmodule // fast + + +module saf(out); + output out; + reg out; + + initial begin + #0 out = 0; + #1 out = 1; // 100us + end + +endmodule // saf + +`timescale 1us / 1us +module main; + reg pass; + wire slow, fast, fast_g, saf; + + slow m1 (slow); + fast_g m2 (fast_g); + fast m3 (fast); + saf m4 (saf); + + initial begin + pass = 1'b1; + #9; + if (slow !== 1'b0) begin + $display("FAILED: slow at 9us, expected 1'b0, got %b.", slow); + pass = 1'b0; + end + + if (saf !== 1'b0) begin + $display("FAILED: saf at 9us, expected 1'b0, got %b.", saf); + pass = 1'b0; + end + + if (fast !== 1'b0) begin + $display("FAILED: fast at 9us, expected 1'b0, got %b.", fast); + pass = 1'b0; + end + + if (fast_g !== 1'b0) begin + $display("FAILED: fast_g at 9us, expected 1'b0, got %b.", fast_g); + pass = 1'b0; + end + + #2 // 11us + if (slow !== 1'b0) begin + $display("FAILED: slow at 11us, expected 1'b0, got %b.", slow); + pass = 1'b0; + end + + if (saf !== 1'b0) begin + $display("FAILED: saf at 11us, expected 1'b0, got %b.", saf); + pass = 1'b0; + end + + if (fast !== 1'b1) begin + $display("FAILED: fast at 11us, expected 1'b1, got %b.", fast); + pass = 1'b0; + end + + if (fast_g !== 1'b1) begin + $display("FAILED: fast_g at 11us, expected 1'b1, got %b.", fast_g); + pass = 1'b0; + end + + #88 // 99 us + if (slow !== 1'b0) begin + $display("FAILED: slow at 99us, expected 1'b0, got %b.", slow); + pass = 1'b0; + end + + if (saf !== 1'b0) begin + $display("FAILED: saf at 99us, expected 1'b0, got %b.", saf); + pass = 1'b0; + end + + if (fast !== 1'b1) begin + $display("FAILED: fast at 99us, expected 1'b1, got %b.", fast); + pass = 1'b0; + end + + if (fast_g !== 1'b1) begin + $display("FAILED: fast_g at 99us, expected 1'b1, got %b.", fast_g); + pass = 1'b0; + end + + #2 // 101 us + if (slow !== 1'b1) begin + $display("FAILED: slow at 101us, expected 1'b1, got %b.", slow); + pass = 1'b0; + end + + if (saf !== 1'b1) begin + $display("FAILED: saf at 101us, expected 1'b1, got %b.", saf); + pass = 1'b0; + end + + if (fast !== 1'b1) begin + $display("FAILED: fast at 101us, expected 1'b1, got %b.", fast); + pass = 1'b0; + end + + if (fast_g !== 1'b1) begin + $display("FAILED: fast_g at 101us, expected 1'b1, got %b.", fast_g); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/sv_timeunit_prec3a.v b/ivtest/ivltests/sv_timeunit_prec3a.v new file mode 100644 index 000000000..6f096d2ff --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec3a.v @@ -0,0 +1,178 @@ +/* + * Check the basic parsing. + */ + +// A global timeunit and timeprecision are OK +timeunit 100us; +timeprecision 1us; + +/* + * Check the various timeunit/precision combinations (this is valid SV syntax). + */ +// A local time unit is OK. +module check_tu; + timeunit 10us; +endmodule + +// A local time precision is OK. +module check_tp; + timeprecision 10us; +endmodule + +// Both a local time unit and precision are OK. +module check_tup; + timeunit 10us; + timeprecision 10us; +endmodule + +// Both a local time unit and precision are OK (check both orders). +module check_tpu; + timeprecision 10us; + timeunit 10us; +endmodule + +/* + * Now do the same with repeat declarations (this is valid SV syntax). + */ +// A global timeunit and timeprecision are OK +timeunit 100us; +timeprecision 1us; + +// A local time unit is OK. +module check_tu_d; + timeunit 10us; + timeunit 10us; +endmodule + +// A local time precision is OK. +module check_tp_d; + timeprecision 10us; + timeprecision 10us; +endmodule + +// Both a local time unit and precision are OK. +module check_tup_d; + timeunit 10us; + timeprecision 10us; + timeunit 10us; + timeprecision 10us; +endmodule + +// Both a local time unit and precision are OK (check both orders). +module check_tpu_d; + timeprecision 10us; + timeunit 10us; + timeprecision 10us; + timeunit 10us; +endmodule + +/* + * Now check all the valid timeunit and time precision values. + */ +module check_100s; + timeunit 100s; + timeprecision 100s; +endmodule +module check_10s; + timeunit 10s; + timeprecision 10s; +endmodule +module check_1s; + timeunit 1s; + timeprecision 1s; +endmodule +module check_100ms; + timeunit 100ms; + timeprecision 100ms; +endmodule +module check_10ms; + timeunit 10ms; + timeprecision 10ms; +endmodule +module check_1ms; + timeunit 1ms; + timeprecision 1ms; +endmodule +module check_100us; + timeunit 100us; + timeprecision 100us; +endmodule +module check_10us; + timeunit 10us; + timeprecision 10us; +endmodule +module check_1us; + timeunit 1us; + timeprecision 1us; +endmodule +module check_100ns; + timeunit 100ns; + timeprecision 100ns; +endmodule +module check_10ns; + timeunit 10ns; + timeprecision 10ns; +endmodule +module check_1ns; + timeunit 1ns; + timeprecision 1ns; +endmodule +module check_100ps; + timeunit 100ps; + timeprecision 100ps; +endmodule +module check_10ps; + timeunit 10ps; + timeprecision 10ps; +endmodule +module check_1ps; + timeunit 1ps; + timeprecision 1ps; +endmodule +module check_100fs; + timeunit 100fs; + timeprecision 100fs; +endmodule +module check_10fs; + timeunit 10fs; + timeprecision 10fs; +endmodule +module check_1fs; + timeunit 1fs; + timeprecision 1fs; +endmodule + +module check1; + +initial begin + $printtimescale(check_100s); + $printtimescale(check_10s); + $printtimescale(check_1s); + $printtimescale(check_100ms); + $printtimescale(check_10ms); + $printtimescale(check_1ms); + $printtimescale(check_100us); + $printtimescale(check_10us); + $printtimescale(check_1us); + $printtimescale(check_100ns); + $printtimescale(check_10ns); + $printtimescale(check_1ns); + $printtimescale(check_100ps); + $printtimescale(check_10ps); + $printtimescale(check_1ps); + $printtimescale(check_100fs); + $printtimescale(check_10fs); + $printtimescale(check_1fs); + $display(""); + $printtimescale(check_tu); + $printtimescale(check_tp); + $printtimescale(check_tup); + $printtimescale(check_tpu); + $display(""); + $printtimescale(check_tu_d); + $printtimescale(check_tp_d); + $printtimescale(check_tup_d); + $printtimescale(check_tpu_d); +end + +endmodule diff --git a/ivtest/ivltests/sv_timeunit_prec3b.v b/ivtest/ivltests/sv_timeunit_prec3b.v new file mode 100644 index 000000000..a607d3bed --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec3b.v @@ -0,0 +1,69 @@ +/* + * Check declarations and repeat declarations in nested modules. + */ +timeunit 100us; +timeprecision 1us; + +// A local time unit is OK. +module check_tu_nest; + timeunit 10us; + module nested; + timeunit 100us; + timeunit 100us; + endmodule + timeunit 10us; +endmodule + +// A local time precision is OK. +module check_tp_nest; + timeprecision 10us; + module nested; + timeprecision 1us; + timeprecision 1us; + endmodule + timeprecision 10us; +endmodule + +// Both a local time unit and precision are OK. +module check_tup_nest; + timeunit 10us; + timeprecision 10us; + module nested; + timeunit 100us; + timeprecision 1us; + timeunit 100us; + timeprecision 1us; + endmodule + timeunit 10us; + timeprecision 10us; +endmodule + +// Both a local time unit and precision are OK (check both orders). +module check_tpu_nest; + timeprecision 10us; + timeunit 10us; + module nested; + timeprecision 1us; + timeunit 100us; + timeprecision 1us; + timeunit 100us; + endmodule + timeprecision 10us; + timeunit 10us; +endmodule + +module check2; + +initial begin + $printtimescale(check_tu_nest); + $printtimescale(check_tp_nest); + $printtimescale(check_tup_nest); + $printtimescale(check_tpu_nest); + $display(""); + $printtimescale(check_tu_nest.nested); + $printtimescale(check_tp_nest.nested); + $printtimescale(check_tup_nest.nested); + $printtimescale(check_tpu_nest.nested); +end + +endmodule diff --git a/ivtest/ivltests/sv_timeunit_prec3c.v b/ivtest/ivltests/sv_timeunit_prec3c.v new file mode 100644 index 000000000..f8aaa011b --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec3c.v @@ -0,0 +1,21 @@ +// A global timeprecision and local time units. + +timeprecision 10ps; + +module gtp_ltu1; + timeunit 1ns; +endmodule + +module gtp_ltu2; + timeunit 1us; +endmodule + +`timescale 1s/1s +module check3; + +initial begin + $printtimescale(gtp_ltu1); + $printtimescale(gtp_ltu2); +end + +endmodule diff --git a/ivtest/ivltests/sv_timeunit_prec3d.v b/ivtest/ivltests/sv_timeunit_prec3d.v new file mode 100644 index 000000000..4f4db1a23 --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec3d.v @@ -0,0 +1,21 @@ +// A global timeunit and local time precision. + +timeunit 10s; + +module gtu_ltp1; + timeprecision 10ps; +endmodule + +module gtu_ltp2; + timeprecision 1ns; +endmodule + +`timescale 1s/1s +module check4; + +initial begin + $printtimescale(gtu_ltp1); + $printtimescale(gtu_ltp2); +end + +endmodule diff --git a/ivtest/ivltests/sv_timeunit_prec4a.v b/ivtest/ivltests/sv_timeunit_prec4a.v new file mode 100644 index 000000000..a26f1ced2 --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec4a.v @@ -0,0 +1,114 @@ +/* + * Check the basic parsing. + */ + +/* + * Check the various timeunit/precision combinations (this is valid SV syntax). + */ +// A global timeunit and timeprecision are OK +timeunit 100us/1us; + +// Both a local time unit and precision are OK. +module check_tup; + timeunit 10us/10us; +endmodule + +/* + * Now do the same with repeat declarations (this is valid SV syntax). + */ +// A global timeunit and timeprecision are OK +timeunit 100us/1us; + +// Both a local time unit and precision are OK. +module check_tup_d; + timeunit 10us/10us; + timeunit 10us/10us; + timeunit 10us; + timeprecision 10us; +endmodule + +/* + * Now check all the valid timeunit and time precision values. + */ +module check_100s; + timeunit 100s / 100s; +endmodule +module check_10s; + timeunit 10s / 10s; +endmodule +module check_1s; + timeunit 1s / 1s; +endmodule +module check_100ms; + timeunit 100ms / 100ms; +endmodule +module check_10ms; + timeunit 10ms / 10ms; +endmodule +module check_1ms; + timeunit 1ms / 1ms; +endmodule +module check_100us; + timeunit 100us / 100us; +endmodule +module check_10us; + timeunit 10us / 10us; +endmodule +module check_1us; + timeunit 1us / 1us; +endmodule +module check_100ns; + timeunit 100ns / 100ns; +endmodule +module check_10ns; + timeunit 10ns / 10ns; +endmodule +module check_1ns; + timeunit 1ns / 1ns; +endmodule +module check_100ps; + timeunit 100ps / 100ps; +endmodule +module check_10ps; + timeunit 10ps / 10ps; +endmodule +module check_1ps; + timeunit 1ps / 1ps; +endmodule +module check_100fs; + timeunit 100fs / 100fs; +endmodule +module check_10fs; + timeunit 10fs / 10fs; +endmodule +module check_1fs; + timeunit 1fs / 1fs; +endmodule + +module check1; + +initial begin + $printtimescale(check_100s); + $printtimescale(check_10s); + $printtimescale(check_1s); + $printtimescale(check_100ms); + $printtimescale(check_10ms); + $printtimescale(check_1ms); + $printtimescale(check_100us); + $printtimescale(check_10us); + $printtimescale(check_1us); + $printtimescale(check_100ns); + $printtimescale(check_10ns); + $printtimescale(check_1ns); + $printtimescale(check_100ps); + $printtimescale(check_10ps); + $printtimescale(check_1ps); + $printtimescale(check_100fs); + $printtimescale(check_10fs); + $printtimescale(check_1fs); + $display(""); + $printtimescale(check_tup); + $printtimescale(check_tup_d); +end + +endmodule diff --git a/ivtest/ivltests/sv_timeunit_prec4b.v b/ivtest/ivltests/sv_timeunit_prec4b.v new file mode 100644 index 000000000..829c30037 --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec4b.v @@ -0,0 +1,23 @@ +/* + * Check declarations and repeat declarations in nested modules. + */ +timeunit 100us/1us; + +// Both a local time unit and precision are OK. +module check_tup_nest; + timeunit 10us / 10us; + module nested; + timeunit 100us / 1us; + timeunit 100us / 1us; + endmodule + timeunit 10us / 10us; +endmodule + +module check2(); + +initial begin + $printtimescale(check_tup_nest); + $printtimescale(check_tup_nest.nested); +end + +endmodule diff --git a/ivtest/ivltests/sv_timeunit_prec_fail1.v b/ivtest/ivltests/sv_timeunit_prec_fail1.v new file mode 100644 index 000000000..5ca0b909b --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec_fail1.v @@ -0,0 +1 @@ +// deliberately empty diff --git a/ivtest/ivltests/sv_timeunit_prec_fail1a.v b/ivtest/ivltests/sv_timeunit_prec_fail1a.v new file mode 100644 index 000000000..f41812c96 --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec_fail1a.v @@ -0,0 +1,64 @@ +/* + * Check that errors are caught. + */ + +timeunit 100us; +timeprecision 1us; + +// Repeated declarations must match the initial declarations. +timeunit 1ms; +timeprecision 1ns; + +// A local time unit is OK, but a repeat must match. +module check_tu_d_e; + timeunit 10us; + timeunit 1us; +endmodule + +// A local time precision is OK, but a repeat must match. +module check_tp_d_e; + timeprecision 10us; + timeprecision 1us; +endmodule + +// A repeat time unit is only allowed if an initial one is given. +module check_tu_m_e; + integer foo; + timeunit 10us; +endmodule + +// A repeat time precision is only allowed if an initial one is given. +module check_tp_m_e; + integer foo; + timeprecision 10us; +endmodule + +// A local time unit is OK and a repeat is OK, but this is not a prec decl. +module check_tup_d_e; + timeunit 10us; + timeunit 10us; + timeprecision 1us; +endmodule + +// A local time prec is OK and a repeat is OK, but this is not a unit decl. +module check_tpu_d_e; + timeprecision 1us; + timeprecision 1us; + timeunit 10us; +endmodule + +/* Check some invalid values */ + +// Only a power of 10 is allowed. +timeunit 200s; +timeprecision 200s; +// Too many zeros (only allow 0 - 2). +timeunit 1000s; +timeprecision 1000s; +// This actually trips as an invalid scale of '2s'. +timeunit 12s; +timeprecision 12s; +// This needs to be checked. The base time_literal supports this, but +// for now timeunit/precision code does not. +timeunit 1_0s; +timeprecision 1_0s; diff --git a/ivtest/ivltests/sv_timeunit_prec_fail1b.v b/ivtest/ivltests/sv_timeunit_prec_fail1b.v new file mode 100644 index 000000000..886e77a63 --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec_fail1b.v @@ -0,0 +1,5 @@ +// Check a missing global time precision. +`resetall +timeunit 1ns; +module no_gtp; +endmodule diff --git a/ivtest/ivltests/sv_timeunit_prec_fail1c.v b/ivtest/ivltests/sv_timeunit_prec_fail1c.v new file mode 100644 index 000000000..073cf9195 --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec_fail1c.v @@ -0,0 +1,6 @@ +// Check a global timeprecision that is too large. +`resetall +timeunit 1ns; +timeprecision 10ns; +module gtp_large; +endmodule diff --git a/ivtest/ivltests/sv_timeunit_prec_fail1d.v b/ivtest/ivltests/sv_timeunit_prec_fail1d.v new file mode 100644 index 000000000..149fafb3b --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec_fail1d.v @@ -0,0 +1,6 @@ +// Check a missing local time precision. +`resetall +module no_ltp; + timeunit 1ns; +endmodule + diff --git a/ivtest/ivltests/sv_timeunit_prec_fail1e.v b/ivtest/ivltests/sv_timeunit_prec_fail1e.v new file mode 100644 index 000000000..b99128cdf --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec_fail1e.v @@ -0,0 +1,7 @@ +// Check a local timeprecision that is too large. +`resetall +module ltp_large; + timeunit 1ns; + timeprecision 10ns; +endmodule + diff --git a/ivtest/ivltests/sv_timeunit_prec_fail2.v b/ivtest/ivltests/sv_timeunit_prec_fail2.v new file mode 100644 index 000000000..5ca0b909b --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec_fail2.v @@ -0,0 +1 @@ +// deliberately empty diff --git a/ivtest/ivltests/sv_timeunit_prec_fail2a.v b/ivtest/ivltests/sv_timeunit_prec_fail2a.v new file mode 100644 index 000000000..02e3562a7 --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec_fail2a.v @@ -0,0 +1,46 @@ +/* + * Check that errors are caught. + */ + +timeunit 100us/1us; + +// Repeated declarations must match the initial declarations. +timeunit 1ms/1ns; + +// A local time unit/precision is OK, but a repeat must match. +module check_tup_d_e; + timeunit 10us/10us; + timeunit 1us/1us; + timeunit 1us; + timeprecision 1us; +endmodule + +// A repeat time unit/precision is only allowed if an initial one is given. +module check_tup_m_e; + integer foo; + timeunit 10us/10us; +endmodule + +// A local time unit is OK and a repeat is OK, but this is not a prec decl. +module check_tu_d_e; + timeunit 10us; + timeunit 10us/1us; +endmodule + +// A local time prec is OK and a repeat is OK, but this is not a unit decl. +module check_tp_d_e; + timeprecision 1us; + timeunit 10us/1us; +endmodule + +/* Check some invalid values */ + +// Only a power of 10 is allowed. +timeunit 200s/200s; +// Too many zeros (only allow 0 - 2). +timeunit 1000s/1000s; +// This actually trips as an invalid scale of '2s'. +timeunit 12s/12s; +// This needs to be checked. The base time_literal supports this, but +// for now timeunit/precision code does not. +timeunit 1_0s/1_0s; diff --git a/ivtest/ivltests/sv_timeunit_prec_fail2b.v b/ivtest/ivltests/sv_timeunit_prec_fail2b.v new file mode 100644 index 000000000..1bea020d2 --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec_fail2b.v @@ -0,0 +1,6 @@ +// Check a global timeprecision that is too large. +`resetall +timeunit 1ns/10ns; +module gtp_large; +endmodule + diff --git a/ivtest/ivltests/sv_timeunit_prec_fail2c.v b/ivtest/ivltests/sv_timeunit_prec_fail2c.v new file mode 100644 index 000000000..c1b9da8fb --- /dev/null +++ b/ivtest/ivltests/sv_timeunit_prec_fail2c.v @@ -0,0 +1,5 @@ +// Check a local timeprecision that is too large. +`resetall +module ltp_large; + timeunit 1ns/10ns; +endmodule diff --git a/ivtest/ivltests/sv_typedef_scope.v b/ivtest/ivltests/sv_typedef_scope.v new file mode 100644 index 000000000..5bcdb7d54 --- /dev/null +++ b/ivtest/ivltests/sv_typedef_scope.v @@ -0,0 +1,42 @@ + +typedef struct packed { + logic [1:0] hig; + logic [1:0] low; +} foo_t; + +module main; + // This typedef should work, and should shadow the foo_t definition + // in the $root scope. + typedef struct packed { + logic [2:0] hig_x; + logic [2:0] low_x; + } foo_t; + + foo_t foo; + + initial begin + foo = 6'b111000; + + if ($bits(foo_t) != 6) begin + $display("FAILED -- Got wrong foo_t definition?"); + $finish; + end + + if ($bits(foo) != 6) begin + $display("FAILED -- $bits(foo)==%0d", $bits(foo)); + $finish; + end + + if (foo.hig_x !== 3'b111) begin + $display("FAILED -- foo=%b, foo.hig_x=%b", foo, foo.hig_x); + $finish; + end + + if (foo.low_x !== 3'b000) begin + $display("FAILED -- foo=%b, foo.low_x=%b", foo, foo.low_x); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/sv_union1.v b/ivtest/ivltests/sv_union1.v new file mode 100644 index 000000000..3ee231833 --- /dev/null +++ b/ivtest/ivltests/sv_union1.v @@ -0,0 +1,38 @@ + +module main; + + typedef union packed { + logic [3:0] bits; + struct packed { logic [1:0] hig; logic [1:0] low; } words; + } bits_t; + + bits_t foo; + + initial begin + foo.bits = 'b1001; + if (foo.bits !== 'b1001) begin + $display("FAILED -- foo.bits=%b", foo.bits); + $finish; + end + + if (foo.words !== 'b1001) begin + $display("FAILED -- foo.words=%b", foo.words); + $finish; + end + + //foo.words.low = 'b00; + //foo.words.hig = 'b11; + foo.words = 'b1100; + if (foo.words !== 'b1100) begin + $display("FAILED -- foo.words=%b", foo.words); + $finish; + end + if (foo.bits !== 'b1100) begin + $display("FAILED -- foo.bits=%b", foo.bits); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sv_union1b.v b/ivtest/ivltests/sv_union1b.v new file mode 100644 index 000000000..f4585e443 --- /dev/null +++ b/ivtest/ivltests/sv_union1b.v @@ -0,0 +1,38 @@ + +typedef union packed { + logic [3:0] bits; + struct packed { logic [1:0] hig; logic [1:0] low; } words; +} bits_t; + +module main; + + bits_t foo; + + initial begin + foo.bits = 'b1001; + if (foo.bits !== 'b1001) begin + $display("FAILED -- foo.bits=%b", foo.bits); + $finish; + end + + if (foo.words !== 'b1001) begin + $display("FAILED -- foo.words=%b", foo.words); + $finish; + end + + //foo.words.low = 'b00; + //foo.words.hig = 'b11; + foo.words = 'b1100; + if (foo.words !== 'b1100) begin + $display("FAILED -- foo.words=%b", foo.words); + $finish; + end + if (foo.bits !== 'b1100) begin + $display("FAILED -- foo.bits=%b", foo.bits); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sv_union2.v b/ivtest/ivltests/sv_union2.v new file mode 100644 index 000000000..7e1b06245 --- /dev/null +++ b/ivtest/ivltests/sv_union2.v @@ -0,0 +1,42 @@ + +module main; + typedef struct packed { + logic [1:0] hig; + logic [1:0] low; + } word_as_nibbles; + + typedef union packed { + logic [3:0] bits; + word_as_nibbles words; + } bits_t; + + bits_t foo; + + initial begin + foo.bits = 'b1001; + if (foo.bits != 'b1001) begin + $display("FAILED -- foo.bits=%b", foo.bits); + $finish; + end + + if (foo.words != 'b1001) begin + $display("FAILED -- foo.words=%b", foo.words); + $finish; + end + + //foo.words.low = 'b00; + //foo.words.hig = 'b11; + foo.words = 'b1100; + if (foo.words != 'b1100) begin + $display("FAILED -- foo.words=%b", foo.words); + $finish; + end + if (foo.bits != 'b1100) begin + $display("FAILED -- foo.bits=%b", foo.bits); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sv_union2b.v b/ivtest/ivltests/sv_union2b.v new file mode 100644 index 000000000..6f86417ee --- /dev/null +++ b/ivtest/ivltests/sv_union2b.v @@ -0,0 +1,43 @@ + +typedef struct packed { + logic [1:0] hig; + logic [1:0] low; +} word_as_nibbles; + +typedef union packed { + logic [3:0] bits; + word_as_nibbles words; +} bits_t; + +module main; + + bits_t foo; + + initial begin + foo.bits = 'b1001; + if (foo.bits != 'b1001) begin + $display("FAILED -- foo.bits=%b", foo.bits); + $finish; + end + + if (foo.words != 'b1001) begin + $display("FAILED -- foo.words=%b", foo.words); + $finish; + end + + //foo.words.low = 'b00; + //foo.words.hig = 'b11; + foo.words = 'b1100; + if (foo.words != 'b1100) begin + $display("FAILED -- foo.words=%b", foo.words); + $finish; + end + if (foo.bits != 'b1100) begin + $display("FAILED -- foo.bits=%b", foo.bits); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sv_union3.v b/ivtest/ivltests/sv_union3.v new file mode 100644 index 000000000..34e7a8d4d --- /dev/null +++ b/ivtest/ivltests/sv_union3.v @@ -0,0 +1,38 @@ + +module main; + + typedef enum logic [3:0] { WORD0, WORD1, WORD9='b1001, WORDC='b1100 } word_t; + + typedef union packed { + logic [3:0] bits; + word_t words; + } bits_t; + + bits_t foo; + + initial begin + foo.bits = 'b1001; + if (foo.bits !== 'b1001) begin + $display("FAILED -- foo.bits=%b", foo.bits); + $finish; + end + + if (foo.words !== WORD9) begin + $display("FAILED -- foo.words=%b", foo.words); + $finish; + end + + foo.words = WORDC; + if (foo.words !== WORDC) begin + $display("FAILED -- foo.words=%b", foo.words); + $finish; + end + if (foo.bits !== 'b1100) begin + $display("FAILED -- foo.bits=%b", foo.bits); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sv_union3b.v b/ivtest/ivltests/sv_union3b.v new file mode 100644 index 000000000..20c1cb381 --- /dev/null +++ b/ivtest/ivltests/sv_union3b.v @@ -0,0 +1,39 @@ + + +typedef enum logic [3:0] { WORD0, WORD1, WORD9='b1001, WORDC='b1100 } word_t; + +typedef union packed { + logic [3:0] bits; + word_t words; +} bits_t; + +module main; + + bits_t foo; + + initial begin + foo.bits = 'b1001; + if (foo.bits !== 'b1001) begin + $display("FAILED -- foo.bits=%b", foo.bits); + $finish; + end + + if (foo.words !== WORD9) begin + $display("FAILED -- foo.words=%b", foo.words); + $finish; + end + + foo.words = WORDC; + if (foo.words !== WORDC) begin + $display("FAILED -- foo.words=%b", foo.words); + $finish; + end + if (foo.bits !== 'b1100) begin + $display("FAILED -- foo.bits=%b", foo.bits); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sv_union4b.v b/ivtest/ivltests/sv_union4b.v new file mode 100644 index 000000000..f73fc0d67 --- /dev/null +++ b/ivtest/ivltests/sv_union4b.v @@ -0,0 +1,26 @@ + +typedef union packed { + logic [3:0] bits; + struct packed { logic [1:0] hig; logic [1:0] low; } words; +} bits_t; + +module main; + + bits_t foo; + + initial begin + + if ($bits(foo) !== 4) begin + $display("FAILED -- $bits(foo)=%0d", $bits(foo)); + $finish; + end + + if ($bits(bits_t) !== 4) begin + $display("FAILED -- $bits(bits_t)=%0d", $bits(bits_t)); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sv_unit1a.v b/ivtest/ivltests/sv_unit1a.v new file mode 100644 index 000000000..eac925260 --- /dev/null +++ b/ivtest/ivltests/sv_unit1a.v @@ -0,0 +1,19 @@ +`define MACRO2 12 +`define MACRO3 13 + +`default_nettype tri1 + +module test1(); + +buf(a,b); + +initial #1 begin + $display("test1 macro1 = %0d", `MACRO1 ); + $display("test1 macro2 = %0d", `MACRO2 ); + $display("test1 macro3 = %0d", `MACRO3 ); + $display("test1 wire = %b", a); +end + +endmodule + +`undef MACRO1 diff --git a/ivtest/ivltests/sv_unit1b.v b/ivtest/ivltests/sv_unit1b.v new file mode 100644 index 000000000..fdb9a3f21 --- /dev/null +++ b/ivtest/ivltests/sv_unit1b.v @@ -0,0 +1,22 @@ +`ifndef MACRO1 +`define MACRO1 21 +`endif +`ifndef MACRO2 +`define MACRO2 22 +`endif +`ifndef MACRO3 +`define MACRO3 23 +`endif + +module test2(input w); + +buf(a,b); + +initial #2 begin + $display("test2 macro1 = %0d", `MACRO1 ); + $display("test2 macro2 = %0d", `MACRO2 ); + $display("test2 macro3 = %0d", `MACRO3 ); + $display("test2 wire = %b", a); +end + +endmodule diff --git a/ivtest/ivltests/sv_unit1c.v b/ivtest/ivltests/sv_unit1c.v new file mode 100644 index 000000000..fdb9a3f21 --- /dev/null +++ b/ivtest/ivltests/sv_unit1c.v @@ -0,0 +1,22 @@ +`ifndef MACRO1 +`define MACRO1 21 +`endif +`ifndef MACRO2 +`define MACRO2 22 +`endif +`ifndef MACRO3 +`define MACRO3 23 +`endif + +module test2(input w); + +buf(a,b); + +initial #2 begin + $display("test2 macro1 = %0d", `MACRO1 ); + $display("test2 macro2 = %0d", `MACRO2 ); + $display("test2 macro3 = %0d", `MACRO3 ); + $display("test2 wire = %b", a); +end + +endmodule diff --git a/ivtest/ivltests/sv_unit2a.v b/ivtest/ivltests/sv_unit2a.v new file mode 100644 index 000000000..18965c42b --- /dev/null +++ b/ivtest/ivltests/sv_unit2a.v @@ -0,0 +1,96 @@ +function int hello(int a); + begin + $display("hello from unit 1"); + hello = a; + end +endfunction + + +task hello1; + begin + $display("hello1 from unit 1"); + end +endtask + + +task hello2; + begin + $display("hello2 from unit 1"); + end +endtask + + +task hello3; + begin + $display("hello3 from unit 1"); + end +endtask + + +class c1; + + task hello2; + begin + hello1; + $display("hello2 from c1"); + end + endtask + +endclass + + +module m1(); + + int i; + + c1 obj; + + initial begin + #1; + i = $unit::hello(1); + obj = new; + obj.hello2; + hello1; + hello2; + hello3; + hello4; + end + + task hello2; + begin + $display("hello2 from m1"); + end + endtask + +endmodule + + +module m2(); + + m1 m1inst(); + + task hello1; + begin + $display("hello1 from m2"); + end + endtask + + task hello2; + begin + $display("hello2 from m2"); + end + endtask + + task hello3; + begin + $display("hello3 from m2"); + end + endtask + + task hello4; + begin + $display("hello4 from m2"); + end + endtask + +endmodule diff --git a/ivtest/ivltests/sv_unit2b.v b/ivtest/ivltests/sv_unit2b.v new file mode 100644 index 000000000..d2379c084 --- /dev/null +++ b/ivtest/ivltests/sv_unit2b.v @@ -0,0 +1,70 @@ +task hello1; + begin + $display("hello1 from unit 2"); + end +endtask + + +task hello2; + begin + $display("hello2 from unit 2"); + end +endtask + + +task hello3; + begin + $display("hello3 from unit 2"); + end +endtask + + +module m3(); + + initial begin + #2; // allow m1 to go first + m2.m1inst.obj.hello2; + hello1; + hello2; + hello3; + hello4; + end + + task hello2; + begin + $display("hello2 from m3"); + end + endtask + +endmodule + + +module m4(); + + m3 m3inst(); + + task hello1; + begin + $display("hello1 from m4"); + end + endtask + + task hello2; + begin + $display("hello2 from m4"); + end + endtask + + task hello3; + begin + $display("hello3 from m4"); + end + endtask + + task hello4; + begin + $display("hello4 from m4"); + end + endtask + +endmodule diff --git a/ivtest/ivltests/sv_unit3a.v b/ivtest/ivltests/sv_unit3a.v new file mode 100644 index 000000000..d8c7e60f9 --- /dev/null +++ b/ivtest/ivltests/sv_unit3a.v @@ -0,0 +1,52 @@ +int num1 = 101; string str1 = "unit1"; +int num2 = 102; string str2 = "unit1"; +int num3 = 103; string str3 = "unit1"; + +class c1; + + int num2 = 100; string str2 = "c1"; + + task display; + begin + $display("%d from %s", num1, str1); + $display("%d from %s", num2, str2); + end + endtask + +endclass + + +module m1(); + + int num2 = 112; string str2 = "m1"; + + c1 obj; + + initial begin + #1; + obj = new; + obj.display; + $display("%d from %s", num1, str1); + $display("%d from %s", num2, str2); + $display("%d from %s", num3, str3); + $display("%d from %s", m2.num4, m2.str4); + end + +/* This should not change the result, but Icarus ignores the order in + which variables are declared and used. + int num3 = 113; string str3 = "m1"; +*/ + +endmodule + + +module m2(); + + int num1 = 121; string str1 = "m2"; + int num2 = 122; string str2 = "m2"; + int num3 = 123; string str3 = "m2"; + int num4 = 124; string str4 = "m2"; + + m1 m1inst(); + +endmodule diff --git a/ivtest/ivltests/sv_unit3b.v b/ivtest/ivltests/sv_unit3b.v new file mode 100644 index 000000000..e03cb72c5 --- /dev/null +++ b/ivtest/ivltests/sv_unit3b.v @@ -0,0 +1,35 @@ +int num1 = 201; string str1 = "unit2"; +int num2 = 202; string str2 = "unit2"; +int num3 = 203; string str3 = "unit2"; + +module m3(); + + int num2 = 232; string str2 = "m3"; + + initial begin + #2; // allow m1 to go first + m2.m1inst.obj.display; + $display("%d from %s", num1, str1); + $display("%d from %s", num2, str2); + $display("%d from %s", num3, str3); + $display("%d from %s", m4.num4, m4.str4); + end + +/* This should not change the result, but Icarus ignores the order in + which variables are declared and used. + int num3 = 113; string str3 = "m3"; +*/ + +endmodule + + +module m4(); + + int num1 = 241; string str1 = "m4"; + int num2 = 242; string str2 = "m4"; + int num3 = 243; string str3 = "m4"; + int num4 = 244; string str4 = "m4"; + + m3 m3inst(); + +endmodule diff --git a/ivtest/ivltests/sv_unit4a.v b/ivtest/ivltests/sv_unit4a.v new file mode 100644 index 000000000..356f3fdcb --- /dev/null +++ b/ivtest/ivltests/sv_unit4a.v @@ -0,0 +1,52 @@ +localparam num1 = 101, str1 = "unit1"; +localparam num2 = 102, str2 = "unit1"; +localparam num3 = 103, str3 = "unit1"; + +class c1; + + const int num2 = 100; const string str2 = "c1"; + + task display; + begin + $display("%d from %s", num1, str1); + $display("%d from %s", num2, str2); + end + endtask + +endclass + + +module m1(); + + localparam num2 = 112, str2 = "m1"; + + c1 obj; + + initial begin + #1; + obj = new; + obj.display; + $display("%d from %s", num1, str1); + $display("%d from %s", num2, str2); + $display("%d from %s", num3, str3); + $display("%d from %s", m2.num4, m2.str4); + end + +/* This should not change the result, but Icarus ignores the order in + which variables are declared and used. + localparam num3 = 113, str3 = "m1"; +*/ + +endmodule + + +module m2(); + + localparam num1 = 121, str1 = "m2"; + localparam num2 = 122, str2 = "m2"; + localparam num3 = 123, str3 = "m2"; + localparam num4 = 124, str4 = "m2"; + + m1 m1inst(); + +endmodule diff --git a/ivtest/ivltests/sv_unit4b.v b/ivtest/ivltests/sv_unit4b.v new file mode 100644 index 000000000..cb7fbd3df --- /dev/null +++ b/ivtest/ivltests/sv_unit4b.v @@ -0,0 +1,35 @@ +parameter num1 = 201, str1 = "unit2"; +parameter num2 = 202, str2 = "unit2"; +parameter num3 = 203, str3 = "unit2"; + +module m3(); + + parameter num2 = 232, str2 = "m3"; + + initial begin + #2; // allow m1 to go first + m2.m1inst.obj.display; + $display("%d from %s", num1, str1); + $display("%d from %s", num2, str2); + $display("%d from %s", num3, str3); + $display("%d from %s", m4.num4, m4.str4); + end + +/* This should not change the result, but Icarus ignores the order in + which variables are declared and used. + parameter num = 113, str3 = "m3"; +*/ + +endmodule + + +module m4(); + + parameter num1 = 241, str1 = "m4"; + parameter num2 = 242, str2 = "m4"; + parameter num3 = 243, str3 = "m4"; + parameter num4 = 244, str4 = "m4"; + + m3 m3inst(); + +endmodule diff --git a/ivtest/ivltests/sv_unpacked_port.v b/ivtest/ivltests/sv_unpacked_port.v new file mode 100644 index 000000000..f06b25f2c --- /dev/null +++ b/ivtest/ivltests/sv_unpacked_port.v @@ -0,0 +1,49 @@ + +module test + #(parameter width = 8) + (input wire clk, + input wire [1:0] addr, + input wire [width-1:0] data[0:3], + output reg [width-1:0] Q + /* */); + + always @(posedge clk) + Q <= data[addr]; + +endmodule // test + +module main; + + localparam width = 8; + + reg clk; + reg [1:0] addr; + logic [width-1:0] data [0:3]; + + wire [width-1:0] Q; + + test #(.width(width)) DUT (.clk(clk), .addr(addr), .data(data), .Q(Q)); + + reg [2:0] idx; + initial begin + clk = 0; + data[0] = 0; + data[1] = 1; + data[2] = 2; + data[3] = 3; + addr = 0; + + for (idx = 0 ; idx < 4 ; idx += 1) begin + clk = 0; + #1 addr = idx[1:0]; + #1 clk = 1; + #1 if (Q !== data[addr]) begin + $display("FAILED -- data[%0d]==%h, Q==%h", addr, data[addr], Q); + $finish; + end + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/sv_unpacked_port2.v b/ivtest/ivltests/sv_unpacked_port2.v new file mode 100644 index 000000000..417b45e43 --- /dev/null +++ b/ivtest/ivltests/sv_unpacked_port2.v @@ -0,0 +1,57 @@ + +module test + (input clk, + input wire [7:0] D, + input wire [1:0] S, + output reg [7:0] Q [0:3] + /* */); + + always @(posedge clk) + Q[S] <= D; + +endmodule // test + + +module main; + + reg clk; + reg [1:0] S; + reg [7:0] D; + wire [7:0] Q [0:3]; + + test dut(.clk(clk), .D(D), .S(S), .Q(Q)); + + initial begin + clk = 0; + + S = 0; + D = 0; + #1 clk = 1; + #1 clk = 0; + + S = 1; + D = 1; + #1 clk = 1; + #1 clk = 0; + + S = 2; + D = 2; + #1 clk = 1; + #1 clk = 0; + + S = 3; + D = 3; + #1 clk = 1; + #1 clk = 0; + + for (int idx = 0 ; idx < 4 ; idx = idx+1) begin + if (Q[idx] != idx) begin + $display("FAILED -- Q[%0d] = %0d", idx, Q[idx]); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sv_unpacked_wire.v b/ivtest/ivltests/sv_unpacked_wire.v new file mode 100644 index 000000000..bc89b7d34 --- /dev/null +++ b/ivtest/ivltests/sv_unpacked_wire.v @@ -0,0 +1,42 @@ + +module main; + + localparam width = 8; + + reg clk; + reg [1:0] addr; + logic [width-1:0] data [0:3]; + + reg [width-1:0] Q; + + // Does SystemVerilog support continuous assignment + // of unpacked arrays? I think it does, but the LRM + // is really not clear on this. + wire [width-1:0] data_x[0:3]; + assign data_x = data; + always @(posedge clk) + Q <= data_x[addr]; + + reg [2:0] idx; + initial begin + clk = 0; + data[0] = 0; + data[1] = 1; + data[2] = 2; + data[3] = 3; + addr = 0; + + for (idx = 0 ; idx < 4 ; idx += 1) begin + clk = 0; + #1 addr = idx[1:0]; + #1 clk = 1; + #1 if (Q !== data[addr]) begin + $display("FAILED -- data[%0d]==%h, Q==%h", addr, data[addr], Q); + $finish; + end + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/sv_unpacked_wire2.v b/ivtest/ivltests/sv_unpacked_wire2.v new file mode 100644 index 000000000..9ade63a7b --- /dev/null +++ b/ivtest/ivltests/sv_unpacked_wire2.v @@ -0,0 +1,36 @@ + +module TEST + #(parameter ME = 0) + (input OE, + output wire [3:0] Q + /* */); + + assign Q = OE? ME : 4'd0; + +endmodule // TEST + +module main; + + logic OE; + logic [3:0] Q [0:3]; + + genvar gidx; + + for (gidx = 0 ; gidx < 4 ; gidx = gidx+1) begin : DRV + TEST #(.ME(gidx)) dut (.OE(OE), .Q(Q[gidx])); + end + + int idx; + initial begin + OE = 1; + #1 ; + for (idx = 0 ; idx < 4 ; idx = idx+1) begin + if (Q[idx] !== idx[3:0]) begin + $display("FAILED -- Q[%0d] === %b", idx, Q[idx]); + $finish; + end + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/sv_uwire1.v b/ivtest/ivltests/sv_uwire1.v new file mode 100644 index 000000000..2a56327d2 --- /dev/null +++ b/ivtest/ivltests/sv_uwire1.v @@ -0,0 +1,30 @@ + +// This simple program tests that a variable can be assigned +// party by continuous assignment, and partly by behavioral +// assignment. As long as the parts don't overlap, this is +// legal (in SystemVerilog) + +module main; + + logic [3:0] foo; + + // Part of the vector is assigned by continuous assignment + logic [1:0] bar; + assign foo[2:1] = bar; + + initial begin + // Part of the vector is assigned behaviorally. + foo[0] = 1'b1; + foo[3] = 1'b1; + bar = 2'b00; + + #1 if (foo !== 4'b1001) begin + $display("FAILED -- foo=%b", foo); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/sv_uwire2.v b/ivtest/ivltests/sv_uwire2.v new file mode 100644 index 000000000..eb0353fa1 --- /dev/null +++ b/ivtest/ivltests/sv_uwire2.v @@ -0,0 +1,30 @@ + +// This simple program tests that a variable can be assigned +// party by continuous assignment, and partly by behavioral +// assignment. As long as the parts don't overlap, this is +// legal (in SystemVerilog) + +module main; + + logic [3:0] foo; + + // Part of the vector is assigned by continuous assignment + logic [1:0] bar; + assign foo[2:1] = bar; + + initial begin + // Part of the vector is assigned behaviorally. + foo[0:0] = 1'b1; + foo[3:3] = 1'b1; + bar = 2'b00; + + #1 if (foo !== 4'b1001) begin + $display("FAILED -- foo=%b", foo); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/sv_uwire3.v b/ivtest/ivltests/sv_uwire3.v new file mode 100644 index 000000000..09dec4e3d --- /dev/null +++ b/ivtest/ivltests/sv_uwire3.v @@ -0,0 +1,43 @@ + +// output ports may be uwire, or even a variable, if wire-ness +// or variable-ness are not explicitly stated. + +typedef struct packed { + logic [1:0] a; + logic [1:0] b; +} sample_t; + +module main; + sample_t dst; + logic [1:0] src_a, src_b; + + DUT dut(.out(dst), .x(src_a), .y(src_b)); + + initial begin + src_a = 1; + src_b = 2; + + #1 /* wait for dst */; + if (dst.a !== 1) begin + $display("FAILED -- dst.a=%b (dst=%b)", dst.a, dst); + $finish; + end + + if (dst.b !== 2) begin + $display("FAILED -- dst.b=%b (dst=%b)", dst.b, dst); + $finish; + end + + $display("PASSED"); + end +endmodule // main + +module DUT(output sample_t out, + input logic [1:0] x, y); + + always @* begin + out.a = x; + out.b = y; + end + +endmodule diff --git a/ivtest/ivltests/sv_uwire4.v b/ivtest/ivltests/sv_uwire4.v new file mode 100644 index 000000000..b80f79ef4 --- /dev/null +++ b/ivtest/ivltests/sv_uwire4.v @@ -0,0 +1,43 @@ + +// output ports may be uwire, or even a variable, if wire-ness +// or variable-ness are not explicitly stated. + +typedef struct packed { + logic [1:0] a; + logic [1:0] b; +} sample_t; + +module main; + sample_t dst; + logic [1:0] src_a, src_b; + + DUT dut(.out(dst), .a(src_a), .b(src_b)); + + initial begin + src_a = 1; + src_b = 2; + + #1 /* wait for dst */; + if (dst.a !== 1) begin + $display("FAILED -- dst.a=%b (dst=%b)", dst.a, dst); + $finish; + end + + if (dst.b !== 2) begin + $display("FAILED -- dst.b=%b (dst=%b)", dst.b, dst); + $finish; + end + + $display("PASSED"); + end +endmodule // main + +module DUT(output sample_t out, + input logic [1:0] a, b); + + always @* begin + out.a = a; + out.b = b; + end + +endmodule diff --git a/ivtest/ivltests/sv_var_init1.v b/ivtest/ivltests/sv_var_init1.v new file mode 100644 index 000000000..5c30a4517 --- /dev/null +++ b/ivtest/ivltests/sv_var_init1.v @@ -0,0 +1,16 @@ +module top(); + +integer i = 1; +integer j = 0; + +always @(i) j = i; + +initial begin + #0 $display("%0d %0d", i, j); + if ((i === 1) && (j === 0)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule // main diff --git a/ivtest/ivltests/sv_var_init2.v b/ivtest/ivltests/sv_var_init2.v new file mode 100644 index 000000000..3c9c767e5 --- /dev/null +++ b/ivtest/ivltests/sv_var_init2.v @@ -0,0 +1,15 @@ +module top(); + +always @(sub.i) sub.j = sub.i; + +initial begin:sub + static integer i = 1; + static integer j = 0; + #0 $display("%0d %0d", i, j); + if ((i === 1) && (j === 0)) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule // main diff --git a/ivtest/ivltests/sv_wildcard_import1.v b/ivtest/ivltests/sv_wildcard_import1.v new file mode 100644 index 000000000..0df62388d --- /dev/null +++ b/ivtest/ivltests/sv_wildcard_import1.v @@ -0,0 +1,47 @@ +package my_package; + +parameter p1 = 1; +localparam p2 = p1 + 2; + +typedef logic [15:0] word; + +typedef struct packed { + word v; +} st; + +st s; + +event e; + +function word f(word g); + f = g + 1; +endfunction + +task h(word i); + s.v = s.v + i; + $display(s.v); +endtask + +endpackage + +module test(); + +import my_package::*; + +word my_v; + +initial begin + my_v = p1; + #1 ->e; +end + +initial begin + @e s.v = my_v; + h(f(1)); + if (p2 === 3 && s.v === 3) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/sv_wildcard_import2.v b/ivtest/ivltests/sv_wildcard_import2.v new file mode 100644 index 000000000..2a121a8fc --- /dev/null +++ b/ivtest/ivltests/sv_wildcard_import2.v @@ -0,0 +1,66 @@ +package my_package; + +parameter p1 = 1; +localparam p2 = p1 + 'bx; + +typedef logic [1:0] word; + +word v = 2'bx; + +event e; + +function word f(word g); + f = g + 2'bx; +endfunction + +task h(word i); + v = v + i + 2'bx; + $display(v); +endtask + +endpackage + +module test(); + +import my_package::*; + +parameter p1 = 3; +localparam p2 = p1 + 2; + +typedef logic [7:0] word; + +word v = 0; + +event e; + +word my_v = 0; + +initial begin + #1 ->my_package::e; +end + +initial begin + @(my_package::e); + my_v = p1; + #1 ->e; +end + +initial begin + @e v = my_v; + h(f(1)); + if (p2 === 5 && $bits(v) === 8 && v === 5) + $display("PASSED"); + else + $display("FAILED"); +end + +function word f(word g); + f = g + 1; +endfunction + +task h(word i); + v = v + i; + $display(v); +endtask + +endmodule diff --git a/ivtest/ivltests/sv_wildcard_import3.v b/ivtest/ivltests/sv_wildcard_import3.v new file mode 100644 index 000000000..5bdbc7ab9 --- /dev/null +++ b/ivtest/ivltests/sv_wildcard_import3.v @@ -0,0 +1,67 @@ +package my_package; + +parameter p1 = 1; +localparam p2 = 2; + +typedef logic [3:0] word; + +word v = 0; + +event e; + +function word f(word g); + f = g + 1; +endfunction + +task h(word i); + v = v + i; + $display(v); +endtask + +endpackage + +module test(); + +parameter p1 = 'bx; +localparam p2 = 'bx; + +typedef logic [7:0] word; + +word v = 8'bx; + +event e; + +word my_v = 1; + +initial begin + #1 ->my_package::e; +end + +initial begin + @(my_package::e); + #1 my_v = 8'bx; + #1 ->e; +end + +initial begin:my_block + import my_package::*; + // Because this is a new scope, we should use the + // imported versions of p1, p2, e, v, f, and h. + @e v = my_v; + h(f(1)); + if (p1 === 1 && p2 === 2 && $bits(v) === 4 && v === 3) + $display("PASSED"); + else + $display("FAILED"); +end + +function word f(word g); + f = g + 8'bx; +endfunction + +task h(word i); + v = v + i + 8'bx; + $display(v); +endtask + +endmodule diff --git a/ivtest/ivltests/sv_wildcard_import4.v b/ivtest/ivltests/sv_wildcard_import4.v new file mode 100644 index 000000000..954b5030f --- /dev/null +++ b/ivtest/ivltests/sv_wildcard_import4.v @@ -0,0 +1,33 @@ +package my_package; + +parameter p1 = 1; +localparam p2 = 2; + +typedef logic [1:0] word; + +word v; + +event e; + +endpackage + +module test(); + +import my_package::*; + +word my_v; + +initial begin + @(e) v = p1 + p2; +end + +parameter p1 = 3; +localparam p2 = 4; + +typedef logic [7:0] word; + +word v; + +event e; + +endmodule diff --git a/ivtest/ivltests/sv_wildcard_import5.v b/ivtest/ivltests/sv_wildcard_import5.v new file mode 100644 index 000000000..12e72b9c3 --- /dev/null +++ b/ivtest/ivltests/sv_wildcard_import5.v @@ -0,0 +1,57 @@ +package my_package1; + +parameter p1 = 1; +localparam p2 = 2; + +typedef logic [1:0] word; + +word v; + +event e; + +function word f(word g); + f = g + 1; +endfunction + +task h(word i); + v = v + i; + $display(v); +endtask + +endpackage + +package my_package2; + +parameter p1 = 1; +localparam p2 = 2; + +typedef logic [1:0] word; + +word v; + +event e; + +function word f(word g); + f = g + 1; +endfunction + +task h(word i); + v = v + i; + $display(v); +endtask + +endpackage + +module test(); + +import my_package1::*; +import my_package2::*; + +word my_v; + +initial begin + @(e) v = p1 + p2; + h(f(1)); +end + +endmodule diff --git a/ivtest/ivltests/sv_wildcard_import6.v b/ivtest/ivltests/sv_wildcard_import6.v new file mode 100644 index 000000000..c803db449 --- /dev/null +++ b/ivtest/ivltests/sv_wildcard_import6.v @@ -0,0 +1,54 @@ +package my_package1; + +parameter p1 = 1; +localparam p2 = p1 + 2; + +typedef logic [15:0] word; + +typedef struct packed { + word v; +} st; + +endpackage + +package my_package2; + +import my_package1::*; + +st s; + +event e; + +function word f(word g); + f = g + 1; +endfunction + +task h(word i); + s.v = s.v + i; + $display(s.v); +endtask + +endpackage + +module test(); + +import my_package1::*; +import my_package2::*; + +word my_v; + +initial begin + my_v = p1; + #1 ->e; +end + +initial begin + @e s.v = my_v; + h(f(1)); + if (p2 === 3 && s.v === 3) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/sv_wildcard_import7.v b/ivtest/ivltests/sv_wildcard_import7.v new file mode 100644 index 000000000..6dc7d82cd --- /dev/null +++ b/ivtest/ivltests/sv_wildcard_import7.v @@ -0,0 +1,49 @@ +package my_package; + +parameter p1 = 1; +localparam p2 = p1 + 2; + +typedef logic [15:0] word; + +typedef struct packed { + word v; +} st; + +endpackage + +import my_package::*; + +st s; + +event e; + +function word f(word g); + f = g + 1; +endfunction + +task h(word i); + s.v = s.v + i; + $display(s.v); +endtask + +module test(); + +import my_package::*; + +word my_v; + +initial begin + my_v = p1; + #1 ->e; +end + +initial begin + @e s.v = my_v; + h(f(1)); + if (p2 === 3 && s.v === 3) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/switch_primitives.v b/ivtest/ivltests/switch_primitives.v new file mode 100644 index 000000000..ec7d676f2 --- /dev/null +++ b/ivtest/ivltests/switch_primitives.v @@ -0,0 +1,50 @@ +module switch_primitives(); + +wire a; +wire b0; +wire b1; +wire m0; +wire m1; +wire t0; +wire t1; +reg in; +reg en; + +bufif0(b0, a, en); +bufif1(b1, a, en); + +pmos(m0, a, en); +nmos(m1, a, en); + +tranif0(t0, a, en); +tranif1(a, t1, en); + +assign a = in; + +initial begin + $monitor("%b %b %b %b %b %b %b %b %v %v %v %v %v %v", + en, a, b0, b1, m0, m1, t0, t1, + b0, b1, m0, m1, t0, t1); + #1 $display("------------------"); + #1 en = 1'b0; in = 1'b0; + #1 en = 1'b0; in = 1'b1; + #1 en = 1'b0; in = 1'bx; + #1 en = 1'b0; in = 1'bz; + #1 $display("------------------"); + #1 en = 1'b1; in = 1'b0; + #1 en = 1'b1; in = 1'b1; + #1 en = 1'b1; in = 1'bx; + #1 en = 1'b1; in = 1'bz; + #1 $display("------------------"); + #1 en = 1'bx; in = 1'b0; + #1 en = 1'bx; in = 1'b1; + #1 en = 1'bx; in = 1'bx; + #1 en = 1'bx; in = 1'bz; + #1 $display("------------------"); + #1 en = 1'bz; in = 1'b0; + #1 en = 1'bz; in = 1'b1; + #1 en = 1'bz; in = 1'bx; + #1 en = 1'bz; in = 1'bz; +end + +endmodule diff --git a/ivtest/ivltests/swrite.v b/ivtest/ivltests/swrite.v new file mode 100644 index 000000000..d3c9c3487 --- /dev/null +++ b/ivtest/ivltests/swrite.v @@ -0,0 +1,326 @@ +`timescale 1ns/1ps + +//`define DEBUG +module top; + parameter length = 34; + parameter str = "%s"; + reg [length*8-1:0] result, fmt; + integer val = 1000; + reg [31:0] eval, uval, zval; + reg [63:0] hval, sval; + real rval = 1234.567; + wire net; + time tm = 234567; + realtime rtm = 2345.678; + reg failed; +`ifdef DEBUG + integer lp; +`endif + + assign (pull1, strong0) net = 1'b1; + + task check_result; + input [length*8-1:0] result, value; + input [80*8-1:0] message; + if (result != value) begin + $display("%0s", message); + $display("Got :%s:", result); + $display("Wanted :%s:", value); +`ifdef DEBUG + for (lp=0; lp", "%l in $swrite failed!"); + $swrite(result, "%L"); + check_result(result, "<%L>", "%L in $swrite failed!"); + + // %m + $swrite(result, "%m"); + check_result(result, "top", "%m in $swrite failed!"); + $swrite(result, "%M"); + check_result(result, "top", "%M in $swrite failed!"); + $swrite(result, "%8m"); + check_result(result, " top", "%m in $swrite failed!"); + $swrite(result, "%-8m"); + check_result(result, "top ", "%m in $swrite failed!"); + + // %s + $swrite(result, "%s", "Hello"); + check_result(result, "Hello", "%s in $swrite failed!"); + $swrite(result, "%S", "Hello"); + check_result(result, "Hello", "%S in $swrite failed!"); + $swrite(result, str, "Hello"); + check_result(result, "Hello", "%s in $swrite failed!"); + $swrite(result, "%14s", "Hello"); + check_result(result, " Hello", "%14s in $swrite failed!"); + $swrite(result, "%-14s", "Hello"); + check_result(result, "Hello ", "%-14s in $swrite failed!"); + + // %t + $swrite(result, "%t", 0); + check_result(result, " 0.0000 ps", "%t in $swrite failed!"); + $swrite(result, "%t", 1); + check_result(result, " 1000.0000 ps", "%t in $swrite failed!"); + $swrite(result, "%T", 1); + check_result(result, " 1000.0000 ps", "%T in $swrite failed!"); + $swrite(result, "%t", 10_000); + check_result(result, " 10000000.0000 ps", "%t in $swrite failed!"); + $swrite(result, "%t", $time); + check_result(result, " 1000.0000 ps", "%t $time in $swrite failed!"); +// $swrite(result, "%t", $simtime); +// check_result(result, " 1000.0000 ps", +// "%t $simtime in $swrite failed!"); + $swrite(result, "%-t", 1); + check_result(result, "1000.0000 ps ", "%-t in $swrite failed!"); + $swrite(result, "%15t", 1); + check_result(result, " 1000.0000 ps", "%15t in $swrite failed!"); + $swrite(result, "%-15t", 1); + check_result(result, "1000.0000 ps ", "%-15t in $swrite failed!"); + $swrite(result, "%15.1t", 1); + check_result(result, " 1000.0 ps", "%15.1t in $swrite failed!"); + // Real values. + $swrite(result, "%t", 1.1); + check_result(result, " 1100.0000 ps", "%t in $swrite failed!"); + $swrite(result, "%t", $realtime); + check_result(result, " 1000.0000 ps", + "%t $realtime in $swrite failed!"); + $swrite(result, "%-t", 1.1); + check_result(result, "1100.0000 ps ", "%-t in $swrite failed!"); + $swrite(result, "%15t", 1.1); + check_result(result, " 1100.0000 ps", "%15t in $swrite failed!"); + $swrite(result, "%-15t", 1.1); + check_result(result, "1100.0000 ps ", "%-15t in $swrite failed!"); + $swrite(result, "%15.1t", 1.1); + check_result(result, " 1100.0 ps", "%15.1t in $swrite failed!"); + + // %u + $swrite(result, "%u", eval); + check_result(result, "\"", "%u in $swrite failed!"); + $swrite(result, "%U", eval); + check_result(result, "\"", "%U in $swrite failed!"); + $swrite(result, "%u", sval); + check_result(result, "Help me!", "%u in $swrite failed!"); + // "Help me!" + $swrite(result, "%u", hval); + check_result(result, "Help me!", "%u in $swrite failed!"); + // "Help" with check for correct x and z functionality. + $swrite(result, "%u", uval); + check_result(result, "Help", "%u in $swrite failed!"); + + // %v + $swrite(result, "%v", net); + check_result(result, "Pu1", "%v in $swrite failed!"); + $swrite(result, "%V", net); + check_result(result, "Pu1", "%V in $swrite failed!"); + $swrite(result, "%14v", net); + check_result(result, " Pu1", "%14v in $swrite failed!"); + $swrite(result, "%-14v", net); + check_result(result, "Pu1 ", "%-14v in $swrite failed!"); + + // %z + $swrite(result, "%z", eval); + check_result(result, "\"", "%z in $swrite failed!"); + $swrite(result, "%Z", eval); + check_result(result, "\"", "%Z in $swrite failed!"); + // "Help me!", but because of NULLs we only get "Help" + $swrite(result, "%z", hval); + check_result(result, "Help", "%z in $swrite failed!"); + // "Help me!" encoded using all the states! + $swrite(result, "%z", zval); + check_result(result, "Help me!", "%z in $swrite failed!"); + + // $sformat() + $sformat(result, "%s", "Hello world"); + check_result(result, "Hello world", "String in $sformat failed!"); + $sformat(result, str, "Hello world"); + check_result(result, "Hello world", "Parameter in $sformat failed!"); + $sformat(result, fmt, "Hello world"); + check_result(result, "Hello world", "Register in $sformat failed!"); + + $sformat(result, "%s"); + check_result(result, "<%s>", "$sformat missing argument failed!"); + $sformat(result, "%s", "Hello world", 2); + check_result(result, "Hello world", "$sformat extra argument failed!"); + + if (!failed) $display("All tests passed."); + + end +endmodule diff --git a/ivtest/ivltests/synth_if_no_else.v b/ivtest/ivltests/synth_if_no_else.v new file mode 100644 index 000000000..1b980aa5a --- /dev/null +++ b/ivtest/ivltests/synth_if_no_else.v @@ -0,0 +1,39 @@ + +module test(output reg Q, input wire D, input wire OE); + + always @* begin + Q = 0; + if (OE) + Q = D; + end +endmodule // test + +module main; + reg D, OE; + wire Q; + + test dut(Q, D, OE); + + (* ivl_synthesis_off *) initial begin + OE = 0; + D = 0; + #1 if (Q !== 0) begin + $display("FAILED -- Q=%b, D=%b, OE=%b", Q, D, OE); + $finish; + end + + D = 1; + #1 if (Q !== 0) begin + $display("FAILED -- Q=%b, D=%b, OE=%b", Q, D, OE); + $finish; + end + + OE = 1; + #1 if (Q !== 1) begin + $display("FAILED -- Q=%b, D=%b, OE=%b", Q, D, OE); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/sys_func_as_task.v b/ivtest/ivltests/sys_func_as_task.v new file mode 100644 index 000000000..b93fd507e --- /dev/null +++ b/ivtest/ivltests/sys_func_as_task.v @@ -0,0 +1,11 @@ +module top; + reg [79:0] str; + integer val; + + initial begin + str = "5"; + $sscanf(str, "%d", val); + if (val == 5) $display("PASSED"); + else $display("Failed to convert string, got %d", val); + end +endmodule diff --git a/ivtest/ivltests/sys_func_task_error.v b/ivtest/ivltests/sys_func_task_error.v new file mode 100644 index 000000000..3ee172cc3 --- /dev/null +++ b/ivtest/ivltests/sys_func_task_error.v @@ -0,0 +1,14 @@ +module top; + reg [79:0] str; + integer val; + + initial begin + // This should be a not defined in any module message. + $this_icarus_call_should_not_exist; + str = "5"; + // This should be a system function is being called as a task error. + $sscanf(str, "%d", val); + // This should be a system task is being called as a function error. + val = $display; + end +endmodule diff --git a/ivtest/ivltests/sysargs.v b/ivtest/ivltests/sysargs.v new file mode 100644 index 000000000..889a9bc4c --- /dev/null +++ b/ivtest/ivltests/sysargs.v @@ -0,0 +1,21 @@ +module main; + + wire a; + device U1(a); + + task work; + begin + $deposit(U1.r, 1); + $display("PASSED"); + $finish; + end + endtask + + initial work; + +endmodule + +module device(r); + output r; + reg r; +endmodule diff --git a/ivtest/ivltests/system.vhd b/ivtest/ivltests/system.vhd new file mode 100644 index 000000000..1d55ab3d4 --- /dev/null +++ b/ivtest/ivltests/system.vhd @@ -0,0 +1,158 @@ +-- This system does nothing useful +-- It takes input X and this is registered internally +-- It computes x+1 and x+const independently +-- The output is computed as (x+const)-(x+1)=const-1 +-- so the higher level modifies C and then C-1 is returned + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity Const_system is +generic (C: in integer := 500); +port (clk, reset: in std_logic; + x: in std_logic_vector (7 downto 0); + y: out std_logic_vector (10 downto 0) ); +end Const_system; + +library ieee; +use ieee.std_logic_1164.all; + +entity Add is + generic (n: integer := 8); + port (a, b: in std_logic_vector (n-1 downto 0); + sum: out std_logic_vector (n-1 downto 0); + cin: in std_logic ); +end Add; + +library ieee; +use ieee.std_logic_1164.all; + +entity Inc is + generic (n: integer := 8); + port (a: in std_logic_vector (n-1 downto 0); + sum: out std_logic_vector (n-1 downto 0) + ); +end Inc; + +library ieee; +use ieee.std_logic_1164.all; + +entity Reg_N is + generic (n: integer := 4); + port (clk, reset: in std_logic; + a: in std_logic_vector (n-1 downto 0); + a_reg: out std_logic_vector (n-1 downto 0) ); +end Reg_N; + +architecture System_rtl of Const_system is + +-- Register component +component Reg_N is + generic (n: integer := 4); + port (clk, reset: in std_logic; + a: in std_logic_vector (n-1 downto 0); + a_reg: out std_logic_vector (n-1 downto 0) ); +end component; + +-- incrementer component +component Inc is + generic (n: integer := 8); + port (a: in std_logic_vector (n-1 downto 0); + sum: out std_logic_vector (n-1 downto 0) + ); +end component; + +-- adder component +component Add is + generic (n: integer := 8); + port (a, b: in std_logic_vector (n-1 downto 0); + sum: out std_logic_vector (n-1 downto 0); + cin: in std_logic ); +end component; + + +signal x_int: std_logic_vector (7 downto 0); +signal x_inc: std_logic_vector (7 downto 0); +signal x_sum: std_logic_vector (10 downto 0); +signal x_ext: std_logic_vector (10 downto 0); +signal x_inv: std_logic_vector (10 downto 0); +signal x_dif: std_logic_vector (10 downto 0); + +signal zero, one: std_logic; + +signal const: std_logic_vector (10 downto 0); +begin + +const <= conv_std_logic_vector (C, 11); + +-- connstant bit 0, 1 +zero <= '0'; +one <= '1'; + +-- registering input X +RegX: Reg_N generic map (n => 8) + port map ( clk => clk, reset => reset, a => x, a_reg => x_int); + +-- Incrementing input x_int +incrementer: Inc generic map (n => 8) + port map (a => x_int, sum => x_inc); -- x + 1 + +-- forming 1's complement of x+1 +x_inv <= "111" & not x_inc; + +x_ext <= "000" & x_int; +-- adding constant to x_int +addition: Add generic map (n => 11) + port map (a => x_ext, b => const, cin => zero, sum => x_sum); -- x + 1000 + +-- this should get x+1000-(x+1) = 1000-1 = 999 +subtraction: Add generic map (n => 11) + port map (a => x_sum, b => x_inv, cin => one, sum => x_dif); + +-- registering output X +RegY: Reg_N generic map (n => 11) + port map ( clk => clk, reset => reset, a => x_dif, a_reg => y); + + +end System_rtl; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +architecture Add_rtl of Add is +signal cx: std_logic_vector (n downto 0); +begin +cx <= ('0' & a) + ('0' & b) + cin; +sum <= cx (n-1 downto 0); +end Add_rtl; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +architecture Inc_rtl of Inc is +signal cx: std_logic_vector (n downto 0); +begin +cx <= ('0' & a) + '1'; +sum <= cx (n-1 downto 0); +end Inc_rtl; + +library ieee; +use ieee.std_logic_1164.all; + +architecture Reg_rtl of Reg_N is +begin + +My_register: process (clk, reset) +begin + if (reset = '1') then + a_reg <= (others => '0'); + elsif (clk'event and clk = '1') then + a_reg <= a; + end if; +end process; + +end Reg_rtl; diff --git a/ivtest/ivltests/talu.v b/ivtest/ivltests/talu.v new file mode 100644 index 000000000..36eabaa3e --- /dev/null +++ b/ivtest/ivltests/talu.v @@ -0,0 +1,116 @@ +/* talu - a verilog test, + * illustrating problems I had in fragments of an ALU from an 8-bit micro + */ + +module talu; + reg error; + + reg [7:0] a; + reg [7:0] b; + reg cin; + reg [1:0] op; + + wire cout; + wire [7:0] aluout; + + alu alu_m(a, b, cin, op, aluout, cout); + + initial begin + error = 0; + + // add + op='b00; cin='b0; a='h0; b='h0; + #2 if({cout, aluout} != 9'h000) begin + $display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout); + error = 1; + end + + // add1 + op='b01; cin='b0; a='h01; b='h01; + #2 if({cout, aluout} != 9'h103) begin + $display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout); + error = 1; + end + + // and + op='b10; cin='b0; a='h16; b='h0F; + #2 if({cout, aluout} != 9'h006) begin + $display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout); + error = 1; + end + op='b10; cin='b0; a='h28; b='hF7; + #2 if({cout, aluout} != 9'h020) begin + $display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout); + error = 1; + end + + // genbit + op='b11; cin='b0; a='h00; b='h03; + #2 if({cout, aluout} != 9'h008) begin + $display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout); + error = 1; + end + op='b11; cin='b0; a='h00; b='h00; + #2 if({cout, aluout} != 9'h001) begin + $display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout); + error = 1; + end + /* tests are incomplete - doesn't compile yet on ivl */ + + + if(error == 0) + $display("PASSED"); + $finish; + + end + +endmodule + +/* + * fragments of an ALU from an 8-bit micro + */ + +module alu(Aval, Bval, cin, op, ALUout, cout); + input [7:0] Aval; + input [7:0] Bval; + input cin; + input [1:0] op; + output cout; + output [7:0] ALUout; + + reg cout; + reg [7:0] ALUout; + + always @(Aval or Bval or cin or op) begin + case(op) + 2'b00 : {cout, ALUout} = Aval + Bval; + 2'b10 : {cout, ALUout} = {1'b0, Aval & Bval}; + +// C++ compilation troubles with both of these: + 2'b01 : {cout, ALUout} = 9'h100 ^ (Aval + Bval + 9'h001); + 2'b11 : {cout, ALUout} = {1'b0, 8'b1 << Bval}; + +// 2'b01 : {cout, ALUout} = 9'h000; +// 2'b11 : {cout, ALUout} = 9'h000; + endcase + end // always @ (Aval or Bval or cin or op) + +endmodule + +/* Copyright (C) 1999 Stephen G. Tell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this software; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + */ diff --git a/ivtest/ivltests/task-scope.v b/ivtest/ivltests/task-scope.v new file mode 100644 index 000000000..a96e553f3 --- /dev/null +++ b/ivtest/ivltests/task-scope.v @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2000 Stephan I. Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// compile time test for nested task scope elaboration + +`define TEST + +module nest(r); + + output [7:0] r; + reg [7:0] r; + + task incr; + input [7:0] a; + begin + r <= r+a; + #1 $display("R=%b",r); + end + endtask + +endmodule + +module test; + + wire [7:0] acc; + + nest n(acc); + + initial n.r <= 0; + +`ifdef TEST + task increment; + begin + n.incr(1); + end + endtask +`endif + + initial + begin +`ifdef TEST + #10 increment; + #10 increment; + #10 increment; +`else + #10 n.incr(3); +`endif + #10; + if (acc==3) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/task3.14A.v b/ivtest/ivltests/task3.14A.v new file mode 100644 index 000000000..283c6e777 --- /dev/null +++ b/ivtest/ivltests/task3.14A.v @@ -0,0 +1,40 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate task w/ no I/O or internal state + + +module main; + +reg globvar; + +task my_task ; + globvar = 1'b1; +endtask + +initial + begin + globvar = 1'b0; + my_task; + if(globvar) + $display("PASSED"); + else + $display("FAILED - task 3.14A task didn't correctly affect global var"); + end + +endmodule // main diff --git a/ivtest/ivltests/task3.14B.v b/ivtest/ivltests/task3.14B.v new file mode 100644 index 000000000..1a3c8d99e --- /dev/null +++ b/ivtest/ivltests/task3.14B.v @@ -0,0 +1,41 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate task w/ simple input. + + +module main; + +reg globvar; + +task my_task ; + input in1; + globvar = in1; +endtask + +initial + begin + globvar = 1'b0; + my_task(1'b1); + if(globvar) + $display("PASSED"); + else + $display("FAILED - task 3.14B task didn't correctly affect global var"); + end + +endmodule // main diff --git a/ivtest/ivltests/task3.14C.v b/ivtest/ivltests/task3.14C.v new file mode 100644 index 000000000..2c65841cc --- /dev/null +++ b/ivtest/ivltests/task3.14C.v @@ -0,0 +1,55 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate task w/ simple input and output + + +module main; + +reg globvar; +reg in1; +reg error; + +task my_task ; + input in1; + output out1; + out1 = in1; +endtask + +initial + begin + error = 0; + my_task(1'b1,globvar); + if(~globvar) + begin + $display("FAILED - task 3.14C task didn't correctly affect global var(1)"); + error = 1; + end + + in1 = 0; + my_task(!in1,globvar); + if(~globvar) + begin + $display("FAILED - task 3.14C task didn't correctly affect global var(2)"); + error = 1; + end + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/task3.14D.v b/ivtest/ivltests/task3.14D.v new file mode 100644 index 000000000..8e829258a --- /dev/null +++ b/ivtest/ivltests/task3.14D.v @@ -0,0 +1,67 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate task w/ multiple inputs, single output + + +module main; + +reg var1,var2; +reg in1; +reg error; + +task my_task ; + input in1,in2; + output out1,out2; + begin + out1 = in1 ; + out2 = in2 ; + end +endtask + +initial + begin + error = 0; + my_task(1'b1,1'b0,var1,var2); + if(~(var1 & ~var2)) + begin + $display("FAILED - task 3.14D task didn't return correct value (1)"); + error = 1; + end + + in1 = 0; + my_task(~in1,~in1,var1,var2); + if(~(var1 & var2)) + begin + $display("FAILED - task 3.14D task didn't return correct value(2)"); + error = 1; + end + + in1 = 0; + my_task(in1,in1,var1,var2); + if(~(~var1 & ~var2)) + begin + $display("FAILED - task 3.14D task didn't return correct value(2)"); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/task3.14E.v b/ivtest/ivltests/task3.14E.v new file mode 100644 index 000000000..1b35d331c --- /dev/null +++ b/ivtest/ivltests/task3.14E.v @@ -0,0 +1,72 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate task calling a function + + +module main; + +reg var1,var2; +reg in1; +reg error; + +function foo ; + input in1 ; + foo = in1 ; +endfunction + +task my_task ; + input in1,in2; + output out1,out2; + begin + out1 = foo(~foo(in1)) ; + out2 = foo(in2) ; + end +endtask + +initial + begin + error = 0; + my_task(1'b1,1'b0,var1,var2); + if(~(~var1 & ~var2)) + begin + $display("FAILED - task 3.14E task calling a function (1)"); + error = 1; + end + + in1 = 0; + my_task(~in1,~in1,var1,var2); + if(~(~var1 & var2)) + begin + $display("FAILED - task 3.14E task calling a function(2)"); + error = 1; + end + + in1 = 0; + my_task(in1,in1,var1,var2); + if(~(var1 & ~var2)) + begin + $display("FAILED - task 3.14E task calling a function(3)"); + error = 1; + end + + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/task3.14F.v b/ivtest/ivltests/task3.14F.v new file mode 100644 index 000000000..b14437947 --- /dev/null +++ b/ivtest/ivltests/task3.14F.v @@ -0,0 +1,58 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate task with internal delay + + +module main; + +reg var1,var2; +reg in1; +reg error; + +task my_task ; + input in1; + output out1; + out1 = #10 in1; +endtask + +initial + begin + var1 = 0; + error = 0; + fork + my_task(1'b1,var1); + begin + if(var1 != 1'b0) + begin + $display("FAILED - task3.14F Task with internal delay(1)"); + error = 1; + end + #20; + if(var1 != 1'b1) + begin + $display("FAILED - task3.14F Task with internal delay(2)"); + error = 1; + end + end + join + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/task_bypath.v b/ivtest/ivltests/task_bypath.v new file mode 100644 index 000000000..8eb51edc5 --- /dev/null +++ b/ivtest/ivltests/task_bypath.v @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2001 Peter Bain + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test; + +task foo; +begin + $display("PASSED"); +end +endtask + +task bar; +begin + test.foo; +end +endtask + +initial begin + test.bar; +end + +endmodule diff --git a/ivtest/ivltests/task_init_assign.v b/ivtest/ivltests/task_init_assign.v new file mode 100644 index 000000000..2d932f60e --- /dev/null +++ b/ivtest/ivltests/task_init_assign.v @@ -0,0 +1,21 @@ +module main; + + // The declaration assignment within a task it not allowed + // in Verilog, but it is allowed in SystemVerilog. + task foo (input integer x, output integer y); + integer step = 3; + y = x + step; + endtask // foo + + integer a, b; + initial begin + a = 3; + foo(a, b); + if (b !== 6) begin + $display("FAILED"); + $finish; + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/task_init_var1.v b/ivtest/ivltests/task_init_var1.v new file mode 100644 index 000000000..620702fff --- /dev/null +++ b/ivtest/ivltests/task_init_var1.v @@ -0,0 +1,42 @@ +module test(); + +task accumulate1(input integer value, output integer result); + static int acc = 1; + acc = acc + value; + result = acc; +endtask + +task automatic accumulate2(input integer value, output integer result); + int acc = 1; + acc = acc + value; + result = acc; +endtask + +integer value; + +reg failed = 0; + +initial begin + accumulate1(2, value); + $display("%d", value); + if (value !== 3) failed = 1; + + accumulate1(3, value); + $display("%d", value); + if (value !== 6) failed = 1; + + accumulate2(2, value); + $display("%d", value); + if (value !== 3) failed = 1; + + accumulate2(3, value); + $display("%d", value); + if (value !== 4) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/task_init_var2.v b/ivtest/ivltests/task_init_var2.v new file mode 100644 index 000000000..fb418febd --- /dev/null +++ b/ivtest/ivltests/task_init_var2.v @@ -0,0 +1,46 @@ +module static test(); + +task accumulate1(input integer value, output integer result); +begin:blk + static int acc = 1; + acc = acc + value; + result = acc; +end +endtask + +task automatic accumulate2(input integer value, output integer result); +begin:blk + int acc = 1; + acc = acc + value; + result = acc; +end +endtask + +integer value; + +initial begin + static reg failed = 0; + + accumulate1(2, value); + $display("%d", value); + if (value !== 3) failed = 1; + + accumulate1(3, value); + $display("%d", value); + if (value !== 6) failed = 1; + + accumulate2(2, value); + $display("%d", value); + if (value !== 3) failed = 1; + + accumulate2(3, value); + $display("%d", value); + if (value !== 4) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/task_init_var3.v b/ivtest/ivltests/task_init_var3.v new file mode 100644 index 000000000..f2b24c728 --- /dev/null +++ b/ivtest/ivltests/task_init_var3.v @@ -0,0 +1,42 @@ +module automatic test(); + +task static accumulate1(input integer value, output integer result); + static int acc = 1; + acc = acc + value; + result = acc; +endtask + +task accumulate2(input integer value, output integer result); + int acc = 1; + acc = acc + value; + result = acc; +endtask + +integer value; + +reg failed = 0; + +initial begin + accumulate1(2, value); + $display("%d", value); + if (value !== 3) failed = 1; + + accumulate1(3, value); + $display("%d", value); + if (value !== 6) failed = 1; + + accumulate2(2, value); + $display("%d", value); + if (value !== 3) failed = 1; + + accumulate2(3, value); + $display("%d", value); + if (value !== 4) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/task_inpad.v b/ivtest/ivltests/task_inpad.v new file mode 100644 index 000000000..b43bd0b4c --- /dev/null +++ b/ivtest/ivltests/task_inpad.v @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * The assignment to the input of a task port should pad with + * zeros. It seems that certain Verilog bugs can cause this test to + * fail. + */ + +module test; + task writeInto; + input [31:0] x; + begin + $display("x=%h", x); + if (x[31:10] !== 22'd0) begin + $display("FAILED -- x is %b", x); + $finish; + end + end + endtask + + reg [7:0] y; + reg [31:0] y1; + initial begin + y1 = 512; + y = 4; + writeInto(y1); + writeInto(y); + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/task_iotypes.v b/ivtest/ivltests/task_iotypes.v new file mode 100644 index 000000000..ae211e70e --- /dev/null +++ b/ivtest/ivltests/task_iotypes.v @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program, based on PR#150, need only compile. It is testing + * the syntax of giving types to task ports. I'm careful to *not* + * invoke this task because there are potential optimization gotchas + * that have been known to trip up the compiler. Specifically, ports + * that are unused in a task that is not called can cause crashes in + * some Icarus Verilog versions + */ + +module gen_errors; + task A; + input B; + integer B; + output C; + integer C; + output D; + reg D; + inout [31:0] E; + reg [31:0] E; + input [15:0] F; + reg [15:0] F; + begin + C = B; + end + endtask + + initial begin + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/task_iotypes2.v b/ivtest/ivltests/task_iotypes2.v new file mode 100644 index 000000000..7486bff40 --- /dev/null +++ b/ivtest/ivltests/task_iotypes2.v @@ -0,0 +1,41 @@ +module main; + + task take_args; + + input integer iarg; + input real rarg; + output integer iout; + output real rout; + + begin + iout = iarg + 1; + rout = rarg + 1.0; + end + + endtask // take_args + + integer ii, io; + real ri, ro; + + initial begin + ii = 4; + ri = 6.0; + io = 0; + ro = 0.0; + + take_args(ii,ri,io,ro); + + if (io !== 5) begin + $display("FAILED -- ii=%d, io=%d", ii, io); + $finish; + end + + if (ro != 7.0) begin + $display("FAILED -- ri=%f, ro=%f", ri, ro); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/task_mem.v b/ivtest/ivltests/task_mem.v new file mode 100644 index 000000000..d38b835cd --- /dev/null +++ b/ivtest/ivltests/task_mem.v @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program tests the use of memories within tasks. + */ +module test; + parameter addrsiz = 14; + parameter ramsiz = 1 << addrsiz; + + task loadram; + integer i, j; + reg [15:0] memword; + reg [15:0] tempram[0:(2*ramsiz)-1]; + begin + for (i = 0; i < 16; i = i + 2) + tempram[i] = i; + + for (i = 0; i < 16; i = i + 2) + if (tempram[i] !== i) begin + $display("FAILED -- %m.tempram[%d] = %b", i, tempram[i]); + $finish; + end + + $display("PASSED"); + end + endtask // loadram + + initial loadram; + +endmodule diff --git a/ivtest/ivltests/task_noop.v b/ivtest/ivltests/task_noop.v new file mode 100644 index 000000000..09f9cad2f --- /dev/null +++ b/ivtest/ivltests/task_noop.v @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2000 Chris Lattner + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test catches the definition of a null task. The statement is + * empty, so the compiler can do some optimizations. + */ +module test; + task mod; + input [31:0] a; + begin + end + endtask + + initial begin + mod(5'd0); + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/task_noop2.v b/ivtest/ivltests/task_noop2.v new file mode 100644 index 000000000..a32f940de --- /dev/null +++ b/ivtest/ivltests/task_noop2.v @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2000 Philips Semiconductors Stefan.Thiede@philips.com + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module test(a); +input a; +task otto; + ; +endtask +endmodule diff --git a/ivtest/ivltests/task_omemw.v b/ivtest/ivltests/task_omemw.v new file mode 100644 index 000000000..0dccd8bca --- /dev/null +++ b/ivtest/ivltests/task_omemw.v @@ -0,0 +1,42 @@ +// Copyright (c) 2000 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +// This tests tasks being able to write to output parameters that +// are memory words. This is legal as val[0] is a valid l-value. + + +module test; + reg [31:0] val[1:0], tmp; + + + task testT; + output [31:0] val2; + begin + val2 = 1234; + end + endtask + + initial begin + testT(val[0]); + if (val[0] === 1234) + $display("PASSED"); + else + $display("FAILED -- val[0] == %b"); + + end +endmodule diff --git a/ivtest/ivltests/task_omemw2.v b/ivtest/ivltests/task_omemw2.v new file mode 100644 index 000000000..d1bbbd100 --- /dev/null +++ b/ivtest/ivltests/task_omemw2.v @@ -0,0 +1,44 @@ +// Copyright (c) 2000 Stephen Williams (steve@icarus.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +// This tests tasks being able to write to output parameters that +// are memory words. This is legal as val[0] is a valid l-value. +// In addition, it catches binding issues. Note the common name +// of the val parameter and the val memory. + + +module test; + reg [31:0] val[1:0], tmp; + + + task testT; + output [31:0] val; + begin + val = 1234; + end + endtask + + initial begin + testT(val[0]); + if (val[0] === 1234) + $display("PASSED"); + else + $display("FAILED -- val[0] == %b",val[0]); + + end +endmodule diff --git a/ivtest/ivltests/task_omemw3.v b/ivtest/ivltests/task_omemw3.v new file mode 100644 index 000000000..6b29f2909 --- /dev/null +++ b/ivtest/ivltests/task_omemw3.v @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module test; + reg [31:0] arr[1:0]; + + task writeInto; + output [31:0] into; + begin + into = 1; + end + endtask + + initial begin + writeInto(arr[1]); + if (arr[1] !== 32'd0) begin + $display("FAILED -- arr[1] = %h", arr[1]); + $finish; + end + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/task_port_size.v b/ivtest/ivltests/task_port_size.v new file mode 100644 index 000000000..ffc85552b --- /dev/null +++ b/ivtest/ivltests/task_port_size.v @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: task_port_size.v,v 1.1 2001/07/24 04:13:49 sib4 Exp $ + +// PR#205 + +module main; + + function f; + input a; + begin + f = a; + end + endfunction + + reg r; + + initial + begin + r <= f(32'b 101); + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/task_scope.v b/ivtest/ivltests/task_scope.v new file mode 100644 index 000000000..7f37bcb6b --- /dev/null +++ b/ivtest/ivltests/task_scope.v @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: task_scope.v,v 1.1 2001/06/19 13:52:13 ka6s Exp $ +// $Log: task_scope.v,v $ +// Revision 1.1 2001/06/19 13:52:13 ka6s +// Added 4 tests from Stephan Boettcher +// + +// Test for task scope lookup in VVP + +module test; + + wire w; + + jobs j(w); + + task ini; + begin + j.set(1'bz); + end + endtask + + initial + begin + ini; + #1; + j.set(1'b1); + #1; + if (w===1) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule // test + +module jobs (out); + + output out; + reg out; + + task set; + input val; + begin + #1 out = val; + end + endtask + +endmodule // jobs diff --git a/ivtest/ivltests/task_scope2.v b/ivtest/ivltests/task_scope2.v new file mode 100644 index 000000000..67c01ea70 --- /dev/null +++ b/ivtest/ivltests/task_scope2.v @@ -0,0 +1,70 @@ +/* + * Modified to add "endtask : " syntax. This modification tests + * the SystemVerilog extension to the syntax. -- Stephen Williams + */ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: task_scope.v,v 1.1 2001/06/19 13:52:13 ka6s Exp $ +// $Log: task_scope.v,v $ +// Revision 1.1 2001/06/19 13:52:13 ka6s +// Added 4 tests from Stephan Boettcher +// + +// Test for task scope lookup in VVP + +module test; + + wire w; + + jobs j(w); + + task ini; + begin + j.set(1'bz); + end + endtask : ini + + initial + begin + ini; + #1; + j.set(1'b1); + #1; + if (w===1) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule // test + +module jobs (out); + + output out; + reg out; + + task set; + input val; + begin + #1 out = val; + end + endtask : set + +endmodule // jobs diff --git a/ivtest/ivltests/tern1.v b/ivtest/ivltests/tern1.v new file mode 100644 index 000000000..7bf288c26 --- /dev/null +++ b/ivtest/ivltests/tern1.v @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test catches the case where the operands of the ?: operator + * have different sizes. + */ +module main; + + reg [3:0] r; + reg [3:0] a; + reg [4:0] b; + reg f; + + + initial begin + a = 4'b1010; + b = 5'b10101; + + f = 1; + r = f? a : b; + if (r !== 4'b1010) begin + $display("FAILED: r === %b", r); + $finish; + end + + f = 0; + r = f? a : b; + if (r !== 4'b0101) begin + $display("FAILED: r === %b", r); + $finish; + end + + $display("PASSED"); + + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/tern10.v b/ivtest/ivltests/tern10.v new file mode 100644 index 000000000..d8596cbb9 --- /dev/null +++ b/ivtest/ivltests/tern10.v @@ -0,0 +1,28 @@ +module main; + + reg flag; + reg [3:0] a, b; + wire [4:0] Q = flag? a : b; + + initial begin + flag = 1; + a = 4'b1010; + b = 4'b0101; + + #1 $display("%b = %b? %b : %b", Q, flag, a, b); + + if (Q !== 5'b01010) begin + $display("FAILED -- Q=%b, flag=%b, a=%b", Q, flag, a); + $finish; + end + + flag = 0; + #1 if (Q !== 5'b00101) begin + $display("FAILED -- Q=%b, flag=%b, b=%b", Q, flag, b); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/tern2.v b/ivtest/ivltests/tern2.v new file mode 100644 index 000000000..212441d7f --- /dev/null +++ b/ivtest/ivltests/tern2.v @@ -0,0 +1,23 @@ +/* + * This program doesn't do anything, and shouldn't be run. This is + * only to check that the null target can see the ternary operator. + */ + +module main2( ); + + reg sel; + reg [13:0] out; + reg [13:0] a, b; + +// This assign works OK +// assign out[13:0] = ( sel ? a[13:0] : b[13:0] ); + + always @( + sel or + a or + b + ) + begin + out[13:0] = ( sel ? a[13:0] : b[13:0] ); + end +endmodule diff --git a/ivtest/ivltests/tern3.v b/ivtest/ivltests/tern3.v new file mode 100644 index 000000000..ee293146b --- /dev/null +++ b/ivtest/ivltests/tern3.v @@ -0,0 +1,27 @@ +module test; + + reg [0:0] stat; + initial begin + stat = 1'b0; + // This should display (Start). + $display("(%s)", stat[0] ? "Stop" : "Start"); + + // This should also display (Start). It's been known + // to display (tart) by getting the expression width + // from the true clause. + $display("(%s)", !stat[0] ? "Start" : "Stop"); + + $display("$bits == %0d", $bits(stat[0] ? "Stop" : "Start")); + if ($bits(stat[0] ? "Stop" : "Start") !== 40) begin + $display("FAILED"); + $finish; + end + + $display("$bits == %0d", $bits(stat[0] ? "Start" : "Stop")); + if ($bits(stat[0] ? "Start" : "Stop") !== 40) begin + $display("FAILED"); + $finish; + end + end + +endmodule diff --git a/ivtest/ivltests/tern4.v b/ivtest/ivltests/tern4.v new file mode 100644 index 000000000..4995eb78b --- /dev/null +++ b/ivtest/ivltests/tern4.v @@ -0,0 +1,21 @@ +module main; + + reg out, c, a, b; + + initial begin + c = 0; + a = 0; + b = 1; + out = c ? (a & b) : b; + + $display("%b = %b ? (%b & %b) : %b;", out, c, a, b, b); + if (out !== 1) begin + $display("FAILED -- out=%b result is incorrect!", out); + $finish; + end + + $display("PASSED"); + $finish; + end + +endmodule // main diff --git a/ivtest/ivltests/tern5.v b/ivtest/ivltests/tern5.v new file mode 100644 index 000000000..f0b251469 --- /dev/null +++ b/ivtest/ivltests/tern5.v @@ -0,0 +1,47 @@ +/* + */ + +module main(); + + reg [8:0] foo; + + reg [1:0] bar; + initial begin + foo = 2'b00 ? 9'b000111xxx : 9'b01x01x01x; + $display("00: foo = %b", foo); + + foo = 2'b01 ? 9'b000111xxx : 9'b01x01x01x; + $display("01: foo = %b", foo); + + foo = 2'b0x ? 9'b000111xxx : 9'b01x01x01x; + $display("0x: foo = %b", foo); + + foo = 2'b11 ? 9'b000111xxx : 9'b01x01x01x; + $display("11: foo = %b", foo); + + foo = 2'b1x ? 9'b000111xxx : 9'b01x01x01x; + $display("1x: foo = %b", foo); + + bar = 2'b00; + foo = bar? 9'b000111xxx : 9'b01x01x01x; + $display("%b: foo = %b", bar, foo); + + bar = 2'b01; + foo = bar? 9'b000111xxx : 9'b01x01x01x; + $display("%b: foo = %b", bar, foo); + + bar = 2'b0x; + foo = bar? 9'b000111xxx : 9'b01x01x01x; + $display("%b: foo = %b", bar, foo); + + bar = 2'b11; + foo = bar? 9'b000111xxx : 9'b01x01x01x; + $display("%b: foo = %b", bar, foo); + + bar = 2'b1x; + foo = bar? 9'b000111xxx : 9'b01x01x01x; + $display("%b: foo = %b", bar, foo); + + end + +endmodule diff --git a/ivtest/ivltests/tern6.v b/ivtest/ivltests/tern6.v new file mode 100644 index 000000000..9f664e09f --- /dev/null +++ b/ivtest/ivltests/tern6.v @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version.will need a Picture Elements Binary Software + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program catches some glitches in the MUXZ that Icarus Verilog + * uses to implement the ?: in structural cases. + */ +module main; + + reg [6:0] a, b; + reg sel; + + wire [6:0] test = sel? a : b; + + wire [7:0] test2 = test; + + initial begin + sel = 0; + // At this point, test2 should be x. + #1 $display("sel=%b, test2=%b", sel, test2); + + b = 0; + #1 $display("sel=b, test2=%b", sel, test2); + if (test2 !== 8'b0_0000000) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/tern7.v b/ivtest/ivltests/tern7.v new file mode 100644 index 000000000..1e36b2087 --- /dev/null +++ b/ivtest/ivltests/tern7.v @@ -0,0 +1,66 @@ +`begin_keywords "1364-2005" +/* + * Copyright (c) 2005 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* tern7.v + * This tests types. + */ +module main; + + reg b, c, d, e; + wire a = b ? c : (d&e); + + reg [4:0] tmp; + reg ref; + initial begin + // Do an exaustive scan of the possible values. + for (tmp = 0 ; tmp < 16 ; tmp = tmp + 1) begin + b <= tmp[0]; + c <= tmp[1]; + d <= tmp[2]; + e <= tmp[3]; + ref = tmp[0] ? tmp[1] : (tmp[2]&tmp[3]); + + #1 if (ref !== a) begin + $display("FAILED -- a=%b, b=%b, c=%b, d=%b, e=%b", + a, b, c, d, e); + $finish; + end + end // for (tmp = 0 ; tmp < 16 ; tmp = tmp + 1) + + b <= 0; + c <= 1; + d <= 1; + e <= 0; + #1 if (a !== 1'b0) begin + $display("FAILED (1)"); + $finish; + end + + e <= 1; + #1 if (a !== 1'b1) begin + $display("FAILED (2)"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main +`end_keywords diff --git a/ivtest/ivltests/tern8.v b/ivtest/ivltests/tern8.v new file mode 100644 index 000000000..14105411f --- /dev/null +++ b/ivtest/ivltests/tern8.v @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2005 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* tern8.v + * This tests types. + */ +module main; + + reg b; + real c, d; + wire real a = b ? c : d; + + initial begin + + b <= 0; + c <= 1.0; + d <= 2.0; + #1 if (a != 2.0) begin + $display("FAILED (1)"); + $finish; + end + + b <= 1; + #1 if (a != 1.0) begin + $display("FAILED (2)"); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/tern9.v b/ivtest/ivltests/tern9.v new file mode 100644 index 000000000..66ab986c5 --- /dev/null +++ b/ivtest/ivltests/tern9.v @@ -0,0 +1,99 @@ +/* tern9.v + */ +module main; + + reg flag; + reg val; + wire test1 = flag? val : 1'bx; + wire test2 = flag? 1'b0 : 1'bx; + wire test3 = flag? 1'bx : val; + + initial begin + flag = 1; + val = 0; + + #1 if (test1 !== 1'b0) begin + $display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1); + $finish; + end + + if (test2 !== 1'b0) begin + $display("FAILED -- flag=%b, test2=%b", flag, test2); + $finish; + end + + if (test3 !== 1'bx) begin + $display("FAILED -- flag=%b, test3=%b", flag, test3); + $finish; + end + + val = 1; + + #1 if (test1 !== 1'b1) begin + $display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1); + $finish; + end + + val = 1'bx; + + #1 if (test1 !== 1'bx) begin + $display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1); + $finish; + end + + val = 1'bz; + + #1 if (test1 !== 1'bz) begin + $display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1); + $finish; + end + + flag = 0; + val = 0; + + #1 if (test1 !== 1'bx) begin + $display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1); + $finish; + end + + if (test2 !== 1'bx) begin + $display("FAILED -- flag=%b, test2=%b", flag, test2); + $finish; + end + + if (test3 !== 1'b0) begin + $display("FAILED -- flag=%b, test3=%b", flag, test3); + $finish; + end + + val = 1; + + #1 if (test1 !== 1'bx) begin + $display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1); + $finish; + end + + if (test3 !== 1'b1) begin + $display("FAILED -- flag=%b, test3=%b", flag, test3); + $finish; + end + + val = 1'bx; + + #1 if (test3 !== 1'bx) begin + $display("FAILED -- flag=%b, val=%b, test3=%b", flag, val, test3); + $finish; + end + + val = 1'bz; + + #1 if (test3 !== 1'bz) begin + $display("FAILED -- flag=%b, val=%b, test3=%b", flag, val, test3); + $finish; + end + + $display("PASSED"); + $finish; + end // initial begin + +endmodule diff --git a/ivtest/ivltests/test_bufif0.v b/ivtest/ivltests/test_bufif0.v new file mode 100644 index 000000000..1ec36c4d9 --- /dev/null +++ b/ivtest/ivltests/test_bufif0.v @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2000 Intrinsity, Inc. + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test_bufif0 (); + +wire t0, t1, t2, t3, t4, t5, t6, t7, + t8, t9, ta, tb, tc, td, te, tf; + +reg gnd, vdd, x, z; +reg failed; + +wire StH, StL; + +assign (strong1, highz0) StH = 1'bx; +assign (highz1, strong0) StL = 1'bx; + +bufif0 n0 ( t0, gnd, gnd); +bufif0 n1 ( t1, gnd, vdd); +bufif0 n2 ( t2, gnd, x); +bufif0 n3 ( t3, gnd, z); + +bufif0 n4 ( t4, vdd, gnd); +bufif0 n5 ( t5, vdd, vdd); +bufif0 n6 ( t6, vdd, x); +bufif0 n7 ( t7, vdd, z); + +bufif0 n8 ( t8, x, gnd); +bufif0 n9 ( t9, x, vdd); +bufif0 na ( ta, x, x); +bufif0 nb ( tb, x, z); + +bufif0 nc ( tc, z, gnd); +bufif0 nd ( td, z, vdd); +bufif0 ne ( te, z, x); +bufif0 nf ( tf, z, z); + +initial begin + + assign gnd = 1'b1; + assign vdd = 1'b0; + assign x = 1'b0; + assign z = 1'b0; + #10; + + assign gnd = 1'b0; + assign vdd = 1'b1; + assign x = 1'b1; + assign z = 1'b1; + #10; + + assign gnd = 1'b0; + assign vdd = 1'b1; + assign x = 1'bx; + assign z = 1'bz; + #10; + + failed = 0; + + if (t0 !== gnd) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:0", gnd, gnd, t0 ); + end + + if (t1 !== z) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:z", gnd, vdd, t1 ); + end + if (t2 !== StL) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:StL", gnd, x, t2 ); + end + + if (t3 !== StL) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:StL", gnd, x, t3 ); + end + + if (t4 !== 1'b1) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:1", vdd, gnd, t4 ); + end + if (t5 !== z) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:z", vdd, vdd, t5 ); + end + if (t6 !== StH) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:StH", vdd, x, t6 ); + end + if (t7 !== StH) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:StH", vdd, x, t7 ); + end + + if (t8 !== 1'bx) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:x", x, gnd, t8 ); + end + if (t9 !== 1'bz) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:z", x, vdd, t9 ); + end + if (ta !== 1'bx) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:x", x, x, ta ); + end + if (tb !== 1'bx) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:x", x, z, tb ); + end + + if (tc !== 1'bx) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:x", z, gnd, tc ); + end + if (td !== 1'bz) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:z", z, vdd, td ); + end + if (te !== 1'bx) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:x", z, x, te ); + end + if (tf !== 1'bx) + begin + failed = 1; + $display ("FAILED: bufif0 s:%d g:%d d:%d expected:x", z, z, tf ); + end + + if (failed == 0) + $display ("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/test_bufif1.v b/ivtest/ivltests/test_bufif1.v new file mode 100644 index 000000000..5e88dedb9 --- /dev/null +++ b/ivtest/ivltests/test_bufif1.v @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2000 Intrinsity, Inc. + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test_bufif1 ( ); + +reg gnd, vdd, x, z; + +wire t0, t1, t2, t3, t4, t5, t6, t7, + t8, t9, ta, tb, tc, td, te, tf; + +reg failed; +wire StH, StL; + +assign (strong1, highz0) StH = 1'bx; +assign (highz1, strong0) StL = 1'bx; + +bufif1 b0 ( t0, gnd, gnd); +bufif1 b1 ( t1, gnd, vdd); +bufif1 b2 ( t2, gnd, x); +bufif1 b3 ( t3, gnd, z); + +bufif1 b4 ( t4, vdd, gnd); +bufif1 b5 ( t5, vdd, vdd); +bufif1 b6 ( t6, vdd, x); +bufif1 b7 ( t7, vdd, z); + +bufif1 b8 ( t8, x, gnd); +bufif1 b9 ( t9, x, vdd); +bufif1 ba ( ta, x, x); +bufif1 bb ( tb, x, z); + +bufif1 bc ( tc, z, gnd); +bufif1 bd ( td, z, vdd); +bufif1 be ( te, z, x); +bufif1 bf ( tf, z, z); + +initial begin + + // + // work around initial state assignment bug + failed = 0; + assign gnd = 1'b1; + assign vdd = 1'b0; + assign x = 1'b1; + assign z = 1'b1; + #10; + + assign gnd = 1'b0; + assign vdd = 1'b1; + assign x = 1'bx; + assign z = 1'bz; + #10; + + if (t0 !== z) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:z", gnd, gnd, t0 ); + end + + if (t1 !== 0) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:0", gnd, vdd, t1 ); + end + if (t2 !== StL) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:StL", gnd, x, t2 ); + end + if (t3 !== StL) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:StL", gnd, z, t3 ); + end + + if (t4 !== 1'bz) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:z", gnd, z, t4 ); + end + if (t5 !== 1) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:1", vdd, vdd, t5 ); + end + if (t6 !== StH) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:StH", vdd, x, t6 ); + end + if (t7 !== StH) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:StH", vdd, z, t7 ); + end + + if (t8 !== 1'bz) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:z", x, gnd, t8 ); + end + if (t9 !== 1'bx) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:x", x, vdd, t9 ); + end + if (ta !== 1'bx) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:x", x, x, ta ); + end + if (tb !== 1'bx) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:x", x, z, tb ); + end + + if (tc !== 1'bz) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:z", z, gnd, tc ); + end + if (td !== 1'bx) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:x", z, vdd, td ); + end + if (te !== 1'bx) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:x", z, x, te ); + end + if (tf !== 1'bx) + begin + failed = 1; + $display ("FAILED: bufif1 s:%d g:%d d:%d expected:x", z, z, tf ); + end + + if (failed == 0) + $display ("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/test_dec2to4.v b/ivtest/ivltests/test_dec2to4.v new file mode 100644 index 000000000..32b8cf0cc --- /dev/null +++ b/ivtest/ivltests/test_dec2to4.v @@ -0,0 +1,106 @@ +// This module generate enable and two-bit selector for verifying a 2-to-4 decoder + +module stimulus #(parameter M = 8, T = 10) ( + output reg [1:0] sel, + output reg en + ); + +bit [2:0] i; + +initial begin + sel = 0; + en = 1'bx; + #T; + sel = 1; + #T; + sel = 2; + #T; + sel = 3; + #T; + sel = 2'bxx; + #T; + en = 0; + #T; + en = 1; + #T; + en = 1'bx; + #T; + for (i = 0; i < M; i=i+1) begin + #T; + {sel, en} = i; + end + +end + + +endmodule + +// This module always checks that y complies with a decoding operation + +module check (input [1:0] sel, input en, input [0:3] y); + +always @(sel, en, y) begin + if (en == 0) begin + #1; + if (y !== 4'b0000) begin + $display("ERROR"); + $finish; + end + else if (en == 1) begin + #1; + case (sel) + 0: if (y !== 4'b1000) begin + $display("ERROR"); + $finish; + end + 1: if (y !== 4'b0100) begin + $display("ERROR"); + $finish; + end + 2: if (y !== 4'b0010) begin + $display("ERROR"); + $finish; + end + 3: if (y !== 4'b0001) begin + $display("ERROR"); + $finish; + end + default: if (y !== 4'b0000) begin + $display("ERROR"); + $finish; + end + endcase + end // else + else begin + if (y !== 4'b0000) begin + $display("ERROR"); + $finish; + end + end + end // if +end + +endmodule + + +module test; + parameter M = 8; + parameter T = 10; + parameter S = 4*M*T + 40; + + wire [1:0] sel; + wire en; + wire [0:3] y; + + + stimulus #(M, T) stim (.sel(sel), .en(en) ); + dec2to4 duv (.sel(sel), .en(en), .y(y) ); + check check (.sel(sel), .en(en), .y(y) ); + + initial begin + #S; + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/test_disphob.v b/ivtest/ivltests/test_disphob.v new file mode 100644 index 000000000..d915e3b54 --- /dev/null +++ b/ivtest/ivltests/test_disphob.v @@ -0,0 +1,73 @@ +// Released under GPL2.0 +// (c) 2002 Tom Verbeure + +module main; + + integer myInt; + reg [13:0] myReg14; + reg [7:0] myReg8; + reg [31:0] myReg32; + + initial begin + $display("============================ myReg14 = 65"); + myReg14 = 65; + + $display(">| 65|"); + $display("*|",myReg14,"|"); + $write("*|",myReg14,"|\n"); + + $display(">|0041|"); + $displayh("*|",myReg14,"|"); + $writeh("*|",myReg14,"|\n"); + + $display(">|00101|"); + $displayo("*|",myReg14,"|"); + $writeo("*|",myReg14,"|\n"); + + $display(">|00000001000001|"); + $displayb("*|",myReg14,"|"); + $writeb("*|",myReg14,"|\n"); + + $display("============================ myInt = -10"); + myInt = -10; + $display(">| -10|"); + $display("*|",myInt,"|"); + + $display(">|fffffff6|"); + $displayh("*|",myInt,"|"); + + $display(">|37777777766|"); + $displayo("*|",myInt,"|"); + + $display(">|11111111111111111111111111110110|"); + $displayb("*|",myInt,"|"); + + $display("============================ myReg32 = -10"); + myReg32 = -10; + $display(">|4294967286|"); + $display("*|",myReg32,"|"); + + $display(">|fffffff6|"); + $displayh("*|",myReg32,"|"); + + $display(">|37777777766|"); + $displayo("*|",myReg32,"|"); + + $display(">|11111111111111111111111111110110|"); + $displayb("*|",myReg32,"|"); + + $display("============================ myInt = 65"); + myInt = 65; + $display(">| 65|"); + $display("*|",myInt,"|"); + + $display(">|00000041|"); + $displayh("*|",myInt,"|"); + + $display(">|00000000101|"); + $displayo("*|",myInt,"|"); + + $display(">|00000000000000000000000001000001|"); + $displayb("*|",myInt,"|"); + end +endmodule diff --git a/ivtest/ivltests/test_dispwided.v b/ivtest/ivltests/test_dispwided.v new file mode 100644 index 000000000..901c7e95d --- /dev/null +++ b/ivtest/ivltests/test_dispwided.v @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test the display of very wide vectors in decimal. + */ +module test; + + reg signed [127:0] value; + + initial begin + value = 1; + while (value != 0) begin + $display("value=%d", value); + value = value << 1; + end + + value = -1; + while (value != 0) begin + $display("value=%d", value); + value = value << 1; + end + + end +endmodule // test diff --git a/ivtest/ivltests/test_enumsystem.v b/ivtest/ivltests/test_enumsystem.v new file mode 100644 index 000000000..8284969c7 --- /dev/null +++ b/ivtest/ivltests/test_enumsystem.v @@ -0,0 +1,107 @@ +/*************************************************************** +** Author: Oswaldo Cadenas (oswaldo.cadenas@gmail.com) +** Date: September 27 2011 +** +** Test: Intended to test the vhd code in enumsystem.vhd +** +** A stimulus modules generates a count 0,1,.., 7, 1 and an enable signal +** A scoreboard forces a check according to the operation found in enumsystem.vhd +** +** The test runs for sometime making sure relevant input conditions are met throughout +**************************************************************************************/ + +module stim (input clk, reset, output reg [2:0] count, output reg en); + + always @(posedge clk) begin + if (reset) count <= 3'b0; + else count <= count + 1; +end + + +initial begin + en = 1; + repeat (100) @(posedge clk); + en = 0; +end + +endmodule + +module scoreboard (input [2:0] count, input reset, en, input [0:3] y); + +initial begin + @(posedge reset); + @(negedge reset); // waiting for reset to become inactive + mycheck(); +end + +task mycheck; + forever begin + #1; + if (en == 0) begin + if (y !== 4'b0000) begin + $display ("ERROR"); + $finish; + end + end + else begin + #2; + case (count) + 0: if (y !== 4'b1000) begin + $display("ERROR"); + $finish; + end + 1: if (y !== 4'b0100) begin + $display("ERROR"); + $finish; + end + 2: if (y !== 4'b0010) begin + $display("ERROR"); + $finish; + end + 3: if (y !== 4'b0001) begin + $display("ERROR"); + $finish; + end + default: if (y !== 4'b1111 && en == 1) begin + $display("ERROR here, en = %d", en); + $finish; + end + endcase + end // else +end // always +endtask + +endmodule + + +module test; +parameter T = 10; +parameter S = 2*10*150; + +bit clk = 0, reset = 0; +wire en; +wire [2:0] count; +wire [0:3] y; + + +initial forever #(T) clk = !clk; + + initial begin + @(negedge clk); + reset = 1'b1; + repeat(6) @(negedge clk); + reset = 1'b0; + end + +stim stim (.clk(clk), .reset(reset), .en(en), .count(count) ); +enumsystem duv (.clk(clk), .reset(reset), .en(en), .y(y) ); +scoreboard check (.en(en), .reset(reset), .count(count), .y(y) ); + +initial begin + #S; + $display("PASSED"); + $finish; +end + + +endmodule diff --git a/ivtest/ivltests/test_extended.v b/ivtest/ivltests/test_extended.v new file mode 100644 index 000000000..6d84e35ef --- /dev/null +++ b/ivtest/ivltests/test_extended.v @@ -0,0 +1,113 @@ +// Released under GPL2.0 +// (c) 2002 Tom Verbeure + +module main; + + integer myInt; + reg [39:0] myReg40; + reg [0:39] myReg40r; + reg [0:38] myReg39r; + reg [13:0] myReg14; + reg [7:0] myReg8; + reg [31:0] myReg32; + + initial begin + $display("============================ myReg8 = 65"); + myReg8 = 65; + $display(">| 65|"); + $display("*|%d|", myReg8); + $display("*|",myReg8,"|"); + + + $display("============================ myReg14 = -10"); + myReg14 = -10; + $display(">|16374|"); + $display("*|%d|", myReg14); + $display("*|",myReg14,"|"); + + $display("============================ myReg14 = 65"); + myReg14 = 65; + $display(">1| 65|"); + $display("*1|%d|", myReg14); + $display(">2|65|"); + $display("*2|%0d|", myReg14); + $display(">3| 65|"); + $display("*3|%10d|", myReg14); + $display(">4| 65|"); + $display("*4|%08d|", myReg14); + $display("*4|%8d|", myReg14); + $display(">5| 65|"); + $display("*5|%03d|", myReg14); + $display("*5|%3d|", myReg14); + + $display("============================ myReg14 = 1000"); + myReg14 = 1000; + $display(">|1000|"); + $display("*|%03d|", myReg14); + + $finish(0); + + $display("*|",myReg14,"|"); + + $display(">|0041|"); + $display("*|%h|", myReg14); + $display(">|00000001000001|"); + $display("*|%b|", myReg14); + $display(">|41|"); + $display("*|%0h|", myReg14); + $display(">|1000001|"); + $display("*|%0b|", myReg14); + $display(">| A|"); + $display("*|%s|", myReg14); + $display(">|A|"); + $display("*|%0s|", myReg14); + + $display("============================ myInt = -10"); + myInt = -10; + $display(">| -10|"); + $display("*|%d|", myInt); + $display("*|",myInt,"|"); + + $display(">|fffffff6|"); + $display("*|%h|", myInt); + + $display("============================ myReg32 = -10"); + myReg32 = -10; + $display(">|4294967286|"); + $display("*|%d|", myReg32); + $display("*|",myReg32,"|"); + + $display(">|fffffff6|"); + $display("*|%h|", myReg32); + + $display("============================ myInt = 65"); + myInt = 65; + $display(">| 65|"); + $display("*|%d|", myInt); + $display("*|",myInt,"|"); + $display("*| A|"); + $display(">|%s|", myInt); + $display("*|A|"); + $display(">|%0s|", myInt); + + $display("============================ myReg32 = 65"); + myReg32 = 65; + $display(">| 65|"); + $display("*|%d|", myReg32); + $display("*|",myReg32,"|"); + $display("*| A|"); + $display(">|%s|", myReg32); + $display("*|A|"); + $display(">|%0s|", myReg32); + + $display("*| A|"); + $display(">|%s|", " A"); + $display("*| A|"); + $display(">|%0s|", " A"); + + $display("*|0|"); + $display(">|%0t|", $time); + $display("*| 0|"); + $display(">|%t|", $time); + end +endmodule diff --git a/ivtest/ivltests/test_forgen.v b/ivtest/ivltests/test_forgen.v new file mode 100644 index 000000000..ba15985ad --- /dev/null +++ b/ivtest/ivltests/test_forgen.v @@ -0,0 +1,30 @@ +module main; + + parameter WIDTH = 8; + parameter ITERATIONS = 1000; + + reg [WIDTH-1:0] src0, src1, ref_dst; + reg clk; + wire [WIDTH-1:0] dst; + + test #(.width(WIDTH)) test0 (.dst(dst), .src0(src0), .src1(src1), .clk(clk)); + + integer idx; + initial begin + clk = 0; + for (idx = 0 ; idx < ITERATIONS ; idx = idx+1) begin + src0 = $random; + src1 = $random; + ref_dst = src0 ^ src1; + #1 clk = 1; + #1 if (dst !== ref_dst) begin + $display("FAILED: src0=%b, src1=%b dst=%b, ref=%b", + src0, src1, dst, ref_dst); + $finish; + end + clk = 0; + end + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/test_gxor.v b/ivtest/ivltests/test_gxor.v new file mode 100644 index 000000000..0e215202e --- /dev/null +++ b/ivtest/ivltests/test_gxor.v @@ -0,0 +1,59 @@ +// This module generate M single 2*HW-1 bit vector each T time steps + +module stimulus #(parameter HW = 4, T = 10, M = 200) ( + output reg [2*HW-1:0] a + ); + +int i; +int MAX; + + +initial begin + MAX = 1 << 2*HW; + for (i = 0; i < M; i=i+1) begin + a = $random % MAX ; + #T; + end + +end + + +endmodule + +// This module always checks that y complies with an XOR reduction operation on 2*HW-1 bits input as x + +module check #(parameter HW = 4) (input [2*HW-1:0] x, input y); + +wire yi = ^x; + +always @(y, yi) begin + #1; + if (y !== yi) begin + $display("ERROR"); + $finish; + end +end + +endmodule + + +module test; + parameter M = 200; // number of test vectors + parameter T = 10; // time step unit + parameter HW = 4; // bit width of input vecotrs + parameter S = M*T + 40; + + wire [2*HW-1:0] a; + wire y; + + stimulus #(HW, T, M) stim (.a(a)); + gxor_reduce #(HW) duv (.a(a), .ar(y)); + check check (.x(a), .y(y) ); + + initial begin + #S; + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/test_inc_dec.v b/ivtest/ivltests/test_inc_dec.v new file mode 100644 index 000000000..14a57eae3 --- /dev/null +++ b/ivtest/ivltests/test_inc_dec.v @@ -0,0 +1,403 @@ +/* + * Author: Oswaldo Cadenas + */ +module test; + +parameter S = 9; +parameter K = 3; +parameter L = 2**(S-K); +parameter N = 2**(S-1); + +reg signed [S-1:0] a_reg; +bit signed [S-1:0] a_bit; +byte signed a_byte; +shortint signed a_short; +int signed a_int; +longint signed a_long; +byte signed amount; +byte unsigned pos; +int temp; +int i; + +initial begin + // test for style "a += some" statement on type reg + for (i = 0; i < N; i = i+1) begin + a_reg = $random % L; + amount = $random % K; + #1; + temp = a_reg + amount; + a_reg += amount; + #1; + //$display ("a = %0d, amount = %0d, temp = %0d", a, amount, temp); + if (temp !== a_reg) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_reg - amount; + a_reg -= amount; + #1; + if (temp !== a_reg) begin + $display("FAILED"); + $finish; + end + end + + // test for style "a += some" statement on type bit + for (i = 0; i < N; i = i+1) begin + a_bit = $random % L; + amount = $random % K; + #1; + temp = a_bit + amount; + a_bit += amount; + #1; + if (temp !== a_bit) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_bit - amount; + a_bit -= amount; + #1; + if (temp !== a_bit) begin + $display("FAILED"); + $finish; + end + end // for + + // test for style "a += some" statement on type byte + for (i = 0; i < N; i = i+1) begin + a_byte = $random % L; + amount = $random % K; + #1; + temp = a_byte + amount; + a_byte += amount; + #1; + if (temp !== a_byte) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_byte - amount; + a_byte -= amount; + #1; + if (temp !== a_byte) begin + $display("FAILED"); + $finish; + end + end // for + + // test for style "a += some" statement on type shortint + for (i = 0; i < N; i = i+1) begin + a_short = 2*($random % L); + amount = 2*($random % K); + #1; + temp = a_short + amount; + a_short += amount; + #1; + if (temp !== a_short) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_short - amount; + a_short -= amount; + #1; + if (temp !== a_short) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_short * amount; + a_short *= amount; + #1; + if (temp !== a_short) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_short / amount; + a_short /= amount; + #1; + if (temp !== a_short) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_short % amount; + a_short %= amount; + #1; + if (temp !== a_short) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_short & amount; + a_short &= amount; + #1; + if (temp !== a_short) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_short | amount; + a_short |= amount; + #1; + if (temp !== a_short) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_short ^ amount; + a_short ^= amount; + #1; + if (temp !== a_short) begin + $display("FAILED"); + $finish; + end + #1; + pos = 2*({$random} % K); + temp = a_short << pos; + a_short <<= pos; + #1; + if (temp !== a_short) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_short >> pos; + a_short >>= pos; + #1; + if (temp !== a_short) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_short <<< pos; + a_short <<<= pos; + #1; + if (temp !== a_short) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_short >>> pos; + a_short >>>= pos; + #1; + if (temp !== a_short) begin + $display("FAILED"); + $finish; + end + end // for + + // test for style "a += some" statement on type int + for (i = 0; i < N; i = i+1) begin + a_int = 4*($random % L); + amount = 4*($random % K); + #1; + temp = a_int + amount; + a_int += amount; + #1; + if (temp !== a_int) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_int - amount; + a_int -= amount; + #1; + if (temp !== a_int) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_int * amount; + a_int *= amount; + #1; + if (temp !== a_int) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_int / amount; + a_int /= amount; + #1; + if (temp !== a_int) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_int % amount; + a_int %= amount; + #1; + if (temp !== a_int) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_int & amount; + a_int &= amount; + #1; + if (temp !== a_int) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_int | amount; + a_int |= amount; + #1; + if (temp !== a_int) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_int ^ amount; + a_int ^= amount; + #1; + if (temp !== a_int) begin + $display("FAILED"); + $finish; + end + #1; + pos = 4*({$random} % K); + temp = a_int << pos; + a_int <<= pos; + #1; + if (temp !== a_int) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_int >> pos; + a_int >>= pos; + #1; + if (temp !== a_int) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_int <<< pos; + a_int <<<= pos; + #1; + if (temp !== a_int) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_int >>> pos; + a_int >>= pos; + #1; + if (temp !== a_int) begin + $display("FAILED"); + $finish; + end + end // for + + // test for style "a += some" statement on type longint + for (i = 0; i < N; i = i+1) begin + a_long = 8*($random % L); + amount = 8*($random % K); + #1; + temp = a_long + amount; + a_long += amount; + #1; + if (temp !== a_long) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_long - amount; + a_long -= amount; + #1; + if (temp !== a_long) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_long * amount; + a_long *= amount; + #1; + if (temp !== a_long) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_long / amount; + a_long /= amount; + #1; + if (temp !== a_long) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_long % amount; + a_long %= amount; + #1; + if (temp !== a_long) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_long & amount; + a_long &= amount; + #1; + if (temp !== a_long) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_long | amount; + a_long |= amount; + #1; + if (temp !== a_long) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_long ^ amount; + a_long ^= amount; + #1; + if (temp !== a_long) begin + $display("FAILED"); + $finish; + end + #1; + pos = 8*({$random} % K); + temp = a_long << pos; + a_long <<= pos; + #1; + if (temp !== a_long) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_long >> pos; + a_long >>= pos; + #1; + if (temp !== a_long) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_long <<< pos; + a_long <<<= pos; + #1; + if (temp !== a_long) begin + $display("FAILED"); + $finish; + end + #1; + temp = a_long >>> pos; + a_long >>= pos; + #1; + if (temp !== a_long) begin + $display("FAILED"); + $finish; + end + end // for + + $display("PASSED"); + $finish; +end + +endmodule diff --git a/ivtest/ivltests/test_mos_strength_reduction.v b/ivtest/ivltests/test_mos_strength_reduction.v new file mode 100644 index 000000000..f9a0aa47d --- /dev/null +++ b/ivtest/ivltests/test_mos_strength_reduction.v @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2000 Intrinsity, Inc. + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module rpull ( i, o); +input i; +output o; + +wire gnd; +wire vdd; +wire pu0; +wire pu1; + +reg failed; + +assign gnd = 1'b0; +assign vdd = 1'b1; + +assign (pull0,pull1) pu0 = 1'b0; +assign (pull0,pull1) pu1 = 1'b1; + +rnmos n0 ( o, gnd, i); +rpmos p0 ( o, vdd, i); + +initial begin +#1; + failed = 0; + if (i === vdd) + if (o !== pu0) begin + $display ("FAILED: test_mos_strength_reduction: case pull i:%d o:%d pu0:%d", i, o, pu0); + failed = 1; + end + + else if (i === gnd) + if (o !== pu1) begin + $display ("FAILED: test_mos_strength_reduction: case pull i:%d o:%d pu0:%d", i, o, pu0); + failed = 1; + end + else begin + $display ("FAILED: test_mos_strength_reduction: case pull i:%d o:%d pu0:%d", i, o, pu0); + failed = 1; + end + + if ( ! failed ) + $display ("PASSED"); +end +endmodule + +module rweak (i, o); +input i; +output o; + +wire gnd; +wire vdd; +wire we0; +wire we1; + +reg failed; + +assign gnd = 1'b0; +assign vdd = 1'b1; + +assign (weak0,weak1) we0 = 1'b0; +assign (weak0,weak1) we1 = 1'b1; + +rnmos rn0 ( n0, gnd, i); +rnmos rn1 ( o, n0, i); +rpmos rp1 ( o, p0, i); +rpmos rp0 ( p0, vdd, i); + +initial begin +#1; + failed = 0; + if (i === vdd) + if (o !== we0) begin + $display ("FAILED: test_mos_strength_reduction: case weak i:%d o:%d pu0:%d", i, o, we0); + failed = 1; + end + + else if (i === gnd) + if (o !== we1) begin + $display ("FAILED: test_mos_strength_reduction: case weak i:%d o:%d pu0:%d", i, o, we0); + failed = 1; + end + else begin + $display ("FAILED: test_mos_strength_reduction: case weak i:%d o:%d pu0:%d", i, o, we0); + failed = 1; + end + + if ( ! failed ) + $display ("PASSED: test_mos_strength_reduction: case rweak"); +end +endmodule +module test_mos_strength_reduction; /* beginning of _testbench */ + +reg vdd; +reg gnd; + +reg c0,c1; +reg failed; + +wire n0,p0; +wire n1,p1; +wire n2,p2; +wire n3,p3; +wire n4,p4; + +wire st1st0; +wire pu1pu0; +wire we1pu0; +wire me1pu0; +wire sm1pu0; + +wire o0; +wire o1; + +assign (strong1, strong0) st1st0 = 1'b1; +assign (strong1, strong0) st1st0 = 1'b0; + +assign (pull1, pull0) pu1pu0 = 1'b1; +assign (pull1, pull0) pu1pu0 = 1'b0; + +assign (weak1, weak0) we1pu0 = 1'b1; +assign (pull1, pull0) we1pu0 = 1'b0; + +rpull pu0 (vdd,o0); +rweak we0 (vdd,o1); + +rnmos rn_0 (n1,gnd,c0); +rnmos rn_1 (n2,n1,c0); +rnmos rn_2 (n3,n2,c0); +rnmos rn_3 (n4,n3,c0); +rnmos rn_4 ( o,n4,c0); +rpmos rp_0 (p0,vdd,c1); +rpmos rp_1 (p1,p0,c1); +rpmos rp_2 (p2,p1,c1); +rpmos rp_3 (p3,p2,c1); +rpmos rp_4 ( o,p3,c1); + + +initial begin + failed = 0; + vdd = 1'b1; + gnd = 1'b0; +#1; + c0 = 1'b1; + c1 = 1'b1; +#1; + if (o !== gnd ) begin + $display ("FAILED: test_mos_strength_reduction: case 0"); + failed = 1; + end +#1; + c0 = 1'b0; + c1 = 1'b0; +#1; + if (o !== vdd ) begin + $display ("FAILED: test_mos_strength_reduction: case 1"); + failed = 1; + end +#1; + c0 = 1'b1; + c1 = 1'b0; +#1; + if (o !== 1'bx ) begin + $display ("FAILED: test_mos_strength_reduction: case x"); + failed = 1; + end + if (! failed ) + $display ("PASSED: test_mos_strength_reduction"); +#1; +end +endmodule diff --git a/ivtest/ivltests/test_mux2to1.v b/ivtest/ivltests/test_mux2to1.v new file mode 100644 index 000000000..3c5bde8aa --- /dev/null +++ b/ivtest/ivltests/test_mux2to1.v @@ -0,0 +1,58 @@ +// This module generate all 8 inputs for three boolean variables + +module stimulus #(parameter M = 8, T = 10) ( + output reg i0, i1, + output reg s + ); + +bit [2:0] i; + +initial begin + for (i = 0; i < M; i=i+1) begin + #T; + {i0, i1, s} = i; + end + #T; +end + + +endmodule + +// This module always checks the internal generated muxed output complies with the received one + +module check (input i0, i1, s, y); + +logic y_check; + +always @(i0, i1, s) + y_check = s ? i1 : i0; + +always @(y, y_check) begin + #1 if (y != y_check) begin + $display("ERROR"); + $finish; + end +end + +endmodule + + +module test; + parameter M = 8; + parameter T = 10; + parameter S = (M+1)*T + 40; + + wire i0, i1, s, y; + + + stimulus #(M, T) stim (.i0(i0), .i1(i1), .s(s) ); + mux2to1 duv (.i0(i0), .i1(i1), .s(s), .y(y) ); + check check (.i0(i0), .i1(i1), .s(s), .y(y) ); + + initial begin + #S; + $display("PASSED"); + $finish; + end + +endmodule diff --git a/ivtest/ivltests/test_nmos.v b/ivtest/ivltests/test_nmos.v new file mode 100644 index 000000000..7b8e7287e --- /dev/null +++ b/ivtest/ivltests/test_nmos.v @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2000 Intrinsity, Inc. + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test_nmos (); + +wire t0, t1, t2, t3, t4, t5, t6, t7, + t8, t9, ta, tb, tc, td, te, tf; + +reg gnd, vdd, x, z; +reg failed; + +wire StH, StL; + +assign (strong1, highz0) StH = 1'bx; +assign (highz1, strong0) StL = 1'bx; + +nmos n0 ( t0, gnd, gnd); +nmos n1 ( t1, gnd, vdd); +nmos n2 ( t2, gnd, x); +nmos n3 ( t3, gnd, z); + +nmos n4 ( t4, vdd, gnd); +nmos n5 ( t5, vdd, vdd); +nmos n6 ( t6, vdd, x); +nmos n7 ( t7, vdd, z); + +nmos n8 ( t8, x, gnd); +nmos n9 ( t9, x, vdd); +nmos na ( ta, x, x); +nmos nb ( tb, x, z); + +nmos nc ( tc, z, gnd); +nmos nd ( td, z, vdd); +nmos ne ( te, z, x); +nmos nf ( tf, z, z); + +initial begin + + + + assign gnd = 1'b1; + assign vdd = 1'b0; + assign x = 1'b0; + assign z = 1'b0; + #10; + + assign gnd = 1'b0; + assign vdd = 1'b1; + assign x = 1'b1; + assign z = 1'b1; + #10; + + assign gnd = 1'b0; + assign vdd = 1'b1; + assign x = 1'bx; + assign z = 1'bz; + #10; + + failed = 0; + + if (t0 !== z) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:z", gnd, gnd, t0 ); + end + + if (t1 !== 0) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:0", gnd, vdd, t1 ); + end + if (t2 !== StL) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:StL", gnd, x, t2 ); + end + if (t3 !== StL) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:StL", gnd, z, t3 ); + end + + if (t4 !== 1'bz) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:z", vdd, gnd, t4 ); + end + if (t5 !== 1) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:0", vdd, vdd, t5 ); + end + if (t6 !== StH) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:StH", vdd, x, t6 ); + end + if (t7 !== StH) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:StH", vdd, z, t7 ); + end + + if (t8 !== 1'bz) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:z", x, gnd, t8 ); + end + if (t9 !== 1'bx) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:x", x, vdd, t9 ); + end + if (ta !== 1'bx) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:x", x, x, ta ); + end + if (tb !== 1'bx) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:x", x, z, tb ); + end + + if (tc !== 1'bz) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, gnd, tc ); + end + if (td !== 1'bz) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, vdd, td ); + end + if (te !== 1'bz) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, x, te ); + end + if (tf !== 1'bz) + begin + failed = 1; + $display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, z, tf ); + end + + if (failed == 0) + $display ("PASSED"); + +end +endmodule diff --git a/ivtest/ivltests/test_notif0.v b/ivtest/ivltests/test_notif0.v new file mode 100644 index 000000000..9d26d7539 --- /dev/null +++ b/ivtest/ivltests/test_notif0.v @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2000 Intrinsity, Inc. + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test_notif0 (); + +reg gnd, vdd, x, z; +wire t0, t1, t2, t3, t4, t5, t6, t7, + t8, t9, ta, tb, tc, td, te, tf; + +reg failed; + +wire StH, StL; + +assign (strong1, highz0) StH = 1'bx; +assign (highz1, strong0) StL = 1'bx; + + +notif0 n0 ( t0, gnd, gnd); +notif0 n1 ( t1, gnd, vdd); +notif0 n2 ( t2, gnd, x); +notif0 n3 ( t3, gnd, z); + +notif0 n4 ( t4, vdd, gnd); +notif0 n5 ( t5, vdd, vdd); +notif0 n6 ( t6, vdd, x); +notif0 n7 ( t7, vdd, z); + +notif0 n8 ( t8, x, gnd); +notif0 n9 ( t9, x, vdd); +notif0 na ( ta, x, x); +notif0 nb ( tb, x, z); + +notif0 nc ( tc, z, gnd); +notif0 nd ( td, z, vdd); +notif0 ne ( te, z, x); +notif0 nf ( tf, z, z); + +initial begin + + assign gnd = 1'b1; + assign vdd = 1'b0; + assign x = 1'b0; + assign z = 1'b0; + #10; + + assign gnd = 1'b0; + assign vdd = 1'b1; + assign x = 1'b1; + assign z = 1'b1; + #10; + + assign gnd = 1'b0; + assign vdd = 1'b1; + assign x = 1'bx; + assign z = 1'bz; + #10; + + failed = 0; + + if (t0 !== vdd) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:1", gnd, gnd, t0 ); + end + + if (t1 !== z) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:z", gnd, vdd, t1 ); + end + if (t2 !== StH) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:StH", gnd, x, t2 ); + end + if (t3 !== StH) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:StH", gnd, z, t3 ); + end + + if (t4 !== 1'b0) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:0", vdd, gnd, t4 ); + end + if (t5 !== z) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:z", vdd, vdd, t5 ); + end + if (t6 !== StL) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:Stl", vdd, x, t6 ); + end + if (t7 !== StL) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:Stl", vdd, z, t7 ); + end + + if (t8 !== 1'bx) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:x", x, gnd, t8 ); + end + if (t9 !== 1'bz) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:z", x, vdd, t9 ); + end + if (ta !== 1'bx) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:x", x, x, ta ); + end + if (tb !== 1'bx) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:x", x, z, tb ); + end + + if (tc !== 1'bx) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:x", z, gnd, tc ); + end + if (td !== 1'bz) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:z", z, vdd, td ); + end + if (te !== 1'bx) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:x", z, x, te ); + end + if (tf !== 1'bx) + begin + failed = 1; + $display ("FAILED: notif0 s:%d g:%d d:%d expected:x", z, z, tf ); + end + + if (failed == 0) + $display ("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/test_notif1.v b/ivtest/ivltests/test_notif1.v new file mode 100644 index 000000000..9d997bc2b --- /dev/null +++ b/ivtest/ivltests/test_notif1.v @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2000 Intrinsity, Inc. + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test_notif1 ( ); + +reg gnd, vdd, x, z; + +wire t0, t1, t2, t3, t4, t5, t6, t7, + t8, t9, ta, tb, tc, td, te, tf; + +reg failed; + +wire StH, StL; + +assign (strong1, highz0) StH = 1'bx; +assign (highz1, strong0) StL = 1'bx; + +notif1 b0 ( t0, gnd, gnd); +notif1 b1 ( t1, gnd, vdd); +notif1 b2 ( t2, gnd, x); +notif1 b3 ( t3, gnd, z); + +notif1 b4 ( t4, vdd, gnd); +notif1 b5 ( t5, vdd, vdd); +notif1 b6 ( t6, vdd, x); +notif1 b7 ( t7, vdd, z); + +notif1 b8 ( t8, x, gnd); +notif1 b9 ( t9, x, vdd); +notif1 ba ( ta, x, x); +notif1 bb ( tb, x, z); + +notif1 bc ( tc, z, gnd); +notif1 bd ( td, z, vdd); +notif1 be ( te, z, x); +notif1 bf ( tf, z, z); + +initial begin + + // + // work around initial state assignment bug + failed = 0; + assign gnd = 1'b1; + assign vdd = 1'b0; + assign x = 1'b1; + assign z = 1'b1; + #10; + + assign gnd = 1'b0; + assign vdd = 1'b1; + assign x = 1'bx; + assign z = 1'bz; + #10; + + if (t0 !== z) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:z", gnd, gnd, t0 ); + end + + if (t1 !== 1) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:1", gnd, vdd, t1 ); + end + if (t2 !== StH) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:StH", gnd, x, t2 ); + end + if (t3 !== StH) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:StH", gnd, z, t3 ); + end + + if (t4 !== 1'bz) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:z", vdd, gnd, t4 ); + end + if (t5 !== 0) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:0", vdd, vdd, t5 ); + end + if (t6 !== StL) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:StL", vdd, x, t6 ); + end + if (t7 !== StL) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:StL", vdd, z, t7 ); + end + + if (t8 !== 1'bz) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:z", x, gnd, t8 ); + end + if (t9 !== 1'bx) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:x", x, vdd, t9 ); + end + if (ta !== 1'bx) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:x", x, x, ta ); + end + if (tb !== 1'bx) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:x", x, z, tb ); + end + + if (tc !== 1'bz) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:z", z, gnd, tc ); + end + if (td !== 1'bx) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:x", z, vdd, td ); + end + if (te !== 1'bx) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:x", z, x, te ); + end + if (tf !== 1'bx) + begin + failed = 1; + $display ("FAILED: notif1 s:%d g:%d d:%d expected:x", z, z, tf ); + end + + if (failed == 0) + $display ("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/test_pmos.v b/ivtest/ivltests/test_pmos.v new file mode 100644 index 000000000..9dd314275 --- /dev/null +++ b/ivtest/ivltests/test_pmos.v @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2000 Intrinsity, Inc. + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test_pmos (); + +reg gnd, vdd, x, z; +wire t0, t1, t2, t3, t4, t5, t6, t7, + t8, t9, ta, tb, tc, td, te, tf; + +wire StH, StL; + +assign (strong1, highz0) StH = 1'bx; +assign (highz1, strong0) StL = 1'bx; + +reg failed; + + +pmos n0 ( t0, gnd, gnd); +pmos n1 ( t1, gnd, vdd); +pmos n2 ( t2, gnd, x); +pmos n3 ( t3, gnd, z); + +pmos n4 ( t4, vdd, gnd); +pmos n5 ( t5, vdd, vdd); +pmos n6 ( t6, vdd, x); +pmos n7 ( t7, vdd, z); + +pmos n8 ( t8, x, gnd); +pmos n9 ( t9, x, vdd); +pmos na ( ta, x, x); +pmos nb ( tb, x, z); + +pmos nc ( tc, z, gnd); +pmos nd ( td, z, vdd); +pmos ne ( te, z, x); +pmos nf ( tf, z, z); + +initial begin + + assign gnd = 1'b1; + assign vdd = 1'b0; + assign x = 1'b0; + assign z = 1'b0; + #10; + + assign gnd = 1'b0; + assign vdd = 1'b1; + assign x = 1'b1; + assign z = 1'b1; + #10; + + assign gnd = 1'b0; + assign vdd = 1'b1; + assign x = 1'bx; + assign z = 1'bz; + #10; + + failed = 0; + + if (t0 !== gnd) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:0", gnd, gnd, t0 ); + end + + if (t1 !== z) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:z", gnd, vdd, t1 ); + end + if (t2 !== StL) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:StL", gnd, x, t2 ); + end + if (t3 !== StL) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:StL", gnd, z, t3 ); + end + + if (t4 !== 1'b1) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:1", vdd, gnd, t4 ); + end + if (t5 !== z) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:z", vdd, vdd, t5 ); + end + if (t6 !== StH) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:StH", vdd, x, t6 ); + end + if (t7 !== StH) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:StH", vdd, z, t7 ); + end + + if (t8 !== 1'bx) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:x", x, gnd, t8 ); + end + if (t9 !== 1'bz) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:z", x, vdd, t9 ); + end + if (ta !== 1'bx) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:x", x, x, ta ); + end + if (tb !== 1'bx) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:x", x, z, tb ); + end + + if (tc !== 1'bz) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:z", z, gnd, tc ); + end + if (td !== 1'bz) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:z", z, vdd, td ); + end + if (te !== 1'bz) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:z", z, x, te ); + end + if (tf !== 1'bz) + begin + failed = 1; + $display ("FAILED: pmos s:%d g:%d d:%d expected:z", z, z, tf ); + end + + if (failed == 0) + $display ("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/test_rnmos.v b/ivtest/ivltests/test_rnmos.v new file mode 100644 index 000000000..a759bb0eb --- /dev/null +++ b/ivtest/ivltests/test_rnmos.v @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2000 Intrinsity, Inc. + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test_rnmos (); + +reg gnd, vdd, x, z; +wire t0, t1, t2, t3, t4, t5, t6, t7, + t8, t9, ta, tb, tc, td, te, tf; + +wire StH, StL; + +assign (strong1, highz0) StH = 1'bx; +assign (highz1, strong0) StL = 1'bx; + +reg failed; + + +rnmos n0 ( t0, gnd, gnd); +rnmos n1 ( t1, gnd, vdd); +rnmos n2 ( t2, gnd, x); +rnmos n3 ( t3, gnd, z); + +rnmos n4 ( t4, vdd, gnd); +rnmos n5 ( t5, vdd, vdd); +rnmos n6 ( t6, vdd, x); +rnmos n7 ( t7, vdd, z); + +rnmos n8 ( t8, x, gnd); +rnmos n9 ( t9, x, vdd); +rnmos na ( ta, x, x); +rnmos nb ( tb, x, z); + +rnmos nc ( tc, z, gnd); +rnmos nd ( td, z, vdd); +rnmos ne ( te, z, x); +rnmos nf ( tf, z, z); + +initial begin + + assign gnd = 1'b1; + assign vdd = 1'b0; + assign x = 1'b0; + assign z = 1'b0; + #10; + + assign gnd = 1'b0; + assign vdd = 1'b1; + assign x = 1'b1; + assign z = 1'b1; + #10; + + assign gnd = 1'b0; + assign vdd = 1'b1; + assign x = 1'bx; + assign z = 1'bz; + #10; + + failed = 0; + + if (t0 !== z) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:z", gnd, gnd, t0 ); + end + + if (t1 !== 0) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:0", gnd, vdd, t1 ); + end + if (t2 !== StL) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:StL", gnd, x, t2 ); + end + if (t3 !== StL) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:StL", gnd, z, t3 ); + end + + if (t4 !== 1'bz) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:z", vdd, gnd, t4 ); + end + if (t5 !== 1) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:0", vdd, vdd, t5 ); + end + if (t6 !== StH) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:StH", vdd, x, t6 ); + end + if (t7 !== StH) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:StH", vdd, z, t7 ); + end + + if (t8 !== 1'bz) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:z", x, gnd, t8 ); + end + if (t9 !== 1'bx) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:x", x, vdd, t9 ); + end + if (ta !== 1'bx) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:x", x, x, ta ); + end + if (tb !== 1'bx) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:x", x, z, tb ); + end + + if (tc !== 1'bz) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:z", z, gnd, tc ); + end + if (td !== 1'bz) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:z", z, vdd, td ); + end + if (te !== 1'bz) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:z", z, x, te ); + end + if (tf !== 1'bz) + begin + failed = 1; + $display ("FAILED: rnmos s:%d g:%d d:%d expected:z", z, z, tf ); + end + + if (failed == 0) + $display ("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/test_rpmos.v b/ivtest/ivltests/test_rpmos.v new file mode 100644 index 000000000..cafc1c8db --- /dev/null +++ b/ivtest/ivltests/test_rpmos.v @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2000 Intrinsity, Inc. + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test_rpmos (); + +reg gnd, vdd, x, z; +wire t0, t1, t2, t3, t4, t5, t6, t7, + t8, t9, ta, tb, tc, td, te, tf; + +wire StH, StL; + +assign (strong1, highz0) StH = 1'bx; +assign (highz1, strong0) StL = 1'bx; + +reg failed; + + +rpmos n0 ( t0, gnd, gnd); +rpmos n1 ( t1, gnd, vdd); +rpmos n2 ( t2, gnd, x); +rpmos n3 ( t3, gnd, z); + +rpmos n4 ( t4, vdd, gnd); +rpmos n5 ( t5, vdd, vdd); +rpmos n6 ( t6, vdd, x); +rpmos n7 ( t7, vdd, z); + +rpmos n8 ( t8, x, gnd); +rpmos n9 ( t9, x, vdd); +rpmos na ( ta, x, x); +rpmos nb ( tb, x, z); + +rpmos nc ( tc, z, gnd); +rpmos nd ( td, z, vdd); +rpmos ne ( te, z, x); +rpmos nf ( tf, z, z); + +initial begin + + assign gnd = 1'b1; + assign vdd = 1'b0; + assign x = 1'b0; + assign z = 1'b0; + #10; + + assign gnd = 1'b0; + assign vdd = 1'b1; + assign x = 1'b1; + assign z = 1'b1; + #10; + + assign gnd = 1'b0; + assign vdd = 1'b1; + assign x = 1'bx; + assign z = 1'bz; + #10; + + failed = 0; + + if (t0 !== gnd) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:0", gnd, gnd, t0 ); + end + + if (t1 !== z) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:z", gnd, vdd, t1 ); + end + if (t2 !== StL) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:StL", gnd, x, t2 ); + end + if (t3 !== StL) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:StL", gnd, z, t3 ); + end + + if (t4 !== 1'b1) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:1", vdd, gnd, t4 ); + end + if (t5 !== z) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:z", vdd, vdd, t5 ); + end + if (t6 !== StH) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:StH", vdd, x, t6 ); + end + if (t7 !== StH) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:StH", vdd, z, t7 ); + end + + if (t8 !== 1'bx) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:x", x, gnd, t8 ); + end + if (t9 !== 1'bz) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:z", x, vdd, t9 ); + end + if (ta !== 1'bx) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:x", x, x, ta ); + end + if (tb !== 1'bx) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:x", x, z, tb ); + end + + if (tc !== 1'bz) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:z", z, gnd, tc ); + end + if (td !== 1'bz) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:z", z, vdd, td ); + end + if (te !== 1'bz) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:z", z, x, te ); + end + if (tf !== 1'bz) + begin + failed = 1; + $display ("FAILED: rpmos s:%d g:%d d:%d expected:z", z, z, tf ); + end + + if (failed == 0) + $display ("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/test_signal_init_assign.v b/ivtest/ivltests/test_signal_init_assign.v new file mode 100644 index 000000000..41e3433a2 --- /dev/null +++ b/ivtest/ivltests/test_signal_init_assign.v @@ -0,0 +1,50 @@ +module main; + + reg src; + reg clk; + wire dst0, dst1; + +test #(.parm(0)) test0 (.dst(dst0), .src(src), .clk(clk)); +test #(.parm(1)) test1 (.dst(dst1), .src(src), .clk(clk)); + +//Note: For Modelsim compatibility do instantiation as: +//test #(.parm(2'b10)) test0 (.dst(dst0), .src(src), .clk(clk)); +//test #(.parm(2'b11)) test1 (.dst(dst1), .src(src), .clk(clk)); +//The reason is that Modelsim handles single-bit std_logic as an +//enumeration, and enumeration values 2 and 3 correspond to the +//stdlogic '0' and '1' values. The integer to std_logic values +//in modelsim are: + // 0 - 'U' + // 1 - 'X' + // 2 - '0' + // 3 - '1' + // 4 - 'Z' + // 5 - 'W' + // 6 - 'L' + // 7 - 'H' + // 8 - '-' +//Maybe in the future we'll have to do something similar? + + + initial begin + clk = 0; + src = 0; + #1 clk = 1; + #1 if (dst0 !== 1'b0 || dst1 !== 1'b1) begin + $display("FAILED: src=%b, dst0=%b dst1=%b", src, dst0, dst1); + $finish; + end + clk = 0; + src = 1; + #1 clk = 1; + #1 if (dst0 !== 1'b1 || dst1 !== 1'b0) begin + $display("FAILED: src=%b, dst0=%b dst1=%b", src, dst0, dst1); + $finish; + end + $display("PASSED"); + end // initial begin + + + + +endmodule // main diff --git a/ivtest/ivltests/test_system.v b/ivtest/ivltests/test_system.v new file mode 100644 index 000000000..c9934f883 --- /dev/null +++ b/ivtest/ivltests/test_system.v @@ -0,0 +1,53 @@ +/*************************************************************** +** Author: Oswaldo Cadenas (oswaldo.cadenas@gmail.com) +** Date: September 26 2011 +** +** Test: Intended to test a system composed of some parametric system +** that has an adder, a register and an incrementer +** Each module has parameter: N for data length +** +** A system is given parameter P and should return P-1, this is run for M test vectors +**************************************************************************************/ + +module test; +parameter integer T = 25; // for the clock period +parameter integer P = 1000; // a constant passed to the system under test +parameter integer M = 200; // number of test vectors + +int i; + +bit clk = 0, reset = 0; + +byte unsigned x; +wire [10:0] y; + +initial forever #(T) clk = !clk; + +initial begin + @(negedge clk); + reset = 1'b1; + repeat(6) @(negedge clk); + reset = 1'b0; +end + +initial begin + @(posedge reset); + @(negedge reset); + for (i = 0; i < M; i=i+1) begin + x = {$random} % 255; + @(negedge clk); + if (y !== P-1) begin + $display ("ERROR"); + $finish; + end + end + #100; + $display ("PASSED"); + $finish; +end + +const_system #(P) duv (.clk(clk), .reset(reset), .x(x), .y(y) ); + + + +endmodule diff --git a/ivtest/ivltests/test_timebase.v b/ivtest/ivltests/test_timebase.v new file mode 100644 index 000000000..e6bf98224 --- /dev/null +++ b/ivtest/ivltests/test_timebase.v @@ -0,0 +1,85 @@ +/*************************************************************** +** Author: Oswaldo Cadenas (oswaldo.cadenas@gmail.com) +** Date: September 26 2011 +** +** Test: Intended to test parametric counter in timebase.vhd +** the counter has parameters: N for counter length and + VALUE to flag when the count reaches this value +** +** Four counter instances are created here: +** duv1 with counter default parameters for N and VALUE +** duv2 with N1, V1 for parameter N, VALUE respectively +** duv3 with N2, V2 for parameters N, VALUE respectively +** duv4 with N2 replacing N and VALUE left as default +** +** The test for a long time making sure each of the four counter flags TICK become one +**************************************************************************************/ + +module test; + parameter integer T = 25; + parameter integer N1 = 8; + parameter integer N2 = 17; + parameter integer V1 = 200; + parameter integer V2 = 17'h16C8A; + + bit clk = 0, reset = 0; + wire [11:0] count1; + wire [N1-1:0] count2; + wire [N2-1:0] count3; + wire [N2-1:0] count4; + + wire tick1, tick2, tick3, tick4; + reg tick1_reg, tick2_reg, tick3_reg, tick4_reg; + + initial forever #(T) clk = !clk; + + + initial begin + @(negedge clk); + reset = 1'b1; + repeat(6) @(negedge clk); + reset = 1'b0; + end + + // duv1 switch + always @(posedge clk, posedge reset) + if (reset) tick1_reg <= 1'b0; + else if (tick1) tick1_reg <= 1'b1; + + // duv2 switch + always @(posedge clk, posedge reset) + if (reset) tick2_reg <= 1'b0; + else if (tick2) tick2_reg <= 1'b1; + + // duv3 switch + always @(posedge clk, posedge reset) + if (reset) tick3_reg <= 1'b0; + else if (tick3) tick3_reg <= 1'b1; + + // duv4 switch + always @(posedge clk, posedge reset) + if (reset) tick4_reg <= 1'b0; + else if (tick4) tick4_reg <= 1'b1; + + initial begin + #(V2*2*T + 1000); + if (tick1_reg != 1 || tick2_reg != 1 || tick3_reg != 1 || tick4_reg != 1) begin + $display ("Counting FAILED"); + $finish; + end + else begin + $display ("PASSED"); + #20; + $finish; + end +end + + timebase duv1 (.clock(clk), .reset(reset), .enable(1'b1), .tick(tick1), .count_value(count1) ); // default parameters + timebase #(.n(N1), .value(V1)) + duv2 (.clock(clk), .reset(reset), .enable(1'b1), .tick(tick2), .count_value(count2) ); // N1, V1 parameters + timebase #(N2, V2) + duv3 (.clock(clk), .reset(reset), .enable(1'b1), .tick(tick3), .count_value(count3) ); // N2, V2 parameters + timebase #(.n(N2)) + duv4 (.clock(clk), .reset(reset), .enable(1'b1), .tick(tick4), .count_value(count4) ); // only one parameter modified + +endmodule diff --git a/ivtest/ivltests/test_tliteral.v b/ivtest/ivltests/test_tliteral.v new file mode 100644 index 000000000..9d1a6902e --- /dev/null +++ b/ivtest/ivltests/test_tliteral.v @@ -0,0 +1,94 @@ +timeunit 1ns; +timeprecision 10ps; + +module test; + +parameter factor = 1e-9/10e-12; + +longint tmanual, tnow, tdiff; +longint incr; + +initial begin + tmanual = 0; + if ($realtime != 0) begin + $display ("FAILED"); + $finish; + end + #33.1ns; + incr = 33.1e-9/10e-12; + tmanual = tmanual + incr; + tnow = $realtime*factor; + tdiff = tnow-tmanual; + if (tdiff != 0) begin + $display ("FAILED"); + $finish; + end + #78.1ps; + incr = 78.1e-12/10e-12; + tmanual = tmanual + incr; + tnow = $realtime*factor; + tdiff = tnow-tmanual; + if (tdiff != 0) begin + $display ("FAILED"); + $finish; + end + #123.08ns; + incr = 123.08e-9/10e-12; + tmanual = tmanual + incr; + tnow = $realtime*factor; + tdiff = tnow-tmanual; + if (tdiff != 0) begin + $display ("FAILED"); + $finish; + end + #9.006ns; + incr = 9.006e-9/10e-12; + tmanual = tmanual + incr; + tnow = $realtime*factor; + tdiff = tnow-tmanual; + if (tdiff != 0) begin + $display ("FAILED"); + $finish; + end + #17.003ns; + incr = 17.003e-9/10e-12; + tmanual = tmanual + incr; + tnow = $realtime*factor; + tdiff = tnow-tmanual; + if (tdiff != 0) begin + $display ("FAILED"); + $finish; + end + #578.23us; + incr = 578.23e-6/10e-12; + tmanual = tmanual + incr; + tnow = $realtime*factor; + tdiff = tnow-tmanual; + if (tdiff != 0) begin + $display ("FAILED"); + $finish; + end + #0.0356ms; + incr = 0.0356e-3/10e-12; + tmanual = tmanual + incr; + tnow = $realtime*factor; + tdiff = tnow-tmanual; + if (tdiff != 0) begin + $display ("FAILED"); + $finish; + end + #1.011s; + incr = 1.011e0/10e-12; + tmanual = tmanual + incr; + tnow = $realtime*factor; + tdiff = tnow-tmanual; + if (tdiff != 0) begin + $display ("FAILED"); + $finish; + end + $display("PASSED"); + //$display ("Time now is: %t, manual = %0d, tnow = %0d, diff = %0d ", $realtime, tmanual, tnow, tdiff); + $finish; +end + +endmodule diff --git a/ivtest/ivltests/test_va_math.v b/ivtest/ivltests/test_va_math.v new file mode 100644 index 000000000..22a877c34 --- /dev/null +++ b/ivtest/ivltests/test_va_math.v @@ -0,0 +1,561 @@ +/* + * Verilog-A math library test code for Icarus Verilog. + * http://www.icarus.com/eda/verilog/ + * + * Copyright (C) 2007-2009 Cary R. (cygcary@yahoo.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * As of Dec. 2009 some systems have started returning the sign of + * a NaN, because of this we can for some conditions get -nan. This + * will cause mismatches with the gold file. Alan M. Feldstein + * suggested on the iverilog-devel mailing list that we use fabs + * ($abs()) since C99 speifies that it will remove the sign of the + * NaN. This appears to work, so I wrapped all functions that we + * expect to return NaN with a call to $abs(). + */ + +// Get the Verilog-A constants. +`include "constants.vams" + +module top; + real zero, mzero, inf, minf, nan; + + initial begin + // Define a few constants. + zero = 0.0; + mzero = -1.0 * zero; + inf = 1/0.0; + minf = $ln(0); + nan = $abs($sqrt(-1.0)); + + $display("Using +0 = %f, -0 = %f, nan = %f, inf = %f and -inf = %f.\n", + zero, mzero, nan, inf, minf); + + // Check that the comparisons used to detection a NaN work correctly. + if (nan != nan) $display("NaN != comparison works correctly."); + else $display("NaN != comparison failed."); + if (nan == nan) $display("NaN == comparison failed.\n"); + else $display("NaN == comparison works correctly.\n"); + + check_sqrt; + $display(""); + check_ln; + $display(""); + check_log; + $display(""); + check_exp; + $display(""); + check_abs; + $display(""); + check_ceil; + $display(""); + check_floor; + $display(""); + check_sin; + $display(""); + check_cos; + $display(""); + check_tan; + $display(""); + check_asin; + $display(""); + check_acos; + $display(""); + check_atan; + $display(""); + check_sinh; + $display(""); + check_cosh; + $display(""); + check_tanh; + $display(""); + check_asinh; + $display(""); + check_acosh; + $display(""); + check_atanh; + $display(""); + check_min; + $display(""); + check_max; + $display(""); + check_pow; + $display(""); + check_atan2; + $display(""); + check_hypot; + $display(""); + check_constants; + end + + // Task to check the square root function. + task check_sqrt; + begin + $display("--- Checking the $sqrt function ---"); + $display("The square root of 2.0 is %f.", $sqrt(2.0)); + $display("The square root of 1.0 is %f.", $sqrt(1.0)); + $display("The square root of 0.0 is %f.", $sqrt(zero)); + $display("The square root of -0.0 is %f.", $sqrt(mzero)); + $display("The square root of -1.0 is %f.", $abs($sqrt(-1.0))); + $display("The square root of inf is %f.", $sqrt(inf)); + $display("The square root of -inf is %f.", $abs($sqrt(minf))); + $display("The square root of nan is %f.", $abs($sqrt(nan))); + end + endtask + + // Task to check the natural log function. + task check_ln; + begin + $display("--- Checking the $ln function ---"); + $display("The natural log of 10.0 is %f.", $ln(10.0)); + $display("The natural log of 1.0 is %f.", $ln(1.0)); + $display("The natural log of 0.5 is %f.", $ln(0.5)); + $display("The natural log of 0.0 is %f.", $ln(zero)); + $display("The natural log of -0.0 is %f.", $ln(mzero)); + $display("The natural log of -1.0 is %f.", $abs($ln(-1.0))); + $display("The natural log of inf is %f.", $ln(inf)); + $display("The natural log of -inf is %f.", $abs($ln(minf))); + $display("The natural log of nan is %f.", $abs($ln(nan))); + end + endtask + + // Task to check the log base 10 function. + // This was originally $log, but that was deprecated in VAMS-2.3. + task check_log; + begin + $display("--- Checking the $log10 function ---"); + $display("The log base 10 of 10.0 is %f.", $log10(10.0)); + $display("The log base 10 of 1.0 is %f.", $log10(1.0)); + $display("The log base 10 of 0.5 is %f.", $log10(0.5)); + $display("The log base 10 of 0.0 is %f.", $log10(zero)); + $display("The log base 10 of -0.0 is %f.", $log10(mzero)); + $display("The log base 10 of -1.0 is %f.", $abs($log10(-1.0))); + $display("The log base 10 of inf is %f.", $log10(inf)); + $display("The log base 10 of -inf is %f.", $abs($log10(minf))); + $display("The log base 10 of nan is %f.", $abs($log10(nan))); + end + endtask + + // Task to check the exponential function. + task check_exp; + begin + $display("--- Checking the $exp function ---"); + $display("The exponential of 1.0 is %f.", $exp(1.0)); + $display("The exponential of 0.0 is %f.", $exp(zero)); + $display("The exponential of -0.0 is %f.", $exp(mzero)); + $display("The exponential of -1.0 is %f.", $exp(-1.0)); + $display("The exponential of inf is %f.", $exp(inf)); + $display("The exponential of -inf is %f.", $exp(minf)); + $display("The exponential of nan is %f.", $abs($exp(nan))); + end + endtask + + // Task to check the absolute value function. + task check_abs; + begin + $display("--- Checking the $abs function ---"); + $display("The absolute value of 1.0 is %f.", $abs(1.0)); + $display("The absolute value of 0.0 is %f.", $abs(zero)); + $display("The absolute value of -0.0 is %f.", $abs(mzero)); + $display("The absolute value of -1.0 is %f.", $abs(-1.0)); + $display("The absolute value of inf is %f.", $abs(inf)); + $display("The absolute value of -inf is %f.", $abs(minf)); + $display("The absolute value of nan is %f.", $abs(nan)); + end + endtask + + // Task to check the ceiling function. + task check_ceil; + begin + $display("--- Checking the $ceil function ---"); + $display("The ceiling of 2.1 is %f.", $ceil(2.1)); + $display("The ceiling of 0.5 is %f.", $ceil(0.5)); + // Some C math libraries return -0.0 and some return 0.0. + // Both appear to be correct since the standard does not + // specify exactly what should be done so convert to 0.0. + $display("The ceiling of -0.5 is %f.", $ceil(-0.5)+0.0); + $display("The ceiling of -1.1 is %f.", $ceil(-1.1)); + $display("The ceiling of inf is %f.", $ceil(inf)); + $display("The ceiling of -inf is %f.", $ceil(minf)); + $display("The ceiling of nan is %f.", $abs($ceil(nan))); + end + endtask + + // Task to check the floor function. + task check_floor; + begin + $display("--- Checking the $floor function ---"); + $display("The floor of 2.1 is %f.", $floor(2.1)); + $display("The floor of 0.5 is %f.", $floor(0.5)); + $display("The floor of -0.5 is %f.", $floor(-0.5)); + $display("The floor of -1.1 is %f.", $floor(-1.1)); + $display("The floor of inf is %f.", $floor(inf)); + $display("The floor of -inf is %f.", $floor(minf)); + $display("The floor of nan is %f.", $abs($floor(nan))); + end + endtask + + // Task to check the sin function. + task check_sin; + begin + $display("--- Checking the $sin function ---"); + $display("The sin of 4.0 is %f.", $sin(4.0)); + $display("The sin of 1.0 is %f.", $sin(1.0)); + $display("The sin of 0.0 is %f.", $sin(zero)); + $display("The sin of -0.0 is %f.", $sin(mzero)); + $display("The sin of -1.0 is %f.", $sin(-1.0)); + $display("The sin of -4.0 is %f.", $sin(-4.0)); + $display("The sin of inf is %f.", $abs($sin(inf))); + $display("The sin of -inf is %f.", $abs($sin(minf))); + $display("The sin of nan is %f.", $abs($sin(nan))); + end + endtask + + // Task to check the cos function. + task check_cos; + begin + $display("--- Checking the $cos function ---"); + $display("The cos of 4.0 is %f.", $cos(4.0)); + $display("The cos of 1.0 is %f.", $cos(1.0)); + $display("The cos of 0.0 is %f.", $cos(zero)); + $display("The cos of -0.0 is %f.", $cos(mzero)); + $display("The cos of -1.0 is %f.", $cos(-1.0)); + $display("The cos of -4.0 is %f.", $cos(-4.0)); + $display("The cos of inf is %f.", $abs($cos(inf))); + $display("The cos of -inf is %f.", $abs($cos(minf))); + $display("The cos of nan is %f.", $abs($cos(nan))); + end + endtask + + // Task to check the tan function. + task check_tan; + begin + $display("--- Checking the $tan function ---"); + $display("The tan of 4.0 is %f.", $tan(4.0)); + $display("The tan of 1.0 is %f.", $tan(1.0)); + $display("The tan of 0.0 is %f.", $tan(zero)); + $display("The tan of -0.0 is %f.", $tan(mzero)); + $display("The tan of -1.0 is %f.", $tan(-1.0)); + $display("The tan of -4.0 is %f.", $tan(-4.0)); + // The underlying C math libraries can give different results for + // this corner case, so we can only use four significant digits + // for these two tests. + $display("The tan of pi/2 is %.4g.", $tan($asin(1.0))); + $display("The tan of -pi/2 is %.4g.", $tan($asin(-1.0))); + $display("The tan of inf is %f.", $abs($tan(inf))); + $display("The tan of -inf is %f.", $abs($tan(minf))); + $display("The tan of nan is %f.", $abs($tan(nan))); + end + endtask + + // Task to check the asin function. + task check_asin; + begin + $display("--- Checking the $asin function ---"); + $display("The asin of 1.1 is %f.", $abs($asin(1.1))); + $display("The asin of 1.0 is %f.", $asin(1.0)); + $display("The asin of 0.5 is %f.", $asin(0.5)); + $display("The asin of 0.0 is %f.", $asin(zero)); + $display("The asin of -0.0 is %f.", $asin(mzero)); + $display("The asin of -0.5 is %f.", $asin(-0.5)); + $display("The asin of -1.0 is %f.", $asin(-1.0)); + $display("The asin of -1.1 is %f.", $abs($asin(-1.1))); + $display("The asin of inf is %f.", $abs($asin(inf))); + $display("The asin of -inf is %f.", $abs($asin(minf))); + $display("The asin of nan is %f.", $abs($asin(nan))); + end + endtask + + // Task to check the acos function. + task check_acos; + begin + $display("--- Checking the $acos function ---"); + $display("The acos of 1.1 is %f.", $abs($acos(1.1))); + $display("The acos of 1.0 is %f.", $acos(1.0)); + $display("The acos of 0.5 is %f.", $acos(0.5)); + $display("The acos of 0.0 is %f.", $acos(zero)); + $display("The acos of -0.0 is %f.", $acos(mzero)); + $display("The acos of -0.5 is %f.", $acos(-0.5)); + $display("The acos of -1.0 is %f.", $acos(-1.0)); + $display("The acos of -1.1 is %f.", $abs($acos(-1.1))); + $display("The acos of inf is %f.", $abs($acos(inf))); + $display("The acos of -inf is %f.", $abs($acos(minf))); + $display("The acos of nan is %f.", $abs($acos(nan))); + end + endtask + + // Task to check the atan function. + task check_atan; + begin + $display("--- Checking the $atan function ---"); + $display("The atan of 2.0 is %f.", $atan(2.0)); + $display("The atan of 0.5 is %f.", $atan(0.5)); + $display("The atan of 0.0 is %f.", $atan(zero)); + $display("The atan of -0.0 is %f.", $atan(mzero)); + $display("The atan of -0.5 is %f.", $atan(-0.5)); + $display("The atan of -2.0 is %f.", $atan(-2.0)); + $display("The atan of inf is %f.", $atan(inf)); + $display("The atan of -inf is %f.", $atan(minf)); + $display("The atan of nan is %f.", $abs($atan(nan))); + end + endtask + + // Task to check the sinh function. + task check_sinh; + begin + $display("--- Checking the $sinh function ---"); + $display("The sinh of 2.0 is %f.", $sinh(2.0)); + $display("The sinh of 1.0 is %f.", $sinh(1.0)); + $display("The sinh of 0.5 is %f.", $sinh(0.5)); + $display("The sinh of 0.0 is %f.", $sinh(zero)); + $display("The sinh of -0.0 is %f.", $sinh(mzero)); + $display("The sinh of -0.5 is %f.", $sinh(-0.5)); + $display("The sinh of -1.0 is %f.", $sinh(-1.0)); + $display("The sinh of -2.0 is %f.", $sinh(-2.0)); + $display("The sinh of inf is %f.", $sinh(inf)); + $display("The sinh of -inf is %f.", $sinh(minf)); + $display("The sinh of nan is %f.", $abs($sinh(nan))); + end + endtask + + // Task to check the cosh function. + task check_cosh; + begin + $display("--- Checking the $cosh function ---"); + $display("The cosh of 2.0 is %f.", $cosh(2.0)); + $display("The cosh of 1.0 is %f.", $cosh(1.0)); + $display("The cosh of 0.5 is %f.", $cosh(0.5)); + $display("The cosh of 0.0 is %f.", $cosh(zero)); + $display("The cosh of -0.0 is %f.", $cosh(mzero)); + $display("The cosh of -0.5 is %f.", $cosh(-0.5)); + $display("The cosh of -1.0 is %f.", $cosh(-1.0)); + $display("The cosh of -2.0 is %f.", $cosh(-2.0)); + $display("The cosh of inf is %f.", $cosh(inf)); + $display("The cosh of -inf is %f.", $cosh(minf)); + $display("The cosh of nan is %f.", $abs($cosh(nan))); + end + endtask + + // Task to check the tanh function. + task check_tanh; + begin + $display("--- Checking the $tanh function ---"); + $display("The tanh of 2.0 is %f.", $tanh(2.0)); + $display("The tanh of 1.0 is %f.", $tanh(1.0)); + $display("The tanh of 0.5 is %f.", $tanh(0.5)); + $display("The tanh of 0.0 is %f.", $tanh(zero)); + $display("The tanh of -0.0 is %f.", $tanh(mzero)); + $display("The tanh of -0.5 is %f.", $tanh(-0.5)); + $display("The tanh of -1.0 is %f.", $tanh(-1.0)); + $display("The tanh of -2.0 is %f.", $tanh(-2.0)); + $display("The tanh of inf is %f.", $tanh(inf)); + $display("The tanh of -inf is %f.", $tanh(minf)); + $display("The tanh of nan is %f.", $abs($tanh(nan))); + end + endtask + + // Task to check the asinh function. + task check_asinh; + begin + $display("--- Checking the $asinh function ---"); + $display("The asinh of 2.0 is %f.", $asinh(2.0)); + $display("The asinh of 1.0 is %f.", $asinh(1.0)); + $display("The asinh of 0.5 is %f.", $asinh(0.5)); + $display("The asinh of 0.0 is %f.", $asinh(zero)); + $display("The asinh of -0.0 is %f.", $asinh(mzero)); + $display("The asinh of -0.5 is %f.", $asinh(-0.5)); + $display("The asinh of -1.0 is %f.", $asinh(-1.0)); + $display("The asinh of -2.0 is %f.", $asinh(-2.0)); + $display("The asinh of inf is %f.", $asinh(inf)); + $display("The asinh of -inf is %f.", $asinh(minf)); + $display("The asinh of nan is %f.", $abs($asinh(nan))); + end + endtask + + // Task to check the acosh function. + task check_acosh; + begin + $display("--- Checking the $acosh function ---"); + $display("The acosh of 2.0 is %f.", $acosh(2.0)); + $display("The acosh of 1.0 is %f.", $acosh(1.0)); + $display("The acosh of 0.5 is %f.", $abs($acosh(0.5))); + $display("The acosh of 0 is %f.", $abs($acosh(zero))); + $display("The acosh of -0 is %f.", $abs($acosh(mzero))); + $display("The acosh of -0.5 is %f.", $abs($acosh(-0.5))); + $display("The acosh of -1.0 is %f.", $abs($acosh(-1.0))); + $display("The acosh of -2.0 is %f.", $abs($acosh(-2.0))); + $display("The acosh of inf is %f.", $acosh(inf)); + $display("The acosh of -inf is %f.", $abs($acosh(minf))); + $display("The acosh of nan is %f.", $abs($acosh(nan))); + end + endtask + + // Task to check the atanh function. + task check_atanh; + begin + $display("--- Checking the $atanh function ---"); + $display("The atanh of 2.0 is %f.", $abs($atanh(2.0))); + $display("The atanh of 1.0 is %f.", $atanh(1.0)); + $display("The atanh of 0.5 is %f.", $atanh(0.5)); + $display("The atanh of 0.0 is %f.", $atanh(zero)); + $display("The atanh of -0.0 is %f.", $atanh(mzero)); + $display("The atanh of -0.5 is %f.", $atanh(-0.5)); + $display("The atanh of -1.0 is %f.", $atanh(-1.0)); + $display("The atanh of -2.0 is %f.", $abs($atanh(-2.0))); + $display("The atanh of inf is %f.", $abs($atanh(inf))); + $display("The atanh of -inf is %f.", $abs($atanh(minf))); + $display("The atanh of nan is %f.", $abs($atanh(nan))); + end + endtask + + // Task to check the min function. + task check_min; + begin + $display("--- Checking the $min function ---"); + $display("The minimum of 1.0 and 2.0 is %f.", $min(1.0, 2.0)); + $display("The minimum of 2.0 and 1.0 is %f.", $min(2.0, 1.0)); + $display("The minimum of 1.0 and -1.0 is %f.", $min(1.0, -1.0)); + $display("The minimum of -1.0 and -2.0 is %f.", $min(-1.0, -2.0)); + $display("The minimum of 2.0 and inf is %f.", $min(2.0, inf)); + $display("The minimum of inf and 2.0 is %f.", $min(inf, 2.0)); + $display("The minimum of 2.0 and -inf is %f.", $min(2.0, minf)); + $display("The minimum of -inf and 2.0 is %f.", $min(minf, 2.0)); + $display("The minimum of 2.0 and nan is %f.", $min(2.0, nan)); + $display("The minimum of nan and 2.0 is %f.", $min(nan, 2.0)); + end + endtask + + // Task to check the max function. + task check_max; + begin + $display("--- Checking the $max function ---"); + $display("The maximum of 1.0 and 2.0 is %f.", $max(1.0, 2.0)); + $display("The maximum of 2.0 and 1.0 is %f.", $max(2.0, 1.0)); + $display("The maximum of 1.0 and -1.0 is %f.", $max(1.0, -1.0)); + $display("The maximum of -1.0 and -2.0 is %f.", $max(-1.0, -2.0)); + $display("The maximum of 2.0 and inf is %f.", $max(2.0, inf)); + $display("The maximum of inf and 2.0 is %f.", $max(inf, 2.0)); + $display("The maximum of 2.0 and -inf is %f.", $max(2.0, minf)); + $display("The maximum of -inf and 2.0 is %f.", $max(minf, 2.0)); + $display("The maximum of 2.0 and nan is %f.", $max(2.0, nan)); + $display("The maximum of nan and 2.0 is %f.", $max(nan, 2.0)); + end + endtask + + // Task to check the power function. + task check_pow; + begin + $display("--- Checking the $pow function ---"); + $display(" 0.0 to the power of 0.0 is %f.", $pow(zero, zero)); + $display(" 1.0 to the power of 0.0 is %f.", $pow(1.0, zero)); + $display("-1.0 to the power of 0.0 is %f.", $pow(-1.0, zero)); + $display(" 0.0 to the power of 1.0 is %f.", $pow(zero, 1.0)); + $display(" 1.0 to the power of 1.0 is %f.", $pow(1.0, 1.0)); + $display("-1.0 to the power of 1.0 is %f.", $pow(-1.0, 1.0)); + $display(" 8.0 to the power of 1/3 is %f.", $pow(8.0, 1.0/3.0)); + $display(" 8.0 to the power of -1/3 is %f.", $pow(8.0, -1.0/3.0)); + $display(" 2.0 to the power of 3.0 is %f.", $pow(2.0, 3.0)); + $display(" 2.0 to the power of 5000 is %f.", $pow(2.0, 5000)); + $display("-2.0 to the power of 5001 is %f.", $pow(-2.0, 5001)); + $display(" 2.0 to the power of -5000 is %f.", $pow(2.0, -5000)); + $display(" inf to the power of 0.0 is %f.", $pow(inf, zero)); + $display("-inf to the power of 0.0 is %f.", $pow(minf, zero)); + $display(" inf to the power of 1.0 is %f.", $pow(inf, 1.0)); + $display("-inf to the power of 1.0 is %f.", $pow(minf, 1.0)); + $display(" inf to the power of 2.0 is %f.", $pow(inf, 2.0)); + $display("-inf to the power of 2.0 is %f.", $pow(minf, 2.0)); + $display(" 1.0 to the power of inf is %f.", $pow(1.0, inf)); + $display("-1.0 to the power of inf is %f.", $pow(-1.0, inf)); + $display(" 0.5 to the power of inf is %f.", $pow(0.5, inf)); + $display(" 2.0 to the power of inf is %f.", $pow(2.0, inf)); + $display(" 1.0 to the power of -inf is %f.", $pow(1.0, minf)); + $display("-1.0 to the power of -inf is %f.", $pow(-1.0, minf)); + $display(" 0.5 to the power of -inf is %f.", $pow(0.5, minf)); + $display(" 2.0 to the power of -inf is %f.", $pow(2.0, minf)); + $display("-1.0 to the power of -1/3 is %f.", $abs($pow(-1.0, -1.0/3.0))); + $display(" 1.0 to the power of nan is %f.", $pow(1.0, nan)); + $display(" nan to the power of 1.0 is %f.", $abs($pow(nan, 1.0))); + $display(" nan to the power of 0.0 is %f.", $pow(nan, zero)); + $display(" nan to the power of nan is %f.", $abs($pow(nan, nan))); + end + endtask + + // Task to check the atan of x/y function. + task check_atan2; + begin + $display("--- Checking the $atan2 function ---"); + $display("The atan of 0.0/ 0.0 is %f.", $atan2(zero, zero)); + $display("The atan of -0.0/ 0.0 is %f.", $atan2(mzero, zero)); + $display("The atan of 0.0/-0.0 is %f.", $atan2(zero, mzero)); + $display("The atan of -0.0/-0.0 is %f.", $atan2(mzero, mzero)); + $display("The atan of 0.0/ 1.0 is %f.", $atan2(zero, 1.0)); + $display("The atan of 1.0/ 0.0 is %f.", $atan2(1.0, zero)); + $display("The atan of 1.0/ 1.0 is %f.", $atan2(1.0, 1.0)); + $display("The atan of 0.0/-1.0 is %f.", $atan2(zero, -1.0)); + $display("The atan of -1.0/ 0.0 is %f.", $atan2(-1.0, zero)); + $display("The atan of -1.0/-1.0 is %f.", $atan2(-1.0, -1.0)); + $display("The atan of inf/ 0.0 is %f.", $atan2(inf, zero)); + $display("The atan of 0.0/ inf is %f.", $atan2(zero, inf)); + $display("The atan of inf/ inf is %f.", $atan2(inf, inf)); + $display("The atan of -inf/ 0.0 is %f.", $atan2(minf, zero)); + $display("The atan of 0.0/-inf is %f.", $atan2(zero, minf)); + $display("The atan of -inf/-inf is %f.", $atan2(minf, minf)); + $display("The atan of nan/ 0.0 is %f.", $abs($atan2(nan, zero))); + $display("The atan of nan/ 1.0 is %f.", $abs($atan2(nan, 1.0))); + $display("The atan of 1.0/ nan is %f.", $abs($atan2(1.0, nan))); + end + endtask + + // Task to check the distance from origin function. + task check_hypot; + begin + $display("--- Checking the $hypot function ---"); + $display("The distance to ( 0.0, 0.0) is %f.", $hypot(zero, zero)); + $display("The distance to ( 2.0, 0.0) is %f.", $hypot(2.0, zero)); + $display("The distance to ( -2.0, 0.0) is %f.", $hypot(-2.0, zero)); + $display("The distance to ( 0.0, 2.0) is %f.", $hypot(zero, 2.0)); + $display("The distance to ( 0.0, -2.0) is %f.", $hypot(zero, -2.0)); + $display("The distance to ( inf, 0.0) is %f.", $hypot(inf, zero)); + $display("The distance to ( 0.0, inf) is %f.", $hypot(zero, inf)); + $display("The distance to ( -inf, 0.0) is %f.", $hypot(minf, zero)); + $display("The distance to ( nan, 0.0) is %f.", $abs($hypot(nan, zero))); + $display("The distance to ( 0.0, nan) is %f.", $abs($hypot(zero, nan))); + end + endtask + + // Task to check the mathematical constants. + task check_constants; + begin + $display("--- Checking the mathematical constants ---"); + $display(" Pi is %.16f.", `M_PI); + $display(" 2*Pi is %.16f.", `M_TWO_PI); + $display(" Pi/2 is %.16f.", `M_PI_2); + $display(" Pi/4 is %.16f.", `M_PI_4); + $display(" 1/Pi is %.16f.", `M_1_PI); + $display(" 2/Pi is %.16f.", `M_2_PI); + $display("2/sqrt(Pi) is %.16f.", `M_2_SQRTPI); + $display(" e is %.16f.", `M_E); + $display(" log2(e) is %.16f.", `M_LOG2E); + $display(" log10(e) is %.16f.", `M_LOG10E); + $display(" loge(2) is %.16f.", `M_LN2); + $display(" loge(10) is %.16f.", `M_LN10); + $display(" sqrt(2) is %.16f.", `M_SQRT2); + $display(" 1/sqrt(2) is %.16f.", `M_SQRT1_2); + end + endtask +endmodule diff --git a/ivtest/ivltests/test_vams_math.v b/ivtest/ivltests/test_vams_math.v new file mode 100644 index 000000000..b5bf9a077 --- /dev/null +++ b/ivtest/ivltests/test_vams_math.v @@ -0,0 +1,557 @@ +/* + * Verilog-A math library test code for Icarus Verilog. + * http://www.icarus.com/eda/verilog/ + * + * Copyright (C) 2007-2009 Cary R. (cygcary@yahoo.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * As of Dec. 2009 some systems have started returning the sign of + * a NaN, because of this we can for some conditions get -nan. This + * will cause mismatches with the gold file. Alan M. Feldstein + * suggested on the iverilog-devel mailing list that we use fabs + * (abs()) since C99 speifies that it will remove the sign of the + * NaN. This appears to work, so I wrapped all functions that we + * expect to return NaN with a call to abs(). + */ + +// Get the Verilog-A constants. +`include "constants.vams" + +module top; + real zero, mzero, pinf, minf, nan; + + initial begin + // Define a few constants. + zero = 0.0; + mzero = -1.0 * zero; + pinf = 1/0.0; + minf = ln(0); + nan = abs(sqrt(-1.0)); + + $display("Using +0 = %f, -0 = %f, nan = %f, inf = %f and -inf = %f.\n", + zero, mzero, nan, pinf, minf); + + // Check that the comparisons used to detection a NaN work correctly. + if (nan != nan) $display("NaN != comparison works correctly."); + else $display("NaN != comparison failed."); + if (nan == nan) $display("NaN == comparison failed.\n"); + else $display("NaN == comparison works correctly.\n"); + + check_sqrt; + $display(""); + check_ln; + $display(""); + check_log; + $display(""); + check_exp; + $display(""); + check_abs; + $display(""); + check_ceil; + $display(""); + check_floor; + $display(""); + check_sin; + $display(""); + check_cos; + $display(""); + check_tan; + $display(""); + check_asin; + $display(""); + check_acos; + $display(""); + check_atan; + $display(""); + check_sinh; + $display(""); + check_cosh; + $display(""); + check_tanh; + $display(""); + check_asinh; + $display(""); + check_acosh; + $display(""); + check_atanh; + $display(""); + check_min; + $display(""); + check_max; + $display(""); + check_pow; + $display(""); + check_atan2; + $display(""); + check_hypot; + $display(""); + check_constants; + end + + // Task to check the square root function. + task check_sqrt; + begin + $display("--- Checking the sqrt function ---"); + $display("The square root of 2.0 is %f.", sqrt(2.0)); + $display("The square root of 1.0 is %f.", sqrt(1.0)); + $display("The square root of 0.0 is %f.", sqrt(zero)); + $display("The square root of -0.0 is %f.", sqrt(mzero)); + $display("The square root of -1.0 is %f.", abs(sqrt(-1.0))); + $display("The square root of inf is %f.", sqrt(pinf)); + $display("The square root of -inf is %f.", abs(sqrt(minf))); + $display("The square root of nan is %f.", abs(sqrt(nan))); + end + endtask + + // Task to check the natural log function. + task check_ln; + begin + $display("--- Checking the ln function ---"); + $display("The natural log of 10.0 is %f.", ln(10.0)); + $display("The natural log of 1.0 is %f.", ln(1.0)); + $display("The natural log of 0.5 is %f.", ln(0.5)); + $display("The natural log of 0.0 is %f.", ln(zero)); + $display("The natural log of -0.0 is %f.", ln(mzero)); + $display("The natural log of -1.0 is %f.", abs(ln(-1.0))); + $display("The natural log of inf is %f.", ln(pinf)); + $display("The natural log of -inf is %f.", abs(ln(minf))); + $display("The natural log of nan is %f.", abs(ln(nan))); + end + endtask + + // Task to check the log base 10 function. + task check_log; + begin + $display("--- Checking the log function ---"); + $display("The log base 10 of 10.0 is %f.", log(10.0)); + $display("The log base 10 of 1.0 is %f.", log(1.0)); + $display("The log base 10 of 0.5 is %f.", log(0.5)); + $display("The log base 10 of 0.0 is %f.", log(zero)); + $display("The log base 10 of -0.0 is %f.", log(mzero)); + $display("The log base 10 of -1.0 is %f.", abs(log(-1.0))); + $display("The log base 10 of inf is %f.", log(pinf)); + $display("The log base 10 of -inf is %f.", abs(log(minf))); + $display("The log base 10 of nan is %f.", abs(log(nan))); + end + endtask + + // Task to check the exponential function. + task check_exp; + begin + $display("--- Checking the exp function ---"); + $display("The exponential of 1.0 is %f.", exp(1.0)); + $display("The exponential of 0.0 is %f.", exp(zero)); + $display("The exponential of -0.0 is %f.", exp(mzero)); + $display("The exponential of -1.0 is %f.", exp(-1.0)); + $display("The exponential of inf is %f.", exp(pinf)); + $display("The exponential of -inf is %f.", exp(minf)); + $display("The exponential of nan is %f.", abs(exp(nan))); + end + endtask + + // Task to check the absolute value function. + task check_abs; + begin + $display("--- Checking the abs function ---"); + $display("The absolute value of 1.0 is %f.", abs(1.0)); + $display("The absolute value of 0.0 is %f.", abs(zero)); + $display("The absolute value of -0.0 is %f.", abs(mzero)); + $display("The absolute value of -1.0 is %f.", abs(-1.0)); + $display("The absolute value of inf is %f.", abs(pinf)); + $display("The absolute value of -inf is %f.", abs(minf)); + $display("The absolute value of nan is %f.", abs(nan)); + end + endtask + + // Task to check the ceiling function. + task check_ceil; + begin + $display("--- Checking the ceil function ---"); + $display("The ceiling of 2.1 is %f.", ceil(2.1)); + $display("The ceiling of 0.5 is %f.", ceil(0.5)); + $display("The ceiling of -0.5 is %f.", ceil(-0.5) + 0.0); + $display("The ceiling of -1.1 is %f.", ceil(-1.1)); + $display("The ceiling of inf is %f.", ceil(pinf)); + $display("The ceiling of -inf is %f.", ceil(minf)); + $display("The ceiling of nan is %f.", abs(ceil(nan))); + end + endtask + + // Task to check the floor function. + task check_floor; + begin + $display("--- Checking the floor function ---"); + $display("The floor of 2.1 is %f.", floor(2.1)); + $display("The floor of 0.5 is %f.", floor(0.5)); + $display("The floor of -0.5 is %f.", floor(-0.5)); + $display("The floor of -1.1 is %f.", floor(-1.1)); + $display("The floor of inf is %f.", floor(pinf)); + $display("The floor of -inf is %f.", floor(minf)); + $display("The floor of nan is %f.", abs(floor(nan))); + end + endtask + + // Task to check the sin function. + task check_sin; + begin + $display("--- Checking the sin function ---"); + $display("The sin of 4.0 is %f.", sin(4.0)); + $display("The sin of 1.0 is %f.", sin(1.0)); + $display("The sin of 0.0 is %f.", sin(zero)); + $display("The sin of -0.0 is %f.", sin(mzero)); + $display("The sin of -1.0 is %f.", sin(-1.0)); + $display("The sin of -4.0 is %f.", sin(-4.0)); + $display("The sin of inf is %f.", abs(sin(pinf))); + $display("The sin of -inf is %f.", abs(sin(minf))); + $display("The sin of nan is %f.", abs(sin(nan))); + end + endtask + + // Task to check the cos function. + task check_cos; + begin + $display("--- Checking the cos function ---"); + $display("The cos of 4.0 is %f.", cos(4.0)); + $display("The cos of 1.0 is %f.", cos(1.0)); + $display("The cos of 0.0 is %f.", cos(zero)); + $display("The cos of -0.0 is %f.", cos(mzero)); + $display("The cos of -1.0 is %f.", cos(-1.0)); + $display("The cos of -4.0 is %f.", cos(-4.0)); + $display("The cos of inf is %f.", abs(cos(pinf))); + $display("The cos of -inf is %f.", abs(cos(minf))); + $display("The cos of nan is %f.", abs(cos(nan))); + end + endtask + + // Task to check the tan function. + task check_tan; + begin + $display("--- Checking the tan function ---"); + $display("The tan of 4.0 is %f.", tan(4.0)); + $display("The tan of 1.0 is %f.", tan(1.0)); + $display("The tan of 0.0 is %f.", tan(zero)); + $display("The tan of -0.0 is %f.", tan(mzero)); + $display("The tan of -1.0 is %f.", tan(-1.0)); + $display("The tan of -4.0 is %f.", tan(-4.0)); + // The underlying math libraries can give different results for + // this corner case, so we can only use four significant digits + // for these two tests. + $display("The tan of pi/2 is %.4g.", tan(asin(1.0))); + $display("The tan of -pi/2 is %.4g.", tan(asin(-1.0))); + $display("The tan of inf is %f.", abs(tan(pinf))); + $display("The tan of -inf is %f.", abs(tan(minf))); + $display("The tan of nan is %f.", abs(tan(nan))); + end + endtask + + // Task to check the asin function. + task check_asin; + begin + $display("--- Checking the asin function ---"); + $display("The asin of 1.1 is %f.", abs(asin(1.1))); + $display("The asin of 1.0 is %f.", asin(1.0)); + $display("The asin of 0.5 is %f.", asin(0.5)); + $display("The asin of 0.0 is %f.", asin(zero)); + $display("The asin of -0.0 is %f.", asin(mzero)); + $display("The asin of -0.5 is %f.", asin(-0.5)); + $display("The asin of -1.0 is %f.", asin(-1.0)); + $display("The asin of -1.1 is %f.", abs(asin(-1.1))); + $display("The asin of inf is %f.", abs(asin(pinf))); + $display("The asin of -inf is %f.", abs(asin(minf))); + $display("The asin of nan is %f.", abs(asin(nan))); + end + endtask + + // Task to check the acos function. + task check_acos; + begin + $display("--- Checking the acos function ---"); + $display("The acos of 1.1 is %f.", abs(acos(1.1))); + $display("The acos of 1.0 is %f.", acos(1.0)); + $display("The acos of 0.5 is %f.", acos(0.5)); + $display("The acos of 0.0 is %f.", acos(zero)); + $display("The acos of -0.0 is %f.", acos(mzero)); + $display("The acos of -0.5 is %f.", acos(-0.5)); + $display("The acos of -1.0 is %f.", acos(-1.0)); + $display("The acos of -1.1 is %f.", abs(acos(-1.1))); + $display("The acos of inf is %f.", abs(acos(pinf))); + $display("The acos of -inf is %f.", abs(acos(minf))); + $display("The acos of nan is %f.", abs(acos(nan))); + end + endtask + + // Task to check the atan function. + task check_atan; + begin + $display("--- Checking the atan function ---"); + $display("The atan of 2.0 is %f.", atan(2.0)); + $display("The atan of 0.5 is %f.", atan(0.5)); + $display("The atan of 0.0 is %f.", atan(zero)); + $display("The atan of -0.0 is %f.", atan(mzero)); + $display("The atan of -0.5 is %f.", atan(-0.5)); + $display("The atan of -2.0 is %f.", atan(-2.0)); + $display("The atan of inf is %f.", atan(pinf)); + $display("The atan of -inf is %f.", atan(minf)); + $display("The atan of nan is %f.", abs(atan(nan))); + end + endtask + + // Task to check the sinh function. + task check_sinh; + begin + $display("--- Checking the sinh function ---"); + $display("The sinh of 2.0 is %f.", sinh(2.0)); + $display("The sinh of 1.0 is %f.", sinh(1.0)); + $display("The sinh of 0.5 is %f.", sinh(0.5)); + $display("The sinh of 0.0 is %f.", sinh(zero)); + $display("The sinh of -0.0 is %f.", sinh(mzero)); + $display("The sinh of -0.5 is %f.", sinh(-0.5)); + $display("The sinh of -1.0 is %f.", sinh(-1.0)); + $display("The sinh of -2.0 is %f.", sinh(-2.0)); + $display("The sinh of inf is %f.", sinh(pinf)); + $display("The sinh of -inf is %f.", sinh(minf)); + $display("The sinh of nan is %f.", abs(sinh(nan))); + end + endtask + + // Task to check the cosh function. + task check_cosh; + begin + $display("--- Checking the cosh function ---"); + $display("The cosh of 2.0 is %f.", cosh(2.0)); + $display("The cosh of 1.0 is %f.", cosh(1.0)); + $display("The cosh of 0.5 is %f.", cosh(0.5)); + $display("The cosh of 0.0 is %f.", cosh(zero)); + $display("The cosh of -0.0 is %f.", cosh(mzero)); + $display("The cosh of -0.5 is %f.", cosh(-0.5)); + $display("The cosh of -1.0 is %f.", cosh(-1.0)); + $display("The cosh of -2.0 is %f.", cosh(-2.0)); + $display("The cosh of inf is %f.", cosh(pinf)); + $display("The cosh of -inf is %f.", cosh(minf)); + $display("The cosh of nan is %f.", abs(cosh(nan))); + end + endtask + + // Task to check the tanh function. + task check_tanh; + begin + $display("--- Checking the tanh function ---"); + $display("The tanh of 2.0 is %f.", tanh(2.0)); + $display("The tanh of 1.0 is %f.", tanh(1.0)); + $display("The tanh of 0.5 is %f.", tanh(0.5)); + $display("The tanh of 0.0 is %f.", tanh(zero)); + $display("The tanh of -0.0 is %f.", tanh(mzero)); + $display("The tanh of -0.5 is %f.", tanh(-0.5)); + $display("The tanh of -1.0 is %f.", tanh(-1.0)); + $display("The tanh of -2.0 is %f.", tanh(-2.0)); + $display("The tanh of inf is %f.", tanh(pinf)); + $display("The tanh of -inf is %f.", tanh(minf)); + $display("The tanh of nan is %f.", abs(tanh(nan))); + end + endtask + + // Task to check the asinh function. + task check_asinh; + begin + $display("--- Checking the asinh function ---"); + $display("The asinh of 2.0 is %f.", asinh(2.0)); + $display("The asinh of 1.0 is %f.", asinh(1.0)); + $display("The asinh of 0.5 is %f.", asinh(0.5)); + $display("The asinh of 0.0 is %f.", asinh(zero)); + $display("The asinh of -0.0 is %f.", asinh(mzero)); + $display("The asinh of -0.5 is %f.", asinh(-0.5)); + $display("The asinh of -1.0 is %f.", asinh(-1.0)); + $display("The asinh of -2.0 is %f.", asinh(-2.0)); + $display("The asinh of inf is %f.", asinh(pinf)); + $display("The asinh of -inf is %f.", asinh(minf)); + $display("The asinh of nan is %f.", abs(asinh(nan))); + end + endtask + + // Task to check the acosh function. + task check_acosh; + begin + $display("--- Checking the acosh function ---"); + $display("The acosh of 2.0 is %f.", acosh(2.0)); + $display("The acosh of 1.0 is %f.", acosh(1.0)); + $display("The acosh of 0.5 is %f.", abs(acosh(0.5))); + $display("The acosh of 0 is %f.", abs(acosh(zero))); + $display("The acosh of -0 is %f.", abs(acosh(mzero))); + $display("The acosh of -0.5 is %f.", abs(acosh(-0.5))); + $display("The acosh of -1.0 is %f.", abs(acosh(-1.0))); + $display("The acosh of -2.0 is %f.", abs(acosh(-2.0))); + $display("The acosh of inf is %f.", acosh(pinf)); + $display("The acosh of -inf is %f.", abs(acosh(minf))); + $display("The acosh of nan is %f.", abs(acosh(nan))); + end + endtask + + // Task to check the atanh function. + task check_atanh; + begin + $display("--- Checking the atanh function ---"); + $display("The atanh of 2.0 is %f.", abs(atanh(2.0))); + $display("The atanh of 1.0 is %f.", atanh(1.0)); + $display("The atanh of 0.5 is %f.", atanh(0.5)); + $display("The atanh of 0.0 is %f.", atanh(zero)); + $display("The atanh of -0.0 is %f.", atanh(mzero)); + $display("The atanh of -0.5 is %f.", atanh(-0.5)); + $display("The atanh of -1.0 is %f.", atanh(-1.0)); + $display("The atanh of -2.0 is %f.", abs(atanh(-2.0))); + $display("The atanh of inf is %f.", abs(atanh(pinf))); + $display("The atanh of -inf is %f.", abs(atanh(minf))); + $display("The atanh of nan is %f.", abs(atanh(nan))); + end + endtask + + // Task to check the min function. + task check_min; + begin + $display("--- Checking the min function ---"); + $display("The minimum of 1.0 and 2.0 is %f.", min(1.0, 2.0)); + $display("The minimum of 2.0 and 1.0 is %f.", min(2.0, 1.0)); + $display("The minimum of 1.0 and -1.0 is %f.", min(1.0, -1.0)); + $display("The minimum of -1.0 and -2.0 is %f.", min(-1.0, -2.0)); + $display("The minimum of 2.0 and inf is %f.", min(2.0, pinf)); + $display("The minimum of inf and 2.0 is %f.", min(pinf, 2.0)); + $display("The minimum of 2.0 and -inf is %f.", min(2.0, minf)); + $display("The minimum of -inf and 2.0 is %f.", min(minf, 2.0)); + $display("The minimum of 2.0 and nan is %f.", min(2.0, nan)); + $display("The minimum of nan and 2.0 is %f.", min(nan, 2.0)); + end + endtask + + // Task to check the max function. + task check_max; + begin + $display("--- Checking the max function ---"); + $display("The maximum of 1.0 and 2.0 is %f.", max(1.0, 2.0)); + $display("The maximum of 2.0 and 1.0 is %f.", max(2.0, 1.0)); + $display("The maximum of 1.0 and -1.0 is %f.", max(1.0, -1.0)); + $display("The maximum of -1.0 and -2.0 is %f.", max(-1.0, -2.0)); + $display("The maximum of 2.0 and inf is %f.", max(2.0, pinf)); + $display("The maximum of inf and 2.0 is %f.", max(pinf, 2.0)); + $display("The maximum of 2.0 and -inf is %f.", max(2.0, minf)); + $display("The maximum of -inf and 2.0 is %f.", max(minf, 2.0)); + $display("The maximum of 2.0 and nan is %f.", max(2.0, nan)); + $display("The maximum of nan and 2.0 is %f.", max(nan, 2.0)); + end + endtask + + // Task to check the power function. + task check_pow; + begin + $display("--- Checking the pow function ---"); + $display(" 0.0 to the power of 0.0 is %f.", pow(zero, zero)); + $display(" 1.0 to the power of 0.0 is %f.", pow(1.0, zero)); + $display("-1.0 to the power of 0.0 is %f.", pow(-1.0, zero)); + $display(" 0.0 to the power of 1.0 is %f.", pow(zero, 1.0)); + $display(" 1.0 to the power of 1.0 is %f.", pow(1.0, 1.0)); + $display("-1.0 to the power of 1.0 is %f.", pow(-1.0, 1.0)); + $display(" 8.0 to the power of 1/3 is %f.", pow(8.0, 1.0/3.0)); + $display(" 8.0 to the power of -1/3 is %f.", pow(8.0, -1.0/3.0)); + $display(" 2.0 to the power of 3.0 is %f.", pow(2.0, 3.0)); + $display(" 2.0 to the power of 5000 is %f.", pow(2.0, 5000)); + $display("-2.0 to the power of 5001 is %f.", pow(-2.0, 5001)); + $display(" 2.0 to the power of -5000 is %f.", pow(2.0, -5000)); + $display(" inf to the power of 0.0 is %f.", pow(pinf, zero)); + $display("-inf to the power of 0.0 is %f.", pow(minf, zero)); + $display(" inf to the power of 1.0 is %f.", pow(pinf, 1.0)); + $display("-inf to the power of 1.0 is %f.", pow(minf, 1.0)); + $display(" inf to the power of 2.0 is %f.", pow(pinf, 2.0)); + $display("-inf to the power of 2.0 is %f.", pow(minf, 2.0)); + $display(" 1.0 to the power of inf is %f.", pow(1.0, pinf)); + $display("-1.0 to the power of inf is %f.", pow(-1.0, pinf)); + $display(" 0.5 to the power of inf is %f.", pow(0.5, pinf)); + $display(" 2.0 to the power of inf is %f.", pow(2.0, pinf)); + $display(" 1.0 to the power of -inf is %f.", pow(1.0, minf)); + $display("-1.0 to the power of -inf is %f.", pow(-1.0, minf)); + $display(" 0.5 to the power of -inf is %f.", pow(0.5, minf)); + $display(" 2.0 to the power of -inf is %f.", pow(2.0, minf)); + $display("-1.0 to the power of -1/3 is %f.", abs(pow(-1.0, -1.0/3.0))); + $display(" 1.0 to the power of nan is %f.", pow(1.0, nan)); + $display(" nan to the power of 1.0 is %f.", abs(pow(nan, 1.0))); + $display(" nan to the power of 0.0 is %f.", pow(nan, zero)); + $display(" nan to the power of nan is %f.", abs(pow(nan, nan))); + end + endtask + + // Task to check the atan of x/y function. + task check_atan2; + begin + $display("--- Checking the atan2 function ---"); + $display("The atan of 0.0/ 0.0 is %f.", atan2(zero, zero)); + $display("The atan of -0.0/ 0.0 is %f.", atan2(mzero, zero)); + $display("The atan of 0.0/-0.0 is %f.", atan2(zero, mzero)); + $display("The atan of -0.0/-0.0 is %f.", atan2(mzero, mzero)); + $display("The atan of 0.0/ 1.0 is %f.", atan2(zero, 1.0)); + $display("The atan of 1.0/ 0.0 is %f.", atan2(1.0, zero)); + $display("The atan of 1.0/ 1.0 is %f.", atan2(1.0, 1.0)); + $display("The atan of 0.0/-1.0 is %f.", atan2(zero, -1.0)); + $display("The atan of -1.0/ 0.0 is %f.", atan2(-1.0, zero)); + $display("The atan of -1.0/-1.0 is %f.", atan2(-1.0, -1.0)); + $display("The atan of inf/ 0.0 is %f.", atan2(pinf, zero)); + $display("The atan of 0.0/ inf is %f.", atan2(zero, pinf)); + $display("The atan of inf/ inf is %f.", atan2(pinf, pinf)); + $display("The atan of -inf/ 0.0 is %f.", atan2(minf, zero)); + $display("The atan of 0.0/-inf is %f.", atan2(zero, minf)); + $display("The atan of -inf/-inf is %f.", atan2(minf, minf)); + $display("The atan of nan/ 0.0 is %f.", abs(atan2(nan, zero))); + $display("The atan of nan/ 1.0 is %f.", abs(atan2(nan, 1.0))); + $display("The atan of 1.0/ nan is %f.", abs(atan2(1.0, nan))); + end + endtask + + // Task to check the distance from origin function. + task check_hypot; + begin + $display("--- Checking the hypot function ---"); + $display("The distance to ( 0.0, 0.0) is %f.", hypot(zero, zero)); + $display("The distance to ( 2.0, 0.0) is %f.", hypot(2.0, zero)); + $display("The distance to ( -2.0, 0.0) is %f.", hypot(-2.0, zero)); + $display("The distance to ( 0.0, 2.0) is %f.", hypot(zero, 2.0)); + $display("The distance to ( 0.0, -2.0) is %f.", hypot(zero, -2.0)); + $display("The distance to ( inf, 0.0) is %f.", hypot(pinf, zero)); + $display("The distance to ( 0.0, inf) is %f.", hypot(zero, pinf)); + $display("The distance to ( -inf, 0.0) is %f.", hypot(minf, zero)); + $display("The distance to ( nan, 0.0) is %f.", abs(hypot(nan, zero))); + $display("The distance to ( 0.0, nan) is %f.", abs(hypot(zero, nan))); + end + endtask + + // Task to check the mathematical constants. + task check_constants; + begin + $display("--- Checking the mathematical constants ---"); + $display(" Pi is %.16f.", `M_PI); + $display(" 2*Pi is %.16f.", `M_TWO_PI); + $display(" Pi/2 is %.16f.", `M_PI_2); + $display(" Pi/4 is %.16f.", `M_PI_4); + $display(" 1/Pi is %.16f.", `M_1_PI); + $display(" 2/Pi is %.16f.", `M_2_PI); + $display("2/sqrt(Pi) is %.16f.", `M_2_SQRTPI); + $display(" e is %.16f.", `M_E); + $display(" log2(e) is %.16f.", `M_LOG2E); + $display(" log10(e) is %.16f.", `M_LOG10E); + $display(" loge(2) is %.16f.", `M_LN2); + $display(" loge(10) is %.16f.", `M_LN10); + $display(" sqrt(2) is %.16f.", `M_SQRT2); + $display(" 1/sqrt(2) is %.16f.", `M_SQRT1_2); + end + endtask +endmodule diff --git a/ivtest/ivltests/test_varray1.v b/ivtest/ivltests/test_varray1.v new file mode 100644 index 000000000..cf4ca5ba8 --- /dev/null +++ b/ivtest/ivltests/test_varray1.v @@ -0,0 +1,97 @@ +// This module generate M single 2*HW-1 bit vector each T time steps + +module stimulus #(parameter W = 8, M = 200, MAX = 256) ( + input bit clk, reset, + output reg [W-1:0] x + ); + +int i; + +initial begin + @(negedge reset); + for (i = 0; i < M; i=i+1) begin + @(negedge clk); + x = {$random} % MAX; + end + +end + + +endmodule + +module test; + parameter M = 200; // number of test vectors + parameter W = 8; // bit width of input vecotrs + parameter T = 10; // for timing + parameter D = 8; // depth of pipeline, MAX of 8 + parameter K = 10; // distance between boundaries of pipeline + parameter S = 2*M*T + 12*D; + parameter MAX = D*K; + + bit clk =0, reset = 0; + + wire [W-1:0] xin; + wire [W-1:0] din = K; + + wire [W-1:0] dout, bout, xout; + + wire [2:0] lin = 3'b111; // -1 in fact + wire [2:0] lout; + + int x_gold; // for computing expected result + + initial forever #T clk = ~clk; + + + + stimulus #(W, M, MAX) stim (.clk(clk), .reset(reset), .x(xin)); + diq_array #(W, D) duv (.clk(clk), .reset(reset), + .din(din), .bin(8'd0), .xin(xin), .lin(lin), + .dout(dout), .bout(bout), .xout(xout), + .lout(lout) ); + + +initial begin: checking + @(negedge reset); + @(posedge clk); + repeat (D) @(negedge clk); + forever begin + @(posedge clk); + #1; + // checking dout + if (dout !== din) begin + $display("ERROR"); + $finish; + end + // checking bout + if (bout !== MAX) begin + $display("ERROR"); + $finish; + end + // checking lout + x_gold = xout-1; // dirty fix, for example xin = 30 muste be reported as 2 + if (lout !== x_gold/K) begin + $display("ERROR"); + $finish; + end + + end +end + + initial begin + doreset(); + #S; + $display("PASSED"); + $finish; + end + + task doreset; + begin + @(negedge clk); + reset = 1; + repeat (5) @(negedge clk); + reset = 0; + end + endtask + +endmodule diff --git a/ivtest/ivltests/test_when_else.v b/ivtest/ivltests/test_when_else.v new file mode 100644 index 000000000..0ad5afe75 --- /dev/null +++ b/ivtest/ivltests/test_when_else.v @@ -0,0 +1,35 @@ +module main; + + reg [1:0] src; + wire [3:0] dst, dst2, dst3; + + foo_entity dut (.data_o(dst), .data_o2(dst2), .data_o3(dst3), .data_i(src)); + + initial begin + src = 2'b00; + #1 if (dst != 4'b0001 || dst2 != 4'bxxxx || dst3 != 4'bxxx) begin + $display("FAILED"); + $finish; + end + + src = 2'b01; + #1 if (dst != 4'b0010 || dst2 != 4'b0101 || dst3 != 4'b0011) begin + $display("FAILED"); + $finish; + end + + src = 2'b10; + #1 if (dst != 4'b0100 || dst2 != 4'b0101 || dst3 != 4'b1100) begin + $display("FAILED"); + $finish; + end + + src = 2'b11; + #1 if (dst != 4'b1000 || dst2 != 4'b0101 || dst3 != 4'b1100) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/test_width.v b/ivtest/ivltests/test_width.v new file mode 100644 index 000000000..e3731dea5 --- /dev/null +++ b/ivtest/ivltests/test_width.v @@ -0,0 +1,127 @@ +// Released under GPL2.0 +// (c) 2002 Tom Verbeure + +module main; + + integer myInt; + reg [39:0] myReg40; + reg [0:39] myReg40r; + reg [0:38] myReg39r; + reg [13:0] myReg14; + reg [7:0] myReg8; + reg [31:0] myReg32; + + initial begin + $display("============================ myReg14 = -10"); + myReg14 = -10; + + $display(">|16374|"); + $display("*|%d|", myReg14); + $display("*|%0d|", myReg14); + $display("*|",myReg14,"|"); + + $display("============================ myReg14 = 65"); + myReg14 = 65; + + $display(">| 65|"); + $display("*|%d|", myReg14); + $display("*|",myReg14,"|"); + $display(">|65|"); + $display("*|%0d|", myReg14); + + $display(">|0041|"); + $display("*|%h|", myReg14); + $display(">|41|"); + $display("*|%0h|", myReg14); + + $display(">|00101|"); + $display("*|%o|", myReg14); + $display(">|101|"); + $display("*|%0o|", myReg14); + + $display(">|00000001000001|"); + $display("*|%b|", myReg14); + $display(">|1000001|"); + $display("*|%0b|", myReg14); + + $display(">| A|"); + $display("*|%s|", myReg14); + $display(">|A|"); + $display("*|%0s|", myReg14); + + $display("============================ myInt = -10"); + myInt = -10; + $display(">| -10|"); + $display("*|%d|", myInt); + $display("*|",myInt,"|"); + $display(">|-10|"); + $display("*|%0d|", myInt); + + $display(">|fffffff6|"); + $display("*|%h|", myInt); + $display("*|%0h|", myInt); + + $display(">|37777777766|"); + $display("*|%o|", myInt); + $display("*|%0o|", myInt); + + $display(">|11111111111111111111111111110110|"); + $display("*|%b|", myInt); + $display("*|%0b|", myInt); + + $display("============================ myReg32 = -10"); + myReg32 = -10; + $display(">|4294967286|"); + $display("*|%d|", myReg32); + $display("*|%0d|", myReg32); + $display("*|",myReg32,"|"); + + $display(">|fffffff6|"); + $display("*|%h|", myReg32); + $display("*|%0h|", myReg32); + + $display(">|37777777766|"); + $display("*|%o|", myReg32); + $display("*|%0o|", myReg32); + + $display("============================ myInt = 65"); + myInt = 65; + $display(">| 65|"); + $display("*|%d|", myInt); + $display("*|",myInt,"|"); + $display(">|65|"); + $display("*|%0d|", myInt); + + $display(">|00000041|"); + $display("*|%h|", myInt); + $display(">|41|"); + $display("*|%0h|", myInt); + + $display(">|00000000101|"); + $display("*|%o|", myInt); + $display(">|101|"); + $display("*|%0o|", myInt); + + $display(">|00000000000000000000000001000001|"); + $display("*|%b|", myInt); + $display(">|1000001|"); + $display("*|%0b|", myInt); + + $display("*| A|"); + $display(">|%s|", myInt); + $display("*|A|"); + $display(">|%0s|", myInt); + + $display("============================ Print \" A\""); + $display("*| A|"); + $display(">|%s|", " A"); + $display(">|%0s|", " A"); + + $display("============================ Print $time"); + $display("*| 0|"); + $display(">|%t|", $time); + $display("*|0|"); + $display(">|%0t|", $time); + + end +endmodule diff --git a/ivtest/ivltests/test_work14.v b/ivtest/ivltests/test_work14.v new file mode 100644 index 000000000..54f481d2c --- /dev/null +++ b/ivtest/ivltests/test_work14.v @@ -0,0 +1,28 @@ +module test14; +import work14_pkg::*; +bit clk = 0; + +parameter longint maxvalue = 2**29 + 17; +logic [29:0] mvalue; +logic [29:0] lvalue; + +initial begin : clkgen forever #10 clk = ~clk; end + +assign lvalue = maxvalue; + +work14_comp #(.max_out_val(maxvalue)) duv (.clk_i(clk), .val(mvalue)); + +initial begin + @(posedge clk); + #1; + if (lvalue !== mvalue) $display ("ERROR due to mismatch between lvalue=%d and mvalue=%d", lvalue, mvalue); + @(posedge clk); + #1; + if (lvalue !== mvalue) $display ("ERROR due to mismatch between lvalue=%d and mvalue=%d", lvalue, mvalue); + #5; + $display ("PASSED"); + $finish; +end + + +endmodule diff --git a/ivtest/ivltests/time1.v b/ivtest/ivltests/time1.v new file mode 100644 index 000000000..344f75b20 --- /dev/null +++ b/ivtest/ivltests/time1.v @@ -0,0 +1,65 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - Verify glitch doesn't propagate. +// +// D: + +module main (); + +reg a; +reg error; +wire c; +reg d; + +assign c = a; +always @(c) + #5 d = c; + + + +always @(posedge d) + error <= 1'b1; + +initial + begin +/* + $dumpfile("/root/testsuite/dump.vcd"); + $dumpvars(0,main); + $dumpon; +*/ + a =1'b0; + error = 1'b0; + #10; + + a = 1'b1; + # 3; + a = 1'b0; + # 10; + + if(error) + $display("FAILED"); + else + $display("PASSED"); + #5; + $finish ; + end + + +endmodule diff --git a/ivtest/ivltests/time2.v b/ivtest/ivltests/time2.v new file mode 100644 index 000000000..ae85cb708 --- /dev/null +++ b/ivtest/ivltests/time2.v @@ -0,0 +1,53 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Check posedge vector - should use bit 0 only. Doesn't work with XL + +module time2 (); + +reg [3:0] clock; +reg [3:0] b; +reg [3:0] count; + +initial + begin + b = 4'b1111; + count = 0; + for (clock = 0; clock<=10; clock = clock + 1) + begin + $display("time = %t, clock = %h",$time,clock); + #10; + end + end + +always @(posedge clock & b) + begin + count = count+1; + $display(" edge ! time = %t, count = %h",$time,count); + end + +initial + begin + #1000; + if(count != 6) + $display("FAILED - vect[0] clock detect count=%d",count); + else + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/time3.v b/ivtest/ivltests/time3.v new file mode 100644 index 000000000..6781e92c7 --- /dev/null +++ b/ivtest/ivltests/time3.v @@ -0,0 +1,65 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// SDW - time3.v - Verify glitch doesn't propagate with non-blocking +// +// D: + +module main (); + +reg a; +reg error; +wire c; +reg d; + +assign c = a; +always @(c) + #5 d <= c; + + + +always @(posedge d) + error <= 1'b1; + +initial + begin +/* + $dumpfile("/root/testsuite/dump.vcd"); + $dumpvars(0,main); + $dumpon; +*/ + a =1'b0; + error = 1'b0; + #10; + + a = 1'b1; + # 3; + a = 1'b0; + # 10; + + if(error) + $display("FAILED"); + else + $display("PASSED"); + #5; + $finish; + end + + +endmodule diff --git a/ivtest/ivltests/time4.v b/ivtest/ivltests/time4.v new file mode 100644 index 000000000..9b6a78c94 --- /dev/null +++ b/ivtest/ivltests/time4.v @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This module tests time variables + */ +module main; + + time t; + + initial begin + if (t !== 64'bx) begin + $display("FAILED -- t == %b", t); + $finish; + end + + #35 t = $time; + + #5 if (t !== 35) begin + $display("FAILED -- t == %b (should be 35)", t); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/time5.v b/ivtest/ivltests/time5.v new file mode 100644 index 000000000..fb96cc96c --- /dev/null +++ b/ivtest/ivltests/time5.v @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +/* + * This program tests that a non-integer delay, in the absence of any + * timescale values, will round properly. A 2.4 delay rounds to 2, and + * a 2.6 delay rounds to 3. + */ + +module main; + + reg clk; + reg out1, out2; + time time1; + time time2; + + always @(posedge clk) #2.4 begin + $display($time,, "set out1 == 1"); + time1 = $time; + out1 = 1; + end + + always @(posedge clk) #2.6 begin + $display($time,, "set out2 == 1"); + time2 = $time; + out2 = 1; + end + + initial begin + clk = 0; + out1 = 0; + out2 = 0; + time1 = 0; + time2 = 0; + + #1 if (out1 !== 0) begin + $display("FAILED -- out1 is not 0: %b", out1); + $finish; + end + + clk = 1; + + #3 if (out1 !== 1) begin + $display("FAILED -- out is not 1 at time 3: %b", out1); + $finish; + end + + if (time1 != 3) begin + $display("FAILED -- time1 = %d", time1); + $finish; + end + + #1 if (time2 != 4) begin + $display("FAILED -- time2 = %d", time2); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/time6.v b/ivtest/ivltests/time6.v new file mode 100644 index 000000000..ca99635d4 --- /dev/null +++ b/ivtest/ivltests/time6.v @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +/* + * This program tests that a non-integer delay gets its extra + * precision accounted for if the timescale supports it. In this + * example, set the units to 1ms, but set the precision so that the + * numbers can be given accurate to .1ms. This should cause a delay + * of 2.4 and 2.6 to really be different. + */ + +`timescale 1ms / 100us + +module main; + + reg clk; + reg out1, out2; + time time1; + time time2; + + always @(posedge clk) #2.4 begin + $display($time,, "set out1 == 1"); + time1 = $simtime; + out1 = 1; + end + + always @(posedge clk) #2.6 begin + $display($time,, "set out2 == 1"); + time2 = $simtime; + out2 = 1; + end + + initial begin + clk = 0; + out1 = 0; + out2 = 0; + time1 = 0; + time2 = 0; + + #1 if (out1 !== 0) begin + $display("FAILED -- out1 is not 0: %b", out1); + $finish; + end + + clk = 1; + + #3 if (out1 !== 1) begin + $display("FAILED -- out is not 1 at time 3: %b", out1); + $finish; + end + + if (time1 != 34) begin + $display("FAILED -- time1 = %d", time1); + $finish; + end + + #1 if (time2 != 36) begin + $display("FAILED -- time2 = %d", time2); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/time6b.v b/ivtest/ivltests/time6b.v new file mode 100644 index 000000000..c8f8b3dbd --- /dev/null +++ b/ivtest/ivltests/time6b.v @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +/* + * This program tests that a non-integer delay gets its extra + * precision accounted for if the timescale supports it. In this + * example, set the units to 1ms, but set the precision so that the + * numbers can be given accurate to .1ms. This should cause a delay + * of 2.4 and 2.6 to really be different. + */ + +`timescale 1ms / 100us + +module main; + reg err; + reg clk; + reg out1, out2; + realtime time1; + realtime time2; + + real eps; + + always @(posedge clk) #2.4 begin + $display($time,,$realtime, " set out1 == 1"); + time1 = $realtime; + out1 = 1; + end + + always @(posedge clk) #2.6 begin + $display($time,,$realtime, " set out2 == 1"); + time2 = $realtime; + out2 = 1; + end + + initial begin + clk = 0; + out1 = 0; + out2 = 0; + time1 = 0; + time2 = 0; + err = 0; + $timeformat(-3,1,"ms",5); + + #1 if (out1 !== 0) begin + $display("Error -- out1 s/b 0 at time $time but is=%x", out1); + err =1 ; + end + + clk = 1; + + #3 if (out1 !== 1) begin + $display("Error -- out1 s/b 1 at time $time but is=%x", out1); + err =1 ; + end + + eps = time1 - 3.4; + if (eps < 0.0) + eps = 0.0 - eps; + + if (eps > 0.0001) begin + $display("Error -- time1 s/b 3.4 but is=%t", time1); + + err =1 ; + end + + #1 eps = time2 - 3.6; + if (eps < 0.0) + eps = 0.0 - eps; + if (eps > 0.0001) begin + $display("Error -- time2 s/b 3.6 but is=%t, ", time2); + err =1 ; + end + + if(err == 0) + $display("PASSED"); + else + $display("FAILED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/time6c.v b/ivtest/ivltests/time6c.v new file mode 100644 index 000000000..1f1c222bf --- /dev/null +++ b/ivtest/ivltests/time6c.v @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +/* + * This program tests that a non-integer delay gets its extra + * precision accounted for if the timescale supports it. In this + * example, set the units to 1ms, but set the precision so that the + * numbers can be given accurate to .1ms. This should cause a delay + * of 2.4 and 2.6 to really be different. + */ + +`timescale 1ms / 100us + +module main; + reg err; + reg clk; + reg out1, out2; + realtime time1; + realtime time2; + + real eps; + + always @(posedge clk) #2.4 begin + $display($time,,$realtime, " set out1 == 1"); + time1 = $realtime; + out1 = 1; + end + + always @(posedge clk) #2.6 begin + $display($time,,$realtime, " set out2 == 1"); + time2 = $realtime; + out2 = 1; + end + + initial begin + clk = 0; + out1 = 0; + out2 = 0; + time1 = 0; + time2 = 0; + err = 0; + $timeformat(-3,1,"ms",5); + + #1 if (out1 !== 0) begin + $display("Error -- out1 s/b 0 at time $time but is=%x", out1); + err =1 ; + end + + clk = 1; + + #3 if (out1 !== 1) begin + $display("Error -- out1 s/b 1 at time $time but is=%x", out1); + err =1 ; + end + + eps = time1 - 3.4; + if (eps < 0.0) + eps = 0.0 - eps; + + if (eps > 0.0001) begin + $display("Error -- time1 s/b 3.4 but is=%t", time1); + + err =1 ; + end + + #1 eps = time2 - 3.6; + if (eps < 0.0) + eps = 0.0 - eps; + if (eps > 0.0001) begin + $display("Error -- time2 s/b 3.6 but is=%t, ", time2); + err =1 ; + end + + // Use a gold file to check this version. + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/time7.v b/ivtest/ivltests/time7.v new file mode 100644 index 000000000..26fde4065 --- /dev/null +++ b/ivtest/ivltests/time7.v @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2000 Nadim Shaikli + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* This is made up from PR#63 */ +module main; + + reg one, clk; + reg [1:0] a, b, c, passed; + reg [7:0] count; + + always + #1 one = ~one; + + // generate a clock + always + #10 clk = ~clk; + + initial + begin + $display ("\n<< BEGIN >>"); + one = 1'b1; + clk = 1'b0; + passed = 2'b00; + count = 0; + #15 a[1:0] = 2'b01; + #10 a[1:0] = 2'b10; + #20 $display ("\n<< END >>"); + if (passed == 2) + $display ("PASSED"); + else + $display ("FAILED"); + $finish; + end + + always @(clk) + begin + // Problematic lines below -- comment them out to see timing skew + b[1:0] <= #2.5 a[1:0]; + c[1:0] <= #7.8 a[1:0]; + end + + always @(one) + count[7:0] <= count + 1; + + always @(count) + begin + case ( count ) + 'd25: + if (b[1:0] == 2'b01) + begin + $display ("@ %0t - Got ONE", $time); + passed = passed + 1; + end + else + $display ("@ %0t - failure", $time); + 'd29: + if (b[1:0] == 2'b01) + begin + $display ("@ %0t - Got ONE", $time); + passed = passed + 1; + end + else + $display ("@ %0t - failure", $time); + default: + $display ("@ %0t - no count", $time); + endcase + end + + // Waves definition +// initial +// begin +// $recordvars("primitives", "drivers"); +// $dumpfile("out.dump"); +// $dumpvars(5, main); +// Line below ought to work +// $dumpvars; +// end + +endmodule // main diff --git a/ivtest/ivltests/time8.v b/ivtest/ivltests/time8.v new file mode 100644 index 000000000..e1e9d6e31 --- /dev/null +++ b/ivtest/ivltests/time8.v @@ -0,0 +1,52 @@ +/* + * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg [1:0] out; + + initial begin + out = 2'b0; + + if (out !== 2'b0) begin + $display("FAILED to initialize: out == %b", out); + $finish; + end + + out <= #5 2'b1; + + if (out !== 2'b0) begin + $display("FAILED -- changed immediately: out == %b", out); + $finish; + end + + #4 if (out !== 2'b0) begin + $display("FAILED -- changed too soon: out == %b", out); + $finish; + end + + #2 if (out !== 2'b1) begin + $display("FAILED to change after delay: out == %b", out); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/timebase.vhd b/ivtest/ivltests/timebase.vhd new file mode 100644 index 000000000..8d11a2f11 --- /dev/null +++ b/ivtest/ivltests/timebase.vhd @@ -0,0 +1,45 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +-- The operation is: +-- 1) An internal counter is initilaised to zero after a reset is received. +-- 2) An enable allows an internal running counter to count clock pulses +-- 3) A tick signal output is generated when a the number of pulses accumulated +-- are equal to a specified parameter + + +entity TimeBase is + generic (N: in Natural := 12; VALUE: Natural := 1999); + port( + CLOCK : in std_logic; -- input clock of 20MHz + TICK : out std_logic; -- out 1 sec timebase signal + RESET : in std_logic; -- master reset signal (active high) + ENABLE : in std_logic; + COUNT_VALUE: out std_logic_vector (N-1 downto 0) + ); +end TimeBase; + +architecture TimeBase_rtl of TimeBase is + + signal RunningCounter : std_logic_vector(N-1 downto 0); -- this is the N bit free running counter to allow a big count +begin + + RunningCounterProcess : process (CLOCK) + begin + if ( CLOCK'event and CLOCK = '1') then + if (RESET = '1') then + RunningCounter <= (others => '0'); + elsif ( ENABLE = '1') then + RunningCounter <= RunningCounter + 1; + end if; + else + RunningCounter <= RunningCounter; + end if; + end process; + + TICK <= '1' when (RunningCounter = VALUE) else '0'; + +COUNT_VALUE <= RunningCounter; + +end TimeBase_rtl; diff --git a/ivtest/ivltests/timeform1.v b/ivtest/ivltests/timeform1.v new file mode 100644 index 000000000..330275158 --- /dev/null +++ b/ivtest/ivltests/timeform1.v @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + */ +`timescale 1ns / 1ns + +module main; + + initial begin + #3 $display("$time = %t (unformatted)", $time); + $timeformat(-6, 6, "ns", 12); + $display("$time = %t (-6,6)", $time); + $timeformat(-6, 1, "ns", 12); + $display("$time = %t (-6,1)", $time); + end + + +endmodule // main diff --git a/ivtest/ivltests/timeform2.v b/ivtest/ivltests/timeform2.v new file mode 100644 index 000000000..9ebcfe6ae --- /dev/null +++ b/ivtest/ivltests/timeform2.v @@ -0,0 +1,34 @@ +// +// Copyright (c) 2003 Steve Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +`timescale 1ns / 1ps + +module main; + + task test; + $display("time within task: %t", $time); + endtask // test + + initial begin + $timeformat(-9, 3, "ns", 6); + #1 $display("time within module: %t", $time); + test; + end + +endmodule diff --git a/ivtest/ivltests/timeliteral.v b/ivtest/ivltests/timeliteral.v new file mode 100644 index 000000000..219d1cda9 --- /dev/null +++ b/ivtest/ivltests/timeliteral.v @@ -0,0 +1,124 @@ +/* + * From IEEE 1800-2012 + * + * 5.8 Time literals + * + * Time is written in integer or fixed-point format, followed without a space by a + * time unit ( fs ps ns us ms s ). + * For example: + * 2.1ns + * 40ps + * The time literal is interpreted as a realtime value scaled to the current time + * unit and rounded to the current time precision. + */ + +module same; + timeunit 1ps; + timeprecision 1ps; + + function logic check_time; + realtime result; + + check_time = 1'b1; + + result = 1ns; + if (result != 1000.0) begin + $display("Failed-same: Expected 1ns to be rounded to 1000.0, got %f", result); + check_time = 1'b0; + end + + result = 1ps; + if (result != 1.0) begin + $display("Failed-same: Expected 1ps to be rounded to 1.0, got %f", result); + check_time = 1'b0; + end + + result = 0.5ps; + if (result != 1.0) begin + $display("Failed-same: Expected 0.5ps to be rounded to 1.0, got %f", result); + check_time = 1'b0; + end + + result = 0.499ps; + if (result != 0.0) begin + $display("Failed-same: Expected 0.49ps to be rounded to 0.0, got %f", result); + check_time = 1'b0; + end + endfunction +endmodule + +module max; + timeunit 100s; + timeprecision 1fs; + + function logic check_time; + realtime result; + + check_time = 1'b1; + + result = 1s; + if (result != 1e-2) begin + $display("Failed-max: Expected 1s to be rounded to 1.0e-2, got %f", result); + check_time = 1'b0; + end + + result = 0.5fs; + if (result != 1e-17) begin + $display("Failed-max: Expected 0.5fs to be rounded to 1.0e-17, got %f", result); + check_time = 1'b0; + end + + result = 0.499fs; + if (result != 0.0) begin + $display("Failed-max: Expected 0.49fs to be rounded to 0.0, got %f", result); + check_time = 1'b0; + end + endfunction +endmodule + +module top; + timeunit 1ns; + timeprecision 1ps; + + realtime result; + logic passed; + + initial begin + passed = 1'b1; + + result = 1ns; + if (result != 1.0) begin + $display("Failed: Expected 1ns to be rounded to 1.0, got %f", result); + passed = 1'b0; + end + + result = 1ps; + if (result != 0.001) begin + $display("Failed: Expected 1ps to be rounded to 0.001, got %f", result); + passed = 1'b0; + end + + result = 1.23456789ps; + if (result != 0.001) begin + $display("Failed: Expected 1.23456789ps to be rounded to 0.001, got %f", result); + passed = 1'b0; + end + + result = 0.5ps; + if (result != 0.001) begin + $display("Failed: Expected 0.5ps to be rounded to 0.001, got %f", result); + passed = 1'b0; + end + + result = 0.499ps; + if (result != 0.0) begin + $display("Failed: Expected 0.49ps to be rounded to 0.0, got %f", result); + passed = 1'b0; + end + + passed &= same.check_time(); + passed &= max.check_time(); + + if (passed) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/timescale1.v b/ivtest/ivltests/timescale1.v new file mode 100644 index 000000000..a4c892afe --- /dev/null +++ b/ivtest/ivltests/timescale1.v @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test checks that times within modules are scaled up to the + * precision of the simulation. + */ + +`timescale 100us / 1us +module slow (out); + output out; + reg out; + + initial begin + #0 out = 0; + #1 out = 1; + end + +endmodule // slow + + +`timescale 10us / 1us +module fast (out); + output out; + reg out; + + initial begin + #0 out = 0; + #1 out = 1; + end + +endmodule // fast + +`timescale 1us / 1us +module main; + + wire slow, fast; + + slow m1 (slow); + fast m2 (fast); + + initial begin + #5 + if (slow !== 1'b0) begin + $display("FAILED"); + $finish; + end + + if (fast !== 1'b0) begin + $display("FAILED"); + $finish; + end + + #10 + if (slow !== 1'b0) begin + $display("FAILED"); + $finish; + end + + if (fast !== 1'b1) begin + $display("FAILED"); + $finish; + end + + #80 + if (slow !== 1'b0) begin + $display("FAILED"); + $finish; + end + + if (fast !== 1'b1) begin + $display("FAILED"); + $finish; + end + + #10 + if (slow !== 1'b1) begin + $display("FAILED"); + $finish; + end + + if (fast !== 1'b1) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/timescale2.v b/ivtest/ivltests/timescale2.v new file mode 100644 index 000000000..0ebe1087d --- /dev/null +++ b/ivtest/ivltests/timescale2.v @@ -0,0 +1,23 @@ +`timescale 1ns/1ns +module main; + + submodule test(); + +endmodule // main + +`timescale 10ns/1ns +module submodule; + + reg [63:0] val; + initial begin + #1 $display("$time = %0d", $time); + val = $time; + if (val !== 64'd1) begin + $display("FAILED -- value is %0d (should be 1)", val); + $finish; + end + $display("PASSED"); + end + + +endmodule // submodule diff --git a/ivtest/ivltests/timescale3.v b/ivtest/ivltests/timescale3.v new file mode 100644 index 000000000..11f259a0e --- /dev/null +++ b/ivtest/ivltests/timescale3.v @@ -0,0 +1,3 @@ +// This is an error since the timeunit is less than the precision. + +`timescale 1ns/10ns diff --git a/ivtest/ivltests/tran-keeper.v b/ivtest/ivltests/tran-keeper.v new file mode 100644 index 000000000..5b4e02dde --- /dev/null +++ b/ivtest/ivltests/tran-keeper.v @@ -0,0 +1,49 @@ +module main; + + + // Model a pin with a weak keeper circuit. The way this works: + // If the pin value is 1, then attach a weak1 pullup, but + // if the pin value is 0, attach a weak0 pulldown. + wire pin; + pullup (weak1) (keep1); + pulldown (weak0) (keep0); + tranif1 (pin, keep1, pin); + tranif0 (pin, keep0, pin); + + // Logic to drive a value onto a pin. + reg value, enable; + bufif1 (pin, value, enable); + + initial begin + value = 0; + enable = 1; + #1 if (pin !== 0) begin + $display("FAILED -- value=%b, enable=%b, pin=%b", value, enable, pin); + $finish; + end + + // pin should hold its value after the drive is removed. + enable = 0; + #1 if (pin !== 0) begin + $display("FAILED -- value=%b, enable=%b, pin=%b", value, enable, pin); + $finish; + end + + value = 1; + enable = 1; + #1 if (pin !== 1) begin + $display("FAILED -- value=%b, enable=%b, pin=%b", value, enable, pin); + $finish; + end + + // pin should hold its value after the drive is removed. + enable = 0; + #1 if (pin !== 1) begin + $display("FAILED -- value=%b, enable=%b, pin=%b", value, enable, pin); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/tran.v b/ivtest/ivltests/tran.v new file mode 100644 index 000000000..ea9e70090 --- /dev/null +++ b/ivtest/ivltests/tran.v @@ -0,0 +1,122 @@ +module test(); + +reg a, b; + +wire a1, a2, a3, a4, a5, a6, a7; + +assign (supply1, supply0) a1 = a; + +tran t1(a1, a2); +tran t2(a2, a3); +tran t3(a3, a4); +tran t4(a4, a5); +tran t5(a5, a6); +tran t6(a6, a7); + +wire a11, a12, a13, a14, a15, b11, b12, b13, b14, b15; +wire a21, a22, a23, a24, a25, b21, b22, b23, b24, b25; +wire a31, a32, a33, a34, a35, b31, b32, b33, b34, b35; +wire a41, a42, a43, a44, a45, b41, b42, b43, b44, b45; +wire a51, a52, a53, a54, a55, b51, b52, b53, b54, b55; + +assign (supply1, supply0) a11 = a, b11 = b; +assign (supply1, strong0) a12 = a, b12 = b; +assign (supply1, pull0) a13 = a, b13 = b; +assign (supply1, weak0) a14 = a, b14 = b; +assign (supply1, highz0) a15 = a, b15 = b; + +assign (strong1, supply0) a21 = a, b21 = b; +assign (strong1, strong0) a22 = a, b22 = b; +assign (strong1, pull0) a23 = a, b23 = b; +assign (strong1, weak0) a24 = a, b24 = b; +assign (strong1, highz0) a25 = a, b25 = b; + +assign ( pull1, supply0) a31 = a, b31 = b; +assign ( pull1, strong0) a32 = a, b32 = b; +assign ( pull1, pull0) a33 = a, b33 = b; +assign ( pull1, weak0) a34 = a, b34 = b; +assign ( pull1, highz0) a35 = a, b35 = b; + +assign ( weak1, supply0) a41 = a, b41 = b; +assign ( weak1, strong0) a42 = a, b42 = b; +assign ( weak1, pull0) a43 = a, b43 = b; +assign ( weak1, weak0) a44 = a, b44 = b; +assign ( weak1, highz0) a45 = a, b45 = b; + +assign ( highz1, supply0) a51 = a, b51 = b; +assign ( highz1, strong0) a52 = a, b52 = b; +assign ( highz1, pull0) a53 = a, b53 = b; +assign ( highz1, weak0) a54 = a, b54 = b; + +tran t11(a11, b11); +tran t12(a12, b12); +tran t13(a13, b13); +tran t14(a14, b14); +tran t15(a15, b15); + +tran t21(a21, b21); +tran t22(a22, b22); +tran t23(a23, b23); +tran t24(a24, b24); +tran t25(a25, b25); + +tran t31(a31, b31); +tran t32(a32, b32); +tran t33(a33, b33); +tran t34(a34, b34); +tran t35(a35, b35); + +tran t41(a41, b41); +tran t42(a42, b42); +tran t43(a43, b43); +tran t44(a44, b44); +tran t45(a45, b45); + +tran t51(a51, b51); +tran t52(a52, b52); +tran t53(a53, b53); +tran t54(a54, b54); +tran t55(a55, b55); + +task display_strengths; + +input ta, tb; + +begin + a = ta; + b = tb; + #1; + $display("a = %b b = %b", a, b); + $display("a1(%v) a2(%v) a3(%v) a4(%v) a5(%v) a6(%v) a7(%v)", a1, a2, a3, a4, a5, a6, a7); + $display("t11(%v %v) t12(%v %v) t13(%v %v) t14(%v %v) t15(%v %v)", a11, b11, a12, b12, a13, b13, a14, b14, a15, b15); + $display("t21(%v %v) t22(%v %v) t23(%v %v) t24(%v %v) t25(%v %v)", a21, b21, a22, b22, a23, b23, a24, b24, a25, b25); + $display("t31(%v %v) t32(%v %v) t33(%v %v) t34(%v %v) t35(%v %v)", a31, b31, a32, b32, a33, b33, a34, b34, a35, b35); + $display("t41(%v %v) t42(%v %v) t43(%v %v) t44(%v %v) t45(%v %v)", a41, b41, a42, b42, a43, b43, a44, b44, a45, b45); + $display("t51(%v %v) t52(%v %v) t53(%v %v) t54(%v %v) t55(%v %v)", a51, b51, a52, b52, a53, b53, a54, b54, a55, b55); +end + +endtask + +initial begin + display_strengths(1'bz, 1'bz); + display_strengths(1'bx, 1'bz); + display_strengths(1'b0, 1'bz); + display_strengths(1'b1, 1'bz); + + display_strengths(1'bz, 1'bx); + display_strengths(1'bx, 1'bx); + display_strengths(1'b0, 1'bx); + display_strengths(1'b1, 1'bx); + + display_strengths(1'bz, 1'b0); + display_strengths(1'bx, 1'b0); + display_strengths(1'b0, 1'b0); + display_strengths(1'b1, 1'b0); + + display_strengths(1'bz, 1'b1); + display_strengths(1'bx, 1'b1); + display_strengths(1'b0, 1'b1); + display_strengths(1'b1, 1'b1); +end + +endmodule diff --git a/ivtest/ivltests/tranif0.v b/ivtest/ivltests/tranif0.v new file mode 100644 index 000000000..c27b2fcf6 --- /dev/null +++ b/ivtest/ivltests/tranif0.v @@ -0,0 +1,183 @@ +module test(); + +reg a, b, en; + +wire a1, a2, a3, a4, a5, a6, a7; + +assign (supply1, supply0) a1 = a; + +tranif0 t1(a1, a2, en); +tranif0 t2(a2, a3, en); +tranif0 t3(a3, a4, en); +tranif0 t4(a4, a5, en); +tranif0 t5(a5, a6, en); +tranif0 t6(a6, a7, en); + +wire a11, a12, a13, a14, a15, b11, b12, b13, b14, b15; +wire a21, a22, a23, a24, a25, b21, b22, b23, b24, b25; +wire a31, a32, a33, a34, a35, b31, b32, b33, b34, b35; +wire a41, a42, a43, a44, a45, b41, b42, b43, b44, b45; +wire a51, a52, a53, a54, a55, b51, b52, b53, b54, b55; + +assign (supply1, supply0) a11 = a, b11 = b; +assign (supply1, strong0) a12 = a, b12 = b; +assign (supply1, pull0) a13 = a, b13 = b; +assign (supply1, weak0) a14 = a, b14 = b; +assign (supply1, highz0) a15 = a, b15 = b; + +assign (strong1, supply0) a21 = a, b21 = b; +assign (strong1, strong0) a22 = a, b22 = b; +assign (strong1, pull0) a23 = a, b23 = b; +assign (strong1, weak0) a24 = a, b24 = b; +assign (strong1, highz0) a25 = a, b25 = b; + +assign ( pull1, supply0) a31 = a, b31 = b; +assign ( pull1, strong0) a32 = a, b32 = b; +assign ( pull1, pull0) a33 = a, b33 = b; +assign ( pull1, weak0) a34 = a, b34 = b; +assign ( pull1, highz0) a35 = a, b35 = b; + +assign ( weak1, supply0) a41 = a, b41 = b; +assign ( weak1, strong0) a42 = a, b42 = b; +assign ( weak1, pull0) a43 = a, b43 = b; +assign ( weak1, weak0) a44 = a, b44 = b; +assign ( weak1, highz0) a45 = a, b45 = b; + +assign ( highz1, supply0) a51 = a, b51 = b; +assign ( highz1, strong0) a52 = a, b52 = b; +assign ( highz1, pull0) a53 = a, b53 = b; +assign ( highz1, weak0) a54 = a, b54 = b; + +tranif0 t11(a11, b11, en); +tranif0 t12(a12, b12, en); +tranif0 t13(a13, b13, en); +tranif0 t14(a14, b14, en); +tranif0 t15(a15, b15, en); + +tranif0 t21(a21, b21, en); +tranif0 t22(a22, b22, en); +tranif0 t23(a23, b23, en); +tranif0 t24(a24, b24, en); +tranif0 t25(a25, b25, en); + +tranif0 t31(a31, b31, en); +tranif0 t32(a32, b32, en); +tranif0 t33(a33, b33, en); +tranif0 t34(a34, b34, en); +tranif0 t35(a35, b35, en); + +tranif0 t41(a41, b41, en); +tranif0 t42(a42, b42, en); +tranif0 t43(a43, b43, en); +tranif0 t44(a44, b44, en); +tranif0 t45(a45, b45, en); + +tranif0 t51(a51, b51, en); +tranif0 t52(a52, b52, en); +tranif0 t53(a53, b53, en); +tranif0 t54(a54, b54, en); +tranif0 t55(a55, b55, en); + +task display_strengths; + +input ta, tb, ten; + +begin + a = ta; + b = tb; + en = ten; + #1; + $display("a = %b b = %b en = %b", a, b, en); + $display("a1(%v) a2(%v) a3(%v) a4(%v) a5(%v) a6(%v) a7(%v)", a1, a2, a3, a4, a5, a6, a7); + $display("t11(%v %v) t12(%v %v) t13(%v %v) t14(%v %v) t15(%v %v)", a11, b11, a12, b12, a13, b13, a14, b14, a15, b15); + $display("t21(%v %v) t22(%v %v) t23(%v %v) t24(%v %v) t25(%v %v)", a21, b21, a22, b22, a23, b23, a24, b24, a25, b25); + $display("t31(%v %v) t32(%v %v) t33(%v %v) t34(%v %v) t35(%v %v)", a31, b31, a32, b32, a33, b33, a34, b34, a35, b35); + $display("t41(%v %v) t42(%v %v) t43(%v %v) t44(%v %v) t45(%v %v)", a41, b41, a42, b42, a43, b43, a44, b44, a45, b45); + $display("t51(%v %v) t52(%v %v) t53(%v %v) t54(%v %v) t55(%v %v)", a51, b51, a52, b52, a53, b53, a54, b54, a55, b55); +end + +endtask + +initial begin + display_strengths(1'bz, 1'bz, 1'bz); + display_strengths(1'bz, 1'bz, 1'bx); + display_strengths(1'bz, 1'bz, 1'b0); + display_strengths(1'bz, 1'bz, 1'b1); + + display_strengths(1'bx, 1'bz, 1'bz); + display_strengths(1'bx, 1'bz, 1'bx); + display_strengths(1'bx, 1'bz, 1'b0); + display_strengths(1'bx, 1'bz, 1'b1); + + display_strengths(1'b0, 1'bz, 1'bz); + display_strengths(1'b0, 1'bz, 1'bx); + display_strengths(1'b0, 1'bz, 1'b0); + display_strengths(1'b0, 1'bz, 1'b1); + + display_strengths(1'b1, 1'bz, 1'bz); + display_strengths(1'b1, 1'bz, 1'bx); + display_strengths(1'b1, 1'bz, 1'b0); + display_strengths(1'b1, 1'bz, 1'b1); + + display_strengths(1'bz, 1'bx, 1'bz); + display_strengths(1'bz, 1'bx, 1'bx); + display_strengths(1'bz, 1'bx, 1'b0); + display_strengths(1'bz, 1'bx, 1'b1); + + display_strengths(1'bx, 1'bx, 1'bz); + display_strengths(1'bx, 1'bx, 1'bx); + display_strengths(1'bx, 1'bx, 1'b0); + display_strengths(1'bx, 1'bx, 1'b1); + + display_strengths(1'b0, 1'bx, 1'bz); + display_strengths(1'b0, 1'bx, 1'bx); + display_strengths(1'b0, 1'bx, 1'b0); + display_strengths(1'b0, 1'bx, 1'b1); + + display_strengths(1'b1, 1'bx, 1'bz); + display_strengths(1'b1, 1'bx, 1'bx); + display_strengths(1'b1, 1'bx, 1'b0); + display_strengths(1'b1, 1'bx, 1'b1); + + display_strengths(1'bz, 1'b0, 1'bz); + display_strengths(1'bz, 1'b0, 1'bx); + display_strengths(1'bz, 1'b0, 1'b0); + display_strengths(1'bz, 1'b0, 1'b1); + + display_strengths(1'bx, 1'b0, 1'bz); + display_strengths(1'bx, 1'b0, 1'bx); + display_strengths(1'bx, 1'b0, 1'b0); + display_strengths(1'bx, 1'b0, 1'b1); + + display_strengths(1'b0, 1'b0, 1'bz); + display_strengths(1'b0, 1'b0, 1'bx); + display_strengths(1'b0, 1'b0, 1'b0); + display_strengths(1'b0, 1'b0, 1'b1); + + display_strengths(1'b1, 1'b0, 1'bz); + display_strengths(1'b1, 1'b0, 1'bx); + display_strengths(1'b1, 1'b0, 1'b0); + display_strengths(1'b1, 1'b0, 1'b1); + + display_strengths(1'bz, 1'b1, 1'bz); + display_strengths(1'bz, 1'b1, 1'bx); + display_strengths(1'bz, 1'b1, 1'b0); + display_strengths(1'bz, 1'b1, 1'b1); + + display_strengths(1'bx, 1'b1, 1'bz); + display_strengths(1'bx, 1'b1, 1'bx); + display_strengths(1'bx, 1'b1, 1'b0); + display_strengths(1'bx, 1'b1, 1'b1); + + display_strengths(1'b0, 1'b1, 1'bz); + display_strengths(1'b0, 1'b1, 1'bx); + display_strengths(1'b0, 1'b1, 1'b0); + display_strengths(1'b0, 1'b1, 1'b1); + + display_strengths(1'b1, 1'b1, 1'bz); + display_strengths(1'b1, 1'b1, 1'bx); + display_strengths(1'b1, 1'b1, 1'b0); + display_strengths(1'b1, 1'b1, 1'b1); +end + +endmodule diff --git a/ivtest/ivltests/tranif1.v b/ivtest/ivltests/tranif1.v new file mode 100644 index 000000000..65f4ca447 --- /dev/null +++ b/ivtest/ivltests/tranif1.v @@ -0,0 +1,183 @@ +module test(); + +reg a, b, en; + +wire a1, a2, a3, a4, a5, a6, a7; + +assign (supply1, supply0) a1 = a; + +tranif1 t1(a1, a2, en); +tranif1 t2(a2, a3, en); +tranif1 t3(a3, a4, en); +tranif1 t4(a4, a5, en); +tranif1 t5(a5, a6, en); +tranif1 t6(a6, a7, en); + +wire a11, a12, a13, a14, a15, b11, b12, b13, b14, b15; +wire a21, a22, a23, a24, a25, b21, b22, b23, b24, b25; +wire a31, a32, a33, a34, a35, b31, b32, b33, b34, b35; +wire a41, a42, a43, a44, a45, b41, b42, b43, b44, b45; +wire a51, a52, a53, a54, a55, b51, b52, b53, b54, b55; + +assign (supply1, supply0) a11 = a, b11 = b; +assign (supply1, strong0) a12 = a, b12 = b; +assign (supply1, pull0) a13 = a, b13 = b; +assign (supply1, weak0) a14 = a, b14 = b; +assign (supply1, highz0) a15 = a, b15 = b; + +assign (strong1, supply0) a21 = a, b21 = b; +assign (strong1, strong0) a22 = a, b22 = b; +assign (strong1, pull0) a23 = a, b23 = b; +assign (strong1, weak0) a24 = a, b24 = b; +assign (strong1, highz0) a25 = a, b25 = b; + +assign ( pull1, supply0) a31 = a, b31 = b; +assign ( pull1, strong0) a32 = a, b32 = b; +assign ( pull1, pull0) a33 = a, b33 = b; +assign ( pull1, weak0) a34 = a, b34 = b; +assign ( pull1, highz0) a35 = a, b35 = b; + +assign ( weak1, supply0) a41 = a, b41 = b; +assign ( weak1, strong0) a42 = a, b42 = b; +assign ( weak1, pull0) a43 = a, b43 = b; +assign ( weak1, weak0) a44 = a, b44 = b; +assign ( weak1, highz0) a45 = a, b45 = b; + +assign ( highz1, supply0) a51 = a, b51 = b; +assign ( highz1, strong0) a52 = a, b52 = b; +assign ( highz1, pull0) a53 = a, b53 = b; +assign ( highz1, weak0) a54 = a, b54 = b; + +tranif1 t11(a11, b11, en); +tranif1 t12(a12, b12, en); +tranif1 t13(a13, b13, en); +tranif1 t14(a14, b14, en); +tranif1 t15(a15, b15, en); + +tranif1 t21(a21, b21, en); +tranif1 t22(a22, b22, en); +tranif1 t23(a23, b23, en); +tranif1 t24(a24, b24, en); +tranif1 t25(a25, b25, en); + +tranif1 t31(a31, b31, en); +tranif1 t32(a32, b32, en); +tranif1 t33(a33, b33, en); +tranif1 t34(a34, b34, en); +tranif1 t35(a35, b35, en); + +tranif1 t41(a41, b41, en); +tranif1 t42(a42, b42, en); +tranif1 t43(a43, b43, en); +tranif1 t44(a44, b44, en); +tranif1 t45(a45, b45, en); + +tranif1 t51(a51, b51, en); +tranif1 t52(a52, b52, en); +tranif1 t53(a53, b53, en); +tranif1 t54(a54, b54, en); +tranif1 t55(a55, b55, en); + +task display_strengths; + +input ta, tb, ten; + +begin + a = ta; + b = tb; + en = ten; + #1; + $display("a = %b b = %b en = %b", a, b, en); + $display("a1(%v) a2(%v) a3(%v) a4(%v) a5(%v) a6(%v) a7(%v)", a1, a2, a3, a4, a5, a6, a7); + $display("t11(%v %v) t12(%v %v) t13(%v %v) t14(%v %v) t15(%v %v)", a11, b11, a12, b12, a13, b13, a14, b14, a15, b15); + $display("t21(%v %v) t22(%v %v) t23(%v %v) t24(%v %v) t25(%v %v)", a21, b21, a22, b22, a23, b23, a24, b24, a25, b25); + $display("t31(%v %v) t32(%v %v) t33(%v %v) t34(%v %v) t35(%v %v)", a31, b31, a32, b32, a33, b33, a34, b34, a35, b35); + $display("t41(%v %v) t42(%v %v) t43(%v %v) t44(%v %v) t45(%v %v)", a41, b41, a42, b42, a43, b43, a44, b44, a45, b45); + $display("t51(%v %v) t52(%v %v) t53(%v %v) t54(%v %v) t55(%v %v)", a51, b51, a52, b52, a53, b53, a54, b54, a55, b55); +end + +endtask + +initial begin + display_strengths(1'bz, 1'bz, 1'bz); + display_strengths(1'bz, 1'bz, 1'bx); + display_strengths(1'bz, 1'bz, 1'b0); + display_strengths(1'bz, 1'bz, 1'b1); + + display_strengths(1'bx, 1'bz, 1'bz); + display_strengths(1'bx, 1'bz, 1'bx); + display_strengths(1'bx, 1'bz, 1'b0); + display_strengths(1'bx, 1'bz, 1'b1); + + display_strengths(1'b0, 1'bz, 1'bz); + display_strengths(1'b0, 1'bz, 1'bx); + display_strengths(1'b0, 1'bz, 1'b0); + display_strengths(1'b0, 1'bz, 1'b1); + + display_strengths(1'b1, 1'bz, 1'bz); + display_strengths(1'b1, 1'bz, 1'bx); + display_strengths(1'b1, 1'bz, 1'b0); + display_strengths(1'b1, 1'bz, 1'b1); + + display_strengths(1'bz, 1'bx, 1'bz); + display_strengths(1'bz, 1'bx, 1'bx); + display_strengths(1'bz, 1'bx, 1'b0); + display_strengths(1'bz, 1'bx, 1'b1); + + display_strengths(1'bx, 1'bx, 1'bz); + display_strengths(1'bx, 1'bx, 1'bx); + display_strengths(1'bx, 1'bx, 1'b0); + display_strengths(1'bx, 1'bx, 1'b1); + + display_strengths(1'b0, 1'bx, 1'bz); + display_strengths(1'b0, 1'bx, 1'bx); + display_strengths(1'b0, 1'bx, 1'b0); + display_strengths(1'b0, 1'bx, 1'b1); + + display_strengths(1'b1, 1'bx, 1'bz); + display_strengths(1'b1, 1'bx, 1'bx); + display_strengths(1'b1, 1'bx, 1'b0); + display_strengths(1'b1, 1'bx, 1'b1); + + display_strengths(1'bz, 1'b0, 1'bz); + display_strengths(1'bz, 1'b0, 1'bx); + display_strengths(1'bz, 1'b0, 1'b0); + display_strengths(1'bz, 1'b0, 1'b1); + + display_strengths(1'bx, 1'b0, 1'bz); + display_strengths(1'bx, 1'b0, 1'bx); + display_strengths(1'bx, 1'b0, 1'b0); + display_strengths(1'bx, 1'b0, 1'b1); + + display_strengths(1'b0, 1'b0, 1'bz); + display_strengths(1'b0, 1'b0, 1'bx); + display_strengths(1'b0, 1'b0, 1'b0); + display_strengths(1'b0, 1'b0, 1'b1); + + display_strengths(1'b1, 1'b0, 1'bz); + display_strengths(1'b1, 1'b0, 1'bx); + display_strengths(1'b1, 1'b0, 1'b0); + display_strengths(1'b1, 1'b0, 1'b1); + + display_strengths(1'bz, 1'b1, 1'bz); + display_strengths(1'bz, 1'b1, 1'bx); + display_strengths(1'bz, 1'b1, 1'b0); + display_strengths(1'bz, 1'b1, 1'b1); + + display_strengths(1'bx, 1'b1, 1'bz); + display_strengths(1'bx, 1'b1, 1'bx); + display_strengths(1'bx, 1'b1, 1'b0); + display_strengths(1'bx, 1'b1, 1'b1); + + display_strengths(1'b0, 1'b1, 1'bz); + display_strengths(1'b0, 1'b1, 1'bx); + display_strengths(1'b0, 1'b1, 1'b0); + display_strengths(1'b0, 1'b1, 1'b1); + + display_strengths(1'b1, 1'b1, 1'bz); + display_strengths(1'b1, 1'b1, 1'bx); + display_strengths(1'b1, 1'b1, 1'b0); + display_strengths(1'b1, 1'b1, 1'b1); +end + +endmodule diff --git a/ivtest/ivltests/tri0.v b/ivtest/ivltests/tri0.v new file mode 100644 index 000000000..08128bfa6 --- /dev/null +++ b/ivtest/ivltests/tri0.v @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This module tests the basic behavior of a tri0 register. We use a ?: + * to turn on/off the driver to the tri0 net and watch its value. + * A tri0 net should pull to 0 when undriven, and follow the driver + * otherwise. + */ +module main; + + reg enable, val; + tri0 t0 = enable ? val : 1'bz; + + initial begin + enable = 0; + val = 0; + + #1 if (t0 !== 1'b0) begin + $display("FAILED -- undriven t0 == %b", t0); + $finish; + end + + enable = 1; + + #1 if (t0 !== 1'b0) begin + $display("FAILED -- driven-0 t0 == %b", t0); + $finish; + end + + val = 1; + + #1 if (t0 !== 1'b1) begin + $display("FAILED -- driven-1 t0 == %b", t0); + $finish; + end + + $display("PASSED"); + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/tri0b.v b/ivtest/ivltests/tri0b.v new file mode 100644 index 000000000..cdb7f2e4a --- /dev/null +++ b/ivtest/ivltests/tri0b.v @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This module tests the basic behavior of a tri0 register. We use a ?: + * to turn on/off the driver to the tri0 net and watch its value. + * A tri0 net should pull to 0 when undriven, and follow the driver + * otherwise. + */ +module main; + + reg enable, val; + tri0 t0 = (~enable) ? 1'bz : val; + + initial begin + enable = 0; + val = 0; + + #1 if (t0 !== 1'b0) begin + $display("FAILED -- undriven t0 == %b", t0); + $finish; + end + + enable = 1; + + #1 if (t0 !== 1'b0) begin + $display("FAILED -- driven-0 t0 == %b", t0); + $finish; + end + + val = 1; + + #1 if (t0 !== 1'b1) begin + $display("FAILED -- driven-1 t0 == %b", t0); + $finish; + end + + $display("PASSED"); + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/tri1.v b/ivtest/ivltests/tri1.v new file mode 100644 index 000000000..526ba13cd --- /dev/null +++ b/ivtest/ivltests/tri1.v @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This module tests the basic behavior of a tri1 register. We use a ?: + * to turn on/off the driver to the tri1 net and watch its value. + * A tri1 net should pull to 1 when undriven, and follow the driver + * otherwise. + */ +module main; + + reg enable, val; + tri1 t1 = enable ? val : 1'bz; + + initial begin + enable = 0; + val = 0; + + #1 if (t1 !== 1'b1) begin + $display("FAILED -- undriven t1 == %b", t1); + $finish; + end + + enable = 1; + + #1 if (t1 !== 1'b0) begin + $display("FAILED -- driven-0 t1 == %b", t1); + $finish; + end + + val = 1; + + #1 if (t1 !== 1'b1) begin + $display("FAILED -- driven-1 t1 == %b", t1); + $finish; + end + + $display("PASSED"); + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/tri2.v b/ivtest/ivltests/tri2.v new file mode 100644 index 000000000..529f0b717 --- /dev/null +++ b/ivtest/ivltests/tri2.v @@ -0,0 +1,38 @@ +`timescale 1 ns / 1 ns +module short(inout [7:0] p, input en); + assign p = en ? 8'h55 : 8'hzz; +endmodule + +module long(inout [15:0] p, input en); + assign p = en ? 16'haaaa : 16'hzzzz; +endmodule + +module main; + wire [15:0] bus; + reg l_en, s_en; + integer fails=0; + long l(.p(bus), .en(l_en)); + short s(.p(bus[7:0]), .en(s_en)); + initial begin + // $dumpfile("tri.vcd"); + // $dumpvars(3,main); + l_en = 0; + s_en = 0; + #10; + l_en = 1; + #10; + $display("s.p = %4x", s.p); + if (s.p !== 8'haa) fails=1; + #10; + l_en = 0; + s_en = 1; + #10; + $display("l.p = %4x", l.p); + if (l.p !== 16'hzz55) fails=2; + #10; + s_en = 0; + #10; + if (fails == 0) $display("PASSED"); + else $display("FAILED ",fails); + end +endmodule diff --git a/ivtest/ivltests/tri3.v b/ivtest/ivltests/tri3.v new file mode 100644 index 000000000..394194132 --- /dev/null +++ b/ivtest/ivltests/tri3.v @@ -0,0 +1,22 @@ +module test(); + +tri1 a; +tri0 b; + +assign (pull1,pull0) a = 1'b0; +assign (pull1,pull0) b = 1'b1; + +reg failed; + +initial begin + failed = 0; #1; + $display("a = %b, expect x", a); if (a !== 1'bx) failed = 1; + $display("b = %b, expect x", b); if (b !== 1'bx) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/triand.v b/ivtest/ivltests/triand.v new file mode 100644 index 000000000..ab3f9ade2 --- /dev/null +++ b/ivtest/ivltests/triand.v @@ -0,0 +1,83 @@ +module main; + + reg a, b; + + triand net; + + assign net = a; + assign net = b; + + initial begin + a = 'b0; + b = 'b0; + #1 if (net !== 1'b0) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'b0; + b = 'b1; + #1 if (net !== 1'b0) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'b0; + b = 'bx; + #1 if (net !== 1'b0) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'b0; + b = 'bz; + #1 if (net !== 1'b0) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'b1; + b = 'b1; + #1 if (net !== 1'b1) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'b1; + b = 'bx; + #1 if (net !== 1'bx) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'b1; + b = 'bz; + #1 if (net !== 1'b1) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'bx; + b = 'bx; + #1 if (net !== 1'bx) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'bx; + b = 'bz; + #1 if (net !== 1'bx) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'bz; + b = 'bz; + #1 if (net !== 1'bz) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/trior.v b/ivtest/ivltests/trior.v new file mode 100644 index 000000000..0281a3ede --- /dev/null +++ b/ivtest/ivltests/trior.v @@ -0,0 +1,83 @@ +module main; + + reg a, b; + + trior net; + + assign net = a; + assign net = b; + + initial begin + a = 'b0; + b = 'b0; + #1 if (net !== 1'b0) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'b0; + b = 'b1; + #1 if (net !== 1'b1) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'b0; + b = 'bx; + #1 if (net !== 1'bx) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'b0; + b = 'bz; + #1 if (net !== 1'b0) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'b1; + b = 'b1; + #1 if (net !== 1'b1) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'b1; + b = 'bx; + #1 if (net !== 1'b1) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'b1; + b = 'bz; + #1 if (net !== 1'b1) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'bx; + b = 'bx; + #1 if (net !== 1'bx) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'bx; + b = 'bz; + #1 if (net !== 1'bx) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + a = 'bz; + b = 'bz; + #1 if (net !== 1'bz) begin + $display("FAILED -- a=%b, b=%b, net=%b", a, b, net); + $finish; + end + + $display("PASSED"); + end +endmodule // main diff --git a/ivtest/ivltests/two_state_display.v b/ivtest/ivltests/two_state_display.v new file mode 100644 index 000000000..7cacb25cb --- /dev/null +++ b/ivtest/ivltests/two_state_display.v @@ -0,0 +1,35 @@ +module top; + bit [2:-1] vec = 4'b1001; + bit btvar = 0; + byte bvar = 0; + shortint svar = 0; + int ivar = 0; + longint lvar = 0; + initial begin + if ((vec[-1] != 1) && (vec[0] != 0) && + (vec[1] != 0) && (vec[2] != 1)) begin + $display("Failed to select vector bits correctly"); + $finish; + end + $display("Vec: ", vec); + $display("Bit: ", btvar); + $display("Byte: ", bvar); + $display("Short: ", svar); + $display("Int: ", ivar); + $display("Long: ", lvar); + $display("Monitor results:"); + + $monitor("Time: ", $stime, + "\n Bit: ", btvar, + "\n Byte: ", bvar, + "\n Short: ", svar, + "\n Int: ", ivar, + "\n Long: ", lvar); + + #1 btvar = 1; + #1 bvar = 1; + #1 svar = 1; + #1 ivar = 1; + #1 lvar = 1; + end +endmodule diff --git a/ivtest/ivltests/types1.v b/ivtest/ivltests/types1.v new file mode 100644 index 000000000..2d332747c --- /dev/null +++ b/ivtest/ivltests/types1.v @@ -0,0 +1,41 @@ +/* + * This is a simplified version of the test program for issue 1323691 + * from the iverilog bugs database. + */ +`timescale 1ns/1ns + + +module main; + + parameter early_empty=1; + + reg re; + + reg rc_isEmpty, rc_willBeEmpty; + wire empty; + + assign empty = (early_empty!=0) ? + rc_willBeEmpty && re || rc_isEmpty : + rc_isEmpty; + + + initial begin + rc_isEmpty <= 1'bx; + rc_willBeEmpty <= 1'b1; + re <= 1'b0; + rc_isEmpty <= 1'b0; + + #1 if (empty !== 1'b0) begin + $display("FAILED -- empty == %b (s.b. 0)", empty); + $finish; + end + + rc_isEmpty <= 1; + #1 if (empty !== 1'b1) begin + $display("FAILED -- empty == %b (s.b. 1)", empty); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/ubyte_test.v b/ivtest/ivltests/ubyte_test.v new file mode 100644 index 000000000..a7182d55f --- /dev/null +++ b/ivtest/ivltests/ubyte_test.v @@ -0,0 +1,322 @@ +// Ten basic tests in here: +// 1. byte must be initialised before any initial or always block +// 2. assignments to (unsigned) bytes with random numbers +// 3. assignments to (unsigned) bytes with random values including X and Z +// 4. converting unsigned integers to unsigned bytes +// 5. converting signed integers to unsigned bytes +// 6. converting integers including X and Z states to unsigned bytes +// 7. trying unsigned sums (procedural, function, task and module) +// 8. trying unsigned (truncated) mults (procedural, function and task) +// 9. trying relational operators +// 10. smaller signed number to unsigned bytes (sign extension) + +module mu_add (input byte unsigned a, b, output byte unsigned sc, ss); + assign sc = a + b; + always @(a, b) ss = a + b; +endmodule + + +module main; + parameter N_REPS = 500; // repetition with random numbers + parameter XZ_REPS = 500; // repetition with 'x 'z values + parameter MAX = 256; + parameter LEN = 8; + // variables used as golden references + reg unsigned [LEN-1:0] ar; // holds numbers + reg unsigned [LEN-1:0] ar_xz; // holds 'x and/or 'z in random positions + reg unsigned [LEN-1:0] ar_expected; + integer unsigned ui; + integer signed si; + reg signed [LEN/2-1:0] slice; + // types to be tested + byte unsigned bu; // holds numbers + byte unsigned bu_xz; // 'x and 'z are attempted on this + byte unsigned bresult; // hold results from sums and mults + byte unsigned mcaresult; // this is permanently wired to a module + byte unsigned mabresult; // this is permanently wired to a module + + + integer i; + + // continuous assigments + // type LHS type RHS + // --------- --------- + // byte 4-value logic + assign bu = ar; + assign bu_xz = ar_xz; + + // module instantiation + mu_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) ); + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if ( bu !== 8'b0 || bu_xz !== 8'b0 || bresult !== 8'b0 || mcaresult !== 8'b0 || mabresult !== 8'b0) + begin + $display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz); + $finish; + end + // driving byte type with unsigned random numbers from a variable + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = {$random} % MAX; + #1; + if (bu !== ar) + begin + $display ("FAILED - incorrect assigment to byte: %b", bu); + $finish; + end + end + # 1; + // attempting to drive variables having 'x 'z values into type unsigned bytes + // 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + ar = {$random} % MAX; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect assigment to byte (when 'x 'z): %b", bu); + $finish; + end + end + // converting unsigned integers to unsigned bytes + // truncation expected (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ui = {$random}; + #1; + force bu = ui; + #1; + if (bu !== ui[LEN-1:0]) + begin + $display ("FAILED - incorrect truncation from unsigned integer to byte: %b", bu); + $finish; + end + end + release bu; + // converting signed integers to unsigned bytes + // truncation expected (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + si = $random % MAX/2; + #1; + force bu = si; + #1; + if (bu !== si[LEN-1:0]) + begin + $display ("FAILED - incorrect truncation from signed integer to byte: %b mismatchs %b", bu, si[7:0]); + $finish; + end + end + release bu; + // converting signed integers having 'x 'z values into type unsigned bytes + // 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM) + // truncation and coercion to zero expected + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + si = $random; + ar_xz = xz_inject (si[LEN-1:0]); + si = {si[31:LEN], ar_xz}; + ar_expected = xz_expected (ar_xz); + #1; + force bu_xz = si; + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect conversion from integer (with 'x 'z) to byte: %b mismatchs %b", bu_xz, ar_expected); + $finish; + end + end + release bu_xz; + // trying unsigned sums + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = {$random} % MAX; + ar_xz = {$random} % MAX; + #1; + bresult = bu + bu_xz; + #1; + if ( bresult !== u_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of unsigned bytes: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz)); + $finish; + end + // invoking byte sum function + if ( fu_sum (bu, bu_xz) !== u_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of unsigned bytes in function"); + $finish; + end + // invoking byte sum task + tu_sum (bu, bu_xz, bresult); + if ( bresult !== u_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of unsigned bytes in task: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz)); + $finish; + end + // checking byte sum from module + if ( mcaresult !== u_sum(ar, ar_xz) || mabresult !== u_sum(ar, ar_xz)) + begin + $display ("FAILED - incorrect addition of unsigned bytes from module"); + $finish; + end + end + // trying unsigned mults: trucation is forced + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = ({$random} % MAX) << LEN/2; + ar_xz = ({$random} % MAX) << (LEN/2 -1); + #1; + bresult = bu * bu_xz; + #1; + if ( bresult !== u_mul(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of unsigned bytes: %0d mismatchs %0d", bresult, u_mul(ar, ar_xz)); + $finish; + end + // invoking byte mult function + if ( fu_mul (bu, bu_xz) !== u_mul(ar, ar_xz) ) + begin + $display ("FAILED - incorrect product of unsigned bytes in function"); + $finish; + end + // invoking byte mult task + tu_mul (bu, bu_xz, bresult); + if ( bresult !== u_mul(ar, ar_xz) ) + begin + $display ("FAILED - incorrect product of unsigned bytes in task: %0d mismatchs %0d", bresult, u_mul(ar, ar_xz)); + $finish; + end + end + // trying relational operators + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = {$random} % MAX; + ar_xz = {$random} % MAX; + #1; + if ( (bu < bu_xz ) !== (ar < ar_xz) ) + begin + $display ("FAILED - incorrect 'less than' on unsigned bytes"); + $finish; + end + if ( (bu <= bu_xz ) !== (ar <= ar_xz) ) + begin + $display ("FAILED - incorrect 'less than or equal' on unsigned bytes"); + $finish; + end + if ( (bu > bu_xz ) !== (ar > ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than' on unsigned bytes"); + $finish; + end + if ( (bu >= bu_xz ) !== (ar >= ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than or equal' than on unsigned bytes"); + $finish; + end + if ( (bu == bu_xz ) !== (ar == ar_xz) ) + begin + $display ("FAILED - incorrect 'equal to' on unsigned bytes"); + $finish; + end + if ( (bu != bu_xz ) !== (ar != ar_xz) ) + begin + $display ("FAILED - incorrect 'not equal to' on unsigned bytes"); + $finish; + end + end + # 1; + // signed small number to unsigned byte + for (i = 0; i < (1< + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: udp_jkff.v,v 1.2 2007/08/29 00:01:22 stevewilliams Exp $ + +module test_jkff; + + reg cp; + reg j, k; + reg s, r; + reg qq; + + integer errors; + initial errors = 0; + + initial + begin + cp <= 0; + #10 {s,r, qq} <= 3'b 10_1; + #10 {s,r, qq} <= 3'b 00_1; + #10 {s,r, qq} <= 3'b x0_1; + #10 {s,r, qq} <= 3'b 00_1; + #10 {s,r, qq} <= 3'b 01_0; + #10 {s,r, qq} <= 3'b 00_0; + #10 {s,r, qq} <= 3'b x0_x; + #10 {s,r, qq} <= 3'b 00_x; + #10 {s,r, qq} <= 3'b 10_1; + #10 {s,r, qq} <= 3'b 11_x; + #10 {s,r, qq} <= 3'b 01_0; + #10 {s,r, qq} <= 3'b 00_0; + #10 {s,r, qq} <= 3'b 01_0; + #10 {s,r, qq} <= 3'b 11_x; + #10 {s,r, qq} <= 3'b 01_0; + #10 {s,r, qq} <= 3'b 00_0; + #10 {cp, j,k, qq} <= 4'b 0_00_0; + #10 {cp, j,k, qq} <= 4'b 1_00_0; + #10 {cp, j,k, qq} <= 4'b 0_01_0; + #10 {cp, j,k, qq} <= 4'b 1_01_0; + #10 {cp, j,k, qq} <= 4'b 0_11_0; + #10 {cp, j,k, qq} <= 4'b 1_11_1; + #10 {cp, j,k, qq} <= 4'b 0_11_1; + #10 {cp, j,k, qq} <= 4'b 1_11_0; + #10 {cp, j,k, qq} <= 4'b 0_00_0; + #10 {cp, j,k, qq} <= 4'b x_00_0; + #10 {cp, j,k, qq} <= 4'b 0_10_0; + #10 {cp, j,k, qq} <= 4'b 1_10_1; + #10 {cp, j,k, qq} <= 4'b x_10_1; + #10 {cp, j,k, qq} <= 4'b 1_10_1; + #10 {cp, j,k, qq} <= 4'b 0_10_1; + #10 {cp, j,k, qq} <= 4'b x_10_1; + #10 {cp, j,k, qq} <= 4'b 0_01_1; + #10 {cp, j,k, qq} <= 4'b x_01_x; + #10 {cp, j,k, qq} <= 4'b 1_01_x; + #10 {cp, j,k, qq} <= 4'b 0_11_x; + #10 {cp, j,k, qq} <= 4'b 1_11_x; + #10 {cp, j,k, qq} <= 4'b 0_01_x; + #10 {cp, j,k, qq} <= 4'b 1_01_0; + #10 {cp, j,k, qq} <= 4'b x_11_0; + #10 {cp, j,k, qq} <= 4'b 1_11_x; + #10 {cp, j,k, qq} <= 4'b 0_10_x; + #10 {cp, j,k, qq} <= 4'b 1_10_1; + #10 {cp, j,k, qq} <= 4'b 0_00_1; + #10; + if (errors > 0) + $display("FAILED"); + else + $display("PASSED"); + #10 $finish; + end + + wire q; +`ifdef FAKE_UDP + // to get a vvp template, from which to build a UDP test vvp + and ff (q, j, k, s, r); +`else + jkff ff (q, cp, j, k, s, r); +`endif + + always @(cp or j or k or s or r) + begin + #2; + $display("cp=%b j=%b k=%b s=%b r=%b q=%b", cp, j, k, s, r, q); + if (q !== qq && $time > 2) + begin + $display("FAILED: expect q=%b (time=%t)", qq, $time); + errors = errors + 1; + end + end + +endmodule + +`ifdef FAKE_UDP +`else +primitive jkff(q, cp, j, k, s, r); + output q; + input cp, j, k, s, r; + reg q; + table + // (cp) jk s r : q : q ; + ? ?? (?0) 0 : ? : - ; + ? ?? 0 (?0) : ? : - ; + ? *? 0 0 : ? : - ; + ? ?* 0 0 : ? : - ; + ? ?? 1 0 : ? : 1 ; + ? ?? 0 1 : ? : 0 ; + ? ?? x 0 : 1 : 1 ; + ? ?? 0 x : 0 : 0 ; + (?0) ?? 0 0 : ? : - ; + (1x) ?? 0 0 : ? : - ; + (?1) 0? 0 0 : 0 : 0 ; + (?1) ?0 0 0 : 1 : 1 ; + (0x) 0? 0 0 : 0 : 0 ; + (0x) ?0 0 0 : 1 : 1 ; + (01) 1? 0 0 : 0 : 1 ; + (01) ?1 0 0 : 1 : 0 ; + (01) 10 0 0 : x : 1 ; + (01) 01 0 0 : x : 0 ; + endtable +endprimitive +`endif diff --git a/ivtest/ivltests/udp_lfsr.v b/ivtest/ivltests/udp_lfsr.v new file mode 100644 index 000000000..fc23d9085 --- /dev/null +++ b/ivtest/ivltests/udp_lfsr.v @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2001 Stephan Boettcher + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// $Id: udp_lfsr.v,v 1.1 2001/10/27 23:38:29 sib4 Exp $ + +module test_lfsr; + + reg cp; + reg in; + wire out; + reg reset; + lfsr sr(cp, reset, in, out); + + reg errors; + initial errors = 0; + integer i; + + initial + begin + in = 0; + cp = 0; + #2 reset = 1; + #2 reset = 0; + #1; + for (i=0; i<512; i=i+1) + #5 cp = ~cp; + + in = 0; + cp = 0; + #2 reset = 1; + #2 reset = 0; + #1; + for (i=0; i<512; i=i+1) + #5 cp <= ~cp; + + #5; + if (errors == 0) + $display("PASSED"); + #10 $finish; + end + + reg [7:0] here; + reg [7:0] next; + reg [7:0] old; + reg [7:0] new; + + always @(reset) + if (reset) + begin + here = 1; + #1; + old = {out, sr.s}; + if (old === here) + begin + $display("%b RESET", old); + end + else + begin + $display("%b RESET FAILED: expect %b", old, here); + errors = 1; + end + end + + always + begin + @(posedge cp) old = {out, sr.s}; + next = {here[6:0], ^(here & sr.P) ^ in}; + @(negedge cp) new = {out, sr.s}; + if (old != here || new !== next) + begin + $display("%b->%b FAILED: expect %b->%b", old, new, here, next); + errors = 1; + end + else + begin + $display("%b->%b", old, new); + end + here = next; + end + +endmodule + +module lfsr (clk, reset, in, out); + + parameter P = 8'b 1101_1001; + + input clk; + input reset; + input in; + + output out; + wire [6:0] s; + wire i = ^{P & {out,s}} ^ in; + + jkff ff1 (s[0], clk, i, ~i, reset, 0); + jkff ff2 (s[1], clk, s[0], ~s[0], 0, reset); + jkff ff3 (s[2], clk, s[1], ~s[1], 0, reset); + jkff ff4 (s[3], clk, s[2], ~s[2], 0, reset); + + jkff ff8 (out, clk, s[6], ~s[6], 0, reset); + jkff ff7 (s[6], clk, s[5], ~s[5], 0, reset); + jkff ff6 (s[5], clk, s[4], ~s[4], 0, reset); + jkff ff5 (s[4], clk, s[3], ~s[3], 0, reset); + +endmodule + +primitive jkff(q, cp, j, k, s, r); + output q; + input cp, j, k, s, r; + reg q; + table + // (cp) j k s r : q : q ; + ? ? ? (?0) 0 : ? : - ; + ? ? ? 0 (?0) : ? : - ; + ? * ? 0 0 : ? : - ; + ? ? * 0 0 : ? : - ; + ? ? ? 1 0 : ? : 1 ; + ? ? ? 0 1 : ? : 0 ; + ? ? ? x 0 : 1 : 1 ; + ? ? ? 0 x : 0 : 0 ; + (?0) ? ? 0 0 : ? : - ; + (1x) ? ? 0 0 : ? : - ; + (?1) 0 ? 0 0 : 0 : 0 ; + (?1) ? 0 0 0 : 1 : 1 ; + (0x) 0 ? 0 0 : 0 : 0 ; + (0x) ? 0 0 0 : 1 : 1 ; + (01) 1 ? 0 0 : 0 : 1 ; + (01) ? 1 0 0 : 1 : 0 ; + (01) 1 0 0 0 : x : 1 ; + (01) 0 1 0 0 : x : 0 ; + endtable +endprimitive diff --git a/ivtest/ivltests/udp_prop.v b/ivtest/ivltests/udp_prop.v new file mode 100644 index 000000000..13e3f6de6 --- /dev/null +++ b/ivtest/ivltests/udp_prop.v @@ -0,0 +1,54 @@ +module test; + + reg cp; + reg d; + wire q; + + dff ff(q, cp, d); + + always begin #5 cp=0; #5 cp=1; end + + always + begin + @(negedge cp) + d <= ~d; + + @(posedge cp) + if (q !== 'bx && d === q) + begin + $display("FAILED, d=%b, q=%b", d, q); + #1 $finish; + end + end + + initial + begin + #1 d <= 1; + #22; + $display("PASSED"); + $finish; + end + + initial $monitor($time,,cp,,d,,q); + +endmodule + +primitive dff(q, cp, d); + output q; + input cp, d; + reg q; + + table + // (cp) d : q : q ; + ? * : ? : - ; + (?0) ? : ? : - ; + (1x) ? : ? : - ; + (x1) 0 : 0 : 0 ; + (x1) 1 : 1 : 1 ; + (0x) 0 : 0 : 0 ; + (0x) 1 : 1 : 1 ; + (01) 0 : ? : 0 ; + (01) 1 : ? : 1 ; + endtable + +endprimitive diff --git a/ivtest/ivltests/udp_real_delay.v b/ivtest/ivltests/udp_real_delay.v new file mode 100644 index 000000000..5ed2a388f --- /dev/null +++ b/ivtest/ivltests/udp_real_delay.v @@ -0,0 +1,54 @@ +`timescale 1ns/100ps + +primitive udp_and( + output y, + input a, + input b +); + +table +//a b : y + 0 0 : 0 ; + 0 1 : 0 ; + 1 0 : 0 ; + 1 1 : 1 ; + x 0 : 0 ; + 0 x : 0 ; +endtable + +endprimitive + +module test(); + +reg a; +reg b; +wire y; + +udp_and #0.5 gate(y, a, b); + +reg failed = 0; + +initial begin + $monitor($realtime,,a,,b,,y); + a = 0; b = 0; + #0.6 if (y !== 1'b0) failed = 1; + a = 1; b = 1; + #0.4 if (y !== 1'b0) failed = 1; + #0.2 if (y !== 1'b1) failed = 1; + a = 0; b = 1; + #0.4 if (y !== 1'b1) failed = 1; + #0.2 if (y !== 1'b0) failed = 1; + a = 1; b = 1; + #0.4 if (y !== 1'b0) failed = 1; + #0.2 if (y !== 1'b1) failed = 1; + a = 1; b = 0; + #0.4 if (y !== 1'b1) failed = 1; + #0.2 if (y !== 1'b0) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/udp_sched.v b/ivtest/ivltests/udp_sched.v new file mode 100644 index 000000000..cce742876 --- /dev/null +++ b/ivtest/ivltests/udp_sched.v @@ -0,0 +1,59 @@ +/* + * This test tries to assure that all synchronous UDP outputs are + * scheduled before any non-blocking assignment event. The reason + * is that primitive outputs are scheduled in the active event + * queue, which is supposed to empty before any non-blocking + * assignments take effect. + * + * This is based on an example by Steve Sharp + */ + +primitive u_dff(q,d,c); +output q; +reg q; +input d,c; +table +//d c : q : q+ + 0 p : ? : 0 ; + 1 p : ? : 1 ; + ? n : ? : - ; + * ? : ? : - ; +endtable +endprimitive + + +module top; + +reg rclk, dclk; +wire clk = rclk; +wire q0,q1,q2,q3,q4; + +u_dff ff0(q0, 1'b1, clk), + ff1(q1, 1'b1, q0), + ff2(q2, 1'b1, q1), + ff3(q3, 1'b1, q2), + ff4(q4, 1'b1, q3); + +initial +begin + #1 + // Blocking assign makes an active event that + // starts the u_dff devices rippling + rclk = 1; + + // Non-blocking assign and the following @(dclk) pause + // the thread until the non-blocking event queue is + // processed. + dclk <= 1; + @(dclk) + + if (q4 !== 1'b1) begin + $display("FAILED -- q4 did not propagate in time (q4=%b)", q4); + $finish; + end + + $display("q4=%b", q4); + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/udp_x.v b/ivtest/ivltests/udp_x.v new file mode 100644 index 000000000..6e877d581 --- /dev/null +++ b/ivtest/ivltests/udp_x.v @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program checks that conbinational UDPs with x outputs are + * properly executed. + */ + +module main; + + wire Y; + reg A, B, S; + + muxx1 MUX2 ( Y, S, A, B ) ; + + initial begin + S = 0; + A = 0; + B = 0; + #1 if (Y !== 1'b0) begin + $display("FAILED -- Y is %b", Y); + $finish; + end + + B = 1; + #1 if (Y !== 1'b0) begin + $display("FAILED -- Y is %b", Y); + $finish; + end + + S = 1; + #1 if (Y !== 1'b1) begin + $display("FAILED -- Y is %b", Y); + $finish; + end + + B = 1'bx; + #1 if (Y !== 1'bx) begin + $display("FAILED -- Y is %b", Y); + $finish; + end + + B = 1; + S = 1'bx; + #1 if (Y !== 1'bx) begin + $display("FAILED -- Y is %b", Y); + $finish; + end + + B = 0; + #1 if (Y !== 1'b0) begin + $display("FAILED -- Y is %b", Y); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule + +primitive muxx1(Q, S, A, B); + output Q; + input S, A, B; + + table + // S A B Q + 0 0 ? : 0 ; + 0 1 ? : 1 ; + 0 x ? : x ; // problem line + 1 ? 0 : 0 ; + 1 ? 1 : 1 ; + 1 ? x : x ; // problem line + x 0 0 : 0 ; + x 1 1 : 1 ; + + endtable +endprimitive diff --git a/ivtest/ivltests/ufuncsynth1.v b/ivtest/ivltests/ufuncsynth1.v new file mode 100644 index 000000000..ffd1bc16f --- /dev/null +++ b/ivtest/ivltests/ufuncsynth1.v @@ -0,0 +1,44 @@ +module main; + + function [15:0] sum; + input [15:0] a; + input [15:0] b; + + sum = a + b; + endfunction // sum + + reg clk; + reg [15:0] d, e, out; + (* ivl_synthesis_on *) + always @(posedge clk) + out <= sum(d, e); + + + initial begin + clk = 0; + d = 0; + e = 0; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 16'd0) begin + $display("FAILED -- sum(%0d,%d) --> %0d", d, e, out); + $finish; + end + + d = 5; + e = 13; + + #1 clk = 1; + #1 clk = 0; + + if (out !== 16'd18) begin + $display("FAILED -- sum(%0d,%d) --> %0d", d, e, out); + $finish; + end + + $display("PASSED"); + $finish; + end +endmodule // main diff --git a/ivtest/ivltests/uint_test.v b/ivtest/ivltests/uint_test.v new file mode 100644 index 000000000..cef8e126b --- /dev/null +++ b/ivtest/ivltests/uint_test.v @@ -0,0 +1,372 @@ +// Eleven basic tests in here: +// 1. int must be initialised before any initial or always block +// 2. assignments to (unsigned) int with random numbers +// 3. assignments to (unsigned) int with random values including X and Z +// 4. converting unsigned integers to unsigned int +// 5. converting signed integers to unsigned int +// 6. converting integers including X and Z states to unsigned int +// 7. trying unsigned sums (procedural, function, task and module) +// 8. trying unsigned mults (procedural, function and task) +// 9. trying relational operators +// 10. smaller signed numbers to unsigned int (signed extension) +// 11. trying some concatenations from bytes, shortints to ints + +module mu_add (input int unsigned a, b, output int unsigned sc, ss); + assign sc = a + b; + always @(a, b) ss = a + b; +endmodule + +module main; + parameter N_REPS = 500; // repetition with random numbers + parameter XZ_REPS = 500; // repetition with 'x 'z values + parameter UMAX = 'hffff_ffff; + parameter MAX8 = 256; + parameter MAX16 = 65536; + parameter LEN = 32; + // variables used as golden references + reg unsigned [LEN-1:0] ar; // holds numbers + reg unsigned [LEN-1:0] ar_xz; // holds 'x and/or 'z in random positions + reg unsigned [LEN-1:0] ar_expected; + integer unsigned ui; + integer signed si; + reg signed [LEN/2-1:0] slice; + + // type assumed tested before + byte unsigned pt1, pt2; + shortint unsigned ps1, ps2; + + // types to be tested + int unsigned bu; // holds numbers + int unsigned bu_xz; // 'x and 'z are attempted on this + int unsigned bresult; // hold results from sums and mults + int unsigned mcaresult; // wired to a module instance + int unsigned mabresult; // also wired to a module instance + + + integer i; + + // continuous assigments + // type LHS type RHS + // --------- --------- + // int 4-value logic + assign bu = ar; + assign bu_xz = ar_xz; + + // module instantiation + mu_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) ); + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 32'b0 || bu_xz !== 32'b0 || bresult !== 32'b0 || mcaresult !== 32'b0 || mabresult !== 32'b0) + begin + $display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz); + $finish; + end + // driving int type with unsigned random numbers from a variable + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = {$random}; + #1; + if (bu !== ar) + begin + $display ("FAILED - incorrect assigment to int: %b", bu); + $finish; + end + end + # 1; + // attempting to drive variables having 'x 'z values into type unsigned int + // 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + ar = {$random}; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect assigment to int (when 'x 'z): %b", bu); + $finish; + end + end + // converting unsigned integers to unsigned int + // truncation expected (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ui = {$random}; + #1; + force bu = ui; + #1; + if (bu !== ui) + begin + $display ("FAILED - incorrect truncation from unsigned integer to int: %b", bu); + $finish; + end + end + release bu; + // converting signed integers to unsigned ints + // truncation expected (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + si = $random; + #1; + force bu = si; + #1; + if (bu !== si) + begin + $display ("FAILED - incorrect truncation from signed integer to int: %b mismatchs %b", bu, si); + $finish; + end + end + release bu; + // converting integers having 'x 'z values into type unsigned int + // 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM) + // truncation and coercion to zero expected + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + si = $random; + ar_xz = xz_inject (si); + si = ar_xz; + ar_expected = xz_expected (ar_xz); + #1; + force bu_xz = si; + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect conversion from integer (with 'x 'z) to int: %b mismatchs %b", bu_xz, ar_expected); + $finish; + end + end + release bu_xz; + // trying unsigned sums + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = {$random}; + ar_xz = {$random}; + #1; + bresult = bu + bu_xz; + #1; + if ( bresult !== u_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of unsigned ints: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz)); + $finish; + end + // invoking shortint sum function + if ( fu_sum (bu, bu_xz) !== u_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of unsigned int in function"); + $finish; + end + // invoking byte sum task + tu_sum (bu, bu_xz, bresult); + if ( bresult !== u_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of unsigned int in task: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz)); + $finish; + end + // checking byte sum from module + if ( mcaresult !== u_sum(ar, ar_xz) || mabresult !== u_sum(ar, ar_xz)) + begin + $display ("FAILED - incorrect addition of unsigned int from module"); + $finish; + end + end + // trying unsigned mults + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = ({$random} % UMAX) << (LEN/2); + ar_xz = ({$random} % UMAX) << (LEN/2 - 1); + #1; + bresult = bu * bu_xz; // truncated multiplication + #1; + if ( bresult !== uh_mul(ar, ar_xz) ) + begin + $display ("FAILED - incorrect multiplication of unsigned ints (truncated)"); + $finish; + end + #1; + ps1 = {$random} % 'hffff; + ps2 = {$random} % 'hffff; + #1; + bresult = ps1 * ps2; // int = shortint x shortint + #1; + if ( bresult !== u_mul(ps1, ps2) ) + begin + $display ("FAILED - incorrect multiplication of unsigned input shorints"); + $finish; + end + // invoking shortint mult function (byte*byte) + if ( fu_mul (ps1, ps2) !== u_mul(ps1, ps2) ) + begin + $display ("FAILED - incorrect product of unsigned shortint for a function returning unsigned int"); + $finish; + end + // invoking shortint mult task (byte*byte) + tu_mul (ps1, ps2, bresult); + if ( bresult !== u_mul(ps1, ps2) ) + begin + $display ("FAILED - incorrect product of unsigned shortint in task returning unsigned int"); + $finish; + end + end + // trying relational operators + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = {$random}; + ar_xz = {$random}; + #1; + if ( (bu < bu_xz ) !== (ar < ar_xz) ) + begin + $display ("FAILED - incorrect 'less than' on unsigned ints"); + $finish; + end + if ( (bu <= bu_xz ) !== (ar <= ar_xz) ) + begin + $display ("FAILED - incorrect 'less than or equal' on unsigned ints"); + $finish; + end + if ( (bu > bu_xz ) !== (ar > ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than' on unsigned ints"); + $finish; + end + if ( (bu >= bu_xz ) !== (ar >= ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than or equal' than on unsigned ints"); + $finish; + end + if ( (bu == bu_xz ) !== (ar == ar_xz) ) + begin + $display ("FAILED - incorrect 'equal to' on unsigned ints"); + $finish; + end + if ( (bu != bu_xz ) !== (ar != ar_xz) ) + begin + $display ("FAILED - incorrect 'not equal to' on unsigned ints"); + $finish; + end + end + # 1; + // signed small numbers to unsigned int + for (i = 0; i < (1< '0, 'z -> '0 + begin + $display ("FAILED - incorrect assigment to longint (when 'x 'z): %b", bu); + $finish; + end + end + // converting unsigned 64-bit integers (time) to unsigned longint + // this should pass trivially + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ui = { {$random}, {$random} }; + #1; + force bu = ui; + #1; + if (bu !== ui) + begin + $display ("FAILED - incorrect assignment from 64-bit integer to longint: %b", bu); + $finish; + end + end + release bu; + // converting signed integers to unsigned ints + // keeping the same bit representation is expected + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ui = { {$random}, {$random} }; + #1; + force bu = -ui; + #1; + if (-bu !== ui) + begin + $display ("FAILED - incorrect assignment from 64-bit signed integer to longint: %d mismatchs %d", bu, -ui); + $finish; + end + end + release bu; + // converting integers having 'x 'z values into type unsigned longint + // 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM) + // coercion to zero expected + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + ui = { {$random}, {$random} }; + ar_xz = xz_inject (ui); + ui = ar_xz; + ar_expected = xz_expected (ar_xz); + #1; + force bu_xz = ui; + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect conversion from 64-bit integer (with 'x 'z) to longint: %b mismatchs %b", bu_xz, ar_expected); + $finish; + end + end + release bu_xz; + // trying unsigned sums + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = { {$random}, {$random} }; + ar_xz = { {$random}, {$random} }; + #1; + bresult = bu + bu_xz; + #1; + if ( bresult !== u_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of unsigned longints: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz)); + $finish; + end + // invoking longint sum function + if ( fu_sum (bu, bu_xz) !== u_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of unsigned longint in function"); + $finish; + end + // invoking longint sum task + tu_sum (bu, bu_xz, bresult); + if ( bresult !== u_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of unsigned longint in task: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz)); + $finish; + end + // checking longint sum from module + if ( mcaresult !== u_sum(ar, ar_xz) || mabresult !== u_sum(ar, ar_xz)) + begin + $display ("FAILED - incorrect addition of unsigned longtint from module"); + $finish; + end + end + // trying unsigned mults + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = { {$random} % 32'd65536, {$random} % 32'd32768 }; + ar_xz = { {$random} % 32'd32768, {$random} % 32'd65536 }; + #1; + bresult = bu * bu_xz; // truncated mult + #1; + if ( bresult !== uh_mul(ar, ar_xz) ) + begin + $display ("FAILED - incorrect multiplication of unsigned longints: %0d mismatchs %0d", bresult, uh_mul(ar, ar_xz)); + $finish; + end + #1; + pv1 = {$random}; + pv2 = {$random}; + #1; + bresult = pv1 * pv2; // longint = int x int + #1; + if ( bresult !== u_mul(pv1, pv2) ) + begin + $display ("FAILED - incorrect multiplication of unsigned longints for int inputs"); + $finish; + end + // invoking longint mult function (int*int) + if ( fu_mul (pv1, pv2) !== u_mul(pv1, pv2) ) + begin + $display ("FAILED - incorrect product of unsigned ints for a function returning unsigned longint"); + $finish; + end + // invoking longint mult task (int*int) + tu_mul (pv1, pv2, bresult); + if ( bresult !== u_mul(pv1, pv2) ) + begin + $display ("FAILED - incorrect product of unsigned int in task returning unsigned longint"); + $finish; + end + end + // trying relational operators + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = { {$random}, {$random} }; + ar_xz = { {$random}, {$random} }; + #1; + if ( (bu < bu_xz ) != (ar < ar_xz) ) + begin + $display ("FAILED - incorrect 'less than' on unsigned longints"); + $finish; + end + if ( (bu <= bu_xz ) != (ar <= ar_xz) ) + begin + $display ("FAILED - incorrect 'less than or equal' on unsigned longints"); + $finish; + end + if ( (bu > bu_xz ) != (ar > ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than' on unsigned longints"); + $finish; + end + if ( (bu >= bu_xz ) != (ar >= ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than or equal' than on unsigned longints"); + $finish; + end + if ( (bu == bu_xz ) != (ar == ar_xz) ) + begin + $display ("FAILED - incorrect 'equal to' on unsigned longints"); + $finish; + end + if ( (bu != bu_xz ) != (ar != ar_xz) ) + begin + $display ("FAILED - incorrect 'not equal to' on unsigned ints"); + $finish; + end + end + # 1; + // signed small number to unsigned shorint + for (i = 0; i < N_REPS; i = i+1) + begin + #1; + slice = $random % 'h7fff_ffff; + force bu = slice; + ar = slice; + #1; + if (bu !== ar) + begin + $display ("FAILED - incorrect signed extend to unsigned longint"); + $finish; + end + end + release bu; + // trying concatenations (and replication) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + pt1 = {$random} % MAX8; + pt2 = {$random} % MAX8; + #1; + bresult = { {4{pt1}}, {4{pt2}} }; + #1; + if ( bresult[63:56] !== pt1 || bresult[55:48] !== pt1 || bresult[47:40] !== pt1 || bresult[39:32] !== pt1 || + bresult[31:24] !== pt2 || bresult[23:16] !== pt2 || bresult[15:8] !== pt2 || bresult[7:0] !== pt2) + begin + $display ("FAILED - incorrect concatenation and replication of bytes into unsigned longints"); + $finish; + end + #1; + ps1 = {$random} % MAX16; + ps2 = {$random} % MAX16; + #1; + bresult = { {2{ps1}}, {2{ps2}} }; + #1; + if ( bresult[63:48] !== ps1 || bresult[47:32] !== ps1 || bresult[31:16] !== ps2 || bresult[15:0] !== ps2) + begin + $display ("FAILED - incorrect concatenation and replication of shortint into unsigned long ints"); + $finish; + end + #1; + pv1 = {$random}; + pv2 = {$random}; + #1; + bresult = { pv1, pv2 }; + #1; + if ( bresult[63:32] !== pv1 || bresult[31:0] !== pv2) + begin + $display ("FAILED - incorrect concatenation and replication of int into unsigned longints"); + $finish; + end + end + #1; + $display("PASSED"); + end + + // this returns X and Z states into bit random positions for a value + function [LEN-1:0] xz_inject (input unsigned [LEN-1:0] value); + integer i, k; + time temp; + begin + temp = {$random, $random}; + for (i=0; i %b", val, y); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/unary_lnot2.v b/ivtest/ivltests/unary_lnot2.v new file mode 100644 index 000000000..31813b7cb --- /dev/null +++ b/ivtest/ivltests/unary_lnot2.v @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2000 Chris Lattner + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module test; + reg [3:0] val, y; + + initial begin + val = 2; + y = !{!val}; + if (y !== 4'b0001) begin + $display("FAILED -- !!4'b%b --> 4'b%b", val, y); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/unary_lnot3.v b/ivtest/ivltests/unary_lnot3.v new file mode 100644 index 000000000..30b452ab3 --- /dev/null +++ b/ivtest/ivltests/unary_lnot3.v @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This checks that ! of x works properly. + */ + +module main; + + reg x; + reg [1:0] xx; + + + initial begin + if (1'bx !== 1'bx) begin + $display("FAILED -- simple constant x does't compare."); + $finish; + end + + if (1'bx !== !1'bx) begin + $display("FAILED -- !1'bx comes out wrong."); + $finish; + end + + x = 1'bx; + if (x !== 1'bx) begin + $display("FAILED -- variable x comes out wrong."); + $finish; + end + + x = !x; + if (x !== 1'bx) begin + $display("FAILED -- ! of variable x comes out wrong."); + $finish; + end + + xx = 2'bx0; + if (xx !== 2'bx0) begin + $display("FAILED -- variable x comes out wrong."); + $finish; + end + + x = !xx; + if (x !== 1'bx) begin + $display("FAILED -- ! of variable xx comes out wrong."); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/unary_minus.v b/ivtest/ivltests/unary_minus.v new file mode 100644 index 000000000..e58eee5f6 --- /dev/null +++ b/ivtest/ivltests/unary_minus.v @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg [7:0] x, y; + + initial begin + x = -4; + if (x !== 8'hfc) begin + $display("FAILED -- x = -4 --> %b", x); + $finish; + end + + x = 4; + if (x !== 8'h04) begin + $display("FAILED"); + $finish; + end + + y = -x; + if (y !== 8'hfc) begin + $display("FAILED -- y = -%b --> %b", x, y); + $finish; + end + + $display("PASSED"); + end // initial begin + + +endmodule // main diff --git a/ivtest/ivltests/unary_minus1.v b/ivtest/ivltests/unary_minus1.v new file mode 100644 index 000000000..f867bb858 --- /dev/null +++ b/ivtest/ivltests/unary_minus1.v @@ -0,0 +1,62 @@ +// +// Copyright (c) 2001 Steve Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - From PR 272 reported by Lennart Augustsson + +module test; + + reg clk; + reg [31:0] x; + reg [31:0] y; + reg error; + + always@(posedge clk) + x <= -y; + + always #2 clk = ~clk; + + initial + begin + clk = 0; + error = 0; + y = 0; + + #10; + if( x !== 32'h0) + begin + error = 1; + $display("FAILED - X should still be 0, and it's not"); + end + + #10; + y = 32'h11111111; + #10; + if(x !== 32'heeee_eeef) + begin + error = 1; + $display("FAILED - X should still be EEEE_EEEF, rather x=%h",x); + end + + #10; + if(error == 0) + $display("PASSED"); + + $finish ; + end + +endmodule diff --git a/ivtest/ivltests/unary_minus2.v b/ivtest/ivltests/unary_minus2.v new file mode 100644 index 000000000..c978c0fc8 --- /dev/null +++ b/ivtest/ivltests/unary_minus2.v @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +`timescale 1ns / 1ns + +module U1 (OUT); + + parameter VALUE = -384; + + output [9:0] OUT; + + assign OUT = VALUE; + +endmodule + +module U2 (OUT); + + parameter VALUE = 96; + + output [9:0] OUT; + + assign OUT = VALUE; + +endmodule + +module main; + wire [9:0] out1, out2; + + U1 u1 (out1); + U2 u2 (out2); + + initial #1 begin + if (out1 !== 10'h280) begin + $display("FAILED -- out1 = %b", out1); + $finish; + end + + if (out2 !== 10'h060) begin + $display("FAILED -- out2 = %b", out2); + $finish; + end + + $display("PASSED"); + end // initial #1 +endmodule // main diff --git a/ivtest/ivltests/unary_minus3.v b/ivtest/ivltests/unary_minus3.v new file mode 100644 index 000000000..5dad21cb0 --- /dev/null +++ b/ivtest/ivltests/unary_minus3.v @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test(); + + reg [7:0] test; + wire [7:0] neg_test = -test; + + initial begin + for (test = 0 ; test < 255 ; test = test + 1) begin + #1 if (neg_test !== (-test)) begin + $display("FAILED -- %b !== -%b", neg_test, test); + $finish; + end + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/unary_minus4.v b/ivtest/ivltests/unary_minus4.v new file mode 100644 index 000000000..73edbe25a --- /dev/null +++ b/ivtest/ivltests/unary_minus4.v @@ -0,0 +1,25 @@ +module bug(); + + reg [15 : 0] in; + reg sel; + wire [31 : 0] result = { 16'd0, sel ? -in : in }; + + initial begin + in = 100; + sel = 0; + #1 if (result !== 32'h0000_0064) begin + $display("FAILED -- result=%h, sel=%b, in=%h", result, sel, in); + $finish; + end + + sel = 1; + #1 if (result !== 32'h0000_ff9c) begin + $display("FAILED == result=%h, sel=%b, in=%h, -in=%h", + result, sel, in, -in); + $finish; + end + + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/unary_nand.v b/ivtest/ivltests/unary_nand.v new file mode 100644 index 000000000..94a108176 --- /dev/null +++ b/ivtest/ivltests/unary_nand.v @@ -0,0 +1,55 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate unary nand ~&(value) +// + + +module main; + +reg [3:0] vect; +reg error; +wire result; + +assign result = ~&(vect); + +initial + begin + error = 0; + for(vect=4'b000;vect<4'b1111;vect = vect + 1) + begin + #1; + if(result !== 1'b1) + begin + $display("FAILED - Unary nand ~&(%b)=%b",vect,result); + error = 1'b1; + end + end + #1; + vect = 4'b1111; + #1; + if(result !== 1'b0) + begin + $display("FAILED - Unary nand ~&(%b)=%b",vect,result); + error = 1'b1; + end + if(error === 0 ) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/unary_nand2.v b/ivtest/ivltests/unary_nand2.v new file mode 100644 index 000000000..4488d98ae --- /dev/null +++ b/ivtest/ivltests/unary_nand2.v @@ -0,0 +1,55 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate unary nand ~&(value) +// + +// SJW - Make a version that uses behavioral code to implement ~& + +module main; + +reg [3:0] vect; +reg error; +reg result; + + +initial + begin + error = 0; + for(vect=4'b000;vect<4'b1111;vect = vect + 1) + begin + result = ~& vect; + if(result !== 1'b1) + begin + $display("FAILED - Unary nand ~&(%b)=%b",vect,result); + error = 1'b1; + end + end + #1; + vect = 4'b1111; + result = ~& vect; + if(result !== 1'b0) + begin + $display("FAILED - Unary nand ~&(%b)=%b",vect,result); + error = 1'b1; + end + if(error === 0 ) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/unary_nor.v b/ivtest/ivltests/unary_nor.v new file mode 100644 index 000000000..6436e948c --- /dev/null +++ b/ivtest/ivltests/unary_nor.v @@ -0,0 +1,55 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate unary nor ~|(value) +// + + +module main; + +reg [3:0] vect; +reg error; +wire result; + +assign result = ~|(vect); + +initial + begin + error = 0; + for(vect=4'b0001;vect<4'b1111;vect = vect + 1) + begin + #1; + if(result !== 1'b0) + begin + $display("FAILED - Unary nor ~|(%b)=%b",vect,result); + error = 1'b1; + end + end + #1; + vect = 4'b0000; + #1; + if(result !== 1'b1) + begin + $display("FAILED - Unary nor |~(%b)=%b",vect,result); + error = 1'b1; + end + if(error === 0 ) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/unary_nor2.v b/ivtest/ivltests/unary_nor2.v new file mode 100644 index 000000000..cbbcd4345 --- /dev/null +++ b/ivtest/ivltests/unary_nor2.v @@ -0,0 +1,54 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate unary nor ~|(value) +// SJW - ~| in behavioral assignment to reg. + + +module main; + +reg [3:0] vect; +reg error; +reg result; + + +initial + begin + error = 0; + for(vect=4'b0001;vect<4'b1111;vect = vect + 1) + begin + result = ~| vect; + if(result !== 1'b0) + begin + $display("FAILED - Unary nor ~|(%b)=%b",vect,result); + error = 1'b1; + end + end + #1; + vect = 4'b0000; + result = ~| vect; + if(result !== 1'b1) + begin + $display("FAILED - Unary nor |~(%b)=%b",vect,result); + error = 1'b1; + end + if(error === 0 ) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/unary_not.v b/ivtest/ivltests/unary_not.v new file mode 100644 index 000000000..56077249f --- /dev/null +++ b/ivtest/ivltests/unary_not.v @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2001 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg [7:0] tmp; + + initial begin + tmp = 8'b0; + #1 if (tmp !== 8'b00000000) begin + $display("FAILED to set tmp: %b", tmp); + $finish; + end + + tmp <= ~ 8'b0; + + #1 if (tmp !== 8'b11111111) begin + $display("FAILED to set ~0: %b", tmp); + $finish; + end + + tmp <= ~tmp; + + #1 if (tmp !== 8'b00000000) begin + $display("FAILED to invert tmp: %b", tmp); + $finish; + end + + $display("PASSED"); + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/unary_or.v b/ivtest/ivltests/unary_or.v new file mode 100644 index 000000000..594139907 --- /dev/null +++ b/ivtest/ivltests/unary_or.v @@ -0,0 +1,55 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate unary or |(value) +// + + +module main; + +reg [3:0] vect; +reg error; +wire result; + +assign result = |(vect); + +initial + begin + error = 0; + for(vect=4'b0001;vect<4'b1111;vect = vect + 1) + begin + #1; + if(result !== 1'b1) + begin + $display("FAILED - Unary or |(%b)=%b",vect,result); + error = 1'b1; + end + end + #1; + vect = 4'b0000; + #1; + if(result !== 1'b0) + begin + $display("FAILED - Unary or |(%b)=%b",vect,result); + error = 1'b1; + end + if(error === 0 ) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/unary_xnor1.v b/ivtest/ivltests/unary_xnor1.v new file mode 100644 index 000000000..073952c41 --- /dev/null +++ b/ivtest/ivltests/unary_xnor1.v @@ -0,0 +1,66 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate unary or ~^(value) +// + + +module main; + +reg [3:0] vect; +reg error; +wire result; + +assign result = ~^(vect); + +initial + begin + error = 0; + for(vect=4'b0001;vect<4'b0000;vect = vect << 1) + begin + #1; + if(result !== 1'b0) + begin + $display("FAILED - Unary xnor ~^(%b)=%b",vect,result); + error = 1'b1; + end + end + #1; + for(vect=4'b0011;vect<4'b0000;vect = vect << 1) + begin + #1; + if(result !== 1'b0) + begin + $display("FAILED - Unary xnor ~^(%b)=%b",vect,result); + error = 1'b1; + end + end + #1; + + vect = 4'b0000; + #1; + if(result !== 1'b1) + begin + $display("FAILED - Unary xnor ~^(%b)=%b",vect,result); + error = 1'b1; + end + if(error === 0 ) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/unary_xnor2.v b/ivtest/ivltests/unary_xnor2.v new file mode 100644 index 000000000..706c821d7 --- /dev/null +++ b/ivtest/ivltests/unary_xnor2.v @@ -0,0 +1,66 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate unary or ^~(value) +// + + +module main; + +reg [3:0] vect; +reg error; +wire result; + +assign result = ^~(vect); + +initial + begin + error = 0; + for(vect=4'b0001;vect<4'b0000;vect = vect << 1) + begin + #1; + if(result !== 1'b0) + begin + $display("FAILED - Unary xnor ^~(%b)=%b",vect,result); + error = 1'b1; + end + end + #1; + for(vect=4'b0011;vect<4'b0000;vect = vect << 1) + begin + #1; + if(result !== 1'b0) + begin + $display("FAILED - Unary xnor ^~(%b)=%b",vect,result); + error = 1'b1; + end + end + #1; + + vect = 4'b0000; + #1; + if(result !== 1'b1) + begin + $display("FAILED - Unary xnor ^~(%b)=%b",vect,result); + error = 1'b1; + end + if(error === 0 ) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/unary_xor.v b/ivtest/ivltests/unary_xor.v new file mode 100644 index 000000000..bae3ba38c --- /dev/null +++ b/ivtest/ivltests/unary_xor.v @@ -0,0 +1,66 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate unary or |(value) +// + + +module main; + +reg [3:0] vect; +reg error; +wire result; + +assign result = ^(vect); + +initial + begin + error = 0; + for(vect=4'b0001;vect<4'b0000;vect = vect << 1) + begin + #1; + if(result !== 1'b1) + begin + $display("FAILED - Unary xor ^(%b)=%b",vect,result); + error = 1'b1; + end + end + #1; + for(vect=4'b0011;vect<4'b0000;vect = vect << 1) + begin + #1; + if(result !== 1'b0) + begin + $display("FAILED - Unary xor ^(%b)=%b",vect,result); + error = 1'b1; + end + end + #1; + + vect = 4'b0000; + #1; + if(result !== 1'b0) + begin + $display("FAILED - Unary xor ^(%b)=%b",vect,result); + error = 1'b1; + end + if(error === 0 ) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/uncon_drive.v b/ivtest/ivltests/uncon_drive.v new file mode 100644 index 000000000..abcf92d90 --- /dev/null +++ b/ivtest/ivltests/uncon_drive.v @@ -0,0 +1,41 @@ +module top; + reg pass; + + highz dutz(); + pulllow dut0(); + pullhigh dut1(); + + initial begin + pass = 1'b1; + #10; + if (pass) $display("PASSED"); + end +endmodule + +module highz(in); + input in; + initial #1 if (in !== 1'bz) begin + $display("FAILED: high-Z of floating input port (%b)", in); + top.pass = 1'b0; + end +endmodule + +`unconnected_drive pull0 +module pulllow(in); + input in; + initial #1 if (in !== 1'b0) begin + $display("FAILED: pull0 of floating input port (%b)", in); + top.pass = 1'b0; + end +endmodule +`nounconnected_drive + +`unconnected_drive pull1 +module pullhigh(in); + input in; + initial #1 if (in !== 1'b1) begin + $display("FAILED: pull1 of floating input port (%b)", in); + top.pass = 1'b0; + end +endmodule +`nounconnected_drive diff --git a/ivtest/ivltests/undef.v b/ivtest/ivltests/undef.v new file mode 100644 index 000000000..400a2bc1a --- /dev/null +++ b/ivtest/ivltests/undef.v @@ -0,0 +1,29 @@ +/* + * 1364-2001 19.3.2 "An undefined text macro has no value, just as if it had + * never been defined." + */ +`define a 1 + +`ifdef a +`define b 1 +`else +`define b 0 +`endif + +`undef a + +`ifdef a +`define c 1 +`else +`define c 0 +`endif + +module test; +initial begin + if(`a+1 !== 1) begin $display("FAIL"); $finish; end + if(`b+1 === 1) begin $display("FAIL"); $finish; end + if(`c+1 !== 1) begin $display("FAIL"); $finish; end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/undef_lval_select.v b/ivtest/ivltests/undef_lval_select.v new file mode 100644 index 000000000..d458c1bb0 --- /dev/null +++ b/ivtest/ivltests/undef_lval_select.v @@ -0,0 +1,124 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + reg [2:-1] vec; + integer idx; + + initial begin + pass = 1'b1; + + idx = 'bx; + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1'bx] = 1'b1; +`endif + if (vec !== 4'bxxx) begin + $display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; + vec[idx] = 1'b1; + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1'bx:0] = 1'b1; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx:0], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[0:1'bx] = 1'b1; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[0:1'bx], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1'bx:1'bx] = 1'b1; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx:1'bx], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1'bx+:1] = 1'b1; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx+:1], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1'bx+:2] = 2'b01; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx+:2], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1'bx-:1] = 1'b1; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx-:1], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1'bx-:2] = 2'b01; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx-:2], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; + vec[idx+:1] = 1'b1; + if (vec !== 4'bxxxx) begin + $display("Failed vec[idx+:1], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; + vec[idx+:2] = 2'b01; + if (vec !== 4'bxxxx) begin + $display("Failed vec[idx+:2], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; + vec[idx-:1] = 1'b1; + if (vec !== 4'bxxxx) begin + $display("Failed vec[idx-:1], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; + vec[idx-:2] = 2'b01; + if (vec !== 4'bxxxx) begin + $display("Failed vec[idx-:2], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/undef_lval_select2.v b/ivtest/ivltests/undef_lval_select2.v new file mode 100644 index 000000000..1a01687fa --- /dev/null +++ b/ivtest/ivltests/undef_lval_select2.v @@ -0,0 +1,124 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + reg [2:-1] vec; + integer idx; + + initial begin + pass = 1'b1; + + idx = 'bx; + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1'bx] <= 1'b1; +`endif + #1 if (vec !== 4'bxxx) begin + $display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; + vec[idx] <= 1'b1; + #1 if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1'bx:0] <= 1'b1; +`endif + #1 if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx:0], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[0:1'bx] <= 1'b1; +`endif + #1 if (vec !== 4'bxxxx) begin + $display("Failed vec[0:1'bx], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1'bx:1'bx] <= 1'b1; +`endif + #1 if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx:1'bx], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1'bx+:1] <= 1'b1; +`endif + #1 if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx+:1], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1'bx+:2] <= 2'b01; +`endif + #1 if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx+:2], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1'bx-:1] <= 1'b1; +`endif + #1 if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx-:1], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1'bx-:2] <= 2'b01; +`endif + #1 if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx-:2], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; + vec[idx+:1] <= 1'b1; + #1 if (vec !== 4'bxxxx) begin + $display("Failed vec[idx+:1], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; + vec[idx+:2] <= 2'b01; + #1 if (vec !== 4'bxxxx) begin + $display("Failed vec[idx+:2], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; + vec[idx-:1] <= 1'b1; + #1 if (vec !== 4'bxxxx) begin + $display("Failed vec[idx-:1], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + vec = 4'bxxxx; + vec[idx-:2] <= 2'b01; + #1 if (vec !== 4'bxxxx) begin + $display("Failed vec[idx-:2], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/undef_lval_select3a.v b/ivtest/ivltests/undef_lval_select3a.v new file mode 100644 index 000000000..a1d8baa71 --- /dev/null +++ b/ivtest/ivltests/undef_lval_select3a.v @@ -0,0 +1,110 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + reg [2:-1] vec; + + initial begin + pass = 1'b1; + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign vec[1'bx] = 1'b1; +`endif + if (vec !== 4'bxxx) begin + $display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + deassign vec[1'bx]; +`endif + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign vec[1'bx:0] = 1'b1; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx:0], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + deassign vec[1'bx:0]; +`endif + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign vec[0:1'bx] = 1'b1; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[0:1'bx], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + deassign vec[0:1'bx]; +`endif + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign vec[1'bx:1'bx] = 1'b1; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx:1'bx], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + deassign vec[1'bx:1'bx]; +`endif + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign vec[1'bx+:1] = 1'b1; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx+:1], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + deassign vec[1'bx+:1]; +`endif + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign vec[1'bx+:2] = 2'b01; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx+:2], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + deassign vec[1'bx+:2]; +`endif + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign vec[1'bx-:1] = 1'b1; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx-:1], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + deassign vec[1'bx-:1]; +`endif + + vec = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign vec[1'bx-:2] = 2'b01; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx-:2], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + deassign vec[1'bx-:2]; +`endif + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/undef_lval_select3b.v b/ivtest/ivltests/undef_lval_select3b.v new file mode 100644 index 000000000..5b852fb4b --- /dev/null +++ b/ivtest/ivltests/undef_lval_select3b.v @@ -0,0 +1,10 @@ +module top; + reg [2:-1] vec; + integer idx; + + initial begin + idx = 'bx; + assign vec[idx] = 1'b1; + deassign vec[idx]; + end +endmodule diff --git a/ivtest/ivltests/undef_lval_select3c.v b/ivtest/ivltests/undef_lval_select3c.v new file mode 100644 index 000000000..5ef210f51 --- /dev/null +++ b/ivtest/ivltests/undef_lval_select3c.v @@ -0,0 +1,10 @@ +module top; + reg [2:-1] vec; + integer idx; + + initial begin + idx = 'bx; + assign vec[idx+:1] = 1'b1; + deassign vec[idx+:1]; + end +endmodule diff --git a/ivtest/ivltests/undef_lval_select4a.v b/ivtest/ivltests/undef_lval_select4a.v new file mode 100644 index 000000000..4009634ab --- /dev/null +++ b/ivtest/ivltests/undef_lval_select4a.v @@ -0,0 +1,104 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + wire [2:-1] vec; + + assign vec = 4'bxxxx; + + initial begin + pass = 1'b1; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + force vec[1'bx] = 1'b1; +`endif + if (vec !== 4'bxxx) begin + $display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + release vec[1'bx]; +`endif + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + force vec[1'bx:0] = 1'b1; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx:0], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + release vec[1'bx:0]; +`endif + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + force vec[0:1'bx] = 1'b1; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[0:1'bx], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + release vec[0:1'bx]; +`endif + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + force vec[1'bx:1'bx] = 1'b1; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx:1'bx], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + release vec[1'bx:1'bx]; +`endif + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + force vec[1'bx+:1] = 1'b1; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx+:1], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + release vec[1'bx+:1]; +`endif + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + force vec[1'bx+:2] = 2'b01; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx+:2], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + release vec[1'bx+:2]; +`endif + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + force vec[1'bx-:1] = 1'b1; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx-:1], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + release vec[1'bx-:1]; +`endif + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + force vec[1'bx-:2] = 2'b01; +`endif + if (vec !== 4'bxxxx) begin + $display("Failed vec[1'bx-:2], expected 4'bxxxx, got %b", vec); + pass = 1'b0; + end +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + release vec[1'bx-:2]; +`endif + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/undef_lval_select4b.v b/ivtest/ivltests/undef_lval_select4b.v new file mode 100644 index 000000000..2f2becbba --- /dev/null +++ b/ivtest/ivltests/undef_lval_select4b.v @@ -0,0 +1,10 @@ +module top; + wire [2:-1] vec; + integer idx; + + initial begin + idx = 'bx; + force vec[idx] = 1'b1; + release vec[idx]; + end +endmodule diff --git a/ivtest/ivltests/undef_lval_select4c.v b/ivtest/ivltests/undef_lval_select4c.v new file mode 100644 index 000000000..504c9da27 --- /dev/null +++ b/ivtest/ivltests/undef_lval_select4c.v @@ -0,0 +1,10 @@ +module top; + wire [2:-1] vec; + integer idx; + + initial begin + idx = 'bx; + force vec[idx+:1] = 1'b1; + release vec[idx+:1]; + end +endmodule diff --git a/ivtest/ivltests/undef_lval_select5.v b/ivtest/ivltests/undef_lval_select5.v new file mode 100644 index 000000000..235f19dce --- /dev/null +++ b/ivtest/ivltests/undef_lval_select5.v @@ -0,0 +1,68 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + wire [2:-1] vec1; + wire [2:-1] vec2; + wire [2:-1] vec3; + wire [2:-1] vec4; + wire [2:-1] vec5; + wire [2:-1] vec6; + + assign vec1 = 4'bxxxx; + assign vec2 = 4'bxxxx; + assign vec3 = 4'bxxxx; + assign vec4 = 4'bxxxx; + assign vec5 = 4'bxxxx; + assign vec6 = 4'bxxxx; + +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + assign vec1[1'bx] = 1'b1; + + assign vec2[1'bx:0] = 1'b1; + assign vec3[0:1'bx] = 1'b1; + + assign vec4[1'bx:1'bx] = 1'b1; + + assign vec5[1'bx+:1] = 1'b1; + assign vec6[1'bx-:1] = 1'b1; +`endif + + initial begin + pass = 1'b1; + + if (vec1 !== 4'bxxx) begin + $display("Failed vec1, expected 4'bxxxx, got %b", vec1); + pass = 1'b0; + end + + if (vec2 !== 4'bxxx) begin + $display("Failed vec2, expected 4'bxxxx, got %b", vec2); + pass = 1'b0; + end + + if (vec3 !== 4'bxxx) begin + $display("Failed vec3, expected 4'bxxxx, got %b", vec3); + pass = 1'b0; + end + + if (vec4 !== 4'bxxx) begin + $display("Failed vec4, expected 4'bxxxx, got %b", vec4); + pass = 1'b0; + end + + if (vec5 !== 4'bxxx) begin + $display("Failed vec5, expected 4'bxxxx, got %b", vec5); + pass = 1'b0; + end + + if (vec6 !== 4'bxxx) begin + $display("Failed vec6, expected 4'bxxxx, got %b", vec6); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/undef_lval_select_SV.v b/ivtest/ivltests/undef_lval_select_SV.v new file mode 100644 index 000000000..dfcdb0941 --- /dev/null +++ b/ivtest/ivltests/undef_lval_select_SV.v @@ -0,0 +1,27 @@ +`ifdef __ICARUS__ + `define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST +`endif + +module top; + reg pass; + reg [1:-1][3:0] vec; + + initial begin + pass = 1'b1; + + vec[1] = 4'bxxxx; + vec[0] = 4'bxxxx; + vec[-1] = 4'bxxxx; +`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST + vec[1'bx] = 4'b1001; +`endif + if ((vec[1] !== 4'bxxx) && (vec[0] !== 4'bxxxx) && + (vec[-1] !== 4'bxxxx)) begin + $display("Failed vec[1'bx], expected 4'bxxxx, got %b, %b,%b", + vec[1], vec[0], vec[-1]); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/undefined_shift.v b/ivtest/ivltests/undefined_shift.v new file mode 100644 index 000000000..1a914f42b --- /dev/null +++ b/ivtest/ivltests/undefined_shift.v @@ -0,0 +1,163 @@ +// Check that when the right hand operand of a shift operation +// contains 'x' or 'z' bits, the result is undefined. +module test; + reg pass; + reg signed [3:0] lhs; + reg [3:0] rhs; + reg [3:0] res; + + wire [3:0] res1 = lhs << rhs; + wire [3:0] res2 = lhs >> rhs; + wire [3:0] res3 = lhs >>> rhs; + + wire [3:0] res4 = lhs << 4'b000x; + wire [3:0] res5 = lhs >> 4'b00x0; + wire [3:0] res6 = lhs >>> 4'b0z00; + + wire [3:0] res7 = 4'd1 << 4'b000x; + wire [3:0] res8 = 4'd1 >> 4'b00x0; + wire [3:0] res9 = 4'd1 >>> 4'b0z00; + + wire [3:0] res10 = 4'd0 << rhs; + wire [3:0] res11 = 4'd0 >> rhs; + wire [3:0] res12 = 4'd0 >>> rhs; + + initial begin + pass = 1'b1; + lhs = 4'd1; + + if (res1 !== 4'bxxxx) begin + $display("FAILED test 1, expected 4'bxxxx, got 4'b%b", res1); + pass = 1'b0; + end + + if (res2 !== 4'bxxxx) begin + $display("FAILED test 2, expected 4'bxxxx, got 4'b%b", res2); + pass = 1'b0; + end + + if (res3 !== 4'bxxxx) begin + $display("FAILED test 3, expected 4'bxxxx, got 4'b%b", res3); + pass = 1'b0; + end + + if (res4 !== 4'bxxxx) begin + $display("FAILED test 4, expected 4'bxxxx, got 4'b%b", res4); + pass = 1'b0; + end + + if (res5 !== 4'bxxxx) begin + $display("FAILED test 5, expected 4'bxxxx, got 4'b%b", res5); + pass = 1'b0; + end + + if (res6 !== 4'bxxxx) begin + $display("FAILED test 6, expected 4'bxxxx, got 4'b%b", res6); + pass = 1'b0; + end + + if (res7 !== 4'bxxxx) begin + $display("FAILED test 7, expected 4'bxxxx, got 4'b%b", res7); + pass = 1'b0; + end + + if (res8 !== 4'bxxxx) begin + $display("FAILED test 8, expected 4'bxxxx, got 4'b%b", res8); + pass = 1'b0; + end + + if (res9 !== 4'bxxxx) begin + $display("FAILED test 9, expected 4'bxxxx, got 4'b%b", res9); + pass = 1'b0; + end + + if (res10 !== 4'bxxxx) begin + $display("FAILED test 10, expected 4'bxxxx, got 4'b%b", res10); + pass = 1'b0; + end + + if (res11 !== 4'bxxxx) begin + $display("FAILED test 11, expected 4'bxxxx, got 4'b%b", res11); + pass = 1'b0; + end + + if (res12 !== 4'bxxxx) begin + $display("FAILED test 12, expected 4'bxxxx, got 4'b%b", res12); + pass = 1'b0; + end + + res = lhs << rhs; + if (res !== 4'bxxxx) begin + $display("FAILED test 13, expected 4'bxxxx, got 4'b%b", res); + pass = 1'b0; + end + + res = lhs >> rhs; + if (res !== 4'bxxxx) begin + $display("FAILED test 14, expected 4'bxxxx, got 4'b%b", res); + pass = 1'b0; + end + + res = lhs >>> rhs; + if (res !== 4'bxxxx) begin + $display("FAILED test 15, expected 4'bxxxx, got 4'b%b", res); + pass = 1'b0; + end + + res = lhs << 4'b000x; + if (res !== 4'bxxxx) begin + $display("FAILED test 16, expected 4'bxxxx, got 4'b%b", res); + pass = 1'b0; + end + + res = lhs >> 4'b00x0; + if (res !== 4'bxxxx) begin + $display("FAILED test 17, expected 4'bxxxx, got 4'b%b", res); + pass = 1'b0; + end + + res = lhs >>> 4'b0z00; + if (res !== 4'bxxxx) begin + $display("FAILED test 18, expected 4'bxxxx, got 4'b%b", res); + pass = 1'b0; + end + + res = 4'd1 << 4'b000x; + if (res !== 4'bxxxx) begin + $display("FAILED test 19, expected 4'bxxxx, got 4'b%b", res); + pass = 1'b0; + end + + res = 4'd1 >> 4'b00x0; + if (res !== 4'bxxxx) begin + $display("FAILED test 20, expected 4'bxxxx, got 4'b%b", res); + pass = 1'b0; + end + + res = 4'd1 >>> 4'b0z00; + if (res !== 4'bxxxx) begin + $display("FAILED test 21, expected 4'bxxxx, got 4'b%b", res); + pass = 1'b0; + end + + res = 4'd0 << rhs; + if (res !== 4'bxxxx) begin + $display("FAILED test 22, expected 4'bxxxx, got 4'b%b", res); + pass = 1'b0; + end + + res = 4'd0 >> rhs; + if (res !== 4'bxxxx) begin + $display("FAILED test 23, expected 4'bxxxx, got 4'b%b", res); + pass = 1'b0; + end + + res = 4'd0 >>> rhs; + if (res !== 4'bxxxx) begin + $display("FAILED test 24, expected 4'bxxxx, got 4'b%b", res); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/unnamed_generate_block.v b/ivtest/ivltests/unnamed_generate_block.v new file mode 100644 index 000000000..fede8c5fd --- /dev/null +++ b/ivtest/ivltests/unnamed_generate_block.v @@ -0,0 +1,72 @@ +// Copyright 2007, Martin Whitaker. +// This code may be freely copied for any purpose. + +module unnamed_generate_block(); + +localparam up = 1; + +wire [2:0] count1; +wire [2:0] count2; +wire [2:0] count3; + +generate + if (up) + count_up counter(count1); + else + count_down counter(count1); +endgenerate + +generate + if (up) + begin:genblk1 + count_up counter(count2); + end + else + begin:genblk1 + count_down counter(count2); + end +endgenerate + +count_down genblk01(count3); + +initial begin:genblk001 + reg [2:0] count; + + #1 count = 4; + #1 count = 5; + #1 count = 6; + #1 count = 7; +end + +always @(genblk0001.counter.count) begin + $display(genblk0001.counter.count); +end + +//initial begin +// $dumpfile("dump.vcd"); +// $dumpvars; +//end + +endmodule + +module count_up(output reg [2:0] count); + +initial begin + #1 count = 0; + #1 count = 1; + #1 count = 2; + #1 count = 3; +end + +endmodule + +module count_down(output reg [2:0] count); + +initial begin + #1 count = 3; + #1 count = 2; + #1 count = 1; + #1 count = 0; +end + +endmodule diff --git a/ivtest/ivltests/unp_array_typedef.v b/ivtest/ivltests/unp_array_typedef.v new file mode 100644 index 000000000..bbb0377a5 --- /dev/null +++ b/ivtest/ivltests/unp_array_typedef.v @@ -0,0 +1,175 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for typedefs using unpacked arrays (including dynamic arrays). + +module unp_array_typedef(); + typedef logic [7:0] bit_darray []; + typedef logic [15:0] bit_unparray [4]; + typedef string string_darray []; + typedef string string_unparray [2]; + typedef real real_darray []; + typedef real real_unparray [5]; + typedef int int_darray []; + typedef int int_unparray [3]; + typedef struct packed { + logic [7:0] high; + logic [7:0] low; + } word; + typedef word word_darray []; + typedef word word_unparray [2]; + + bit_darray bit_darr; + bit_unparray bit_unparr; + string_darray string_darr; + string_unparray string_unparr; + real_darray real_darr; + real_unparray real_unparr; + int_darray int_darr; + int_unparray int_unparr; + word_darray word_darr; + word_unparray word_unparr; + +initial begin + // Bit type + bit_darr = new[3]; + bit_darr[0] = "a"; + bit_darr[1] = "b"; + bit_darr[2] = "c"; + + if(bit_darr[0] !== "a" || bit_darr[1] !== "b" || bit_darr[2] !== "c") + begin + $display("FAILED 1"); + $finish(); + end + + bit_unparr[0] = 16'h1234; + bit_unparr[1] = 16'h5678; + bit_unparr[2] = 16'h9abc; + + if(bit_unparr[0] !== 16'h1234 || bit_unparr[1] !== 16'h5678 || bit_unparr[2] !== 16'h9abc) + begin + $display("FAILED 2"); + $finish(); + end + + // String type + string_darr = new[3]; + string_darr[0] = "icarus"; + string_darr[1] = "verilog"; + string_darr[2] = "test"; + + if(string_darr[0] != "icarus" || string_darr[1] != "verilog" || string_darr[2] != "test") begin + $display("FAILED 3"); + $finish(); + end + + string_unparr[0] = "test_string"; + string_unparr[1] = "another test"; + + if(string_unparr[0] != "test_string" || string_unparr[1] != "another test") begin + $display("FAILED 4"); + $finish(); + end + + // Real type + real_darr = new[3]; + real_darr[0] = -1.20; + real_darr[1] = 2.43; + real_darr[2] = 7.4; + + if(real_darr[0] != -1.20 || real_darr[1] != 2.43 || real_darr[2] != 7.4) begin + $display("FAILED 5"); + $finish(); + end + + real_unparr[0] = 1.0; + real_unparr[1] = 2.5; + real_unparr[2] = 3.0; + real_unparr[3] = 4.5; + real_unparr[4] = 5.0; + + if(real_unparr[0] != 1.0 || real_unparr[1] != 2.5 || real_unparr[2] != 3.0 || + real_unparr[3] != 4.5 || real_unparr[4] != 5.0) begin + $display("FAILED 6"); + $finish(); + end + + // Integer type + int_darr = new[3]; + int_darr[0] = -3; + int_darr[1] = 3; + int_darr[2] = 72; + + if(int_darr[0] !== -3 || int_darr[1] != 3 || int_darr[2] != 72) begin + $display("FAILED 7"); + $finish(); + end + + int_unparr[0] = 22; + int_unparr[1] = 18; + int_unparr[2] = 9; + + if(int_unparr[0] !== 22 || int_unparr[1] != 18 || int_unparr[2] != 9) begin + $display("FAILED 8"); + $finish(); + end + + // Struct + // TODO at the moment dynamic arrays of struct are not supported + /* word_darr = new[3]; + word_darr[0].high = 8'h11; + word_darr[0].low = 8'h22; + word_darr[1].high = 8'h33; + word_darr[1].low = 8'h44; + word_darr[2].high = 8'h55; + word_darr[2].low = 8'h66; + + if(word_darr[0].low !== 8'h22 || word_darr[0].high !== 8'h11 || + word_darr[1].low !== 8'h44 || word_darr[1].high !== 8'h33) begin + word_darr[2].low !== 8'h66 || word_darr[2].high !== 8'h55) begin + $display("FAILED 9"); + $finish(); + end*/ + + // TODO not available at the moment + //word_unparr[0].high = 8'haa; + //word_unparr[0].low = 8'h55; + //word_unparr[1].high = 8'h02; + //word_unparr[1].low = 8'h01; + + //if(word_unparr[0].low !== 8'h55 || word_unparr[0].high !== 8'haa || + //word_unparr[1].low !== 8'h01 || word_unparr[1].high !== 8'h02) begin + //$display("FAILED 10"); + //$finish(); + //end + + word_unparr[0] = 16'haa55; + word_unparr[1] = 16'h0102; + + if(word_unparr[0] !== 16'haa55 || word_unparr[1] !== 16'h0102) + begin + $display("FAILED 10"); + $finish(); + end + + $display("PASSED"); +end +endmodule + diff --git a/ivtest/ivltests/urand.v b/ivtest/ivltests/urand.v new file mode 100644 index 000000000..74c3c320d --- /dev/null +++ b/ivtest/ivltests/urand.v @@ -0,0 +1,18 @@ +`begin_keywords "1364-2005" +module top; + reg [31:0] var; + integer ivar; + + wire [31:0] out = ivar + 2147483648; + + initial begin + $monitor(var,, out); + var = 0; + ivar = -2147483648; + repeat (60) begin + #1 var = $urandom; + ivar = $random; + end + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/urand_r.v b/ivtest/ivltests/urand_r.v new file mode 100644 index 000000000..9f52a394a --- /dev/null +++ b/ivtest/ivltests/urand_r.v @@ -0,0 +1,15 @@ +`begin_keywords "1364-2005" +module top; + reg [31:0] var; + + initial begin + $monitor(var); + var = 0; + repeat (60) begin + #1 var = $urandom_range(16,0); +// #1 var = $urandom_range(4294967295,0); +// #1 var = $urandom_range(-1,0); + end + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/urand_r2.v b/ivtest/ivltests/urand_r2.v new file mode 100644 index 000000000..bf17c4841 --- /dev/null +++ b/ivtest/ivltests/urand_r2.v @@ -0,0 +1,13 @@ +`begin_keywords "1364-2005" +module top; + reg [31:0] var; + + initial begin + $monitor(var); + var = 0; + repeat (60) begin + #1 var = $urandom_range(0,16); + end + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/urand_r3.v b/ivtest/ivltests/urand_r3.v new file mode 100644 index 000000000..3fd546a1a --- /dev/null +++ b/ivtest/ivltests/urand_r3.v @@ -0,0 +1,13 @@ +`begin_keywords "1364-2005" +module top; + reg [31:0] var; + + initial begin + $monitor(var); + var = 0; + repeat (60) begin + #1 var = $urandom_range(16); + end + end +endmodule +`end_keywords diff --git a/ivtest/ivltests/ushortint_test.v b/ivtest/ivltests/ushortint_test.v new file mode 100644 index 000000000..feb2dceba --- /dev/null +++ b/ivtest/ivltests/ushortint_test.v @@ -0,0 +1,358 @@ +// Eleven basic tests in here: +// 1. shortint must be initialised before any initial or always block +// 2. assignments to (unsigned) shortint with random numbers +// 3. assignments to (unsigned) shortint with random values including X and Z +// 4. converting unsigned integers to unsigned shortint +// 5. converting signed integers to unsigned shortint +// 6. converting integers including X and Z states to unsigned shortint +// 7. trying unsigned sums (procedural, function, task and module) +// 8. trying unsigned mults (procedural, function and task) +// 9. trying relational operators +// 10. smaller signed numbers to unsigned shortint (signed extension) +// 11. trying some concatenations from bytes to shortints + +module mu_add (input shortint unsigned a, b, output shortint unsigned sc, ss); + assign sc = a + b; + always @(a, b) ss = a + b; +endmodule + +module main; + parameter N_REPS = 500; // repetition with random numbers + parameter XZ_REPS = 500; // repetition with 'x 'z values + parameter UMAX = 65536; + parameter MAX8 = 256; + parameter LEN = 16; + // variables used as golden references + reg unsigned [LEN-1:0] ar; // holds numbers + reg unsigned [LEN-1:0] ar_xz; // holds 'x and/or 'z in random positions + reg unsigned [LEN-1:0] ar_expected; + integer unsigned ui; + integer signed si; + reg signed [LEN/2-1:0] slice; + + // type assumed tested before + byte unsigned pt1, pt2; + + // types to be tested + shortint unsigned bu; // holds numbers + shortint unsigned bu_xz; // 'x and 'z are attempted on this + shortint unsigned bresult; // hold results from sums and mults + shortint unsigned mcaresult; // wired to a module instance + shortint unsigned mabresult; // also wired to a module instance + + + integer i; + + // continuous assigments + // type LHS type RHS + // --------- --------- + // shortint 4-value logic + assign bu = ar; + assign bu_xz = ar_xz; + + // module instantiation + mu_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) ); + + // all test + initial begin + // time 0 checkings (Section 6.4 of IEEE 1850 LRM) + if (bu !== 16'b0 || bu_xz !== 16'b0 || bresult !== 16'b0 || mcaresult !== 16'b0 || mabresult !== 16'b0) + begin + $display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz); + $finish; + end + // driving shortint type with unsigned random numbers from a variable + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = {$random} % UMAX; + #1; + if (bu !== ar) + begin + $display ("FAILED - incorrect assigment to shortint: %b", bu); + $finish; + end + end + # 1; + // attempting to drive variables having 'x 'z values into type unsigned shortint + // 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + ar = {$random} % UMAX; + ar_xz = xz_inject (ar); + ar_expected = xz_expected (ar_xz); + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect assigment to shortint (when 'x 'z): %b", bu); + $finish; + end + end + // converting unsigned integers to unsigned shortint + // truncation expected (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ui = {$random} % UMAX; + #1; + force bu = ui; + #1; + if (bu !== ui[LEN-1:0]) + begin + $display ("FAILED - incorrect truncation from unsigned integer to shortint: %b", bu); + $finish; + end + end + release bu; + // converting signed integers to unsigned shortints + // truncation expected (Section 4.3.2 of IEEE 1850 LRM) + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + si = $random % UMAX/2-1; + #1; + force bu = si; + #1; + if (bu !== si[LEN-1:0]) + begin + $display ("FAILED - incorrect truncation from signed integer to shortint: %b mismatchs %b", bu, si[LEN-1:0]); + $finish; + end + end + release bu; + // converting integers having 'x 'z values into type unsigned shortint + // 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM) + // truncation and coercion to zero expected + for (i = 0; i< XZ_REPS; i = i+1) + begin + #1; + si = $random; + ar_xz = xz_inject (si[LEN-1:0]); + si = {si[31:LEN], ar_xz}; + ar_expected = xz_expected (ar_xz); + #1; + force bu_xz = si; + #1; + if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0 + begin + $display ("FAILED - incorrect conversion from integer (with 'x 'z) to shortint: %b mismatchs %b", bu_xz, ar_expected); + $finish; + end + end + release bu_xz; + // trying unsigned sums + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = {$random} % UMAX; + ar_xz = {$random} % UMAX; + #1; + bresult = bu + bu_xz; + #1; + if ( bresult !== u_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of unsigned shortints: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz)); + $finish; + end + // invoking shortint sum function + if ( fu_sum (bu, bu_xz) !== u_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of unsigned shortint in function"); + $finish; + end + // invoking byte sum task + tu_sum (bu, bu_xz, bresult); + if ( bresult !== u_sum(ar, ar_xz) ) + begin + $display ("FAILED - incorrect addition of unsigned shortint in task: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz)); + $finish; + end + // checking shortint sum from module + if ( mcaresult !== u_sum(ar, ar_xz) || mabresult !== u_sum(ar, ar_xz)) + begin + $display ("FAILED - incorrect addition of unsigned shortint from module"); + $finish; + end + end + // trying unsigned mults + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = ({$random} % UMAX) << LEN/2; + ar_xz = ({$random} % UMAX) << (LEN/2 - 1); + #1; + bresult = bu * bu_xz; // truncated multiplication + #1; + if ( bresult !== uh_mul(ar, ar_xz) ) + begin + $display ("FAILED - incorrect multiplication of unsigned shortints (truncated)"); + $finish; + end + #1; + pt1 = {$random}; + pt2 = {$random}; + #1; + bresult = pt1 * pt2; // shortint = byte x byte + #1; + if ( bresult !== u_mul(pt1, pt2) ) + begin + $display ("FAILED - incorrect multiplication of unsigned shortints for bytes inputs"); + $finish; + end + // invoking shortint mult function (byte*byte) + if ( fu_mul (pt1, pt2) !== u_mul(pt1, pt2) ) + begin + $display ("FAILED - incorrect product of unsigned bytes for a function returning unsigned shortint"); + $finish; + end + // invoking shortint mult task (byte*byte) + tu_mul (pt1, pt2, bresult); + if ( bresult !== u_mul(pt1, pt2) ) + begin + $display ("FAILED - incorrect product of unsigned bytes in task returning unsigned shortint"); + $finish; + end + end + // trying relational operators + for (i = 0; i< N_REPS; i = i+1) + begin + #1; + ar = {$random} % UMAX; + ar_xz = {$random} % UMAX; + #1; + if ( (bu < bu_xz ) !== (ar < ar_xz) ) + begin + $display ("FAILED - incorrect 'less than' on unsigned shortints"); + $finish; + end + if ( (bu <= bu_xz ) !== (ar <= ar_xz) ) + begin + $display ("FAILED - incorrect 'less than or equal' on unsigned shortints"); + $finish; + end + if ( (bu > bu_xz ) !== (ar > ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than' on unsigned shortints"); + $finish; + end + if ( (bu >= bu_xz ) !== (ar >= ar_xz) ) + begin + $display ("FAILED - incorrect 'greater than or equal' than on unsigned shortints"); + $finish; + end + if ( (bu == bu_xz ) !== (ar == ar_xz) ) + begin + $display ("FAILED - incorrect 'equal to' on unsigned shortints"); + $finish; + end + if ( (bu != bu_xz ) !== (ar != ar_xz) ) + begin + $display ("FAILED - incorrect 'not equal to' on unsigned shortints"); + $finish; + end + end + # 1; + // signed small number to unsigned shorint + for (i = 0; i < (1< width) + port map (clk => clk, din => d_path(i), bin => b_path(i), reset => reset, + xin => x_path(i), lin => l_int(i), + dout => d_path(i+1), bout => b_path(i+1), + xout => x_path(i+1), lout => l_int(i+1) ); +end generate; +d_path(0) <= din; +b_path(0) <= bin; +x_path(0) <= xin; +l_int(0) <= lin; +dout <= d_path(size); +bout <= b_path(size); +xout <= x_path(size); +lout <= l_int(size); +end systolic; + +library ieee; +use ieee.std_logic_1164.all; +use work.diq_pkg.all; + +entity diq is +generic (n: integer := 8); +port (clk, reset: in std_logic; + din,bin,xin: in std_logic_vector (n-1 downto 0); + lin: in std_logic_vector (2 downto 0); + dout,bout,xout: out std_logic_vector (n-1 downto 0); + lout: out std_logic_vector (2 downto 0) ); +end diq; + +architecture diq_wordlevel of diq is + + +signal b_int, d_int, x_int, x_inv: std_logic_vector (n-1 downto 0); +signal l_int, l_inc: std_logic_vector (2 downto 0); +signal sel: std_logic; +signal zero,uno: std_logic; +begin +d_reg: process(clk,reset) +begin +if reset = '1' then + d_int <= (others => '0'); +elsif (clk'event and clk = '1') then + d_int <= din; +end if; +end process; + +l_reg: process(clk,reset) +begin +if reset = '1' then + l_int <= (others => '0'); +elsif (clk'event and clk = '1') then + l_int <= lin; +end if; +end process; + + +b_reg: process(clk,reset) +begin +if reset = '1' then + b_int <= (others => '0'); +elsif (clk'event and clk = '1') then + b_int <= bin; +end if; +end process; + +x_reg: process(clk,reset) +begin +if reset = '1' then + x_int <= (others => '0'); +elsif (clk'event and clk = '1') then + x_int <= xin; +end if; +end process; + + +zero <= '0'; +uno <= '1'; +addition: Add_Synth generic map (n => n) + port map (a => b_int, b => d_int, cin => zero, comp => open, sum => bout); +x_inv <= not x_int; +comparison: Add_Synth generic map (n => n) + port map (a => b_int, b => x_inv, cin => uno, comp => sel, sum => open); +incrementer: Inc_Synth generic map (n => 3) + port map (a => l_int, sum => l_inc); +-- outputs +lout <= l_inc when (sel = '1') else l_int; +dout <= d_int; +xout <= x_int; +end diq_wordlevel; + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity Inc_Synth is + generic (n: integer := 8); + port (a: in std_logic_vector (n-1 downto 0); + sum: out std_logic_vector (n-1 downto 0) + ); +end Inc_Synth; + +architecture compact_inc of Inc_Synth is +signal cx: std_logic_vector (n downto 0); +begin +cx <= ('0' & a) + '1'; +sum <= cx (n-1 downto 0); +end compact_inc; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity Add_Synth is + generic (n: integer := 8); + port (a, b: in std_logic_vector (n-1 downto 0); + sum: out std_logic_vector (n-1 downto 0); + cin: in std_logic; + comp: out std_logic ); +end Add_Synth; + +architecture compact of Add_Synth is +signal cx: std_logic_vector (n downto 0); +begin +cx <= ('0' & a) + ('0' & b) + cin; +sum <= cx (n-1 downto 0); +comp <= cx(n-1); +end compact; diff --git a/ivtest/ivltests/varrshft.v b/ivtest/ivltests/varrshft.v new file mode 100644 index 000000000..2f1a757db --- /dev/null +++ b/ivtest/ivltests/varrshft.v @@ -0,0 +1,128 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate variable right shift in assign + + +module main; + +reg globvar; + +reg [7:0] var1,var2,var3; +reg error; +wire [7:0] value; +assign value = var1 >> var2; + +initial + begin + error = 0; + #1 ; + var1 = 8'h80; + var2 = 8'h7; + #1; + if(value !== 8'h1) + begin + error = 1; + $display ("FAILED - 80 >> 7 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h6; + #1; + if(value !== 8'h2) + begin + error = 1; + $display ("FAILED - 80 >> 6 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h5; + #1; + if(value !== 8'h4) + begin + error = 1; + $display ("FAILED - 80 >> 5 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h4; + #1; + if(value !== 8'h8) + begin + error = 1; + $display ("FAILED - 80 >> 4 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h3; + #1; + if(value !== 8'h10) + begin + error = 1; + $display ("FAILED - 80 >> 3 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h2; + #1; + if(value !== 8'h20) + begin + error = 1; + $display ("FAILED - 80 >> 2 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h1; + #1; + if(value !== 8'h40) + begin + error = 1; + $display ("FAILED - 80 >> 1 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h0; + #1; + if(value !== 8'h80) + begin + error = 1; + $display ("FAILED - 80 >> 0 is %h",value); + end + #1 ; + var1 = 8'ha5; + var2 = 8'h7; + #1; + if(value !== 8'h01) + begin + error = 1; + $display ("FAILED - a5 >> 7 is %h",value); + end + #1 ; + var1 = 8'ha5; + var2 = 8'h1; + #1; + if(value !== 8'h52) + begin + error = 1; + $display ("FAILED - aa >> 1 is %h",value); + end + if(error === 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/varrshft1.v b/ivtest/ivltests/varrshft1.v new file mode 100644 index 000000000..d098a9621 --- /dev/null +++ b/ivtest/ivltests/varrshft1.v @@ -0,0 +1,130 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate variable right shift in always + + +module main; + +reg globvar; + +reg [7:0] var1,var2,var3; +reg error; +reg [7:0] value; + +always @(var1 or var2) + value = var1 >> var2; + +initial + begin + error = 0; + #1 ; + var1 = 8'h80; + var2 = 8'h7; + #1; + if(value !== 8'h1) + begin + error = 1; + $display ("FAILED - 80 >> 7 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h6; + #1; + if(value !== 8'h2) + begin + error = 1; + $display ("FAILED - 80 >> 6 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h5; + #1; + if(value !== 8'h4) + begin + error = 1; + $display ("FAILED - 80 >> 5 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h4; + #1; + if(value !== 8'h8) + begin + error = 1; + $display ("FAILED - 80 >> 4 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h3; + #1; + if(value !== 8'h10) + begin + error = 1; + $display ("FAILED - 80 >> 3 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h2; + #1; + if(value !== 8'h20) + begin + error = 1; + $display ("FAILED - 80 >> 2 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h1; + #1; + if(value !== 8'h40) + begin + error = 1; + $display ("FAILED - 80 >> 1 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h0; + #1; + if(value !== 8'h80) + begin + error = 1; + $display ("FAILED - 80 >> 0 is %h",value); + end + #1 ; + var1 = 8'ha5; + var2 = 8'h7; + #1; + if(value !== 8'h01) + begin + error = 1; + $display ("FAILED - a5 >> 7 is %h",value); + end + #1 ; + var1 = 8'ha5; + var2 = 8'h1; + #1; + if(value !== 8'h52) + begin + error = 1; + $display ("FAILED - aa >> 1 is %h",value); + end + if(error === 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/varrshft2.v b/ivtest/ivltests/varrshft2.v new file mode 100644 index 000000000..e540d7195 --- /dev/null +++ b/ivtest/ivltests/varrshft2.v @@ -0,0 +1,144 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate variable right shift in function + + +module main; + +reg globvar; + +reg [7:0] var1,var2,var3; +reg error; +reg [7:0] value; + +function [7:0] rshft; +input [7:0] var1,var2; +begin + rshft = var1 >> var2; +end +endfunction + +initial + begin + error = 0; + #1 ; + var1 = 8'h80; + var2 = 8'h7; + value = rshft(var1,var2); + #1; + if(value !== 8'h1) + begin + error = 1; + $display ("FAILED - 80 >> 7 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h6; + value = rshft(var1,var2); + #1; + if(value !== 8'h2) + begin + error = 1; + $display ("FAILED - 80 >> 6 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h5; + value = rshft(var1,var2); + #1; + if(value !== 8'h4) + begin + error = 1; + $display ("FAILED - 80 >> 5 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h4; + value = rshft(var1,var2); + #1; + if(value !== 8'h8) + begin + error = 1; + $display ("FAILED - 80 >> 4 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h3; + value = rshft(var1,var2); + #1; + if(value !== 8'h10) + begin + error = 1; + $display ("FAILED - 80 >> 3 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h2; + value = rshft(var1,var2); + #1; + if(value !== 8'h20) + begin + error = 1; + $display ("FAILED - 80 >> 2 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h1; + value = rshft(var1,var2); + #1; + if(value !== 8'h40) + begin + error = 1; + $display ("FAILED - 80 >> 1 is %h",value); + end + #1 ; + var1 = 8'h80; + var2 = 8'h0; + value = rshft(var1,var2); + #1; + if(value !== 8'h80) + begin + error = 1; + $display ("FAILED - 80 >> 0 is %h",value); + end + #1 ; + var1 = 8'ha5; + var2 = 8'h7; + value = rshft(var1,var2); + #1; + if(value !== 8'h01) + begin + error = 1; + $display ("FAILED - a5 >> 7 is %h",value); + end + #1 ; + var1 = 8'ha5; + var2 = 8'h1; + value = rshft(var1,var2); + #1; + if(value !== 8'h52) + begin + error = 1; + $display ("FAILED - aa >> 1 is %h",value); + end + if(error === 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/vcd-dup.v b/ivtest/ivltests/vcd-dup.v new file mode 100644 index 000000000..8e2cc44d4 --- /dev/null +++ b/ivtest/ivltests/vcd-dup.v @@ -0,0 +1,75 @@ +module test; + + reg a, b1, b2; + + submod m1 (a, b1, c1); + submod m2 (a, b2, c2); + + task set; + input [2:0] bits; + reg t1; + begin + t1 <= a; + #1 {a,b1,b2} <= bits; + end + endtask + + initial + begin + $dumpfile("work/vcd-dup.vcd"); + $dumpvars(2, test); // test, test.m1, test.m2 + $dumpvars(3, m2.c1, m1.mm1.c1); // duplicate signals + #0; // does not trip $enddefinitions + a = 0; // does not trip $enddefinitions + $dumpvars(0, m1); // (test.m1), test.m1.mm1, test.m1.mm2 + #1; // $enddefinitions called + $dumpvars(0, m2); // ignored + end + + initial + begin + #1 set(3'd 0); + #1; + #1 set(3'd 1); + #1; + #1 set(3'd 2); + #1 $dumpoff; + #1 set(3'd 3); + #1; + #1 set(3'd 4); + #1 $dumpon; + #1 set(3'd 5); + #1; + #1 set(3'd 6); + #1; + #1 set(3'd 7); + #1; + #1 set(3'd 0); + #1 $dumpall; + #1 $finish; + end + +endmodule + +module submod (a, b, c); + + input a, b; + output c; + + subsub mm1 (a&b, c1); + subsub mm2 (a|b, c2); + + assign c = c1 ^ c2; + +endmodule + +module subsub (a, c); + + input a; + output c; + + wire c1 = ~a; + + assign c = c1; + +endmodule diff --git a/ivtest/ivltests/vcd1.v b/ivtest/ivltests/vcd1.v new file mode 100644 index 000000000..324390818 --- /dev/null +++ b/ivtest/ivltests/vcd1.v @@ -0,0 +1,69 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate declared wire and implicit wires displayed. +// + + +// This circuit has 3 i/os and 3 implicit wires. Both should be +// present in vcd file?? +module xorckt (out,in0,in1); +input in0; +input in1; + +wire junk; + +nand #1 na1 (na1_out,in0,in1); +nand #1 na2 (na2_out,in0,na1_out); +nand #1 na3 (na3_out,in1,na1_out); +nand #1 na4 (out,na2_out,na3_out); + +assign junk = in0; + +endmodule + +module main; + +wire xout; +reg i1,i2; + +xorckt myckt (.out(xout),.in0(i1),.in1(i2)); + +initial + begin + $dumpfile("work/test.vcd"); + $dumpvars(0,main.myckt); + i1 = 1'b0; + i2 = 1'b0; + #5; + $display("%b xor %b = %b",i1,i2,xout); + i1 = 1'b1; + i2 = 1'b0; + #5; + $display("%b xor %b = %b",i1,i2,xout); + i1 = 1'b1; + i2 = 1'b1; + #5; + $display("%b xor %b = %b",i1,i2,xout); + i1 = 1'b0; + i2 = 1'b1; + #5 ; + $display("%b xor %b = %b",i1,i2,xout); + end + +endmodule // main diff --git a/ivtest/ivltests/vector.v b/ivtest/ivltests/vector.v new file mode 100644 index 000000000..a6af6d32b --- /dev/null +++ b/ivtest/ivltests/vector.v @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2001 Brendan J Simon + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// test case to show vector ordering bugs. + +module test; + +reg [4:0] foo40; // works great. + +reg [0:4] foo04; // only works for time=0; +//reg [4:0] foo04; + +reg [5:1] foo51; // never works. +//reg [4:0] foo51; + +reg [1:5] foo15; // never works. +//reg [4:0] foo15; + +initial begin + #102; $finish(0); +end + +initial #1 begin + foo40 = 0; + foo04 = 0; + foo51 = 0; + foo15 = 0; +end + +always #10 begin + foo40 <= foo40 + 1; + foo04 <= foo04 + 1; + foo51 <= foo51 + 1; + foo15 <= foo15 + 1; +end + +always @(foo40) begin + $write("foo40=%8d\n", foo40); +end + +always @(foo04) begin + $write(" foo04=%8d\n", foo04); +end + +always @(foo51) begin + $write(" foo51=%8d\n", foo51); +end + +always @(foo15) begin + $write(" foo15=%8d\n", foo15); +end + +endmodule diff --git a/ivtest/ivltests/verify_two_var_delays.v b/ivtest/ivltests/verify_two_var_delays.v new file mode 100644 index 000000000..1eb228c37 --- /dev/null +++ b/ivtest/ivltests/verify_two_var_delays.v @@ -0,0 +1,111 @@ +`timescale 1ns/10ps + +module top; + reg pass; + real rise, fall, delay, base, diff; + reg in, ctl; + wire out, outif0; + + buf #(rise, fall) dut(out, in); + bufif0 #(rise, fall) dutif0(outif0, in, ctl); + + // Check that the buffer output has the correct value and changed at the + // correct time. + always @(out) begin + if ((in === 1'bz && out !== 1'bx) || + (in !== 1'bz && out !== in)) begin + $display("in (%b) !== out (%b) at %.1f", in, out, $realtime); + pass = 1'b0; + end + diff = $realtime - (base + delay); + if (diff < 0.0) diff = -diff; + if (diff >= 0.01) begin + $display("Incorrect buf delay at %.1f, got %.1f, expected %.1f", + base, $realtime-base, delay); + pass = 1'b0; + end + end + + // Check that the bufif0 output has the correct value and changed at the + // correct time. + always @(outif0) begin + if (ctl) begin + if (outif0 !== 1'bz) begin + $display("outif0 (%b) !== 1'bz at %.1f", out, $realtime); + pass = 1'b0; + end + end else if ((in === 1'bz && outif0 !== 1'bx) || + (in !== 1'bz && outif0 !== in)) begin + $display("in (%b) !== outif0 (%b) at %.1f", in, outif0, $realtime); + pass = 1'b0; + end + diff = $realtime - (base + delay); + if (diff < 0.0) diff = -diff; + if (diff >= 0.01) begin + $display("Incorrect bufif0 delay at %.1f, got %.1f, expected %.1f", + base, $realtime-base, delay); + pass = 1'b0; + end + end + + function real min(input real a, input real b); + if (a < b) min = a; + else min = b; + endfunction + + initial begin +// $monitor($realtime,,out,outif0,, in,, ctl); + pass = 1'b1; + rise = 1.1; + fall = 1.2; + ctl = 1'b0; + // x -> 0 (fall) + in = 1'b0; + delay = fall; + base = $realtime; + #2; + // 0 -> 1 (rise) + in = 1'b1; + delay = rise; + base = $realtime; + #2; + // 1 -> x (min(rise, fall)) + delay = min(rise, fall); + in = 1'bz; + base = $realtime; + #2; + // x -> 1 (rise) + in = 1'b1; + delay = rise; + base = $realtime; + #2; + // 1 -> 0 (fall) + in = 1'b0; + delay = fall; + base = $realtime; + #2; + fall = 1.0; + // 0 -> x (min(rise, fall)) + in = 1'bx; + delay = min(rise, fall); + base = $realtime; + #2; + // x -> z (min(rise, fall)) + ctl = 1'b1; + delay = min(rise, fall); + base = $realtime; + #2; + // z -> x (min(rise, fall)) + ctl = 1'b0; + delay = min(rise, fall); + base = $realtime; + #2; + fall = 1.2; + // x -> z (min(rise, fall)) + ctl = 1'b1; + delay = min(rise, fall); + base = $realtime; + #2; + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/vhdl_and104_stdlogic.v b/ivtest/ivltests/vhdl_and104_stdlogic.v new file mode 100644 index 000000000..41d140e69 --- /dev/null +++ b/ivtest/ivltests/vhdl_and104_stdlogic.v @@ -0,0 +1,82 @@ +module check (input unsigned [103:0] a, b, c); + wire [103:0] int_AB; + + assign int_AB = a & b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB !== c) begin + $display("ERROR"); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [103:0] A, B); + parameter S = 2000; + int unsigned i; + + + initial begin + A = 0; B= 0; + // values with 0, 1 + for (i=0; i +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test case for handling an array of arrays + +module vhdl_array_of_array_test; +vhdl_array_of_array dut(); + +initial begin + if(dut.sig[0] !== 8'haa) + begin + $display("FAILED"); + $finish(); + end + + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/vhdl_array_of_array.vhd b/ivtest/ivltests/vhdl_array_of_array.vhd new file mode 100644 index 000000000..be87582a5 --- /dev/null +++ b/ivtest/ivltests/vhdl_array_of_array.vhd @@ -0,0 +1,35 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test case for handling an array of arrays + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vhdl_array_of_array is +end entity vhdl_array_of_array; + +architecture test of vhdl_array_of_array is + type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0); + signal sig : t_byte_array(2 downto 0); + +begin + sig <= (0 => x"aa", 1 => x"bb", 2 => x"cc"); +end architecture test; diff --git a/ivtest/ivltests/vhdl_boolean.v b/ivtest/ivltests/vhdl_boolean.v new file mode 100644 index 000000000..90a006fe5 --- /dev/null +++ b/ivtest/ivltests/vhdl_boolean.v @@ -0,0 +1,93 @@ +// Copyright (c) 2015 CERN +// @author Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// boolean values test. + +module vhdl_boolean_test; + +vhdl_boolean dut(); + +initial begin + if(dut.true_val != \true ) begin + $display("FAILED true 1"); + $finish(); + end + + if(!dut.true_val) begin + $display("FAILED true 2"); + $finish(); + end + + + if(dut.false_val != \false ) begin + $display("FAILED false 1"); + $finish(); + end + + if(dut.false_val) begin + $display("FAILED false 2"); + $finish(); + end + + + if(!dut.and1) begin + $display("FAILED and1"); + $finish(); + end + + if(dut.and2) begin + $display("FAILED and2"); + $finish(); + end + + if(dut.and3) begin + $display("FAILED and3"); + $finish(); + end + + + if(!dut.or1) begin + $display("FAILED or1"); + $finish(); + end + + if(!dut.or2) begin + $display("FAILED or2"); + $finish(); + end + + if(dut.or3) begin + $display("FAILED or3"); + $finish(); + end + + + if(!dut.not1) begin + $display("FAILED not1"); + $finish(); + end + + if(dut.not2) begin + $display("FAILED not2"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/vhdl_boolean.vhd b/ivtest/ivltests/vhdl_boolean.vhd new file mode 100644 index 000000000..dfe040ec6 --- /dev/null +++ b/ivtest/ivltests/vhdl_boolean.vhd @@ -0,0 +1,43 @@ +-- Copyright (c) 2015 CERN +-- @author Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- boolean values test. + +library ieee; + +entity vhdl_boolean is +end vhdl_boolean; + +architecture test of vhdl_boolean is + signal true_val, false_val, and1, and2, and3, or1, or2, or3, not1, not2 : boolean; +begin + true_val <= true; + false_val <= false; + + and1 <= true and true; + and2 <= true and false; + and3 <= false and false; + + or1 <= true or true; + or2 <= true or false; + or3 <= false or false; + + not1 <= not false; + not2 <= not true; +end architecture test; diff --git a/ivtest/ivltests/vhdl_case_multi.v b/ivtest/ivltests/vhdl_case_multi.v new file mode 100644 index 000000000..ce38ba041 --- /dev/null +++ b/ivtest/ivltests/vhdl_case_multi.v @@ -0,0 +1,45 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +// Test for multiple choices in case alternative statements. + +module vhdl_case_multi_test; + reg [2:0] test_vec; + reg parity; + vhdl_case_multi dut(test_vec, parity); + + initial begin + // Execute both paths + test_vec = 'b101; + #1; + if(parity !== 1'b0) begin + $display("FAILED 1"); + $finish(); + end + + test_vec = 'b001; + #1; + if(parity !== 1'b1) begin + $display("FAILED 2"); + $finish(); + end + + $display("PASSED"); + end +endmodule + diff --git a/ivtest/ivltests/vhdl_case_multi.vhd b/ivtest/ivltests/vhdl_case_multi.vhd new file mode 100644 index 000000000..b7e02da9c --- /dev/null +++ b/ivtest/ivltests/vhdl_case_multi.vhd @@ -0,0 +1,41 @@ +-- Copyright (c) 2014 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +-- Test for multiple choices in case alternative statements. + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_case_multi is + port ( inp: in std_logic_vector (0 to 2); + parity: out std_logic ); +end vhdl_case_multi; + +architecture vhdl_case_multi_rtl of vhdl_case_multi is +begin + + process (inp) + begin + case inp is + when "000"|"011"|"101"|"110" => parity <= "0"; + when "001"|"010"|"100"|"111" => parity <= "1"; + when others => parity <= "Z"; + end case; + end process; + +end vhdl_case_multi_rtl; diff --git a/ivtest/ivltests/vhdl_concat.v b/ivtest/ivltests/vhdl_concat.v new file mode 100644 index 000000000..a545094e8 --- /dev/null +++ b/ivtest/ivltests/vhdl_concat.v @@ -0,0 +1,42 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for expression concatenation in VHDL. + +module concat_test; +concat dut(); + +initial begin + #1; // wait for signal assignments + + if(dut.concat1 !== 2'b10) + begin + $display("FAILED: concat1 should be 10 but is %b", dut.concat1); + $finish(); + end + + if(dut.concat2 !== 5'b11010) + begin + $display("FAILED: concat2 should be 11010 but is %b", dut.concat2); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/vhdl_concat.vhd b/ivtest/ivltests/vhdl_concat.vhd new file mode 100644 index 000000000..26586a56f --- /dev/null +++ b/ivtest/ivltests/vhdl_concat.vhd @@ -0,0 +1,34 @@ +-- Copyright (c) 2014 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for expression concatenation in VHDL. + +library ieee; +use ieee.std_logic_1164.all; + +entity concat is +end concat; + +architecture test of concat is + signal concat1 : std_logic_vector(1 downto 0); + signal concat2 : std_logic_vector(0 to 4); +begin + concat1 <= '1' & '0'; + concat2 <= '1' & "10" & concat1; +end test; diff --git a/ivtest/ivltests/vhdl_concat_func.v b/ivtest/ivltests/vhdl_concat_func.v new file mode 100644 index 000000000..d3678e484 --- /dev/null +++ b/ivtest/ivltests/vhdl_concat_func.v @@ -0,0 +1,38 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place / Suite 330, Boston, MA 02111/1307, USA + + +// Test for concatenation of function call results. + +module test_concat_func(); + logic [7:0] in_word, out_word; + + concat_func dut(in_word, out_word); + + initial begin + in_word = 8'b11101010; + #1; + + if(out_word !== 8'b11010010) begin + $display("FAILED out_word = %b", out_word); + $finish(); + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/vhdl_concat_func.vhd b/ivtest/ivltests/vhdl_concat_func.vhd new file mode 100644 index 000000000..2b6e8f129 --- /dev/null +++ b/ivtest/ivltests/vhdl_concat_func.vhd @@ -0,0 +1,41 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for concatenation of function call results. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity concat_func is + port(in_word : in std_logic_vector(7 downto 0); + out_word : out std_logic_vector(7 downto 0)); +end entity concat_func; + +architecture test of concat_func is +begin + process(in_word) + variable tmp : unsigned(7 downto 0); + variable int : integer; + begin + tmp := unsigned(in_word); + int := to_integer(tmp); + out_word <= in_word(7 downto 6) & std_logic_vector(to_unsigned(int, 3)) & std_logic_vector(resize(tmp, 3)); + end process; +end architecture test; diff --git a/ivtest/ivltests/vhdl_concurrent_assert.v b/ivtest/ivltests/vhdl_concurrent_assert.v new file mode 100644 index 000000000..9af6bc1b0 --- /dev/null +++ b/ivtest/ivltests/vhdl_concurrent_assert.v @@ -0,0 +1,25 @@ +// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for concurrent assertion statements. + +module vhdl_concurrent_assert_test; +vhdl_concurrent_assert dut(); +// we do not need anything else here +endmodule diff --git a/ivtest/ivltests/vhdl_concurrent_assert.vhd b/ivtest/ivltests/vhdl_concurrent_assert.vhd new file mode 100644 index 000000000..5ca754c25 --- /dev/null +++ b/ivtest/ivltests/vhdl_concurrent_assert.vhd @@ -0,0 +1,37 @@ +-- Copyright (c) 2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for concurrent assertion statements. + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_concurrent_assert is +end vhdl_concurrent_assert; + +architecture test of vhdl_concurrent_assert is + signal bool_false: boolean := false; + signal bool_true: boolean := true; +begin + assert (bool_false) + report "this assert should be fired"; + + assert (bool_true) + report "this assert should not be fired"; +end test; diff --git a/ivtest/ivltests/vhdl_const_array.v b/ivtest/ivltests/vhdl_const_array.v new file mode 100644 index 000000000..f2d3a1d81 --- /dev/null +++ b/ivtest/ivltests/vhdl_const_array.v @@ -0,0 +1,72 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for constant arrays access + +module constant_array_test(); +reg [7:0] out_word; +reg [2:0] index; +constant_array dut(index, out_word); + +initial begin + index = 2; + #1; // wait for signal assignments + + if(out_word !== 16) + begin + $display("FAILED 1"); + $finish(); + end + + index = 4; + #1; + + if(out_word !== 64) + begin + $display("FAILED 2"); + $finish(); + end + + if(dut.test_a !== 32) + begin + $display("FAILED 3"); + $finish(); + end + + if(dut.test_b !== 4) + begin + $display("FAILED 4"); + $finish(); + end + + if(dut.test_c !== 3'b100) + begin + $display("FAILED 5"); + $finish(); + end + + if(dut.test_d !== 1'b1) + begin + $display("FAILED 6"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/vhdl_const_array.vhd b/ivtest/ivltests/vhdl_const_array.vhd new file mode 100644 index 000000000..9f53fa2ee --- /dev/null +++ b/ivtest/ivltests/vhdl_const_array.vhd @@ -0,0 +1,59 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for constant arrays access + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.constant_array_pkg.all; + +entity constant_array is + port (index : in std_logic_vector(2 downto 0); + output : out std_logic_vector(7 downto 0)); +end entity constant_array; + +architecture test of constant_array is + type logic_array is array (integer range <>) of std_logic_vector(0 to 3); + constant test_array : logic_array(0 to 5) := + (0 => "0010", + 1 => "1000", + 2 => "0100", + 3 => "0110", + 4 => "0101", + 5 => "1100"); + + -- Check if constant vectors are not broken with the changes + constant vector : std_logic_vector(5 downto 0) := "110011"; + + signal test_a : unsigned(7 downto 0); + signal test_b : std_logic_vector(3 downto 0); + signal test_c : std_logic_vector(2 downto 0); + signal test_d : std_logic; +begin + test_a <= const_array(3); + test_b <= test_array(2); + test_c <= vector(4 downto 2); + test_d <= vector(5); + + process (index) + begin + output <= const_array(to_integer(unsigned(index))); + end process; +end architecture test; diff --git a/ivtest/ivltests/vhdl_const_array_pkg.vhd b/ivtest/ivltests/vhdl_const_array_pkg.vhd new file mode 100644 index 000000000..36106dca3 --- /dev/null +++ b/ivtest/ivltests/vhdl_const_array_pkg.vhd @@ -0,0 +1,36 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for constant arrays access + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package constant_array_pkg is + type t_unsigned_array is array (natural range <>) of unsigned(7 downto 0); + constant const_array : t_unsigned_array(7 downto 0) := + (0 => "00000010", + 1 => "00001000", + 2 => "00010000", + 3 => "00100000", + 4 => "01000000", + 5 => "01111100", + others => "00000010"); +end package constant_array_pkg; diff --git a/ivtest/ivltests/vhdl_const_package.v b/ivtest/ivltests/vhdl_const_package.v new file mode 100644 index 000000000..fc65aeda0 --- /dev/null +++ b/ivtest/ivltests/vhdl_const_package.v @@ -0,0 +1,40 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +// Tests if constants in packages can be initialized with expressions +// that normally require elaboration to be properly emitted. + +module const_package_test; + const_package dut(); + + initial begin + if(dut.c_bitstring != 'b1001) begin + $display("FAILED 1"); + $finish; + end + + #1; // wait for signal assignment + + if(dut.c_aggregate != 'b10001000) begin + $display("FAILED 2"); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/vhdl_const_package.vhd b/ivtest/ivltests/vhdl_const_package.vhd new file mode 100644 index 000000000..ac2766c09 --- /dev/null +++ b/ivtest/ivltests/vhdl_const_package.vhd @@ -0,0 +1,35 @@ +-- Copyright (c) 2014 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Tests if constants in packages can be initialized with expressions +-- that normally require elaboration to be properly emitted. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use work.const_package_pkg.all; + +entity const_package is +end const_package; + +architecture test of const_package is + signal bitstring : std_logic_vector(3 downto 0) := c_bitstring; + signal aggregate : std_logic_vector(7 downto 0); +begin + aggregate <= c_aggregate; +end test; diff --git a/ivtest/ivltests/vhdl_const_package_pkg.vhd b/ivtest/ivltests/vhdl_const_package_pkg.vhd new file mode 100644 index 000000000..76023ca46 --- /dev/null +++ b/ivtest/ivltests/vhdl_const_package_pkg.vhd @@ -0,0 +1,32 @@ +-- Copyright (c) 2014 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Tests if constants in packages can be initialized with expressions +-- that normally require elaboration to be properly emitted. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package const_package_pkg is + constant c_bitstring : std_logic_vector(3 downto 0) := "1001"; + constant c_aggregate : std_logic_vector(7 downto 0) := (7 => '1', 3 => '1', others => '0'); +end const_package_pkg; + +package body const_package_pkg is +end const_package_pkg; diff --git a/ivtest/ivltests/vhdl_const_record.v b/ivtest/ivltests/vhdl_const_record.v new file mode 100644 index 000000000..494db7ba8 --- /dev/null +++ b/ivtest/ivltests/vhdl_const_record.v @@ -0,0 +1,70 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for accessing constant records & arrays of records in VHDL. + +module vhdl_const_record_test; +int sel; +logic [7:0] hex; +logic [7:0] aval; +vhdl_const_record dut(sel, hex, aval); + +initial begin + if(dut.sig !== 8'h66) + begin + $display("FAILED 1"); + $finish(); + end + + sel = 0; + #1; + if(hex !== 8'h14 || aval !== 8'haa || dut.sig2 !== 8'h00) + begin + $display("FAILED 2"); + $finish(); + end + + sel = 1; + #1; + if(hex !== 8'h24 || aval !== 8'hbb || dut.sig2 !== 8'h11) + begin + $display("FAILED 3"); + $finish(); + end + + sel = 2; + #1; + if(hex !== 8'h34 || aval !== 8'hcc || dut.sig2 !== 8'h22) + begin + $display("FAILED 4"); + $finish(); + end + + sel = 3; + #1; + if(hex !== 8'h56 || aval !== 8'hdd || dut.sig2 !== 8'h33) + begin + $display("FAILED 5"); + $finish(); + end + + $display("PASSED"); +end +endmodule + diff --git a/ivtest/ivltests/vhdl_const_record.vhd b/ivtest/ivltests/vhdl_const_record.vhd new file mode 100644 index 000000000..ffd980d05 --- /dev/null +++ b/ivtest/ivltests/vhdl_const_record.vhd @@ -0,0 +1,75 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for accessing constant records & arrays of records in VHDL. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vhdl_const_record is + port(sel : in integer range 0 to 3; + hex : out std_logic_vector(7 downto 0); + aval : out std_logic_vector(7 downto 0)); +end entity vhdl_const_record; + +architecture test of vhdl_const_record is + type t_var is (var_presence, var_identif, var_1, var_2, var_3, var_rst, var_4, var_5, var_whatever); + type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0); + + type t_var_record is record + var : t_var; -- 32 bits + a : t_byte_array (3 downto 0); -- 4*8 bits + hexvalue : std_logic_vector (7 downto 0); -- 8 bits + end record; -- total 72 bits + + type t_var_array is array (natural range <>) of t_var_record; + + constant c_vars_array : t_var_array(0 to 3) := ( + 0 => (var => var_presence, + hexvalue => x"14", + a => (0 => x"aa", 1 => x"ab", 2 => x"ac", 3 => x"ad")), + 1 => (var => var_identif, + hexvalue => x"24", + a => (0 => x"ba", 1 => x"bb", 2 => x"bc", 3 => x"bd")), + 2 => (var => var_1, + hexvalue => x"34", + a => (0 => x"ca", 1 => x"cb", 2 => x"cc", 3 => x"cd")), + 3 => (var => var_2, + hexvalue => x"56", + a => (0 => x"da", 1 => x"db", 2 => x"dc", 3 => x"dd")) + ); + + constant c_record : t_var_record := ( + var => var_4, + hexvalue => x"66", + a => (0 => x"00", 1 => x"11", 2 => x"22", 3 => x"33") + ); + signal sig : std_logic_vector(7 downto 0); + signal sig2 : std_logic_vector(7 downto 0); +begin + sig <= c_record.hexvalue; + + process(sel) + begin + sig2 <= c_record.a(sel); + hex <= c_vars_array(sel).hexvalue; + aval <= c_vars_array(sel).a(sel); + end process; +end architecture test; diff --git a/ivtest/ivltests/vhdl_delay_assign.v b/ivtest/ivltests/vhdl_delay_assign.v new file mode 100644 index 000000000..9b5989574 --- /dev/null +++ b/ivtest/ivltests/vhdl_delay_assign.v @@ -0,0 +1,59 @@ +// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for delayed assignment statements. + +module vhdl_delay_assign_test; +logic a, b, c; +int passed = 0; +vhdl_delay_assign dut(a, b, c); + +always @(b) +begin + if($time == 10) begin + passed = passed + 1; + end else begin + $display("FAILED 1"); + $finish(); + end +end + +always @(c) +begin + if($time == 10) begin + passed = passed + 1; + end else begin + $display("FAILED 2"); + $finish(); + end +end + +initial begin + a = 1; + #11; + + if(passed !== 2) begin + $display("FAILED 3"); + $finish(); + end + + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/vhdl_delay_assign.vhd b/ivtest/ivltests/vhdl_delay_assign.vhd new file mode 100644 index 000000000..e6c1d6482 --- /dev/null +++ b/ivtest/ivltests/vhdl_delay_assign.vhd @@ -0,0 +1,38 @@ +-- Copyright (c) 2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for delayed assignment statements. + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_delay_assign is + port(a : in std_logic; + b, c : out std_logic); +end vhdl_delay_assign; + +architecture test of vhdl_delay_assign is +begin + b <= a after 10 ns; + + process(a) + begin + c <= a after 10 ns; + end process; +end test; diff --git a/ivtest/ivltests/vhdl_elab_range.v b/ivtest/ivltests/vhdl_elab_range.v new file mode 100644 index 000000000..497bf27a2 --- /dev/null +++ b/ivtest/ivltests/vhdl_elab_range.v @@ -0,0 +1,42 @@ +// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Bug report test (could not elaborate a function used to specify a range). + +module vhdl_elab_range_test; +integer left, right; +vhdl_elab_range dut(left, right); + +initial begin + #1; + + if(left !== 2) begin + $display("FAILED 1"); + $finish(); + end + + if(right !== 0) begin + $display("FAILED 2"); + $finish(); + end + + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/vhdl_elab_range.vhd b/ivtest/ivltests/vhdl_elab_range.vhd new file mode 100644 index 000000000..d85c9b578 --- /dev/null +++ b/ivtest/ivltests/vhdl_elab_range.vhd @@ -0,0 +1,44 @@ +-- Copyright (c) 2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Bug report test (could not elaborate a function used to specify a range). + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vhdl_elab_range is + port(sig_left, sig_right : out integer); +end entity vhdl_elab_range; + +architecture test of vhdl_elab_range is + function inc_by_two(a : in integer) return integer is + begin + return a + 2; + end function inc_by_two; + + signal test_sig : unsigned(inc_by_two(0) downto 0) := (others => '0'); +begin + process + begin + sig_left <= test_sig'left; + sig_right <= test_sig'right; + wait; + end process; +end architecture test; diff --git a/ivtest/ivltests/vhdl_eval_cond.v b/ivtest/ivltests/vhdl_eval_cond.v new file mode 100644 index 000000000..dfe997a92 --- /dev/null +++ b/ivtest/ivltests/vhdl_eval_cond.v @@ -0,0 +1,35 @@ +// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place / Suite 330, Boston, MA 02111/1307, USA + + +// Test initial conditional assignment evaluation + +module vhdl_eval_cond_test; +logic in, out; +vhdl_eval_cond dut(in, out); + +assign in = 1; + +initial begin + if(out === 1'b0) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/ivltests/vhdl_eval_cond.vhd b/ivtest/ivltests/vhdl_eval_cond.vhd new file mode 100644 index 000000000..d966d9b0a --- /dev/null +++ b/ivtest/ivltests/vhdl_eval_cond.vhd @@ -0,0 +1,37 @@ +-- Copyright (c) 2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and-or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test initial conditional assignment evaluation + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_eval_cond is + port( + input : in std_logic; + output : out std_logic + ); +end vhdl_eval_cond; + +architecture rtl of vhdl_eval_cond is + +begin + output <= '1' when input = '0' else '0'; +end rtl; + diff --git a/ivtest/ivltests/vhdl_expr1.v b/ivtest/ivltests/vhdl_expr1.v new file mode 100644 index 000000000..e6b4a5cc5 --- /dev/null +++ b/ivtest/ivltests/vhdl_expr1.v @@ -0,0 +1,22 @@ +module main; + + wire [3:0] a, b; + wire [3:0] out; + + subtract dut (.a(a), .b(b), .out_sig(out)); + + reg [8:0] test_vector; + assign {a, b} = test_vector; + + initial begin + for (test_vector=0 ; test_vector[8]==0 ; test_vector=test_vector+1) begin + #1 if (out != a-b) begin + $display("FAILED -- out=%b, expecting %b-%b=%b", out, a, b, a-b); + $finish; + end + end + + $display("PASSED"); + $finish; + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/vhdl_expr1.vhd b/ivtest/ivltests/vhdl_expr1.vhd new file mode 100644 index 000000000..2b2a802ad --- /dev/null +++ b/ivtest/ivltests/vhdl_expr1.vhd @@ -0,0 +1,19 @@ +-- This VHDL was converted from Verilog using the +-- Icarus Verilog VHDL Code Generator 0.10.0 (devel) (s20090923-519-g6ce96cc) + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity subtract is + port ( + a : in unsigned(3 downto 0); + b : in unsigned(3 downto 0); + out_sig : out unsigned(3 downto 0) + ); +end entity; + +architecture test of subtract is +begin + out_sig <= (a + not b) + 1; +end architecture; diff --git a/ivtest/ivltests/vhdl_fa4_test1.v b/ivtest/ivltests/vhdl_fa4_test1.v new file mode 100644 index 000000000..89fa5a812 --- /dev/null +++ b/ivtest/ivltests/vhdl_fa4_test1.v @@ -0,0 +1,31 @@ +/* + * This module instantiates the fa4 entity, which in turn + * instantiates other entities. This demonstrates hierarchical + * constructs in VHDL. + */ +module test; + +reg [3:0] a, b; +reg cin; + +wire [3:0] s; +wire cout; + +initial begin + cin = 0; + a = 4'h2; + b = 4'h3; +end + +initial begin + #1; + if (s !== 4'h5) begin + $display("Error in trivial sum"); + $finish; + end + $display ("PASSED"); +end + +fa4 duv (.c_i(cin), .va_i(a), .vb_i(b), .vs_o(s), .c_o(cout) ); + +endmodule // test diff --git a/ivtest/ivltests/vhdl_fa4_test1.vhd b/ivtest/ivltests/vhdl_fa4_test1.vhd new file mode 100644 index 000000000..278cbbb75 --- /dev/null +++ b/ivtest/ivltests/vhdl_fa4_test1.vhd @@ -0,0 +1,80 @@ +library ieee; +use ieee.numeric_bit.all; + +-- Declare a 1-bit full-adder. +entity fa1 is + port (a_i, b_i, c_i: in bit; + s_o, c_o: out bit + ); +end entity fa1; + +architecture fa1_rtl of fa1 is +begin + + s_o <= a_i xor b_i xor c_i; + c_o <= (a_i and b_i) or (c_i and (a_i xor b_i)); + +end architecture fa1_rtl; + +-- Declare and implement a 4-bit full-adder that uses the +-- 1-bit full-adder described above. +entity fa4 is + port (va_i, vb_i: in bit_vector (3 downto 0); + c_i: in bit; + vs_o: out bit_vector (3 downto 0); + c_o: out bit + ); +end entity fa4; + +architecture fa4_rtl of fa4 is + + -- full 1-bit adder + component fa1 is + port (a_i, b_i, c_i: in bit; + s_o, c_o: out bit); + end component fa1; + + -- internal carry signals propagation + signal c_int4, c_int3, c_int2, c_int1, c_int0: bit; + + begin + + -- carry in + c_int0 <= c_i; + + -- slice 0 + s0: fa1 port map (c_i => c_int0, + a_i => va_i(0), + b_i => vb_i(0), + s_o => vs_o(0), + c_o => c_int1 + ); + + -- slice 1 + s1: fa1 port map (c_i => c_int1, + a_i => va_i(1), + b_i => vb_i(1), + s_o => vs_o(1), + c_o => c_int2 + ); + + -- slice 2 + s2: fa1 port map (c_i => c_int2, + a_i => va_i(2), + b_i => vb_i(2), + s_o => vs_o(2), + c_o => c_int3 + ); + + -- slice 3 + s3: fa1 port map (c_i => c_int3, + a_i => va_i(3), + b_i => vb_i(3), + s_o => vs_o(3), + c_o => c_int4 + ); + + -- carry out + c_o <= c_int4; + +end architecture fa4_rtl; diff --git a/ivtest/ivltests/vhdl_fa4_test2.v b/ivtest/ivltests/vhdl_fa4_test2.v new file mode 100644 index 000000000..89fa5a812 --- /dev/null +++ b/ivtest/ivltests/vhdl_fa4_test2.v @@ -0,0 +1,31 @@ +/* + * This module instantiates the fa4 entity, which in turn + * instantiates other entities. This demonstrates hierarchical + * constructs in VHDL. + */ +module test; + +reg [3:0] a, b; +reg cin; + +wire [3:0] s; +wire cout; + +initial begin + cin = 0; + a = 4'h2; + b = 4'h3; +end + +initial begin + #1; + if (s !== 4'h5) begin + $display("Error in trivial sum"); + $finish; + end + $display ("PASSED"); +end + +fa4 duv (.c_i(cin), .va_i(a), .vb_i(b), .vs_o(s), .c_o(cout) ); + +endmodule // test diff --git a/ivtest/ivltests/vhdl_fa4_test2.vhd b/ivtest/ivltests/vhdl_fa4_test2.vhd new file mode 100644 index 000000000..d9302a578 --- /dev/null +++ b/ivtest/ivltests/vhdl_fa4_test2.vhd @@ -0,0 +1,80 @@ +library ieee; +use ieee.numeric_bit.all; + +-- Declare a 1-bit full-adder. +entity fa1 is + port (a_i, b_i, c_i: in bit; + s_o, c_o: out bit + ); +end entity fa1; + +architecture fa1_rtl of fa1 is +begin + + s_o <= a_i xor b_i xor c_i; + c_o <= (a_i and b_i) or (c_i and (a_i xor b_i)); + +end architecture fa1_rtl; + +-- Declare and implement a 4-bit full-adder that uses the +-- 1-bit full-adder described above. +entity fa4 is + port (va_i, vb_i: in bit_vector (3 downto 0); + c_i: in bit; + vs_o: out bit_vector (3 downto 0); + c_o: out bit + ); +end entity fa4; + +architecture fa4_rtl of fa4 is + + -- full 1-bit adder + component fa1 is + port (a_i, b_i, c_i: in bit; + s_o, c_o: out bit); + end component fa1; + + -- internal carry signals propagation + signal c_int: bit_vector (4 downto 0); + + begin + + -- carry in + c_int(0) <= c_i; + + -- slice 0 + s0: fa1 port map (c_i => c_int(0), + a_i => va_i(0), + b_i => vb_i(0), + s_o => vs_o(0), + c_o => c_int(1) + ); + + -- slice 1 + s1: fa1 port map (c_i => c_int(1), + a_i => va_i(1), + b_i => vb_i(1), + s_o => vs_o(1), + c_o => c_int(2) + ); + + -- slice 2 + s2: fa1 port map (c_i => c_int(2), + a_i => va_i(2), + b_i => vb_i(2), + s_o => vs_o(2), + c_o => c_int(3) + ); + + -- slice 3 + s3: fa1 port map (c_i => c_int(3), + a_i => va_i(3), + b_i => vb_i(3), + s_o => vs_o(3), + c_o => c_int(4) + ); + + -- carry out + c_o <= c_int(4); + +end architecture fa4_rtl; diff --git a/ivtest/ivltests/vhdl_fa4_test3.v b/ivtest/ivltests/vhdl_fa4_test3.v new file mode 100644 index 000000000..89fa5a812 --- /dev/null +++ b/ivtest/ivltests/vhdl_fa4_test3.v @@ -0,0 +1,31 @@ +/* + * This module instantiates the fa4 entity, which in turn + * instantiates other entities. This demonstrates hierarchical + * constructs in VHDL. + */ +module test; + +reg [3:0] a, b; +reg cin; + +wire [3:0] s; +wire cout; + +initial begin + cin = 0; + a = 4'h2; + b = 4'h3; +end + +initial begin + #1; + if (s !== 4'h5) begin + $display("Error in trivial sum"); + $finish; + end + $display ("PASSED"); +end + +fa4 duv (.c_i(cin), .va_i(a), .vb_i(b), .vs_o(s), .c_o(cout) ); + +endmodule // test diff --git a/ivtest/ivltests/vhdl_fa4_test3.vhd b/ivtest/ivltests/vhdl_fa4_test3.vhd new file mode 100644 index 000000000..53676e4b3 --- /dev/null +++ b/ivtest/ivltests/vhdl_fa4_test3.vhd @@ -0,0 +1,85 @@ +-- In this test, we declare a component in the "gates" package +-- and show that it can be referenced within the package namespace. + +library ieee; +use ieee.numeric_bit.all; + +package gates is + -- full 1-bit adder + component fa1 is + port (a_i, b_i, c_i: in bit; + s_o, c_o: out bit); + end component fa1; +end package gates; + +-- Declare and implement a 4-bit full-adder that uses the +-- 1-bit full-adder described above. +entity fa4 is + port (va_i, vb_i: in bit_vector (3 downto 0); + c_i: in bit; + vs_o: out bit_vector (3 downto 0); + c_o: out bit + ); +end entity fa4; + +architecture fa4_rtl of fa4 is + + use work.gates.fa1; + + -- internal carry signals propagation + signal c_int: bit_vector (4 downto 0); + + begin + + -- carry in + c_int(0) <= c_i; + + -- slice 0 + s0: fa1 port map (c_i => c_int(0), + a_i => va_i(0), + b_i => vb_i(0), + s_o => vs_o(0), + c_o => c_int(1) + ); + + -- slice 1 + s1: fa1 port map (c_i => c_int(1), + a_i => va_i(1), + b_i => vb_i(1), + s_o => vs_o(1), + c_o => c_int(2) + ); + + -- slice 2 + s2: fa1 port map (c_i => c_int(2), + a_i => va_i(2), + b_i => vb_i(2), + s_o => vs_o(2), + c_o => c_int(3) + ); + + -- slice 3 + s3: fa1 port map (c_i => c_int(3), + a_i => va_i(3), + b_i => vb_i(3), + s_o => vs_o(3), + c_o => c_int(4) + ); + + -- carry out + c_o <= c_int(4); + +end architecture fa4_rtl; + +-- Declare a 1-bit full-adder. +entity fa1 is + port (a_i, b_i, c_i: in bit; + s_o, c_o: out bit + ); +end entity fa1; + +architecture fa1_rtl of fa1 is +begin + s_o <= a_i xor b_i xor c_i; + c_o <= (a_i and b_i) or (c_i and (a_i xor b_i)); +end architecture fa1_rtl; diff --git a/ivtest/ivltests/vhdl_fa4_test4.v b/ivtest/ivltests/vhdl_fa4_test4.v new file mode 100644 index 000000000..89fa5a812 --- /dev/null +++ b/ivtest/ivltests/vhdl_fa4_test4.v @@ -0,0 +1,31 @@ +/* + * This module instantiates the fa4 entity, which in turn + * instantiates other entities. This demonstrates hierarchical + * constructs in VHDL. + */ +module test; + +reg [3:0] a, b; +reg cin; + +wire [3:0] s; +wire cout; + +initial begin + cin = 0; + a = 4'h2; + b = 4'h3; +end + +initial begin + #1; + if (s !== 4'h5) begin + $display("Error in trivial sum"); + $finish; + end + $display ("PASSED"); +end + +fa4 duv (.c_i(cin), .va_i(a), .vb_i(b), .vs_o(s), .c_o(cout) ); + +endmodule // test diff --git a/ivtest/ivltests/vhdl_fa4_test4.vhd b/ivtest/ivltests/vhdl_fa4_test4.vhd new file mode 100644 index 000000000..3c85a28b5 --- /dev/null +++ b/ivtest/ivltests/vhdl_fa4_test4.vhd @@ -0,0 +1,102 @@ +-- In this test, we declare a component in the "mypackage" package +-- and show that it can be referenced within the package namespace. +-- it also shows the usage of subtypes, constants and signals +-- expressed in terms of defined subtypes + +library ieee; +use ieee.numeric_bit.all; + +package mypackage is + + -- trivial sub type + subtype Myrange_t is integer range 0 to 4; + + -- some constants + constant ZERO: Myrange_t := 0; + constant ONE: Myrange_t := 1; + constant TWO: Myrange_t := 2; + constant THREE: Myrange_t := 3; + constant FOUR: Myrange_t := 4; + + -- another subtype + subtype AdderWidth_t is bit_vector (THREE downto ZERO); + subtype CarryWidth_t is bit_vector (THREE+1 downto ZERO); + + -- full 1-bit adder + component fa1 is + port (a_i, b_i, c_i: in bit; + s_o, c_o: out bit); + end component fa1; +end package mypackage; + +-- Declare and implement a 4-bit full-adder that uses the +-- 1-bit full-adder described above. + +use work.mypackage.all; +entity fa4 is + port (va_i, vb_i: in AdderWidth_t; + c_i: in bit; + vs_o: out AdderWidth_t; + c_o: out bit + ); +end entity fa4; + +architecture fa4_rtl of fa4 is + +-- auxiliary signal for carry +signal c_int: CarryWidth_t; + +begin + + -- carry in + c_int(ZERO) <= c_i; + + -- slice 0 + s0: fa1 port map (c_i => c_int(ZERO), + a_i => va_i(ZERO), + b_i => vb_i(ZERO), + s_o => vs_o(ZERO), + c_o => c_int(ONE) + ); + + -- slice 1 + s1: fa1 port map (c_i => c_int(ONE), + a_i => va_i(ONE), + b_i => vb_i(ONE), + s_o => vs_o(ONE), + c_o => c_int(TWO) + ); + + -- slice 2 + s2: fa1 port map (c_i => c_int(TWO), + a_i => va_i(TWO), + b_i => vb_i(TWO), + s_o => vs_o(TWO), + c_o => c_int(THREE) + ); + + -- slice 3 + s3: fa1 port map (c_i => c_int(THREE), + a_i => va_i(THREE), + b_i => vb_i(THREE), + s_o => vs_o(THREE), + c_o => c_int(FOUR) + ); + + -- carry out + c_o <= c_int(FOUR); + +end architecture fa4_rtl; + +-- Declare a 1-bit full-adder. +entity fa1 is + port (a_i, b_i, c_i: in bit; + s_o, c_o: out bit + ); +end entity fa1; + +architecture fa1_rtl of fa1 is +begin + s_o <= a_i xor b_i xor c_i; + c_o <= (a_i and b_i) or (c_i and (a_i xor b_i)); +end architecture fa1_rtl; diff --git a/ivtest/ivltests/vhdl_file_open.v b/ivtest/ivltests/vhdl_file_open.v new file mode 100644 index 000000000..f95a1057f --- /dev/null +++ b/ivtest/ivltests/vhdl_file_open.v @@ -0,0 +1,36 @@ +// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test file_open() function. + +module file_open_test; +logic active, ok; +vhdl_file_open dut(active, ok); + +initial begin + active = 1; + #1; + if(ok !== 1'b1) begin + $display("FAILED"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/vhdl_file_open.vhd b/ivtest/ivltests/vhdl_file_open.vhd new file mode 100644 index 000000000..1c33ddd47 --- /dev/null +++ b/ivtest/ivltests/vhdl_file_open.vhd @@ -0,0 +1,50 @@ +-- Copyright (c) 2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test file_open() function. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +entity vhdl_file_open is + port(active : in std_logic; + ok : out std_logic); +end vhdl_file_open; + +architecture test of vhdl_file_open is +begin + process(active) + file ok_file, bad_file : text; + variable ok_status, bad_status : FILE_OPEN_STATUS; + begin + if rising_edge(active) then + file_open(ok_status, ok_file, "ivltests/vhdl_file_open.vhd", read_mode); + file_open(bad_status, bad_file, "not_existing_file", read_mode); + + if ok_status = OPEN_OK and bad_status = NAME_ERROR then + ok := '1'; + else + ok := '0'; + end if; + file_close(ok_file); + end if; + end process; +end test; diff --git a/ivtest/ivltests/vhdl_generic_default.v b/ivtest/ivltests/vhdl_generic_default.v new file mode 100644 index 000000000..26be5b00c --- /dev/null +++ b/ivtest/ivltests/vhdl_generic_default.v @@ -0,0 +1,33 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for generics without a default value. + +module vhdl_generic_default_test; +logic a; +vhdl_generic_default #(.\value (1'b1))dut(a); + +initial begin + if(a !== 1'b1) begin + $display("FAILED"); + $finish(); + end + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/vhdl_generic_default.vhd b/ivtest/ivltests/vhdl_generic_default.vhd new file mode 100644 index 000000000..d939ba104 --- /dev/null +++ b/ivtest/ivltests/vhdl_generic_default.vhd @@ -0,0 +1,33 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for generics without a default value. + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_generic_default is + generic(value : std_logic); + port(a : out std_logic); +end vhdl_generic_default; + +architecture test of vhdl_generic_default is +begin + a <= value; +end test; diff --git a/ivtest/ivltests/vhdl_generic_eval.v b/ivtest/ivltests/vhdl_generic_eval.v new file mode 100644 index 000000000..b76224bd0 --- /dev/null +++ b/ivtest/ivltests/vhdl_generic_eval.v @@ -0,0 +1,38 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for generics evaluation. + +module generic_eval(); +reg [7:0] data; +reg out_bit_def, out_bit_ovr; +test_eval_generic dut(data, out_bit_def, out_bit_ovr); + +initial begin + data = 8'b11010010; + #1; + + if(out_bit_def !== 1'b0 || out_bit_ovr !== 1'b1) begin + $display("FAILED"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/vhdl_generic_eval.vhd b/ivtest/ivltests/vhdl_generic_eval.vhd new file mode 100644 index 000000000..95e66d0f8 --- /dev/null +++ b/ivtest/ivltests/vhdl_generic_eval.vhd @@ -0,0 +1,79 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for generics evaluation. + +library ieee; +use ieee.std_logic_1164.all; + +entity eval_generic is + generic( + msb : integer range 1 to 7 := 7; + bit_select : integer range 0 to 7 := 3 + ); + port( + in_word : in std_logic_vector(msb downto 0); + out_bit : out std_logic + ); +end entity eval_generic; + +architecture test of eval_generic is +begin + out_bit <= in_word(bit_select); +end architecture test; + + +library ieee; +use ieee.std_logic_1164.all; + +entity test_eval_generic is + port( + in_word : in std_logic_vector(7 downto 0); + out_bit_def, out_bit_ovr : out std_logic + ); +end entity test_eval_generic; + +architecture test of test_eval_generic is + constant const_int : integer := 7; + + component eval_generic is + generic( + msb : integer range 1 to 7; + bit_select : integer range 0 to 7 + ); + port( + in_word : in std_logic_vector(msb downto 0); + out_bit : out std_logic + ); + end component eval_generic; +begin + override_test_unit: eval_generic + generic map(bit_select => 2, + msb => const_int) + port map( + in_word => (others => '1'), + out_bit => out_bit_ovr + ); + + default_test_unit: eval_generic + port map( + in_word => in_word, + out_bit => out_bit_def + ); +end architecture test; diff --git a/ivtest/ivltests/vhdl_image_attr.v b/ivtest/ivltests/vhdl_image_attr.v new file mode 100644 index 000000000..3f5c6aa4c --- /dev/null +++ b/ivtest/ivltests/vhdl_image_attr.v @@ -0,0 +1,30 @@ +// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for 'image attribute in VHDL. + +module image_attr_test; +logic start_test; +image_attr_entity dut(start_test); + +initial begin + start_test = 1'b0; + #1 start_test = 1'b1; +end +endmodule diff --git a/ivtest/ivltests/vhdl_image_attr.vhd b/ivtest/ivltests/vhdl_image_attr.vhd new file mode 100644 index 000000000..c86c15233 --- /dev/null +++ b/ivtest/ivltests/vhdl_image_attr.vhd @@ -0,0 +1,44 @@ +-- Copyright (c) 2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for 'image attribute in VHDL. + +library ieee; +use ieee.std_logic_1164.all; + +entity image_attr_entity is + port (start_test : in std_logic); +end image_attr_entity; + +architecture test of image_attr_entity is +begin + process(start_test) + variable var_int : integer := 10; + variable var_real : real := 12.34; + variable var_char : character := 'o'; + variable var_time : time := 10 ns; + begin + if(start_test = '1') then + report "integer'image test: " & integer'image(var_int); + report "real'image test: " & real'image(var_real); + report "character'image test: " & character'image(var_char); + report "time'image test: " & time'image(var_time); + end if; + end process; +end test; diff --git a/ivtest/ivltests/vhdl_init.v b/ivtest/ivltests/vhdl_init.v new file mode 100644 index 000000000..3a659ec7d --- /dev/null +++ b/ivtest/ivltests/vhdl_init.v @@ -0,0 +1,44 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Tests signal initializers. + +module vhdl_init_testbench; + vhdl_init dut(); + + initial begin + // Simply check if the assigned values are correct + if (dut.a !== 'b11101001) begin + $display("FAILED #1: expected 11101001, got %b", dut.a); + $finish; + end + + if (dut.b !== 'b1010) begin + $display("FAILED #2: expected 1010, got %b", dut.b); + $finish; + end + + if (dut.c !== 'b1000) begin + $display("FAILED #3: expected 1000, got %b", dut.c); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/vhdl_init.vhd b/ivtest/ivltests/vhdl_init.vhd new file mode 100644 index 000000000..fd22d02d3 --- /dev/null +++ b/ivtest/ivltests/vhdl_init.vhd @@ -0,0 +1,39 @@ +-- Copyright (c) 2014 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Tests signal initializers. + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_init is +end; + +architecture test of vhdl_init is + -- Convert string to bitstring in initalizer + signal a : std_logic_vector(7 downto 0) := "11101001"; + -- Initialize with aggregate expression + signal b : std_logic_vector(3 downto 0) := (0 => '0', 3 => '1', 1 => '1', 2 => '0'); + -- Initialize with aggregate expression, inverted range + signal c : std_logic_vector(0 to 3) := (3 => '1', others => '0'); +begin + -- Architecture statement part cannot be empty + -- Assign the previous value, otherwise you will get unknown value + a <= "11101001"; +end test; diff --git a/ivtest/ivltests/vhdl_inout.v b/ivtest/ivltests/vhdl_inout.v new file mode 100644 index 000000000..3ce0dce66 --- /dev/null +++ b/ivtest/ivltests/vhdl_inout.v @@ -0,0 +1,43 @@ +// Copyright (c) 2015 CERN +// @author Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for port inout mode. + +module vhdl_inout_test; +logic a, b, c; +vhdl_inout dut(a, b, c); + +initial begin + b <= 1'b0; + #1; + if(a !== 1'b1 || c !== 1'b0) begin + $display("FAILED 1"); + $finish(); + end + + b <= 1'b1; + #1; + if(a !== 1'b0 || c !== 1'b1) begin + $display("FAILED 2"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/vhdl_inout.vhd b/ivtest/ivltests/vhdl_inout.vhd new file mode 100644 index 000000000..f331864c0 --- /dev/null +++ b/ivtest/ivltests/vhdl_inout.vhd @@ -0,0 +1,44 @@ +-- Copyright (c) 2015 CERN +-- @author Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for port inout mode. + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_inout is + port(a : inout std_logic; + b : in std_logic; + c : out std_logic); +end vhdl_inout; + +architecture test of vhdl_inout is +begin + a <= not b; + + process(a) + begin + -- c indirectly follows b + if(a = '1') then + c <= '0'; + else + c <= '1'; + end if; + end process; +end architecture test; diff --git a/ivtest/ivltests/vhdl_labeled_assign.v b/ivtest/ivltests/vhdl_labeled_assign.v new file mode 100644 index 000000000..23524e25a --- /dev/null +++ b/ivtest/ivltests/vhdl_labeled_assign.v @@ -0,0 +1,44 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for labeled assignment statements + +module labeled_assign_test; +reg [7:0] in, out; +labeled_assign dut(in, out); + +initial begin + in = 8'hdd; + #1; + + if(out !== 8'h11) + begin + $display("FAILED 1"); + $finish(); + end + + if(dut.test_rx !== 8'haa) + begin + $display("FAILED 2"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/vhdl_labeled_assign.vhd b/ivtest/ivltests/vhdl_labeled_assign.vhd new file mode 100644 index 000000000..9eb4cfba3 --- /dev/null +++ b/ivtest/ivltests/vhdl_labeled_assign.vhd @@ -0,0 +1,42 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for labeled assignment statements + +library ieee; +use ieee.std_logic_1164.all; + +entity labeled_assign is + port (input : in std_logic_vector(7 downto 0); + output : out std_Logic_vector(7 downto 0)); +end entity; + +architecture test of labeled_assign is + signal test_rx : std_logic_vector (7 downto 0); +begin + first_label: test_rx <= x"aa"; + + process(input) + variable tmp : std_logic_vector(7 downto 0); + begin + second_label: tmp := input; + third_label: output <= tmp xor x"cc"; + end process; + +end architecture; diff --git a/ivtest/ivltests/vhdl_lfcr.v b/ivtest/ivltests/vhdl_lfcr.v new file mode 100644 index 000000000..49abe70c4 --- /dev/null +++ b/ivtest/ivltests/vhdl_lfcr.v @@ -0,0 +1,25 @@ +// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test special character enums (LF, CR). + +module vhdl_lfcr_test; +vhdl_lfcr dut(); +// we do not need anything more +endmodule diff --git a/ivtest/ivltests/vhdl_lfcr.vhd b/ivtest/ivltests/vhdl_lfcr.vhd new file mode 100644 index 000000000..d4afc7083 --- /dev/null +++ b/ivtest/ivltests/vhdl_lfcr.vhd @@ -0,0 +1,35 @@ +-- Copyright (c) 2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test special character enums (LF, CR). + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_lfcr is +end vhdl_lfcr; + +architecture test of vhdl_lfcr is +begin + process + begin + report "first line" & LF & "after LF" & CR & "after CR"; + wait; + end process; +end test; diff --git a/ivtest/ivltests/vhdl_logic.v b/ivtest/ivltests/vhdl_logic.v new file mode 100644 index 000000000..a7b6c508a --- /dev/null +++ b/ivtest/ivltests/vhdl_logic.v @@ -0,0 +1,60 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// std_logic values test. + +module vhdl_logic_test; + +logic low, high, hiz, dontcare, uninitialized, unknown; +vhdl_logic dut(low, high, hiz, dontcare, uninitialized, unknown); + +initial begin + if(low !== 1'b0) begin + $display("FAILED low"); + $finish(); + end + + if(high !== 1'b1) begin + $display("FAILED high"); + $finish(); + end + + if(hiz !== 1'bz) begin + $display("FAILED hiz"); + $finish(); + end + + if(dontcare !== 1'bx) begin + $display("FAILED dontcare"); + $finish(); + end + + if(uninitialized !== 1'bx) begin + $display("FAILED uninitialized"); + $finish(); + end + + if(unknown !== 1'bx) begin + $display("FAILED unknown"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/vhdl_logic.vhd b/ivtest/ivltests/vhdl_logic.vhd new file mode 100644 index 000000000..aebae416e --- /dev/null +++ b/ivtest/ivltests/vhdl_logic.vhd @@ -0,0 +1,36 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- std_logic values test. + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_logic is + port (low, high, hiz, dontcare, uninitialized, unknown : out std_logic); +end vhdl_logic; + +architecture test of vhdl_logic is begin + low <= '0'; + high <= '1'; + hiz <= 'Z'; + dontcare <= '-'; + uninitialized <= 'U'; + unknown <= 'X'; +end architecture test; diff --git a/ivtest/ivltests/vhdl_loop.v b/ivtest/ivltests/vhdl_loop.v new file mode 100644 index 000000000..d4686da06 --- /dev/null +++ b/ivtest/ivltests/vhdl_loop.v @@ -0,0 +1,40 @@ +// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for basic loops in VHDL. + +module vhdl_loop_test; +logic start; +int counter; +vhdl_loop dut(start, counter); + +initial begin + for(int i = 0; i < 5; ++i) begin + if(counter !== i) begin + $display("FAILED"); + $finish(); + end + + #10; + end + + $display("PASSED"); + $finish(); +end +endmodule diff --git a/ivtest/ivltests/vhdl_loop.vhd b/ivtest/ivltests/vhdl_loop.vhd new file mode 100644 index 000000000..d093e2559 --- /dev/null +++ b/ivtest/ivltests/vhdl_loop.vhd @@ -0,0 +1,41 @@ +-- Copyright (c) 2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for basic loops in VHDL. + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_loop is + port(start : in std_logic; + counter : out integer); +end vhdl_loop; + +architecture test of vhdl_loop is +begin + process(start) + variable cnt : integer := 0; + begin + loop + cnt := cnt + 1; + counter <= cnt; + wait for 10 s; + end loop; + end process; +end test; diff --git a/ivtest/ivltests/vhdl_multidim_array.v b/ivtest/ivltests/vhdl_multidim_array.v new file mode 100644 index 000000000..180909283 --- /dev/null +++ b/ivtest/ivltests/vhdl_multidim_array.v @@ -0,0 +1,42 @@ +// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test multidimensional arrays. + +module vhdl_multidim_array_test; +vhdl_multidim_array dut(); + +initial begin + int i, j; + + for(i = 0; i <= 1; i = i + 1) begin + for(j = dut.array_size - 1; j >= 0; j = j - 1) begin + $display("%d", dut.arr[i][j]); + //$display("%d, %d = %d", i, j, arr[i][j]); + //if(dut.arr[i][j] !== i * 10 + j) begin + //$display("FAILED: arr[%d][%d] == %d, instead of %d", i, j, dut.arr[i][j], i * 10 + j); + //$finish(); + //end + end + end + + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/vhdl_multidim_array.vhd b/ivtest/ivltests/vhdl_multidim_array.vhd new file mode 100644 index 000000000..4de336d8e --- /dev/null +++ b/ivtest/ivltests/vhdl_multidim_array.vhd @@ -0,0 +1,46 @@ +-- Copyright (c) 2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test multidimensional arrays. + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity vhdl_multidim_array is +end vhdl_multidim_array; + +architecture archi of vhdl_multidim_array is + constant array_size : integer := 16; + subtype one_dim is unsigned(array_size - 1 downto 0); + type multi_dim is array (0 to 1) of one_dim; + +begin + process + variable arr : multi_dim; + begin + -- fill the array with test data + for i in array_size - 1 downto 0 + loop + arr(0)(i) := 2 ** i; + arr(1)(i) := not arr(0)(i); + end loop; + wait; + end process; +end archi; diff --git a/ivtest/ivltests/vhdl_nand104_stdlogic.v b/ivtest/ivltests/vhdl_nand104_stdlogic.v new file mode 100644 index 000000000..9957edd3d --- /dev/null +++ b/ivtest/ivltests/vhdl_nand104_stdlogic.v @@ -0,0 +1,82 @@ +module check (input unsigned [103:0] a, b, c); + wire [103:0] int_AB; + + assign int_AB = ~(a & b); + +always @(a, b, int_AB, c) begin + #1; + if (int_AB !== c) begin + $display("ERROR"); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [103:0] A, B); + parameter S = 2000; + int unsigned i; + + + initial begin + A = 0; B= 0; + // values with 0, 1 + for (i=0; i +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for NOW() system function. + +module now_test; +logic gen_report; +now_entity dut(gen_report); + +initial begin + gen_report = 0; + #5; + gen_report = 1; + #5; + gen_report = 0; + #5; + gen_report = 1; + #5; + gen_report = 0; + #5; + gen_report = 1; +end +endmodule diff --git a/ivtest/ivltests/vhdl_now.vhd b/ivtest/ivltests/vhdl_now.vhd new file mode 100644 index 000000000..6a2ed6b21 --- /dev/null +++ b/ivtest/ivltests/vhdl_now.vhd @@ -0,0 +1,37 @@ +-- Copyright (c) 2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for NOW() system function. + +library ieee; +use ieee.std_logic_1164.all; + +entity now_entity is + port (report_time : in std_logic); +end now_entity; + +architecture test of now_entity is +begin + process(report_time) + begin + if(rising_edge(report_time)) then + report "reporting sim time: " & integer'image(now); + end if; + end process; +end architecture test; diff --git a/ivtest/ivltests/vhdl_or104_stdlogic.v b/ivtest/ivltests/vhdl_or104_stdlogic.v new file mode 100644 index 000000000..b9a374512 --- /dev/null +++ b/ivtest/ivltests/vhdl_or104_stdlogic.v @@ -0,0 +1,82 @@ +module check (input unsigned [103:0] a, b, c); + wire [103:0] int_AB; + + assign int_AB = a | b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB !== c) begin + $display("ERROR"); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [103:0] A, B); + parameter S = 2000; + int unsigned i; + + + initial begin + A = 0; B= 0; + // values with 0, 1 + for (i=0; i +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Power and division remainder operators test + +module vhdl_pow_rem_test; +integer a, b, pow_res, rem_res; +vhdl_pow_rem dut(a, b, pow_res, rem_res); + +initial begin + a = 5; + b = 2; + + if(pow_res != 25 || rem_res != 1) begin + $display("FAILED 1"); + $finish(); + end + + a = -5; + b = 3; + + if(rem_res != -2 || pow_res != -125) begin + $display("FAILED 2"); + $finish(); + end + + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/vhdl_pow_rem.vhd b/ivtest/ivltests/vhdl_pow_rem.vhd new file mode 100644 index 000000000..4b2520db4 --- /dev/null +++ b/ivtest/ivltests/vhdl_pow_rem.vhd @@ -0,0 +1,37 @@ +-- Copyright (c) 2016 CERN +-- @author Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Power and division remainder operators test + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_pow_rem is + port( + a, b : in integer; + pow_res, rem_res : out integer + ); +end vhdl_pow_rem; + +architecture rtl of vhdl_pow_rem is +begin + pow_res <= a ** b; + rem_res <= a rem b; +end rtl; + diff --git a/ivtest/ivltests/vhdl_prefix_array.v b/ivtest/ivltests/vhdl_prefix_array.v new file mode 100644 index 000000000..2aeddf10f --- /dev/null +++ b/ivtest/ivltests/vhdl_prefix_array.v @@ -0,0 +1,39 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place / Suite 330, Boston, MA 02111/1307, USA + + +// Example to test prefix for VTypeArray (and using function as index). + +module test_prefix_aray(); + logic [1:0] sel_word; + logic [31:0] out_word; + + prefix_array dut(sel_word, out_word); + + initial begin + sel_word = 2; + #1; + + if(out_word !== 32'd5) begin + $display("FAILED out_word = %d", out_word); + $finish(); + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/vhdl_prefix_array.vhd b/ivtest/ivltests/vhdl_prefix_array.vhd new file mode 100644 index 000000000..8ff36e50a --- /dev/null +++ b/ivtest/ivltests/vhdl_prefix_array.vhd @@ -0,0 +1,50 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Example to test prefix for VTypeArray (and using function as index). + +library ieee; +use ieee.std_logic_1164.all; + +entity prefix_array is + port(sel_word : in std_logic_vector(1 downto 0); + out_word : out integer); +end entity prefix_array; + +architecture test of prefix_array is + type t_timeouts is + record + a : integer; + b : integer; + end record; + + type t_timeouts_table is array (natural range <>) of t_timeouts; + + constant c_TIMEOUTS_TABLE : t_timeouts_table(3 downto 0) := + (0 => (a => 1, b => 2), + 1 => (a => 3, b => 4), + 2 => (a => 5, b => 6), + 3 => (a => 7, b => 8)); + +begin + process(sel_word) + begin + out_word <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(sel_word))).a), 32); + end process; +end architecture test; diff --git a/ivtest/ivltests/vhdl_procedure.v b/ivtest/ivltests/vhdl_procedure.v new file mode 100644 index 000000000..e8e6a97f6 --- /dev/null +++ b/ivtest/ivltests/vhdl_procedure.v @@ -0,0 +1,30 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for VHDL procedure calls + +module vhdl_procedure_test; +logic run; +vhdl_procedure dut(run); + +initial begin + run = 0; + #1 run = 1; +end +endmodule diff --git a/ivtest/ivltests/vhdl_procedure.vhd b/ivtest/ivltests/vhdl_procedure.vhd new file mode 100644 index 000000000..9d18b25c8 --- /dev/null +++ b/ivtest/ivltests/vhdl_procedure.vhd @@ -0,0 +1,46 @@ +-- Copyright (c) 2014 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for VHDL procedure calls. + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_procedure is + port(run : in std_logic); +end entity vhdl_procedure; + +architecture test of vhdl_procedure is + +procedure proc(word_i : std_logic_vector(3 downto 0)) is +begin + report "Procedure executed"; +end procedure; + +begin + process(run) begin + report "before rising_edge"; + + if rising_edge(run) then + proc("0000"); + end if; + + report "after rising_edge"; + end process; +end test; diff --git a/ivtest/ivltests/vhdl_process_scope.v b/ivtest/ivltests/vhdl_process_scope.v new file mode 100644 index 000000000..476a561e7 --- /dev/null +++ b/ivtest/ivltests/vhdl_process_scope.v @@ -0,0 +1,32 @@ +// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test a case when two variables with the same name are used in two +// different processes. + +module vhdl_process_scope_test; +vhdl_process_scope dut(); + +initial begin + #0; + // the test takes place in the dut processes + $display("PASSED"); +end +endmodule + diff --git a/ivtest/ivltests/vhdl_process_scope.vhd b/ivtest/ivltests/vhdl_process_scope.vhd new file mode 100644 index 000000000..74d4e74a6 --- /dev/null +++ b/ivtest/ivltests/vhdl_process_scope.vhd @@ -0,0 +1,44 @@ +-- Copyright (c) 2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test a case when two variables with the same name are used in two +-- different processes. + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_process_scope is +end vhdl_process_scope; + +architecture test of vhdl_process_scope is +begin + process + variable var : integer := 1; + begin + assert var = 1; + wait; + end process; + + process + variable var : integer := 2; + begin + assert var = 2; + wait; + end process; +end architecture test; diff --git a/ivtest/ivltests/vhdl_rand23_bit.v b/ivtest/ivltests/vhdl_rand23_bit.v new file mode 100644 index 000000000..a6c9f905b --- /dev/null +++ b/ivtest/ivltests/vhdl_rand23_bit.v @@ -0,0 +1,47 @@ +module check (input unsigned [0:22] a, b, c); + wire [0:22] int_AB; + + assign int_AB = a & b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB != c) begin + $display("ERROR"); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [0:22] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 0; + for (i=0; i +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for 'range, 'reverse_range, 'left and 'right attributes in VHDL. + +module range_test; +range_entity dut(); + +initial begin + int i; + #1; // wait for signal assignments + + if(dut.left_asc !== 2) + begin + $display("FAILED: left_asc should be %2d but is %2d", 2, dut.left_asc); + $finish(); + end + + if(dut.right_asc !== 4) + begin + $display("FAILED: right_asc should be %2d but is %2d", 2, dut.right_asc); + $finish(); + end + + if(dut.left_dsc !== 9) + begin + $display("FAILED: left_dsc should be %2d but is %2d", 2, dut.left_dsc); + $finish(); + end + + if(dut.right_dsc !== 3) + begin + $display("FAILED: right_dsc should be %2d but is %2d", 2, dut.right_dsc); + $finish(); + end + + if(dut.pow_left !== 16) + begin + $display("FAILED: pow_left should be %2d but is %2d", 16, dut.pow_left); + $finish(); + end + + if(dut.rem_left !== 2) + begin + $display("FAILED: rem_left should be %2d but is %2d", 2, dut.rem_left); + $finish(); + end + + for(i = $left(dut.ascending); i <= $right(dut.ascending); i++) + begin + if(2*i !== dut.ascending[i]) + begin + $display("FAILED: ascending[%2d] should be %2d but is %2d", i, 2*i, dut.ascending[i]); + $finish(); + end + end + + for(i = $right(dut.descending); i <= $left(dut.descending); i++) + begin + if(3*i !== dut.descending[i]) + begin + $display("FAILED: descending[%2d] should be %2d but is %2d", i, 3*i, dut.descending[i]); + $finish(); + end + end + + for(i = $left(dut.ascending_rev); i <= $right(dut.ascending_rev); i++) + begin + if(4*i !== dut.ascending_rev[i]) + begin + $display("FAILED: ascending_rev[%2d] should be %2d but is %2d", i, 4*i, dut.ascending_rev[i]); + $finish(); + end + end + + for(i = $right(dut.descending_rev); i <= $left(dut.descending_rev); i++) + begin + if(5*i !== dut.descending_rev[i]) + begin + $display("FAILED: descending_rev[%2d] should be %2d but is %2d", i, 5*i, dut.descending_rev[i]); + $finish(); + end + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/vhdl_range.vhd b/ivtest/ivltests/vhdl_range.vhd new file mode 100644 index 000000000..55474d182 --- /dev/null +++ b/ivtest/ivltests/vhdl_range.vhd @@ -0,0 +1,71 @@ +-- Copyright (c) 2014 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for 'range, 'reverse_range, 'left and 'right attributes in VHDL. + +library ieee; +use ieee.std_logic_1164.all; +use work.vhdl_range_pkg.all; + +entity range_entity is + port (gen_vals: in std_logic); +end range_entity; + +architecture test of range_entity is + type int_array is array (integer range <>) of integer; + + signal ascending : int_array(2 to 4); + signal descending : int_array(9 downto 3); + signal ascending_rev : int_array(8 to 13); + signal descending_rev : int_array(15 downto 10); + signal range_pow : int_array(2**4 downto 0); + signal range_rem : int_array(8 rem 3 downto 0); + signal left_asc, right_asc, left_dsc, right_dsc, pow_left, rem_left : integer; + + -- There is no limited ranged integer in SystemVerilog, so just see if it compiles + signal int_asc : integer_asc; + signal int_desc : integer_desc; +begin + process(gen_vals) begin + left_asc <= ascending'left; + right_asc <= ascending'right; + left_dsc <= descending'left; + right_dsc <= descending'right; + pow_left <= range_pow'left; + rem_left <= range_rem'left; + + -- 'range test + for i in ascending'range loop + ascending(i) <= i * 2; + end loop; + + for i in descending'range loop + descending(i) <= i * 3; + end loop; + + -- 'reverse_range test + for i in ascending_rev'reverse_range loop + ascending_rev(i) <= i * 4; + end loop; + + for i in descending_rev'reverse_range loop + descending_rev(i) <= i * 5; + end loop; + end process; +end test; diff --git a/ivtest/ivltests/vhdl_range_func.v b/ivtest/ivltests/vhdl_range_func.v new file mode 100644 index 000000000..546d4fa78 --- /dev/null +++ b/ivtest/ivltests/vhdl_range_func.v @@ -0,0 +1,43 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for 'range, 'left and 'right attributes in VHDL subprograms. + +module range_func_test; + +range_func dut(); + +initial begin + #1; + + if(dut.neg_out !== 4'b0011) + begin + $display("FAILED 1"); + $finish(); + end + + if(dut.rev_out !== 4'b0001) + begin + $display("FAILED 2"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/vhdl_range_func.vhd b/ivtest/ivltests/vhdl_range_func.vhd new file mode 100644 index 000000000..77bab72be --- /dev/null +++ b/ivtest/ivltests/vhdl_range_func.vhd @@ -0,0 +1,49 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for 'range, 'left and 'right attributes in VHDL subprograms. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.range_func_pkg.all; + +entity range_func is +end range_func; + +architecture test of range_func is + signal neg_inp : std_logic_vector(3 downto 0); + signal neg_out : std_logic_vector(3 downto 0); + signal rev_inp : std_logic_vector(3 downto 0); + signal rev_out : std_logic_vector(3 downto 0); +begin + neg_inp <= "1100"; + rev_inp <= "1000"; + + process(neg_inp) + begin + neg_out <= negator(neg_inp); + end process; + + process(rev_inp) + begin + rev_out <= reverse(rev_inp); + end process; +end test; + diff --git a/ivtest/ivltests/vhdl_range_func_pkg.vhd b/ivtest/ivltests/vhdl_range_func_pkg.vhd new file mode 100644 index 000000000..2bba4baba --- /dev/null +++ b/ivtest/ivltests/vhdl_range_func_pkg.vhd @@ -0,0 +1,53 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for 'range, 'left and 'right attributes in VHDL subprograms. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package range_func_pkg is + function negator (word_i : std_logic_vector(3 downto 0)) return std_logic_vector; + function reverse (word_i : std_logic_vector(3 downto 0)) return std_logic_vector; +end range_func_pkg; + +package body range_func_pkg is + +function negator (word_i : std_logic_vector(3 downto 0)) return std_logic_vector is + variable neg : std_logic_vector(word_i'left downto word_i'right); +begin + for I in word_i'range loop + neg (I) := not word_i(I); + end loop; + + return neg; +end function; + +function reverse (word_i : std_logic_vector(3 downto 0)) return std_logic_vector is + variable rev : std_logic_vector(3 downto 0); +begin + for I in word_i'right to word_i'left loop + rev (rev'left - I) := word_i(I); + end loop; + + return rev; +end function; + +end range_func_pkg; diff --git a/ivtest/ivltests/vhdl_range_pkg.vhd b/ivtest/ivltests/vhdl_range_pkg.vhd new file mode 100644 index 000000000..0878e4cee --- /dev/null +++ b/ivtest/ivltests/vhdl_range_pkg.vhd @@ -0,0 +1,29 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package vhdl_range_pkg is + subtype integer_asc is integer range 0 to 7; + subtype integer_desc is integer range 8 downto 1; +end vhdl_range_pkg; + +package body vhdl_range_pkg is +end vhdl_range_pkg; diff --git a/ivtest/ivltests/vhdl_real.v b/ivtest/ivltests/vhdl_real.v new file mode 100644 index 000000000..97a44a15d --- /dev/null +++ b/ivtest/ivltests/vhdl_real.v @@ -0,0 +1,60 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Basic test for 'real' floating-type support in VHDL. + +module vhdl_real_testbench; + vhdl_real dut(); + + initial begin + // simply check if the assigned values are correct + if (dut.c != 1111.222) begin + $display("FAILED"); + $finish; + end + + if (dut.e != 1135.022) begin + $display("FAILED"); + $finish; + end + + if (dut.a != 1.2) begin + $display("FAILED"); + $finish; + end + + if (dut.b != 32.12323) begin + $display("FAILED"); + $finish; + end + + if (dut.exp != 2.334e+2) begin + $display("FAILED"); + $finish; + end + + #10; // wait for the no_init signal assignment + if (dut.no_init != 33.32323) begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/vhdl_real.vhd b/ivtest/ivltests/vhdl_real.vhd new file mode 100644 index 000000000..9467a669d --- /dev/null +++ b/ivtest/ivltests/vhdl_real.vhd @@ -0,0 +1,39 @@ +-- Copyright (c) 2014 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Basic test for 'real' floating-type support in VHDL. + +library ieee; + +entity vhdl_real is +end; + +architecture test of vhdl_real is + constant c : real := 1111.222; + constant d : real := 23.8; + constant e : real := c + d; + + signal a : real := 1.2; + signal b : real := 32.123_23; + signal pi : real := 3.14159265; + signal exp : real := 2.334E+2; + signal no_init : real; +begin + no_init <= a + b; +end test; diff --git a/ivtest/ivltests/vhdl_record_elab.v b/ivtest/ivltests/vhdl_record_elab.v new file mode 100644 index 000000000..4c5777369 --- /dev/null +++ b/ivtest/ivltests/vhdl_record_elab.v @@ -0,0 +1,52 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Tests initialization of records with aggregate expressions. +// (based on the vhdl_struct_array test) + +module vhdl_record_elab_test; + reg [15:0] in; + wire [15:0] out; + + vhdl_record_elab dut( + .o_high1(out[15:12]), .o_low1(out[11:8]), + .o_high0(out[7:4]), .o_low0(out[3:0]), + + .i_high1(in[15:12]), .i_low1(in[11:8]), + .i_high0(in[7:4]), .i_low0(in[3:0])); + + initial begin + for (in = 0 ; in < 256 ; in = in+1) begin + #1 if (in !== out[15:0]) begin + $display("FAILED -- out=%h, in=%h", out, in); + $finish; + end + end + + if (dut.dword_a[0].low !== 4'b0110 || dut.dword_a[0].high !== 4'b1001 || + dut.dword_a[1].low !== 4'b0011 || dut.dword_a[1].high !== 4'b1100) + begin + $display("FAILED 2"); + $finish; + end + + $display("PASSED"); + end +endmodule + diff --git a/ivtest/ivltests/vhdl_record_elab.vhd b/ivtest/ivltests/vhdl_record_elab.vhd new file mode 100644 index 000000000..9ab76b985 --- /dev/null +++ b/ivtest/ivltests/vhdl_record_elab.vhd @@ -0,0 +1,65 @@ +-- Copyright (c) 2014 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Tests initialization of records with aggregate expressions. +-- (based on the vhdl_struct_array test) + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_record_elab is + port ( + i_low0: in std_logic_vector (3 downto 0); + i_high0: in std_logic_vector (3 downto 0); + i_low1: in std_logic_vector (3 downto 0); + i_high1: in std_logic_vector (3 downto 0); + o_low0: out std_logic_vector (3 downto 0); + o_high0: out std_logic_vector (3 downto 0); + o_low1: out std_logic_vector (3 downto 0); + o_high1: out std_logic_vector (3 downto 0) + ); +end vhdl_record_elab; + +architecture test of vhdl_record_elab is + +type word is record + high: std_logic_vector (3 downto 0); + low: std_logic_vector (3 downto 0); +end record; + +type dword is array (1 downto 0) of word; + +signal my_dword : dword; +signal dword_a : dword; + +begin + -- inputs + my_dword(0) <= (low => i_low0, high => i_high0); + -- test if you can assign values in any order + my_dword(1) <= (high => i_high1, low => i_low1); + + dword_a <= (0 => (low => "0110", high => "1001"), + 1 => (high => "1100", low => "0011")); + + -- outputs + o_low0 <= my_dword(0).low; + o_high0 <= my_dword(0).high; + o_low1 <= my_dword(1).low; + o_high1 <= my_dword(1).high; +end test; diff --git a/ivtest/ivltests/vhdl_reduce.v b/ivtest/ivltests/vhdl_reduce.v new file mode 100644 index 000000000..39ab364c6 --- /dev/null +++ b/ivtest/ivltests/vhdl_reduce.v @@ -0,0 +1,73 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for or_reduce/and_reduce functions. + +module vhdl_reduce_test; +logic [4:0] inp; +logic and_reduced, or_reduced; + +vhdl_reduce test(inp, and_reduced, or_reduced); + +initial begin + inp = 5'b00000; + #1 if(and_reduced !== 1'b0 || or_reduced !== 1'b0) begin + $display("FAILED 1"); + $finish(); + end + + inp = 5'b00010; + #1 if(and_reduced !== 1'b0 || or_reduced !== 1'b1) begin + $display("FAILED 2"); + $finish(); + end + + inp = 5'b11111; + #1 if(and_reduced !== 1'b1 || or_reduced !== 1'b1) begin + $display("FAILED 3"); + $finish(); + end + + inp = 5'bzz1xx; + #1 if(and_reduced !== 1'bx || or_reduced !== 1'b1) begin + $display(and_reduced); + $display(or_reduced); + $display("FAILED 4"); + $finish(); + end + + inp = 5'bzz0xx; + #1 if(and_reduced !== 1'b0 || or_reduced !== 1'bx) begin + $display(and_reduced); + $display(or_reduced); + $display("FAILED 5"); + $finish(); + end + + inp = 5'bzzzxx; + #1 if(and_reduced !== 1'bx || or_reduced !== 1'bx) begin + $display(and_reduced); + $display(or_reduced); + $display("FAILED 6"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/vhdl_reduce.vhd b/ivtest/ivltests/vhdl_reduce.vhd new file mode 100644 index 000000000..cd00bba33 --- /dev/null +++ b/ivtest/ivltests/vhdl_reduce.vhd @@ -0,0 +1,39 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for or_reduce/and_reduce functions. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_misc.all; + +entity vhdl_reduce is + port(inp : in std_logic_vector(4 downto 0); + and_reduced : out std_logic; + or_reduced : out std_logic); +end vhdl_reduce; + +architecture test of vhdl_reduce is +begin + process(inp) + begin + or_reduced <= or_reduce(inp); + and_reduced <= and_reduce(inp); + end process; +end test; diff --git a/ivtest/ivltests/vhdl_report.v b/ivtest/ivltests/vhdl_report.v new file mode 100644 index 000000000..234ebe4db --- /dev/null +++ b/ivtest/ivltests/vhdl_report.v @@ -0,0 +1,35 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Report & assert tests. + +module vhdl_report_test; + +logic start_test; +vhdl_report dut(start_test); +int a; + +initial begin + // as of the moment of writing vhdlpp does not handle procedure calls + a = vhdl_report_pkg::test_asserts(0); + + start_test = 1'b0; + #1 start_test = 1'b1; +end +endmodule diff --git a/ivtest/ivltests/vhdl_report.vhd b/ivtest/ivltests/vhdl_report.vhd new file mode 100644 index 000000000..03a34c05c --- /dev/null +++ b/ivtest/ivltests/vhdl_report.vhd @@ -0,0 +1,63 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Report & assert tests. + +library ieee; +use ieee.std_logic_1164.all; +use work.vhdl_report_pkg.all; + +entity vhdl_report is + port (start_test : in std_logic); +end vhdl_report; + +architecture test of vhdl_report is +begin + process(start_test) + begin + if(start_test = '1') then + -- Report without severity specified, by default it is NOTE + report "normal report"; + + -- Report with severity specified + -- should continue execution when severity != FAILURE + report "report with severity" + severity ERROR; + + -- Assert, no report, no severity specified, by default it is ERROR + assert false; + + -- Assert with report, no severity specified, by default it is ERROR + assert 1 = 0 + report "assert with report"; + + -- Assert without report, severity specified + -- should continue execution when severity != FAILURE + assert 1 = 2 + severity NOTE; + + -- Assert with report and severity specified + assert false + report "assert with report & severity" + severity FAILURE; -- FAILURE causes program to stop + + report "this should never be shown"; + end if; + end process; +end architecture test; diff --git a/ivtest/ivltests/vhdl_report_pkg.vhd b/ivtest/ivltests/vhdl_report_pkg.vhd new file mode 100644 index 000000000..a6b33b8dd --- /dev/null +++ b/ivtest/ivltests/vhdl_report_pkg.vhd @@ -0,0 +1,53 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Report & assert tests. + +library ieee; +use ieee.std_logic_1164.all; + +package vhdl_report_pkg is + -- as of the moment of writing vhdlpp does not support procedures + function test_asserts(a : integer) return integer; +end vhdl_report_pkg; + +package body vhdl_report_pkg is + +-- Test functions used to output package files +function test_asserts(a : integer) return integer is +begin + report "procedure 1" + severity ERROR; + + assert false; + + assert 1 = 0 + report "procedure 2"; + + assert 1 = 2 + severity NOTE; + + assert false + report "procedure 3" + severity WARNING; + + return 0; +end function; + +end vhdl_report_pkg; diff --git a/ivtest/ivltests/vhdl_resize.v b/ivtest/ivltests/vhdl_resize.v new file mode 100644 index 000000000..46ca0dc1a --- /dev/null +++ b/ivtest/ivltests/vhdl_resize.v @@ -0,0 +1,45 @@ +// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Resize function test + +module vhdl_resize_test; +logic signed [7:0] in; +logic signed [15:0] out; +vhdl_resize dut(in, out); + +initial begin + in = -120; + #0; + if(out !== -115) begin + $display("FAILED 1: out = %d", out); + $finish(); + end + + in = 120; + #0; + if(out !== 125) begin + $display("FAILED 2: out = %d", out); + $finish(); + end + + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/vhdl_resize.vhd b/ivtest/ivltests/vhdl_resize.vhd new file mode 100644 index 000000000..f88589faa --- /dev/null +++ b/ivtest/ivltests/vhdl_resize.vhd @@ -0,0 +1,36 @@ +-- Copyright (c) 2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and-or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Resize function test + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vhdl_resize is + port( + input : in signed(7 downto 0); + output : out signed(15 downto 0) + ); +end vhdl_resize; + +architecture rtl of vhdl_resize is +begin + output <= resize(input + 5, output'length); +end rtl; diff --git a/ivtest/ivltests/vhdl_rtoi.v b/ivtest/ivltests/vhdl_rtoi.v new file mode 100644 index 000000000..1b7d42ec9 --- /dev/null +++ b/ivtest/ivltests/vhdl_rtoi.v @@ -0,0 +1,50 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test real to integer conversion + +module vhdl_rtoi_testbench; + vhdl_rtoi dut(); + + initial begin + #1; // wait for the no_init signal assignment + + if (dut.a !== 2) begin + $display("FAILED 1"); + $finish; + end + + if (dut.b !== 4) begin + $display("FAILED 2"); + $finish; + end + + if (dut.c !== 5) begin + $display("FAILED 3"); + $finish; + end + + if (dut.d !== 17) begin + $display("FAILED 4"); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/vhdl_rtoi.vhd b/ivtest/ivltests/vhdl_rtoi.vhd new file mode 100644 index 000000000..a8441bd37 --- /dev/null +++ b/ivtest/ivltests/vhdl_rtoi.vhd @@ -0,0 +1,36 @@ +-- Copyright (c) 2014 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test real to integer conversion + +library ieee; +use ieee.numeric_std.all; + +entity vhdl_rtoi is +end; + +architecture test of vhdl_rtoi is + signal a, b, c, d : integer; +begin + -- test rounding + a <= integer(2.3); -- should be 2 + b <= integer(3.7); -- should be 4 + c <= integer(4.5); -- should be 5 + d <= integer(8.1 * 2.1); -- ==17.01, should be 17 +end test; diff --git a/ivtest/ivltests/vhdl_sa1_test1.v b/ivtest/ivltests/vhdl_sa1_test1.v new file mode 100644 index 000000000..2f522b1ca --- /dev/null +++ b/ivtest/ivltests/vhdl_sa1_test1.v @@ -0,0 +1,109 @@ +// This module generates M pairs of N-1 bits unsigned numbers A, B +// and also serialises them starting from LSB bits between +// activation of active-high reset signal + +module stimulus #(parameter N = 4, M = 10) (input clk, + output reg reset, + output reg sa, sb, + output reg unsigned [N-1:0] A, B ); + +parameter D = 5; +int unsigned i; +reg unsigned [N-1:0] r1, r2; + +initial begin + repeat(M) begin + r1 = {$random} % N; + r2 = {$random} % N; + do_items(r1, r2); + end +end + +task do_items (input unsigned [N-1:0] v1, v2); +begin + A = 0; B = 0; reset = 0; + do_reset(); + A = v1; B = v2; + for (i=0; i| |------>|D Q|---> s_o +-- b_i -->| FA1 | | | +-- | |--- | | +-- ---> |_______| | |_____| +--rst __|_______________________| +-- | | | +-- | | | +-- | | | ______ +-- | | ---->|D Q|--- +-- | | | | | +-- | | | | | +-- | | |_____| | +-- | |____________| | +-- |________________________________| +-- + +library ieee; +use ieee.std_logic_1164.all; +use work.work6.all; + +entity sa1 is + port (clk, reset: in std_logic; + a_i, b_i: in std_logic; + s_o: out std_logic + ); +end entity sa1; + +architecture sa1_rtl of sa1 is +signal sum, carry, carry_reg: std_logic; +begin + + a1: fa1 port map (c_i => carry_reg, + a_i => a_i, + b_i => b_i, + s_o => sum, + c_o => carry + ); + + f1: fdc port map (clk => clk, reset => reset, d => sum, q => s_o); + f2: fdc port map (clk => clk, reset => reset, d => carry, q => carry_reg); + +end architecture sa1_rtl; +-- a one bit full adder written according to +-- textbook's boolean equations + +library ieee; +use ieee.std_logic_1164.all; + +entity fa1 is + port (a_i, b_i, c_i: in std_logic; + s_o, c_o: out std_logic + ); +end entity fa1; + +architecture fa1_rtl of fa1 is +begin + + s_o <= a_i xor b_i xor c_i; + c_o <= (a_i and b_i) or (c_i and (a_i xor b_i)); + +end architecture fa1_rtl;-- a D-type flip-flop with synchronous reset + +library ieee; +use ieee.std_logic_1164.all; + + +entity fdc is +port (clk: in std_logic; + reset: in std_logic; + d: in std_logic; + q: out std_logic +); +end fdc; + +architecture fdc_rtl of fdc is +begin + +i_finish: process (clk) +begin + if (clk'event and clk = '1') then + if (reset = '1') then + q <= '0'; + else + q <= d; + end if; + end if; +end process; + +end fdc_rtl; diff --git a/ivtest/ivltests/vhdl_sa1_test2.v b/ivtest/ivltests/vhdl_sa1_test2.v new file mode 100644 index 000000000..2f522b1ca --- /dev/null +++ b/ivtest/ivltests/vhdl_sa1_test2.v @@ -0,0 +1,109 @@ +// This module generates M pairs of N-1 bits unsigned numbers A, B +// and also serialises them starting from LSB bits between +// activation of active-high reset signal + +module stimulus #(parameter N = 4, M = 10) (input clk, + output reg reset, + output reg sa, sb, + output reg unsigned [N-1:0] A, B ); + +parameter D = 5; +int unsigned i; +reg unsigned [N-1:0] r1, r2; + +initial begin + repeat(M) begin + r1 = {$random} % N; + r2 = {$random} % N; + do_items(r1, r2); + end +end + +task do_items (input unsigned [N-1:0] v1, v2); +begin + A = 0; B = 0; reset = 0; + do_reset(); + A = v1; B = v2; + for (i=0; i| |------>|D Q|---> s_o +-- b_i -->| FA1 | | | +-- | |--- | | +-- ---> |_______| | |_____| +--rst __|_______________________| +-- | | | +-- | | | +-- | | | ______ +-- | | ---->|D Q|--- +-- | | | | | +-- | | | | | +-- | | |_____| | +-- | |____________| | +-- |________________________________| +-- + +library ieee; +use ieee.std_logic_1164.all; +use work.work6.all; + +entity sa1 is + port (clk, reset: in std_logic; + a_i, b_i: in std_logic; + s_o: out std_logic + ); +end entity sa1; + +architecture sa1_rtl of sa1 is +signal sum, carry, carry_reg: std_logic; +begin + + a1: fa1 port map (c_i => carry_reg, + a_i => a_i, + b_i => b_i, + s_o => sum, + c_o => carry + ); + + f1: fdc port map (clk => clk, reset => reset, d => sum, q => s_o); + f2: fdc port map (clk => clk, reset => reset, d => carry, q => carry_reg); + +end architecture sa1_rtl; +-- a one bit full adder written according to +-- textbook's boolean equations + +library ieee; +use ieee.std_logic_1164.all; + +entity fa1 is + port (a_i, b_i, c_i: in std_logic; + s_o, c_o: out std_logic + ); +end entity fa1; + +architecture fa1_rtl of fa1 is +begin + + s_o <= a_i xor b_i xor c_i; + c_o <= (a_i and b_i) or (c_i and (a_i xor b_i)); + +end architecture fa1_rtl;-- a D-type flip-flop with synchronous reset + +library ieee; +use ieee.std_logic_1164.all; + + +entity fdc is +port (clk: in std_logic; + reset: in std_logic; + d: in std_logic; + q: out std_logic +); +end fdc; + +architecture fdc_rtl of fdc is +begin + +i_finish: process (clk) +begin + if (clk'event and clk = '1') then + if (reset = '1') then + q <= '0'; + else + q <= d; + end if; + end if; +end process; + +end fdc_rtl; diff --git a/ivtest/ivltests/vhdl_sa1_test3.v b/ivtest/ivltests/vhdl_sa1_test3.v new file mode 100644 index 000000000..71f14156e --- /dev/null +++ b/ivtest/ivltests/vhdl_sa1_test3.v @@ -0,0 +1,34 @@ +module test; + reg clk, reset; + wire [24:0] count; + + initial begin + clk = 1'b0; + forever #25 clk = ~clk; + end + + initial begin + reset = 1'b0; + @(negedge clk); + reset = 1'b1; + repeat(6) @(negedge clk); + reset = 1'b0; + end + + initial begin + #200000; + #500; + if (count != 2000) begin + $display ("Counting FAILED"); + $finish; + end + else begin + $display ("PASSED"); + #20; + $finish; + end +end + + bigcount duv (.clk(clk), .reset(reset), .count(count) ); + +endmodule diff --git a/ivtest/ivltests/vhdl_sa1_test3.vhd b/ivtest/ivltests/vhdl_sa1_test3.vhd new file mode 100644 index 000000000..4b8258f9e --- /dev/null +++ b/ivtest/ivltests/vhdl_sa1_test3.vhd @@ -0,0 +1,123 @@ +library ieee; +use ieee.std_logic_1164.all; + +package work6 is + + -- D-type flip flop + component fdc is + port (clk: in std_logic; + reset: in std_logic; + d: in std_logic; + q: out std_logic); + end component; + + component TimeBase is + port( + CLOCK : in std_logic; -- input clock of 20MHz + TICK : out std_logic; -- out 1 sec timebase signal + RESET : in std_logic; -- master reset signal (active high) + ENABLE : in std_logic; + COUNT_VALUE: out std_logic_vector (24 downto 0) + ); +end component; + +end package work6; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +-- The operation is: +-- 1) An internal counter (of 25 bits) is initilaised to zero after a reset is received. +-- 2) An enable allows an internal running counter to count clock pulses +-- 3) A tick signal output is generated when a count of 20000000 pulses has been accumulated + + +entity TimeBase is + port( + CLOCK : in std_logic; -- input clock of 20MHz + TICK : out std_logic; -- out 1 sec timebase signal + RESET : in std_logic; -- master reset signal (active high) + ENABLE : in std_logic; + COUNT_VALUE: out std_logic_vector (24 downto 0) + ); +end TimeBase; + +architecture TimeBase_rtl of TimeBase is + + constant DIVIDER_VALUE : std_logic_vector := x"7cf"; -- 20000000 count value, 1 second + signal RunningCounter : std_logic_vector(24 downto 0); -- this is the 25 bit free running counter to allow a big count +begin + + RunningCounterProcess : process (CLOCK) + begin + if ( CLOCK'event and CLOCK = '1') then + if (RESET = '1') then + RunningCounter <= '0' & x"000000"; + elsif ( ENABLE = '1') then + RunningCounter <= RunningCounter + 1; + end if; + else + RunningCounter <= RunningCounter; + end if; + end process; + + TICK <= '1' when (RunningCounter = DIVIDER_VALUE) else '0'; + +COUNT_VALUE <= RunningCounter; + +end TimeBase_rtl; + +library ieee; +use ieee.std_logic_1164.all; +use work.work6.all; + +entity bigcount is + port (clk, reset: in std_logic; + count: out std_logic_vector (24 downto 0) + ); +end entity bigcount; + +architecture bigcount_rtl of bigcount is +signal d, t, q, myreset: std_logic; +begin + +d <= t xor q; + +myreset <= reset or t; + +f1: fdc port map (clk => clk, reset => reset, d => d, q => q); +tb: timebase port map (CLOCK => clk, RESET => myreset, ENABLE => '1', TICK => t, COUNT_VALUE => open ); + +counting: timebase port map (CLOCK => clk, RESET => reset, ENABLE => q, TICK => open, COUNT_VALUE => count ); + + +end bigcount_rtl;-- a D-type flip-flop with synchronous reset + +library ieee; +use ieee.std_logic_1164.all; + + +entity fdc is +port (clk: in std_logic; + reset: in std_logic; + d: in std_logic; + q: out std_logic +); +end fdc; + +architecture fdc_rtl of fdc is +begin + +i_finish: process (clk) +begin + if (clk'event and clk = '1') then + if (reset = '1') then + q <= '0'; + else + q <= d; + end if; + end if; +end process; + +end fdc_rtl; diff --git a/ivtest/ivltests/vhdl_sadd23_bit.v b/ivtest/ivltests/vhdl_sadd23_bit.v new file mode 100644 index 000000000..dc54b62f5 --- /dev/null +++ b/ivtest/ivltests/vhdl_sadd23_bit.v @@ -0,0 +1,54 @@ +module check (input signed [22:0] a, b, c); + wire signed [22:0] int_AB; + + assign int_AB = a + b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB != c) begin + $display("ERROR"); + $finish; + end +end + +endmodule + +module stimulus (output reg signed [22:0] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 0; + for (i=0; i +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for selected assignments. + +module vhdl_selected_test; +logic [1:0] sel; +logic [3:0] in; +logic out; +vhdl_selected dut(sel, in, out); + +initial begin + in = 4'b1010; + + sel = 1'b00; + #1; + if(out !== 1'b0) begin + $display("FAILED 1"); + $finish(); + end + + sel = 1'b01; + #1; + if(out !== 1'b1) begin + $display("FAILED 2"); + $finish(); + end + + sel = 1'b10; + #1; + if(out !== 1'b0) begin + $display("FAILED 3"); + $finish(); + end + + sel = 1'b11; + #1; + if(out !== 1'b1) begin + $display("FAILED 4"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/vhdl_selected.vhd b/ivtest/ivltests/vhdl_selected.vhd new file mode 100644 index 000000000..5f7b8762b --- /dev/null +++ b/ivtest/ivltests/vhdl_selected.vhd @@ -0,0 +1,39 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for selected assignments. + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_selected is + port(sel : in std_logic_vector(1 downto 0); + inputs : in std_logic_vector(3 downto 0); + output : out std_logic); +end vhdl_selected; + +architecture test of vhdl_selected is +begin + with sel select + output <= inputs(0) when "00", + inputs(1) when "01", + inputs(2) when "10", + inputs(3) when "11", + 'Z' when others; +end test; diff --git a/ivtest/ivltests/vhdl_shift.v b/ivtest/ivltests/vhdl_shift.v new file mode 100644 index 000000000..e3a6f8d38 --- /dev/null +++ b/ivtest/ivltests/vhdl_shift.v @@ -0,0 +1,81 @@ +// Copyr (c) 2015-2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for shift operators (logical and arithmetic) + +module shifter_test; +reg signed [7:0] inp, out_srl, out_sll, out_sra, out_sla, out_shl_u, out_shr_u, out_shl_s, out_shr_s; +shifter dut(inp, out_srl, out_sll, out_sra, out_sla, out_shl_u, out_shr_u, out_shl_s, out_shr_s); + +initial begin + inp = 8'b11101100; + #1; // wait for signal assignments + + if(out_srl !== 8'b01110110) + begin + $display("FAILED 1"); + $finish(); + end + + if(out_sll !== 8'b11011000) + begin + $display("FAILED 2"); + $finish(); + end + + if(out_sra !== 8'b11110110) + begin + $display("FAILED 3"); + $finish(); + end + + if(out_sla !== 8'b11011000) + begin + $display("FAILED 4"); + $finish(); + end + + if(out_shl_u !== 8'b10110000) + begin + $display("FAILED 5"); + $finish(); + end + + if(out_shr_u !== 8'b00111011) + begin + $display("FAILED 6"); + $finish(); + end + + if(out_shl_s !== 8'b10110000) + begin + $display("FAILED 7"); + $finish(); + end + + if(out_shr_s !== 8'b11111011) + begin + $display("FAILED 8"); + $finish(); + end + + $display("PASSED"); +end +endmodule + diff --git a/ivtest/ivltests/vhdl_shift.vhd b/ivtest/ivltests/vhdl_shift.vhd new file mode 100644 index 000000000..8c64c36f7 --- /dev/null +++ b/ivtest/ivltests/vhdl_shift.vhd @@ -0,0 +1,50 @@ +-- Copyright (c) 2015-2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for shift operators (logical and arithmetic) + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_bit.all; + +entity shifter is + port(input : in signed(7 downto 0); + out_srl, out_sll, out_sra, out_sla : out signed(7 downto 0); + out_shl_u, out_shr_u : out unsigned(7 downto 0); + out_shl_s, out_shr_s : out signed(7 downto 0) + ); +end entity shifter; + +architecture test of shifter is +begin + process(input) + -- test the unsigned variant of shift_left/right() functions + variable unsigned_input : unsigned(7 downto 0); + begin + unsigned_input := input; + out_srl <= input srl 1; + out_sll <= input sll 1; + out_sra <= input sra 1; + out_sla <= input sla 1; + out_shl_s <= shift_left(input, 2); + out_shr_s <= shift_right(input, 2); + out_shl_u <= shift_left(unsigned_input, 2); + out_shr_u <= shift_right(unsigned_input, 2); + end process; +end architecture test; diff --git a/ivtest/ivltests/vhdl_signals.v b/ivtest/ivltests/vhdl_signals.v new file mode 100644 index 000000000..10cb4e9eb --- /dev/null +++ b/ivtest/ivltests/vhdl_signals.v @@ -0,0 +1,19 @@ +module main; + + reg [4:0] src; + wire dst; + + test dut(.i(src[3:0]), .o(dst)); + + initial begin + for (src = 0 ; src < 16 ; src = src+1) begin + #1 if (dst !== & src[3:0]) begin + $display("FAILED: src=%b, dst=%b", src, dst); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/vhdl_signals.vhd b/ivtest/ivltests/vhdl_signals.vhd new file mode 100644 index 000000000..59351d330 --- /dev/null +++ b/ivtest/ivltests/vhdl_signals.vhd @@ -0,0 +1,32 @@ +-- This VHDL was converted from Verilog using the +-- Icarus Verilog VHDL Code Generator 0.10.0 (devel) (s20090923-656-gce5c263) + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Generated from Verilog module test (foo.v:3) +entity test is + port ( + i : in unsigned(3 downto 0); + o : out std_logic + ); +end entity; + +-- Generated from Verilog module test (foo.v:3) +architecture from_verilog of test is + signal tmp_s1 : std_logic; -- Temporary created at foo.v:6 + signal tmp_s11 : std_logic; -- Temporary created at foo.v:6 + signal tmp_s3 : std_logic; -- Temporary created at foo.v:6 + signal tmp_s4 : std_logic; -- Temporary created at foo.v:6 + signal tmp_s7 : std_logic; -- Temporary created at foo.v:6 + signal tmp_s8 : std_logic; -- Temporary created at foo.v:6 +begin + tmp_s4 <= tmp_s1 and tmp_s3; + tmp_s8 <= tmp_s4 and tmp_s7; + o <= tmp_s8 and tmp_s11; + tmp_s1 <= i(3); + tmp_s3 <= i(2); + tmp_s7 <= i(1); + tmp_s11 <= i(0); +end architecture; diff --git a/ivtest/ivltests/vhdl_smul23_bit.v b/ivtest/ivltests/vhdl_smul23_bit.v new file mode 100644 index 000000000..48c6e7c17 --- /dev/null +++ b/ivtest/ivltests/vhdl_smul23_bit.v @@ -0,0 +1,54 @@ +module check (input signed [22:0] a, b, input signed [45:0] c); + wire signed [45:0] int_AB; + + assign int_AB = a * b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB != c) begin + $display("ERROR"); + $finish; + end +end + +endmodule + +module stimulus (output reg signed [22:0] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 0; + for (i=0; i +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test string escaping in VHDL. + +module vhdl_string_test; +logic start; +vhdl_string dut(start); +// nothing else is needed here +endmodule diff --git a/ivtest/ivltests/vhdl_string.vhd b/ivtest/ivltests/vhdl_string.vhd new file mode 100644 index 000000000..cc443baea --- /dev/null +++ b/ivtest/ivltests/vhdl_string.vhd @@ -0,0 +1,43 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test string escaping in VHDL. + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_string is + port (start : in std_logic); +end entity vhdl_string; + +architecture test of vhdl_string is +begin + process (start) + variable test_str : string(1 to 4) := "VHDL"; + begin + report ""; + report """"; + report "test"; + report test_str; + + report ("brackets test"); + report ((("multiple brackets test"))); + report """quotation "" marks "" test"""; + end process; +end architecture test; diff --git a/ivtest/ivltests/vhdl_string_lim.v b/ivtest/ivltests/vhdl_string_lim.v new file mode 100644 index 000000000..d83885fd9 --- /dev/null +++ b/ivtest/ivltests/vhdl_string_lim.v @@ -0,0 +1,36 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test limited length strings in VHDL. + +module vhdl_string_lim_test; +logic start, res; +vhdl_string_lim dut(start, res); + +initial begin + #1; + + if(res !== 1'b1) begin + $display("FAILED"); + $finish(); + end + + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/vhdl_string_lim.vhd b/ivtest/ivltests/vhdl_string_lim.vhd new file mode 100644 index 000000000..87e9a6d80 --- /dev/null +++ b/ivtest/ivltests/vhdl_string_lim.vhd @@ -0,0 +1,43 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test limited length strings in VHDL. + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_string_lim is + port (start : in std_logic; + res : out std_logic); +end entity vhdl_string_lim; + +architecture test of vhdl_string_lim is +begin + process (start) + variable a : string; + variable b : string(1 to 1); + variable c : string(1 to 5); + begin + a := "test string"; + b := "a"; + c := "abcde"; + + res <= (a = "test string") and (b = "a") and (c = "abcde"); + end process; +end architecture test; diff --git a/ivtest/ivltests/vhdl_struct_array.v b/ivtest/ivltests/vhdl_struct_array.v new file mode 100644 index 000000000..edb743565 --- /dev/null +++ b/ivtest/ivltests/vhdl_struct_array.v @@ -0,0 +1,22 @@ +module main; + + reg [16:0] in; + wire [15:0] out; + + foo_entity dut (.o_high1(out[15:12]), .o_low1(out[11:8]), + .o_high0(out[7:4]), .o_low0(out[3:0]), + + .i_high1(in[15:12]), .i_low1(in[11:8]), + .i_high0(in[7:4]), .i_low0(in[3:0])); + + initial begin + for (in = 0 ; in < 256 ; in = in+1) begin + #1 if (in !== out[15:0]) begin + $display("FAILED -- out=%h, in=%h", out, in); + $finish; + end + end + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/vhdl_struct_array.vhd b/ivtest/ivltests/vhdl_struct_array.vhd new file mode 100644 index 000000000..b6865a6c1 --- /dev/null +++ b/ivtest/ivltests/vhdl_struct_array.vhd @@ -0,0 +1,41 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity foo_entity is + port ( + i_low0: in std_logic_vector (3 downto 0); + i_high0: in std_logic_vector (3 downto 0); + i_low1: in std_logic_vector (3 downto 0); + i_high1: in std_logic_vector (3 downto 0); + o_low0: out std_logic_vector (3 downto 0); + o_high0: out std_logic_vector (3 downto 0); + o_low1: out std_logic_vector (3 downto 0); + o_high1: out std_logic_vector (3 downto 0) + ); +end foo_entity; + +architecture beh of foo_entity is + +type word is record + high: std_logic_vector (3 downto 0); + low: std_logic_vector (3 downto 0); +end record; + +type dword is array (1 downto 0) of word; + +signal my_dword: dword; + +begin + -- inputs + my_dword(0).low <= i_low0; + my_dword(0).high <= i_high0; + my_dword(1).low <= i_low1; + my_dword(1).high <= i_high1; + + -- outputs + o_low0 <= my_dword(0).low; + o_high0 <= my_dword(0).high; + o_low1 <= my_dword(1).low; + o_high1 <= my_dword(1).high; + +end beh; diff --git a/ivtest/ivltests/vhdl_subprogram.v b/ivtest/ivltests/vhdl_subprogram.v new file mode 100644 index 000000000..bb16c5c9c --- /dev/null +++ b/ivtest/ivltests/vhdl_subprogram.v @@ -0,0 +1,40 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +// Tests for various subprogram features (see the responding VHDL file for +// details). + +module subprogram_test; + subprogram dut(); + + initial begin + #1; // wait for signal assignment + + if(dut.negated !== 'b00111000) begin + $display("FAILED 1"); + $finish; + end + + if(dut.reversed != 'b11100001) begin + $display("FAILED 2"); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/vhdl_subprogram.vhd b/ivtest/ivltests/vhdl_subprogram.vhd new file mode 100644 index 000000000..63f8deb2c --- /dev/null +++ b/ivtest/ivltests/vhdl_subprogram.vhd @@ -0,0 +1,51 @@ +-- Copyright (c) 2014 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +-- Tests for various subprogram features. + +library ieee; +use ieee.std_logic_1164.all; +-- tests subprograms imported from an external library +use work.subprogram_pkg.all; + +entity subprogram is +end; + +architecture behaviour of subprogram is + function negate(input_word : std_logic_vector(7 downto 0)) + -- tests using undefined size std_logic_vector as a return type + return std_logic_vector is + -- tests variable declaration in subprograoms + variable output_word : std_logic_vector(7 downto 0); + begin + for i in 7 downto 0 loop + -- tests distuingishing between vector and function call basing on the + -- function parameter + output_word(i) := not input_word(i); + end loop; + + return output_word; + end function; + + signal negated : std_logic_vector(7 downto 0); + signal reversed : std_logic_vector(7 downto 0); +begin + -- parameter type is determined by checking the parameter type in function declaration + negated <= negate("11000111"); + reversed <= reverse("10000111"); +end; diff --git a/ivtest/ivltests/vhdl_subprogram_pkg.vhd b/ivtest/ivltests/vhdl_subprogram_pkg.vhd new file mode 100644 index 000000000..3abeb7ae4 --- /dev/null +++ b/ivtest/ivltests/vhdl_subprogram_pkg.vhd @@ -0,0 +1,41 @@ +-- Copyright (c) 2014 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +-- Tests for various subprogram features. + +library ieee; +use ieee.std_logic_1164.all; + +-- tests functions defined in packages +package subprogram_pkg is + function reverse(input_word : std_logic_vector(7 downto 0)) + return std_logic_vector; +end subprogram_pkg; + +package body subprogram_pkg is + function reverse(input_word : std_logic_vector(7 downto 0)) + return std_logic_vector is + variable output_word : std_logic_vector(7 downto 0); + begin + for i in 7 downto 0 loop + output_word(i) := input_word(7 - i); + end loop; + + return output_word; + end function; +end subprogram_pkg; diff --git a/ivtest/ivltests/vhdl_subtypes.v b/ivtest/ivltests/vhdl_subtypes.v new file mode 100644 index 000000000..2222afbf8 --- /dev/null +++ b/ivtest/ivltests/vhdl_subtypes.v @@ -0,0 +1,61 @@ +// Copyright (c) 2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for subtype definitions. + +module vhdl_subtypes_test; +int a, b, c; +time d; +int e; + +vhdl_subtypes dut(a, b, c, d, e); + +initial +begin + #1; + + if(a !== 1) begin + $display("FAILED"); + $finish(); + end + + if(b !== 2) begin + $display("FAILED"); + $finish(); + end + + if(c !== 3) begin + $display("FAILED"); + $finish(); + end + + if(d !== 4) begin + $display("FAILED"); + $finish(); + end + + if(e !== 5) begin + $display("FAILED"); + $finish(); + end + + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/vhdl_subtypes.vhd b/ivtest/ivltests/vhdl_subtypes.vhd new file mode 100644 index 000000000..96682a1dd --- /dev/null +++ b/ivtest/ivltests/vhdl_subtypes.vhd @@ -0,0 +1,47 @@ +-- Copyright (c) 2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for subtype definitions. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_bit.all; +use work.vhdl_subtypes_pkg.all; + +entity vhdl_subtypes is + port( a : out int_type_const; + b : out int_type; + c : out int_type_downto; + d : out time_type; + e : out uns_type_const + ); +end vhdl_subtypes; + +architecture test of vhdl_subtypes is +begin + process + begin + a <= 1; + b <= 2; + c <= 3; + d <= 4 s; + e <= 5; + wait; + end process; +end test; diff --git a/ivtest/ivltests/vhdl_subtypes_pkg.vhd b/ivtest/ivltests/vhdl_subtypes_pkg.vhd new file mode 100644 index 000000000..5c407c7d1 --- /dev/null +++ b/ivtest/ivltests/vhdl_subtypes_pkg.vhd @@ -0,0 +1,37 @@ +-- Copyright (c) 2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for subtype definitions. + +library ieee; +use ieee.numeric_bit.all; + +package vhdl_subtypes_pkg is + constant type_range : integer := 10; + + subtype int_type_const is integer range 0 to type_range-1; + subtype int_type is integer range 0 to 7; + subtype int_type_downto is integer range 8 downto 1; + subtype time_type is time range 0 fs to 1 ms; + subtype uns_type_const is unsigned(7 downto 0); +end vhdl_subtypes_pkg; + +package body vhdl_subtypes_pkg is +end vhdl_subtypes_pkg; + diff --git a/ivtest/ivltests/vhdl_test1.v b/ivtest/ivltests/vhdl_test1.v new file mode 100644 index 000000000..b9b5828a8 --- /dev/null +++ b/ivtest/ivltests/vhdl_test1.v @@ -0,0 +1,19 @@ +module main; + + wire [15:0] out; + reg [16:0] in; + + mask dut (.\output (out), .\input (in[15:0])); + + wire [15:0] out_ref = in[15:0] & 16'haaaa; + initial begin + for (in = 0 ; in[16] == 0 ; in = in+1) + #1 if (out !== out_ref) begin + $display("FAILED: in=%b, out=%b, out_ref=%b", in, out, out_ref); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/vhdl_test1.vhd b/ivtest/ivltests/vhdl_test1.vhd new file mode 100644 index 000000000..9048a0d6a --- /dev/null +++ b/ivtest/ivltests/vhdl_test1.vhd @@ -0,0 +1,25 @@ +-- +-- Author: Pawel Szostek (pawel.szostek@cern.ch) +-- Date: 28.07.2011 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mask is + port (input : in std_logic_vector(15 downto 0); + output : out std_logic_vector(15 downto 0) + ); +end; + +architecture behaviour of mask is +begin + L: process(input) + variable tmp : std_logic_vector(15 downto 0); + begin + output <= tmp; --this shouln't really change anything + tmp := input; + tmp := tmp and "1010101010101010"; + output <= tmp; + end process; +end; diff --git a/ivtest/ivltests/vhdl_test2.v b/ivtest/ivltests/vhdl_test2.v new file mode 100644 index 000000000..f4bc5bbe4 --- /dev/null +++ b/ivtest/ivltests/vhdl_test2.v @@ -0,0 +1,22 @@ +module main; + + wire [15:0] out; + reg [16:0] in; + reg [15:0] mask; + + mask dut (.\output (out), .\input (in[15:0]), .mask(mask)); + + wire [15:0] out_ref = in[15:0] & mask; + initial begin + for (in = 0 ; in[16] == 0 ; in = in+1) begin + mask = $random; + #1 if (out !== out_ref) begin + $display("FAILED: in=%b, out=%b, mask=%b, out_ref=%b", in, out, mask, out_ref); + $finish; + end + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/vhdl_test2.vhd b/ivtest/ivltests/vhdl_test2.vhd new file mode 100644 index 000000000..b668f9841 --- /dev/null +++ b/ivtest/ivltests/vhdl_test2.vhd @@ -0,0 +1,25 @@ +-- +-- Author: Pawel Szostek (pawel.szostek@cern.ch) +-- Date: 28.07.2011 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mask is + port (input : in std_logic_vector(15 downto 0); + mask : in std_logic_vector(15 downto 0); + output : out std_logic_vector(15 downto 0) + ); +end; + +architecture behaviour of mask is +begin + L: process(input) + variable tmp : std_logic_vector(15 downto 0); + begin + tmp := input; + tmp := tmp and mask; + output <= tmp; + end process; +end; diff --git a/ivtest/ivltests/vhdl_test3.v b/ivtest/ivltests/vhdl_test3.v new file mode 100644 index 000000000..37cd49f6a --- /dev/null +++ b/ivtest/ivltests/vhdl_test3.v @@ -0,0 +1,18 @@ +module main; + + reg clk; + reg [4:0] in; + wire [15:0] out; + + dummy dut (.clk(clk), .\input (in[3:0]), .\output (out)); + + initial begin + clk = 0; + for (in = 0 ; in <= 16 ; in = in+1) begin + #1 clk = 1; + #1 clk = 0; + $display("input = %b, output=%b", in[3:0], out); + end + end + +endmodule // main diff --git a/ivtest/ivltests/vhdl_test3.vhd b/ivtest/ivltests/vhdl_test3.vhd new file mode 100644 index 000000000..4665b7162 --- /dev/null +++ b/ivtest/ivltests/vhdl_test3.vhd @@ -0,0 +1,37 @@ +-- +-- Author: Pawel Szostek (pawel.szostek@cern.ch) +-- Date: 28.07.2011 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dummy is + port (clk : in std_logic; + input : in std_logic_vector(3 downto 0); + output : out std_logic_vector(15 downto 0) + ); +end; + +architecture behaviour of dummy is +begin + L: process(clk) + variable one : integer; -- mix integers and unsigned + variable a : unsigned (6 downto 0); -- + variable b,c,d : unsigned(6 downto 0); + begin + if(clk'event and clk = '1') then + --do some mess around.. + a(3 downto 0) := unsigned(input); + a(6 downto 4) := "000"; + one := 1; + b := a + one; --unsigned plus integer + b := a + 1; --variable plus constant integer + c := a + a; -- + c := c - b; --two assignments in a row to the same variable + d := c + 2; + output(6 downto 0) <= std_logic_vector(d); --signal assignment + output(15 downto 7) <= (others => '0'); + end if; + end process; +end; diff --git a/ivtest/ivltests/vhdl_test4.v b/ivtest/ivltests/vhdl_test4.v new file mode 100644 index 000000000..7f74f140b --- /dev/null +++ b/ivtest/ivltests/vhdl_test4.v @@ -0,0 +1,25 @@ +module test; + + wire [7:0] o1, o2, o3; + dummy foo(.o1(o1), .o2(o2), .o3(o3)); + + initial begin + #1 if (o1 !== 8'h00) begin + $display("FAILED -- o1 = %b", o1); + $finish; + end + + if (o2 !== 8'h08) begin + $display("FAILED -- o2 = %b", o2); + $finish; + end + + if (o3 !== 8'h80) begin + $display("FAILED == o3 = %b", o3); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule diff --git a/ivtest/ivltests/vhdl_test4.vhd b/ivtest/ivltests/vhdl_test4.vhd new file mode 100644 index 000000000..014906eea --- /dev/null +++ b/ivtest/ivltests/vhdl_test4.vhd @@ -0,0 +1,22 @@ +-- +-- Author: Pawel Szostek (pawel.szostek@cern.ch) +-- Date: 27.07.2011 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dummy is + port (o1: out std_logic_vector(7 downto 0); + o2: out std_logic_vector(7 downto 0); + o3: out std_logic_vector(7 downto 0) + ); +end; + +architecture behaviour of dummy is +begin + o1 <= (others => '0'); + o2 <= (3 => '1', others => '0'); + o3 <= (7=>'1', 6|5|4|3|2|1|0 => '0', others => '1'); --tricky + +end; diff --git a/ivtest/ivltests/vhdl_test5.v b/ivtest/ivltests/vhdl_test5.v new file mode 100644 index 000000000..1d3461625 --- /dev/null +++ b/ivtest/ivltests/vhdl_test5.v @@ -0,0 +1,60 @@ +// +// Author: Pawel Szostek (pawel.szostek@cern.ch) +// Date: 01.08.2011 + +`timescale 1ns/1ps + +module stimulus (output reg [7:0] a); + parameter S = 20000; + int unsigned j,i; + initial begin + for(i=0; i= 10) + ret = 1'b1; + else if(temp >= 4) + ret = 1'b0; + else if(temp >= 2) + ret = 1'bx; + else + ret = 1'b0; + inject = ret; + end + endfunction +endmodule +module main; + wire [7:0] i, o; + wire [0:7] o_vl; + dummy dummy_vhdl(o, i); + stimulus stim(i); + assign o_vl = i; + + always @(i) begin + #1; + if(o !== o_vl) begin + $display("OUTPUT: ", o); + $display("INPUT: ", i); + $display("CORRECT: ", o_vl); + end + end + initial begin + #120000; + $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/vhdl_test5.vhd b/ivtest/ivltests/vhdl_test5.vhd new file mode 100644 index 000000000..30080d09b --- /dev/null +++ b/ivtest/ivltests/vhdl_test5.vhd @@ -0,0 +1,18 @@ +-- +-- Author: Pawel Szostek (pawel.szostek@cern.ch) +-- Date: 27.07.2011 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dummy is + port (o1: out std_logic_vector(7 downto 0); -- intentionally messed indices + i1: in std_logic_vector(0 to 7) -- + ); +end; + +architecture behaviour of dummy is +begin + o1 <= i1; +end; diff --git a/ivtest/ivltests/vhdl_test6.v b/ivtest/ivltests/vhdl_test6.v new file mode 100644 index 000000000..d377fbc03 --- /dev/null +++ b/ivtest/ivltests/vhdl_test6.v @@ -0,0 +1,60 @@ +// +// Author: Pawel Szostek (pawel.szostek@cern.ch) +// Date: 01.08.2011 + +`timescale 1ns/1ps + +module stimulus (output reg [7:0] a); + parameter S = 20000; + int unsigned j,i; + initial begin + for(i=0; i= 10) + ret = 1'b1; + else if(temp >= 4) + ret = 1'b0; + else if(temp >= 2) + ret = 1'bx; + else + ret = 1'b0; + inject = ret; + end + endfunction +endmodule +module main; + wire [7:0] i, o; + wire [0:7] o_vl; + dummy dummy_vhdl(o, i); + stimulus stim(i); + assign o_vl = i; + + always @(i) begin + #1 + if(o !== o_vl) begin + $display("OUTPUT: ", o); + $display("INPUT: ", i); + $display("CORRECT: ", o_vl); + end + end + initial begin + #120000; + $display("PASSED"); + $finish; + end +endmodule diff --git a/ivtest/ivltests/vhdl_test6.vhd b/ivtest/ivltests/vhdl_test6.vhd new file mode 100644 index 000000000..7aa323172 --- /dev/null +++ b/ivtest/ivltests/vhdl_test6.vhd @@ -0,0 +1,18 @@ +-- +-- Author: Pawel Szostek (pawel.szostek@cern.ch) +-- Date: 27.07.2011 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dummy is + port (o1: out std_logic_vector(8 downto 1); -- intentionally messed indices + i1: in std_logic_vector(0 to 7) -- + ); +end; + +architecture behaviour of dummy is +begin + o1 <= i1; +end; diff --git a/ivtest/ivltests/vhdl_test7.v b/ivtest/ivltests/vhdl_test7.v new file mode 100644 index 000000000..701769809 --- /dev/null +++ b/ivtest/ivltests/vhdl_test7.v @@ -0,0 +1,67 @@ +// +// Author: Pawel Szostek (pawel.szostek@cern.ch) +// Date: 01.08.2011 + +`timescale 1ns/1ps + +module dummy_v( input [7:0] in, output reg [7:0] out); + assign out = {in[7], 7'b1111111}; //there is no equivalent to vhdl's `others' +endmodule + +module stimulus (output reg [7:0] a); + parameter S = 20000; + int unsigned j,i; + initial begin + for(i=0; i= 10) + ret = 1'b1; + else if(temp >= 4) + ret = 1'b0; + else if(temp >= 2) + ret = 1'bx; + else + ret = 1'b0; + inject = ret; + end + endfunction +endmodule +module main; + wire [7:0] i,o; + wire [7:0] veri; + dummy dummy_vhdl(i,o); + dummy_v dummy_verilog(i, veri); + stimulus stim(i); + + + always @(i) begin + #1; + if(o != veri) begin + $display("ERROR!"); + $display("VERILOG: ", veri); + $display("VHDL: ", o); + $stop; + end + end + initial begin + #12000; + #10; + $display("PASSED"); + //stop; + end +endmodule diff --git a/ivtest/ivltests/vhdl_test7.vhd b/ivtest/ivltests/vhdl_test7.vhd new file mode 100644 index 000000000..f0491a231 --- /dev/null +++ b/ivtest/ivltests/vhdl_test7.vhd @@ -0,0 +1,25 @@ +-- +-- Author: Pawel Szostek (pawel.szostek@cern.ch) +-- Date: 28.07.2011 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dummy is + port ( + input : in std_logic_vector(7 downto 0); + output : out std_logic_vector(7 downto 0) + ); +end; + +architecture behaviour of dummy is +begin + L: process(input) + variable tmp : std_logic_vector(7 downto 0); + begin + tmp := input; -- use multiple assignments to the same variable + tmp := (7 => input(7), others => '1'); -- inluding slices in a process + output <= tmp; + end process; +end; diff --git a/ivtest/ivltests/vhdl_test8.v b/ivtest/ivltests/vhdl_test8.v new file mode 100644 index 000000000..917eabbff --- /dev/null +++ b/ivtest/ivltests/vhdl_test8.v @@ -0,0 +1,70 @@ +// +// Author: Pawel Szostek (pawel.szostek@cern.ch) +// Date: 01.08.2011 + +`timescale 1ns/1ps +module match_bits_v(input [7:0] a,b, output reg [7:0] match); + integer i; + wire ab_xor; + always @(a or b) begin + for (i=7; i>=0; i=i-1) begin + match[i] = ~(a[i]^b[i]); + end + end +endmodule + +module check(input [7:0] a,b,o_vhdl, o_verilog); + +always @(a or b) begin + #1 if (o_vhdl !== o_verilog) begin + $display("ERROR!"); + $display("VERILOG: ", o_verilog); + $display("VHDL: ", o_vhdl); + $finish; + end +end +endmodule + +module stimulus (output reg [7:0] a,b); + parameter S = 20000; + int unsigned i,j,k,l; + initial begin //stimulate data + for (i=0; i= 10) + inject = 1'b1; + else + inject = 1'b0; + end + endfunction +endmodule + +module main; + wire [7:0] a,b,o_vhdl, o_verilog; + + match_bits match_vhdl(a,b,o_vhdl); + match_bits_v match_verilog(a,b,o_verilog); + stimulus stim(a,b); + check c(a,b,o_vhdl, o_verilog); +endmodule diff --git a/ivtest/ivltests/vhdl_test8.vhd b/ivtest/ivltests/vhdl_test8.vhd new file mode 100644 index 000000000..73cde8ad6 --- /dev/null +++ b/ivtest/ivltests/vhdl_test8.vhd @@ -0,0 +1,22 @@ +-- +-- Author: Pawel Szostek (pawel.szostek@cern.ch) +-- Date: 27.07.2011 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity match_bits is + port (a,b: in std_logic_vector(7 downto 0); + matches : out std_logic_vector(7 downto 0) + ); +end; + +architecture behaviour of match_bits is +begin + process(a, b) begin + for i in 7 downto 0 loop + matches(i) <= not (a(i) xor b(i)); + end loop; + end process; +end; diff --git a/ivtest/ivltests/vhdl_test9.v b/ivtest/ivltests/vhdl_test9.v new file mode 100644 index 000000000..5df11a651 --- /dev/null +++ b/ivtest/ivltests/vhdl_test9.v @@ -0,0 +1,75 @@ +// +// Author: Pawel Szostek (pawel.szostek@cern.ch) +// Date: 01.08.2011 + +`timescale 1ns/1ps +module count_ones_v(input [15:0] vec, output reg [4:0] count); + integer i; + integer result; + always @(vec) begin + result = 0; + for (i=15; i>=0; i=i-1) begin + if(vec[i] == 1'b1) begin + result = result + 1; + end + end + count = result; + end +endmodule + +module check(input [15:0] a, input [4:0] o_vhdl, input [4:0] o_verilog); + reg ena; +initial begin + ena = 0; + #10; + ena = 1; +end +always @(a)begin + #1 if (ena == 0) begin end + else if (o_vhdl !== o_verilog) begin + $display("ERROR!"); + $display("VERILOG: ", o_verilog); + $display("VHDL: ", o_vhdl); + end +end +endmodule + +module stimulus (output reg [15:0] a); + parameter S = 20000; + int unsigned i,j,k,l; + initial begin //stimulate data + for (i=0; i= 10) + inject = 1'b1; + else + inject = 1'b0; + end + endfunction +endmodule + +module main; + wire [15:0] a; + wire [4:0] o_vhdl, o_verilog; + + count_ones_v c_vhdl(a,o_vhdl); + count_ones c_verilog(a,o_verilog); + stimulus stim(a); + check c(a,o_vhdl, o_verilog); + + initial begin + #120000; + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/vhdl_test9.vhd b/ivtest/ivltests/vhdl_test9.vhd new file mode 100644 index 000000000..6e4ee02a0 --- /dev/null +++ b/ivtest/ivltests/vhdl_test9.vhd @@ -0,0 +1,27 @@ +-- +-- Author: Pawel Szostek (pawel.szostek@cern.ch) +-- Date: 27.07.2011 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity count_ones is + port ( vec: in std_logic_vector(15 downto 0); + count : out unsigned(4 downto 0)); +end; + +architecture behaviour of count_ones is +begin + process(vec) + variable result : unsigned(4 downto 0); + begin + result := to_unsigned(0, result'length); + for i in 15 downto 0 loop + if vec(i) = '1' then + result := result +1; + end if; + end loop; + count <= result; + end process; +end; diff --git a/ivtest/ivltests/vhdl_textio_read.v b/ivtest/ivltests/vhdl_textio_read.v new file mode 100644 index 000000000..c98bf34c1 --- /dev/null +++ b/ivtest/ivltests/vhdl_textio_read.v @@ -0,0 +1,45 @@ +// Copyright (c) 2015-2016 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test reading files using std.textio library. + +module vhdl_textio_read_test; +reg clk, active, ok; +int line_counter; +vhdl_textio_read dut(clk, active, line_counter, ok); + +always #1 clk = ~clk; + +initial begin + clk = 0; + active = 1; + + // wait until the input file is read + #14 active = 0; + + if(ok !== 1'b1) begin + $display("FAILED"); + $finish(); + end + + $display("PASSED"); + #0; // Need to wait for the file to close before we finish! + $finish(); +end +endmodule diff --git a/ivtest/ivltests/vhdl_textio_read.vhd b/ivtest/ivltests/vhdl_textio_read.vhd new file mode 100644 index 000000000..e17dd9db7 --- /dev/null +++ b/ivtest/ivltests/vhdl_textio_read.vhd @@ -0,0 +1,84 @@ +-- Copyright (c) 2015-2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test reading files using std.textio library. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +entity vhdl_textio_read is + port( + clk, active : in std_logic; + line_counter : out integer; + ok : out std_logic + ); +end vhdl_textio_read; + +architecture test of vhdl_textio_read is +begin + read_data: process(clk, active) + file data_file : text; + variable data_line : line; + + variable data_string : string(6 downto 1); + variable data_int, data_hex : integer; + variable data_bool : boolean; + variable data_real : real; + variable data_time : time; + variable data_logic : std_logic_vector(5 downto 0); + + begin + if rising_edge(active) then + file_open(data_file, "vhdl_textio.tmp", read_mode); + line_counter := 0; + elsif falling_edge(active) then + file_close(data_file); + end if; + + if rising_edge(clk) and active = '1' then + readline(data_file, data_line); + line_counter := line_counter + 1; + + case line_counter is + -- Test reading different variable types + when 1 => read(data_line, data_int); + when 2 => read(data_line, data_bool); + when 3 => read(data_line, data_time); + when 4 => hread(data_line, data_hex); + when 5 => read(data_line, data_real); + when 6 => read(data_line, data_string); + when 7 => + read(data_line, data_logic); + + -- Verify the read data + if data_int = 123 + and data_bool = true + and data_time = 100 s + and data_hex = x"f3" + and data_real = 12.21 + and data_string = "string" + and data_logic = "1100XZ" then + ok <= '1'; + end if; + end case; + end if; + end process; +end test; diff --git a/ivtest/ivltests/vhdl_textio_write.v b/ivtest/ivltests/vhdl_textio_write.v new file mode 100644 index 000000000..69306376b --- /dev/null +++ b/ivtest/ivltests/vhdl_textio_write.v @@ -0,0 +1,30 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test writing files using std.textio library. + +module vhdl_textio_write_test; +reg write; +vhdl_textio_write dut(write); + +initial begin + // this test is later verified by vhdl_read_textio + $display("PASSED"); +end +endmodule diff --git a/ivtest/ivltests/vhdl_textio_write.vhd b/ivtest/ivltests/vhdl_textio_write.vhd new file mode 100644 index 000000000..c3d550353 --- /dev/null +++ b/ivtest/ivltests/vhdl_textio_write.vhd @@ -0,0 +1,73 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test writing files using std.textio library. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +entity vhdl_textio_write is + port( + wr : in std_logic + ); +end vhdl_textio_write; + +architecture test of vhdl_textio_write is + +begin + write_data: process(wr) + file data_file : text open write_mode is "vhdl_textio.tmp"; + variable data_line : line; + + variable data_string : string(6 downto 1); + variable data_int, data_hex : integer; + variable data_bool : boolean; + variable data_real : real; + variable data_time : time; + variable data_vector : std_logic_vector(5 downto 0); + + begin + data_string := "string"; + data_int := 123; + data_hex := X"F3"; + data_bool := true; + data_real := 12.21; + data_time := 100 s; + data_vector := "1100XZ"; + + -- Test writing different variable types + write(data_line, data_int); + writeline(data_file, data_line); + write(data_line, data_bool); + writeline(data_file, data_line); + write(data_line, data_time); + writeline(data_file, data_line); + + hwrite(data_line, data_hex); + writeline(data_file, data_line); + write(data_line, data_real); + writeline(data_file, data_line); + write(data_line, data_string); + writeline(data_file, data_line); + write(data_line, data_vector); + writeline(data_file, data_line); + end process; +end test; diff --git a/ivtest/ivltests/vhdl_time.v b/ivtest/ivltests/vhdl_time.v new file mode 100644 index 000000000..53f50a540 --- /dev/null +++ b/ivtest/ivltests/vhdl_time.v @@ -0,0 +1,41 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for time related expressions. + +module vhdl_time_test; +logic a, b; +time tout, tin; +vhdl_time dut(a, b, tout, tin); + +always @(a) +begin + $display("a changed at %t", $realtime); +end + +initial begin + tin = 100ns; + + // Start the test + b = 1'b0; + b = 1'b1; + + $display(tout); +end +endmodule diff --git a/ivtest/ivltests/vhdl_time.vhd b/ivtest/ivltests/vhdl_time.vhd new file mode 100644 index 000000000..39531de35 --- /dev/null +++ b/ivtest/ivltests/vhdl_time.vhd @@ -0,0 +1,73 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for time related expressions. + +library ieee; +use ieee.std_logic_1164.all; +use work.time_pkg.all; + +entity vhdl_time is + port(a : out std_logic; + b : in std_logic; + tout : out time; + tin : in time); +end vhdl_time; + +architecture test of vhdl_time is + signal time_sig : time_subtype := 100 ns; +begin + tout <= 140 ns; + + process(b) + variable time_var : time; + begin + if(rising_edge(b)) then + time_var := 100 ns; + time_sig := 500 ns; + + a := '0'; + wait for 50 ns; + a := '1'; + wait for time_sig; -- signal + a := '0'; + wait for time_const; -- constant + a := '1'; + wait for time_var; -- variable + a := '0'; + + wait for (time_sig + time_const + time_var); + a := '1'; + + -- Modify variable & signal values + time_var := 10 ns; + wait for time_var; + a := '0'; + + time_sig := 20 ns; + wait for time_sig; + a := '1'; + + -- Test time read from port + wait for tin; + a := '0'; + end if; + end process; + +end test; diff --git a/ivtest/ivltests/vhdl_time_pkg.vhd b/ivtest/ivltests/vhdl_time_pkg.vhd new file mode 100644 index 000000000..15332094f --- /dev/null +++ b/ivtest/ivltests/vhdl_time_pkg.vhd @@ -0,0 +1,32 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for time related expressions. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package time_pkg is +constant time_const : time := 200 ns; +subtype time_subtype is time range 0 fs to 1 ms; +end time_pkg; + +package body time_pkg is +end time_pkg; diff --git a/ivtest/ivltests/vhdl_timescale_1ns.cfg b/ivtest/ivltests/vhdl_timescale_1ns.cfg new file mode 100644 index 000000000..4e3798de9 --- /dev/null +++ b/ivtest/ivltests/vhdl_timescale_1ns.cfg @@ -0,0 +1 @@ ++timescale+1ns/1ns diff --git a/ivtest/ivltests/vhdl_to_integer.v b/ivtest/ivltests/vhdl_to_integer.v new file mode 100644 index 000000000..48e05e299 --- /dev/null +++ b/ivtest/ivltests/vhdl_to_integer.v @@ -0,0 +1,48 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for to_integer() function. + +module to_int_test; +logic unsigned [7:0] unsign; +logic signed [7:0] sign; +to_int dut(unsign, sign); + +initial begin + unsign = 8'b11001100; + sign = 8'b11001100; + + #1; + + if(dut.s_natural !== 204) + begin + $display("FAILED 1"); + $finish(); + end + + if(dut.s_integer !== -52) + begin + $display("FAILED 2"); + $finish(); + end + + $display("PASSED"); +end +endmodule + diff --git a/ivtest/ivltests/vhdl_to_integer.vhd b/ivtest/ivltests/vhdl_to_integer.vhd new file mode 100644 index 000000000..31a19cd8e --- /dev/null +++ b/ivtest/ivltests/vhdl_to_integer.vhd @@ -0,0 +1,48 @@ +-- Copyright (c) 2014 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for to_integer() function. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity to_int is + port ( + unsign : in unsigned(7 downto 0); + sign : in signed(7 downto 0) + ); +end to_int; + +architecture test of to_int is + signal s_natural : natural; + signal s_integer : integer; +begin + +process (unsign) +begin + s_natural <= (unsign); +end process; + +process (sign) +begin + s_integer <= (sign); +end process; + +end test; diff --git a/ivtest/ivltests/vhdl_uadd23_bit.v b/ivtest/ivltests/vhdl_uadd23_bit.v new file mode 100644 index 000000000..dbace1e7a --- /dev/null +++ b/ivtest/ivltests/vhdl_uadd23_bit.v @@ -0,0 +1,52 @@ +module check (input unsigned [22:0] a, b, c); + wire unsigned [22:0] int_AB; + + assign int_AB = a + b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB != c) begin + $display("ERROR"); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [22:0] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 0; + for (i=0; i +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Unary minus operator test + +module vhdl_unary_minus_test; +logic signed [7:0] data_in; +logic signed [7:0] data_out; +logic clk = 1'b0; + +vhdl_unary_minus dut(data_in, clk, data_out); + +always #10 clk = ~clk; + +initial begin + #5; + + data_in = -12; + #20; + if(data_out !== 12) begin + $display("FAILED 1"); + $finish(); + end + + data_in = 33; + #20; + if(data_out !== -33) begin + $display("FAILED 2"); + $finish(); + end + + $display("PASSED"); + $finish(); +end + +endmodule diff --git a/ivtest/ivltests/vhdl_unary_minus.vhd b/ivtest/ivltests/vhdl_unary_minus.vhd new file mode 100644 index 000000000..882759213 --- /dev/null +++ b/ivtest/ivltests/vhdl_unary_minus.vhd @@ -0,0 +1,43 @@ +-- Copyright (c) 2016 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and-or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Unary minus operator test + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vhdl_unary_minus is + port(data_in : in signed(7 downto 0); + clk : in std_logic; + data_out : out signed(7 downto 0) + ); +end vhdl_unary_minus; + +architecture test of vhdl_unary_minus is +begin + +process(clk) +begin + if rising_edge(clk) then + data_out <= -data_in; + end if; +end process; + +end test; diff --git a/ivtest/ivltests/vhdl_unbounded.v b/ivtest/ivltests/vhdl_unbounded.v new file mode 100644 index 000000000..8a5ae6319 --- /dev/null +++ b/ivtest/ivltests/vhdl_unbounded.v @@ -0,0 +1,45 @@ +// Copyright (c) 2014 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Basic test for the unbounded arrays in VHDL. + +module vhdl_unbounded_array_test; + vhdl_unbounded_array dut(); + + initial begin + #1; // wait for signal assignment + + if(dut.sig_logic != 'b01010101) begin + $display("FAILED 1"); + $finish; + end + + if(dut.sig_integer[2] != 1) begin + $display("FAILED 2"); + $finish; + end + + if(dut.sig_real[1] != 2.5) begin + $display("FAILED 3"); + $finish; + end + + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/vhdl_unbounded.vhd b/ivtest/ivltests/vhdl_unbounded.vhd new file mode 100644 index 000000000..33cf7c91a --- /dev/null +++ b/ivtest/ivltests/vhdl_unbounded.vhd @@ -0,0 +1,42 @@ +-- Copyright (c) 2014 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Basic test for the unbounded arrays in VHDL. + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_unbounded_array is +end vhdl_unbounded_array; + +architecture test of vhdl_unbounded_array is + -- This can be translated as an unpacked array in SystemVerilog + type unb_logic is array (integer range <>) of std_logic; + -- These have to be packed arrays + type unb_integer is array (natural range <>) of integer; + type unb_real is array (integer range <>) of real; + + signal sig_logic : unb_logic(7 downto 0); + signal sig_integer : unb_integer(3 downto 0); + signal sig_real : unb_real(0 to 3); +begin + sig_logic <= "01010101"; + sig_integer(2) <= 1; + sig_real(1) <= 2.5; +end architecture test; diff --git a/ivtest/ivltests/vhdl_unbounded_func.v b/ivtest/ivltests/vhdl_unbounded_func.v new file mode 100644 index 000000000..67cf33a39 --- /dev/null +++ b/ivtest/ivltests/vhdl_unbounded_func.v @@ -0,0 +1,52 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Basic test for functions that work with unbounded vectors as return +// and param types. + +module vhdl_unbounded_func_test(); + vhdl_unbounded_func dut(); + + initial begin + #1; // wait for signal assignment + + if(dut.test_out1 != 'b1010100110) begin + $display("FAILED 1"); + $finish; + end + + if(dut.test_out2 != 'b010110) begin + $display("FAILED 2"); + $finish; + end + + if(dut.neg_test_out1 != ~dut.test_out1) begin + $display("FAILED 3"); + $finish; + end + + if(dut.neg_test_out2 != ~dut.test_out2) begin + $display("FAILED 4"); + $finish; + end + + $display("PASSED"); + end +endmodule + diff --git a/ivtest/ivltests/vhdl_unbounded_func.vhd b/ivtest/ivltests/vhdl_unbounded_func.vhd new file mode 100644 index 000000000..3997847fb --- /dev/null +++ b/ivtest/ivltests/vhdl_unbounded_func.vhd @@ -0,0 +1,60 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Basic test for functions that work with unbounded vectors as return +-- and param types. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.vhdl_unbounded_func_pkg.all; + +package included_pkg is + function negator(word_i : std_logic_vector) return std_logic_vector; +end included_pkg; + +package body included_pkg is +function negator(word_i : std_logic_vector) return std_logic_vector is + variable word_o : std_logic_vector (word_i'left downto word_i'right); +begin + for I in word_i'range loop + word_o (I) := not word_i(I); + end loop; + + return word_o; +end function; +end included_pkg; + +entity vhdl_unbounded_func is +end vhdl_unbounded_func; + +architecture test of vhdl_unbounded_func is + signal test_out1 : std_logic_vector(9 downto 0); + signal test_out2 : std_logic_vector(5 downto 0); + + signal neg_test_out1 : std_logic_vector(9 downto 0); + signal neg_test_out2 : std_logic_vector(5 downto 0); + +begin + test_out1 <= f_manch_encoder(B"11101"); + test_out2 <= f_manch_encoder(B"001"); + neg_test_out1 <= negator(test_out1); + neg_test_out2 <= negator(test_out2); +end test; + diff --git a/ivtest/ivltests/vhdl_unbounded_func_pkg.vhd b/ivtest/ivltests/vhdl_unbounded_func_pkg.vhd new file mode 100644 index 000000000..9be617e26 --- /dev/null +++ b/ivtest/ivltests/vhdl_unbounded_func_pkg.vhd @@ -0,0 +1,44 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Basic test for functions that work with unbounded vectors as return +-- and param types. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package vhdl_unbounded_func_pkg is + function f_manch_encoder (word_i :std_logic_vector) return std_logic_vector; +end vhdl_unbounded_func_pkg; + +package body vhdl_unbounded_func_pkg is + +function f_manch_encoder (word_i : std_logic_vector) return std_logic_vector is + variable word_manch_o : std_logic_vector((2*word_i'length) - 1 downto 0); +begin + for I in word_i'range loop + word_manch_o (I*2) := not word_i(I); + word_manch_o (I*2+1) := word_i(I); + end loop; + + return word_manch_o; +end function; + +end vhdl_unbounded_func_pkg; diff --git a/ivtest/ivltests/vhdl_usub23_bit.v b/ivtest/ivltests/vhdl_usub23_bit.v new file mode 100644 index 000000000..bf595b6e6 --- /dev/null +++ b/ivtest/ivltests/vhdl_usub23_bit.v @@ -0,0 +1,55 @@ +module check (input unsigned [22:0] a, b, c); + wire unsigned [22:0] int_AB; + + assign int_AB = a - b; + +always @(a, b, int_AB, c) begin + #1; + if (int_AB != c) begin + $display("ERROR"); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [22:0] A, B); + parameter MAX = 1 << 23; + parameter S = 10000; + int unsigned i; + + + initial begin + A = 0; B= 0; + for (i=0; i +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for variable initialization. + +module vhdl_var_init_test; +logic init; +logic [7:0] slv; +bit b; +int i; +vhdl_var_init dut(init, slv, b, i); + +initial begin + init = 0; + #1 init = 1; + #1; + + if(slv !== 8'b01000010) begin + $display("FAILED 1"); + $finish(); + end + + if(b !== false) begin + $display("FAILED 2"); + $finish(); + end + + if(i !== 42) begin + $display("FAILED 3"); + $finish(); + end + + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/vhdl_var_init.vhd b/ivtest/ivltests/vhdl_var_init.vhd new file mode 100644 index 000000000..acc6ecfb7 --- /dev/null +++ b/ivtest/ivltests/vhdl_var_init.vhd @@ -0,0 +1,48 @@ +-- Copyright (c) 2015 CERN +-- @author Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test for variable initialization. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vhdl_var_init is + port(init : in std_logic; + slv : out std_logic_vector(7 downto 0); + bool : out boolean; + i : out integer + ); +end vhdl_var_init; + +architecture test of vhdl_var_init is + +begin + process(init) + variable var_slv : std_logic_vector(7 downto 0) := "01000010"; + variable var_bool : boolean := false; + variable var_int : integer := 42; + begin + if rising_edge(init) then + slv <= var_slv; + bool <= var_bool; + i <= var_int; + end if; + end process; +end test; diff --git a/ivtest/ivltests/vhdl_wait.v b/ivtest/ivltests/vhdl_wait.v new file mode 100644 index 000000000..2336a30fd --- /dev/null +++ b/ivtest/ivltests/vhdl_wait.v @@ -0,0 +1,41 @@ +// Copyright (c) 2015 CERN +// @author Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// 'wait on' & 'wait until' test + +module vhdl_wait_test; +logic [1:0] a, b; +vhdl_wait dut(a, b); + +always @(posedge b[0]) begin + $display("wait 1 acknowledged"); + // complete "wait 2" + a[1] = 1'b0; +end + +always @(posedge b[1]) begin + $display("wait 2 acknowledged"); +end + +initial begin + // complete "wait 1" + a = 2'b00; +end + +endmodule diff --git a/ivtest/ivltests/vhdl_wait.vhd b/ivtest/ivltests/vhdl_wait.vhd new file mode 100644 index 000000000..84f3051a5 --- /dev/null +++ b/ivtest/ivltests/vhdl_wait.vhd @@ -0,0 +1,51 @@ +-- Copyright (c) 2015 CERN +-- @author Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- 'wait on' & 'wait until' test + +library ieee; +use ieee.std_logic_1164.all; + +entity vhdl_wait is + port(a : in std_logic_vector(1 downto 0); + b : out std_logic_vector(1 downto 0)); +end vhdl_wait; + +architecture test of vhdl_wait is +begin + process begin + report "final wait test"; + wait; + end process; + + process begin + wait on a(0); + report "wait 1 completed"; + -- acknowledge wait 1 + b(0) <= '1'; + end process; + + process begin + wait until(a(1) = '1' and a(1)'event); + report "wait 2 completed"; + -- acknowledge wait 2 + b(1) <= '1'; + end process; +end test; + diff --git a/ivtest/ivltests/vhdl_while.v b/ivtest/ivltests/vhdl_while.v new file mode 100644 index 000000000..fb64e7818 --- /dev/null +++ b/ivtest/ivltests/vhdl_while.v @@ -0,0 +1,39 @@ +// Copyright (c) 2015 CERN +// Maciej Suminski +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test while loops in VHDL. + +module vhdl_while_test; +logic start; +int out; +vhdl_while dut(start, out); + +initial begin + start = 1; + #1; + + if(out !== 10) begin + $display("FAILED"); + $finish(); + end + + $display("PASSED"); +end +endmodule + diff --git a/ivtest/ivltests/vhdl_while.vhd b/ivtest/ivltests/vhdl_while.vhd new file mode 100644 index 000000000..35905076c --- /dev/null +++ b/ivtest/ivltests/vhdl_while.vhd @@ -0,0 +1,45 @@ +-- Copyright (c) 2015 CERN +-- Maciej Suminski +-- +-- This source code is free software; you can redistribute it +-- and/or modify it in source code form under the terms of the GNU +-- General Public License as published by the Free Software +-- Foundation; either version 2 of the License, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +-- Test while loops in VHDL. + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity vhdl_while is + port( + start: in std_logic; + output: out integer + ); +end vhdl_while; + +architecture test of vhdl_while is +begin + process(start) + variable a : integer := 0; + begin + if(rising_edge(start)) then + while (a < 10) loop + a := a + 1; + end loop; + output <= a; + end if; + end process; +end test; diff --git a/ivtest/ivltests/vhdl_xnor104_stdlogic.v b/ivtest/ivltests/vhdl_xnor104_stdlogic.v new file mode 100644 index 000000000..64f3c2d97 --- /dev/null +++ b/ivtest/ivltests/vhdl_xnor104_stdlogic.v @@ -0,0 +1,82 @@ +module check (input unsigned [103:0] a, b, c); + wire [103:0] int_AB; + + assign int_AB = ~(a ^ b); + +always @(a, b, int_AB, c) begin + #1; + if (int_AB !== c) begin + $display("ERROR"); + $finish; + end +end + +endmodule + +module stimulus (output reg unsigned [103:0] A, B); + parameter S = 2000; + int unsigned i; + + + initial begin + A = 0; B= 0; + // values with 0, 1 + for (i=0; i +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +// Test for vvp_net_fun_t::recv_vec4_pv() implementation (vvp). + +module vvp_recv_vec4_pv (input wire logic clk, input wire logic inp, + output wire logic[16:0] arr_out); +logic[16:0] arr; + +always begin + arr[15:0] <= arr[16:1]; + @(clk); wait(clk == 1'b1); +end + +assign arr[16] = inp; +assign arr_out = arr; + +endmodule + + +module vvp_recv_vec4_pv_test; +logic clk, inp; +logic [16:0] arr, src; +vvp_recv_vec4_pv dut(clk, inp, arr); + +always #5 clk <= ~clk; + +initial begin + int i; + + src <= 17'b01101110010011011; + clk <= 1'b1; + #5; + + for(i = 0; i < 17; i = i + 1) begin + #10 inp = src[i]; + end + + #5; // wait for the last assignment occuring in the for loop above + + if(arr !== src) begin + $display("FAILED"); + end else begin + $display("PASSED"); + end + + $finish(); +end + +endmodule + diff --git a/ivtest/ivltests/vvp_scalar_value.v b/ivtest/ivltests/vvp_scalar_value.v new file mode 100644 index 000000000..65c6feca2 --- /dev/null +++ b/ivtest/ivltests/vvp_scalar_value.v @@ -0,0 +1,45 @@ +module vvp_scalar_value(); + +reg [2:0] v1; +reg [2:0] v2; + +wire [2:0] w1; +wire [2:0] w2; +wire [2:0] w3; + +assign ( highz1, strong0) w1 = v1; +assign (strong1, highz0) w2 = v1; + +assign ( highz1, strong0) w3 = v1; +assign (strong1, highz0) w3 = v2; + +reg failed; + +initial begin + failed = 0; + + v1 = 3'bz10; #1; + $display("%b %v %v %v", w1, w1[2], w1[1], w1[0]); + if (w1 !== 3'bzz0) failed = 1; + $display("%b %v %v %v", w2, w2[2], w2[1], w2[0]); + if (w2 !== 3'bz1z) failed = 1; + + v2 = 3'b000; #1; + $display("%b %v %v %v", w3, w3[2], w3[1], w3[0]); + if (w3 !== 3'bzz0) failed = 1; + + v2 = 3'b111; #1; + $display("%b %v %v %v", w3, w3[2], w3[1], w3[0]); + if (w3 !== 3'b11x) failed = 1; + + v2 = 3'bzzz; #1; + $display("%b %v %v %v", w3, w3[2], w3[1], w3[0]); + if (w3 !== 3'bzz0) failed = 1; + + if (failed) + $display("FAILED"); + else + $display("PASSED"); +end + +endmodule diff --git a/ivtest/ivltests/wait1.v b/ivtest/ivltests/wait1.v new file mode 100644 index 000000000..4ac963d57 --- /dev/null +++ b/ivtest/ivltests/wait1.v @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +module main; + + reg foo = 0; + + initial #10 foo = 1; + + initial #1 begin + if (foo !== 1'b0) begin + $display("FAILED -- foo before wait is %b", foo); + $finish; + end + + // This wait without a statement has caused a few bugs. + wait (foo) ; + + if (foo !== 1'b1) begin + $display("FAILED -- foo after wait is %b", foo); + $finish; + end + + if ($time != 10) begin + $display("FAILED -- $time after wait is %t", $time); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/wait2.v b/ivtest/ivltests/wait2.v new file mode 100644 index 000000000..6f45479ee --- /dev/null +++ b/ivtest/ivltests/wait2.v @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +module main; + + reg foo = 1'bx; + + initial #10 foo = 1; + + initial #1 begin + if (foo !== 1'bx) begin + $display("FAILED -- foo before wait is %b", foo); + $finish; + end + + // This wait without a statement has caused a few bugs. + wait (foo) ; + + if (foo !== 1'b1) begin + $display("FAILED -- foo after wait is %b", foo); + $finish; + end + + if ($time != 10) begin + $display("FAILED -- $time after wait is %t", $time); + $finish; + end + + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/wait3.v b/ivtest/ivltests/wait3.v new file mode 100644 index 000000000..c146265a1 --- /dev/null +++ b/ivtest/ivltests/wait3.v @@ -0,0 +1,56 @@ +/* + * this test attempts to show a problem with the waits. This skip + * and skip2 modules should have identical behavior. + */ + +module skip(r,a); +input r; +output a; +wire r; +reg a; +initial + a=0; +always begin + wait(r); + #1 a=1; + wait(!r); + #1 a=0; +end +endmodule + +module skip2(r,a); +input r; +output a; +wire r; +reg a; +initial + a=0; +always @ (r or a) begin + case ({r,a}) + 00: ; // idle + 10: #1 a=1; + 11: ; // idle + 01: #1 a=0; + endcase +end +endmodule + +module test; +reg r1; +wire a1; +reg clk; +// skip2 skip1(r1,a1); // simulates as expected +skip skip1(r1,a1); // simulation hangs + +always #50 clk= !clk; + +initial begin + $monitor($time," ",r1,a1); + $display("starting"); + #100 r1=0; + #100 r1=1; + wait(a1); + #100 r1=0; + #1000 $display("timeout"); $finish(0); +end +endmodule diff --git a/ivtest/ivltests/wait_fork.v b/ivtest/ivltests/wait_fork.v new file mode 100644 index 000000000..670439630 --- /dev/null +++ b/ivtest/ivltests/wait_fork.v @@ -0,0 +1,31 @@ +module top; + reg [4:1] res; + reg pass; + + initial begin + pass = 1'b1; + res = 4'b0000; + fork + #3 res[3] = 1'b1; + #4 res[4] = 1'b1; + join_none + + fork + #1 res[1] = 1'b1; + #2 res[2] = 1'b1; + join_any + + if (res != 4'b0001) begin + $display("Error: Only first process should have run: %b", res); + pass = 1'b0; + end + + wait fork; + if (res != 4'b1111) begin + $display("Error: All processes should have run: %b", res); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/warn_opt_sys_tf.v b/ivtest/ivltests/warn_opt_sys_tf.v new file mode 100644 index 000000000..08281fc7a --- /dev/null +++ b/ivtest/ivltests/warn_opt_sys_tf.v @@ -0,0 +1,25 @@ +// This will not generate a RE if these are calling the correct warning. +module top; + integer res; + + initial begin + // $countdrivers is now implemented + res = $getpattern; + $input; + $key; + $nokey; + $list; + $log; + $nolog; + $save; + $restart; + $incsave; + res = $scale; + $scope; + $showscopes; + $showvars; + $sreadmemb; + $sreadmemh; + $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/when_else.vhd b/ivtest/ivltests/when_else.vhd new file mode 100644 index 000000000..af5c3be5a --- /dev/null +++ b/ivtest/ivltests/when_else.vhd @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity foo_entity is + + port( + data_i : in std_logic_vector(1 downto 0); + data_o, data_o2, data_o3 : out std_logic_vector(3 downto 0) + ); + +end foo_entity; + +architecture behaviour of foo_entity is + +begin + + data_o <= "0001" when ( data_i="00" ) else + "0010" when ( data_i="01" ) else + "0100" when ( data_i="10" ) else + "1000"; + + -- test cases without the final 'else' statement + data_o2 <= "0101" when ( data_i="01" ); + + data_o3 <= "1100" when ( data_i="10" ) else + "0011" when ( data_i="01" ); + +end behaviour; diff --git a/ivtest/ivltests/width.v b/ivtest/ivltests/width.v new file mode 100644 index 000000000..ee2c85529 --- /dev/null +++ b/ivtest/ivltests/width.v @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2000 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg [7:0] a; + reg [6:-1] b; + + initial begin + a = 1; + b = 2; + if (a !== 8'h01) begin + $display("FAILED -- to initialize a: %b", a); + $finish; + end + + if (b !== 8'h02) begin + $display("FAILED -- to initialize b: %b", b); + $finish; + end + + b = a; + if (b !== 8'h01) begin + $display("FAILED -- to copy a to b: %b", b); + $finish; + end + + $display("PASSED"); + end // initial begin +endmodule // main diff --git a/ivtest/ivltests/wild_cmp_const.v b/ivtest/ivltests/wild_cmp_const.v new file mode 100644 index 000000000..2c3468dd5 --- /dev/null +++ b/ivtest/ivltests/wild_cmp_const.v @@ -0,0 +1,190 @@ +module top; + parameter weq1 = 2'b01 ==? 2'b01; + parameter weq2 = 2'b01 ==? 2'b00; + parameter weq3 = 2'b0x ==? 2'b00; + parameter weq4 = 2'b00 ==? 2'b0x; + parameter weq5 = 2'b01 ==? 2'b0x; + parameter weq6 = 2'b0z ==? 2'b0x; + parameter weq7 = 2'b0x ==? 2'b0x; + parameter weq8 = 2'b00 ==? 2'b0z; + parameter weq9 = 2'b01 ==? 2'b0z; + parameter weqa = 2'b0z ==? 2'b0z; + parameter weqb = 2'b0x ==? 2'b0z; + parameter weqc = 2'bx0 ==? 2'b00; + parameter weqd = 2'bx1 ==? 2'b00; + parameter weqe = 2'b1x ==? 2'b00; + parameter weqf = 3'b100 ==? 2'b00; + parameter wneq1 = 2'b01 !=? 2'b01; + parameter wneq2 = 2'b01 !=? 2'b00; + parameter wneq3 = 2'b0x !=? 2'b00; + parameter wneq4 = 2'b00 !=? 2'b0x; + parameter wneq5 = 2'b01 !=? 2'b0x; + parameter wneq6 = 2'b0z !=? 2'b0x; + parameter wneq7 = 2'b0x !=? 2'b0x; + parameter wneq8 = 2'b00 !=? 2'b0z; + parameter wneq9 = 2'b01 !=? 2'b0z; + parameter wneqa = 2'b0z !=? 2'b0z; + parameter wneqb = 2'b0x !=? 2'b0z; + parameter wneqc = 2'bx0 !=? 2'b00; + parameter wneqd = 2'bx1 !=? 2'b00; + parameter wneqe = 2'b1x !=? 2'b00; + parameter wneqf = 3'b100 !=? 2'b00; + + reg pass; + + initial begin + pass = 1'b1; + + if (weq1 !== 1'b1) begin + $display("Failed: parameter 2'b01 ==? 2'b01 returned 1'b%b not 1'b1", weq1); + pass = 1'b0; + end + + if (weq2 !== 1'b0) begin + $display("Failed: parameter 2'b01 ==? 2'b00 returned 1'b%b not 1'b0", weq2); + pass = 1'b0; + end + + if (weq3 !== 1'bx) begin + $display("Failed: parameter 2'b0x ==? 2'b00 returned 1'b%b not 1'bx", weq3); + pass = 1'b0; + end + + if (weq4 !== 1'b1) begin + $display("Failed: parameter 2'b00 ==? 2'b0x returned 1'b%b not 1'b1", weq4); + pass = 1'b0; + end + + if (weq5 !== 1'b1) begin + $display("Failed: parameter 2'b01 ==? 2'b0x returned 1'b%b not 1'b1", weq5); + pass = 1'b0; + end + + if (weq6 !== 1'b1) begin + $display("Failed: parameter 2'b0x ==? 2'b0x returned 1'b%b not 1'b1", weq6); + pass = 1'b0; + end + + if (weq7 !== 1'b1) begin + $display("Failed: parameter 2'b0z ==? 2'b0x returned 1'b%b not 1'b1", weq7); + pass = 1'b0; + end + + if (weq8 !== 1'b1) begin + $display("Failed: parameter 2'b00 ==? 2'b0z returned 1'b%b not 1'b1", weq8); + pass = 1'b0; + end + + if (weq9 !== 1'b1) begin + $display("Failed: parameter 2'b01 ==? 2'b0z returned 1'b%b not 1'b1", weq9); + pass = 1'b0; + end + + if (weqa !== 1'b1) begin + $display("Failed: parameter 2'b0x ==? 2'b0z returned 1'b%b not 1'b1", weqa); + pass = 1'b0; + end + + if (weqb !== 1'b1) begin + $display("Failed: parameter 2'b0z ==? 2'b0z returned 1'b%b not 1'b1", weqb); + pass = 1'b0; + end + + if (weqc !== 1'bx) begin + $display("Failed: parameter 2'bx0 ==? 2'b00 returned 1'b%b not 1'bx", weqc); + pass = 1'b0; + end + + if (weqd !== 1'b0) begin + $display("Failed: parameter 2'bx1 ==? 2'b00 returned 1'b%b not 1'b0", weqd); + pass = 1'b0; + end + + if (weqe !== 1'b0) begin + $display("Failed: parameter 2'b1x ==? 2'b00 returned 1'b%b not 1'b0", weqe); + pass = 1'b0; + end + + if (weqf !== 1'b0) begin + $display("Failed: parameter 3'b100 ==? 2'b00 returned 1'b%b not 1'b0", weqf); + pass = 1'b0; + end + + if (wneq1 !== 1'b0) begin + $display("Failed: parameter 2'b01 !=? 2'b01 returned 1'b%b not 1'b0", wneq1); + pass = 1'b0; + end + + if (wneq2 !== 1'b1) begin + $display("Failed: parameter 2'b01 !=? 2'b00 returned 1'b%b not 1'b1", wneq2); + pass = 1'b0; + end + + if (wneq3 !== 1'bx) begin + $display("Failed: parameter 2'b0x !=? 2'b00 returned 1'b%b not 1'bx", wneq3); + pass = 1'b0; + end + + if (wneq4 !== 1'b0) begin + $display("Failed: parameter 2'b00 !=? 2'b0x returned 1'b%b not 1'b0", wneq4); + pass = 1'b0; + end + + if (wneq5 !== 1'b0) begin + $display("Failed: parameter 2'b01 !=? 2'b0x returned 1'b%b not 1'b0", wneq5); + pass = 1'b0; + end + + if (wneq6 !== 1'b0) begin + $display("Failed: parameter 2'b0x !=? 2'b0x returned 1'b%b not 1'b0", wneq6); + pass = 1'b0; + end + + if (wneq7 !== 1'b0) begin + $display("Failed: parameter 2'b0z !=? 2'b0x returned 1'b%b not 1'b0", wneq7); + pass = 1'b0; + end + + if (wneq8 !== 1'b0) begin + $display("Failed: parameter 2'b00 !=? 2'b0z returned 1'b%b not 1'b0", wneq8); + pass = 1'b0; + end + + if (wneq9 !== 1'b0) begin + $display("Failed: parameter 2'b01 !=? 2'b0z returned 1'b%b not 1'b0", wneq9); + pass = 1'b0; + end + + if (wneqa !== 1'b0) begin + $display("Failed: parameter 2'b0x !=? 2'b0z returned 1'b%b not 1'b0", wneqa); + pass = 1'b0; + end + + if (wneqb !== 1'b0) begin + $display("Failed: parameter 2'b0z !=? 2'b0z returned 1'b%b not 1'b0", wneqb); + pass = 1'b0; + end + + if (wneqc !== 1'bx) begin + $display("Failed: parameter 2'bx0 !=? 2'b00 returned 1'b%b not 1'bx", wneqc); + pass = 1'b0; + end + + if (wneqd !== 1'b1) begin + $display("Failed: parameter 2'bx1 !=? 2'b00 returned 1'b%b not 1'b1", wneqd); + pass = 1'b0; + end + + if (wneqe !== 1'b1) begin + $display("Failed: parameter 2'b1x !=? 2'b00 returned 1'b%b not 1'b1", wneqe); + pass = 1'b0; + end + + if (wneqf !== 1'b1) begin + $display("Failed: parameter 3'b100 !=? 2'b00 returned 1'b%b not 1'b1", wneqf); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/wild_cmp_err.v b/ivtest/ivltests/wild_cmp_err.v new file mode 100644 index 000000000..cc6862e26 --- /dev/null +++ b/ivtest/ivltests/wild_cmp_err.v @@ -0,0 +1,10 @@ +module top; + parameter weq1 = 2'b01 ==? 0.0; + parameter weq2 = 0.0 ==? 2'b01; + parameter wneq1 = 2'b01 !=? 0.0; + parameter wneq2 = 0.0 !=? 2'b01; + + initial begin + $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/wild_cmp_err2.v b/ivtest/ivltests/wild_cmp_err2.v new file mode 100644 index 000000000..ddcf06ad0 --- /dev/null +++ b/ivtest/ivltests/wild_cmp_err2.v @@ -0,0 +1,29 @@ +module top; + reg [1:0] lv, rv; + real rl; + reg res; + string st; + + wire r1, r2, r3, r4, r5, r6, r7, r8; + + assign r1 = rl ==? rv; + assign r2 = lv ==? rl; + assign r3 = rl !=? rv; + assign r4 = lv !=? rl; + assign r1 = st ==? rv; + assign r2 = lv ==? st; + assign r3 = st !=? rv; + assign r4 = lv !=? st; + + initial begin + res = rl ==? rv; + res = lv ==? rl; + res = rl !=? rv; + res = lv !=? rl; + res = st ==? rv; + res = lv ==? st; + res = st !=? rv; + res = lv !=? st; + $display("FAILED"); + end +endmodule diff --git a/ivtest/ivltests/wild_cmp_net.v b/ivtest/ivltests/wild_cmp_net.v new file mode 100644 index 000000000..e2c506291 --- /dev/null +++ b/ivtest/ivltests/wild_cmp_net.v @@ -0,0 +1,131 @@ +module top; + reg [1:0] lv, rv; + reg pass; + wire res, resb; + + assign res = lv ==? rv; + assign resb = lv !=? rv; + + initial begin + pass = 1'b1; + + lv = 2'b00; + rv = 2'b00; + #1; + if (res !== 1'b1) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res); + pass = 1'b0; + end + + if (resb !== 1'b0) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, resb); + pass = 1'b0; + end + + #1; + lv = 2'b00; + rv = 2'b01; + #1; + if (res !== 1'b0) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res); + pass = 1'b0; + end + if (resb !== 1'b1) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, resb); + pass = 1'b0; + end + + #1; + lv = 2'b10; + rv = 2'b00; + #1; + if (res !== 1'b0) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res); + pass = 1'b0; + end + if (resb !== 1'b1) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, resb); + pass = 1'b0; + end + + #1; + lv = 2'b1x; + rv = 2'b00; + #1; + if (res !== 1'b0) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res); + pass = 1'b0; + end + if (resb !== 1'b1) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, resb); + pass = 1'b0; + end + + #1; + lv = 2'b0x; + rv = 2'b00; + #1; + if (res !== 1'bx) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'bx", lv, rv, res); + pass = 1'b0; + end + if (resb !== 1'bx) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'bx", lv, rv, resb); + pass = 1'b0; + end + + #1; + lv = 2'b00; + rv = 2'b0x; + #1; + if (res !== 1'b1) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res); + pass = 1'b0; + end + if (resb !== 1'b0) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, resb); + pass = 1'b0; + end + + #1; + lv = 2'b01; + rv = 2'b0x; + #1; + if (res !== 1'b1) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res); + pass = 1'b0; + end + if (resb !== 1'b0) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, resb); + pass = 1'b0; + end + + #1; + lv = 2'b0z; + rv = 2'b0x; + #1; + if (res !== 1'b1) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res); + pass = 1'b0; + end + if (resb !== 1'b0) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, resb); + pass = 1'b0; + end + + #1; + lv = 2'b0x; + rv = 2'b0x; + #1; + if (res !== 1'b1) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res); + pass = 1'b0; + end + if (resb !== 1'b0) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, resb); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/wild_cmp_var.v b/ivtest/ivltests/wild_cmp_var.v new file mode 100644 index 000000000..5514f17a1 --- /dev/null +++ b/ivtest/ivltests/wild_cmp_var.v @@ -0,0 +1,176 @@ +module top; + reg [1:0] lv, rv; + reg res, pass; + + initial begin + pass = 1'b1; + + lv = 2'b00; + rv = 2'b00; + res = lv ==? rv; + if (res !== 1'b1) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b00; + rv = 2'b01; + res = lv ==? rv; + if (res !== 1'b0) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b10; + rv = 2'b00; + res = lv ==? rv; + if (res !== 1'b0) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b1x; + rv = 2'b00; + res = lv ==? rv; + if (res !== 1'b0) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b0x; + rv = 2'b00; + res = lv ==? rv; + if (res !== 1'bx) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'bx", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b00; + rv = 2'b0x; + res = lv ==? rv; + if (res !== 1'b1) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b01; + rv = 2'b0x; + res = lv ==? rv; + if (res !== 1'b1) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b0z; + rv = 2'b0x; + res = lv ==? rv; + if (res !== 1'b1) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b0x; + rv = 2'b0x; + res = lv ==? rv; + if (res !== 1'b1) begin + $display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b00; + rv = 2'b00; + res = lv !=? rv; + if (res !== 1'b0) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b00; + rv = 2'b01; + res = lv !=? rv; + if (res !== 1'b1) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b10; + rv = 2'b00; + res = lv !=? rv; + if (res !== 1'b1) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b1x; + rv = 2'b00; + res = lv !=? rv; + if (res !== 1'b1) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b0x; + rv = 2'b00; + res = lv !=? rv; + if (res !== 1'bx) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'bx", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b00; + rv = 2'b0x; + res = lv !=? rv; + if (res !== 1'b0) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b01; + rv = 2'b0x; + res = lv !=? rv; + if (res !== 1'b0) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b0z; + rv = 2'b0x; + res = lv !=? rv; + if (res !== 1'b0) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b0x; + rv = 2'b0x; + res = lv !=? rv; + if (res !== 1'b0) begin + $display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, res); + pass = 1'b0; + end + + // Check in a few other contexts. + + lv = 2'b01; + rv = 2'b0x; + res = (lv ==? rv) ? 1'b1 : 1'b0; + if (res !== 1'b1) begin + $display("Failed: %b ==? %b (ternary) returned 1'b%b not 1'b1", lv, rv, res); + pass = 1'b0; + end + + if (lv !=? rv) begin + $display("Failed: %b ==? %b (if) returned 1'b%b not 1'b1", lv, rv, res); + pass = 1'b0; + end + + lv = 2'b00; + while (lv ==? rv) lv += 2'b01; + if (lv !== 2'b10) begin + $display("Failed: %b ==? %b (while) expected lv to be 2'b10", lv, rv); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule diff --git a/ivtest/ivltests/wildsense.v b/ivtest/ivltests/wildsense.v new file mode 100644 index 000000000..127371677 --- /dev/null +++ b/ivtest/ivltests/wildsense.v @@ -0,0 +1,63 @@ +// Copyright (c) 2000 Steve Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +// SDW: Try the always @ * construct from Verilog 2000 LRM spec + +module test; + + +// +// Define a procedural assignment based mux. +// +reg [1:0] sel; +reg [1:0] out, a,b,c,d; +reg error; + +always @ * + case (sel) + 2'b00: out = a; + 2'b01: out = b; + 2'b10: out = c; + 2'b11: out = d; + endcase + +initial + begin + error = 0; + #1 ; + sel = 0; + a = 0; + #1; + if(out !== 2'b00) + begin + $display("FAILED - Wildcard sensitivy list a != 0(1)"); + error =1; + end + #1; + a = 1; + #1; + if(out !== 2'b01) + begin + $display("FAILED - Wildcard sensitivity list a != 1 (2)"); + error =1; + end + if(error == 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/wildsense2.v b/ivtest/ivltests/wildsense2.v new file mode 100644 index 000000000..b86bb347d --- /dev/null +++ b/ivtest/ivltests/wildsense2.v @@ -0,0 +1,55 @@ +module main; + + reg [2:0] ADDR; + wire [1:0] data0 = 0, data1 = 1, data2 = 2, data3 = 3; + + reg [1:0] data; + always @* + case (ADDR[2:0]) + 3'b000: data = data0; + 3'b001: data = data1; + 3'b010: data = data2; + 3'b011: data = data3; + default: data = 0; + endcase // case(ADDR[2:0]) + + initial begin + ADDR = 0; + #1 $display("data=%b", data); + if (data !== ADDR) begin + $display("FAILED"); + $finish; + end + + ADDR = 1; + #1 $display("data=%b", data); + if (data !== ADDR) begin + $display("FAILED"); + $finish; + end + + ADDR = 2; + #1 $display("data=%b", data); + if (data !== ADDR) begin + $display("FAILED"); + $finish; + end + + ADDR = 3; + #1 $display("data=%b", data); + if (data !== ADDR) begin + $display("FAILED"); + $finish; + end + + ADDR = 4; + #1 $display("data=%b", data); + if (data !== 0)begin + $display("FAILED"); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/ivltests/wireadd1.v b/ivtest/ivltests/wireadd1.v new file mode 100644 index 000000000..79ebfa71b --- /dev/null +++ b/ivtest/ivltests/wireadd1.v @@ -0,0 +1,59 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous adds in assignment..dependent on always + working +// +// $Log: wireadd1.v,v $ +// Revision 1.2 2001/05/03 05:45:37 ka6s +// Lets try this again +// +// + + +module main; + +reg globvar; + +reg [3:0] var1,var2,var3; +wire [3:0] var3a; +reg error; + +assign var3a = var1 + var2; + +always @( var1 or var2) + var3 = var1 + var2 ; + +initial +begin +error = 0; +for ( var1 = 4'b0; var1 != 4'hf; var1 = var1 + 1) + for ( var2 = 4'b0; var2 != 4'hf; var2 = var2 + 1) + begin + #1 ; + if(var3 !== var3a) + error = 1; + #1; + end +if(error == 0) + $display("PASSED"); +else + $display("FAILED"); + +end + +endmodule // main diff --git a/ivtest/ivltests/wireeq.v b/ivtest/ivltests/wireeq.v new file mode 100644 index 000000000..29ea0a147 --- /dev/null +++ b/ivtest/ivltests/wireeq.v @@ -0,0 +1,62 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous <= in assignment. +// + + +module main; + +reg globvar; + +reg [3:0] var1; +reg error; + +wire var2 = (var1 == 4'h02); + +initial + begin + error = 0; + var1 = 4'h0 ; + #1 ; + if(var2 != 1'b0) + begin + $display("FAILED continuous <= logical op (1)"); + error = 1; + end + #1 ; + var1 = 4'h2; + #1 ; + if(var2 != 1'b1) + begin + $display("FAILED continuos <= logical op (2)"); + error = 1; + end + #1 ; + var1 = 4'h4; + #1 ; + if(var2 != 1'b0) + begin + $display("FAILED continuos <= logical op (3)"); + error = 1; + end + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/wirege.v b/ivtest/ivltests/wirege.v new file mode 100644 index 000000000..dbe55ed72 --- /dev/null +++ b/ivtest/ivltests/wirege.v @@ -0,0 +1,62 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous <= in assignment. +// + + +module main; + +reg globvar; + +reg [3:0] var1; +reg error; + +wire var2 = (4'h02 >= var1); + +initial + begin + error = 0; + var1 = 4'h0 ; + #1 ; + if(var2 !== 1'b1) + begin + $display("FAILED continuous >= logical op (1)"); + error = 1; + end + #1 ; + var1 = 4'h2; + #1 ; + if(var2 !== 1'b1) + begin + $display("FAILED continuos <= logical op (2)"); + error = 1; + end + #1 ; + var1 = 4'h4; + #1 ; + if(var2 !== 1'b0) + begin + $display("FAILED continuos <= logical op (3)"); + error = 1; + end + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/wireland.v b/ivtest/ivltests/wireland.v new file mode 100644 index 000000000..717569fd4 --- /dev/null +++ b/ivtest/ivltests/wireland.v @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2000 Peter monta (pmonta@pacbell.net) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +// Reworked slightly to be self checking. +module main; + + wire y; + reg a,b; + reg error; + + assign y = a && (b ? 0 : 1); + + initial + begin + error = 0; + #1 ; // get passed the time 0 race problems ;-) + b = 1; + a = 1; + #1 ; + if(y !== 0) + begin + $display("FAILED"); + error = 1; + end + #1 ; + b = 0; + #1 ; + if(y !== 1) + begin + $display("FAILED"); + error = 1; + end + if(error === 0) + $display("PASSED"); + end + +endmodule diff --git a/ivtest/ivltests/wirele.v b/ivtest/ivltests/wirele.v new file mode 100644 index 000000000..d07f41916 --- /dev/null +++ b/ivtest/ivltests/wirele.v @@ -0,0 +1,62 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous <= in assignment. +// + + +module main; + +reg globvar; + +reg [3:0] var1; +reg error; + +wire var2 = (var1 <= 4'h02); + +initial + begin + error = 0; + var1 = 4'h0 ; + #1 ; + if(var2 !== 1'b1) + begin + $display("FAILED continuous <= logical op (1)"); + error = 1; + end + #1 ; + var1 = 4'h2; + #1 ; + if(var2 !== 1'b1) + begin + $display("FAILED continuos <= logical op (2)"); + error = 1; + end + #1 ; + var1 = 4'h4; + #1 ; + if(var2 !== 1'b0) + begin + $display("FAILED continuos <= logical op (3)"); + error = 1; + end + if(error == 0) + $display("PASSED"); + end + +endmodule // main diff --git a/ivtest/ivltests/wiremod1.v b/ivtest/ivltests/wiremod1.v new file mode 100644 index 000000000..2284324f1 --- /dev/null +++ b/ivtest/ivltests/wiremod1.v @@ -0,0 +1,54 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous % in assignment..dependent on always % working +// + + +module main; + +reg globvar; + +reg [3:0] var1,var2,var3; +wire [3:0] var3a; +reg error; + +assign var3a = var1 % var2; + +always @( var1 or var2) + var3 = var1 % var2 ; + +initial +begin +for ( var1 = 4'b0; var1 != 4'hf; var1 = var1 + 1) + for ( var2 = 4'b0; var2 != 4'hf; var2 = var2 + 1) + begin + error = 0; + #1 ; + if(var3 != var3a) + begin + $display("FAILED continuous 1=%h,2=%h,3=%h,3a=%h", + var1,var2,var3,var3a); + error = 1; + end + #1; + end +if(error == 0) + $display("PASSED"); +end +endmodule // main diff --git a/ivtest/ivltests/wiresl.v b/ivtest/ivltests/wiresl.v new file mode 100644 index 000000000..568c84348 --- /dev/null +++ b/ivtest/ivltests/wiresl.v @@ -0,0 +1,55 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous << in assignment..dependent on always << working +// + + +module main; + +reg globvar; + +reg [3:0] var1,var2,var3; +wire [3:0] var3a; +reg error; + +assign var3a = var1 << var2; + +always @( var1 or var2) + var3 = var1 << var2 ; + +initial +begin +error = 0; +for ( var1 = 4'b0; var1 != 4'hf; var1 = var1 + 1) + for ( var2 = 4'b0; var2 != 4'hf; var2 = var2 + 1) + begin + #1 ; + if(var3 != var3a) + begin + $display("FAILED continous << 1=%h,2=%h,3=%h,3a=%h", + var1,var2,var3,var3a); + error = 1; + end + #1; + end +if(error == 0) + $display("PASSED"); +end + +endmodule // main diff --git a/ivtest/ivltests/wiresl2.v b/ivtest/ivltests/wiresl2.v new file mode 100644 index 000000000..3dead6c97 --- /dev/null +++ b/ivtest/ivltests/wiresl2.v @@ -0,0 +1,60 @@ +`begin_keywords "1364-2005" +/* + * This test is from PR#193 + */ + +/* test:tshl + Compilation fails with vvp from icarus verilog-20010616 snapshot + +$ iverilog -t vvp tshl.v +ivl: eval_expr.c:418: draw_binary_expr_ls: Assertion `0' failed. + + +In vvm, runtime has trouble with $display + +$ iverilog tshl.v +$ ./a.out +out=01 + +(looks like the correct output "out=01" followed by some + random memory garbage.) + + */ + +module tshl; + + reg [2:0] bit; + wire [7:0] shbit; + integer i; + + + shl shl_0(shbit, bit); + + initial begin + + for(i = 0; i < 8; i = i + 1) begin + bit <= i[2:0]; + #1 + $display("out=%h", shbit); + end // for (i = 0; i < 8; i = i + 1) + + $finish(0); + end // initial begin +endmodule + +module shl(out, bit); + + output [7:0] out; + input [2:0] bit; + + reg [7:0] out_reg; + + always @(bit) begin + out_reg <= 8'h01 << bit; + + end // always @ (bit) + + assign out = out_reg; + +endmodule // shl +`end_keywords diff --git a/ivtest/ivltests/wiresr.v b/ivtest/ivltests/wiresr.v new file mode 100644 index 000000000..6ca0df43f --- /dev/null +++ b/ivtest/ivltests/wiresr.v @@ -0,0 +1,55 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous >> in assignment..dependent on always >> working +// + + +module main; + +reg globvar; + +reg [3:0] var1,var2,var3; +wire [3:0] var3a; +reg error; + +assign var3a = var1 >> var2; + +always @( var1 or var2) + var3 = var1 >> var2 ; + +initial +begin +error =0; +for ( var1 = 4'b0; var1 != 4'hf; var1 = var1 + 1) + for ( var2 = 4'b0; var2 != 4'hf; var2 = var2 + 1) + begin + #1 ; + if(var3 != var3a) + begin + $display("FAILED continuous >> 1=%h,2=%h,3=%h,3a=%h", + var1,var2,var3,var3a); + error = 1; + end + #1; + end +if(error == 0) + $display("PASSED"); +end + +endmodule // main diff --git a/ivtest/ivltests/wiresub1.v b/ivtest/ivltests/wiresub1.v new file mode 100644 index 000000000..ddb448e77 --- /dev/null +++ b/ivtest/ivltests/wiresub1.v @@ -0,0 +1,56 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous sub in assignment..dependent on always - working +// + + +module main; + +reg globvar; + +reg [3:0] var1,var2,var3; +wire [3:0] var3a; +reg error; + +assign var3a = var1 - var2; + +always @( var1 or var2) + var3 = var1 - var2 ; + +initial +begin +error = 0; +for ( var1 = 4'b0; var1 != 4'hf; var1 = var1 + 1) + for ( var2 = 4'b0; var2 != 4'hf; var2 = var2 + 1) + begin + #1 ; + if(var3 !== var3a) + begin + #1 ; + error = 1; + end + #1; + end +if(error == 0) + $display("PASSED"); +else + $display("FAILED"); +end + +endmodule // main diff --git a/ivtest/ivltests/wirexor1.v b/ivtest/ivltests/wirexor1.v new file mode 100644 index 000000000..59e2d5b42 --- /dev/null +++ b/ivtest/ivltests/wirexor1.v @@ -0,0 +1,55 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW - Validate continuous xor in assignment..dependent on always ^ working +// + + +module main; + +reg globvar; + +reg [3:0] var1,var2,var3; +wire [3:0] var3a; +reg error; + +assign var3a = var1 ^ var2; + +always @( var1 or var2) + var3 = var1 ^ var2 ; + +initial +begin +error = 0; +for ( var1 = 4'b0; var1 != 4'hf; var1 = var1 + 1) + for ( var2 = 4'b0; var2 != 4'hf; var2 = var2 + 1) + begin + #1 ; + if(var3 != var3a) + begin + $display("FAILED continuous xor 1=%h,2=%h,3=%h,3a=%h", + var1,var2,var3,var3a); + error = 1; + end + #1; + end +if(error == 0) + $display("PASSED"); +end + +endmodule // main diff --git a/ivtest/ivltests/work14.vhd b/ivtest/ivltests/work14.vhd new file mode 100644 index 000000000..9b547d156 --- /dev/null +++ b/ivtest/ivltests/work14.vhd @@ -0,0 +1,30 @@ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.work14_pkg.all; + +entity work14_comp is + + generic ( + max_out_val : natural := 3; + sample_parm : string := "test"); + + port ( + clk_i : in std_logic; + val : out std_logic_vector(f_log2_size(max_out_val)-1 downto 0)); + +end work14_comp; + +architecture rtl of work14_comp is + +begin -- rtl + + foo : process(clk_i) + begin + if rising_edge(clk_i) then + val <= std_logic_vector(to_unsigned(max_out_val, val'length)); + end if; + end process; + +end rtl; diff --git a/ivtest/ivltests/work14_pkg.vhd b/ivtest/ivltests/work14_pkg.vhd new file mode 100644 index 000000000..a2633f939 --- /dev/null +++ b/ivtest/ivltests/work14_pkg.vhd @@ -0,0 +1,33 @@ + +library ieee; +use ieee.std_logic_1164.all; + +package work14_pkg is + + function f_log2_size ( + A : natural) + return natural; + component work14_comp + generic ( + max_out_val : natural; + sample_parm : string); + port ( + clk_i : in std_logic; + val : out std_logic_vector(f_log2_size(max_out_val)-1 downto 0)); + end component; + +end work14_pkg; + +package body work14_pkg is + + function f_log2_size (A : natural) return natural is + begin + for I in 1 to 64 loop -- Works for up to 64 bits + if (2**I >= A) then + return(I); + end if; + end loop; + return(63); + end function f_log2_size; + +end work14_pkg; diff --git a/ivtest/ivltests/work7.cfg b/ivtest/ivltests/work7.cfg new file mode 100644 index 000000000..756232190 --- /dev/null +++ b/ivtest/ivltests/work7.cfg @@ -0,0 +1,4 @@ +ivltests/work7/work7-pkg.vhd +ivltests/work7/timebase.vhd +ivltests/work7/bigcount.vhd +ivltests/work7/fdc.vhd diff --git a/ivtest/ivltests/work7.v b/ivtest/ivltests/work7.v new file mode 100644 index 000000000..71f14156e --- /dev/null +++ b/ivtest/ivltests/work7.v @@ -0,0 +1,34 @@ +module test; + reg clk, reset; + wire [24:0] count; + + initial begin + clk = 1'b0; + forever #25 clk = ~clk; + end + + initial begin + reset = 1'b0; + @(negedge clk); + reset = 1'b1; + repeat(6) @(negedge clk); + reset = 1'b0; + end + + initial begin + #200000; + #500; + if (count != 2000) begin + $display ("Counting FAILED"); + $finish; + end + else begin + $display ("PASSED"); + #20; + $finish; + end +end + + bigcount duv (.clk(clk), .reset(reset), .count(count) ); + +endmodule diff --git a/ivtest/ivltests/work7/bigcount.vhd b/ivtest/ivltests/work7/bigcount.vhd new file mode 100644 index 000000000..db9c337af --- /dev/null +++ b/ivtest/ivltests/work7/bigcount.vhd @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.work7.all; + +entity bigcount is + port (clk, reset: in std_logic; + count: out std_logic_vector (24 downto 0) + ); +end entity bigcount; + +architecture bigcount_rtl of bigcount is +signal d, t, q, myreset: std_logic; +begin + +d <= t xor q; + +myreset <= reset or t; + +f1: fdc port map (clk => clk, reset => reset, d => d, q => q); +tb: timebase port map (CLOCK => clk, RESET => myreset, ENABLE => '1', TICK => t, COUNT_VALUE => open ); + +counting: timebase port map (CLOCK => clk, RESET => reset, ENABLE => q, TICK => open, COUNT_VALUE => count ); + + +end bigcount_rtl; diff --git a/ivtest/ivltests/work7/fdc.vhd b/ivtest/ivltests/work7/fdc.vhd new file mode 100644 index 000000000..241818c8a --- /dev/null +++ b/ivtest/ivltests/work7/fdc.vhd @@ -0,0 +1,29 @@ +-- a D-type flip-flop with synchronous reset + +library ieee; +use ieee.std_logic_1164.all; + + +entity fdc is +port (clk: in std_logic; + reset: in std_logic; + d: in std_logic; + q: out std_logic +); +end fdc; + +architecture fdc_rtl of fdc is +begin + +i_finish: process (clk) +begin + if (clk'event and clk = '1') then + if (reset = '1') then + q <= '0'; + else + q <= d; + end if; + end if; +end process; + +end fdc_rtl; diff --git a/ivtest/ivltests/work7/timebase.vhd b/ivtest/ivltests/work7/timebase.vhd new file mode 100644 index 000000000..63cfbc4a8 --- /dev/null +++ b/ivtest/ivltests/work7/timebase.vhd @@ -0,0 +1,44 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +-- The operation is: +-- 1) An internal counter (of 25 bits) is initilaised to zero after a reset is received. +-- 2) An enable allows an internal running counter to count clock pulses +-- 3) A tick signal output is generated when a count of 20000000 pulses has been accumulated + + +entity TimeBase is + port( + CLOCK : in std_logic; -- input clock of 20MHz + TICK : out std_logic; -- out 1 sec timebase signal + RESET : in std_logic; -- master reset signal (active high) + ENABLE : in std_logic; + COUNT_VALUE: out std_logic_vector (24 downto 0) + ); +end TimeBase; + +architecture TimeBase_rtl of TimeBase is + + constant DIVIDER_VALUE : std_logic_vector := x"7cf"; -- 20000000 count value, 1 second + signal RunningCounter : std_logic_vector(24 downto 0); -- this is the 25 bit free running counter to allow a big count +begin + + RunningCounterProcess : process (CLOCK) + begin + if ( CLOCK'event and CLOCK = '1') then + if (RESET = '1') then + RunningCounter <= '0' & x"000000"; + elsif ( ENABLE = '1') then + RunningCounter <= RunningCounter + 1; + end if; + else + RunningCounter <= RunningCounter; + end if; + end process; + + TICK <= '1' when (RunningCounter = DIVIDER_VALUE) else '0'; + +COUNT_VALUE <= RunningCounter; + +end TimeBase_rtl; diff --git a/ivtest/ivltests/work7/work7-pkg.vhd b/ivtest/ivltests/work7/work7-pkg.vhd new file mode 100644 index 000000000..d25baefeb --- /dev/null +++ b/ivtest/ivltests/work7/work7-pkg.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; + +package work7 is + + -- D-type flip flop + component fdc is + port (clk: in std_logic; + reset: in std_logic; + d: in std_logic; + q: out std_logic); + end component; + + component TimeBase is + port( + CLOCK : in std_logic; -- input clock of 20MHz + TICK : out std_logic; -- out 1 sec timebase signal + RESET : in std_logic; -- master reset signal (active high) + ENABLE : in std_logic; + COUNT_VALUE: out std_logic_vector (24 downto 0) + ); +end component; + +end package work7; diff --git a/ivtest/ivltests/work7b.cfg b/ivtest/ivltests/work7b.cfg new file mode 100644 index 000000000..72064adc2 --- /dev/null +++ b/ivtest/ivltests/work7b.cfg @@ -0,0 +1,5 @@ ++vhdl-libdir+ivltests/work7b + +ivltests/work7b/timebase.vhd +ivltests/work7b/bigcount.vhd +ivltests/work7b/fdc.vhd diff --git a/ivtest/ivltests/work7b.v b/ivtest/ivltests/work7b.v new file mode 100644 index 000000000..71f14156e --- /dev/null +++ b/ivtest/ivltests/work7b.v @@ -0,0 +1,34 @@ +module test; + reg clk, reset; + wire [24:0] count; + + initial begin + clk = 1'b0; + forever #25 clk = ~clk; + end + + initial begin + reset = 1'b0; + @(negedge clk); + reset = 1'b1; + repeat(6) @(negedge clk); + reset = 1'b0; + end + + initial begin + #200000; + #500; + if (count != 2000) begin + $display ("Counting FAILED"); + $finish; + end + else begin + $display ("PASSED"); + #20; + $finish; + end +end + + bigcount duv (.clk(clk), .reset(reset), .count(count) ); + +endmodule diff --git a/ivtest/ivltests/work7b/bigcount.vhd b/ivtest/ivltests/work7b/bigcount.vhd new file mode 100644 index 000000000..8730f5919 --- /dev/null +++ b/ivtest/ivltests/work7b/bigcount.vhd @@ -0,0 +1,26 @@ +library ieee; +library uselib; +use ieee.std_logic_1164.all; +use uselib.work7.all; + +entity bigcount is + port (clk, reset: in std_logic; + count: out std_logic_vector (24 downto 0) + ); +end entity bigcount; + +architecture bigcount_rtl of bigcount is +signal d, t, q, myreset: std_logic; +begin + +d <= t xor q; + +myreset <= reset or t; + +f1: fdc port map (clk => clk, reset => reset, d => d, q => q); +tb: timebase port map (CLOCK => clk, RESET => myreset, ENABLE => '1', TICK => t, COUNT_VALUE => open ); + +counting: timebase port map (CLOCK => clk, RESET => reset, ENABLE => q, TICK => open, COUNT_VALUE => count ); + + +end bigcount_rtl; diff --git a/ivtest/ivltests/work7b/fdc.vhd b/ivtest/ivltests/work7b/fdc.vhd new file mode 100644 index 000000000..241818c8a --- /dev/null +++ b/ivtest/ivltests/work7b/fdc.vhd @@ -0,0 +1,29 @@ +-- a D-type flip-flop with synchronous reset + +library ieee; +use ieee.std_logic_1164.all; + + +entity fdc is +port (clk: in std_logic; + reset: in std_logic; + d: in std_logic; + q: out std_logic +); +end fdc; + +architecture fdc_rtl of fdc is +begin + +i_finish: process (clk) +begin + if (clk'event and clk = '1') then + if (reset = '1') then + q <= '0'; + else + q <= d; + end if; + end if; +end process; + +end fdc_rtl; diff --git a/ivtest/ivltests/work7b/timebase.vhd b/ivtest/ivltests/work7b/timebase.vhd new file mode 100644 index 000000000..63cfbc4a8 --- /dev/null +++ b/ivtest/ivltests/work7b/timebase.vhd @@ -0,0 +1,44 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +-- The operation is: +-- 1) An internal counter (of 25 bits) is initilaised to zero after a reset is received. +-- 2) An enable allows an internal running counter to count clock pulses +-- 3) A tick signal output is generated when a count of 20000000 pulses has been accumulated + + +entity TimeBase is + port( + CLOCK : in std_logic; -- input clock of 20MHz + TICK : out std_logic; -- out 1 sec timebase signal + RESET : in std_logic; -- master reset signal (active high) + ENABLE : in std_logic; + COUNT_VALUE: out std_logic_vector (24 downto 0) + ); +end TimeBase; + +architecture TimeBase_rtl of TimeBase is + + constant DIVIDER_VALUE : std_logic_vector := x"7cf"; -- 20000000 count value, 1 second + signal RunningCounter : std_logic_vector(24 downto 0); -- this is the 25 bit free running counter to allow a big count +begin + + RunningCounterProcess : process (CLOCK) + begin + if ( CLOCK'event and CLOCK = '1') then + if (RESET = '1') then + RunningCounter <= '0' & x"000000"; + elsif ( ENABLE = '1') then + RunningCounter <= RunningCounter + 1; + end if; + else + RunningCounter <= RunningCounter; + end if; + end process; + + TICK <= '1' when (RunningCounter = DIVIDER_VALUE) else '0'; + +COUNT_VALUE <= RunningCounter; + +end TimeBase_rtl; diff --git a/ivtest/ivltests/work7b/uselib/work7.pkg b/ivtest/ivltests/work7b/uselib/work7.pkg new file mode 100644 index 000000000..d25baefeb --- /dev/null +++ b/ivtest/ivltests/work7b/uselib/work7.pkg @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; + +package work7 is + + -- D-type flip flop + component fdc is + port (clk: in std_logic; + reset: in std_logic; + d: in std_logic; + q: out std_logic); + end component; + + component TimeBase is + port( + CLOCK : in std_logic; -- input clock of 20MHz + TICK : out std_logic; -- out 1 sec timebase signal + RESET : in std_logic; -- master reset signal (active high) + ENABLE : in std_logic; + COUNT_VALUE: out std_logic_vector (24 downto 0) + ); +end component; + +end package work7; diff --git a/ivtest/ivltests/wreal.v b/ivtest/ivltests/wreal.v new file mode 100644 index 000000000..2d1884704 --- /dev/null +++ b/ivtest/ivltests/wreal.v @@ -0,0 +1,58 @@ +module top; + reg pass; + real in; + wreal out1, out2, outa; + wreal ca1 = 2.25; + wreal ca2; + + assign ca2 = 4.5; + + sub1 dut1(out1, in); + sub2 dut2(out2, in); + suba duta(outa, in); + + initial begin + pass = 1'b1; + in = 1.0; + #1; + if (out1 != 1.0) begin + $display("FAILED: expected out1 to be 1.0, got %f", out1); + pass = 1'b0; + end + if (out2 != 1.0) begin + $display("FAILED: expected out2 to be 1.0, got %f", out2); + pass = 1'b0; + end + if (outa != 1.0) begin + $display("FAILED: expected outa to be 1.0, got %f", outa); + pass = 1'b0; + end + if (ca1 != 2.25) begin + $display("FAILED: expected ca1 to be 2.25, got %f", ca1); + pass = 1'b0; + end + if (ca2 != 4.5) begin + $display("FAILED: expected ca1 to be 4.5, got %f", ca2); + pass = 1'b0; + end + + if (pass) $display("PASSED"); + end +endmodule + +module sub1(out, in); + output out; + input in; + wreal out, in; + assign out = in; +endmodule + +module sub2(out, in); + output wreal out; + input wreal in; + assign out = in; +endmodule + +module suba(output wreal out, input wreal in); + assign out = in; +endmodule diff --git a/ivtest/ivltests/writemem-error.v b/ivtest/ivltests/writemem-error.v new file mode 100644 index 000000000..9671adb55 --- /dev/null +++ b/ivtest/ivltests/writemem-error.v @@ -0,0 +1,217 @@ +module top; + reg [20*8-1:0] str; + real rval; + reg [7:0] array [0:7]; + reg [7:0] array2 [8:15]; + reg [7:0] check [0:7]; + integer idx, istr; + + + initial begin + for (idx = 0; idx < 8; idx = idx + 1) array[idx] = idx + 1; + for (idx = 8; idx < 16; idx = idx + 1) array2[idx] = 0; + + // An invalid string. + $writememb(str, array); + $writememb(istr, array); + + // Check a valid string. + str = "work/writemem.txt"; + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememb(str, array); + $readmemb(str, check); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememb 1, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + + // Check a string with a non-printing character. + str[7:0] = 'd2; + $writememb(str, array); + + // This should write, but will print a warning about the real. + rval = 0.0; + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememb("work/writemem.txt", array, rval); + $readmemb("work/writemem.txt", check); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememb 2, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + + // This should write, but will print a warning about the real. + rval = 7.0; + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememb("work/writemem.txt", array, 0, rval); + $readmemb("work/writemem.txt", check); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememb 3, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + + // These should not write the array. + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememb("work/writemem.txt", check, -1, 7); + $readmemb("work/writemem.txt", check); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememb 4, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememb("work/writemem.txt", array2, 7, 15); + $readmemb("work/writemem.txt", check); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememb 5, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememb("work/writemem.txt", check, 0, 8); + $readmemb("work/writemem.txt", check); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememb 6, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememb("work/writemem.txt", array2, 8, 16); + $readmemb("work/writemem.txt", check); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememb 7, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + + // Check that we can write part of an array. + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememb("work/writemem.txt", array, 0, 6); + $readmemb("work/writemem.txt", check, 0, 6); + for (idx = 0; idx < 7; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememb 8, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + if (check[7] !== 0) begin + $display("Failed: for index 7 of writememb 8, expected 0, got %0d", + check[7]); + end + + + // An invalid string. + str = 'bx; + $writememh(str, array); + $writememh(istr, array); + + // Check a valid string. + str = "work/writemem.txt"; + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememh(str, array); + $readmemh(str, check); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememh 1, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + + // Check a string with a non-printing character. + str[7:0] = 'd2; + $writememh(str, array); + + // This should write, but will print a warning about the real. + rval = 0.0; + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememh("work/writemem.txt", array, rval); + $readmemh("work/writemem.txt", check); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememh 2, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + + // This should write, but will print a warning about the real. + rval = 7.0; + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememh("work/writemem.txt", array, 0, rval); + $readmemh("work/writemem.txt", check); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememh 3, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + + // These should not write the array. + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememh("work/writemem.txt", check, -1, 7); + $readmemh("work/writemem.txt", check); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememh 4, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememh("work/writemem.txt", array2, 7, 15); + $readmemh("work/writemem.txt", check); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememh 5, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememh("work/writemem.txt", check, 0, 8); + $readmemh("work/writemem.txt", check); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememh 6, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememh("work/writemem.txt", array2, 8, 16); + $readmemh("work/writemem.txt", check); + for (idx = 0; idx < 8; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememh 7, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + + // Check that we can write part of an array. + for (idx = 0; idx < 8; idx = idx + 1) check[idx] = 0; + $writememh("work/writemem.txt", array, 0, 6); + $readmemh("work/writemem.txt", check, 0, 6); + for (idx = 0; idx < 7; idx = idx + 1) begin + if (check[idx] !== idx + 1) begin + $display("Failed: for index %0d of writememh 8, expected %0d, got %0d", + idx, idx+1, check[idx]); + end + end + if (check[7] !== 0) begin + $display("Failed: for index 7 of writememh 8, expected 0, got %0d", + check[7]); + end + + end +endmodule diff --git a/ivtest/ivltests/writemem-invalid.v b/ivtest/ivltests/writemem-invalid.v new file mode 100644 index 000000000..f77481004 --- /dev/null +++ b/ivtest/ivltests/writemem-invalid.v @@ -0,0 +1,21 @@ +module top; + reg [7:0] array [7:0]; + + initial begin + $writememb(); + $writememb(top); + $writememb("writemem.txt"); + $writememb("writemem.txt", top); + $writememb("writemem.txt", array, top); + $writememb("writemem.txt", array, 0, top); + $writememb("writemem.txt", array, 0, 7, top); + + $writememh(); + $writememh(top); + $writememh("writemem.txt"); + $writememh("writemem.txt", top); + $writememh("writemem.txt", array, top); + $writememh("writemem.txt", array, 0, top); + $writememh("writemem.txt", array, 0, 7, top); + end +endmodule diff --git a/ivtest/ivltests/writememb1.v b/ivtest/ivltests/writememb1.v new file mode 100644 index 000000000..c01313151 --- /dev/null +++ b/ivtest/ivltests/writememb1.v @@ -0,0 +1,75 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// + +module main (); + + reg [7:0] array [0:7]; + reg error ; + reg [3:0] count; + + initial + begin + + for(count = 0; count <= 7; count = count + 1) + begin + array[count] = 1 << count; + end + + array[2] = 8'bx0z0x0z0; + $writememb("work/writememb1.dat", array, 6, 1); + + for(count = 0; count <= 7; count = count + 1) + begin + array[count] = 'bx; + end + + error = 0; + $readmemb("work/writememb1.dat", array); + + for(count = 0; count <= 3; count = count + 1) + begin + if(array[count] !== (1<<(6-count))) + begin + error = 1; + $display("FAILED - array[count] == %h, s/b %h", + array[count], 1 << count); + end + end + + if (array[4] != 8'bx0z0x0z0) + begin + error = 1; + $display("FAILED - array[count] == %h, s/b %h", + array[4], 8'bx0z0x0z0); + end + + if (array[5] != 8'b00000010) + begin + error = 1; + $display("FAILED - array[count] == %h, s/b %h", + array[5], 1 << 5); + end + + if(error == 0) + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/writememb2.v b/ivtest/ivltests/writememb2.v new file mode 100644 index 000000000..29603b71c --- /dev/null +++ b/ivtest/ivltests/writememb2.v @@ -0,0 +1,61 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// +// + +module main (); + + reg [7:0] array [7:0]; + reg error ; + reg [3:0] count; + + initial + begin + + for(count = 0; count <= 7; count = count + 1) + begin + array[count] = 1 << count; + end + + $writememb("work/writememb2.dat", array, 6, 1); + + for(count = 0; count <= 7; count = count + 1) + begin + array[count] = 'bx; + end + + error = 0; + + $readmemb("work/writememb2.dat", array); + + for(count = 0; count <= 5; count = count + 1) + begin + if(array[count] !== (1<<(6-count))) + begin + error = 1; + $display("FAILED - array[count] == %h, s/b %h", + array[count], 1 << count); + end + end + + if(error == 0) + $display("PASSED\n"); + $finish ; + end +endmodule diff --git a/ivtest/ivltests/writememh1.v b/ivtest/ivltests/writememh1.v new file mode 100644 index 000000000..8275a4ecd --- /dev/null +++ b/ivtest/ivltests/writememh1.v @@ -0,0 +1,62 @@ +// +// Copyright (c) 1999 Steven Wilson (stevew@home.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +// SDW: Initial readmemh function - length of data = array size. +// +// + +module main (); + + reg [7:0] array [0:7]; + reg error ; + reg [3:0] count; + + initial + begin + + for(count = 0; count <= 7; count = count + 1) + begin + array[count] = 1 << count; + end + + $writememh("work/writememh1.dat", array); + + for(count = 0; count <= 7; count = count + 1) + begin + array[count] = 'bx; + end + + error = 0; + + $readmemh("work/writememh1.dat", array); + + for(count = 0; count <= 7; count = count + 1) + begin + if(array[count] !== (1<& syntax?) + +Fixed always3.1.9A.v, Fixed always3.1.9B.v. Added tests always3.1.9C,D.v +Fixed wiremod1.v, syntax error in ptest006-008 in $display. Howcome +IVL likes these? Removed sdw_template.v. Added "PASSED" printout +to z1,z2. This should make them compatible with XL. +Fixed assign3.2D.v syntax error, moved syntax error into assign3.2E.v +to test for it! +Fixed contrib8.4.v so that it prints PASSED. + +12/11/99 + +Added contrib directory and fifo.v in same donated by Tom Coonan. +He's GPL this and other work for inclusion within the test suite! +THANKS TOM!!!!! + +Note that two tests always3.1.11B and udp_bufg are commented +out because they hang the testsuite currently. + +12/1/99 + +Added qmark6.v contributed by Dan Nelsen. Muxtest.v validates +X on sel, when inputs are both 1 or 0. + +11/12/99 + +Added several ga_* tests that use a primitive gate vector. The ga_nand.v test +of this sequence fails. Went thru the ptestxxx.v series and replaced all +!= or == constructs with !==/===. + +11/8/99 + +Fixed stuff added on 11/6 - it now says PASSED! +Added wirele.v, wirege.v, wireeq.v tests. These with the +CVS 11/7/99 cut that I used to test. + +11/6/99 + +Added tests wireadd1.v wiremod1.v wiresl.v wiresr.v wiresub1.v wirexor1.v +Several of the tests in regress.list had the .v extension so they +weren't running correctly. That's fixed. + +10/14/99 + +This is mainly a debug release. See below. + +lh_varindx added (tests left hand variable index of a vector.) +Rewrote always3.1.6A-C COMPLETELY. Changed time1.v to use +always block and #5 d = a; Added time3.v that looks at same +structure for non-blocking (#5 d <= a). + +Added an always3.1.6D.v ( a case test from Steve Williams.) + +There was a race condition in the always3.1.6A-C that was +due in part to the nature of always case (x) ...default #1; whoops! + +Removed qmark2.v - it became redundant(besides it was broken sematically) + +10/5/99 + +Changed location of #0 to first item in the initial +block for always3.1.6A-C.v This also counts as a +test for proper operation of the semantics for #0 +which is used to defeat what would otherwise be +a race condition. Researched the operation of #0 in +Moorby 4th edition. This seems to be kosher (though +not GOOD programming practice.) + +Added several contributed tests by many folks. + +Note that the regression_report.txt is the results of +running with the 9/28 IVL release. + +9/27/99 + +Added a #0 to take care of a race in always3.1.6A-C. +Added the ability to put an optional main module name as +a 4th arguement within the regress.list line. + +9/20/99 + +This release collects the tests together along with a +regression script(sregress.pl) which is a modified +version of a script contributed by Guy Hutchison. +(Thanks Guy!!!) + +To run the testsuite - ensure that you have the +appropriate IVL environment variables set - the +script doesn't check for THAT yet - maybe next +time;-) You need the appropriate stuff in your +search path for IVL and set VPI_MODULE_PATH and +LD_LIBRARY_PATH as necessary. See the IVL docs +for info. + +Now - simply move into the testsuite directory +and type: ./sregress.pl + +This will run the regression script, and create a +series of log files in the log directory. The test +runs are summarized in regression_report.txt. The +tests run are obtained from regress.list. + +9/9/99 + +Completed thru 3.14F(tasks). So Added from Section +3.11-3.14. Updated ivl_test.html file. Also have included +some of the "contributed" tests. Haven't worked them all +into the test document yet. + +9/6/99 + +Completed all of the always block tests. Added tests +for sections 3.2-3.10. Reworked the 3.1.5 tests that +had bugs. Updated the ivl_tests.html file to +reflect work to date. + +Note that runsh doesn't use the "verilog" script yet. + + +8/18/99 + +New tests added 3.1.5C - 3.1.7B + +8/12/99 + +Initial release to Steve Williams. diff --git a/ivtest/obsolete/elist b/ivtest/obsolete/elist new file mode 100644 index 000000000..4393c20e7 --- /dev/null +++ b/ivtest/obsolete/elist @@ -0,0 +1,75 @@ +# $Log: elist,v $ +# Revision 1.19 2004/01/21 04:52:30 stevewilliams +# Add pr904 +# +# Revision 1.18 2002/11/21 21:16:51 stevewilliams +# Add array5 as an error test. +# +# Revision 1.17 2002/11/13 03:26:33 stevewilliams +# Add tests pr564, pr581 and pr585. +# +# Revision 1.16 2002/11/02 01:11:16 stevewilliams +# Add pr567 to elist +# +# Revision 1.15 2002/11/02 01:02:32 stevewilliams +# memory names in messages no longer have scope. +# +# Revision 1.14 2002/04/22 00:50:54 stevewilliams +# Add the implicit1 test to the elist. +# +# Revision 1.13 2002/04/13 02:39:57 stevewilliams +# Add the memidx2 test of mem index errors. +# +# Revision 1.12 2002/04/12 02:56:57 stevewilliams +# Fix typos in elist file. +# +# Revision 1.11 2002/04/12 02:51:52 stevewilliams +# Add range3 to error test. +# +# Revision 1.10 2002/01/23 05:57:41 stevewilliams +# Fix scope2.v implicit wire error. +# +# Revision 1.9 2001/05/25 02:17:54 stevewilliams +# add port-test3 test. +# +# Revision 1.8 2001/02/13 03:35:31 stevewilliams +# Add cond_wide test (PR#143) +# +# Revision 1.7 2001/02/09 03:01:20 stevewilliams +# Add test for PR#133. +# +# Revision 1.6 2000/12/07 02:24:54 stevewilliams +# Get add32 error message right. +# +# Revision 1.5 2000/12/07 01:41:13 ka6s +# Add the $log feature to the comments here to allow automatic update logging. +# +# +readmemh5 ivltests main +./ivltests/readmemh5.v:35: error: part select of a memory: array +function3.11E ivltests test +./ivltests/function3.11E.v:30: parse error +add32 contrib main +./contrib/add32.v:14: error: sum is not a reg in this context. +range1 ivltests main +./ivltests/range1.v:44: error: bit/part select thing[9:9] is out of range. +range2 ivltests bug +./ivltests/range2.v:9: error: bit/part select [3:2] out of range for din +range3 ivltests simple +./ivltests/range3.v:26: error: Signal ``b'' declared both as a vector and a scalar. +port-test3 ivltests BENCH +./ivltests/port-test3.v:16: error: data in module CPU declared as inout and as a reg type. +scope2b ivltests main +./ivltests/scope2b.v:30: error: Net q is not defined in this context. +memidx2 ivltests main +./ivltests/memidx2.v:14: error: memory mem needs an index in this context. +implicit1 ivltests Counter56 +./ivltests/implicit1.v:25: error: Counter56.CounterReset not defined in this scope. +pr567 ivltests test +./ivltests/pr567.v:3: error: Assign to memory "blah" requires a word select index. +pr581 ivltests main +./ivltests/pr581.v:14: error: memories (data) cannot be l-values in continuous assignments. +array5 ivltests test +./ivltests/array5.v:14: error: Part select expressions must be constant. +pr904 ivltests err +./ivltests/pr904.v:26: error: Missing expression 3 of concatenation list. diff --git a/ivtest/obsolete/eregress.pl b/ivtest/obsolete/eregress.pl new file mode 100644 index 000000000..bc8535544 --- /dev/null +++ b/ivtest/obsolete/eregress.pl @@ -0,0 +1,237 @@ +#!/usr/bin/env perl -s +# +# Copyright (c) 1999 Guy Hutchison (stevew@home.com) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +$total_count = 0; + +$num_opts = $#ARGV ; + +if($num_opts ne -1) { + # Got here cuz there is a command line option + $regress_fn = $ARGV[0]; + if(!( -e "$regress_fn")) { + print("Error - Command line option file $num_opts doesn't exist.\n"); + exit(1); + } +} else { + $regress_fn = "./elist"; +} + + +$logdir = "errlog"; +$bindir = "bin"; # not currently used +$report_fn = "./err_regress.txt"; + +$comp_name = "IVL" ; # Change the name of the compiler in use here. + # this may change to a command line option after + # I get things debugged! + +# Debug variables +$dbg1 = 0; +$dbg2 = 0; + +# Main script + +print ("Reading/parsing test list\n"); +&read_regression_list; +&execute_regression; +print ("Checking logfiles\n"); +&check_results; +print("Testing $testname ********"); + +# +# parses the regression list file +# +# First line +# splits the data into a list of names (@testlist), and a +# number of hashes, indexed by name of test. Hashes are +# (from left-to-right in regression file): +# +# %testtype type of test. compile = compile only +# normal = compile & run, expect standard +# PASSED/FAILED message at EOT. +# %testpath path to test, from root of test directory. No +# trailing slash on test path. +# +# %testmod = main module declaration (optional) +# +# Second line +# +# The error you expect to find. + +sub read_regression_list { + open (REGRESS_LIST, "<$regress_fn"); + local ($found, $testname); + + while () { # read first line + chop; + if (!/^#/) { + # strip out any comments later in the file + s/#.*//g; + @found = split; + $compare_line = ; # Read 2nd line + chop($compare_line); + + # Now spread things out a bit + $testname = $found[0]; + $testpath{$testname} = $found[1]; + $testmod{$testname} = $found[2]; + $compare{$testname} = $compare_line; + push (@testlist, $testname); + if($dbg1 == 1) { + print $testname,"-",$testpath{$testname},"-", + $testmod{$testname},"=",$compare{$testname},"\n"; + } + } + } + close (REGRESS_LIST); +} + +# +# execute_regression sequentially compiles and executes each test in +# the regression. Regression is done as a two-pass run (execute, check +# results) so that at some point the execution part can be parallelized. +# + +sub execute_regression { + local ($testname, $rv); + local ($bpath, $lpath, $vpath); + + foreach $testname (@testlist) { + + # + # First lets clean up the "last" test run. + # + if(-e "core") { + system("rm -f core"); + } + if(-e "simv") { + system("rm -f simv"); + } + if(-e "simv.exe") { + system("rm -f simv.exe"); # And we support DOS too!! + } + + # + # This is REALLY only an IVL switch... + # + # vermod is used to declare the "main module" + # + $vermod = "-s ".$testmod{$testname} ; + $vername = "iverilog "; + $verout = "-o simv"; + $redir = "&>"; + + print "Test $testname:"; + if ($testpath{$testname} eq "") { + $vpath = "./$testname.v"; + } else { + $vpath = "./$testpath{$testname}/$testname.v"; + } + + $lpath = "./$logdir/$testname.log"; + system("rm -rf $lpath"); + system("rm -rf *.out"); + + + # + # if we have a logfile - remove it first + # + if(-e "$lpath") { + system("rm $lpath"); + } + + # + # Now build the command up + # + $cmd = "$vername $versw $verout $vermod $vpath $redir $lpath "; + print "$cmd\n"; + system("$cmd"); # and execute it. + + + } + +} + +sub check_results { + local ($testname, $rv); + local ($bpath, $lpath, $vpath); + local ($pass_count, $fail_count, $crash_count); + local ($result); + + $pass_count = 0; + $no_sorry = 0; + $no_parse_err =0; + $no_run = 0; + $crash_count = 0; + $comperr_cnt = 0; + $comp_err = 0; + + open (REPORT, ">$report_fn"); + + print REPORT "Test Results:\n"; + + $num_tests = 0; + foreach $testname (@testlist) { + $lpath = "$logdir/$testname.log"; + $num_tests++; # count tests + + # Read in the logfile into infile. + open(FILE_D,$lpath); + @infile = ; + close(FILE_D); + + $num_lines = $#infile ; + for($indx=0; $indx <= $num_lines; $indx++) { + chop($infile[$indx]); + } + + if($dbg1 == 1) { + print "Number lines = ",$num_lines,"\n"; + } + + #Now scan the log file for the error + $error_found = 0; + + for($indx=0; $indx <= $num_lines; $indx++) { + if($dbg2 == 1) { + print "Comparing:\n"; + print "read:",$infile[$indx],"\n"; + print "cmpr:",$compare{$testname},"\n"; + } + if($infile[$indx] eq $compare{$testname}) { + $error_found = 1; + } + } + + if($error_found == 1) { + $pass_count++ ; + print REPORT "$testname\t\tPASSED\n"; + print "$testname\t\tPASSED\n"; + } else { + print REPORT "$testname\t\tFAILED\n"; + print "$testname\t\tFAILED\n"; + } + + } + + $total = $pass_count + $no_compile + $no_run + $crash_count; + print REPORT "Tests passed: $pass_count of $num_tests total\n"; + print "Tests passed: $pass_count of $num_tests total\n"; + close (REPORT); +} diff --git a/ivtest/obsolete/sregress.pl b/ivtest/obsolete/sregress.pl new file mode 100644 index 000000000..ffda70d9b --- /dev/null +++ b/ivtest/obsolete/sregress.pl @@ -0,0 +1,512 @@ +#!/usr/bin/env perl -s +##!/utilities/perl/bin/perl -s +# +# Copyright (c) 1999 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# 9/17/99 - SDW - Modified to handle multiple compilers. This is needed +# to allow verification of the sweet in other environments. +# Right now it works with Verilog-XL. Need to debug w/ ivl +# +# Modified the check_results analysis to handle different +# compilers. Works with Veriog-XL. Need to debug w/ ivl +# +# 9/23/99 - SDW - Added command line option to change the source of the +# regress.list - If a command line option is present, then +# it is used as the name of a file for the regress.list. +# +# 9/27/99 - SDW - Added optional "main module" arguement to the regress.list +# format. +# +# 10/5/99 - SDW - Added a "CN" Switch for IVL to pass -t null to the +# compiler. Per Steve Williams' request. +# +# 12/27/99- SDW - added $redir to cmd generation and validated against +# XL again. Using &> it was going into backround on solaris. +# Changed $redir to -l which is the switch for XL to gen a +# log file. This got me a serial run. +# +# 12/31/99 - SDW - Last change of the century! Steve Williams asked for +# qualifying Compiler errors. So far I'm now counting +# sorry messages and "parse error" messages. Steve will +# perhaps be suprised that there are other types appearing +# like "failed to elaborate.." Anyway - seems to work. +# +# 01/01/00 - SDW - Added a grep for "Unable" which should pick up the +# elaboration errors. +# +# 03/13/00 - SDW - Fixed REPORT print error for Compiler Error Count +# +# 05/08/00 - SDW - Added gold=filename as 4th option instead of +# module name (some time I'll have to make it 4th or +# 5th to handle place where we need module names too!) +# Also rm'd any pre-existing log files +# 06/11/00 - SDW - Added CRASH detection for CE class tests +# +# 10/04/00 - SDW - Added suggested change from Steve Williams +# to remove simv.exe for the software to run +# on windows. + +# Global setup and paths + +$total_count = 0; + +$num_opts = $#ARGV ; + +if($num_opts ne -1) { + # Got here cuz there is a command line option + $regress_fn = $ARGV[0]; + if(!( -e "$regress_fn")) { + print("Error - Command line option file $num_opts doesn't exist.\n"); + exit(1); + } +} else { + $regress_fn = "./regress.list"; +} + + +$logdir = "log"; +$bindir = "bin"; # not currently used +$report_fn = "./regression_report.txt"; + +$comp_name = "IVL" ; # Change the name of the compiler in use here. + # this may change to a command line option after + # I get things debugged! + +if($comp_name eq "XL") { + $vername = "vlogcmd"; # XL's command name + $versw = ""; # switches + $verout = ""; + $redir = " -l "; +} else { + $vername = "iverilog"; # IVL's shell + $versw = ""; # switches + $verout = "-o simv"; # output (for IVL ) + $redir = "&>"; +# $redir = "2>&1 > "; +} + +# Main script + +print ("Reading/parsing test list\n"); +&read_regression_list; +&execute_regression; +print ("Checking logfiles\n"); +&check_results; +print("Testing $testname ********"); + +# +# parses the regression list file +# +# splits the data into a list of names (@testlist), and a +# number of hashes, indexed by name of test. Hashes are +# (from left-to-right in regression file): +# +# %testtype type of test. compile = compile only +# normal = compile & run, expect standard +# PASSED/FAILED message at EOT. +# %testpath path to test, from root of test directory. No +# trailing slash on test path. +# +# %testmod = main module declaration (optional) + +sub read_regression_list { + open (REGRESS_LIST, "<$regress_fn"); + local ($found, $testname); + + while () { + chop; + if (!/^#/) { + # strip out any comments later in the file + s/#.*//g; + $found = split; + if ($found > 2) { + $total_count++; + $testname = $_[0]; + $testtype{$testname} = $_[1]; + $testpath{$testname} = $_[2]; + + if($#_ eq 3) { # Check for 4 fields + if(!($_ =~ /gold=/) && !($_ =~ /diff=/ )) { + $testmod{$testname} = $_[3]; # Module name, not gold + $opt{$testname} = ""; # or diff + } elsif ($_ =~ /gold=/) { + $testmod{$testname} = "" ; # It's a gold file + $opt{$testname} = $_[3] ; + } elsif ($_ =~ /diff=/) { # It's a diff file + $testmod{$testname} = ""; + $opt{$testname} = $_[3]; + } + } elsif ($#_ eq 4) { # Check for 5 fields + $testmod{$testname} = $_[3]; # Module name - always in this case + if ($_ =~ /gold=/) { + $opt{$testname} = $_[4]; + } elsif ($_ =~ /diff=/) { + $opt{$testname} = $_[4]; + } + } + + push (@testlist, $testname); + } + } + } + + close (REGRESS_LIST); +} + +# +# execute_regression sequentially compiles and executes each test in +# the regression. Regression is done as a two-pass run (execute, check +# results) so that at some point the execution part can be parallelized. +# + +sub execute_regression { + local ($testname, $rv); + local ($bpath, $lpath, $vpath); + + foreach $testname (@testlist) { + + # + # First lets clean up if its' IVL. We need to know if + # these are generated on the current pass. + # + if($comp_name eq "IVL") { + if(-e "core") { + system("rm -f core"); + } + if(-e "simv") { + system("rm -f simv"); + } + if(-e "simv.exe") { + system("rm -f simv.exe"); + } + } + + # + # This is REALLY only an IVL switch... + # + # vermod is used to declare the "main module" + # + if( $testmod{$testname} ne "") { + $vermod = "-s ".$testmod{$testname} ; + } else { + $vermod = " "; + } + if($comp_name eq "XL") { # Just over-ride for XL + $vermod = " "; + } + + + print "Test $testname:"; + if ($testpath{$testname} eq "") { + $vpath = "./$testname.v"; + } else { + $vpath = "./$testpath{$testname}/$testname.v"; + } + + $lpath = "./$logdir/$testname.log"; + system("rm -rf $lpath"); + system("rm -rf *.out"); + + # Check here for "compile only" situation and set + # the switch appropriately. + # + # While we're in CO mode - take a snapshot of it. Note + # this puts a contraint on the order -never can have a CO + # as the FIRST test in the list for this to work. + # + + if($testtype{$testname} ne "CO") { # Capture ONLY + $versw = $old_versw ; # the non-compile only + } # command here. + + if(($testtype{$testname} eq "CO") || + ($testtype{$testname} eq "CN")) { + if($comp_name eq "XL") { + $versw = "-c" ; + } else { + if($testtype{$testname} eq "CN") { + $versw = "-t null"; + } else { + $versw = ""; + } + } + } else { + $versw = $old_versw ; # Restore non-compile only state + } + + # + # if we have a logfile - remove it first + # + if(-e "$lpath") { + system("rm $lpath"); + } + + # + # Now build the command up + # + # $cmd = "$vername $versw $vermod $verout $vpath &> $lpath "; + $cmd = "$vername $versw $vermod $verout $vpath $redir $lpath "; + print "$cmd\n"; + system("$cmd"); + + # Note that with IVL we have to execute the code now + # that it's compiled - there is GOING to be switch in + # the verilog switch that will make this unnecessary. + + if($comp_name eq "IVL") { + if( -e "simv") { + if(!($testtype{$testname} eq "CO" ) && + !($testtype{$testname} eq "CN" ) && + !($testtype{$testname} eq "CE" )) { + system ("./simv >> $lpath"); + } else { + system ("echo PASSED >> $lpath" ); + } + } elsif ( -e "core") { + system ("echo CRASHED >> $lpath" ); + + } elsif ($testtype{$testname} eq "CN" ) { + system ("echo PASSED >> $lpath" ); + } else { + system ("echo COMPERR >> $lpath" ); + } + } + + } + +} + +sub check_results { + local ($testname, $rv); + local ($bpath, $lpath, $vpath); + local ($pass_count, $fail_count, $crash_count); + local ($result); + + $pass_count = 0; + $no_sorry = 0; + $no_parse_err =0; + $no_run = 0; + $crash_count = 0; + $comperr_cnt = 0; + $comp_err = 0; + + open (REPORT, ">$report_fn"); + + print REPORT "Test Results:\n"; + + foreach $testname (@testlist) { + $lpath = "$logdir/$testname.log"; + + # + # This section is used to compare against GOLD FILES + # We compare the log file against a known GOOD result + # + # This section runs if gold=name is the 4th option + # + + $gold_file = ""; + $gold_file = ""; + $diff_file = ""; + $optname = $opt{$testname} ; + if(($opt{$testname} ne "") && ($optname =~ /gold=/)){ + $gold_file = $opt{$testname}; + $gold_file =~ s/gold=//; # remove gold= operator + system("rm -rf ./dfile"); + system("diff $lpath ./gold/$gold_file > ./dfile "); + if( -z "dfile" ) { + system ("echo PASSED >> $lpath" ); + } else { + system ("echo FAILED >> $lpath"); + } + } + + $gold_file = ""; + $diff_file = ""; + # + # Now look for difference file requirements - use this for + # vcd's initially I guess. + # + if(($opt{$testname} ne "") && ($optname =~ /diff=/)){ + $diff_file = $optname ; + $diff_file =~ s/diff=//; + system("rm -rf ./dfile"); + ($out_file,$gold_file) = split(/:/,$diff_file); + system("diff $out_file $gold_file > ./dfile"); + if( -z "dfile" ) { + system ("echo PASSED >> $lpath" ); + } else { + system ("echo FAILED >> $lpath"); + } + } + + # uncompress the log file, if a compressed log file exists + if (-f "$lpath.gz") { system "gunzip $lpath.gz"; } + + # check the log file for the test status + if (-f $lpath) { + print ("Checking test $lpath\n"); + $result = `tail -150 $lpath`; + + # First do analysis for all tests that SHOULD run + if(($testtype{$testname} ne "CO") && + ($testtype{$testname} ne "CE") && + ($testtype{$testname} ne "CN")) { + # + # This section is true for all tests that execute - + # no matter the compiler. + # + if ($result =~ /PASSED/) { + printf REPORT "%30s passed\n", $testname; + $pass_count++; + } elsif (($result =~ /FAILED/)) { + printf REPORT "%30s execution failed\n", $testname; + $no_run++; + } + + # Need to check for syntax errors in tests that + # are expected to pass. + + if($comp_name eq "XL") { + if($result =~ /Error/) { + printf REPORT "%30s compile errors\n", $testname; + $no_compile++ ; + } + } else {# IVL compile error check goes here + if ($result =~ /PASSED/) { + } elsif ($result =~ /COMPERR/) { + $comp_err = 0; + printf REPORT "%30s ",$testname; + if($result =~ /parse error/) { + printf REPORT "had parse errors:"; + $no_parse_err++; + $no_compile++ ; + $comp_err++; + } + if(($result =~ /Unable/) || + ($result =~ /unhandled/)) { + printf REPORT "had elaboration errors:"; + $no_compile++ ; + $comp_err++; + } + if($result =~ /sorry/) { + printf REPORT "had unsupported features"; + $no_sorry++ ; + $no_compile++ ; + $comp_err++; + } + if($comp_err eq 0) { + printf REPORT "has C Compiler problem"; + $no_compile++ ; + $comperr_cnt++; + } + if($result =~ /CRASHED/ ) { + printf REPORT "%30s compile crashed\n", $testname; + printf "%30s compile crashed(2)\n", $testname; + $crash_count++; + } + printf REPORT "\n"; + + } elsif (($result =~ /CRASHED/)) { + printf REPORT "%30s compile crashed\n", $testname; + printf "%30s compile crashed (1)\n", $testname; + $crash_count++; + } + } + + } + + # Now look at Compile only situation - going to be + # different results for each compiler. + + # Test for CE case first + if($testtype{$testname} eq "CE") { + if($comp_name eq "XL") { + # Deal with XL frist + if($result =~ /Error/) { + $pass_count++; + } + } else { + # Deal with IVL here... + if (($result =~ /CRASHED/)) { + printf REPORT "%30s compile crashed\n", $testname; + printf "%30s compile crashed (1)\n", $testname; + $crash_count++; + } + } + } + + if(($testtype{$testname} eq "CO") || + ($testtype{$testname} eq "CN")) { + if($comp_name eq "XL") { + if($result =~ /Error/) { + printf REPORT "%30s compile failed\n", $testname; + print "%30s compile failed\n", $testname; + $no_compile++ ; + } else { + printf REPORT "%30s passed\n", $testname; + $pass_count++ ; + } + } else { # IVL stuff goes here. + if ($result =~ /PASSED/) { + printf REPORT "%30s passed\n", $testname; + $pass_count++; + } elsif ($result =~ /COMPERR/) { + $comp_err = 0; + printf REPORT "%30s ",$testname; + if($result =~ /parse error/) { + printf REPORT "had parse errors:"; + $no_parse_err++; + $comp_err++; + } + if(($result =~ /Unable/) || + ($result =~ /unhandled/)) { + printf REPORT "had elaboration errors:"; + $comp_err++; + } + if($result =~ /sorry/) { + printf REPORT "had unsupported features"; + $no_sorry++ ; + $comp_err++; + } + if($comp_err eq 0) { + printf REPORT "has C Compiler problem"; + $comperr_cnt++; + } + if(!(comp_err eq 0)) { + $no_compile++; + } + printf REPORT "\n"; + } elsif ($result =~ /CRASHED/ ) { + printf REPORT "%30s compile crashed\n", $testname; + $crash_count++ ; + } + } + } + } else { + printf REPORT "%30s No log file\n", $testname; + $crash_count++; + } + } + + $total = $pass_count + $no_compile + $no_run + $crash_count; + print REPORT "Tests passed: $pass_count, Parse Errors: $no_parse_err, Unsupported: $no_sorry, failed execution, $no_run, crashed: $crash_count, C Compiler errors: $comperr_cnt total: $total_count\n"; + + print "Tests passed: $pass_count, Parse Errors: $no_parse_err, Unsupported: $no_sorry, failed execution, $no_run, crashed: $crash_count, C compiler err: $comperr_cnt total: $total_count\n"; + + close (REPORT); +} diff --git a/ivtest/obsolete/vvptests/COPYING b/ivtest/obsolete/vvptests/COPYING new file mode 100644 index 000000000..916d1f0f2 --- /dev/null +++ b/ivtest/obsolete/vvptests/COPYING @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Library General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. 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If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/ivtest/obsolete/vvptests/README b/ivtest/obsolete/vvptests/README new file mode 100644 index 000000000..dc5ec6af4 --- /dev/null +++ b/ivtest/obsolete/vvptests/README @@ -0,0 +1,6 @@ +This series of tests is used to validate the vvp portion of the iverilog runtimesystem. To use the tests just run: + +./vvp.pl + +This will execute the regression list in regress.list and generate a report in +regression_report.txt diff --git a/ivtest/obsolete/vvptests/regress.list b/ivtest/obsolete/vvptests/regress.list new file mode 100644 index 000000000..0840945e1 --- /dev/null +++ b/ivtest/obsolete/vvptests/regress.list @@ -0,0 +1,46 @@ +# +# Copyright (c) 1999 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# Format of the file +# +# testname testtype directory +# +# Note that no extension is required for the testname, and that the +# sregress.pl logic requires that the FIRST test in the list not be a +# CO class test. +# +# Testtype can be one of +# +# normal: Normal results expected, i.e it should compile an execute +# to a PASSED +# CO: Compile only - Examine the logfile for any errors - shouldn't +# be any. +# CE: Compile with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# The third arguement is the directory, and forth optional is one of +# modulename - Defines the top level module +# gold=filename - Compare a gold file against the generated log file. +# diff=filename1:filename2 - Compare the two files for equality. +# +assignx0 normal vvpsources +hello normal vvpsources +resolvz normal vvpsources +force normal vvpsources +force0 normal vvpsources +force_pca normal vvpsources diff --git a/ivtest/obsolete/vvptests/vvp.pl b/ivtest/obsolete/vvptests/vvp.pl new file mode 100644 index 000000000..e9993ca16 --- /dev/null +++ b/ivtest/obsolete/vvptests/vvp.pl @@ -0,0 +1,415 @@ +#!/usr/bin/env perl -s +##!/utilities/perl/bin/perl -s +# +# Script vvp.pl modified to handle vvp for Steve Williams +# +# Copyright (c) 1999 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# 3/25/2001 SDW Modified sregress.pl script to run vvp. +# 4/13/2001 SDW Added CORE DUMP detection +# 5/5/2001 SDW Modified from vvp_reg.pl to run JUST vvp, no iverilog. +# +# $Log: vvp.pl,v $ +# Revision 1.1 2001/05/07 05:13:21 stevewilliams +# Add the initial suite to CVS. +# +# Revision 1.5 2001/04/14 03:44:03 ka6s +# Added what I THINK is working redirection. The Parse Err is showing up now! +# +# Revision 1.4 2001/04/14 03:33:02 ka6s +# Fixed detection of Core dumps. Made sure I remove core before we run vvp. +# + +# Global setup and paths +$| = 1; # This turns off buffered I/O +$total_count = 0; +$debug = 1; + +$num_opts = $#ARGV ; + +if($num_opts ne -1) { + # Got here cuz there is a command line option + $regress_fn = $ARGV[0]; + if(!( -e "$regress_fn")) { + print("Error - Command line option file $num_opts doesn't exist.\n"); + exit(1); + } +} else { + $regress_fn = "./regress.list"; +} + + +$logdir = "log"; +$bindir = "bin"; # not currently used +$report_fn = "./regression_report.txt"; + +$comp_name = "IVL" ; # Change the name of the compiler in use here. + # this may change to a command line option after + # I get things debugged! + + $vername = "/usr/bin/env vvp"; # IVL's shell + $versw = ""; # switches + $verout = "-o simv -tvvp"; # vvp source output (for IVL ) + #$redir = "&>"; + $redir = "> "; + +# Main script + +print ("Reading/parsing test list\n"); +&read_regression_list; +&rmv_logs ; +&execute_regression; +print ("Checking logfiles\n"); +&check_results; + +# +# Remove log files +# + +sub rmv_logs { + foreach (@testlist) { + $cmd = "rm -rf log/$_.log"; + system("$cmd"); + } +} + +# +# parses the regression list file +# +# splits the data into a list of names (@testlist), and a +# number of hashes, indexed by name of test. Hashes are +# (from left-to-right in regression file): +# +# %testtype type of test. compile = compile only +# normal = compile & run, expect standard +# PASSED/FAILED message at EOT. +# %testpath path to test, from root of test directory. No +# trailing slash on test path. +# +# %testmod = main module declaration (optional) + +sub read_regression_list { + open (REGRESS_LIST, "<$regress_fn"); + local ($found, $testname); + + while () { + chop; + if (!/^#/) { + # strip out any comments later in the file + s/#.*//g; + $found = split; + if ($found > 2) { + $total_count++; + $testname = $_[0]; + $testtype{$testname} = $_[1]; + $testpath{$testname} = $_[2]; + + if($#_ eq 3) { # Check for 4 fields + if(!($_ =~ /gold=/) && !($_ =~ /diff=/ )) { + $testmod{$testname} = $_[3]; # Module name, not gold + $opt{$testname} = ""; # or diff + } elsif ($_ =~ /gold=/) { + $testmod{$testname} = "" ; # It's a gold file + $opt{$testname} = $_[3] ; + } elsif ($_ =~ /diff=/) { # It's a diff file + $testmod{$testname} = ""; + $opt{$testname} = $_[3]; + } + } elsif ($#_ eq 4) { # Check for 5 fields + $testmod{$testname} = $_[3]; # Module name - always in this case + if ($_ =~ /gold=/) { + $opt{$testname} = $_[4]; + } elsif ($_ =~ /diff=/) { + $opt{$testname} = $_[4]; + } + } + + push (@testlist, $testname); + } + } + } + + close (REGRESS_LIST); +} + +# +# execute_regression sequentially compiles and executes each test in +# the regression. Regression is done as a two-pass run (execute, check +# results) so that at some point the execution part can be parallelized. +# + +sub execute_regression { + local ($testname, $rv); + local ($bpath, $lpath, $vpath); + + foreach $testname (@testlist) { + + # + # First lets clean up if its' IVL. We need to know if + # these are generated on the current pass. + # + + # + # This is REALLY only an IVL switch... + # + # vermod is used to declare the "main module" + # + if( $testmod{$testname} ne "") { + $vermod = "-s ".$testmod{$testname} ; + } else { + $vermod = " "; + } + + print "Test $testname:"; + if ($testpath{$testname} eq "") { + $vpath = "./$testname.vp"; + } else { + $vpath = "./$testpath{$testname}/$testname.vp"; + } + + $lpath = "./$logdir/$testname.log"; + system("rm -rf $lpath"); + system("rm -rf *.out"); + + # Check here for "compile only" situation and set + # the switch appropriately. + # + # While we're in CO mode - take a snapshot of it. Note + # this puts a contraint on the order -never can have a CO + # as the FIRST test in the list for this to work. + # + + if($testtype{$testname} ne "CO") { # Capture ONLY + $versw = $old_versw ; # the non-compile only + } # command here. + + if(($testtype{$testname} eq "CO") || + ($testtype{$testname} eq "CN")) { + if($testtype{$testname} eq "CN") { + $versw = "-t null"; + } else { + $versw = ""; + } + } else { + $versw = $old_versw ; # Restore non-compile only state + } + + # + # if we have a logfile - remove it first + # + if(-e "$lpath") { + system("rm $lpath"); + } + + # + # Now build the command up + # + # $cmd = "$vername $versw $vermod $verout $vpath &> $lpath "; + $cmd = "$vername $vpath $redir $lpath 2>&1 "; + + print "$cmd\n"; + $rc = system("$cmd"); + + # Note that with IVL we have to execute the code now + # that it's compiled - there is GOING to be switch in + # the verilog switch that will make this unnecessary. + + #if(($rc == 0) && ($comp_name eq "IVL")) { + # if( -e "simv") { + # if(!($testtype{$testname} eq "CO" ) && + # !($testtype{$testname} eq "CN" ) && + # !($testtype{$testname} eq "CE" )) { + # system ("rm -rf core"); + # system ("/usr/bin/env vvp simv >> $lpath 2>&1 "); + # } else { + # + # } + # if( -e "core") { + # system ("echo CRASHED > $lpath" ); + # } + # } elsif ( -e "core") { + # system ("echo CRASHED >> $lpath" ); + # + # } elsif ($testtype{$testname} eq "CN" ) { + # # system ("echo PASSED >> $lpath" ); + # } else { + # system ("echo COMPERR >> $lpath" ); + # } + #} + + } + +} + +sub check_results { + local ($testname, $rv); + local ($bpath, $lpath, $vpath); + local ($pass_count, $fail_count, $crash_count); + local ($result); + + $pass_count = 0; + $no_sorry = 0; + $parse =0; + $no_run = 0; + $crash_count = 0; + $comperr_cnt = 0; + $comp_err = 0; + $unhandled = 0; + $unable = 0; + $assertion = 0; + $passed = 0; + $failed = 0; + + open (REPORT, ">$report_fn"); + + print REPORT "Test Results:\n"; + + foreach $testname (@testlist) { + $lpath = "$logdir/$testname.log"; + + # + # This section is used to compare against GOLD FILES + # We compare the log file against a known GOOD result + # + # This section runs if gold=name is the 4th option + # + + $gold_file = ""; + $gold_file = ""; + $diff_file = ""; + $optname = $opt{$testname} ; + if(($opt{$testname} ne "") && ($optname =~ /gold=/)){ + $gold_file = $opt{$testname}; + $gold_file =~ s/gold=//; # remove gold= operator + system("rm -rf ./dfile"); + system("diff $lpath ./gold/$gold_file > ./dfile "); + if( -z "dfile" ) { + system ("echo PASSED >> $lpath" ); + } else { + system ("echo FAILED >> $lpath"); + } + } + + $gold_file = ""; + $diff_file = ""; + # + # Now look for difference file requirements - use this for + # vcd's initially I guess. + # + if(($opt{$testname} ne "") && ($optname =~ /diff=/)){ + $diff_file = $optname ; + $diff_file =~ s/diff=//; + system("rm -rf ./dfile"); + ($out_file,$gold_file) = split(/:/,$diff_file); + print("diff $out_file $gold_file > ./dfile"); + system("diff $out_file $gold_file > ./dfile"); + if( -z "dfile" ) { + system ("echo PASSED >> $lpath" ); + } else { + system ("echo FAILED >> $lpath"); + } + } + + # uncompress the log file, if a compressed log file exists + if (-f "$lpath.gz") { system "gunzip $lpath.gz"; } + + # check the log file for the test status + if (-f $lpath) { + print ("Checking test $lpath\n"); + $result = `tail -150 $lpath`; + + $err_flag = 0; + + # First do analysis for all tests that SHOULD run + + printf REPORT "%30s ",$testname; + + if( ($testtype{$testname} ne "CE") && + ($testtype{$testname} ne "CN")) { + # + # This section is true for all tests that execute - + # no matter the compiler. + # + if ($result =~ "Unhandled") { + $err_flag = 1; + printf REPORT "Unhandled-"; + $unhandled++; + } + + if ($result =~ "sorry") { + $err_flag = 1; + printf REPORT "Sorry-"; + $unhandled++; + } + + if ($result =~ "parse") { + $err_flag = 1; + printf REPORT "Parse Err-"; + $parse++; + } + + if ($result =~ "Unable" ) { + $err_flag = 1; + printf REPORT "Unable-"; + $unable++; + } + + if ($result =~ "Assertion" ) { + $err_flag = 1; + printf REPORT "Assertion-"; + $assertion++; + } + if ($result =~ "CRASHED" ) { + $err_flag = 1; + printf REPORT "Ran-CORE DUMP-"; + $failed++; + } + + if($testtype{$testname} ne "CO") { + if ($result =~ "PASSED" ) { + printf REPORT "Ran-PASSED-"; + $passed++; + } + + if ($result =~ "FAILED" ) { + printf REPORT "Ran-FAILED-"; + $failed++; + } + + } else { + if(-z $lpath) { + printf REPORT "CO-PASSED-"; + $passed++; + } else { + printf REPORT "CO-FAILED-"; + $failed++; + } + } + + printf REPORT "\n"; + } else { + printf REPORT "\n"; + } + } + } + $total = $pass_count + $no_compile + $no_run + $crash_count; + print REPORT "Tests passed: $passed, failed: $failed, Unhandled: $unhandled Unable: $unable, Assert: $assertion, Parse Errs: $parse"; + print "Tests passed: $passed, failed: $failed, Unhandled: $unhandled Unable: $unable, Assert: $assertion Parse Errs: $parse\n"; + + close (REPORT); +} diff --git a/ivtest/obsolete/vvptests/vvpsources/assignx0.vp b/ivtest/obsolete/vvptests/vvpsources/assignx0.vp new file mode 100644 index 000000000..fc80ce38f --- /dev/null +++ b/ivtest/obsolete/vvptests/vvpsources/assignx0.vp @@ -0,0 +1,61 @@ +:vpi_time_precision + 0; +:vpi_module "system"; + + +; Copyright (c) 2001 Stephen Williams (steve@icarus.com) +; +; This source code is free software; you can redistribute it +; and/or modify it in source code form under the terms of the GNU +; General Public License as published by the Free Software +; Foundation; either version 2 of the License, or (at your option) +; any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program; if not, write to the Free Software +; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +; +; This program tests the indexed %assign statement. +; + +S_main .scope module, "main"; + +V_test .var "test", 3, 0; + +start %set V_test[0], 0; + %set V_test[1], 0; + %set V_test[2], 0; + %set V_test[3], 0; + + %ix/load 0, 3; + %assign/x0 V_test, 1, 1; + + %delay 2; + + %load 8, V_test[0]; + %load 9, V_test[1]; + %load 10, V_test[2]; + %load 11, V_test[3]; + + %mov 12, 0, 1; + %mov 13, 0, 1; + %mov 14, 0, 1; + %mov 15, 1, 1; + + %cmp/u 8, 12, 4; + %jmp/1 passed, 6; + + %vpi_call "$display", "FAILED"; + %vpi_call "$finish"; + %end; + +passed %vpi_call "$display", "PASSED"; + %vpi_call "$finish"; + %end; + + .thread start; diff --git a/ivtest/obsolete/vvptests/vvpsources/force.vp b/ivtest/obsolete/vvptests/vvpsources/force.vp new file mode 100644 index 000000000..a3297bbe4 --- /dev/null +++ b/ivtest/obsolete/vvptests/vvpsources/force.vp @@ -0,0 +1,72 @@ +#! /usr/bin/env vvp -v +:vpi_time_precision + 0; +:vpi_module "system"; +S_test .scope module, "test"; +V_test.val1 .var "val1", 3, 0; +V_test.val2 .var "val2", 3, 0; +V_test._L0 .net "_L0", 1, 0, C<0>, C<1>; +V_test._L3 .net "_L3", 0, 0, C<0>; +V_test._L4 .net "_L4", 0, 0, L_test._L5; +L_test._L5/L0C0 .functor XNOR, V_test.val1[0], C<0>, C<0>, C<0>; +L_test._L5/L0C1 .functor XNOR, V_test.val1[1], C<1>, C<0>, C<0>; +L_test._L5/L0C2 .functor XNOR, V_test.val1[2], C<0>, C<0>, C<0>; +L_test._L5/L0C3 .functor XNOR, V_test.val1[3], C<0>, C<0>, C<0>; +L_test._L5 .functor AND, L_test._L5/L0C0, L_test._L5/L0C1, L_test._L5/L0C2, L_test._L5/L0C3; + +fofu .force V_test.val2, L_test._L5, C<0>, C<0>, C<0>; + + .scope S_test; +T_0 ; + %set V_test.val2[0], 0; + %set V_test.val2[1], 0; + %set V_test.val2[2], 0; + %set V_test.val2[3], 0; + %set V_test.val1[0], 0; + %set V_test.val1[1], 1; + %set V_test.val1[2], 0; + %set V_test.val1[3], 0; + %delay 50; + %load 8, V_test.val2[0]; + %load 9, V_test.val2[1]; + %load 10, V_test.val2[2]; + %load 11, V_test.val2[3]; + %mov 12, 1, 1; + %mov 13, 0, 3; + %cmp/u 8, 12, 4; + %inv 6, 1; + %mov 8, 6, 1; + %jmp/0xz T_0.0, 8; + %vpi_call "$display", "force FAILED"; + %jmp T_0.1; +T_0.0 ; + %vpi_call "$display", "force PASSED"; +T_0.1 ; + %delay 50; + %load 8, V_test.val2[0]; + %load 9, V_test.val2[1]; + %load 10, V_test.val2[2]; + %load 11, V_test.val2[3]; + %mov 12, 1, 1; + %mov 13, 0, 3; + %cmp/u 8, 12, 4; + %inv 6, 1; + %mov 8, 6, 1; + %jmp/0xz T_0.2, 8; + %vpi_call "$display", "release PASSED"; + %jmp T_0.3; +T_0.2 ; + %vpi_call "$display", "release FAILED"; +T_0.3 ; + %end; + .thread T_0; + .scope S_test; +T_1 ; + %delay 20; + %force fofu[0], 4; + %delay 40; + %release V_test.val2[0]; + %release V_test.val2[1]; + %release V_test.val2[2]; + %release V_test.val2[3]; + %end; + .thread T_1; diff --git a/ivtest/obsolete/vvptests/vvpsources/force0.vp b/ivtest/obsolete/vvptests/vvpsources/force0.vp new file mode 100644 index 000000000..f07d2d21e --- /dev/null +++ b/ivtest/obsolete/vvptests/vvpsources/force0.vp @@ -0,0 +1,28 @@ +#! /home/drjury/stephan/icarus/lib/ivl/../../bin/vvp +:vpi_time_precision + 0; +:vpi_module "system"; +S_ftest .scope module, "ftest"; +V_ftest.a .net "a", 0, 0, C<0>; +V_ftest.b .net "b", 0, 0, C<0>; +V_ftest._L4 .net "_L4", 0, 0, C<1>; + +fofu .force V_ftest.a, C<1> ; + + .scope S_ftest; +T_0 ; + + %force fofu, 1 ; + + %delay 1; + %load 8, V_ftest.b[0]; + %cmp/u 8, 0, 1; + %inv 6, 1; + %mov 8, 6, 1; + %jmp/0xz T_0.0, 8; + %vpi_call "$display", "FAILED: %b %b", V_ftest.a, V_ftest.b; + %jmp T_0.1; +T_0.0 ; + %vpi_call "$display", "PASSED: %b %b", V_ftest.a, V_ftest.b; +T_0.1 ; + %end; + .thread T_0; diff --git a/ivtest/obsolete/vvptests/vvpsources/force_pca.vp b/ivtest/obsolete/vvptests/vvpsources/force_pca.vp new file mode 100644 index 000000000..b12b4d066 --- /dev/null +++ b/ivtest/obsolete/vvptests/vvpsources/force_pca.vp @@ -0,0 +1,202 @@ +#! /home/drjury/stephan/icarus/lib/ivl/../../bin/vvp +:vpi_time_precision + 0; +:vpi_module "system"; +S .scope module, "test"; +V.force_expr .var "force_expr", 1, 0; +V.pca_expr .var "pca_expr", 1, 0; +V.tgt .var "tgt", 1, 0; +S.test .scope task, "test.test", S; +V.test.errors .var "errors", 0, 0; +V.test.expect .var "expect", 1, 0; + +fofu .force V.tgt, V.force_expr[0], V.force_expr[1]; + +TD.test ; + %delay 1; + %load 8, V.tgt[0]; + %load 9, V.tgt[1]; + %load 10, V.test.expect[0]; + %load 11, V.test.expect[1]; + %cmp/u 8, 10, 2; + %inv 6, 1; + %mov 8, 6, 1; + %jmp/0xz T_0.0, 8; + %vpi_call "$display", "%b FAILED: expect %b", V.tgt, V.test.expect; + %set V.test.errors[0], 1; + %jmp T_0.1; +T_0.0 ; + %vpi_call "$display", "%b", V.tgt; +T_0.1 ; + %end; + .scope S; +T_1 ; + %set V.test.errors[0], 0; + %end; + .thread T_1; + .scope S; +T_2 ; + %vpi_call "$dumpvars"; + %set V.tgt[0], 0; + %set V.tgt[1], 0; + %set V.pca_expr[0], 1; + %set V.pca_expr[1], 0; + %set V.force_expr[0], 0; + %set V.force_expr[1], 0; + %set V.test.expect[0], 0; + %set V.test.expect[1], 0; + %fork TD.test, S.test; + %join; + + %cassign V.tgt[0], V.pca_expr[0]; + %cassign V.tgt[1], V.pca_expr[1]; + + %load 8, V.pca_expr[0]; + %load 9, V.pca_expr[1]; + %set V.test.expect[0], 8; + %set V.test.expect[1], 9; + %fork TD.test, S.test; + %join; + %set V.pca_expr[0], 1; + %set V.pca_expr[1], 1; + %load 8, V.pca_expr[0]; + %load 9, V.pca_expr[1]; + %set V.test.expect[0], 8; + %set V.test.expect[1], 9; + %fork TD.test, S.test; + %join; + + %force fofu, 2; + + %load 8, V.force_expr[0]; + %load 9, V.force_expr[1]; + %set V.test.expect[0], 8; + %set V.test.expect[1], 9; + %fork TD.test, S.test; + %join; + %set V.force_expr[0], 0; + %set V.force_expr[1], 1; + %load 8, V.force_expr[0]; + %load 9, V.force_expr[1]; + %set V.test.expect[0], 8; + %set V.test.expect[1], 9; + %fork TD.test, S.test; + %join; + + %release V.tgt[0]; + %release V.tgt[1]; + + %load 8, V.pca_expr[0]; + %load 9, V.pca_expr[1]; + %set V.test.expect[0], 8; + %set V.test.expect[1], 9; + %fork TD.test, S.test; + %join; + + %deassign V.tgt[0], 2; + + %load 8, V.pca_expr[0]; + %load 9, V.pca_expr[1]; + %set V.test.expect[0], 8; + %set V.test.expect[1], 9; + %fork TD.test, S.test; + %join; + + %set V.pca_expr[0], 1; + %set V.pca_expr[1], 0; + %set V.test.expect[0], 1; + %set V.test.expect[1], 1; + %fork TD.test, S.test; + %join; + + %cassign V.tgt[0], V.pca_expr[0]; + %cassign V.tgt[1], V.pca_expr[1]; + + %load 8, V.pca_expr[0]; + %load 9, V.pca_expr[1]; + %set V.test.expect[0], 8; + %set V.test.expect[1], 9; + %fork TD.test, S.test; + %join; + + %force fofu, 2; + + %load 8, V.force_expr[0]; + %load 9, V.force_expr[1]; + %set V.test.expect[0], 8; + %set V.test.expect[1], 9; + %fork TD.test, S.test; + %join; + + %deassign V.tgt[0], 2; + + %load 8, V.force_expr[0]; + %load 9, V.force_expr[1]; + %set V.test.expect[0], 8; + %set V.test.expect[1], 9; + %fork TD.test, S.test; + %join; + + %release V.tgt[0]; + %release V.tgt[1]; + + %load 8, V.pca_expr[0]; + %load 9, V.pca_expr[1]; + %set V.test.expect[0], 8; + %set V.test.expect[1], 9; + %fork TD.test, S.test; + %join; + + %set V.force_expr[0], 1; + %set V.force_expr[1], 1; + + %force fofu, 2; + + %load 8, V.force_expr[0]; + %load 9, V.force_expr[1]; + %set V.test.expect[0], 8; + %set V.test.expect[1], 9; + %fork TD.test, S.test; + %join; + + %cassign V.tgt[0], V.pca_expr[0]; + %cassign V.tgt[1], V.pca_expr[1]; + + %load 8, V.force_expr[0]; + %load 9, V.force_expr[1]; + %set V.test.expect[0], 8; + %set V.test.expect[1], 9; + %fork TD.test, S.test; + %join; + + %release V.tgt[0]; + %release V.tgt[1]; + + %load 8, V.pca_expr[0]; + %load 9, V.pca_expr[1]; + %set V.test.expect[0], 8; + %set V.test.expect[1], 9; + %fork TD.test, S.test; + %join; + + %deassign V.tgt[0], 2; + + %load 8, V.pca_expr[0]; + %load 9, V.pca_expr[1]; + %set V.test.expect[0], 8; + %set V.test.expect[1], 9; + %fork TD.test, S.test; + %join; + + + %load 8, V.test.errors[0]; + %mov 4, 8, 1; + %mov 8, 1, 1; + %jmp/0xz T_2.0, 4; + %mov 8, 0, 1; +T_2.0 ; + %jmp/0xz T_2.1, 8; + %vpi_call "$display", "PASSED"; +T_2.1 ; + %vpi_call "$finish"; + %end; + .thread T_2; diff --git a/ivtest/obsolete/vvptests/vvpsources/hello.vp b/ivtest/obsolete/vvptests/vvpsources/hello.vp new file mode 100644 index 000000000..47835eed3 --- /dev/null +++ b/ivtest/obsolete/vvptests/vvpsources/hello.vp @@ -0,0 +1,8 @@ +#! /usr/bin/env vvp +:vpi_module "system"; +S_main .scope module, "main"; + .scope S_main; +T_0 ; + %vpi_call "$display", "PASSED"; + %end; + .thread T_0; diff --git a/ivtest/obsolete/vvptests/vvpsources/resolvz.vp b/ivtest/obsolete/vvptests/vvpsources/resolvz.vp new file mode 100644 index 000000000..8ce1aa479 --- /dev/null +++ b/ivtest/obsolete/vvptests/vvpsources/resolvz.vp @@ -0,0 +1,84 @@ +:vpi_module "system"; + +; Copyright (c) 2001 Stephen Williams (steve@icarus.com) +; +; This source code is free software; you can redistribute it +; and/or modify it in source code form under the terms of the GNU +; General Public License as published by the Free Software +; Foundation; either version 2 of the License, or (at your option) +; any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program; if not, write to the Free Software +; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + + +; This program tests the .resolv functor. It works by sending a few +; variables into the .resolv object and watching what it does. + +main .scope module, "main" ; + +main.a .var "a", 0, 0; +main.b .var "b", 0, 0; + +main.x .resolv tri, main.a, main.b, C, C; +main.out .net "out", 0, 0, main.x; + +code ; + %set main.a, 3; a = 1'bz + %set main.b, 3; b = 1'bz + %delay 1; + %load 8, main.x; + %cmp/u 8, 3, 1; if (x !== 1'bz) ... + %jmp/1 is_a_z, 6; + + %vpi_call "$display", "FAILED (z) -- main.x = %b", main.out; + %vpi_call "$finish"; + %end; +is_a_z ; ... endif + + %set main.a, 1; a = 1'b1; + %delay 1; + %load 8, main.x; + %cmp/u 8, 1, 1; if (x !== 1'b1) ... + %jmp/1 is_a_1, 6; + + %vpi_call "$display", "FAILED (1) -- main.x = %b", main.out; + %vpi_call "$finish"; + %end; +is_a_1 ; + + %set main.b, 0; b = 1'b0; + %delay 1; + %load 8, main.x; + %cmp/u 8, 2, 1; if (x !== 1'bx) ... + %jmp/1 is_a_x, 6; + + %vpi_call "$display", "FAILED (x) -- main.x = %b", main.out; + %vpi_call "$finish"; + %end; +is_a_x ; + + + %set main.a, 0; a = 1'bz; + %delay 1; + %load 8, main.x; + %cmp/u 8, 0, 1; if (x !== 1'b0) ... + %jmp/1 is_a_0, 6; + + %vpi_call "$display", "FAILED (0) -- main.x = %b", main.out; + %vpi_call "$finish"; + %end; +is_a_0 ; + +; Done. If I get here, it passed all the tests. + + %vpi_call "$display", "PASSED"; + %end; + + .thread code; diff --git a/ivtest/perl-lib/Diff.pm b/ivtest/perl-lib/Diff.pm new file mode 100644 index 000000000..ce11ff61e --- /dev/null +++ b/ivtest/perl-lib/Diff.pm @@ -0,0 +1,132 @@ +# +# Module for comparing expected and actual output of tests. +# It knows how to skip valgrind output ^==\d+== or ^**\d+** +# + +package Diff; + +use strict; +use warnings; + +our $VERSION = '1.00'; + +use base 'Exporter'; + +our @EXPORT = qw(diff); + +# +# We only need a simple diff, but we need to strip \r at the end of line +# and we need to ignore the valgrind output. +# +sub diff { + my ($gold, $log, $skip, $unordered) = @_; + my ($diff, $gline, $lline); + $diff = 0; + + # + # If we do not have a gold file then we just look for a log file line + # with just PASSED on it to indicate that the test worked correctly. + # + if ($gold eq "") { + open (LOG, "<$log") or do { + warn "Error: unable to open $log for reading.\n"; + return 1; + }; + + $diff = 1; + # Loop on the log file lines looking for a "passed" by it self. + # For VHDL tests we need to ignore time, filename, severity, etc. + # that GHDL prints for report statments + foreach $lline () { + if ($lline =~ /^\s*passed\s*$/i) { + $diff = 0; + } + elsif ($lline =~ /@\d+\w+:\(report note\): passed\s*$/i) { + $diff = 0; + } + } + + close (LOG); + } else { + open (GOLD, "<$gold") or do { + warn "Error: unable to open $gold for reading.\n"; + return 1; + }; + open (LOG, "<$log") or do { + warn "Error: unable to open $log for reading.\n"; + return 1; + }; + + if ($unordered) { + my @glines = sort map { s/\r\n$/\n/; $_ } ; + my @llines = sort map { s/\r\n$/\n/; $_ } ; + + my $gindex = 0; + my $lindex = 0; + while ($gindex < @glines) { + # Skip lines from valgrind ^==\d+== or ^**\d+** + while ($lindex < @llines && $llines[$lindex] =~ m/^(==|\*\*)\d+(==|\*\*)/) { + $lindex++ + } + if ($lindex == @llines) { + $diff = 1; + last; + } + # Skip initial lines if needed. + if ($skip > 0) { + $lindex++; + $skip--; + next; + } + if ($glines[$gindex] ne $llines[$lindex]) { + $diff = 1; + last; + } + $gindex++; + $lindex++; + } + + # Check to see if the log file has extra lines. + while ($lindex < @llines && $llines[$lindex] =~ m/^(==|\*\*)\d+(==|\*\*)/) { + $lindex++ + } + $diff = 1 if $lindex < @llines; + } else { + # Loop on the gold file lines. + foreach $gline () { + if (eof LOG) { + $diff = 1; + last; + } + $lline = ; + # Skip lines from valgrind ^==\d+== or ^**\d+** + while ($lline =~ m/^(==|\*\*)\d+(==|\*\*)/) { + $lline = ; + } + # Skip initial lines if needed. + if ($skip > 0) { + $skip--; + next; + } + $gline =~ s/\r\n$/\n/; # Strip at the end of line. + $lline =~ s/\r\n$/\n/; # Strip at the end of line. + if ($gline ne $lline) { + $diff = 1; + last; + } + } + + # Check to see if the log file has extra lines. + while (!eof LOG and !$diff) { + $lline = ; + $diff = 1 if ($lline !~ m/^(==|\*\*)\d+(==|\*\*)/); + } + } + close (LOG); + close (GOLD); + } + + return $diff; +} + +1; # Module loaded OK diff --git a/ivtest/perl-lib/Environment.pm b/ivtest/perl-lib/Environment.pm new file mode 100644 index 000000000..492637193 --- /dev/null +++ b/ivtest/perl-lib/Environment.pm @@ -0,0 +1,105 @@ +# +# Module for processing command line arguments, etc. +# + +package Environment; + +use strict; +use warnings; + +our $VERSION = '1.03'; + +use base 'Exporter'; + +our @EXPORT = qw(get_args get_regress_fn get_ivl_version); + +use constant DEF_REGRESS_FN => './regress.list'; # Default regression list. +use constant DEF_SUFFIX => ''; # Default suffix. +use constant DEF_STRICT => 0; # Default strict option. +use constant DEF_WITH_VALG => 0; # Default valgrind usage (keep this off). +use constant DEF_FORCE_SV => 0; # Default is use the generation supplied. + +use Getopt::Long; + +# +# Get the executable/etc. suffix. +# +sub get_args { + my $suffix = DEF_SUFFIX; + my $strict = DEF_STRICT; + my $with_valg = DEF_WITH_VALG; + my $force_sv = DEF_FORCE_SV; + + if (!GetOptions("suffix=s" => \$suffix, + "strict" => \$strict, + "with-valgrind" => \$with_valg, + "force-sv" => \$force_sv, + "help" => \&usage)) { + die "Error: Invalid argument(s).\n"; + } + + return ($suffix, $strict, $with_valg, $force_sv); +} + +sub usage { + my $def_sfx = DEF_SUFFIX; + my $def_opt = DEF_STRICT ? "yes" : "no"; + my $def_reg_fn = DEF_REGRESS_FN; + my $def_with_valg = DEF_WITH_VALG ? "on" : "off"; + my $def_force_sv = DEF_FORCE_SV ? "yes" : "no"; + warn "$0 usage:\n\n" . + " --suffix= # The Icarus executable suffix, " . + "default \"$def_sfx\".\n" . + " --strict # Force strict standard compliance, " . + "default \"$def_opt\".\n" . + " --with-valgrind # Run the test suite with valgrind, " . + "default \"$def_with_valg\".\n" . + " --force-sv # Force tests to be run as SystemVerilog, " . + "default \"$def_force_sv\".\n" . + " # The regression file, " . + "default \"$def_reg_fn\".\n\n"; + exit; +} + +# +# Get the name of the regression list file. Either the default +# or the file specified in the command line arguments. +# +sub get_regress_fn { + my $regress_fn = DEF_REGRESS_FN; + + # Is there a command line argument (alternate regression list)? + if ($#ARGV != -1) { + $regress_fn = $ARGV[0]; + -e "$regress_fn" or + die "Error: command line regression file $regress_fn doesn't exist.\n"; + -f "$regress_fn" or + die "Error: command line regression file $regress_fn is not a file.\n"; + -r "$regress_fn" or + die "Error: command line regression file $regress_fn is not ". + "readable.\n"; + if ($#ARGV > 0) { + warn "Warning: only using first file argument to script.\n"; + } + } + + return $regress_fn; +} + +# +# Get the current version from iverilog. +# +sub get_ivl_version { + my $sfx = shift(@_); + if (`iverilog$sfx -V` =~ /^Icarus Verilog version (\d+)\.(\d+)/) { + if ($1 == 0) { + return $1.".".$2; + } else { + return $1; + } + } else { + die "Failed to get version from iverilog$sfx -V output"; + } +} + +1; # Module loaded OK diff --git a/ivtest/perl-lib/RegressionList.pm b/ivtest/perl-lib/RegressionList.pm new file mode 100644 index 000000000..a089b4d18 --- /dev/null +++ b/ivtest/perl-lib/RegressionList.pm @@ -0,0 +1,203 @@ +# +# Module for parsing and loading regression test lists. +# + +package RegressionList; + +use strict; +use warnings; + +our $VERSION = '1.01'; + +use base 'Exporter'; + +our @EXPORT = qw(read_regression_list @testlist %srcpath %testtype + %args %plargs %diff %gold %unordered %testmod %offset); + +# Properties of each test. +# It may be nicer to have read_regression_list return an array +# of hashes with these as keys. +our (@testlist, %srcpath, %testtype, %args, %plargs, + %diff, %gold, %unordered, %testmod, %offset) = (); + +# +# Parses the regression list file +# +# Parameters: +# $regress_fn = file name to read tests from. +# $ver = iverilog version. +# +# (from left-to-right in regression file): +# +# test_name type,opt_ivl_args test_dir opt_module_name log/gold_file +# +# type can be: +# normal +# CO = compile only. +# CE = compile error. +# CN = compile null. +# RE = runtime error. +# EF = expected fail. +# NI = not implemented. +# +sub read_regression_list { + my $regress_fn = shift + or die "No regression list file name specified"; + my $ver = shift + or die "No iverilog version specified"; + my $force_sv = shift; + my $opt = shift; + + my ($line, @fields, $tname, $tver, %nameidx, $options); + open (REGRESS_LIST, "<$regress_fn") or + die "Error: unable to open $regress_fn for reading.\n"; + + while ($line = ) { + # can't use chomp here - in MSYS2 it only consumes the LF, not the CR + $line =~ s/\r?\n?$//; + # recognise a trailing '\' as a line continuation + if ($line =~ s/\\$//) { + my $next_line = ; + $next_line =~ s/^\s+//; + $line .= $next_line; + redo unless eof(REGRESS_LIST); + } + next if ($line =~ /^\s*#/); # Skip comments. + next if ($line =~ /^\s*$/); # Skip blank lines. + + $line =~ s/#.*$//; # Strip in line comments. + $line =~ s/\s+$//; # Strip trailing white space. + + @fields = split(' ', $line); + if (@fields < 2) { + die "Error: $fields[0] must have at least 3 fields.\n"; + } + + $tname = $fields[0]; + if ($tname =~ /:/) { + ($tver, $tname) = split(":", $tname); + # Skip if this is not our version or option. + next if (($tver ne "v$ver") && ($tver ne $opt)); + } else { + next if (exists($testtype{$tname})); # Skip if already defined. + } + + # Get the test type and the iverilog argument(s). Separate the + # arguments with a space. + if ($fields[1] =~ ',') { + ($testtype{$tname},$args{$tname}) = split(',', $fields[1], 2); + if ($args{$tname} =~ ',') { + my @args = split(',', $args{$tname}); + $plargs{$tname} = join(' ', grep(/^\+/, @args)); + $args{$tname} = join(' ', grep(!/^\+/, @args)); + } elsif ($args{$tname} =~ /^\+/) { + $plargs{$tname} = $args{$tname}; + $args{$tname} = ""; + } else { + $plargs{$tname} = ""; + } + } else { + $testtype{$tname} = $fields[1]; + $plargs{$tname} = ""; + $args{$tname} = ""; + } + if ($opt ne "std") { + $args{$tname} = $opt . $args{$tname}; + } + + $srcpath{$tname} = $fields[2]; + $srcpath{$tname} = "" if (!defined($srcpath{$tname})); + + # The four field case. + if (@fields == 4) { + if ($fields[3] =~ s/^diff=//) { + $testmod{$tname} = "" ; + ($diff{$tname}, $gold{$tname}, $offset{$tname}) = + split(':', $fields[3]); + # Make sure this is numeric if it is not given. + if (!$offset{$tname}) { + $offset{$tname} = 0; + } + } elsif ($fields[3] =~ s/^gold=//) { + $testmod{$tname} = "" ; + $diff{$tname} = ""; + $gold{$tname} = "gold/$fields[3]"; + $offset{$tname} = 0; + } elsif ($fields[3] =~ s/^unordered=//) { + $testmod{$tname} = "" ; + $diff{$tname} = ""; + $gold{$tname} = "gold/$fields[3]"; + $unordered{$tname} = 1; + $offset{$tname} = 0; + } else { + $testmod{$tname} = $fields[3]; + $diff{$tname} = ""; + $gold{$tname} = ""; + $offset{$tname} = 0; + } + # The five field case. + } elsif (@fields == 5) { + if ($fields[4] =~ s/^diff=//) { + $testmod{$tname} = "" ; + ($diff{$tname}, $gold{$tname}, $offset{$tname}) = + split(':', $fields[4]); + # Make sure this is numeric if it is not given. + if (!$offset{$tname}) { + $offset{$tname} = 0; + } + } elsif ($fields[4] =~ s/^gold=//) { + $testmod{$tname} = "" ; + $diff{$tname} = ""; + $gold{$tname} = "gold/$fields[4]"; + $offset{$tname} = 0; + } elsif ($fields[4] =~ s/^unordered=//) { + $testmod{$tname} = "" ; + $diff{$tname} = ""; + $gold{$tname} = "gold/$fields[4]"; + $unordered{$tname} = 1; + $offset{$tname} = 0; + } + } else { + $testmod{$tname} = ""; + $diff{$tname} = ""; + $gold{$tname} = ""; + $offset{$tname} = 0; + } + + # If the name exists this is a replacement so skip the original one. + if (exists($nameidx{$tname})) { + splice(@testlist, $nameidx{$tname}, 1, ""); + } + push (@testlist, $tname); + $nameidx{$tname} = @testlist - 1; + + # The generation to use is passed if it does not match + # the default. To make sure the tests are protable we + # use the force SV flag to force all tests to be run + # as the latest SystemVerilog generation. This assumes + # the correct `begin_keywords has been added to the + # various files. + if ($force_sv) { + my $fsv_flags = "-g2012"; + $args{$tname} =~ s/-g2012//; + $args{$tname} =~ s/-g2009//; + $args{$tname} =~ s/-g2005-sv//; + $args{$tname} =~ s/-g2005//; + $args{$tname} =~ s/-g2001-noconfig//; + $args{$tname} =~ s/-g2001//; + $args{$tname} =~ s/-g1995//; + $args{$tname} =~ s/-g2x/-gicarus-misc/; # Deprecated for 2001 + $args{$tname} =~ s/-g2//; # Deprecated for 2001 + $args{$tname} =~ s/-g1//; # Deprecated for 1995 + if ($args{$tname}) { + $args{$tname} = "$fsv_flags $args{$tname}"; + } else { + $args{$tname} = "$fsv_flags"; + } + } + } + + close (REGRESS_LIST); +} + +1; # Module loaded OK diff --git a/ivtest/perl-lib/Reporting.pm b/ivtest/perl-lib/Reporting.pm new file mode 100644 index 000000000..31d2f9d5f --- /dev/null +++ b/ivtest/perl-lib/Reporting.pm @@ -0,0 +1,46 @@ +# +# Module for writing to the regression report file. +# + +package Reporting; + +use strict; +use warnings; + +our $VERSION = '1.00'; + +use base 'Exporter'; + +our @EXPORT = qw(open_report_file print_rpt close_report_file); + +use constant DEF_REPORT_FN => './regression_report.txt'; + +$| = 1; # This turns off buffered I/O + +# +# Open the report file for writing. +# If no argument is given, DEF_REPORT_FN is the filename. +# +sub open_report_file { + my $report_fn = shift || DEF_REPORT_FN; + open (REGRESS_RPT, ">$report_fn") or + die "Error: unable to open $report_fn for writing.\n"; +} + +# +# Print the argument to both the normal output and the report file. +# +sub print_rpt { + print @_; + print REGRESS_RPT @_; +} + +# +# Close the report file once we're done with it. +# +sub close_report_file { + close (REGRESS_RPT); +} + + +1; # Module loaded OK diff --git a/ivtest/regress b/ivtest/regress new file mode 100755 index 000000000..619db2cf4 --- /dev/null +++ b/ivtest/regress @@ -0,0 +1,3 @@ +#!/bin/csh +limit coredumpsize 0 +./vvp_reg.pl diff --git a/ivtest/regress-fsv.list b/ivtest/regress-fsv.list new file mode 100644 index 000000000..a6eb46a0e --- /dev/null +++ b/ivtest/regress-fsv.list @@ -0,0 +1,124 @@ +# This test list contains tests that should work using any simulator that +# supports SystemVerilog (1800-2012). + +# +# Copyright (c) 1999-2021 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# Format of the file +# +# testname testtype directory +# +# The is the verilog file name minus an extension. +# +# The can be one of the following: +# +# normal: Normal results expected, i.e it should compile and execute +# producing at least a single line with PASSED. +# +# CO: Compile Only - Compile the file to the default output type. +# +# CN: Compile Null - Compile with the null target. Similar to CO. +# +# CE: Compile with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# RE: Runtime with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# EF: Expected Fail - We EXPECT this test to fail - only use +# with older versions of Icarus. +# +# TE: Translation Error - We EXPECT the translated code to fail - +# only supported in the vlog95 checker. +# +# NI: Not implemented. Only use for version specific tests. +# +# is where the .v file is located. +# +# An optional fourth and fifth argument can be supplied. +# +# The fourth argument may be one of the following. +# +# modulename - Defines the top level module +# gold=filename - Compare a gold file against the +# generated log file. +# unordered=filename - Compare a gold file against the +# generated log file, allowing for lines +# to appear in any order +# diff=filename1:filename2:skip_ln - Compare the two files for equality. +# Skip the first lines or none. +# +# If a is given you can supply a fifth argument for the +# gold or diff commands. +# + +# Some constructs/usage are not errors in SystemVerilog +br1015a normal ivltests +br1027a normal ivltests gold=br1027a-fsv.gold +br1027c normal ivltests gold=br1027c-fsv.gold +br1027e normal ivltests gold=br1027e-fsv.gold +br_gh25a normal ivltests +br_gh25b normal ivltests +br_gh567 normal ivltests +check_constant_3 normal ivltests +function4 normal ivltests +pr1963962 normal ivltests gold=pr1963962-fsv.gold +pr3015421 CE ivltests gold=pr3015421-fsv.gold +resetall normal,-Wtimescale ivltests gold=resetall-fsv.gold +scope2b normal ivltests +sys_func_task_error RE ivltests gold=sys_func_task_error-fsv.gold + +# We do not run synthesis when forcing SystemVerilog so these pass +br995 normal ivltests +br_gh306a normal ivltests +br_gh306b normal ivltests +case5-syn-fail normal ivltests +casesynth7 normal ivltests +casesynth8 normal ivltests +dffsynth normal ivltests +dffsynth8 normal ivltests +memsynth1 normal ivltests +memsynth2 normal ivltests +memsynth3 normal ivltests +memsynth5 normal ivltests +memsynth6 normal ivltests +memsynth7 normal ivltests +memsynth9 normal ivltests +mix_reset normal ivltests + +# These use $abstime() and will actually run correctly with -g2012 (different +# results), but since this file is loaded in sv-tests mark them as NI instead +# of creating the correct gold file +pr2590274a NI ivltests +pr2590274b NI ivltests +pr2590274c NI ivltests + +# These are not supported in Icarus, but are valid SystemVerilog +array_lval_select3a normal ivltests +br605a normal ivltests +br605b normal ivltests +br971 normal ivltests +br1005 normal ivltests +br1015b normal ivltests +br_gh130b normal ivltests +br_gh386d normal ivltests +br_ml20150315b normal ivltests +sv_deferred_assert1 normal ivltests +sv_deferred_assert2 normal ivltests +sv_deferred_assume1 normal ivltests +sv_deferred_assume2 normal ivltests diff --git a/ivtest/regress-ivl1.list b/ivtest/regress-ivl1.list new file mode 100644 index 000000000..53304ecc0 --- /dev/null +++ b/ivtest/regress-ivl1.list @@ -0,0 +1,326 @@ +# This test list contains tests that use Icarus specific language extensions +# and tests for known Icarus limitations and deviations. + +# NOTE: This isn't a complete list - some tests adapt themselves if the +# __ICARUS__ macro is defined. + +# +# Copyright (c) 1999-2021 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# Format of the file +# +# testname testtype directory +# +# The is the verilog file name minus an extension. +# +# The can be one of the following: +# +# normal: Normal results expected, i.e it should compile and execute +# producing at least a single line with PASSED. +# +# CO: Compile Only - Compile the file to the default output type. +# +# CN: Compile Null - Compile with the null target. Similar to CO. +# +# CE: Compile with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# RE: Runtime with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# EF: Expected Fail - We EXPECT this test to fail - only use +# with older versions of Icarus. +# +# TE: Translation Error - We EXPECT the translated code to fail - +# only supported in the vlog95 checker. +# +# NI: Not implemented. Only use for version specific tests. +# +# is where the .v file is located. +# +# An optional fourth and fifth argument can be supplied. +# +# The fourth argument may be one of the following. +# +# modulename - Defines the top level module +# gold=filename - Compare a gold file against the +# generated log file. +# unordered=filename - Compare a gold file against the +# generated log file, allowing for lines +# to appear in any order +# diff=filename1:filename2:skip_ln - Compare the two files for equality. +# Skip the first lines or none. +# +# If a is given you can supply a fifth argument for the +# gold or diff commands. +# + +#------------------------------------------------------------------------------ +# Icarus pre-processor extensions +#------------------------------------------------------------------------------ + +# Escaped defines `` +macro_str_esc normal ivltests gold=macro_str_esc.gold +macro_with_args normal ivltests gold=macro_with_args.gold +mcl1 normal ivltests gold=mcl1.gold +pr622 normal ivltests gold=pr622.gold +pr639 normal ivltests gold=pr639.gold +pr1741212 normal ivltests gold=pr1741212.gold +pr1912112 normal ivltests gold=pr1912112.gold +pr1925360 normal ivltests +repeat1 normal ivltests + +# This just checks whether the pre-processor runs successfully +pr2002443 CO,-E ivltests + +#------------------------------------------------------------------------------ +# Icarus language extensions +#------------------------------------------------------------------------------ + +# $abs, $min and $max to match VAMS abs, min and max +constfunc6_ams normal ivltests +non-polymorphic-abs normal ivltests +pr3270320_ams CE ivltests +test_va_math normal,-mva_math ivltests gold=test_va_math.gold +va_math normal ivltests + +# $abstime from VAMS +abstime normal ivltests +pr2590274a normal ivltests gold=pr2590274.gold +pr2590274b normal ivltests gold=pr2590274.gold +pr2590274c normal,-gspecify ivltests gold=pr2590274.gold + +# $bits +bitsel normal ivltests gold=bitsel.gold +bitsel10 normal ivltests +bitsel2 normal ivltests +bitsel3 normal ivltests +bitsel4 normal ivltests +bitsel5 normal ivltests +bitsel6 normal ivltests +bitsel7 normal ivltests +bitsel8 normal ivltests # pr615 +bitsel9 normal ivltests # pr617 +bitwidth3 normal ivltests +clog2 normal ivltests +clog2-signal normal ivltests +param_vec normal ivltests +param_vec2 normal ivltests +pr498 normal ivltests +pr721 normal ivltests +pr809 normal ivltests +pr809b normal ivltests +pr979 normal ivltests gold=pr979.gold +pr1000 normal ivltests +pr1609611 normal ivltests +pr1750870 normal ivltests +pr1765789 normal ivltests +pr1771903 normal ivltests gold=pr1771903.gold +pr1793749 normal ivltests gold=pr1793749.gold +pr1793749b normal ivltests gold=pr1793749b.gold +pr1861212b normal ivltests gold=pr1861212.gold +pr1864110c normal ivltests gold=pr1864110c.gold +pr1864115 normal ivltests gold=pr1864115.gold +pr2806449 normal ivltests +pr2877555 normal ivltests +real4 normal ivltests +realtobits normal ivltests +specparam1 normal ivltests +specparam2 normal ivltests +tern3 normal ivltests gold=tern3.gold +v2005_math normal ivltests + +# $deposit +deposit normal ivltests +deposit_wire normal ivltests +sysargs normal ivltests + +# $fatal +fatal_et_al normal ivltests gold=fatal_et_al.gold +fatal_et_al2 RE ivltests gold=fatal_et_al2.gold + +# $finish_and_return +plus_arg_string normal,-g2009,\ + +img=test_image.file ivltests + +# $fopena, $fopenr and $fopenw +fileio normal ivltests gold=fileio.gold + +# $is_signed +pr1494799 normal ivltests gold=pr1494799.gold +pr2428890c normal ivltests + +# $ivl_darray_method$to_vec & $ivl_darray_method$from_vec +sv_cast_darray normal,-g2005-sv ivltests + +# $ivl_to_unsigned +br978 normal ivltests +br_ml20150424 normal ivltests + +# $readmempath +pr2509349a normal ivltests gold=pr2509349a.gold +pr2509349b normal ivltests gold=pr2509349b.gold + +# $simparam +simparam normal ivltests + +# $simtime +blocking_repeat_ec normal ivltests +ca_time_smtm normal ivltests gold=ca_time_smtm.gold +nb_array_pv normal ivltests +nb_ec_array normal ivltests +nb_ec_array_pv normal ivltests +nb_ec_pv normal ivltests +nb_ec_pv2 normal ivltests +nb_ec_real normal ivltests +nb_ec_vector normal ivltests +pr2486350 normal ivltests gold=pr2486350.gold +pr534 normal ivltests gold=pr534.gold +stime normal ivltests gold=stime.gold +swrite normal ivltests gold=swrite.gold +time6 normal ivltests +time6b normal ivltests # Rewrote time6 to pass with XL +time6c normal ivltests gold=time6c.gold + +# $sizeof +concat1 normal ivltests # PR#327,372 +concat2 normal ivltests # PR#282 +constconcat1 normal ivltests +constconcat2 normal ivltests +rptconcat2 normal ivltests # Repeat concatenation operation. +sdw_lvalconcat2 normal ivltests + +# bool type +bool1 normal ivltests +compare_bool_reg normal ivltests +constfunc8 normal ivltests + +# Binary ~& and ~| operators +binary_nand normal ivltests +binary_nor normal ivltests + +# real modulus +pr1528093 normal ivltests + +# wire real +br_gh456 normal,-g2012 ivltests +ca_64delay normal ivltests gold=ca_64delay.gold +ca_time_real normal ivltests gold=ca_time_real.gold +ca_var_delay normal ivltests +cast_real_signed normal ivltests +cast_real_unsigned normal ivltests +delayed_sfunc normal,-gspecify ivltests gold=delayed_sfunc.gold +pr1861212c normal ivltests gold=pr1861212.gold +pr1864110a normal ivltests gold=pr1864110a.gold +pr1864110b normal ivltests gold=pr1864110b.gold +pr1873372 normal ivltests gold=pr1873372.gold +pr1880003 normal ivltests +pr1898293 normal ivltests +pr2123158 normal ivltests +pr2453002b normal ivltests +pr2456943 normal ivltests +pr2715748 normal ivltests gold=pr2715748.gold +pr2806474 normal ivltests +pr2976242 normal ivltests +pr2976242b normal ivltests +pr2976242c CE ivltests gold=pr2976242c.gold +real8 normal ivltests +real_array normal ivltests +real_array_nb normal ivltests +real_concat_invalid1 CE ivltests +real_mod_in_ca normal ivltests +real_op_fail CE ivltests +real_pulse_clean normal ivltests +real_pwr_in_ca normal ivltests +real_select_invalid CE ivltests +real_wire_array normal ivltests +real_wire_force_rel normal ivltests +tern8 normal ivltests + +# Two-state wires +br_gh99e normal,-g2009 ivltests +pull371 normal,-g2012 ivltests +sv-2val-nets normal,-g2009 ivltests + +# Left aligned formats +pr2476430 normal ivltests + +# A % at the end of the format string is displayed a a % +eofmt_percent normal ivltests gold=eofmt_percent.gold + +# Command line parameters +br_gh377 normal,-Ptest.name= ivltests gold=br_gh377.gold +cmdline_parm1 normal,-Pmain.foo=2 ivltests + +# Dumping array words +array_dump normal ivltests diff=work/array_dump.vcd:gold/array_dump.vcd.gold:2 +pr2859628 normal ivltests diff=work/pr2859628.vcd:gold/pr2859628.vcd.gold:2 + +# Icarus supports integer values larger than 32-bits +big_int normal ivltests # PR#405 +ca_pow_signed normal ivltests +urand normal ivltests gold=urand.gold + +# Avoiding time-0 races +race normal ivltests + +#------------------------------------------------------------------------------ +# Icarus limitations +#------------------------------------------------------------------------------ + +# Limited support for event expressions in automatic scopes +automatic_error4 CE ivltests + +# These are not currently supported in Icarus +# Also update the regress-fsv.list since it has these marked as normal +array_lval_select3a CE ivltests +br605a EF ivltests +br605b EF ivltests +br971 EF ivltests +br1005 CE,-g2009 ivltests +br1015b CE,-g2009 ivltests +br_gh130b CE,-g2009 ivltests +br_gh386d CE,-g2009 ivltests +br_ml20150315b CE,-g2009 ivltests +sv_deferred_assert1 CE,-g2009 ivltests gold=sv_deferred_assert1.gold +sv_deferred_assert2 CE,-g2009 ivltests gold=sv_deferred_assert2.gold +sv_deferred_assume1 CE,-g2009 ivltests gold=sv_deferred_assume1.gold +sv_deferred_assume2 CE,-g2009 ivltests gold=sv_deferred_assume2.gold + +#------------------------------------------------------------------------------ +# Icarus deviations +#------------------------------------------------------------------------------ + +# Icarus still allows (implicit) declaration after use in some circumstances. +pr1909940 normal ivltests +pr1909940b normal ivltests + +# Icarus allows hierarchical references to unnamed generate blocks. +# We should add a warning about this, as it's not strictly allowed. +unnamed_generate_block normal ivltests gold=unnamed_generate_block.gold + +#------------------------------------------------------------------------------ +# Implementation defined behaviour +#------------------------------------------------------------------------------ + +# From IEEE 1364-2005 section 5.2.1: +# NOTE 2 -- Bit-select or part-select indices that are outside of the declared +# range may be flagged as a compile time error. +br_gh497b CE ivltests gold=br_gh497b.gold +br_gh497d CE ivltests gold=br_gh497d.gold +br_gh497f CE ivltests gold=br_gh497f.gold diff --git a/ivtest/regress-ivl2.list b/ivtest/regress-ivl2.list new file mode 100644 index 000000000..c967344ac --- /dev/null +++ b/ivtest/regress-ivl2.list @@ -0,0 +1,97 @@ +# This test list contains tests that give different results when iverilog +# is run without the -gstrict-expr-width option or vvp is run without the +# -compatible option. + +# +# Copyright (c) 1999-2014 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# Format of the file +# +# testname testtype directory +# +# The is the verilog file name minus an extension. +# +# The can be one of the following: +# +# normal: Normal results expected, i.e it should compile and execute +# producing at least a single line with PASSED. +# +# CO: Compile Only - Compile the file to the default output type. +# +# CN: Compile Null - Compile with the null target. Similar to CO. +# +# CE: Compile with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# RE: Runtime with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# EF: Expected Fail - We EXPECT this test to fail - only use +# with older versions of Icarus. +# +# TE: Translation Error - We EXPECT the translated code to fail - +# only supported in the vlog95 checker. +# +# NI: Not implemented. Only use for version specific tests. +# +# is where the .v file is located. +# +# An optional fourth and fifth argument can be supplied. +# +# The fourth argument may be one of the following. +# +# modulename - Defines the top level module +# gold=filename - Compare a gold file against the +# generated log file. +# unordered=filename - Compare a gold file against the +# generated log file, allowing for lines +# to appear in any order +# diff=filename1:filename2:skip_ln - Compare the two files for equality. +# Skip the first lines or none. +# +# If a is given you can supply a fifth argument for the +# gold or diff commands. +# + +#------------------------------------------------------------------------------ +# Differences when iverilog is run without -gstrict-expr-width +#------------------------------------------------------------------------------ + +# The standard requires oversized unsized constant numbers to be truncated. +# These tests are specifically testing that such numbers aren't truncated. +pr903 normal ivltests +pr1388974 normal ivltests + +# The standard doesn't support lossless expressions. +br_gh13a normal ivltests gold=br_gh13a.gold +param-width normal ivltests gold=param-width-ivl.gold + +#------------------------------------------------------------------------------ +# Differences when vvp is run without -compatible +#------------------------------------------------------------------------------ + +# Different output when real numbers are displayed without a format specifier. +br_gh383d normal,-g2012 ivltests gold=br_gh383d-ivl.gold +ca_time_real normal ivltests gold=ca_time_real-ivl.gold +delayed_sfunc normal,-gspecify ivltests gold=delayed_sfunc-ivl.gold +localparam_type normal ivltests gold=parameter_type-ivl.gold +parameter_type normal ivltests gold=parameter_type-ivl.gold +pr1701890 normal ivltests gold=pr1701890-ivl.gold +pr1864110a normal ivltests gold=pr1864110a-ivl.gold +pr1864110b normal ivltests gold=pr1864110b-ivl.gold +pr1864115 normal ivltests gold=pr1864115-ivl.gold diff --git a/ivtest/regress-msys2.list b/ivtest/regress-msys2.list new file mode 100755 index 000000000..dd20a4cf2 --- /dev/null +++ b/ivtest/regress-msys2.list @@ -0,0 +1,71 @@ +# This test list is used to override other test lists when running +# on Windows using MSYS2. + +# +# Copyright (c) 1999-2015 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# Format of the file +# +# testname testtype directory +# +# The is the verilog file name minus an extension. +# +# The can be one of the following: +# +# normal: Normal results expected, i.e it should compile and execute +# producing at least a single line with PASSED. +# +# CO: Compile Only - Compile the file to the default output type. +# +# CN: Compile Null - Compile with the null target. Similar to CO. +# +# CE: Compile with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# RE: Runtime with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# EF: Expected Fail - We EXPECT this test to fail - only use +# with older versions of Icarus. +# +# TE: Translation Error - We EXPECT the translated code to fail - +# only supported in the vlog95 checker. +# +# NI: Not implemented. Only use for version specific tests. +# +# is where the .v file is located. +# +# An optional fourth and fifth argument can be supplied. +# +# The fourth argument may be one of the following. +# +# modulename - Defines the top level module +# gold=filename - Compare a gold file against the +# generated log file. +# unordered=filename - Compare a gold file against the +# generated log file, allowing for lines +# to appear in any order +# diff=filename1:filename2:skip_ln - Compare the two files for equality. +# Skip the first lines or none. +# +# If a is given you can supply a fifth argument for the +# gold or diff commands. +# + +# Warning about non-existent /tmp directory +pr2509349a normal ivltests gold=pr2509349a-msys2.gold diff --git a/ivtest/regress-sv.list b/ivtest/regress-sv.list new file mode 100644 index 000000000..7fd724239 --- /dev/null +++ b/ivtest/regress-sv.list @@ -0,0 +1,591 @@ +# This test list contains tests that should work using any simulator that +# supports SystemVerilog (1800-2012). + +# +# Copyright (c) 1999-2021 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# Format of the file +# +# testname testtype directory +# +# The is the verilog file name minus an extension. +# +# The can be one of the following: +# +# normal: Normal results expected, i.e it should compile and execute +# producing at least a single line with PASSED. +# +# CO: Compile Only - Compile the file to the default output type. +# +# CN: Compile Null - Compile with the null target. Similar to CO. +# +# CE: Compile with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# RE: Runtime with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# EF: Expected Fail - We EXPECT this test to fail - only use +# with older versions of Icarus. +# +# TE: Translation Error - We EXPECT the translated code to fail - +# only supported in the vlog95 checker. +# +# NI: Not implemented. Only use for version specific tests. +# +# is where the .v file is located. +# +# An optional fourth and fifth argument can be supplied. +# +# The fourth argument may be one of the following. +# +# modulename - Defines the top level module +# gold=filename - Compare a gold file against the +# generated log file. +# unordered=filename - Compare a gold file against the +# generated log file, allowing for lines +# to appear in any order +# diff=filename1:filename2:skip_ln - Compare the two files for equality. +# Skip the first lines or none. +# +# If a is given you can supply a fifth argument for the +# gold or diff commands. +# + +always4A CE,-g2005-sv ivltests +always4B CE,-g2005-sv ivltests +always_comb normal,-g2005-sv ivltests +always_comb_fail CE,-g2005-sv ivltests +always_comb_fail3 CE,-g2005-sv ivltests +always_comb_fail4 CE,-g2005-sv ivltests +always_comb_no_sens nornal,-g2005-sv ivltests gold=always_comb_no_sens.gold +always_comb_rfunc nornal,-g2005-sv ivltests +always_comb_trig normal,-g2005-sv ivltests +always_comb_warn normal,-g2005-sv ivltests gold=always_comb_warn.gold +always_ff normal,-g2005-sv ivltests +always_ff_fail CE,-g2005-sv ivltests +always_ff_fail2 CE,-g2005-sv ivltests +always_ff_fail3 CE,-g2005-sv ivltests +always_ff_fail4 CE,-g2005-sv ivltests +always_ff_no_sens CE,-g2005-sv ivltests +always_ff_warn normal,-g2005-sv ivltests gold=always_ff_warn.gold +always_ff_warn_sens normal,-g2005-sv ivltests gold=always_ff_warn_sens.gold +always_latch normal,-g2005-sv ivltests +always_latch_fail CE,-g2005-sv ivltests +always_latch_fail3 CE,-g2005-sv ivltests +always_latch_fail4 CE,-g2005-sv ivltests +always_latch_no_sens CE,-g2005-sv ivltests +always_latch_trig normal,-g2005-sv ivltests +always_latch_warn normal,-g2005-sv ivltests gold=always_latch_warn.gold +array_size normal,-g2005-sv ivltests # test [size] arrays +array_string normal,-g2009 ivltests +array_unpacked_sysfunct normal,-g2005-sv ivltests +array_packed normal,-g2005-sv ivltests +assign_op_concat normal,-g2009 ivltests +assign_op_type normal,-g2009 ivltests +bitp1 normal,-g2005-sv ivltests +bits normal,-g2005-sv ivltests +bits2 normal,-g2005-sv ivltests +br884 normal,-g2009 ivltests +br917a normal,-g2009 ivltests +br917b normal,-g2009 ivltests +br917c normal,-g2009 ivltests +br917d normal,-g2009 ivltests +br921 normal,-g2009 ivltests gold=br921.gold +br932a normal,-g2009 ivltests +br932b normal,-g2009 ivltests +br936 normal,-g2009 ivltests +br956 normal,-g2009 ivltests +br959 normal,-g2009 ivltests +br962 normal,-g2009 ivltests +br963 normal,-g2009 ivltests +br973 normal,-g2009 ivltests +br974a normal,-g2009 ivltests +br974b normal,-g2009 ivltests +br974c normal,-g2009 ivltests +br975 CE,-g2009 ivltests gold=br975.gold +br979 normal,-g2009 ivltests +br991b CE,-g2009 ivltests gold=br991b.gold +br1003a normal,-g2009 ivltests gold=br1003a.gold +br1003b normal,-g2009 ivltests gold=br1003b.gold +br1003c normal,-g2009 ivltests gold=br1003c.gold +br1003d normal,-g2009 ivltests gold=br1003d.gold +br1004 normal,-g2009 ivltests +br1005 normal,-g2009 ivltests gold=br1005.gold +br1015b normal,-g2009 ivltests +br1025 normal,-g2009 ivltests +br1027b normal,-g2009 ivltests gold=br1027b.gold +br1027d normal,-g2009 ivltests gold=br1027d.gold +br1027f normal,-g2009 ivltests gold=br1027f.gold +br_gh4 normal,-g2009 ivltests +br_gh4a normal,-g2009 ivltests +br_gh72a normal,-g2009 ivltests gold=br_gh72a.gold +br_gh72b normal,-g2009 ivltests gold=br_gh72b.gold +br_gh72b_fail CE,-g2009 ivltests gold=br_gh72b_fail.gold +br_gh104a normal,-g2009 ivltests +br_gh104b normal,-g2009 ivltests +br_gh105a normal,-g2009 ivltests gold=br_gh105a.gold +br_gh105b normal,-g2009 ivltests gold=br_gh105b.gold +br_gh112a normal,-g2009 ivltests +br_gh112b normal,-g2009 ivltests +br_gh112c normal,-g2009 ivltests +br_gh112d normal,-g2009 ivltests +br_gh112e normal,-g2009 ivltests +br_gh112f normal,-g2009 ivltests +br_gh129 normal,-g2009 ivltests +br_gh130a CE,-g2009 ivltests +br_gh165 normal,-g2009 ivltests gold=br_gh165.gold +br_gh164a normal,-g2009 ivltests +br_gh164b normal,-g2009 ivltests +br_gh164c normal,-g2009 ivltests +br_gh164d normal,-g2009 ivltests +br_gh164e normal,-g2009 ivltests +br_gh167a normal,-g2009 ivltests +br_gh167b normal,-g2009 ivltests +br_gh177a normal,-g2009 ivltests +br_gh177b normal,-g2009 ivltests +br_gh194 normal,-g2009 ivltests +br_gh219 normal,-g2009 ivltests +br_gh220 normal,-g2009 ivltests +br_gh224 normal,-g2009 ivltests +br_gh226 normal,-g2009 ivltests +br_gh231 normal,-g2009 ivltests +br_gh243 normal,-g2009 ivltests +br_gh265 CE,-g2009 ivltests gold=br_gh265.gold +br_gh277b normal,-g2009 ivltests +br_gh280 normal,-g2009 ivltests +br_gh281 normal,-g2012 ivltests +br_gh281b normal,-g2012 ivltests +br_gh289a normal,-g2009 ivltests +br_gh289b normal,-g2009 ivltests +br_gh289c normal,-g2009 ivltests +br_gh289d normal,-g2009 ivltests gold=br_gh289d.gold +br_gh337 normal,-g2009 ivltests +br_gh361 normal,-g2009 ivltests +br_gh365 normal,-g2009 ivltests gold=br_gh365.gold +br_gh366 normal,-g2009 ivltests gold=br_gh366.gold +br_gh368 normal,-g2009 ivltests gold=br_gh368.gold +br_gh374 normal,-g2009 ivltests gold=br_gh374.gold +br_gh386a normal,-g2009 ivltests +br_gh386b normal,-g2009 ivltests +br_gh386c CE,-g2009 ivltests +br_gh388 normal,-g2009 ivltests gold=br_gh388.gold +br_gh391 normal,-g2009 ivltests gold=br_gh391.gold +br_gh411 normal,-g2009 ivltests +br_gh418 normal,-g2009 ivltests +br_gh433 normal,-g2009 ivltests gold=br_gh433.gold +br_gh437 normal,-g2009 ivltests +br_gh440 CE,-g2009 ivltests gold=br_gh440.gold +br_gh443 normal,-g2009 ivltests +br_gh445 normal,-g2009 ivltests +br_gh461 normal,-g2009 ivltests +br_gh477 normal,-g2009 ivltests +br_gh478 normal,-g2009 ivltests +br_gh498 normal,-g2009 ivltests +br_gh508a normal,-g2009 ivltests +br_gh527 normal,-g2009 ivltests +br_gh530 CO,-g2009 ivltests +br_gh540 normal,-g2009 ivltests +br_gh553 normal,-g2009 ivltests +br_gh556 normal,-g2009 ivltests +br_gh568 normal,-g2009 ivltests +br_ml20171017 normal,-g2009 ivltests +br_ml20180227 CE,-g2009 ivltests +br_ml20180309a normal,-g2009 ivltests +br_ml20180309b normal,-g2009 ivltests +br_ml20181012a CE,-g2009 ivltests +br_ml20181012b CE,-g2009 ivltests +br_ml20181012c CE,-g2009 ivltests +br_ml20181012d CE,-g2009 ivltests +br_ml20191221 normal,-g2009 ivltests +br_mw20200501 normal,-g2009 ivltests +case_priority normal,-g2005-sv ivltests gold=case_priority.gold +case_unique normal,-g2005-sv ivltests gold=case_unique.gold +cast_real normal,-g2005-sv ivltests +cfunc_assign_op_mixed normal,-g2009 ivltests +cfunc_assign_op_pv normal,-g2009 ivltests +cfunc_assign_op_real normal,-g2009 ivltests +cfunc_assign_op_vec normal,-g2009 ivltests +clkgen_bit normal,-g2009 ivltests +clkgen_logic normal,-g2009 ivltests +clkgen_net normal,-g2009 ivltests +clkgen_reg normal,-g2009 ivltests +disable_fork_cmd normal,-g2009 ivltests +display_bug normal,-g2009 ivltests gold=display_bug.gold +edge normal,-g2009 ivltests +enum_base_range normal,-g2005-sv ivltests +enum_elem_ranges normal,-g2005-sv ivltests +enum_dims_invalid CE,-g2005-sv ivltests +enum_next normal,-g2005-sv ivltests +enum_ports normal,-g2005-sv ivltests +enum_test1 normal,-g2005-sv ivltests +enum_test2 normal,-g2005-sv ivltests +enum_test3 CE,-g2005-sv ivltests +enum_test4 normal,-g2005-sv ivltests +enum_test5 CE,-g2005-sv ivltests +enum_test6 CE,-g2005-sv ivltests +enum_test7 CE,-g2005-sv ivltests +enum_test8 normal,-g2005-sv ivltests +enum_value_expr normal,-g2005-sv ivltests +enum_values normal,-g2005-sv ivltests +escaped_macro_name normal,-g2009 ivltests gold=escaped_macro_name.gold +extra_semicolon normal,-g2005-sv ivltests +fileline normal,-g2009 ivltests gold=fileline.gold +fileline2 normal,-g2009 ivltests gold=fileline2.gold +final normal,-g2005-sv ivltests gold=final.gold +final2 normal,-g2005-sv ivltests gold=final2.gold +first_last_num normal,-g2005-sv ivltests +fork_join_any normal,-g2009 ivltests +fork_join_dis normal,-g2009 ivltests +fork_join_none normal,-g2009 ivltests +fr49 normal,-g2009 ivltests +func_init_var1 normal,-g2009 ivltests +func_init_var2 normal,-g2009 ivltests +func_init_var3 normal,-g2009 ivltests +function10 CO,-g2005-sv ivltests +function11 CE,-g2005-sv ivltests +function12 normal,-g2005-sv ivltests gold=function12.gold +genvar_inc_dec normal,-g2009 ivltests +ibit_test normal,-g2005-sv ivltests +ibyte_test normal,-g2005-sv ivltests +iint_test normal,-g2005-sv ivltests +ilongint_test normal,-g2005-sv ivltests +implicit_cast1 normal,-g2009 ivltests +implicit_cast2 normal,-g2009 ivltests +implicit_cast3 normal,-g2009 ivltests +implicit_cast4 normal,-g2009 ivltests +implicit_cast5 normal,-g2009 ivltests +implicit_cast6 normal,-g2009 ivltests +implicit_cast7 normal,-g2009 ivltests +implicit_cast8 normal,-g2009 ivltests +implicit_cast9 normal,-g2009 ivltests +implicit_cast10 normal,-g2009 ivltests +implicit_cast11 normal,-g2009 ivltests +implicit_cast12 normal,-g2009 ivltests +implicit_cast13 normal,-g2009 ivltests +implicit-port1 normal,-g2005-sv ivltests # SystemVerilog implicit port connections +implicit-port2 CE,-g2005-sv ivltests +implicit-port3 CE,-g2005-sv ivltests +implicit-port4 normal,-g2005-sv ivltests +implicit-port5 normal,-g2005-sv ivltests +implicit-port6 CE,-g2005-sv ivltests +implicit-port7 normal,-g2005-sv ivltests +inc_dec_stmt normal,-g2009 ivltests +int_param normal,-g2009 ivltests +ishortint_test normal,-g2005-sv ivltests +iuint1 normal,-g2005-sv ivltests +l_equiv normal,-g2005-sv ivltests +l_equiv_ca normal,-g2005-sv ivltests +l_equiv_const normal,-g2005-sv ivltests +line_directive normal,-g2009,-I./ivltests ivltests gold=line_directive.gold +localparam_query normal,-g2005-sv ivltests +localparam_type2 normal,-g2009 ivltests +logical_short_circuit normal,-g2012 ivltests +logp2 normal,-g2005-sv ivltests +mod_inst_pkg normal,-g2009 ivltests +named_begin normal,-g2009 ivltests +named_begin_fail CE,-g2009 ivltests +named_fork normal,-g2009 ivltests +named_fork_fail CE,-g2009 ivltests +packeda normal,-g2009 ivltests +packeda2 normal,-g2009 ivltests +parameter_type2 normal,-g2009 ivltests +parpkg_test normal,-g2009 ivltests +parpkg_test2 normal,-g2009 ivltests +parpkg_test3 normal,-g2009 ivltests +part_sel_port normal,-g2005-sv ivltests +plus_5 normal,-g2009 ivltests +pr3366114 normal,-g2009 ivltests +pr3366217a CE,-g2005-sv ivltests gold=pr3366217a.gold +pr3366217b CE,-g2005-sv ivltests gold=pr3366217b.gold +pr3366217c CE,-g2005-sv ivltests gold=pr3366217c.gold +pr3366217d CE,-g2005-sv ivltests gold=pr3366217d.gold +pr3366217e normal,-g2005-sv ivltests +pr3366217f normal,-g2005-sv ivltests gold=pr3366217f.gold +pr3366217g CE,-g2005-sv ivltests unordered=pr3366217g.gold +pr3366217h normal,-g2005-sv ivltests +pr3366217i normal,-g2005-sv ivltests +pr3390385 normal,-g2009 ivltests +pr3390385b normal,-g2009 ivltests +pr3390385c normal,-g2009 ivltests +pr3390385d normal,-g2009 ivltests +pr3462145 normal,-g2009 ivltests +pr3515542 CE,-g2005-sv ivltests gold=pr3515542.gold +pr3534333 normal,-g2005-sv ivltests +pr3576165 normal,-g2009 ivltests +program2 normal,-g2009 ivltests +program2b normal,-g2009 ivltests +program3 normal,-g2009 ivltests +program3a normal,-g2009 ivltests +program3b CE,-g2009 ivltests +program4 normal,-g2009 ivltests +program5a CE,-g2009 ivltests +program5b CE,-g2009 ivltests +program_hello normal,-g2009 ivltests +program_hello2 CE,-g2009 ivltests +sbyte_test normal,-g2005-sv ivltests +scalar_vector normal,-g2005-sv ivltests +sf_countbits normal,-g2012 ivltests +sf_countbits_fail RE,-g2012 ivltests gold=sf_countbits_fail.gold +sf_countones normal,-g2009 ivltests +sf_countones_fail RE,-g2009 ivltests gold=sf_countones_fail.gold +sf_isunknown normal,-g2005-sv ivltests +sf_isunknown_fail RE,-g2005-sv ivltests gold=sf_isunknown_fail.gold +sf_onehot normal,-g2005-sv ivltests +sf_onehot_fail RE,-g2005-sv ivltests gold=sf_onehot_fail.gold +sf_onehot0 normal,-g2005-sv ivltests +sf_onehot0_fail RE,-g2005-sv ivltests gold=sf_onehot0_fail.gold +sformatf normal,-g2009 ivltests +simple_byte normal,-g2005-sv ivltests +simple_int normal,-g2005-sv ivltests +simple_longint normal,-g2005-sv ivltests +simple_shortint normal,-g2005-sv ivltests +sint_test normal,-g2005-sv ivltests +size_cast normal,-g2009 ivltests +size_cast2 normal,-g2005-sv ivltests +size_cast3 normal,-g2009 ivltests +size_cast4 normal,-g2009 ivltests +size_cast5 normal,-g2009 ivltests +slongint_test normal,-g2005-sv ivltests +sshortint_test normal,-g2005-sv ivltests +string_events normal,-g2009 ivltests gold=string_events.gold +string_index normal,-g2005-sv ivltests +struct1 normal,-g2009 ivltests +struct2 normal,-g2009 ivltests +struct3 normal,-g2009 ivltests +struct3b normal,-g2009 ivltests +struct4 normal,-g2009 ivltests +struct5 normal,-g2009 ivltests +struct6 normal,-g2009 ivltests +struct7 normal,-g2009 ivltests +struct8 normal,-g2009 ivltests +struct9 normal,-g2009 ivltests +struct_packed_array normal,-g2009 ivltests +struct_packed_array2 normal,-g2009 ivltests +struct_packed_sysfunct normal,-g2009 ivltests +struct_packed_write_read2 normal,-g2009 ivltests +sv-constants normal,-g2005-sv ivltests +sv_array_assign_pattern2 normal,-g2009 ivltests +sv_cast_integer normal,-g2005-sv ivltests +sv_cast_integer2 normal,-g2005-sv ivltests +sv_cast_string normal,-g2005-sv ivltests +sv_class1 normal,-g2009 ivltests +sv_class2 normal,-g2009 ivltests +sv_class3 normal,-g2009 ivltests +sv_class4 normal,-g2009 ivltests +sv_class5 normal,-g2009 ivltests +sv_class6 normal,-g2009 ivltests +sv_class7 normal,-g2009 ivltests +sv_class8 normal,-g2009 ivltests +sv_class9 normal,-g2009 ivltests +sv_class10 normal,-g2009 ivltests +sv_class11 normal,-g2009 ivltests +sv_class12 normal,-g2009 ivltests +sv_class13 normal,-g2009 ivltests +sv_class14 normal,-g2009 ivltests +sv_class15 normal,-g2009 ivltests +sv_class16 normal,-g2009 ivltests +sv_class17 normal,-g2009 ivltests +sv_class18 normal,-g2009 ivltests +sv_class19 normal,-g2009 ivltests +sv_class20 normal,-g2009 ivltests +sv_class21 normal,-g2009 ivltests +sv_class22 normal,-g2009 ivltests +sv_class23 normal,-g2009 ivltests +sv_class24 normal,-g2009 ivltests +sv_darray1 normal,-g2009 ivltests +sv_darray2 normal,-g2009 ivltests +sv_darray3 normal,-g2009 ivltests +sv_darray4 normal,-g2009 ivltests +sv_darray5 normal,-g2009 ivltests +sv_darray5b normal,-g2009 ivltests +sv_darray6 normal,-g2009 ivltests +sv_darray_args1 normal,-g2009 ivltests +sv_darray_args2 normal,-g2009 ivltests +sv_darray_args2b normal,-g2009 ivltests +sv_darray_args3 normal,-g2009 ivltests +sv_darray_args4 normal,-g2009 ivltests +sv_darray_decl_assign normal,-g2009 ivltests +sv_darray_function normal,-g2009 ivltests +sv_darray_signed normal,-g2009 ivltests +sv_darray_word_size normal,-g2005-sv ivltests +sv_default_port_value1 normal,-g2009 ivltests +sv_default_port_value2 normal,-g2009 ivltests +sv_default_port_value3 CE,-g2009 ivltests gold=sv_default_port_value3.gold +sv_deferred_assert1 normal,-g2009 ivltests gold=sv_deferred_assert1.gold +sv_deferred_assert2 normal,-g2009 ivltests gold=sv_deferred_assert2.gold +sv_deferred_assume1 normal,-g2009 ivltests gold=sv_deferred_assume1.gold +sv_deferred_assume2 normal,-g2009 ivltests gold=sv_deferred_assume2.gold +sv_end_label normal,-g2005-sv ivltests +sv_end_label_fail CE,-g2009 ivltests gold=sv_end_label_fail.gold +sv_end_labels normal,-g2009 ivltests +sv_end_labels_bad CE,-g2009 ivltests gold=sv_end_labels_bad.gold +sv_enum1 normal,-g2009 ivltests +sv_for_variable normal,-g2009 ivltests +sv_foreach1 normal,-g2009 ivltests +sv_foreach2 normal,-g2009 ivltests +sv_foreach3 normal,-g2009 ivltests +sv_foreach4 normal,-g2009 ivltests +sv_foreach5 normal,-g2009 ivltests +sv_immediate_assert normal,-g2009 ivltests gold=sv_immediate_assert.gold +sv_immediate_assume normal,-g2009 ivltests gold=sv_immediate_assume.gold +sv_macro normal,-g2009 ivltests +sv_macro2 normal,-g2009 ivltests gold=sv_macro2.gold +sv_macro3a normal,-g2009 ivltests gold=sv_macro3.gold +sv_macro3b normal,-g2009 ivltests gold=sv_macro3.gold +sv_new_array_error CE,-g2009 ivltests gold=sv_new_array_error.gold +sv_package normal,-g2009 ivltests +sv_package2 normal,-g2009 ivltests +sv_package3 normal,-g2009 ivltests +sv_package4 normal,-g2009 ivltests +sv_package5 normal,-g2009 ivltests +sv_packed_port1 normal,-g2009 ivltests +sv_packed_port2 normal,-g2009 ivltests +sv_param_port_list normal,-g2009 ivltests +sv_pkg_class normal,-g2009 ivltests gold=sv_pkg_class.gold +sv_port_default1 normal,-g2009 ivltests +sv_port_default2 normal,-g2009 ivltests +sv_port_default3 normal,-g2009 ivltests +sv_port_default4 normal,-g2009 ivltests +sv_port_default5 normal,-g2009 ivltests +sv_port_default6 normal,-g2009 ivltests +sv_port_default7 normal,-g2009 ivltests +sv_port_default8 normal,-g2009 ivltests +sv_port_default9 normal,-g2009 ivltests +sv_port_default10 normal,-g2009 ivltests +sv_port_default11 normal,-g2009 ivltests +sv_port_default12 normal,-g2009 ivltests +sv_port_default13 CE,-g2009 ivltests +sv_port_default14 CE,-g2009 ivltests +sv_queue1 normal,-g2009 ivltests +sv_queue2 normal,-g2009 ivltests +sv_queue3 normal,-g2009 ivltests +sv_queue_real normal,-g2009,-pfileline=1 ivltests gold=sv_queue_real.gold +sv_queue_real_bounded normal,-g2009,-pfileline=1 ivltests gold=sv_queue_real_bounded.gold +sv_queue_real_fail CE,-g2009 ivltests gold=sv_queue_real_fail.gold +sv_queue_string normal,-g2009,-pfileline=1 ivltests gold=sv_queue_string.gold +sv_queue_string_bounded normal,-g2009,-pfileline=1 ivltests gold=sv_queue_string_bounded.gold +sv_queue_string_fail CE,-g2009 ivltests gold=sv_queue_string_fail.gold +sv_queue_vec normal,-g2009,-pfileline=1 ivltests gold=sv_queue_vec.gold +sv_queue_vec_bounded normal,-g2009,-pfileline=1 ivltests gold=sv_queue_vec_bounded.gold +sv_queue_vec_fail CE,-g2009 ivltests gold=sv_queue_vec_fail.gold +sv_root_class normal,-g2009 ivltests gold=sv_root_class.gold +sv_root_func normal,-g2009 ivltests gold=sv_root_func.gold +sv_root_task normal,-g2009 ivltests gold=sv_root_task.gold +sv_string1 normal,-g2009 ivltests +sv_string2 normal,-g2009 ivltests +sv_string3 normal,-g2009 ivltests +sv_string4 normal,-g2009 ivltests +sv_string5 normal,-g2009 ivltests +sv_timeunit_prec1 normal,-g2005-sv ivltests +sv_timeunit_prec2 normal,-g2009 ivltests +sv_timeunit_prec3a normal,-g2005-sv ivltests gold=sv_timeunit_prec3a.gold +sv_timeunit_prec3b normal,-g2005-sv ivltests gold=sv_timeunit_prec3b.gold +sv_timeunit_prec3c normal,-g2005-sv ivltests gold=sv_timeunit_prec3c.gold +sv_timeunit_prec3d normal,-g2005-sv ivltests gold=sv_timeunit_prec3d.gold +sv_timeunit_prec4a normal,-g2009 ivltests gold=sv_timeunit_prec4a.gold +sv_timeunit_prec4b normal,-g2009 ivltests gold=sv_timeunit_prec4b.gold +sv_timeunit_prec_fail1 CE,-g2005-sv,-u,\ + ./ivltests/sv_timeunit_prec_fail1a.v,\ + ./ivltests/sv_timeunit_prec_fail1b.v,\ + ./ivltests/sv_timeunit_prec_fail1c.v,\ + ./ivltests/sv_timeunit_prec_fail1d.v,\ + ./ivltests/sv_timeunit_prec_fail1e.v, ivltests gold=sv_timeunit_prec_fail1.gold +sv_timeunit_prec_fail2 CE,-g2009,-u,\ + ./ivltests/sv_timeunit_prec_fail2a.v,\ + ./ivltests/sv_timeunit_prec_fail2b.v,\ + ./ivltests/sv_timeunit_prec_fail2c.v, ivltests gold=sv_timeunit_prec_fail2.gold +sv_typedef_scope normal,-g2009 ivltests +sv_union1 normal,-g2009 ivltests +sv_union1b normal,-g2009 ivltests +sv_union2 normal,-g2009 ivltests +sv_union2b normal,-g2009 ivltests +sv_union3 normal,-g2009 ivltests +sv_union3b normal,-g2009 ivltests +sv_union4b normal,-g2009 ivltests +sv_unit1b normal,-g2009,-DMACRO1=1,-DMACRO2=2,\ + ./ivltests/sv_unit1a.v ivltests gold=sv_unit1b.gold +sv_unit1c normal,-g2009,-DMACRO1=1,-DMACRO2=2,-u,\ + ./ivltests/sv_unit1a.v ivltests gold=sv_unit1c.gold +sv_unit2b normal,-g2009,-u,\ + ./ivltests/sv_unit2a.v ivltests gold=sv_unit2b.gold +sv_unit3b normal,-g2009,-u,\ + ./ivltests/sv_unit3a.v ivltests gold=sv_unit3b.gold +sv_unit4b normal,-g2009,-u,\ + ./ivltests/sv_unit4a.v ivltests gold=sv_unit3b.gold +sv_unpacked_port normal,-g2009 ivltests +sv_unpacked_port2 normal,-g2009 ivltests +sv_unpacked_wire normal,-g2009 ivltests +sv_unpacked_wire2 normal,-g2009 ivltests +sv_uwire1 normal,-g2009 ivltests +sv_uwire2 normal,-g2009 ivltests +sv_uwire3 normal,-g2009 ivltests +sv_uwire4 normal,-g2009 ivltests +sv_var_init1 normal,-g2009 ivltests +sv_var_init2 normal,-g2009 ivltests +sv_wildcard_import1 normal,-g2009 ivltests +sv_wildcard_import2 normal,-g2009 ivltests +sv_wildcard_import3 normal,-g2009 ivltests +sv_wildcard_import4 CE,-g2009 ivltests gold=sv_wildcard_import4.gold +sv_wildcard_import5 CE,-g2009 ivltests unordered=sv_wildcard_import5.gold +sv_wildcard_import6 normal,-g2009 ivltests +sv_wildcard_import7 normal,-g2009 ivltests +sys_func_as_task normal,-g2005-sv ivltests gold=sys_func_as_task.gold +task_init_assign normal,-g2009 ivltests +task_init_var1 normal,-g2009 ivltests +task_init_var2 normal,-g2009 ivltests +task_init_var3 normal,-g2009 ivltests +task_scope2 normal,-g2009 ivltests +test_inc_dec normal,-g2009 ivltests +test_tliteral normal,-g2009 ivltests +timeliteral normal,-g2009 ivltests +two_state_display normal,-g2005-sv ivltests gold=two_state_display.gold +ubyte_test normal,-g2005-sv ivltests +uint_test normal,-g2005-sv ivltests +ulongint_test normal,-g2005-sv ivltests +undef_lval_select_SV normal,-g2009 ivltests +unp_array_typedef normal,-g2005-sv ivltests +packed_dims_invalid_class CE,-g2005-sv ivltests +packed_dims_invalid_module CE,-g2005-sv ivltests +ushortint_test normal,-g2005-sv ivltests +vvp_recv_vec4_pv normal,-g2005-sv ivltests +wait_fork normal,-g2009 ivltests +sf1289 normal,-g2012 ivltests +wild_cmp_const normal,-g2009 ivltests +wild_cmp_net normal,-g2009 ivltests +wild_cmp_var normal,-g2009 ivltests +wild_cmp_err CE,-g2009 ivltests gold=wild_cmp_err.gold +wild_cmp_err2 CE,-g2009 ivltests gold=wild_cmp_err2.gold +gh161a normal,-g2012 ivltests +gh161b normal,-g2012 ivltests +pull371b normal,-g2012 ivltests + +br_gh175 normal,-g2012 ivltests +br_gh307 normal,-g2012 ivltests +br_gh383a normal,-g2012 ivltests gold=br_gh383a.gold +br_gh383b normal,-g2012 ivltests gold=br_gh383b.gold +br_gh383c normal,-g2012 ivltests gold=br_gh383c.gold +br_gh383d normal,-g2012 ivltests gold=br_gh383d.gold +br_gh390a CE,-g2012 ivltests +br_gh390b normal,-g2012 ivltests gold=br_gh390b.gold +br_gh412 normal,-g2012 ivltests +br_gh414 normal,-g2012 ivltests +br_gh436 normal,-g2012 ivltests gold=br_gh436.gold +br_gh451 normal,-g2012,-Ptest.foo=4 ivltests gold=br_gh451.gold +br_gh453 normal,-g2012 ivltests +br_gh460 normal,-g2012 ivltests diff --git a/ivtest/regress-synth.list b/ivtest/regress-synth.list new file mode 100644 index 000000000..7096ceab0 --- /dev/null +++ b/ivtest/regress-synth.list @@ -0,0 +1,163 @@ +# This test list contains tests that exercise the Icarus synthesis +# functionality. The test framework automatically adds the -S option +# for compiler versions that support synthesis. + +# +# Copyright (c) 1999-2014 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# Format of the file +# +# testname testtype directory +# +# The is the verilog file name minus an extension. +# +# The can be one of the following: +# +# normal: Normal results expected, i.e it should compile and execute +# producing at least a single line with PASSED. +# +# CO: Compile Only - Compile the file to the default output type. +# +# CN: Compile Null - Compile with the null target. Similar to CO. +# +# CE: Compile with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# RE: Runtime with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# EF: Expected Fail - We EXPECT this test to fail - only use +# with older versions of Icarus. +# +# TE: Translation Error - We EXPECT the translated code to fail - +# only supported in the vlog95 checker. +# +# NI: Not implemented. Only use for version specific tests. +# +# is where the .v file is located. +# +# An optional fourth and fifth argument can be supplied. +# +# The fourth argument may be one of the following. +# +# modulename - Defines the top level module +# gold=filename - Compare a gold file against the +# generated log file. +# unordered=filename - Compare a gold file against the +# generated log file, allowing for lines +# to appear in any order +# diff=filename1:filename2:skip_ln - Compare the two files for equality. +# Skip the first lines or none. +# +# If a is given you can supply a fifth argument for the +# gold or diff commands. +# + +# We no longer support the ivl_full_case attribute. This is a dangerous +# thing to use, as it results in synthesis vs. simulation mismatches. +#full_case normal ivltests +#full_case2 normal ivltests + +basicexpr normal ivltests +basicexpr2 normal ivltests +basicexpr3 normal ivltests +basicexpr4 normal ivltests +basiclatch normal ivltests +basicreg normal ivltests +basicstate normal ivltests +basicstate2 normal ivltests +blocksynth1 normal ivltests +blocksynth2 normal ivltests +blocksynth3 normal ivltests +br993a normal ivltests +br993b normal ivltests +br994 normal ivltests +br995 CE ivltests +br_gh99v normal ivltests +br_gh99w normal ivltests +br_gh99x normal ivltests +br_gh115 normal ivltests +br_gh306a CE ivltests +br_gh306b CE ivltests +case1 normal ivltests +case2 normal ivltests +case3 normal ivltests +case4 normal ivltests +case5 normal ivltests +case5-syn-fail CE ivltests +case6 normal ivltests +case7 normal ivltests +case_wo_default normal ivltests +casesynth1 normal ivltests +casesynth2 normal ivltests +casesynth3 normal ivltests +casesynth4 normal ivltests +casesynth5 normal ivltests +casesynth6 normal ivltests +casesynth7 normal ivltests gold=casesynth7.gold +casesynth8 CE ivltests +casesynth9 normal ivltests +casex_synth normal ivltests +condit1 normal ivltests +conditsynth1 normal ivltests +conditsynth2 normal ivltests +conditsynth3 normal ivltests +dffsynth normal ivltests +dffsynth2 normal ivltests +dffsynth3 normal ivltests +dffsynth4 normal ivltests +dffsynth5 normal ivltests +dffsynth6 normal ivltests +dffsynth7 normal ivltests +dffsynth8 CE ivltests +dffsynth9 normal ivltests +dffsynth10 normal ivltests +dffsynth11 normal ivltests +ff_dual_enable normal ivltests +for_loop_synth normal ivltests +for_loop_synth2 normal ivltests +if_part_no_else normal ivltests +if_part_no_else2 normal ivltests +inside_synth normal ivltests +inside_synth2 normal ivltests +inside_synth3 normal ivltests +land5 normal ivltests +lcatsynth normal ivltests +memsynth1 normal ivltests +memsynth2 normal ivltests +memsynth3 normal ivltests +memsynth4 normal ivltests +memsynth5 normal ivltests +memsynth6 normal ivltests +memsynth7 normal ivltests +memsynth8 normal ivltests +memsynth9 normal ivltests +mix_reset normal ivltests +multireg normal ivltests +not_a_latch1 normal ivltests +not_a_latch2 normal ivltests +partselsynth normal ivltests +pr519 normal ivltests +pr685 normal ivltests +shiftl normal ivltests +sqrt32synth normal ivltests +ssetclr1 normal ivltests +ssetclr2 normal ivltests +ssetclr3 normal ivltests +synth_if_no_else normal ivltests +ufuncsynth1 normal ivltests diff --git a/ivtest/regress-v10.list b/ivtest/regress-v10.list new file mode 100644 index 000000000..c2221d5a1 --- /dev/null +++ b/ivtest/regress-v10.list @@ -0,0 +1,325 @@ +# This test list is used to override other test lists when using +# Icarus Verilog v10. + +# +# Copyright (c) 1999-2015 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# Format of the file +# +# testname testtype directory +# +# The is the verilog file name minus an extension. +# +# The can be one of the following: +# +# normal: Normal results expected, i.e it should compile and execute +# producing at least a single line with PASSED. +# +# CO: Compile Only - Compile the file to the default output type. +# +# CN: Compile Null - Compile with the null target. Similar to CO. +# +# CE: Compile with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# RE: Runtime with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# EF: Expected Fail - We EXPECT this test to fail - only use +# with older versions of Icarus. +# +# TE: Translation Error - We EXPECT the translated code to fail - +# only supported in the vlog95 checker. +# +# NI: Not implemented. Only use for version specific tests. +# +# is where the .v file is located. +# +# An optional fourth and fifth argument can be supplied. +# +# The fourth argument may be one of the following. +# +# modulename - Defines the top level module +# gold=filename - Compare a gold file against the +# generated log file. +# unordered=filename - Compare a gold file against the +# generated log file, allowing for lines +# to appear in any order +# diff=filename1:filename2:skip_ln - Compare the two files for equality. +# Skip the first lines or none. +# +# If a is given you can supply a fifth argument for the +# gold or diff commands. +# + +# Different error messages. +br975 CE,-g2009 ivltests gold=br975-v10.gold +pr1704726a CE ivltests gold=pr1704726a-v10.gold +pr1704726c CE ivltests gold=pr1704726c-v10.gold +pr1704726d CE ivltests gold=pr1704726d-v10.gold +# The fix to give a sensible error message has not been backported. +br_gh265 CE,-g2009 ivltests +# The enhanced error message has not been backported. +pr1698820 normal ivltests gold=pr1698820-v10.gold + +# Different warning messages. +fdisplay_fail_fd normal ivltests gold=fdisplay_fail_fd-v10.gold +fdisplay_fail_mcd normal ivltests gold=fdisplay_fail_mcd-v10.gold + +# The fix for type elaboration in the correct scope hasn't been backported. +br_gh289a NI +br_gh289b EF,-g2009 ivltests +br_gh289c EF,-g2009 ivltests + +# The fix for class access to enclosing scopes hasn't been backported. +br1003a normal,-g2009 ivltests gold=br1003a-v10.gold +br_ml20191221 CE,-g2009 ivltests + +# The fix for void functions hasn't been backported. +br_gh281 NI +br_gh281b NI +function10 NI +function11 NI +function12 NI + +# The fix for nested structs on the LHS of an assignment hasn't been backported. +gh161a NI + +# The VVP runtime doesn't support return statements in automatic functions. +# It's possible this could be fixed, but for now mark this as not implemented. +# We can't mark it as EF, because it causes a runtime assertion failure. +func_init_var2 NI + +# The fix for the assertion failure on an illegal SV cast causes enum_test1 to fail. +# It's possible this could be fixed, but for now mark this as not implemented. +# We can't mark it as CE, because it causes a compiler assertion failure. +br_ml20180227 NI + +# The timescale parsing rework hasn't been backported to v10. +# sv_timeunit_prec3b and sv_timeunit_prec4b fail at the compilation stage, +# so are marked as NI to distinguish them from expected errors. +resetall normal,-Wtimescale ivltests gold=resetall-v10.gold +br1003b normal,-g2009 ivltests gold=br1003b-v10.gold +br1003c normal,-g2009 ivltests gold=br1003c-v10.gold +sv_timeunit_prec3b NI +sv_timeunit_prec4b NI +sv_timeunit_prec_fail1 CE,-g2005-sv,\ + ./ivltests/sv_timeunit_prec_fail1a.v,\ + ./ivltests/sv_timeunit_prec_fail1b.v,\ + ./ivltests/sv_timeunit_prec_fail1c.v,\ + ./ivltests/sv_timeunit_prec_fail1d.v,\ + ./ivltests/sv_timeunit_prec_fail1e.v, ivltests gold=sv_timeunit_prec_fail1-v10.gold +sv_timeunit_prec_fail2 CE,-g2009,\ + ./ivltests/sv_timeunit_prec_fail2a.v,\ + ./ivltests/sv_timeunit_prec_fail2b.v,\ + ./ivltests/sv_timeunit_prec_fail2c.v, ivltests gold=sv_timeunit_prec_fail2-v10.gold +# nor has the support for separate compilation units. +sv_unit1c NI +sv_unit2b NI +sv_unit3b NI +sv_unit4b NI + +# The macro redefinition warnings haven't been backported to v10 +macro_redefinition NI +macro_replacement NI + +# The fix for casting strings to vectors uses new VVP instructions, +# so can't be backported. +br_ml20180309a NI +br_ml20180309b NI + +# The fix for uninitialised 2-state function return values uses new +# VVP syntax, so can't be backported. +br_gh337 NI + +# The fix for string values in event expressions hasn't been backported. +br_gh365 NI +string_events NI + +# The enhanced support for `` and `" hasn't been backported. +br_gh366 EF ivltests gold=br_gh366.gold +sv_macro3 EF ivltests gold=sv_macro3.gold + +# The fix for join_any inside a task hasn't been backported. +br_gh368 NI + +# V10 does not support analog functionality +analog1 NI +analog2 NI + +# V10 does not support this VHDL functionality +ivlh_textio NI +test_when_else NI +vhdl_concurrent_assert NI +vhdl_delay_assign NI +vhdl_elab_range NI +vhdl_eval_cond NI +vhdl_file_open NI +vhdl_image_attr NI +vhdl_lfcr NI +vhdl_loop NI +vhdl_multidim_array NI +vhdl_now NI +vhdl_pow_rem NI +vhdl_process_scope NI +vhdl_range NI +vhdl_resize NI +vhdl_shift NI +vhdl_string NI +vhdl_string_lim NI +vhdl_subtypes NI +vhdl_textio_write NI +vhdl_textio_read NI +vhdl_unary_minus NI +vhdl_wait NI +vhdl_while NI + +# V10 does not support this SystemVerilog functionality +always_comb NI +always_comb_fail NI +always_comb_fail3 NI +always_comb_fail4 NI +always_comb_no_sens NI +always_comb_rfunc NI +always_comb_trig NI +always_comb_warn NI +always_ff NI +always_ff_fail NI +always_ff_fail2 NI +always_ff_fail3 NI +always_ff_fail4 NI +always_ff_no_sens NI +always_ff_warn NI +always_ff_warn_sens NI +always_latch NI +always_latch_fail NI +always_latch_fail3 NI +always_latch_fail4 NI +always_latch_no_sens NI +always_latch_trig NI +always_latch_warn NI +br1004 NI +br_gh226 CE,-g2009 ivltests +br_gh177a NI +br_gh177b NI +br_gh277b NI +case_priority NI +case_unique NI +genvar_inc_dec NI +gh161b NI +l_equiv NI +l_equiv_ca NI +l_equiv_const NI +sf_countbits NI +sf_countbits_fail NI +sf_countones NI +sf_countones_fail NI +sf_isunknown NI +sf_isunknown_fail NI +sf_onehot NI +sf_onehot_fail NI +sf_onehot0 NI +sf_onehot0_fail NI +sformatf NI +sv_darray_decl_assign NI +sv_deferred_assert1 NI +sv_deferred_assert2 NI +sv_deferred_assume1 NI +sv_deferred_assume2 NI +sv_immediate_assert NI +sv_immediate_assume NI +sv_new_array_error NI +sv_param_port_list NI +sv_queue_real NI +sv_queue_real_bounded NI +sv_queue_real_fail NI +sv_queue_string NI +sv_queue_string_bounded NI +sv_queue_string_fail NI +sv_queue_vec NI +sv_queue_vec_bounded NI +sv_queue_vec_fail NI +sv_wildcard_import1 NI +sv_wildcard_import2 NI +sv_wildcard_import3 NI +sv_wildcard_import4 NI +sv_wildcard_import5 NI +sv_wildcard_import6 NI +sv_wildcard_import7 NI +vvp_recv_vec4_pv CE,-g2009 ivltests +wild_cmp_const NI +wild_cmp_err NI +wild_cmp_err2 NI +wild_cmp_net NI +wild_cmp_var NI +# and has non-standard support for this +sv_cast_darray NI +sv_cast_darray-v10 normal,-g2009 ivltests + +# V10 doesn't support rtran switches +rtran NI +rtranif0 NI +rtranif1 NI + +# V10 doesn't support this by default +br1000 normal,-gshared-loop-index ivltests + +# V10 does not support these SDF elements +br_ml20190814 EF,-gspecify ivltests + +# V10 has incomplete synthesis support +br993a CE,-S ivltests +br993b CE,-S ivltests +br_gh115 CE,-S ivltests +basiclatch normal ivltests +blocksynth2 normal ivltests +blocksynth3 normal ivltests +case1 normal ivltests +case2 normal ivltests +case4 normal ivltests +case5 normal ivltests +case5-syn-fail normal ivltests +case6 normal ivltests +casesynth1 normal ivltests +casesynth2 normal ivltests +casesynth3 normal ivltests +casesynth7 NI +casex_synth normal ivltests +condit1 normal ivltests +conditsynth1 normal ivltests +conditsynth2 normal ivltests +conditsynth3 normal ivltests +dffsynth normal ivltests +dffsynth3 normal ivltests +dffsynth4 normal ivltests +dffsynth9 normal ivltests +dffsynth10 normal ivltests +dffsynth11 normal ivltests +inside_synth normal ivltests +inside_synth3 normal ivltests +memsynth1 normal ivltests +memsynth2 normal ivltests +memsynth3 normal ivltests +memsynth5 normal ivltests +memsynth6 normal ivltests +memsynth7 normal ivltests +memsynth9 normal ivltests +mix_reset normal ivltests +multireg normal ivltests +sqrt32synth normal ivltests +ssetclr3 normal ivltests diff --git a/ivtest/regress-v11.list b/ivtest/regress-v11.list new file mode 100644 index 000000000..57fca1d72 --- /dev/null +++ b/ivtest/regress-v11.list @@ -0,0 +1,156 @@ +# This test list is used to override other test lists when using +# Icarus Verilog v11. + +# +# Copyright (c) 1999-2021 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# Format of the file +# +# testname testtype directory +# +# The is the verilog file name minus an extension. +# +# The can be one of the following: +# +# normal: Normal results expected, i.e it should compile and execute +# producing at least a single line with PASSED. +# +# CO: Compile Only - Compile the file to the default output type. +# +# CN: Compile Null - Compile with the null target. Similar to CO. +# +# CE: Compile with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# RE: Runtime with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# EF: Expected Fail - We EXPECT this test to fail - only use +# with older versions of Icarus. +# +# TE: Translation Error - We EXPECT the translated code to fail - +# only supported in the vlog95 checker. +# +# NI: Not implemented. Only use for version specific tests. +# +# is where the .v file is located. +# +# An optional fourth and fifth argument can be supplied. +# +# The fourth argument may be one of the following. +# +# modulename - Defines the top level module +# gold=filename - Compare a gold file against the +# generated log file. +# unordered=filename - Compare a gold file against the +# generated log file, allowing for lines +# to appear in any order +# diff=filename1:filename2:skip_ln - Compare the two files for equality. +# Skip the first lines or none. +# +# If a is given you can supply a fifth argument for the +# gold or diff commands. +# + +# v11 does not print a warning for too many parameter overrides +param_test3 normal ivltests +eofmt_percent normal ivltests gold=eofmt_percent-v11.gold + +# v11 does not fail during elaboration for these tests +pr1916261a normal ivltests +comment1 normal ivltests + +# v11 has not been updated to support this. +line_directive EF,-I./ivltests ivltests gold=line_directive.gold +program2b CE,-g2009 ivltests +program3a CE,-g2009 ivltests +sv_default_port_value1 CE,-g2009 ivltests +sv_default_port_value2 CE,-g2009 ivltests +sv_default_port_value3 CE,-g2009 ivltests + +# v11 does not check for as many issues as devel. +br_gh440 CE,-g2009 ivltests gold=br_gh440-v11.gold + +# v11 has incomplete synthesis support +dffsynth CE,-S ivltests +memsynth1 CE,-S ivltests +memsynth2 CE,-S ivltests +memsynth3 CE,-S ivltests +memsynth5 CE,-S ivltests +memsynth6 CE,-S ivltests +memsynth7 CE,-S ivltests +memsynth9 CE,-S ivltests +mix_reset CE,-S ivltests + +# These tests pass, but synthesis is creating unnecessary latches. +case1 normal ivltests +case2 normal ivltests +casex_synth normal ivltests + +# For V11 vvp does not fail for these tests +automatic_error11 normal ivltests gold=automatic_error11.gold +automatic_error12 normal ivltests gold=automatic_error12.gold +automatic_error13 normal ivltests gold=automatic_error13.gold +br_gh230 normal ivltests gold=br_gh230.gold +fdisplay3 normal ivltests gold=fdisplay3.gold +fread-error normal ivltests gold=fread-error.gold +pr2800985b normal ivltests gold=pr2800985b.gold +queue_fail normal ivltests gold=queue_fail.gold +readmem-invalid normal ivltests gold=readmem-invalid.gold +scan-invalid normal ivltests gold=scan-invalid.gold +warn_opt_sys_tf normal ivltests gold=warn_opt_sys_tf.gold +writemem-invalid normal ivltests gold=writemem-invalid.gold +sf_countbits_fail normal,-g2012 ivltests gold=sf_countbits_fail.gold +sf_countones_fail normal,-g2009 ivltests gold=sf_countones_fail.gold +sf_isunknown_fail normal,-g2009 ivltests gold=sf_isunknown_fail.gold +sf_onehot_fail normal,-g2009 ivltests gold=sf_onehot_fail.gold +sf_onehot0_fail normal,-g2009 ivltests gold=sf_onehot0_fail.gold + +# These tests are not implemented for v11 +analog1 NI ivltests +analog2 NI ivltests +br605a NI ivltests +br605b NI ivltests +br971 NI ivltests +br_gh72b_fail NI ivltests +br_gh175 NI ivltests +br_gh307 NI ivltests +br_gh383a NI ivltests +br_gh383b NI ivltests +br_gh383c NI ivltests +br_gh383d NI ivltests +br_gh390a NI ivltests +br_gh390b NI ivltests +br_gh412 NI ivltests +br_gh414 NI ivltests +br_gh436 NI ivltests +br_gh453 NI ivltests +br_gh460 NI ivltests +br_gh478 NI ivltests +br_gh527 NI ivltests +edge NI ivltests +fileline2 NI ivltests +ifdef_fail NI ivltests +scalar_vector NI ivltests +string12 NI ivltests +sv_deferred_assert1 NI ivltests +sv_deferred_assert2 NI ivltests +sv_deferred_assume1 NI ivltests +sv_deferred_assume2 NI ivltests +timeliteral NI ivltests +vhdl_multidim_array NI ivltests diff --git a/ivtest/regress-v12.list b/ivtest/regress-v12.list new file mode 100644 index 000000000..8f09d06f0 --- /dev/null +++ b/ivtest/regress-v12.list @@ -0,0 +1,84 @@ +# This test list is used to override other test lists when using +# Icarus Verilog v12. + +# +# Copyright (c) 1999-2015 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# Format of the file +# +# testname testtype directory +# +# The is the verilog file name minus an extension. +# +# The can be one of the following: +# +# normal: Normal results expected, i.e it should compile and execute +# producing at least a single line with PASSED. +# +# CO: Compile Only - Compile the file to the default output type. +# +# CN: Compile Null - Compile with the null target. Similar to CO. +# +# CE: Compile with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# RE: Runtime with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# EF: Expected Fail - We EXPECT this test to fail - only use +# with older versions of Icarus. +# +# TE: Translation Error - We EXPECT the translated code to fail - +# only supported in the vlog95 checker. +# +# NI: Not implemented. Only use for version specific tests. +# +# is where the .v file is located. +# +# An optional fourth and fifth argument can be supplied. +# +# The fourth argument may be one of the following. +# +# modulename - Defines the top level module +# gold=filename - Compare a gold file against the +# generated log file. +# unordered=filename - Compare a gold file against the +# generated log file, allowing for lines +# to appear in any order +# diff=filename1:filename2:skip_ln - Compare the two files for equality. +# Skip the first lines or none. +# +# If a is given you can supply a fifth argument for the +# gold or diff commands. +# + +# v11 has incomplete synthesis support +dffsynth CE,-S ivltests +memsynth1 CE,-S ivltests +memsynth2 CE,-S ivltests +memsynth3 CE,-S ivltests +memsynth5 CE,-S ivltests +memsynth6 CE,-S ivltests +memsynth7 CE,-S ivltests +memsynth9 CE,-S ivltests +mix_reset CE,-S ivltests + +# These tests pass, but synthesis is creating unnecessary latches. +case1 normal ivltests +case2 normal ivltests +casex_synth normal ivltests diff --git a/ivtest/regress-vams.list b/ivtest/regress-vams.list new file mode 100644 index 000000000..0043b0293 --- /dev/null +++ b/ivtest/regress-vams.list @@ -0,0 +1,88 @@ +# This test list contains tests that should work using any simulator that +# supports Verilog-AMS. + +# +# Copyright (c) 1999-2014 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# Format of the file +# +# testname testtype directory +# +# The is the verilog file name minus an extension. +# +# The can be one of the following: +# +# normal: Normal results expected, i.e it should compile and execute +# producing at least a single line with PASSED. +# +# CO: Compile Only - Compile the file to the default output type. +# +# CN: Compile Null - Compile with the null target. Similar to CO. +# +# CE: Compile with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# RE: Runtime with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# EF: Expected Fail - We EXPECT this test to fail - only use +# with older versions of Icarus. +# +# TE: Translation Error - We EXPECT the translated code to fail - +# only supported in the vlog95 checker. +# +# NI: Not implemented. Only use for version specific tests. +# +# is where the .v file is located. +# +# An optional fourth and fifth argument can be supplied. +# +# The fourth argument may be one of the following. +# +# modulename - Defines the top level module +# gold=filename - Compare a gold file against the +# generated log file. +# unordered=filename - Compare a gold file against the +# generated log file, allowing for lines +# to appear in any order +# diff=filename1:filename2:skip_ln - Compare the two files for equality. +# Skip the first lines or none. +# +# If a is given you can supply a fifth argument for the +# gold or diff commands. +# + +analog1 normal,-gverilog-ams ivltests +analog2 normal,-gverilog-ams ivltests +br_gh99c normal,-gverilog-ams ivltests +cast_int_ams normal,-gverilog-ams ivltests +constfunc4_ams normal,-gverilog-ams ivltests +scaled_real normal,-gverilog-ams ivltests +test_vams_math normal,-gverilog-ams ivltests gold=test_vams_math.gold +value_range1 normal,-gverilog-ams ivltests +value_range2 normal,-gverilog-ams ivltests +value_range3 CE,-gverilog-ams ivltests +vams_abs1 normal,-gverilog-ams ivltests +vams_abs2 normal,-gverilog-ams ivltests +wreal normal,-gverilog-ams ivltests +# Verilog functions added in a VAMS simulator +constfunc6_ams normal ivltests +non-polymorphic-abs normal ivltests +pr3270320_ams CE ivltests +test_va_math normal,-mva_math ivltests gold=test_va_math.gold +va_math normal ivltests diff --git a/ivtest/regress-vhdl.list b/ivtest/regress-vhdl.list new file mode 100644 index 000000000..dfe013468 --- /dev/null +++ b/ivtest/regress-vhdl.list @@ -0,0 +1,209 @@ +# This test list contains tests that should work using any simulator that +# supports standard VHDL. + +# +# Copyright (c) 1999-2014 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# Format of the file +# +# testname testtype directory +# +# The is the verilog file name minus an extension. +# +# The can be one of the following: +# +# normal: Normal results expected, i.e it should compile and execute +# producing at least a single line with PASSED. +# +# CO: Compile Only - Compile the file to the default output type. +# +# CN: Compile Null - Compile with the null target. Similar to CO. +# +# CE: Compile with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# RE: Runtime with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# EF: Expected Fail - We EXPECT this test to fail - only use +# with older versions of Icarus. +# +# TE: Translation Error - We EXPECT the translated code to fail - +# only supported in the vlog95 checker. +# +# NI: Not implemented. Only use for version specific tests. +# +# is where the .v file is located. +# +# An optional fourth and fifth argument can be supplied. +# +# The fourth argument may be one of the following. +# +# modulename - Defines the top level module +# gold=filename - Compare a gold file against the +# generated log file. +# unordered=filename - Compare a gold file against the +# generated log file, allowing for lines +# to appear in any order +# diff=filename1:filename2:skip_ln - Compare the two files for equality. +# Skip the first lines or none. +# +# If a is given you can supply a fifth argument for the +# gold or diff commands. +# + +br942 normal,-g2005-sv,ivltests/br942.vhd ivltests +br943_944 normal,-g2005-sv,ivltests/br943_944.vhd ivltests +br985 normal,-g2005-sv,ivltests/br985.vhd ivltests +br986 normal,-g2005-sv,ivltests/br986.vhd ivltests +br987 normal,-g2005-sv,ivltests/br987.vhd ivltests +ivlh_event normal,-mvhdl_sys ivltests gold=ivlh_event.gold +ivlh_rising_falling normal,-mvhdl_sys ivltests gold=ivlh_rising_falling.gold +ivlh_textio normal,-mvhdl_textio,-g2005-sv ivltests +test_dec2to4 normal,-g2005-sv,ivltests/dec2to4.vhd ivltests +test_enumsystem normal,-g2005-sv,ivltests/enumsystem.vhd ivltests +test_forgen normal,-g2005-sv,ivltests/forgen.vhd ivltests +test_gxor normal,-g2005-sv,ivltests/gxor.vhd ivltests +test_mux2to1 normal,-g2005-sv,ivltests/mux2to1.vhd ivltests +test_signal_init_assign normal,-g2005-sv,ivltests/signal_init_assign.vhd ivltests +test_system normal,-g2005-sv,ivltests/system.vhd ivltests +test_timebase normal,-g2005-sv,ivltests/timebase.vhd ivltests +test_varray1 normal,-g2005-sv,ivltests/varray1.vhd ivltests +test_when_else normal,-g2005-sv,ivltests/when_else.vhd ivltests +test_work14 normal,-g2005-sv,ivltests/work14_pkg.vhd,ivltests/work14.vhd ivltests +vhdl_and104_stdlogic normal,-g2005-sv,ivltests/vhdl_and104_stdlogic.vhd ivltests +vhdl_and23_bit normal,-g2005-sv,ivltests/vhdl_and23_bit.vhd ivltests +vhdl_and_gate normal,-g2005-sv,ivltests/vhdl_and_gate.vhd ivltests +vhdl_andg_bit normal,-g2005-sv,ivltests/vhdl_andg_bit.vhd ivltests +vhdl_andg_stdlogic normal,-g2005-sv,ivltests/vhdl_andg_stdlogic.vhd ivltests +vhdl_array_of_array normal,-g2005-sv,ivltests/vhdl_array_of_array.vhd ivltests +vhdl_case_multi normal,-g2005-sv,ivltests/vhdl_case_multi.vhd ivltests +vhdl_boolean normal,-g2005-sv,ivltests/vhdl_boolean.vhd ivltests +vhdl_concat normal,-g2005-sv,ivltests/vhdl_concat.vhd ivltests +vhdl_concat_func normal,-g2005-sv,ivltests/vhdl_concat_func.vhd ivltests +vhdl_concurrent_assert normal,-g2005-sv,ivltests/vhdl_concurrent_assert.vhd ivltests gold=vhdl_concurrent_assert.gold +vhdl_const_package normal,-g2005-sv,ivltests/vhdl_const_package_pkg.vhd,ivltests/vhdl_const_package.vhd ivltests +vhdl_const_record normal,-g2005-sv,ivltests/vhdl_const_record.vhd ivltests +vhdl_const_array normal,-g2005-sv,ivltests/vhdl_const_array_pkg.vhd,ivltests/vhdl_const_array.vhd ivltests +vhdl_delay_assign normal,-g2005-sv,-fivltests/vhdl_timescale_1ns.cfg,ivltests/vhdl_delay_assign.vhd ivltests +vhdl_elab_range normal,-g2005-sv,ivltests/vhdl_elab_range.vhd ivltests +vhdl_eval_cond normal,-g2005-sv,ivltests/vhdl_eval_cond.vhd ivltests +vhdl_expr1 normal,-g2005-sv,ivltests/vhdl_expr1.vhd ivltests +vhdl_generic_eval normal,-g2005-sv,ivltests/vhdl_generic_eval.vhd ivltests +vhdl_fa4_test1 normal,-g2005-sv,ivltests/vhdl_fa4_test1.vhd ivltests +vhdl_fa4_test2 normal,-g2005-sv,ivltests/vhdl_fa4_test2.vhd ivltests +vhdl_fa4_test3 normal,-g2005-sv,ivltests/vhdl_fa4_test3.vhd ivltests +vhdl_fa4_test4 normal,-g2005-sv,ivltests/vhdl_fa4_test4.vhd ivltests +vhdl_file_open normal,-g2005-sv,ivltests/vhdl_file_open.vhd ivltests +vhdl_generic_default normal,-g2005-sv,ivltests/vhdl_generic_default.vhd ivltests +vhdl_init normal,-g2005-sv,ivltests/vhdl_init.vhd ivltests +vhdl_image_attr normal,-g2005-sv,-fivltests/vhdl_timescale_1ns.cfg,ivltests/vhdl_image_attr.vhd ivltests gold=vhdl_image_attr.gold +vhdl_inout normal,-g2005-sv,ivltests/vhdl_inout.vhd ivltests +vhdl_labeled_assign normal,-g2005-sv,ivltests/vhdl_labeled_assign.vhd ivltests +vhdl_lfcr normal,-g2005-sv,ivltests/vhdl_lfcr.vhd ivltests gold=vhdl_lfcr.gold +vhdl_logic normal,-g2005-sv,ivltests/vhdl_logic.vhd ivltests +vhdl_loop normal,-g2005-sv,ivltests/vhdl_loop.vhd ivltests +vhdl_multidim_array normal,-g2005-sv,ivltests/vhdl_multidim_array.vhd ivltests +vhdl_nand104_stdlogic normal,-g2005-sv,ivltests/vhdl_nand104_stdlogic.vhd ivltests +vhdl_nand23_bit normal,-g2005-sv,ivltests/vhdl_nand23_bit.vhd ivltests +vhdl_nandg_bit normal,-g2005-sv,ivltests/vhdl_nandg_bit.vhd ivltests +vhdl_nandg_stdlogic normal,-g2005-sv,ivltests/vhdl_nandg_stdlogic.vhd ivltests +vhdl_nor104_stdlogic normal,-g2005-sv,ivltests/vhdl_nor104_stdlogic.vhd ivltests +vhdl_nor23_bit normal,-g2005-sv,ivltests/vhdl_nor23_bit.vhd ivltests +vhdl_norg_bit normal,-g2005-sv,ivltests/vhdl_norg_bit.vhd ivltests +vhdl_norg_stdlogic normal,-g2005-sv,ivltests/vhdl_norg_stdlogic.vhd ivltests +vhdl_not104_stdlogic normal,-g2005-sv,ivltests/vhdl_not104_stdlogic.vhd ivltests +vhdl_not23_bit normal,-g2005-sv,ivltests/vhdl_not23_bit.vhd ivltests +vhdl_notfunc_stdlogic normal,-g2005-sv,ivltests/vhdl_notfunc_stdlogic.vhd ivltests +vhdl_notg_bit normal,-g2005-sv,ivltests/vhdl_notg_bit.vhd ivltests +vhdl_notg_stdlogic normal,-g2005-sv,ivltests/vhdl_notg_stdlogic.vhd ivltests +vhdl_now normal,-g2005-sv,ivltests/vhdl_now.vhd ivltests gold=vhdl_now.gold +vhdl_or104_stdlogic normal,-g2005-sv,ivltests/vhdl_or104_stdlogic.vhd ivltests +vhdl_or23_bit normal,-g2005-sv,ivltests/vhdl_or23_bit.vhd ivltests +vhdl_org_bit normal,-g2005-sv,ivltests/vhdl_org_bit.vhd ivltests +vhdl_org_stdlogic normal,-g2005-sv,ivltests/vhdl_org_stdlogic.vhd ivltests +vhdl_pow_rem normal,-g2005-sv,ivltests/vhdl_pow_rem.vhd ivltests +vhdl_prefix_array normal,-g2005-sv,ivltests/vhdl_prefix_array.vhd ivltests +vhdl_procedure normal,-g2005-sv,ivltests/vhdl_procedure.vhd ivltests gold=vhdl_procedure.gold +vhdl_process_scope normal,-g2005-sv,ivltests/vhdl_process_scope.vhd ivltests +vhdl_rand23_bit normal,-g2005-sv,ivltests/vhdl_rand23_bit.vhd ivltests +vhdl_range normal,-g2005-sv,ivltests/vhdl_range_pkg.vhd,ivltests/vhdl_range.vhd ivltests +vhdl_range_func normal,-g2005-sv,ivltests/vhdl_range_func_pkg.vhd,ivltests/vhdl_range_func.vhd, ivltests +vhdl_real normal,-g2005-sv,ivltests/vhdl_real.vhd ivltests +vhdl_record_elab normal,-g2005-sv,ivltests/vhdl_record_elab_pkg.vhd,ivltests/vhdl_record_elab.vhd ivltests +vhdl_reduce normal,-g2005-sv,ivltests/vhdl_reduce.vhd ivltests +vhdl_report normal,-g2005-sv,ivltests/vhdl_report_pkg.vhd,ivltests/vhdl_report.vhd ivltests gold=vhdl_report.gold +vhdl_resize normal,-g2005-sv,ivltests/vhdl_resize.vhd ivltests +vhdl_rtoi normal,-g2005-sv,ivltests/vhdl_rtoi.vhd ivltests +vhdl_sa1_test1 normal,-g2005-sv,ivltests/vhdl_sa1_test1.vhd ivltests +vhdl_sa1_test2 normal,-g2005-sv,ivltests/vhdl_sa1_test2.vhd ivltests +vhdl_sa1_test3 normal,-g2005-sv,-mvhdl_sys,ivltests/vhdl_sa1_test3.vhd ivltests +vhdl_sadd23_bit normal,-g2005-sv,ivltests/vhdl_sadd23_bit.vhd ivltests +vhdl_sadd23_stdlogic normal,-g2005-sv,ivltests/vhdl_sadd23_stdlogic.vhd ivltests +vhdl_sdiv23_bit normal,-g2005-sv,ivltests/vhdl_sdiv23_bit.vhd ivltests +vhdl_sdiv23_stdlogic normal,-g2005-sv,ivltests/vhdl_sdiv23_stdlogic.vhd ivltests +vhdl_selected normal,-g2005-sv,ivltests/vhdl_selected.vhd ivltests +vhdl_shift normal,-g2005-sv,ivltests/vhdl_shift.vhd ivltests +vhdl_signals normal,-g2005-sv,ivltests/vhdl_signals.vhd ivltests +vhdl_smul23_bit normal,-g2005-sv,ivltests/vhdl_smul23_bit.vhd ivltests +vhdl_smul23_stdlogic normal,-g2005-sv,ivltests/vhdl_smul23_stdlogic.vhd ivltests +vhdl_ssub23_bit normal,-g2005-sv,ivltests/vhdl_ssub23_bit.vhd ivltests +vhdl_ssub23_stdlogic normal,-g2005-sv,ivltests/vhdl_ssub23_stdlogic.vhd ivltests +vhdl_struct_array normal,-g2005-sv,ivltests/vhdl_struct_array.vhd ivltests +vhdl_subtypes normal,-g2005-sv,ivltests/vhdl_subtypes_pkg.vhd,ivltests/vhdl_subtypes.vhd ivltests +vhdl_subprogram normal,-g2005-sv,ivltests/vhdl_subprogram_pkg.vhd,ivltests/vhdl_subprogram.vhd ivltests +vhdl_string normal,-g2005-sv,ivltests/vhdl_string.vhd ivltests gold=vhdl_string.gold +vhdl_string_lim normal,-g2005-sv,ivltests/vhdl_string_lim.vhd ivltests +vhdl_test1 normal,-g2005-sv,ivltests/vhdl_test1.vhd ivltests +vhdl_test2 normal,-g2005-sv,ivltests/vhdl_test2.vhd ivltests +vhdl_test3 normal,-g2005-sv,ivltests/vhdl_test3.vhd ivltests gold=vhdl_test3.gold +vhdl_test4 normal,-g2005-sv,ivltests/vhdl_test4.vhd ivltests +vhdl_test5 normal,-g2005-sv,ivltests/vhdl_test5.vhd ivltests +vhdl_test6 normal,-g2005-sv,ivltests/vhdl_test6.vhd ivltests +vhdl_test7 normal,-g2005-sv,ivltests/vhdl_test7.vhd ivltests +vhdl_test8 normal,-g2005-sv,ivltests/vhdl_test8.vhd ivltests +vhdl_test9 normal,-g2005-sv,ivltests/vhdl_test9.vhd ivltests +# vhdl_textio_write creates the test data for vhdl_textio_read, so it has to be run first +vhdl_textio_write normal,-g2005-sv,ivltests/vhdl_textio_write.vhd ivltests +vhdl_textio_read normal,-g2005-sv,ivltests/vhdl_textio_read.vhd ivltests +vhdl_time normal,-g2005-sv,-fivltests/vhdl_timescale_1ns.cfg,ivltests/vhdl_time_pkg.vhd,ivltests/vhdl_time.vhd ivltests gold=vhdl_time.gold +vhdl_to_integer normal,-g2005-sv,ivltests/vhdl_to_integer.vhd ivltests +vhdl_uadd23_bit normal,-g2005-sv,ivltests/vhdl_uadd23_bit.vhd ivltests +vhdl_uadd23_stdlogic normal,-g2005-sv,ivltests/vhdl_uadd23_stdlogic.vhd ivltests +vhdl_udiv23_bit normal,-g2005-sv,ivltests/vhdl_udiv23_bit.vhd ivltests +vhdl_udiv23_stdlogic normal,-g2005-sv,ivltests/vhdl_udiv23_stdlogic.vhd ivltests +vhdl_umul23_bit normal,-g2005-sv,ivltests/vhdl_umul23_bit.vhd ivltests +vhdl_umul23_stdlogic normal,-g2005-sv,ivltests/vhdl_umul23_stdlogic.vhd ivltests +vhdl_unary_minus normal,-g2005-sv,ivltests/vhdl_unary_minus.vhd ivltests +vhdl_unbounded normal,-g2005-sv,ivltests/vhdl_unbounded.vhd ivltests +vhdl_unbounded_func normal,-g2005-sv,ivltests/vhdl_unbounded_func_pkg.vhd,ivltests/vhdl_unbounded_func.vhd ivltests +vhdl_usub23_bit normal,-g2005-sv,ivltests/vhdl_usub23_bit.vhd ivltests +vhdl_usub23_stdlogic normal,-g2005-sv,ivltests/vhdl_usub23_stdlogic.vhd ivltests +vhdl_var_init normal,-g2005-sv,ivltests/vhdl_var_init.vhd ivltests +vhdl_wait normal,-g2005-sv,ivltests/vhdl_wait.vhd ivltests gold=vhdl_wait.gold +vhdl_while normal,-g2005-sv,ivltests/vhdl_while.vhd ivltests +vhdl_xnor104_stdlogic normal,-g2005-sv,ivltests/vhdl_xnor104_stdlogic.vhd ivltests +vhdl_xnor104_stdlogic normal,-g2005-sv,ivltests/vhdl_xnor104_stdlogic.vhd ivltests +vhdl_xnor23_bit normal,-g2005-sv,ivltests/vhdl_xnor23_bit.vhd ivltests +vhdl_xnorg_bit normal,-g2005-sv,ivltests/vhdl_xnorg_bit.vhd ivltests +vhdl_xnorg_stdlogic normal,-g2005-sv,ivltests/vhdl_xnorg_stdlogic.vhd ivltests +vhdl_xor23_bit normal,-g2005-sv,ivltests/vhdl_xor23_bit.vhd ivltests +vhdl_xorg_bit normal,-g2005-sv,ivltests/vhdl_xorg_bit.vhd ivltests +vhdl_xorg_stdlogic normal,-g2005-sv,ivltests/vhdl_xorg_stdlogic.vhd ivltests +work7 normal,-g2009,-fivltests/work7.cfg ivltests +work7b normal,-g2009,-fivltests/work7b.cfg ivltests diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list new file mode 100644 index 000000000..7f49555ce --- /dev/null +++ b/ivtest/regress-vlg.list @@ -0,0 +1,1723 @@ +# This test list contains tests that should work using any simulator that +# supports standard Verilog (1364-2005). + +# +# Copyright (c) 1999-2021 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# Format of the file +# +# testname testtype directory +# +# The is the verilog file name minus an extension. +# +# The can be one of the following: +# +# normal: Normal results expected, i.e it should compile and execute +# producing at least a single line with PASSED. +# +# CO: Compile Only - Compile the file to the default output type. +# +# CN: Compile Null - Compile with the null target. Similar to CO. +# +# CE: Compile with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# RE: Runtime with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# EF: Expected Fail - We EXPECT this test to fail - only use +# with older versions of Icarus. +# +# TE: Translation Error - We EXPECT the translated code to fail - +# only supported in the vlog95 checker. +# +# NI: Not implemented. Only use for version specific tests. +# +# is where the .v file is located. +# +# An optional fourth and fifth argument can be supplied. +# +# The fourth argument may be one of the following. +# +# modulename - Defines the top level module +# gold=filename - Compare a gold file against the +# generated log file. +# unordered=filename - Compare a gold file against the +# generated log file, allowing for lines +# to appear in any order +# diff=filename1:filename2:skip_ln - Compare the two files for equality. +# Skip the first lines or none. +# +# If a is given you can supply a fifth argument for the +# gold or diff commands. +# + +addsr normal ivltests # Finds problems with >> using different sizes +addwide normal ivltests +always3.1.1A CE ivltests +always3.1.1B CE ivltests +always3.1.1C normal ivltests +always3.1.1D normal ivltests +always3.1.1E normal ivltests +always3.1.1F normal ivltests +always3.1.1G normal ivltests +always3.1.1H normal ivltests +always3.1.1I normal ivltests +always3.1.1J normal ivltests +always3.1.1K normal ivltests +always3.1.2A CE ivltests +always3.1.2B CE ivltests +always3.1.2C CE ivltests +always3.1.2D CE ivltests +always3.1.2E CE,-Ttyp ivltests +always3.1.2F CE,-Ttyp ivltests +always3.1.2G CE ivltests +always3.1.2H CE ivltests +always3.1.2I CE ivltests +always3.1.3A CE ivltests +always3.1.3B CE ivltests +always3.1.3B2 normal ivltests +always3.1.3C CE ivltests +always3.1.3D CE ivltests +always3.1.3D2 normal ivltests +always3.1.3E CE ivltests +always3.1.3E2 normal ivltests +always3.1.3F CE ivltests +always3.1.3F2 normal ivltests +always3.1.3G CE ivltests +always3.1.3H CE ivltests +always3.1.3J CE ivltests +always3.1.4A normal ivltests +always3.1.4B normal ivltests +always3.1.4C normal ivltests +always3.1.4D normal ivltests +always3.1.4E normal ivltests +always3.1.4F normal ivltests +always3.1.4G normal ivltests +always3.1.4H normal ivltests +always3.1.4I normal ivltests +always3.1.5A normal ivltests +always3.1.5B normal ivltests +always3.1.5C normal ivltests +always3.1.5D normal ivltests +always3.1.5E normal ivltests +always3.1.5F normal ivltests +always3.1.6A normal ivltests +always3.1.6B normal ivltests +always3.1.6C normal ivltests +always3.1.6D normal ivltests +always3.1.7A normal ivltests +always3.1.7B normal ivltests +always3.1.7C normal ivltests +always3.1.7D normal ivltests +always3.1.8A normal ivltests +always3.1.9A CE ivltests +always3.1.9B CE ivltests +always3.1.9C normal ivltests # always #1 disable taskname +always3.1.9D normal ivltests # always #1 disable blockid +always3.1.10A CE ivltests +always3.1.11A normal ivltests +always3.1.11B normal ivltests +always3.1.12A normal ivltests # always fork join +always3.1.12B normal ivltests # always fork: block_id join +always3.1.12C normal ivltests +always_star_array_lval normal ivltests gold=always_star_array_lval.gold +andnot1 normal ivltests +arith-unknown normal ivltests +array4 normal ivltests +array5 CE ivltests +array6 normal ivltests +array7 normal ivltests +array_lval_select1 normal ivltests +array_lval_select2 normal ivltests +array_lval_select3b CE ivltests +array_lval_select3c normal ivltests +array_lval_select4a normal ivltests +array_lval_select4b CE ivltests +array_lval_select5 normal ivltests +array_lval_select6 normal ivltests +array_packed_2d normal ivltests gold=array_packed_2d.gold +array_select normal ivltests +array_select_a normal ivltests +array_word_check normal ivltests gold=array_word_check.gold +array_word_width normal ivltests gold=array_word_width.gold +array_word_width2 normal ivltests +assign3.2A normal ivltests +assign3.2B normal ivltests +assign3.2C normal ivltests +assign3.2D normal ivltests +assign3.2E normal ivltests +assign_add normal ivltests +assign_deassign_pv normal ivltests +assign_delay normal ivltests # continuous assign with a delay +assign_deq normal ivltests # continuous assign with == +assign_ge normal ivltests # continuous assign with >= +assign_le normal ivltests # continuous assign with <= +assign_mem1 normal ivltests +assign_mem2 normal ivltests # Const prop/dead signal elimination +assign_nb1 normal ivltests # Assign a constant to a single bit array (pmonta) +assign_nb2 normal ivltests # Assign a constant to a single bit array (pmonta) +assign_neq normal ivltests # continuous assign with != +attrib normal ivltests +attrib01_module normal ivltests +attrib02_port_decl normal ivltests +attrib03_parameter normal ivltests +attrib04_net_var normal ivltests +attrib05_port_conn normal ivltests +attrib06_operator_suffix normal ivltests +attrib07_func_call normal ivltests +attrib08_mod_inst normal ivltests +attrib09_case normal ivltests +automatic_error1 CE ivltests +automatic_error2 CE ivltests +automatic_error3 CE ivltests +automatic_error5 CE ivltests +automatic_error6 CE ivltests +automatic_error7 CE ivltests +automatic_error8 CE ivltests +automatic_error9 CE ivltests +automatic_error10 CE ivltests +automatic_error11 RE ivltests gold=automatic_error11.gold +automatic_error12 RE ivltests gold=automatic_error12.gold +automatic_error13 RE ivltests gold=automatic_error13.gold +automatic_events normal ivltests gold=automatic_events.gold +automatic_events2 normal ivltests gold=automatic_events.gold +automatic_events3 normal ivltests gold=automatic_events3.gold +automatic_task normal ivltests gold=automatic_task.gold +automatic_task2 normal ivltests gold=automatic_task2.gold +automatic_task3 normal ivltests gold=automatic_task3.gold +bitwidth normal ivltests +bitwidth2 normal ivltests +blankport normal ivltests main # PR 204 Stephan Boettcher - +block_only_with_var_def normal ivltests +bnot normal ivltests # test triggered an overzealous assert in vvm +br605a normal ivltests +br605b normal ivltests +br916a normal ivltests gold=br916a.gold +br916b normal ivltests gold=br916b.gold +br918a normal ivltests +br918b normal ivltests +br918c normal ivltests +br918d normal ivltests +br919 normal ivltests +br924 CE ivltests +br930 CO ivltests +br931 normal ivltests +br935 normal ivltests +br937 normal,+string=0123456789 ivltests +br946 normal ivltests +br947 normal ivltests gold=br947.gold +br948 normal ivltests +br955 normal ivltests +br960a normal,-gspecify ivltests gold=br960a.gold +br960b normal,-gspecify ivltests gold=br960b.gold +br960c normal,-gspecify ivltests gold=br960c.gold +br960d normal,-gspecify ivltests gold=br960d.gold +br961 normal ivltests +br961a CE ivltests +br965 normal ivltests +br967 normal ivltests +br968 normal ivltests +br971 normal ivltests +br972 normal ivltests +br977 normal ivltests +br982 CE ivltests +br982a CE ivltests +br982b CE ivltests +br988 normal ivltests +br990 normal ivltests +br991a normal ivltests +br999 normal ivltests +br1000 normal ivltests +br1001 normal ivltests +br1006 normal,-gspecify ivltests +br1007 normal,-Wselect-range ivltests gold=br1007.gold +br1008 normal ivltests gold=br1008.gold +br1015a CE ivltests +br1019 normal ivltests +br1027 normal ivltests +br1027a CE ivltests gold=br1027a.gold +br1027c CE ivltests gold=br1027c.gold +br1027e CE ivltests gold=br1027e.gold +br1029a normal ivltests gold=br1029a.gold +br1029b normal ivltests gold=br1029a.gold +br1029c CE ivltests gold=br1029c.gold +br_gh6 normal ivltests +br_gh7 normal ivltests +br_gh8 normal ivltests +br_gh9 normal ivltests +br_gh11 CO ivltests +br_gh12 normal ivltests +br_gh13 normal ivltests +br_gh14 normal ivltests +br_gh15 normal ivltests +br_gh18 normal ivltests +br_gh19 normal ivltests +br_gh19a normal ivltests +br_gh19b normal ivltests +br_gh22 normal ivltests +br_gh25a CE ivltests +br_gh25b CE ivltests +br_gh26 CE ivltests +br_gh28 normal ivltests +br_gh30 normal ivltests +br_gh33 normal ivltests gold=br_gh33.gold +br_gh37 normal ivltests +br_gh60a CE ivltests +br_gh62 CE ivltests gold=br_gh62.gold +br_gh79 CE ivltests gold=br_gh79.gold +br_gh99a normal ivltests +br_gh99b normal ivltests +br_gh99d normal ivltests +br_gh99f normal ivltests +br_gh99g normal ivltests +br_gh99h normal ivltests +br_gh99i normal ivltests +br_gh99j normal ivltests +br_gh99k normal ivltests +br_gh99l normal ivltests +br_gh99m normal ivltests +br_gh99o normal ivltests +br_gh99p normal ivltests +br_gh99q normal ivltests +br_gh99r normal ivltests +br_gh99s normal ivltests +br_gh99t normal ivltests +br_gh99u normal ivltests +br_gh103 normal ivltests +br_gh127a normal ivltests gold=br_gh127a.gold +br_gh127b normal ivltests gold=br_gh127b.gold +br_gh127c normal ivltests gold=br_gh127c.gold +br_gh127d normal ivltests gold=br_gh127d.gold +br_gh127e normal ivltests gold=br_gh127e.gold +br_gh127f normal ivltests gold=br_gh127f.gold +br_gh142 CE ivltests +br_gh152 CE ivltests +br_gh157 normal ivltests gold=br_gh157.gold +br_gh162 normal ivltests +br_gh163 CE ivltests +br_gh198 normal ivltests gold=br_gh198.gold +br_gh199a normal ivltests +br_gh199b normal ivltests +br_gh209 normal ivltests diff=work/br_gh209.dat:gold/br_gh209.dat +br_gh230 RE ivltests gold=br_gh230.gold +br_gh244a normal ivltests +br_gh244b normal ivltests +br_gh277a normal ivltests +br_gh283a normal ivltests +br_gh283b normal ivltests +br_gh283c normal ivltests +br_gh309 normal ivltests +br_gh315 normal,-gspecify ivltests +br_gh316a normal,-gspecify ivltests +br_gh316b normal,-gspecify ivltests +br_gh316c normal,-gspecify ivltests +br_gh330 normal ivltests +br_gh345 normal ivltests +br_gh356a normal,-gspecify ivltests +br_gh356b normal,-gspecify ivltests +br_gh435 normal ivltests +br_gh484 normal ivltests +br_gh497a normal ivltests +br_gh497c normal ivltests +br_gh497e normal ivltests +br_gh508b normal ivltests +br_gh515 normal ivltests +br_gh531 normal ivltests gold=br_gh531.gold +br_gh533 CE ivltests +br_gh567 normal,-g2001 ivltests gold=br_gh567.gold +br_ml20150315 normal ivltests gold=br_ml_20150315.gold +br_ml20150321 CE ivltests +br_ml20150606 normal ivltests +br_mw20171108 normal ivltests +br_ml20190806a normal ivltests +br_ml20190806b normal ivltests +br_ml20190814 normal,-gspecify ivltests gold=br_ml20190814.gold +bufif normal ivltests # Validate bufif0, bufif1 +busbug normal ivltests gold=busbug.gold +ca_force normal ivltests +ca_func normal,-gstrict-ca-eval ivltests +ca_mult normal ivltests gold=ca_mult.gold +ca_pow_synth normal ivltests +ca_pow_unsigned normal ivltests +ca_real_logical normal ivltests +ca_time normal ivltests gold=ca_time.gold +case3.8A normal ivltests +case3.8B normal ivltests +case3.8C normal ivltests +case3.8D normal ivltests # test case for x and z exact match in labels. +casex3.9A normal ivltests +casex3.9B normal ivltests +casex3.9C normal ivltests +casex3.9D normal ivltests +casex3.9E normal ivltests +casez3.10A normal ivltests +casez3.10B normal ivltests +casez3.10C normal ivltests +casez3.10D normal ivltests +casez3.10E normal ivltests # Use ? and z in label +cast_int normal ivltests +check_constant_1 CE ivltests +check_constant_2 CE ivltests +check_constant_3 CE,-g1995 ivltests +check_constant_4 CE ivltests +check_constant_5 CE ivltests +check_constant_6 CE ivltests +check_constant_7 CE ivltests +check_constant_8 CE ivltests +check_constant_9 CE ivltests +check_constant_10 CE ivltests +check_constant_11 CE ivltests +check_constant_12 CE ivltests +check_constant_13 CE ivltests +check_constant_14 CE ivltests +check_constant_15 CE ivltests +check_constant_16 CE ivltests +check_constant_17 CE ivltests +check_constant_18 CE ivltests +check_constant_19 CE ivltests +check_constant_20 CE ivltests +cmos normal ivltests gold=cmos.gold +comment1 CE ivltests # PR410/411 +comp1000 normal ivltests gold=comp1000.gold +comp1001 normal ivltests gold=comp1001.gold +comp1001_fail3 normal ivltests +comp1001_fail4 normal ivltests +comp1001_fail5 normal ivltests +complex_lidx normal ivltests +con_tri normal ivltests # Contrib by S Williams +concat3 normal ivltests +concat4 normal ivltests +concat_zero_wid_fail CE ivltests +concat_zero_wid_fail2 normal ivltests +cond_band normal ivltests # Bitwise and in if condition +cond_wide normal ivltests # condition is a wide value +cond_wide2 normal ivltests # condition is a wide value +const normal ivltests # PR 122 - Steve Tell - const without length spec. +const2 normal ivltests # Some cases that the DCM module trips. +const3 normal ivltests +const4 normal ivltests +constadd normal ivltests +constadd2 normal ivltests +constadd3 normal ivltests +constfunc1 normal ivltests +constfunc2 normal ivltests +constfunc3 normal ivltests +constfunc4 normal ivltests +constfunc5 normal ivltests +constfunc6 normal ivltests +constfunc7 normal ivltests +constfunc9 normal ivltests +constfunc10 normal ivltests +constfunc11 normal ivltests +constfunc12 normal ivltests +constfunc13 normal ivltests +constfunc14 normal ivltests +constfunc15 normal ivltests +constmult normal ivltests +consttern normal ivltests +contrib8.1 normal ivltests +contrib8.2 normal ivltests test # Add the 4th optional argument -s test +contrib8.3 CE ivltests +contrib8.4 normal ivltests +contrib8.5 normal ivltests # Add the 4th optional argument -s test +countdrivers1 normal ivltests +countdrivers2 normal ivltests +countdrivers3 normal ivltests +countdrivers4 normal ivltests +countdrivers5 normal ivltests +cprop normal ivltests +credence20041209 normal ivltests +dangling_port normal ivltests # PR#209: dangling port optimization (VVP) +dcomp1 normal ivltests gold=dcomp1.gold +deassign3.4A normal ivltests +decl_assign1 normal ivltests +def_nettype normal ivltests +def_nettype_none CE ivltests gold=def_nettype_none.gold +define1 normal ivltests # Use defined value for reg def and reg assign +defparam normal ivltests main # defparams with list +defparam2 normal ivltests gold=defparam2.gold +defparam3 normal ivltests gold=defparam3.gold +defparam3.5 normal ivltests # defparam(single) +defparam4 normal ivltests gold=defparam4.gold +delay normal ivltests gold=delay.gold +delay2 normal ivltests +delay3 normal ivltests +delay4 normal ivltests +delay5 normal ivltests +delay_assign_nb normal ivltests +delay_assign_nb2 normal ivltests +delay_var normal ivltests gold=delay_var.gold +delayed_comp_reduct normal ivltests +dff1 normal ivltests # Contrib by S Williams +disable3.6A normal ivltests +disable3.6B normal ivltests +disable_cleanup normal ivltests +disable_fork normal ivltests +disblock normal ivltests # PR280 +disblock2 normal ivltests gold=disblock2.gold +disp_dec normal ivltests gold=disp_dec.gold +disp_dec2 normal ivltests gold=disp_dec2.gold +disp_leading_z normal ivltests gold=disp_leading_z.gold +disp_parm normal ivltests gold=disp_parm.gold +disp_part normal ivltests gold=disp_part.gold +div16 normal contrib test_div16 # Uses $random and divide operator (Tom Coonan) +dotinid normal ivltests # escaped names with . dots +drive_strength normal ivltests # Contributed test +drive_strength1 normal ivltests +drive_strength2 normal ivltests gold=drive_strength2.gold +drive_strength3 normal ivltests +dummy7 normal ivltests gold=dummy7.gold +dump_memword normal ivltests diff=work/test.vcd:gold/dump_memword.vcd:2 +dumpvars normal ivltests # PR#174: dumpvars non-hierarchical arguments +eeq normal ivltests # === and !== in structural context +else1 normal ivltests # ifdef with else +else2 normal ivltests # compound ifdef with else +else3 normal ivltests # compound ifdef compound else +elsif_test normal ivltests +eq normal ivltests +escape1 normal ivltests # \$modulename in defparam and if() +escape2a CO ivltests +escape2b CO ivltests +escape2c CO ivltests +escape3 normal ivltests +escape4 normal ivltests +escape4b normal ivltests +event2 normal ivltests +event3 normal ivltests gold=event3.gold +event3.15 normal ivltests # Validate event lists, and -> operator. +event_array CE ivltests +event_list normal ivltests # Contrib by S Williams +event_list2 normal ivltests # Contrib by S Williams +event_list3 normal ivltests gold=event_list3.gold +extend normal ivltests +fdisplay1 normal ivltests gold=fdisplay1.gold +fdisplay2 normal ivltests diff=work/fdisplay2.out:gold/fdisplay2.out +fdisplay3 RE ivltests gold=fdisplay3.gold +fdisplay_fail_fd normal ivltests gold=fdisplay_fail_fd.gold +fdisplay_fail_mcd normal ivltests gold=fdisplay_fail_mcd.gold +fifo normal contrib +fopen1 normal ivltests # Test basic fopen operation +fopen2 normal ivltests # Test basic fopen operation +for3.16A normal ivltests +force1 normal ivltests +force2 normal ivltests +force3.17A normal ivltests +force3.17B normal ivltests +force3.17C normal ivltests +force_lval_part normal ivltests +force_release_reg_pv normal ivltests +force_release_wire8_pv normal ivltests +force_release_wire_pv normal ivltests +fork1 normal ivltests # Validate 3 way fork with simple assignments. +fork3.19A normal ivltests +fork3.19B normal ivltests +format normal ivltests gold=format.gold +fr47 normal ivltests +fread normal ivltests +fread-error RE ivltests gold=fread-error.gold +fscanf_u normal ivltests +fscanf_u_warn normal ivltests gold=fscanf_u_warn.gold +fscanf_z normal ivltests +fscanf_z_warn normal ivltests gold=fscanf_z_warn.gold +function1 normal ivltests gold=function1.gold +function2 normal ivltests +function3 normal ivltests +function3.11B normal ivltests +function3.11C normal ivltests +function3.11D normal ivltests +function3.11F normal ivltests +function4 CE ivltests # Functions must have at least one argument +function5 CO ivltests # PR 184 +function6 normal ivltests +function7 normal ivltests +function8 normal ivltests +function9 normal ivltests +function_exp normal ivltests # Contrib by S Williams +ga_and normal ivltests +ga_mod normal ivltests main +ga_mod1 normal ivltests main +ga_mod2 normal ivltests main +ga_nand normal ivltests +ga_nor normal ivltests +ga_or normal ivltests +ga_xnor normal ivltests +ga_xor normal ivltests +galan normal ivltests # Ternary test with varying size lhs vs rhs +gate_connect1 normal ivltests +gate_connect2 CE ivltests gold=gate_connect2.gold +gen_case_opt1 normal ivltests +gen_case_opt2 normal ivltests +gen_case_opt3 normal ivltests +gencrc normal contrib # 32/16 bit crc +generate_case normal ivltests +generate_case2 normal ivltests +generate_case3 normal ivltests +generate_multi_loop normal ivltests gold=generate_multi_loop.gold +genloop normal ivltests +genvar_scopes normal ivltests +hello1 normal ivltests +hier_ref_error CE ivltests +hierspace normal ivltests # whitespace.around .dots. in. hierarchical .names +idiv1 normal ivltests # Contrib by S Williams +idiv2 normal ivltests # Int div within an expression +idiv3 normal ivltests gold=idiv3.gold +ifdef1 normal ivltests # ifdef with no define +ifdef2 normal ivltests # ifdef with define +ifdef3 normal ivltests # compound ifdef with 1 define +ifdef4 normal ivltests # compound ifdef with 2 defines +ifdef_fail CE ivltests +include1 normal ivltests # include file 1 level deep +include2 normal ivltests # include file 2 levels deep +include3 normal ivltests # include file 3 levels deep +indef_width_concat CE ivltests gold=indef_width_concat.gold +initmod normal ivltests gold=initmod.gold +initmod2 normal ivltests gold=initmod2.gold +inout normal ivltests # modname(a,a); inout a; +inout2 normal ivltests +inout3 normal ivltests +inout4 normal ivltests +int_not_signext normal ivltests gold=int_not_signext.gold +integer1lt normal ivltests +integer2le normal ivltests +integer3gt normal ivltests +integer4ge normal ivltests +integer5 normal ivltests +itor_rtoi normal ivltests gold=itor_rtoi.gold +land2 normal ivltests +land3 normal ivltests +land4 normal ivltests gold=land4.gold +landor1 normal ivltests +ldelay1 normal ivltests +ldelay2 normal ivltests +ldelay3 normal ivltests +ldelay4 normal ivltests +ldelay5 normal ivltests +lh_catadd normal ivltests +lh_memcat normal ivltests gold=lh_memcat.gold +lh_memcat2 normal ivltests +lh_memcat3 normal ivltests +lh_varindx normal ivltests +lh_varindx2 normal ivltests +lh_varindx4 normal ivltests +lh_varindx5 normal ivltests +localparam_type normal ivltests gold=parameter_type.gold +long_div normal ivltests gold=long_div.gold +macro2 normal ivltests +macro_redefinition normal,-Wmacro-redefinition ivltests gold=macro_redefinition.gold +macro_replacement normal,-Wmacro-replacement ivltests gold=macro_replacement.gold +macsub normal ivltests +mangle normal ivltests +mangle_1 normal ivltests +many_drivers normal ivltests # net with many drivers +mcl2 normal ivltests gold=mcl2.gold +mem1 normal ivltests gold=mem1.gold +mem2port normal ivltests # memory ports with constant address +memassign normal ivltests # PR 126 - daavid Leask - assign bus part fm memory item +memidx normal ivltests # PR 221 +memidxrng normal ivltests # PR 271 memory address range checks +meminit normal ivltests +meminit2 normal ivltests +memport_bs normal ivltests # PR#303 +memref normal ivltests +mhead_task normal ivltests # Verify hierarchical task name in another mod. +mixed_type_div_mod normal ivltests +mixed_width_case normal ivltests +modparam normal ivltests top # Override parameter via passed down value +module3.12A normal ivltests main +module3.12B normal ivltests +modulus normal ivltests # wire % and reg % operators +modulus2 normal ivltests # reg % operators +monitor normal ivltests gold=monitor.gold +monitor2 normal ivltests gold=monitor2.gold +monitor3 normal ivltests gold=monitor3.gold +mult1 normal ivltests # wire * and reg * operators +mult16 normal contrib mul16 # Contributed by Tom Coonan - has $random +mult2 normal ivltests # wire * and reg * operators +multi_bit_strength normal ivltests gold=multi_bit_strength.gold +multi_driver_delay normal ivltests +multiply_large normal ivltests # Takes care of PR222 +muxtest normal ivltests # Validates that X sel and inputs same, output not X +named_event_no_edges CE ivltests +nb_assign normal ivltests +nb_delay normal ivltests +nblkorder normal ivltests # Validates Non-blocking order determinism +negative_genvar normal ivltests +negvalue normal ivltests gold=negvalue.gold +neq1 normal ivltests gold=neq1.gold +nested_func normal ivltests gold=nested_func.gold +nested_impl_event1 normal ivltests gold=nested_impl_event1.gold +nested_impl_event2 normal ivltests gold=nested_impl_event2.gold +no_if_statement CE ivltests +no_timescale_in_module CE ivltests +npmos normal ivltests +npmos2 normal ivltests +onehot normal contrib # one hot design +p_monta normal ivltests +par_mismatch CE,-gspecify ivltests +param-extend normal ivltests +param-width normal ivltests gold=param-width.gold +param_add normal ivltests # Addition in param declar +param_and normal ivltests # bitwise & +param_and2 normal ivltests # logical && in param declar +param_band normal ivltests # Bitwise and in param declar +param_binv normal ivltests # Bit vector inv in param declar +param_bor normal ivltests # Bitwise OR in param declar +param_concat normal ivltests # param has concat value (pmonta) +param_eq3 normal ivltests # Bit equiv in param declar +param_expr normal ivltests # & in param declar +param_mod normal ivltests # Modulus in param declar +param_select normal ivltests # bit and part select of parameters. +param_select2 normal ivltests # bit and part select of parameters. +param_select3 normal ivltests # bit and part select of parameters. +param_string normal ivltests # parameter storing a string. +param_tern normal ivltests +param_tern2 normal ivltests +param_test1 normal ivltests gold=param_test1.gold +param_test2 normal ivltests gold=param_test2.gold +param_test3 normal ivltests gold=param_test3.gold # PR#293 +param_test4 normal ivltests +param_times normal ivltests # param has multiplication. +parameter_type normal ivltests gold=parameter_type.gold +patch1268 normal ivltests +pca1 normal ivltests # Procedural Continuous Assignment in a mux +pic normal contrib pictest gold=pic.gold +port-test2 normal ivltests # Port declaration syntax checks +port-test3 CE ivltests # Port declaration syntax checks +port-test4a CE ivltests # Port declaration input duplication checks (PR394) +port-test4b CE ivltests # Port declaration output duplication checks (PR394) +port-test5 normal ivltests # demonstrates 2001 module port syntax +port-test6 normal ivltests # demonstrates 2001 module port syntax +port-test7 normal ivltests # demonstrates 2001 module port syntax +posedge normal ivltests # Contrib by S Williams +pow-ca normal ivltests +pow-const normal ivltests +pow-proc normal ivltests +pow_ca_signed normal ivltests +pow_ca_unsigned normal ivltests +pow_reg_signed normal ivltests +pow_reg_unsigned normal ivltests +pow_signed normal ivltests +pow_unsigned normal ivltests +pr136 normal ivltests # PR136 param foo_size 8 * 4 +pr142 normal ivltests # Test for PR142 +pr183 CO,-gno-specify ivltests +pr224 normal ivltests # reg [3:0] ack; ... @(posedge ack) +pr224a normal ivltests # reg [3:0] ack; ... @(posedge ack[p]) +pr243 normal ivltests gold=pr243.gold +pr245 normal ivltests gold=pr245.gold +pr245_std normal ivltests gold=pr245.gold +pr273 normal ivltests # Non-constant bit select in ordered list. +pr298 normal ivltests gold=pr298.gold +pr304 normal ivltests # test for PR304 +pr307 normal ivltests # wide adds +pr307a normal ivltests # wide adds +pr312 normal ivltests +pr338 CO ivltests # pr 338 - constant zz see also constadd2.v +pr355 normal ivltests +pr377 normal ivltests gold=pr377.gold +pr434 normal ivltests gold=pr434.gold +pr445 normal ivltests +pr478 normal ivltests +pr487 normal ivltests gold=pr487.gold +pr492 normal ivltests gold=pr492.gold +pr508 normal ivltests +pr509 normal ivltests +pr509b normal ivltests +pr511 normal ivltests +pr513 normal ivltests +pr522 normal ivltests gold=pr522.gold +pr524 normal ivltests gold=pr524.gold +pr527 normal ivltests gold=pr527.gold +pr528 normal ivltests gold=pr528.gold +pr528b normal ivltests gold=pr528b.gold +pr529 normal ivltests +pr530a normal ivltests gold=pr530.gold +pr530b normal ivltests gold=pr530.gold +pr530c normal ivltests gold=pr530.gold +pr531a normal ivltests gold=pr531a.gold +pr531b normal ivltests gold=pr531a.gold +pr532 normal ivltests gold=pr532.gold +pr532b normal ivltests gold=pr532.gold +pr533 normal ivltests gold=pr533.gold +pr538 normal ivltests gold=pr538.gold +pr540 normal ivltests gold=pr540.gold +pr540b normal ivltests gold=pr540b.gold +pr540c normal ivltests gold=pr540c.gold +pr541 normal ivltests gold=pr541.gold +pr542 normal ivltests gold=pr542.gold +pr544 normal ivltests gold=pr544.gold +pr547 normal ivltests gold=pr547.gold +pr556 normal ivltests gold=pr556.gold +pr564 normal ivltests +pr569 normal ivltests gold=pr569.gold +pr572 normal ivltests gold=pr572.gold +pr572b normal ivltests gold=pr572.gold +pr578 normal ivltests +pr584 normal ivltests gold=pr584.gold +pr585 normal ivltests +pr587 normal ivltests +pr590 normal ivltests gold=pr590.gold +pr594 normal ivltests gold=pr594.gold +pr596 normal ivltests gold=pr596.gold +pr602 normal ivltests +pr617 normal ivltests +pr632 normal ivltests gold=pr632.gold +pr673 normal ivltests gold=pr673.gold +pr675 normal ivltests +pr678 normal ivltests +pr690 normal ivltests +pr693 normal ivltests gold=pr693.gold +pr699 normal ivltests +pr699b normal ivltests +pr704 normal ivltests # Uses ivltests/pr704.hex +pr707 normal ivltests +pr708 normal ivltests +pr710 normal ivltests +pr718 normal ivltests +pr722 normal ivltests +pr729 normal ivltests gold=pr729.gold +pr734 normal ivltests +pr735 normal ivltests +pr748 normal ivltests +pr751 normal,-Wsensitivity-entire-vector ivltests gold=pr751.gold +pr757 normal ivltests +pr772 normal ivltests +pr810 normal ivltests +pr812 normal ivltests gold=pr812.gold +pr820 normal ivltests gold=pr820.gold +pr823 normal ivltests +pr841 normal ivltests +pr842 normal ivltests +pr848 normal ivltests +pr856 normal ivltests +pr859 normal ivltests +pr860 normal ivltests +pr872 normal ivltests +pr902 normal ivltests gold=pr902.gold +pr905 normal ivltests gold=pr905.gold +pr910 normal ivltests gold=pr910.gold +pr913 normal ivltests +pr923 normal ivltests gold=pr923.gold +pr938 normal ivltests gold=pr938.gold +pr938b normal ivltests gold=pr938.gold +pr938b_std normal ivltests gold=pr938.gold +pr941 normal ivltests +pr973 normal ivltests +pr978 normal ivltests +pr985 normal ivltests gold=pr985.gold +pr987 normal ivltests gold=pr987.gold +pr990 normal ivltests +pr991 normal ivltests gold=pr991.gold +pr993 normal ivltests gold=pr993.gold +pr995 normal ivltests gold=pr995.gold +pr1002 normal ivltests gold=pr1002.gold +pr1002a normal ivltests gold=pr1002a.gold +pr1007 normal ivltests +pr1008 normal ivltests gold=pr1008.gold +pr1022 normal ivltests +pr1024 normal ivltests +pr1026 normal ivltests gold=pr1026.gold +pr1029 normal ivltests +pr1032 normal ivltests +pr1033 normal ivltests gold=pr1033.gold +pr1065 normal ivltests gold=pr1065.gold +pr1072 normal ivltests +pr1077 normal,-g2 ivltests gold=pr1077.gold +pr1087 normal ivltests +pr1101 normal ivltests +pr1115 normal ivltests +pr1353345 normal ivltests +pr1353345b normal ivltests +pr1367855 normal ivltests +pr1380261 normal ivltests +pr1403406 normal ivltests gold=pr1403406.gold +pr1403406a normal,-fivltests/pr1403406-1.cf ivltests gold=pr1403406a.gold +pr1403406b normal,-fivltests/pr1403406-1.cf,-fivltests/pr1403406-2.cf ivltests gold=pr1403406b.gold +pr1421777 normal ivltests +pr1444055 normal ivltests +pr1449749a normal ivltests +pr1455873 normal ivltests +pr1465769 normal ivltests +pr1467825 CO,-gno-specify ivltests +pr1474283 normal ivltests +pr1474316 normal ivltests +pr1474318 normal ivltests +pr1476440 normal ivltests gold=pr1476440.gold +pr1477190 normal ivltests +pr1478121 normal ivltests +pr1478988 normal ivltests +pr1489568 normal ivltests +pr1489570 normal ivltests +pr1491355 normal ivltests +pr1492075 normal ivltests gold=pr1492075.gold +pr1508882 normal ivltests +pr1510724 normal ivltests +pr1515168 normal ivltests +pr1520314 CO ivltests +pr1522570 normal ivltests +pr1530426 normal ivltests +pr1561597 normal ivltests +pr1565544 normal ivltests +pr1565699b normal ivltests +pr1570451 normal ivltests +pr1570451b normal ivltests +pr1570635 normal ivltests +pr1570635b normal ivltests +pr1574175 normal ivltests gold=pr1574175.gold +pr1581580 normal ivltests +pr1587634 CO,-Ttyp ivltests +pr1587669 normal,-gspecify ivltests gold=pr1587669.gold +pr1589497 normal ivltests gold=pr1589497.gold +pr1598445 normal ivltests +pr1601896 normal ivltests +pr1601898 normal ivltests +pr1603313 normal ivltests +pr1603918 normal ivltests +pr1612693 normal ivltests +pr1623097 normal ivltests gold=pr1623097.gold +pr1625912 normal ivltests +pr1628288 normal ivltests gold=pr1628288.gold +pr1628300 normal ivltests gold=pr1628300.gold +pr1629683 normal ivltests gold=pr1629683.gold +pr1632861 normal ivltests gold=pr1632861.gold +pr1634526 normal ivltests gold=pr1634526.gold +pr1636409 normal ivltests gold=pr1636409.gold +pr1637208 normal ivltests +pr1638985 normal ivltests gold=pr1638985.gold +pr1639060 normal ivltests gold=pr1639060.gold +pr1639064 normal ivltests gold=pr1639064.gold +pr1639064b normal ivltests gold=pr1639064b.gold +pr1639968 normal ivltests gold=pr1639968.gold +pr1639971 normal ivltests gold=pr1639971.gold +pr1645277 normal ivltests gold=pr1645277.gold +pr1645518 normal ivltests gold=pr1645518.gold +pr1648365 normal ivltests gold=pr1648365.gold +pr1650842 normal ivltests +pr1657307 normal ivltests +pr1661640 normal ivltests gold=pr1661640.gold +pr1662508 normal ivltests +pr1664684 normal ivltests gold=pr1664684.gold +pr1675789 normal ivltests +pr1675789b normal ivltests +pr1676071 normal ivltests +pr1676836 normal ivltests +pr1682887 normal ivltests +pr1687193 normal ivltests gold=pr1687193.gold +pr1688717 normal ivltests gold=pr1688717.gold +pr1690058 normal ivltests +pr1691599b normal ivltests +pr1691709 normal ivltests +pr1693890 normal ivltests +pr1693921 normal ivltests +pr1694413 normal ivltests +pr1694427 normal ivltests +pr1695257 CO ivltests +pr1695309 normal ivltests +pr1695322 normal ivltests +pr1695334 normal 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normal ivltests gold=pr2001162.gold +pr2011429 normal ivltests +pr2013758 normal ivltests +pr2014673 normal ivltests +pr2015466 normal ivltests +pr2018235a normal ivltests +pr2018235b normal ivltests +pr2018305 normal ivltests +pr2019553 normal ivltests +pr2029336 normal ivltests diff=work/pr2029336.out:gold/pr2029336.gold +pr2030767 normal ivltests +pr2036953 normal ivltests +pr2038048 normal ivltests +pr2039632 CE ivltests +pr2039694 normal ivltests gold=pr2039694.gold +pr2043324 normal ivltests +pr2043585 normal,-Wsensitivity-entire-array ivltests gold=pr2043585.gold +pr2051694 CE ivltests +pr2051975 CE ivltests +pr2053944 normal ivltests gold=pr2053944.gold +pr2076363 normal ivltests +pr2076391 normal ivltests gold=pr2076391.gold +pr2076425 normal ivltests +pr2085984 normal ivltests +pr2091455 normal ivltests gold=pr2091455.gold +pr2109179 normal ivltests +pr2117473 normal ivltests +pr2117488 normal ivltests +pr2119622 normal ivltests gold=pr2119622.gold +pr2121536 normal ivltests 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ivltests +pr2202706b normal,+option ivltests +pr2202706c normal,+hex=123456789abcdef_x_z,+oct=1234567_x_z,+bin=101_x_z,+dec=123456789_,+dec_x=x,+dec_z=z_,+neg=-1_00,+real=12.3456789,+neg_real=-23.456e+3,+real_inf=Inf,+bad_num=not_a_num,+warn_real=9.825units ivltests +pr2202846a normal ivltests +pr2202846b normal ivltests +pr2202846c normal ivltests +pr2208681 normal ivltests +pr2215342 normal,-grelative-include ivltests +pr2219441 normal ivltests +pr2219441b normal ivltests +pr2224845 normal ivltests +pr2224949 normal ivltests +pr2233180 normal ivltests +pr2233180b normal ivltests +pr2233180c normal ivltests +pr2233192 normal ivltests +pr2233192b normal ivltests +pr2233192c normal ivltests +pr2248925 normal ivltests gold=pr2248925.gold +pr2251119 normal ivltests gold=pr2251119.gold +pr2257003 normal ivltests +pr2257003b normal ivltests +pr2270035 normal ivltests +pr2276163 normal ivltests +pr2281479 normal ivltests +pr2305307 normal ivltests +pr2305307b normal ivltests +pr2305307c normal ivltests +pr2306259 normal ivltests +pr2350934 normal ivltests +pr2350934b normal ivltests +pr2350988 normal ivltests +pr2352834 normal ivltests +pr2355304 normal ivltests +pr2355304b normal ivltests +pr2358264 normal ivltests +pr2358848 normal ivltests +pr2395378a CE ivltests +pr2395378b CE ivltests +pr2395378c CE ivltests +pr2395835 normal ivltests +pr2425055a normal ivltests +pr2425055b normal ivltests +pr2425055c normal ivltests +pr2428890 normal ivltests +pr2428890b normal ivltests +pr2434688 normal ivltests +pr2434688b normal ivltests +pr2450244 normal ivltests +pr2453002 normal ivltests +pr2459681 normal ivltests +pr2470181a normal ivltests +pr2470181b normal ivltests +pr2503208 normal ivltests +pr2528915 CE ivltests +pr2533175 normal ivltests +pr2579479 normal ivltests +pr2580730 normal ivltests gold=pr2580730.gold +pr2593733 normal ivltests +pr2597278 normal ivltests +pr2597278b CE ivltests +pr2605006 normal ivltests +pr2673846 normal ivltests +pr2688910 normal ivltests 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gold=pr3015421.gold +pr3022502 normal ivltests +pr3024131 normal ivltests +pr3039548 normal ivltests gold=pr3039548.gold +pr3044843 normal ivltests +pr3054101a normal ivltests gold=pr3054101a.gold +pr3054101b normal ivltests gold=pr3054101a.gold +pr3054101c normal ivltests gold=pr3054101c.gold +pr3054101d normal ivltests gold=pr3054101c.gold +pr3054101e normal ivltests gold=pr3054101e.gold +pr3054101f normal ivltests gold=pr3054101e.gold +pr3054101g normal ivltests gold=pr3054101g.gold +pr3054101h normal ivltests gold=pr3054101g.gold +pr3061015a CE ivltests +pr3061015b CE ivltests +pr3061015c CE ivltests +pr3064375 normal ivltests gold=pr3064375.gold +pr3064511 normal ivltests +pr3077640 normal ivltests +pr3078759 CO,-gspecify ivltests +pr3098439 normal ivltests +pr3098439a normal ivltests +pr3098439b normal ivltests +pr3103880 normal ivltests +pr3104254 normal ivltests +pr3112073a CE ivltests +pr3149494 normal ivltests gold=pr3149494.gold +pr3190941 CE ivltests gold=pr3190941.gold +pr3190948 normal ivltests +pr3194155 normal ivltests gold=pr3194155.gold +pr3197861 normal ivltests +pr3197917 normal ivltests +pr3270320 CE ivltests +pr3284821 normal ivltests +pr3292735 normal ivltests +pr3296466a normal ivltests +pr3296466b normal ivltests +pr3296466c normal ivltests +pr3296466d normal ivltests +pr3306516 normal,-gspecify ivltests +pr3309391 normal ivltests +pr3368642 normal ivltests +pr3409749 normal ivltests +pr3437290a normal ivltests +pr3437290b normal ivltests +pr3437290c normal ivltests +pr3441576 normal ivltests gold=pr3441576.gold +pr3445452 normal ivltests +pr3452808 normal ivltests +pr3465541 normal ivltests +pr3477107 normal ivltests +pr3499807 normal ivltests gold=pr3499807.gold +pr3522653 normal ivltests gold=pr3522653.gold +pr3527022 normal ivltests +pr3527694 normal ivltests gold=pr3527694.gold +pr3534422 normal ivltests +pr3539372 normal ivltests +pr3549328 CE ivltests +pr3557493 normal ivltests +pr3561350 normal ivltests +pr3563412 normal ivltests +pr3571573 normal ivltests gold=pr3571573.gold +pr3582052 normal ivltests +pr3587570 normal ivltests +pr3592746 normal ivltests +prng normal ivltests +ptest001 normal ivltests +ptest002 normal ivltests +ptest003 normal ivltests +ptest004 normal ivltests +ptest005 normal ivltests +ptest006 normal ivltests +ptest007 normal ivltests +ptest008 normal ivltests +ptest009 normal ivltests +ptest010 normal ivltests +ptest011 normal ivltests +pullupdown normal ivltests # Contributed test +pullupdown2 normal ivltests # Contributed test +pullupdown3 normal ivltests # Contributed test +pv_undef_sig_sel normal ivltests +qmark normal ivltests +qmark1 normal ivltests +qmark3 normal ivltests +qmark5 normal ivltests +qmark6 normal ivltests +queue normal ivltests +queue_fail RE ivltests gold=queue_fail.gold +queue_stat normal ivltests gold=queue_stat.gold +ram16x1 normal ivltests # Sitting here for a long time? +readmem-error normal ivltests gold=readmem-error.gold +readmem-invalid RE ivltests gold=readmem-invalid.gold +readmemb1 normal ivltests # basic $readmemb - uses readmemh1.dat +readmemb2 normal ivltests # $readmemb w/ short data file - readmemh2.dat +readmemb3 normal ivltests # $readmemb 0-3 with long dfile - readmemh1.dat +readmemh1 normal ivltests # basic $readmemh - uses readmemh1.dat +readmemh1a normal ivltests # basic $readmemh with @addr - uses readmemh1a.dat +readmemh2 normal ivltests # $readmemh w/ short data file - readmemh2.dat +readmemh3 normal ivltests # $readmemh 0-3 with long dfile - readmemh1.dat +readmemh4 normal ivltests # $readmemh - comments in data file +readmemh5 CE ivltests # Should be error for readmemh(romimg,rom[0:7]) +real normal ivltests +real2 normal ivltests +real3 normal ivltests +real5 normal ivltests gold=real5.gold +real6 normal ivltests +real7 normal ivltests +real9 normal ivltests +real10 normal ivltests +real11 normal ivltests +real_assign_deassign normal ivltests +real_concat_invalid2 CE ivltests +real_delay normal,-gspecify ivltests gold=real_delay.gold +real_events normal ivltests gold=real_events.gold +real_force_rel normal ivltests +real_invalid_ops CE ivltests gold=real_invalid_ops.gold +real_logical normal ivltests +real_reg_force_rel normal ivltests +recursive_func normal ivltests gold=recursive_func.gold +recursive_task normal ivltests gold=recursive_task.gold +redef_net_error CE ivltests +redef_reg_error CE ivltests +repeat2 normal ivltests +repeat_expr_probe normal ivltests +repl_zero_wid_fail CE ivltests +repl_zero_wid_pass normal ivltests +resetall normal,-Wtimescale ivltests gold=resetall.gold +resetall2 normal,-Wtimescale ivltests gold=resetall2.gold +resolv1 normal ivltests # PR#300 +rise_fall_decay1 normal ivltests +rise_fall_decay2 normal ivltests +rise_fall_delay1 normal ivltests +rise_fall_delay2 normal ivltests +rise_fall_delay3 normal ivltests +rl_pow normal ivltests +rnpmos normal ivltests +rnpmos2 normal ivltests +rop normal ivltests +rptconcat normal ivltests # Repeat concatenation operation. +rtran normal ivltests gold=rtran.gold +rtranif0 normal ivltests gold=rtranif0.gold +rtranif1 normal ivltests gold=rtranif1.gold +scan-invalid RE ivltests gold=scan-invalid.gold +scanf normal ivltests +scanf2 normal ivltests +scanf3 normal ivltests +scanf4 normal ivltests +sched1 normal ivltests +sched2 normal ivltests +schedule normal ivltests +scope1 normal ivltests # scope of var into a task +scope2 normal ivltests # scope of var stops at module boundaries +scope2b CE,-g1 ivltests # broken version of scope2 +scope4 normal ivltests +scope5 normal ivltests +scoped_events normal ivltests gold=scoped_events.gold +sdf1 normal,-gspecify ivltests gold=sdf1.gold +sdf2 normal,-gspecify ivltests gold=sdf1.gold +sdf3 normal,-gspecify ivltests gold=sdf1.gold +sdf4 normal,-gspecify ivltests gold=sdf1.gold +sdf5 normal,-gspecify ivltests gold=sdf5.gold +sdf6 normal,-gspecify ivltests gold=sdf6.gold +sdf7 normal,-gspecify ivltests gold=sdf7.gold +sdf8 normal,-gspecify ivltests gold=sdf8.gold +sdf_del_max normal,-gspecify,-Tmax ivltests +sdf_del_min normal,-gspecify,-Tmin ivltests +sdf_del_typ normal,-gspecify,-Ttyp ivltests +sdf_esc_id normal,-gspecify ivltests gold=sdf1.gold +sdw_always1 normal ivltests +sdw_always2 normal ivltests +sdw_always3 normal ivltests +sdw_array normal ivltests +sdw_assign normal ivltests +sdw_dsbl normal ivltests +sdw_force normal ivltests +sdw_function1 normal ivltests +sdw_function2 normal ivltests +sdw_function3 normal ivltests +sdw_function4 normal ivltests # function with if from George Gallant bug rpt +sdw_function5 normal ivltests # function with if from George Gallant bug rpt +sdw_instmod1 normal ivltests +sdw_instmod2 normal ivltests +sdw_int normal ivltests +sdw_lvalconcat normal ivltests +sdw_param1 normal ivltests +sdw_param2 normal ivltests +sdw_release normal ivltests +sdw_stmt002 normal ivltests +sdw_task1 normal ivltests +sdw_task2 normal ivltests +sel_rval_bit_ob normal,-Wselect-range ivltests gold=sel_rval_bit_ob.gold +sel_rval_part_ob normal,-Wselect-range ivltests gold=sel_rval_part_ob.gold +select normal ivltests # structural word select +select2 normal ivltests # structural bit select +select3 normal ivltests gold=select3.gold +select4 normal ivltests # structural bit select +select5 normal ivltests # structural bit select +select6 normal ivltests +select7 normal ivltests +select8 normal ivltests +select_padding normal ivltests +shellho1 normal ivltests top gold=shellho1.gold +shift1 normal ivltests gold=shift1.gold +shift2 normal ivltests +shift3 normal ivltests +shift4 normal ivltests +shift5 normal ivltests gold=shift5.gold +shift_pad normal ivltests +signed1 normal ivltests +signed2 normal ivltests +signed3 normal ivltests +signed4 normal ivltests gold=signed4.gold +signed5 normal ivltests +signed6 normal ivltests +signed7 normal ivltests +signed8 normal ivltests +signed9 normal ivltests +signed10 normal ivltests gold=signed10.gold +signed11 normal ivltests +signed12 normal ivltests gold=signed12.gold +signed13 normal ivltests +signed_a normal ivltests +signed_equality normal ivltests +signed_net_display normal ivltests +signed_part normal ivltests +signed_pv normal ivltests +sp2 normal ivltests diff=work/sp2.inv:gold/sp2.inv +specify1 CO ivltests +specify2 normal,-gspecify ivltests +specify3 normal,-gspecify ivltests gold=specify3.gold +specify4 normal,-gspecify ivltests gold=specify4.gold +specify5 normal,-gspecify ivltests gold=specify5.gold +specify_01 normal,-gspecify ivltests test # Yet another version of specify +sqrt32 normal ivltests +sscanf_u normal ivltests +sscanf_z normal ivltests +stask_parm1 normal ivltests +stask_parm2 normal ivltests gold=stask_parm2.gold +stask_sens_null_arg normal ivltests +string1 normal ivltests +string2 normal ivltests +string3 normal ivltests +string4 normal ivltests gold=string4.gold +string5 normal ivltests gold=string5.gold +string7 normal ivltests gold=string7.gold +string8 normal ivltests gold=string8.gold +string9 normal ivltests gold=string9.gold +string10 normal ivltests gold=string10.gold +string11 normal ivltests gold=string11.gold +string12 normal ivltests +supply1 normal ivltests +supply2 normal ivltests +switch_primitives normal ivltests gold=switch_primitives.gold +sys_func_task_error RE ivltests gold=sys_func_task_error.gold +talu normal ivltests +task-scope normal ivltests +task3.14A normal ivltests +task3.14B normal ivltests +task3.14C normal ivltests +task3.14D normal ivltests +task3.14E normal ivltests +task3.14F normal ivltests +task_bypath normal ivltests # task enabled by complete path name. +task_inpad normal ivltests # Validates input of task should pad w/ 0 +task_iotypes normal ivltests # task ports with types. +task_iotypes2 normal ivltests # task ports with types. +task_mem normal ivltests +task_noop normal ivltests # Task with no contents. +task_noop2 CO ivltests # Task *really* with no contents. +task_omemw2 normal ivltests +task_omemw3 CO ivltests # Pass bit selected from vector to task +task_port_size normal ivltests # truncate task port connections +task_scope normal ivltests +tern1 normal ivltests # Finds problems with ?: using different sizes +tern2 CO ivltests # make sure ?: is recognized by -tnull +tern4 normal ivltests +tern5 normal ivltests gold=tern5.gold +tern6 normal ivltests +tern7 normal ivltests +tern9 normal ivltests +tern10 normal ivltests +test_bufif0 normal ivltests +test_bufif1 normal ivltests +test_disphob normal ivltests gold=test_disphob.gold +test_dispwided normal ivltests gold=test_dispwided.gold +test_extended normal ivltests gold=test_extended.gold +test_mos_strength_reduction normal ivltests +test_nmos normal ivltests +test_notif0 normal ivltests +test_notif1 normal ivltests +test_pmos normal ivltests +test_rnmos normal ivltests +test_rpmos normal ivltests +test_width normal ivltests gold=test_width.gold +time1 normal ivltests +time2 normal ivltests # Tests posedge vector uses vector[0] +time3 normal ivltests +time4 normal ivltests +time5 normal ivltests +time7 normal ivltests # gold=time7.gold +time8 normal ivltests +timeform1 normal ivltests gold=timeform1.gold +timeform2 normal ivltests gold=timeform2.gold +timescale1 normal ivltests +timescale2 normal ivltests +timescale3 CE ivltests +tran normal ivltests gold=tran.gold +tranif0 normal ivltests gold=tranif0.gold +tranif1 normal ivltests gold=tranif1.gold +tran-keeper normal ivltests +tri0 normal ivltests +tri0b normal ivltests +tri1 normal ivltests +tri2 normal ivltests +tri3 normal ivltests +triand normal ivltests +trior normal ivltests +types1 normal ivltests +udp_bufg normal ivltests +udp_bufg2 normal ivltests +udp_bx normal ivltests gold=udp_bx.gold +udp_delay_fail CE ivltests +udp_dff normal ivltests +udp_dff_std normal ivltests +udp_eval_arg normal ivltests +udp_jkff normal ivltests +udp_real_delay normal ivltests +udp_sched normal ivltests +udp_x normal ivltests +unary_and normal ivltests # Unary And &(vect) +unary_lnot1 normal ivltests +unary_lnot2 normal ivltests +unary_lnot3 normal ivltests +unary_minus normal ivltests # Unary minus -(vect) +unary_minus1 normal ivltests # From 272 directly. +unary_minus2 normal ivltests +unary_minus3 normal ivltests +unary_minus4 normal ivltests +unary_nand normal ivltests # Unary nand ~&(vect) +unary_nand2 normal ivltests # Unary nand ~&(vect) +unary_nor normal ivltests # Unary nor ~|(vect) +unary_nor2 normal ivltests # Unary nor ~|(vect) +unary_not normal ivltests # Unary not ~ +unary_or normal ivltests # Unary or |(vect) +unary_xnor1 normal ivltests # Unary xnor ~^(vect) +unary_xnor2 normal ivltests # Unary xnor ^~(vect) +unary_xor normal ivltests # Unary or ^(vect) +uncon_drive normal ivltests +undef normal ivltests gold=undef.gold +undef_lval_select normal ivltests +undef_lval_select2 normal ivltests +undef_lval_select3a normal ivltests +undef_lval_select3b CE ivltests +undef_lval_select3c CE ivltests +undef_lval_select4a normal ivltests +undef_lval_select4b CE ivltests +undef_lval_select4c CE ivltests +undef_lval_select5 normal ivltests +undefined_shift normal ivltests +urand_r normal ivltests gold=urand_r.gold +urand_r2 normal ivltests gold=urand_r.gold +urand_r3 normal ivltests gold=urand_r.gold +uwire normal ivltests +uwire2 normal ivltests +uwire_fail CE ivltests gold=uwire_fail.gold +vardly normal ivltests +varlsfht normal ivltests # variable << in wire +varlsfht1 normal ivltests # variable << in always +varlsfht2 normal ivltests # variable << in function +varrshft normal ivltests # variable >> in wire +varrshft1 normal ivltests # variable >> in always +varrshft2 normal ivltests # variable >> in function +vcd-dup normal ivltests diff=work/vcd-dup.vcd:gold/vcd-dup.vcd.gold:2 +vector normal ivltests gold=vector.gold +verify_two_var_delays normal ivltests +vvp_scalar_value normal ivltests +wait1 normal ivltests +wait2 normal ivltests +wait3 normal ivltests gold=wait3.gold +warn_opt_sys_tf RE ivltests gold=warn_opt_sys_tf.gold +wildsense normal ivltests # Wildcard sensitivity list. +wildsense2 normal ivltests # Wildcard sensitivity list. +wireadd1 normal ivltests +wireeq normal ivltests +wirege normal ivltests +wireland normal ivltests # assign a && (b ? 0 : 1) (pmonta) +wirele normal ivltests +wiremod1 normal ivltests +wiresl normal ivltests +wiresl2 normal ivltests gold=wiresl2.gold +wiresr normal ivltests +wiresub1 normal ivltests +wirexor1 normal ivltests +writemem-error normal ivltests gold=writemem-error.gold +writemem-invalid RE ivltests gold=writemem-invalid.gold +writememb1 normal ivltests # pr#400 +writememb2 normal ivltests # pr#400 +writememh1 normal ivltests # pr#334 +writememh2 normal ivltests # pr#400 +xnor_test normal ivltests # ~^ in an IF() +z1 normal ivltests foo +z2 normal ivltests foo +zero_repl normal ivltests +zero_repl_fail CE ivltests +cmpi normal ivltests diff --git a/ivtest/regress-vlog95.list b/ivtest/regress-vlog95.list new file mode 100644 index 000000000..a6e23db82 --- /dev/null +++ b/ivtest/regress-vlog95.list @@ -0,0 +1,964 @@ +# This test list is used to override other test lists when using +# the Icarus Verilog vlog95 target. + +# +# Copyright (c) 1999-2021 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# Format of the file +# +# testname testtype directory +# +# The is the verilog file name minus an extension. +# +# The can be one of the following: +# +# normal: Normal results expected, i.e it should compile and execute +# producing at least a single line with PASSED. +# +# CO: Compile Only - Compile the file to the default output type. +# +# CN: Compile Null - Compile with the null target. Similar to CO. +# +# CE: Compile with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# RE: Runtime with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# EF: Expected Fail - We EXPECT this test to fail - only use +# with older versions of Icarus. +# +# TE: Translation Error - We EXPECT the translated code to fail - +# only supported in the vlog95 checker. +# +# NI: Not implemented. Only use for version specific tests. +# +# is where the .v file is located. +# +# An optional fourth and fifth argument can be supplied. +# +# The fourth argument may be one of the following. +# +# modulename - Defines the top level module +# gold=filename - Compare a gold file against the +# generated log file. +# unordered=filename - Compare a gold file against the +# generated log file, allowing for lines +# to appear in any order +# diff=filename1:filename2:skip_ln - Compare the two files for equality. +# Skip the first lines or none. +# +# If a is given you can supply a fifth argument for the +# gold or diff commands. +# + +# Verilog 95 does not support automatic tasks or functions. +always_comb_rfunc CE ivltests +automatic_error11 CE ivltests +automatic_error12 CE ivltests +automatic_error13 CE ivltests +automatic_events CE ivltests +automatic_events2 CE ivltests +automatic_events3 CE ivltests +automatic_task CE ivltests +automatic_task2 CE ivltests +automatic_task3 CE ivltests +br942 CE ivltests +br_gh531 CE ivltests +def_nettype CE ivltests +func_init_var1 CE,-pallowsigned=1 ivltests +func_init_var2 CE,-pallowsigned=1 ivltests +func_init_var3 CE,-pallowsigned=1 ivltests +nested_func CE ivltests +pr2169870 CE ivltests +pr2172606b CE ivltests +pr2276163 CE ivltests +pr2929913 CE ivltests +real_events CE ivltests +recursive_func CE ivltests +recursive_task CE ivltests +task_init_var1 CE,-pallowsigned=1 ivltests +task_init_var2 CE,-pallowsigned=1 ivltests +task_init_var3 CE,-pallowsigned=1 ivltests +test_work14 CE ivltests +vhdl_elab_range CE ivltests +vhdl_notfunc_stdlogic CE ivltests +vhdl_procedure CE ivltests +vhdl_range_func CE ivltests +vhdl_report CE ivltests +vhdl_subprogram CE ivltests +vhdl_unbounded_func CE ivltests + +# Verilog 95 does not support real nets. +array_lval_select4a CE ivltests # Also net arrays +array_lval_select4b CE ivltests # Also net arrays +array_lval_select5 CE ivltests # Also net arrays +array_lval_select6 CE ivltests # Also net arrays +br_gh456 CE,-g2009,-pallowsigned=1 ivltests +ca_64delay CE ivltests # Also net arrays +ca_time_real CE ivltests +ca_var_delay CE ivltests +cast_real CE,-pallowsigned=1 ivltests +cast_real_signed CE,-pallowsigned=1 ivltests +cast_real_unsigned CE ivltests +sv_cast_integer normal,-g2005-sv,-pallowsigned=1 ivltests +sv_cast_integer2 normal,-g2005-sv,-pallowsigned=1 ivltests +sv_cast_string CE ivltests +clog2 CE ivltests # Also big int +delayed_sfunc CE ivltests +implicit_cast4 CE,-g2009,-pallowsigned=1 ivltests +implicit_cast5 CE,-g2009,-pallowsigned=1 ivltests +implicit_cast6 CE,-g2009,-pallowsigned=1 ivltests +implicit_cast12 CE,-g2009,-pallowsigned=1 ivltests +implicit_cast13 CE,-g2009,-pallowsigned=1 ivltests +pr1861212c CE ivltests +pr1864110a CE ivltests +pr1864110b CE ivltests +pr1864110c CE ivltests +pr1864115 CE ivltests +pr1873372 CE ivltests +pr1880003 CE ivltests +pr1898293 CE ivltests +pr2123158 CE ivltests +pr2123190 CE ivltests +pr2453002b CE ivltests +pr2456943 CE ivltests +pr2806474 CE ivltests +pr2976242 CE ivltests +pr2976242b CE ivltests +real8 CE ivltests +real_mod_in_ca CE ivltests +real_pulse_clean CE ivltests +real_pwr_in_ca CE ivltests # Also power operator +real_wire_array CE ivltests +real_wire_force_rel CE ivltests +tern8 CE ivltests +v2005_math CE ivltests +vams_abs2 CE,-gverilog-ams,-pallowsigned=1 ivltests +vhdl_real CE,-g2009,ivltests/vhdl_real.vhd ivltests +vhdl_unbounded CE,-g2009,ivltests/vhdl_unbounded.vhd ivltests +wreal CE ivltests + +# Real modulus is an Icarus extension. +pr1528093 CE ivltests + +# IEEE 1364-1995 does not support the general power operator. +br_gh9 CE ivltests +br_gh244a CE ivltests +br_gh244b CE ivltests +ca_pow_signed CE,-pallowsigned=1 ivltests +br_mw20171108 CE,-pallowsigned=1 ivltests +ca_pow_synth CE ivltests +ca_pow_unsigned CE ivltests +constfunc3 CE ivltests +pow_ca_signed CE ivltests +pow_ca_unsigned CE ivltests +pow_reg_signed CE ivltests +pow_reg_unsigned CE ivltests +pow_signed CE ivltests +pow_unsigned CE ivltests +pow-ca CE,-pallowsigned=1 ivltests +pow-proc CE,-pallowsigned=1 ivltests +pr2352834 CE,-pallowsigned=1 ivltests +pr2823711 CE ivltests +pr2909386b CE,-pallowsigned=1 ivltests +rl_pow CE ivltests +vhdl_pow_rem CE,-g2005-sv,-pallowsigned=1,ivltests/vhdl_pow_rem.vhd ivltests + +# IEEE 1364-1995 does not support these SV functions +sf_countbits RE,-g2012 ivltests +sf_countbits_fail RE,-g2012 ivltests +sf_countones RE,-g2009 ivltests +sf_countones_fail RE,-g2009 ivltests +sf_isunknown RE,-g2005-sv ivltests +sf_isunknown_fail RE,-g2005-sv ivltests +sf_onehot RE,-g2005-sv ivltests +sf_onehot_fail RE,-g2005-sv ivltests +sf_onehot0 RE,-g2005-sv ivltests +sf_onehot0_fail RE,-g2005-sv ivltests + +# IEEE 1364-1995 only supports register arrays. +array_lval_select1 normal,-DVLOG95 ivltests +array_lval_select2 normal,-DVLOG95 ivltests +array_lval_select3a TE,-DVLOG95 ivltests +array_lval_select3b CE,-DVLOG95 ivltests +array_lval_select3c normal,-DVLOG95 ivltests +array_select CE,-pallowsigned=1 ivltests +array_select_a CE ivltests +array_unpacked_sysfunct CE,-g2005-sv ivltests +array_word_width2 CE ivltests +br1008 CE ivltests +br1019 CE ivltests +br_gh556 CE,-g2009 ivltests +br_ml20171017 CE ivltests +genvar_scopes CE ivltests +meminit2 CE ivltests +memsynth4 CE,-S ivltests # Synthesized net array +negative_genvar CE ivltests +pr1565544 CE ivltests +pr1657307 CE ivltests +pr1695322 CE ivltests +pr1701855b CE ivltests +pr1703346 CE ivltests +pr1740476b CE ivltests +pr1758122 CE,-g2001-noconfig ivltests +pr1799904 CE ivltests +pr1820472 CE ivltests +pr1868792 CE ivltests +pr1876798 CE ivltests +pr1903324 CE ivltests +pr2011429 CE ivltests +pr2076391 CE,-pallowsigned=1 ivltests +pr2201909 CE ivltests +pr2201909b CE ivltests +pr2166311 CE ivltests +pr2715748 CE ivltests # Also real net +pr2815398b CE ivltests +pr3054101g CE ivltests +pr3054101h CE ivltests +pr3592746 CE ivltests +real_array CE ivltests +real_array_nb CE,-pallowsigned=1 ivltests +scan-invalid CE ivltests +sel_rval_bit_ob CE ivltests +sel_rval_part_ob CE ivltests +signed_net_display CE,-pallowsigned=1 ivltests +sv_unpacked_port CE,-g2009 ivltests +sv_unpacked_port2 CE,-g2009,-pallowsigned=1 ivltests +sv_unpacked_wire CE,-g2009 ivltests +sv_unpacked_wire2 CE,-g2009,-pallowsigned=1 ivltests + +# A zero replication in a CA is not supported. +concat4 EF ivltests + +# SystemVerilog final blocks are not supported. +br_gh443 CE,-g2009 ivltests +final CE,-g2009 ivltests +final2 CE,-g2009 ivltests +program_hello CE,-g2009 ivltests +program2 CE,-g2009,-pallowsigned=1 ivltests +program2b CE,-g2009,-pallowsigned=1 ivltests +program3 CE,-g2009 ivltests +program3a CE,-g2009 ivltests +program4 CE,-g2009 ivltests + +# No support for the SystemVerilog string data type. +array_string CE,-g2009,-pallowsigned=1 ivltests +br932a CE,-g2009 ivltests +br932b CE,-g2009 ivltests +br_gh4 CE,-g2009 ivltests +br_gh175 CE,-g2009,-pallowsigned=1 ivltests +br_gh194 CE,-g2009 ivltests +br_gh365 CE,-g2009 ivltests +br_gh453 CE,-g2009,-pallowsigned=1 ivltests +br_ml20180309a CE,-g2009 ivltests +br_ml20180309b CE,-g2009 ivltests +ivlh_textio CE,-g2005-sv ivltests +plus_arg_string CE,-g2009 ivltests +sformatf CE,-g2009 ivltests +string_events CE,-g2009 ivltests +string_index CE,-g2005-sv ivltests +sv_macro CE,-g2009,-pallowsigned=1 ivltests +sv_string1 CE,-g2009 ivltests +sv_string2 CE,-g2009 ivltests +sv_string3 CE,-g2009 ivltests +sv_string4 CE,-g2009 ivltests +sv_string5 CE,-g2009 ivltests +vhdl_string_lim CE,-g2005-sv,-pallowsigned=1,ivltests/vhdl_string_lim.vhd ivltests +vhdl_textio_write CE,-g2005-sv,-pallowsigned=1,ivltests/vhdl_textio_write.vhd ivltests +vhdl_textio_read CE,-g2005-sv,-pallowsigned=1,ivltests/vhdl_textio_read.vhd ivltests + +# SystemVerilog dynamic arrays and new operator. +always_comb_warn CE,-g2009,-pallowsigned=1 ivltests +always_ff_warn CE,-g2009,-pallowsigned=1 ivltests +always_latch_warn CE,-g2009,-pallowsigned=1 ivltests +br962 CE,-g2009 ivltests +br963 CE,-g2009 ivltests +br_gh164a CE,-g2009,-pallowsigned=1 ivltests +br_gh164b CE,-g2009,-pallowsigned=1 ivltests +br_gh164c CE,-g2009,-pallowsigned=1 ivltests +br_gh164d CE,-g2009,-pallowsigned=1 ivltests +br_gh164e CE,-g2009,-pallowsigned=1 ivltests +br_gh383a CE,-g2012, ivltests +br_gh383b CE,-g2012, ivltests +br_gh383c CE,-g2012,-pallowsigned=1 ivltests +br_gh383d CE,-g2012,-pallowsigned=1 ivltests +br_gh460 CE,-g2012 ivltests +br_ml20191221 CE,-g2009,-pallowsigned=1 ivltests +sv_array_assign_pattern2 CE,-g2009,-pallowsigned=1 ivltests +sv_cast_darray CE,-g2005-sv,-pallowsigned=1 ivltests +sv_darray1 CE,-g2009,-pallowsigned=1 ivltests +sv_darray2 CE,-g2009,-pallowsigned=1 ivltests +sv_darray3 CE,-g2009,-pallowsigned=1 ivltests +sv_darray4 CE,-g2009,-pallowsigned=1 ivltests +sv_darray5 CE,-g2009,-pallowsigned=1 ivltests +sv_darray5b CE,-g2009,-pallowsigned=1 ivltests +sv_darray6 CE,-g2009,-pallowsigned=1 ivltests # Also string +sv_darray_args1 CE,-g2009,-pallowsigned=1 ivltests +sv_darray_args2 CE,-g2009,-pallowsigned=1 ivltests +sv_darray_args2b CE,-g2009,-pallowsigned=1 ivltests +sv_darray_args3 CE,-g2009,-pallowsigned=1 ivltests +sv_darray_args4 CE,-g2009,-pallowsigned=1 ivltests # Also string +sv_darray_decl_assign CE,-g2009,-pallowsigned=1 ivltests +sv_darray_function CE,-g2009,-pallowsigned=1 ivltests +sv_darray_signed CE,-g2009,-pallowsigned=1 ivltests # Also string +sv_darray_word_size CE,-g2009 ivltests +sv_new_array_error CE,-g2009, ivltests +unp_array_typedef CE,-g2009,-pallowsigned=1 ivltests # Also string + +# SystemVerilog classes, new and null operators. +br959 CE,-g2009 ivltests +br1003a CE,-g2009 ivltests +br1004 CE,-g2009 ivltests +br_gh104a CE,-g2009 ivltests +br_gh167a CE,-g2009 ivltests +br_gh167b CE,-g2009 ivltests +br_gh177a CE,-g2009 ivltests +br_gh177b CE,-g2009 ivltests +br_gh388 CE,-g2009 ivltests +br_gh390b CE,-g2009 ivltests +br_gh391 CE,-g2009 ivltests +br_gh437 CE,-g2009 ivltests +br_gh445 CE,-g2009 ivltests +br_gh461 CE,-g2009 ivltests +sv_class1 CE,-g2009 ivltests +sv_class2 CE,-g2009 ivltests +sv_class3 CE,-g2009 ivltests +sv_class4 CE,-g2009 ivltests +sv_class5 CE,-g2009 ivltests +sv_class6 CE,-g2009 ivltests +sv_class7 CE,-g2009 ivltests +sv_class8 CE,-g2009 ivltests +sv_class9 CE,-g2009 ivltests # Also dynamic array +sv_class10 CE,-g2009 ivltests +sv_class11 CE,-g2009 ivltests +sv_class12 CE,-g2009 ivltests +sv_class13 CE,-g2009 ivltests +sv_class14 CE,-g2009 ivltests +sv_class15 CE,-g2009 ivltests +sv_class16 CE,-g2009 ivltests +sv_class17 CE,-g2009 ivltests +sv_class18 CE,-g2009 ivltests +sv_class19 CE,-g2009 ivltests +sv_class20 CE,-g2009 ivltests +sv_class21 CE,-g2009 ivltests +sv_class22 CE,-g2009 ivltests +sv_class23 CE,-g2009 ivltests +sv_class24 CE,-g2009 ivltests +sv_end_label CE,-g2009 ivltests # Also generate +sv_foreach2 CE,-g2009,-pallowsigned=1 ivltests +sv_foreach3 CE,-g2009 ivltests +sv_foreach4 CE,-g2009 ivltests +sv_pkg_class CE,-g2009 ivltests +sv_port_default1 CE,-g2009 ivltests +sv_port_default2 CE,-g2009,-pallowsigned=1 ivltests +sv_port_default3 CE,-g2009 ivltests +sv_port_default4 CE,-g2009,-pallowsigned=1 ivltests +sv_port_default5 CE,-g2009 ivltests +sv_port_default6 CE,-g2009,-pallowsigned=1 ivltests +sv_port_default7 CE,-g2009,-pallowsigned=1 ivltests +sv_port_default8 CE,-g2009,-pallowsigned=1 ivltests +sv_port_default9 CE,-g2009 ivltests +sv_root_class CE,-g2009 ivltests +sv_unit2b CE,-g2009 ivltests +sv_unit3b CE,-g2009 ivltests +sv_unit4b CE,-g2009 ivltests + +# These variable assignments are converted to wire definitions that are +# assigned from both a continuous assignment and a procedural assignment. +# This is not supported in 1364-1995 so the translated code will fail. +sv_uwire1 TE,-g2009 ivltests +sv_uwire2 TE,-g2009 ivltests +vvp_recv_vec4_pv TE,-g2009,-pallowsigned=1 ivltests + +# SystemVerilog requires that variable initialization that is part of a +# declaration is performed before the start of simulation. When standard +# Verilog is selected, Icarus ensures that combinatorial always blocks +# are started before initial blocks, so these tests will fail. +sv_var_init1 EF,-g2009 ivltests +# This test should fail the same way, but there is an unresolved bug in +# translation. +sv_var_init2 TE,-g2009 ivltests + +# No support for these SystemVerilog features +always4A CE,-g2009 ivltests # join_any +always4B CE,-g2009 ivltests # join_none +br936 CE,-g2009,-pallowsigned=1 ivltests # join_any +br_gh165 CE,-g2009 ivltests # join_* +br_gh368 CE,-g2009 ivltests # join_* +br_gh412 CE,-g2009 ivltests # queues +br_gh414 CE,-g2009,-pallowsigned=1 ivltests # strings +br_gh436 CE,-g2012,-pallowsigned=1 ivltests # queues/strings +br_mw20200501 CE,-g2009 ivltests # queues +disable_fork_cmd CE,-g2009 ivltests # disable fork and join_* +enum_next CE,-g2009,-pallowsigned=1 ivltests # enum +enum_test1 CE,-g2009 ivltests # enum +fork_join_any CE,-g2009,-pallowsigned=1 ivltests # join_any +fork_join_dis CE,-g2009,-pallowsigned=1 ivltests # join_any +fork_join_none CE,-g2009,-pallowsigned=1 ivltests # join_none +logical_short_circuit CE,-g2012 ivltests # ++ +plus_5 CE,-g2009,-pallowsigned=1 ivltests # ++/-- +pr3366217f CE,-g2009,-pallowsigned=1 ivltests # enum +pr3366217h CE,-g2009,-pallowsigned=1 ivltests # enum +pr3366217i CE,-g2009 ivltests # enum +pr3390385 CE,-g2009 ivltests # ++ +pr3390385b CE,-g2009 ivltests # ++ +pr3390385c CE,-g2009 ivltests # ++ +pr3390385d CE,-g2009 ivltests # ++ +pr3462145 CE,-g2009 ivltests # ++ +wait_fork CE,-g2009 ivltests # wait fork and join_* +wild_cmp_err CE,-g2009 ivltests # ==?/!=? +wild_cmp_err2 CE,-g2009 ivltests # ==?/!=? +wild_cmp_net CE,-g2009 ivltests # ==?/!=? +wild_cmp_var CE,-g2009 ivltests # ==?/!=? + +# No support for the SystemVerilog two state types (initial value problems). +br_gh337 EF,-g2009,-pallowsigned=1 ivltests +ibit_test EF,-g2009 ivltests +ibyte_test EF,-g2009 ivltests +iint_test EF,-g2009 ivltests +ilongint_test EF,-g2009 ivltests +ishortint_test EF,-g2009 ivltests +sbyte_test EF,-g2009,-pallowsigned=1 ivltests +sint_test EF,-g2009,-pallowsigned=1 ivltests +slongint_test EF,-g2009,-pallowsigned=1 ivltests +sshortint_test EF,-g2009,-pallowsigned=1 ivltests +ubyte_test EF,-g2009,-pallowsigned=1 ivltests +uint_test EF,-g2009,-pallowsigned=1 ivltests +ulongint_test EF,-g2009,-pallowsigned=1 ivltests +ushortint_test EF,-g2009,-pallowsigned=1 ivltests +# These have four state to two state cast problems +br_gh99e EF,-g2009 ivltests +implicit_cast1 EF,-g2009,-pallowsigned=1 ivltests +implicit_cast2 EF,-g2009,-pallowsigned=1 ivltests +implicit_cast3 EF,-g2009,-pallowsigned=1 ivltests +implicit_cast8 EF,-g2009,-pallowsigned=1 ivltests +implicit_cast10 EF,-g2009,-pallowsigned=1 ivltests +implicit_cast11 EF,-g2009,-pallowsigned=1 ivltests + +# These tests have unresolved failures that still need to be looked at. +# The following two have problem getting the correct net/expression +# information from the nexus. pr1723367 is the real torture test. +partselsynth TE,-S ivltests +pr1723367 TE,-gno-io-range-error ivltests gold=pr1723367.gold +# There is a separate driver for each bit of byte_value. +generate_multi_loop NI ivltests # Assert +# There are multiple drivers on the nexus. A local pulldown and the actual +# input driver. +pr3194155 NI ivltests # Asserts +# This is caused because the two port are cross coupled. This creates a +# recursive call that never ends and blows over the stack limit. +pr3452808 NI ivltests # Seg. faults +# Translating selects of a non-zero based vector/array cast the base select +# expression to $signed(). The normalization is already removed, but the code +# cannot currently determine if the $signed() is from the normalization or +# from the original code. +bitsel5 CE ivltests +# Translating selects with the LSB > MSB are also normalized and the code +# cannot determine if the $signed() should be removed or not. +pr751 CE,-Wsensitivity-entire-vector ivltests # gold=pr751.gold +# This has a port connect issue and a failure because the actual port is cast +# from 4-state to 2-state and the port information is removed on the 4-state +# side (the actual port). I'm not sure why the enum is not a bit or other +# 2-state variable, but when that is done there is a compile error. +vhdl_var_init CE,-g2009,vhdl_var_init.vhd ivltests +# This refers to a signal in a parent scope that is driven by a constant, +# which hits the unhandled out_of_scope_drive clause in emit_nexus_as_ca. +vhdl_range_func TE,-g2005-sv,-pallowsigned=1,ivltests/vhdl_range_func_pkg.vhd,ivltests/vhdl_range_func.vhd, ivltests +# This casts a signed value to a larger size (requiring sign extension, then uses +# the cast value in an unsigned expression with an even larger width (requiring +# zero padding. I can't think how to do this in standard Verilog without using +# an intermediate variable. +size_cast4 EF,-g2009,-pallowsigned=1 ivltests +# Similarly, this needs an intermediate variable assignment to produce the +# correct result. +br_gh219 EF,-g2009,-pallowsigned=1 ivltests +# This has a gate output connected to a VP part select. The translator +# creates a CA for the part select, but has nothing to connect it to. +# It leaves the gate output unconnected. +rise_fall_decay2 CE ivltests +# The code generator is generating unnecessary calls to $unsigned. +array_packed_2d normal,-g2009,-pallowsigned=1 ivltests gold=array_packed_2d.gold +br_gh112c normal,-g2009,-pallowsigned=1 ivltests +br_gh112d normal,-g2009,-pallowsigned=1 ivltests +# This generates a very larg (65536 bit) constant, and the parser can't cope. +br_gh162 TE ivltests + +# New tests that need to be looked at go here. +vhdl_concat_func EF,-g2005-sv,-pallowsigned=1,ivltests/vhdl_concat_func.vhd ivltests +vhdl_resize EF,-g2005-sv,-pallowsigned=1,ivltests/vhdl_resize.vhd ivltests + +# Size (spacing) difference since -4 is used for the second value. +# Should this be $signed() if it is not an integer? +pr2159630 EF,-pallowsigned=1 ivltests gold=pr2159630.gold + +# No support for most Verilog-A constructs +analog1 CE,-gverilog-ams ivltests +analog2 CE,-gverilog-ams ivltests + +# These tests have generate scopes that are not currently supported. +br955 CE ivltests +br988 CE ivltests +br_gh345 CE ivltests +br_gh567 CE,-g2001,-pallowsigned=1 ivltests +br_gh568 CE,-g2009,-pallowsigned=1 ivltests +complex_lidx CE ivltests +defparam3 CE ivltests +defparam4 CE ivltests +gen_case_opt1 CE ivltests +gen_case_opt2 CE ivltests +gen_case_opt3 CE ivltests +genloop CE ivltests +generate_case CE ivltests +generate_case2 CE ivltests +generate_case3 CE ivltests +genvar_inc_dec CE,-g2009 ivltests # also integer arrays +packeda2 CE,-g2009,-pallowsigned=1 ivltests +pr1565699b CE ivltests +pr1623097 CE ivltests +pr1676071 CE ivltests +pr1691599b CE ivltests +pr1695309 CE ivltests +pr1704726b CE ivltests +pr1755629 CE ivltests +pr1828642 CE ivltests +pr1956211 CE ivltests +pr1960625 CE ivltests +pr1988302 CE ivltests +pr1988310 CE ivltests +pr2018235a CE ivltests +pr2091455 CE ivltests +pr2109179 CE ivltests +pr2138682 CE ivltests +pr2257003 CE ivltests +pr2257003b CE ivltests +pr2306259 CE ivltests +pr2350934 CE ivltests +pr2350934b CE ivltests +pr2350988 CE ivltests +pr2355304 CE ivltests +pr2728812a CE ivltests +pr2815398a CE ivltests +pr2815398a_std CE ivltests +pr2909414 CE ivltests +pr2924354 CE ivltests +pr3011327 CE ivltests +pr3409749 CE ivltests +pr3437290b CE ivltests +pr3527694 CE ivltests +pr3534422 CE ivltests +pr3557493 CE ivltests +scoped_events CE ivltests +sv_packed_port1 CE,-g2009 ivltests +sv_packed_port2 CE,-g2009 ivltests +br_gh433 CE,-g2009,-pallowsigned=1 ivltests +sv_queue1 CE,-g2009,-pallowsigned=1 ivltests +sv_queue2 CE,-g2009,-pallowsigned=1 ivltests +sv_queue3 CE,-g2009 ivltests +sv_queue_real CE,-g2009 ivltests +sv_queue_real_bounded CE,-g2009 ivltests +sv_queue_real_fail CE,-g2009 ivltests +sv_queue_string CE,-g2009 ivltests +sv_queue_string_bounded CE,-g2009 ivltests +sv_queue_string_fail CE,-g2009 ivltests +sv_queue_vec CE,-g2009,-pallowsigned=1 ivltests +sv_queue_vec_bounded CE,-g2009,-pallowsigned=1 ivltests +sv_queue_vec_fail CE,-g2009,-pallowsigned=1 ivltests +test_forgen CE,-g2009,ivltests/forgen.vhd ivltests +test_gxor CE,-g2009,-pallowsigned=1,ivltests/gxor.vhd ivltests +test_varray1 CE,-g2009,-pallowsigned=1,ivltests/varray1.vhd ivltests +unnamed_generate_block CE ivltests + +# Currently part selects in a CA with a non-zero base are not supported. +always_ff_warn_sens CE,-g2009 ivltests +bitsel6 CE ivltests +bitsel7 CE ivltests +pr3054101a CE ivltests +pr3054101b CE ivltests + +# Currently variable indexed part selects in a CA with a non-zero base are not supported. +pr2835632b CE ivltests # Also scale expr. problems +pr3054101c CE ivltests +pr3054101d CE,-pallowsigned=1 ivltests +pr3054101e CE ivltests # Also scale expr. problems +pr3054101f CE ivltests # Also scale expr. problems +signed_part CE,-pallowsigned=1 ivltests + +# Currently no support for tran_VP (inout ports and tranif gates). +bitsel10 CE ivltests # Also uses a logic bufif0 +br918c CE ivltests # Also uses a logic pullup +br965 CE ivltests +br_gh127b CE ivltests +br_gh127c CE ivltests +br_gh127e CE ivltests +br_gh127f CE ivltests +br_gh315 CE,-gspecify ivltests +br_gh316c CE,-gspecify ivltests +br_gh356a CE,-gspecify ivltests +br_gh356b CE,-gspecify ivltests +countdrivers3 CE ivltests # also uses a logic bufif1 +inout TE ivltests # Duplicate names +inout2 CE ivltests +inout3 CE ivltests +inout4 CE ivltests +pr1444055 CE ivltests +pr1478121 CE ivltests +pr2219441 CE ivltests +pr3296466a CE ivltests +pr3296466b CE ivltests # Also some nexus problems. +pr3296466d CE ivltests +rise_fall_delay3 CE ivltests # Uses tranif1 gates +tri2 CE ivltests + +# The Icarus compiler does not support arrayed UDP instance. These are +# created in the synthesis process. +basicexpr TE,-S ivltests +basicstate TE,-S ivltests +basicstate2 TE,-S ivltests +br993a TE,-S ivltests +br993b TE,-S ivltests +br994 TE,-S ivltests +br_gh99v TE,-S ivltests +br_gh99w TE,-S ivltests +br_gh99x TE,-S ivltests +casesynth1 TE,-S ivltests +casesynth2 TE,-S ivltests +casesynth3 TE,-S ivltests +casesynth7 TE,-S ivltests +conditsynth1 TE,-S ivltests +conditsynth2 TE,-S ivltests +conditsynth3 TE,-S ivltests +dffsynth6 TE,-S ivltests +dffsynth9 TE,-S ivltests +dffsynth10 TE,-S ivltests +inside_synth2 TE,-S ivltests +multireg TE,-S ivltests +shiftl TE,-S ivltests +ufuncsynth1 TE,-S ivltests +pr685 TE,-S ivltests + +# The translator doesn't currently support multi-bit asynchronous set values. +# These are created in the synthesis process. +dffsynth7 CE,-S ivltests +dffsynth11 CE,-S ivltests +sqrt32synth CE,-S ivltests + +# The converter generates a complex expression for $strobe and Icarus does not +# currently support this. The translation is correct. +pr1830834 EF ivltests + +# This test relies on variable initialisation occurring before any other +# process runs. Check that it at least compiles cleanly. +vhdl_loop CO,-g2005-sv,-pallowsigned=1,ivltests/vhdl_loop.vhd ivltests + +# These tests have different output because of file name/line, etc. differences. +br916a normal ivltests gold=br916a-vlog95.gold +br916b normal ivltests gold=br916b-vlog95.gold +br1003b normal,-g2009 ivltests gold=br1003b-vlog95.gold +br1003c normal,-g2009 ivltests gold=br1003c-vlog95.gold +br1003d normal,-g2009 ivltests gold=br1003d-vlog95.gold +br1007 normal,-Wselect-range ivltests gold=br1007-vlog95.gold +br_gh230 RE ivltests gold=br_gh230-vlog95.gold +eofmt_percent normal ivltests gold=eofmt_percent-vlog95.gold +fatal_et_al normal ivltests gold=fatal_et_al-vlog95.gold +fdisplay3 RE ivltests gold=fdisplay3-vlog95.gold +fdisplay_fail_fd normal ivltests gold=fdisplay_fail_fd-vlog95.gold +fdisplay_fail_mcd normal ivltests gold=fdisplay_fail_mcd-vlog95.gold +format RE ivltests gold=format-vlog95.gold +fread-error RE ivltests gold=fread-error-vlog95.gold +fscanf_u_warn normal ivltests gold=fscanf_u_warn-vlog95.gold +fscanf_z_warn normal ivltests gold=fscanf_z_warn-vlog95.gold +localparam_type normal ivltests gold=parameter_type-vlog95.gold +parameter_type normal ivltests gold=parameter_type-vlog95.gold +mem1 normal ivltests gold=mem1-vlog95.gold +pic normal contrib gold=pic-vlog95.gold +pr910 normal ivltests gold=pr910-vlog95.gold +pr1698820 normal ivltests gold=pr1698820-vlog95.gold +pr1819452 normal ivltests gold=pr1819452-vlog95.gold +pr2509349a normal ivltests gold=pr2509349a-vlog95.gold +pr2509349b normal ivltests gold=pr2509349b-vlog95.gold +pr2800985b RE ivltests gold=pr2800985b-vlog95.gold +queue_fail RE ivltests gold=queue_fail-vlog95.gold +readmem-invalid RE ivltests gold=readmem-invalid-vlog95.gold +# Because the lower module has a parameter it is given a unique name that +# does not match what the code is looking for. If we can verify that there +# is only a single instance or that the instance has the original or at +# least all the instances have the same value we may be able to use the +# original name. +simparam EF ivltests +sv_immediate_assert normal,-g2009 ivltests gold=sv_immediate_assert-vlog95.gold +sv_immediate_assume normal,-g2009 ivltests gold=sv_immediate_assume-vlog95.gold +swrite normal ivltests gold=swrite-vlog95.gold +sys_func_task_error RE ivltests gold=sys_func_task_error-vlog95.gold +# In Verilog 95 a system function cannot be called as a task. +sys_func_as_task RE,-g2009 ivltests +warn_opt_sys_tf RE ivltests gold=warn_opt_sys_tf-vlog95.gold +writemem-error normal ivltests gold=writemem-error-vlog95.gold +writemem-invalid RE ivltests gold=writemem-invalid-vlog95.gold + +# For Verilog 95 signed is supported as an option (-pallowsigned=1). +array6 normal,-pallowsigned=1 ivltests +assign_op_type normal,-g2009,-pallowsigned=1 ivltests +bitp1 normal,-g2009,-pallowsigned=1 ivltests +bits normal,-g2009,-pallowsigned=1 ivltests +bits2 normal,-g2009,-pallowsigned=1 ivltests +br884 normal,-g2009,-pallowsigned=1 ivltests +br917a normal,-g2009,-pallowsigned=1 ivltests +br917b normal,-g2009,-pallowsigned=1 ivltests +br917c normal,-g2009,-pallowsigned=1 ivltests +br917d normal,-g2009,-pallowsigned=1 ivltests +br943_944 normal,-g2009,-pallowsigned=1,ivltests/br943_944.vhd ivltests +br985 normal,-g2009,-pallowsigned=1,ivltests/br985.vhd ivltests +br1025 normal,-g2009,-pallowsigned=1 ivltests +br_gh8 normal,-pallowsigned=1 ivltests +br_gh99c normal,-gverilog-ams,-pallowsigned=1 ivltests +br_gh99r normal,-pallowsigned=1 ivltests +br_gh112e normal,-g2009,-pallowsigned=1 ivltests +br_gh112f normal,-g2009,-pallowsigned=1 ivltests +br_gh129 normal,-g2009,-pallowsigned=1 ivltests +br_gh198 normal,-pallowsigned=1 ivltests gold=br_gh198.gold +br_gh199a normal,-pallowsigned=1 ivltests +br_gh199b normal,-pallowsigned=1 ivltests +br_gh231 normal,-g2009,-pallowsigned=1 ivltests +br_gh281 normal,-g2009,-pallowsigned=1 ivltests +br_gh281b normal,-g2009,-pallowsigned=1 ivltests +br_gh283a normal,-pallowsigned=1 ivltests +br_gh283b normal,-pallowsigned=1 ivltests +br_gh283c normal,-pallowsigned=1 ivltests +br_gh289b normal,-g2009,-pallowsigned=1 ivltests +br_gh477 normal,-g2009,-pallowsigned=1 ivltests +br_gh540 normal,-g2009,-pallowsigned=1 ivltests +ca_mult normal,-pallowsigned=1 ivltests gold=ca_mult.gold +cast_int normal,-pallowsigned=1 ivltests +cast_int_ams normal,-gverilog-ams,-pallowsigned=1 ivltests +cfunc_assign_op_vec normal,-g2009,-pallowsigned=1 ivltests +constfunc4 normal,-pallowsigned=1 ivltests +constfunc4_ams normal,-gverilog-ams,-pallowsigned=1 ivltests +constfunc6 normal,-pallowsigned=1 ivltests +constfunc6_ams normal,-pallowsigned=1 ivltests +constfunc7 normal,-pallowsigned=1 ivltests +constfunc13 normal,-pallowsigned=1 ivltests +constfunc14 normal,-pallowsigned=1 ivltests +enum_elem_ranges normal,-g2009,-pallowsigned=1 ivltests +enum_value_expr normal,-g2009,-pallowsigned=1 ivltests +enum_values normal,-g2009,-pallowsigned=1 ivltests +enum_ports normal,-g2005-sv,-pallowsigned=1 ivltests +extend normal,-pallowsigned=1 ivltests +first_last_num normal,-g2009,-pallowsigned=1 ivltests +fr49 normal,-g2009,-pallowsigned=1 ivltests +function12 normal,-g2005-sv,-pallowsigned=1 ivltests gold=function12.gold +implicit_cast7 normal,-g2009,-pallowsigned=1 ivltests +implicit_cast9 normal,-g2009,-pallowsigned=1 ivltests +inc_dec_stmt normal,-g2009,-pallowsigned=1 ivltests +int_param normal,-g2009,-pallowsigned=1 ivltests +iuint1 normal,-g2009,-pallowsigned=1 ivltests +logp2 normal,-g2009,-pallowsigned=1 ivltests +mixed_width_case normal,-pallowsigned=1 ivltests +mod_inst_pkg normal,-g2009,-pallowsigned=1 ivltests +packeda normal,-g2009,-pallowsigned=1 ivltests +pr1033 normal,-pallowsigned=1 ivltests gold=pr1033.gold +pr1380261 normal,-pallowsigned=1 ivltests +pr1494799 normal,-pallowsigned=1 ivltests gold=pr1494799.gold +pr1589497 normal,-pallowsigned=1 ivltests gold=pr1589497.gold +pr1603313 normal,-pallowsigned=1 ivltests +pr1717361 normal,-pallowsigned=1 ivltests +pr1719055 normal,-pallowsigned=1 ivltests gold=pr1719055.gold +pr1793749 normal,-pallowsigned=1 ivltests gold=pr1793749.gold +pr1879226 normal,-pallowsigned=1 ivltests +pr1883052 normal,-pallowsigned=1 ivltests +pr1883052b normal,-pallowsigned=1 ivltests +pr1950282 normal,-pallowsigned=1 ivltests +pr1958801 normal,-pallowsigned=1 ivltests +pr1993479 normal,-pallowsigned=1 ivltests gold=pr1993479.gold +pr2030767 normal,-pallowsigned=1 ivltests +pr2117473 normal,-pallowsigned=1 ivltests +pr2121536 normal,-pallowsigned=1 ivltests +pr2121536b normal,-pallowsigned=1 ivltests +pr2152011 normal,-pallowsigned=1 ivltests gold=pr2152011.gold +pr2233180 normal,-pallowsigned=1 ivltests +pr2233180b normal,-pallowsigned=1 ivltests +pr2233180c normal,-pallowsigned=1 ivltests +pr2233192 normal,-pallowsigned=1 ivltests +pr2233192b normal,-pallowsigned=1 ivltests +pr2233192c normal,-pallowsigned=1 ivltests +pr2425055b normal,-pallowsigned=1 ivltests +pr2425055c normal,-pallowsigned=1 ivltests +pr2722330a normal,-pallowsigned=1 ivltests +pr2722330b normal,-pallowsigned=1 ivltests +pr2909555 normal,-pallowsigned=1 ivltests +pr2913416 normal,-pallowsigned=1 ivltests +pr2913438b normal,-pallowsigned=1 ivltests +pr2922063 normal,-pallowsigned=1 ivltests +pr2922063a normal,-pallowsigned=1 ivltests +pr2922063b normal,-pallowsigned=1 ivltests +pr2986528 normal,-pallowsigned=1 ivltests +pr2998515 normal,-pallowsigned=1 ivltests +pr3104254 normal,-pallowsigned=1 ivltests +pr3284821 normal,-pallowsigned=1 ivltests +pr3292735 normal,-pallowsigned=1 ivltests +pr3366217e normal,-g2009,-pallowsigned=1 ivltests +pr748 normal,-pallowsigned=1 ivltests +pull371 normal,-g2009,-pallowsigned=1 ivltests +pull371b normal,-g2009,-pallowsigned=1 ivltests +sf1289 normal,-g2009,-pallowsigned=1 ivltests +shift2 normal,-pallowsigned=1 ivltests +shift3 normal,-pallowsigned=1 ivltests +shift5 normal,-pallowsigned=1 ivltests gold=shift5.gold +signed1 normal,-pallowsigned=1 ivltests +signed4 normal,-pallowsigned=1 ivltests gold=signed4.gold +signed6 normal,-pallowsigned=1 ivltests +signed7 normal,-pallowsigned=1 ivltests +signed8 normal,-pallowsigned=1 ivltests +signed9 normal,-pallowsigned=1 ivltests +signed12 normal,-pallowsigned=1 ivltests gold=signed12.gold +signed_a normal,-pallowsigned=1 ivltests +signed_pv normal,-pallowsigned=1 ivltests +simple_byte normal,-g2009,-pallowsigned=1 ivltests +simple_int normal,-g2009,-pallowsigned=1 ivltests +simple_longint normal,-g2009,-pallowsigned=1 ivltests +simple_shortint normal,-g2009,-pallowsigned=1 ivltests +size_cast3 normal,-g2009,-pallowsigned=1 ivltests +size_cast5 normal,-g2009,-pallowsigned=1 ivltests +struct_packed_array normal,-g2009,-pallowsigned=1 ivltests +struct_packed_array2 normal,-g2009,-pallowsigned=1 ivltests +sv_for_variable normal,-g2009,-pallowsigned=1 ivltests +sv_foreach1 normal,-g2009,-pallowsigned=1 ivltests +sv_foreach5 normal,-g2009,-pallowsigned=1 ivltests +sv_package normal,-g2009,-pallowsigned=1 ivltests +sv_package2 normal,-g2009,-pallowsigned=1 ivltests +sv_package5 normal,-g2009,-pallowsigned=1 ivltests +sv_port_default10 normal,-g2009,-pallowsigned=1 ivltests +sv_port_default11 normal,-g2009,-pallowsigned=1 ivltests +sv_root_func normal,-g2009,-pallowsigned=1 ivltests gold=sv_root_func.gold +sv_root_task normal,-g2009,-pallowsigned=1 ivltests gold=sv_root_task.gold +test_dispwided normal,-pallowsigned=1 ivltests gold=test_dispwided.gold +test_inc_dec normal,-g2009,-pallowsigned=1 ivltests +test_enumsystem normal,-g2009,-pallowsigned=1,ivltests/enumsystem.vhd ivltests +vhdl_boolean normal,-g2009,-pallowsigned=1,ivltests/vhdl_boolean.vhd ivltests +vhdl_file_open normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_file_open.vhd ivltests +vhdl_prefix_array normal,-g2009,-pallowsigned=1,ivltests/vhdl_prefix_array.vhd ivltests +vhdl_range normal,-g2009,-pallowsigned=1,ivltests/vhdl_range_pkg.vhd,ivltests/vhdl_range.vhd ivltests +vhdl_range_func normal,-g2009,-pallowsigned=1,ivltests/vhdl_range_func_pkg.vhd,ivltests/vhdl_range_func.vhd ivltests +vhdl_rtoi normal,-g2009,-pallowsigned=1,ivltests/vhdl_rtoi.vhd ivltests +vhdl_shift normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_shift.vhd ivltests +vhdl_to_integer normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_to_integer.vhd ivltests +test_system normal,-g2009,-pallowsigned=1,ivltests/system.vhd ivltests +test_tliteral normal,-g2009,-pallowsigned=1 ivltests +vhdl_test8 normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_test8.vhd ivltests +vhdl_test9 normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_test9.vhd ivltests +two_state_display normal,-g2009,-pallowsigned=1 ivltests gold=two_state_display.gold +undefined_shift normal,-pallowsigned=1 ivltests +vams_abs1 normal,-gverilog-ams,-pallowsigned=1 ivltests +vhdl_concurrent_assert normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_concurrent_assert.vhd ivltests gold=vhdl_concurrent_assert.gold +vhdl_const_record normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_const_record.vhd ivltests +vhdl_delay_assign normal,-g2005-sv,-pallowsigned=1,-fivltests/vhdl_timescale_1ns.cfg,ivltests/vhdl_delay_assign.vhd ivltests +vhdl_elab_range normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_elab_range.vhd ivltests +vhdl_image_attr normal,-g2005-sv,-pallowsigned=1,-fivltests/vhdl_timescale_1ns.cfg,ivltests/vhdl_image_attr.vhd ivltests gold=vhdl_image_attr.gold +vhdl_process_scope normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_process_scope.vhd ivltests +vhdl_sadd23_bit normal,-g2009,-pallowsigned=1,ivltests/vhdl_sadd23_bit.vhd ivltests +vhdl_sdiv23_bit normal,-g2009,-pallowsigned=1,ivltests/vhdl_sdiv23_bit.vhd ivltests +vhdl_ssub23_bit normal,-g2009,-pallowsigned=1,ivltests/vhdl_ssub23_bit.vhd ivltests +vhdl_smul23_bit normal,-g2009,-pallowsigned=1,ivltests/vhdl_smul23_bit.vhd ivltests +vhdl_sadd23_stdlogic normal,-g2009,-pallowsigned=1,ivltests/vhdl_sadd23_stdlogic.vhd ivltests +vhdl_sdiv23_stdlogic normal,-g2009,-pallowsigned=1,ivltests/vhdl_sdiv23_stdlogic.vhd ivltests +vhdl_ssub23_stdlogic normal,-g2009,-pallowsigned=1,ivltests/vhdl_ssub23_stdlogic.vhd ivltests +vhdl_smul23_stdlogic normal,-g2009,-pallowsigned=1,ivltests/vhdl_smul23_stdlogic.vhd ivltests +vhdl_test3 normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_test3.vhd ivltests gold=vhdl_test3.gold +vhdl_report normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_report_pkg.vhd,ivltests/vhdl_report.vhd ivltests gold=vhdl_report.gold +vhdl_subprogram normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_subprogram_pkg.vhd,ivltests/vhdl_subprogram.vhd ivltests +vhdl_subtypes normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_subtypes_pkg.vhd,ivltests/vhdl_subtypes.vhd ivltests +vhdl_unary_minus normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_unary_minus.vhd ivltests +vhdl_unbounded_func normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_unbounded_func_pkg.vhd,ivltests/vhdl_unbounded_func.vhd ivltests +vhdl_var_init normal,-g2009,-pallowsigned=1,ivltests/vhdl_var_init.vhd ivltests +vhdl_while normal,-g2005-sv,-pallowsigned=1,ivltests/vhdl_while.vhd ivltests + +# $signed() and $unsigned() in the compiler are always supported and they +# are supported in general if the -pallowsigned=1 flag is provided. +br919 normal,-pallowsigned=1 ivltests +br968 normal,-pallowsigned=1 ivltests +concat3 normal,-pallowsigned=1 ivltests +l_equiv normal,-g2005-sv,-pallowsigned=1 ivltests +l_equiv_ca normal,-g2005-sv,-pallowsigned=1 ivltests +mult2 normal,-pallowsigned=1 ivltests +pr757 normal,-pallowsigned=1 ivltests +pr1002 normal,-pallowsigned=1 ivltests gold=pr1002.gold +pr1002a normal,-pallowsigned=1 ivltests gold=pr1002a.gold +pr1522570 normal,-pallowsigned=1 ivltests +pr1698499 normal,-pallowsigned=1 ivltests gold=pr1698499.gold +pr1793749b normal,-pallowsigned=1 ivltests gold=pr1793749b.gold +pr1795005a normal,-pallowsigned=1 ivltests gold=pr1795005a.gold +pr1795005b normal,-pallowsigned=1 ivltests gold=pr1795005b.gold +pr1823732 normal,-pallowsigned=1 ivltests gold=pr1823732.gold +pr1841300 normal,-pallowsigned=1 ivltests gold=pr1841300.gold +pr1845683 normal,-pallowsigned=1 ivltests gold=pr1845683.gold +pr1960558 normal,-pallowsigned=1 ivltests gold=pr1960558.gold +pr1960619 normal,-pallowsigned=1 ivltests gold=pr1960619.gold +pr1963240 normal,-pallowsigned=1 ivltests gold=pr1963240.gold +pr1990164 normal,-pallowsigned=1 ivltests +pr2136787 normal,-pallowsigned=1 ivltests gold=pr2136787.gold +pr2138979 normal,-pallowsigned=1 ivltests +pr2138979b normal,-pallowsigned=1 ivltests gold=pr2138979b.gold +pr2138979c normal,-pallowsigned=1 ivltests gold=pr2138979c.gold +# This one still has CA $signed() problems. The $signed() is not added when +# the value is not sign extended. +pr2138979d EF,-pallowsigned=1 ivltests gold=pr2138979d.gold +pr2722339a normal,-pallowsigned=1 ivltests +pr2722339b normal,-pallowsigned=1 ivltests +pr2901556 normal,-pallowsigned=1 ivltests +pr2913404 normal,-pallowsigned=1 ivltests +pr3077640 normal,-pallowsigned=1 ivltests +select_padding normal,-pallowsigned=1 ivltests +shift4 normal,-pallowsigned=1 ivltests +signed5 normal,-pallowsigned=1 ivltests +signed10 normal,-pallowsigned=1 ivltests gold=signed10.gold +signed13 normal,-pallowsigned=1 ivltests +# Also tests have different output because of file name/line, etc. differences. +readmem-error normal,-pallowsigned=1 ivltests gold=readmem-error-vlog95.gold + +# Translating a down index part select require -pallowsigned=1 to get the +# index calculation to be 100% correct when the select expression is not +# already signed. +param_select3 normal,-pallowsigned=1 ivltests +select5 normal,-pallowsigned=1 ivltests + +# Translating a parameter with the LSB > MSB requires -pallowsigned=1 to get +# the index calculation correct. +pr487 normal,-pallowsigned=1 ivltests gold=pr487.gold + +# Support for greater than 32 bit integer constants is an Icarus extension. +# If the -pallowsigned=1 flag is given then they can be converted correctly. +big_int normal,-pallowsigned=1 ivltests +pr2673846 normal,-pallowsigned=1 ivltests +pr2029336 normal,-pallowsigned=1 ivltests diff=work/pr2029336.out:gold/pr2029336.gold +urand normal,-pallowsigned=1 ivltests gold=urand.gold + +# The synthesized caseZ compare is not supported. +casesynth6 normal ivltests + +# Tests that require 4-state dynamic arrays +#unp_array_typedef CE,-g2005-sv ivltests +#sv_darray_word_size CE,-g2005-sv,-pallowsigned=1 ivltests +#sv_darray_function CE,-g2005-sv,-pallowsigned=1 ivltests + +# Priority and unique case statements are converted to ordinary case +# statements, so no warnings are generated. +case_priority normal,-g2009 ivltests gold=case_priority-vlog95.gold +case_unique normal,-g2009 ivltests gold=case_unique-vlog95.gold + +# An error is reported for both compiler passes +br_gh377 normal,-Ptest.name= ivltests gold=br_gh377-vlog95.gold diff --git a/ivtest/regression_report-devel.txt b/ivtest/regression_report-devel.txt new file mode 100644 index 000000000..84a661fd2 --- /dev/null +++ b/ivtest/regression_report-devel.txt @@ -0,0 +1,2564 @@ +Running compiler/VVP tests for Icarus Verilog version: 12. +---------------------------------------------------------------------------- + dffsynth: Passed - CE. + memsynth1: Passed - CE. + memsynth2: Passed - CE. + memsynth3: Passed - CE. + memsynth5: Passed - CE. + memsynth6: Passed - CE. + memsynth7: Passed - CE. + memsynth9: Passed - CE. + mix_reset: Passed - CE. + case1: Passed. + case2: Passed. + casex_synth: Passed. + pr903: Passed. + pr1388974: Passed. + br_gh13a: Passed. + param-width: Passed. + br_gh383d: Passed. + ca_time_real: Passed. + delayed_sfunc: Passed. + localparam_type: Passed. + parameter_type: Passed. + pr1701890: Passed. + pr1864110a: Passed. + pr1864110b: Passed. + pr1864115: Passed. + macro_str_esc: Passed. + macro_with_args: Passed. + mcl1: Passed. + pr622: Passed. + pr639: Passed. + pr1741212: Passed. + pr1912112: Passed. + pr1925360: Passed. + repeat1: Passed. + pr2002443: Passed - CO. + constfunc6_ams: Passed. + non-polymorphic-abs: Passed. + pr3270320_ams: Passed - CE. + test_va_math: Passed. + va_math: Passed. + abstime: Passed. + pr2590274a: Passed. + pr2590274b: Passed. + pr2590274c: Passed. + bitsel: Passed. + bitsel10: Passed. + bitsel2: Passed. + bitsel3: Passed. + bitsel4: Passed. + bitsel5: Passed. + bitsel6: Passed. + bitsel7: Passed. + bitsel8: Passed. + bitsel9: Passed. + bitwidth3: Passed. + clog2: Passed. + clog2-signal: Passed. + param_vec: Passed. + param_vec2: Passed. + pr498: Passed. + pr721: Passed. + pr809: Passed. + pr809b: Passed. + pr979: Passed. + pr1000: Passed. + pr1609611: Passed. + pr1750870: Passed. + pr1765789: Passed. + pr1771903: Passed. + pr1793749: Passed. + pr1793749b: Passed. + pr1861212b: Passed. + pr1864110c: Passed. + pr2806449: Passed. + pr2877555: Passed. + real4: Passed. + realtobits: Passed. + specparam1: Passed. + specparam2: Passed. + tern3: Passed. + v2005_math: Passed. + deposit: Passed. + deposit_wire: Passed. + sysargs: Passed. + fatal_et_al: Passed. + fatal_et_al2: Passed - RE. + plus_arg_string: Passed. + fileio: Passed. + pr1494799: Passed. + pr2428890c: Passed. + sv_cast_darray: Passed. + br978: Passed. + br_ml20150424: Passed. + pr2509349a: Passed. + pr2509349b: Passed. + simparam: Passed. + blocking_repeat_ec: Passed. + ca_time_smtm: Passed. + nb_array_pv: Passed. + nb_ec_array: Passed. + nb_ec_array_pv: Passed. + nb_ec_pv: Passed. + nb_ec_pv2: Passed. + nb_ec_real: Passed. + nb_ec_vector: Passed. + pr2486350: Passed. + pr534: Passed. + stime: Passed. + swrite: Passed. + time6: Passed. + time6b: Passed. + time6c: Passed. + concat1: Passed. + concat2: Passed. + constconcat1: Passed. + constconcat2: Passed. + rptconcat2: Passed. + sdw_lvalconcat2: Passed. + bool1: Passed. + compare_bool_reg: Passed. + constfunc8: Passed. + binary_nand: Passed. + binary_nor: Passed. + pr1528093: Passed. + br_gh456: Passed. + ca_64delay: Passed. + ca_var_delay: Passed. + cast_real_signed: Passed. + cast_real_unsigned: Passed. + pr1861212c: Passed. + pr1873372: Passed. + pr1880003: Passed. + pr1898293: Passed. + pr2123158: Passed. + pr2453002b: Passed. + pr2456943: Passed. + pr2715748: Passed. + pr2806474: Passed. + pr2976242: Passed. + pr2976242b: Passed. + pr2976242c: Passed - CE. + real8: Passed. + real_array: Passed. + real_array_nb: Passed. + real_concat_invalid1: Passed - CE. + real_mod_in_ca: Passed. + real_op_fail: Passed - CE. + real_pulse_clean: Passed. + real_pwr_in_ca: Passed. + real_select_invalid: Passed - CE. + real_wire_array: Passed. + real_wire_force_rel: Passed. + tern8: Passed. + br_gh99e: Passed. + pull371: Passed. + sv-2val-nets: Passed. + pr2476430: Passed. + eofmt_percent: Passed. + br_gh377: Passed. + cmdline_parm1: Passed. + array_dump: Passed. + pr2859628: Passed. + big_int: Passed. + ca_pow_signed: Passed. + urand: Passed. + race: Passed. + automatic_error4: Passed - CE. + array_lval_select3a: Passed - CE. + br605a: Passed - expected fail. + br605b: Passed - expected fail. + br971: Passed - expected fail. + br1005: Passed - CE. + br1015b: Passed - CE. + br_gh130b: Passed - CE. + br_gh386d: Passed - CE. + br_ml20150315b: Passed - CE. + sv_deferred_assert1: Passed - CE. + sv_deferred_assert2: Passed - CE. + sv_deferred_assume1: Passed - CE. + sv_deferred_assume2: Passed - CE. + pr1909940: Passed. + pr1909940b: Passed. + unnamed_generate_block: Passed. + br_gh497b: Passed - CE. + br_gh497d: Passed - CE. + br_gh497f: Passed - CE. + addsr: Passed. + addwide: Passed. + always3.1.1A: Passed - CE. + always3.1.1B: Passed - CE. + always3.1.1C: Passed. + always3.1.1D: Passed. + always3.1.1E: Passed. + always3.1.1F: Passed. + always3.1.1G: Passed. + always3.1.1H: Passed. + always3.1.1I: Passed. + always3.1.1J: Passed. + always3.1.1K: Passed. + always3.1.2A: Passed - CE. + always3.1.2B: Passed - CE. + always3.1.2C: Passed - CE. + always3.1.2D: Passed - CE. + always3.1.2E: Passed - CE. + always3.1.2F: Passed - CE. + always3.1.2G: Passed - CE. + always3.1.2H: Passed - CE. + always3.1.2I: Passed - CE. + always3.1.3A: Passed - CE. + always3.1.3B: Passed - CE. + always3.1.3B2: Passed. + always3.1.3C: Passed - CE. + always3.1.3D: Passed - CE. + always3.1.3D2: Passed. + always3.1.3E: Passed - CE. + always3.1.3E2: Passed. + always3.1.3F: Passed - CE. + always3.1.3F2: Passed. + always3.1.3G: Passed - CE. + always3.1.3H: Passed - CE. + always3.1.3J: Passed - CE. + always3.1.4A: Passed. + always3.1.4B: Passed. + always3.1.4C: Passed. + always3.1.4D: Passed. + always3.1.4E: Passed. + always3.1.4F: Passed. + always3.1.4G: Passed. + always3.1.4H: Passed. + always3.1.4I: Passed. + always3.1.5A: Passed. + always3.1.5B: Passed. + always3.1.5C: Passed. + always3.1.5D: Passed. + always3.1.5E: Passed. + always3.1.5F: Passed. + always3.1.6A: Passed. + always3.1.6B: Passed. + always3.1.6C: Passed. + always3.1.6D: Passed. + always3.1.7A: Passed. + always3.1.7B: Passed. + always3.1.7C: Passed. + always3.1.7D: Passed. + always3.1.8A: Passed. + always3.1.9A: Passed - CE. + always3.1.9B: Passed - CE. + always3.1.9C: Passed. + always3.1.9D: Passed. + always3.1.10A: Passed - CE. + always3.1.11A: Passed. + always3.1.11B: Passed. + always3.1.12A: Passed. + always3.1.12B: Passed. + always3.1.12C: Passed. + always_star_array_lval: Passed. + andnot1: Passed. + arith-unknown: Passed. + array4: Passed. + array5: Passed - CE. + array6: Passed. + array7: Passed. + array_lval_select1: Passed. + array_lval_select2: Passed. + array_lval_select3b: Passed - CE. + array_lval_select3c: Passed. + array_lval_select4a: Passed. + array_lval_select4b: Passed - CE. + array_lval_select5: Passed. + array_lval_select6: Passed. + array_packed_2d: Passed. + array_select: Passed. + array_select_a: Passed. + array_word_check: Passed. + array_word_width: Passed. + array_word_width2: Passed. + assign3.2A: Passed. + assign3.2B: Passed. + assign3.2C: Passed. + assign3.2D: Passed. + assign3.2E: Passed. + assign_add: Passed. + assign_deassign_pv: Passed. + assign_delay: Passed. + assign_deq: Passed. + assign_ge: Passed. + assign_le: Passed. + assign_mem1: Passed. + assign_mem2: Passed. + assign_nb1: Passed. + assign_nb2: Passed. + assign_neq: Passed. + attrib: Passed. + attrib01_module: Passed. + attrib02_port_decl: Passed. + attrib03_parameter: Passed. + attrib04_net_var: Passed. + attrib05_port_conn: Passed. + attrib06_operator_suffix: Passed. + attrib07_func_call: Passed. + attrib08_mod_inst: Passed. + attrib09_case: Passed. + automatic_error1: Passed - CE. + automatic_error2: Passed - CE. + automatic_error3: Passed - CE. + automatic_error5: Passed - CE. + automatic_error6: Passed - CE. + automatic_error7: Passed - CE. + automatic_error8: Passed - CE. + automatic_error9: Passed - CE. + automatic_error10: Passed - CE. + automatic_error11: Passed - RE. + automatic_error12: Passed - RE. + automatic_error13: Passed - RE. + automatic_events: Passed. + automatic_events2: Passed. + automatic_events3: Passed. + automatic_task: Passed. + automatic_task2: Passed. + automatic_task3: Passed. + bitwidth: Passed. + bitwidth2: Passed. + blankport: Passed. + block_only_with_var_def: Passed. + bnot: Passed. + br916a: Passed. + br916b: Passed. + br918a: Passed. + br918b: Passed. + br918c: Passed. + br918d: Passed. + br919: Passed. + br924: Passed - CE. + br930: Passed - CO. + br931: Passed. + br935: Passed. + br937: Passed. + br946: Passed. + br947: Passed. + br948: Passed. + br955: Passed. + br960a: Passed. + br960b: Passed. + br960c: Passed. + br960d: Passed. + br961: Passed. + br961a: Passed - CE. + br965: Passed. + br967: Passed. + br968: Passed. + br972: Passed. + br977: Passed. + br982: Passed - CE. + br982a: Passed - CE. + br982b: Passed - CE. + br988: Passed. + br990: Passed. + br991a: Passed. + br999: Passed. + br1000: Passed. + br1001: Passed. + br1006: Passed. + br1007: Passed. + br1008: Passed. + br1015a: Passed - CE. + br1019: Passed. + br1027: Passed. + br1027a: Passed - CE. + br1027c: Passed - CE. + br1027e: Passed - CE. + br1029a: Passed. + br1029b: Passed. + br1029c: Passed - CE. + br_gh6: Passed. + br_gh7: Passed. + br_gh8: Passed. + br_gh9: Passed. + br_gh11: Passed - CO. + br_gh12: Passed. + br_gh13: Passed. + br_gh14: Passed. + br_gh15: Passed. + br_gh18: Passed. + br_gh19: Passed. + br_gh19a: Passed. + br_gh19b: Passed. + br_gh22: Passed. + br_gh25a: Passed - CE. + br_gh25b: Passed - CE. + br_gh26: Passed - CE. + br_gh28: Passed. + br_gh30: Passed. + br_gh33: Passed. + br_gh37: Passed. + br_gh60a: Passed - CE. + br_gh62: Passed - CE. + br_gh79: Passed - CE. + br_gh99a: Passed. + br_gh99b: Passed. + br_gh99d: Passed. + br_gh99f: Passed. + br_gh99g: Passed. + br_gh99h: Passed. + br_gh99i: Passed. + br_gh99j: Passed. + br_gh99k: Passed. + br_gh99l: Passed. + br_gh99m: Passed. + br_gh99o: Passed. + br_gh99p: Passed. + br_gh99q: Passed. + br_gh99r: Passed. + br_gh99s: Passed. + br_gh99t: Passed. + br_gh99u: Passed. + br_gh103: Passed. + br_gh127a: Passed. + br_gh127b: Passed. + br_gh127c: Passed. + br_gh127d: Passed. + br_gh127e: Passed. + br_gh127f: Passed. + br_gh142: Passed - CE. + br_gh152: Passed - CE. + br_gh157: Passed. + br_gh162: Passed. + br_gh163: Passed - CE. + br_gh198: Passed. + br_gh199a: Passed. + br_gh199b: Passed. + br_gh209: Passed. + br_gh230: Passed - RE. + br_gh244a: Passed. + br_gh244b: Passed. + br_gh277a: Passed. + br_gh283a: Passed. + br_gh283b: Passed. + br_gh283c: Passed. + br_gh309: Passed. + br_gh315: Passed. + br_gh316a: Passed. + br_gh316b: Passed. + br_gh316c: Passed. + br_gh330: Passed. + br_gh345: Passed. + br_gh356a: Passed. + br_gh356b: Passed. + br_gh435: Passed. + br_gh484: Passed. + br_gh497a: Passed. + br_gh497c: Passed. + br_gh497e: Passed. + br_gh508b: Passed. + br_gh515: Passed. + br_gh531: Passed. + br_gh533: Passed - CE. + br_gh567: Passed. + br_ml20150315: Passed. + br_ml20150321: Passed - CE. + br_ml20150606: Passed. + br_mw20171108: Passed. + br_ml20190806a: Passed. + br_ml20190806b: Passed. + br_ml20190814: Passed. + bufif: Passed. + busbug: Passed. + ca_force: Passed. + ca_func: Passed. + ca_mult: Passed. + ca_pow_synth: Passed. + ca_pow_unsigned: Passed. + ca_real_logical: Passed. + ca_time: Passed. + case3.8A: Passed. + case3.8B: Passed. + case3.8C: Passed. + case3.8D: Passed. + casex3.9A: Passed. + casex3.9B: Passed. + casex3.9C: Passed. + casex3.9D: Passed. + casex3.9E: Passed. + casez3.10A: Passed. + casez3.10B: Passed. + casez3.10C: Passed. + casez3.10D: Passed. + casez3.10E: Passed. + cast_int: Passed. + check_constant_1: Passed - CE. + check_constant_2: Passed - CE. + check_constant_3: Passed - CE. + check_constant_4: Passed - CE. + check_constant_5: Passed - CE. + check_constant_6: Passed - CE. + check_constant_7: Passed - CE. + check_constant_8: Passed - CE. + check_constant_9: Passed - CE. + check_constant_10: Passed - CE. + check_constant_11: Passed - CE. + check_constant_12: Passed - CE. + check_constant_13: Passed - CE. + check_constant_14: Passed - CE. + check_constant_15: Passed - CE. + check_constant_16: Passed - CE. + check_constant_17: Passed - CE. + check_constant_18: Passed - CE. + check_constant_19: Passed - CE. + check_constant_20: Passed - CE. + cmos: Passed. + comment1: Passed - CE. + comp1000: Passed. + comp1001: Passed. + comp1001_fail3: Passed. + comp1001_fail4: Passed. + comp1001_fail5: Passed. + complex_lidx: Passed. + con_tri: Passed. + concat3: Passed. + concat4: Passed. + concat_zero_wid_fail: Passed - CE. + concat_zero_wid_fail2: Passed. + cond_band: Passed. + cond_wide: Passed. + cond_wide2: Passed. + const: Passed. + const2: Passed. + const3: Passed. + const4: Passed. + constadd: Passed. + constadd2: Passed. + constadd3: Passed. + constfunc1: Passed. + constfunc2: Passed. + constfunc3: Passed. + constfunc4: Passed. + constfunc5: Passed. + constfunc6: Passed. + constfunc7: Passed. + constfunc9: Passed. + constfunc10: Passed. + constfunc11: Passed. + constfunc12: Passed. + constfunc13: Passed. + constfunc14: Passed. + constfunc15: Passed. + constmult: Passed. + consttern: Passed. + contrib8.1: Passed. + contrib8.2: Passed. + contrib8.3: Passed - CE. + contrib8.4: Passed. + contrib8.5: Passed. + countdrivers1: Passed. + countdrivers2: Passed. + countdrivers3: Passed. + countdrivers4: Passed. + countdrivers5: Passed. + cprop: Passed. + credence20041209: Passed. + dangling_port: Passed. + dcomp1: Passed. + deassign3.4A: Passed. + decl_assign1: Passed. + def_nettype: Passed. + def_nettype_none: Passed - CE. + define1: Passed. + defparam: Passed. + defparam2: Passed. + defparam3: Passed. + defparam3.5: Passed. + defparam4: Passed. + delay: Passed. + delay2: Passed. + delay3: Passed. + delay4: Passed. + delay5: Passed. + delay_assign_nb: Passed. + delay_assign_nb2: Passed. + delay_var: Passed. + delayed_comp_reduct: Passed. + dff1: Passed. + disable3.6A: Passed. + disable3.6B: Passed. + disable_cleanup: Passed. + disable_fork: Passed. + disblock: Passed. + disblock2: Passed. + disp_dec: Passed. + disp_dec2: Passed. + disp_leading_z: Passed. + disp_parm: Passed. + disp_part: Passed. + div16: Passed. + dotinid: Passed. + drive_strength: Passed. + drive_strength1: Passed. + drive_strength2: Passed. + drive_strength3: Passed. + dummy7: Passed. + dump_memword: Passed. + dumpvars: Passed. + eeq: Passed. + else1: Passed. + else2: Passed. + else3: Passed. + elsif_test: Passed. + eq: Passed. + escape1: Passed. + escape2a: Passed - CO. + escape2b: Passed - CO. + escape2c: Passed - CO. + escape3: Passed. + escape4: Passed. + escape4b: Passed. + event2: Passed. + event3: Passed. + event3.15: Passed. + event_array: Passed - CE. + event_list: Passed. + event_list2: Passed. + event_list3: Passed. + extend: Passed. + fdisplay1: Passed. + fdisplay2: Passed. + fdisplay3: Passed - RE. + fdisplay_fail_fd: Passed. + fdisplay_fail_mcd: Passed. + fifo: Passed. + fopen1: Passed. + fopen2: Passed. + for3.16A: Passed. + force1: Passed. + force2: Passed. + force3.17A: Passed. + force3.17B: Passed. + force3.17C: Passed. + force_lval_part: Passed. + force_release_reg_pv: Passed. + force_release_wire8_pv: Passed. + force_release_wire_pv: Passed. + fork1: Passed. + fork3.19A: Passed. + fork3.19B: Passed. + format: Passed. + fr47: Passed. + fread: Passed. + fread-error: Passed - RE. + fscanf_u: Passed. + fscanf_u_warn: Passed. + fscanf_z: Passed. + fscanf_z_warn: Passed. + function1: Passed. + function2: Passed. + function3: Passed. + function3.11B: Passed. + function3.11C: Passed. + function3.11D: Passed. + function3.11F: Passed. + function4: Passed - CE. + function5: Passed - CO. + function6: Passed. + function7: Passed. + function8: Passed. + function9: Passed. + function_exp: Passed. + ga_and: Passed. + ga_mod: Passed. + ga_mod1: Passed. + ga_mod2: Passed. + ga_nand: Passed. + ga_nor: Passed. + ga_or: Passed. + ga_xnor: Passed. + ga_xor: Passed. + galan: Passed. + gate_connect1: Passed. + gate_connect2: Passed - CE. + gen_case_opt1: Passed. + gen_case_opt2: Passed. + gen_case_opt3: Passed. + gencrc: Passed. + generate_case: Passed. + generate_case2: Passed. + generate_case3: Passed. + generate_multi_loop: Passed. + genloop: Passed. + genvar_scopes: Passed. + hello1: Passed. + hier_ref_error: Passed - CE. + hierspace: Passed. + idiv1: Passed. + idiv2: Passed. + idiv3: Passed. + ifdef1: Passed. + ifdef2: Passed. + ifdef3: Passed. + ifdef4: Passed. + ifdef_fail: Passed - CE. + include1: Passed. + include2: Passed. + include3: Passed. + indef_width_concat: Passed - CE. + initmod: Passed. + initmod2: Passed. + inout: Passed. + inout2: Passed. + inout3: Passed. + inout4: Passed. + int_not_signext: Passed. + integer1lt: Passed. + integer2le: Passed. + integer3gt: Passed. + integer4ge: Passed. + integer5: Passed. + itor_rtoi: Passed. + land2: Passed. + land3: Passed. + land4: Passed. + landor1: Passed. + ldelay1: Passed. + ldelay2: Passed. + ldelay3: Passed. + ldelay4: Passed. + ldelay5: Passed. + lh_catadd: Passed. + lh_memcat: Passed. + lh_memcat2: Passed. + lh_memcat3: Passed. + lh_varindx: Passed. + lh_varindx2: Passed. + lh_varindx4: Passed. + lh_varindx5: Passed. + long_div: Passed. + macro2: Passed. + macro_redefinition: Passed. + macro_replacement: Passed. + macsub: Passed. + mangle: Passed. + mangle_1: Passed. + many_drivers: Passed. + mcl2: Passed. + mem1: Passed. + mem2port: Passed. + memassign: Passed. + memidx: Passed. + memidxrng: Passed. + meminit: Passed. + meminit2: Passed. + memport_bs: Passed. + memref: Passed. + mhead_task: Passed. + mixed_type_div_mod: Passed. + mixed_width_case: Passed. + modparam: Passed. + module3.12A: Passed. + module3.12B: Passed. + modulus: Passed. + modulus2: Passed. + monitor: Passed. + monitor2: Passed. + monitor3: Passed. + mult1: Passed. + mult16: Passed. + mult2: Passed. + multi_bit_strength: Passed. + multi_driver_delay: Passed. + multiply_large: Passed. + muxtest: Passed. + named_event_no_edges: Passed - CE. + nb_assign: Passed. + nb_delay: Passed. + nblkorder: Passed. + negative_genvar: Passed. + negvalue: Passed. + neq1: Passed. + nested_func: Passed. + nested_impl_event1: Passed. + nested_impl_event2: Passed. + no_if_statement: Passed - CE. + no_timescale_in_module: Passed - CE. + npmos: Passed. + npmos2: Passed. + onehot: Passed. + p_monta: Passed. + par_mismatch: Passed - CE. + param-extend: Passed. + param_add: Passed. + param_and: Passed. + param_and2: Passed. + param_band: Passed. + param_binv: Passed. + param_bor: Passed. + param_concat: Passed. + param_eq3: Passed. + param_expr: Passed. + param_mod: Passed. + param_select: Passed. + param_select2: Passed. + param_select3: Passed. + param_string: Passed. + param_tern: Passed. + param_tern2: Passed. + param_test1: Passed. + param_test2: Passed. + param_test3: Passed. + param_test4: Passed. + param_times: Passed. + patch1268: Passed. + pca1: Passed. + pic: Passed. + port-test2: Passed. + port-test3: Passed - CE. + port-test4a: Passed - CE. + port-test4b: Passed - CE. + port-test5: Passed. + port-test6: Passed. + port-test7: Passed. + posedge: Passed. + pow-ca: Passed. + pow-const: Passed. + pow-proc: Passed. + pow_ca_signed: Passed. + pow_ca_unsigned: Passed. + pow_reg_signed: Passed. + pow_reg_unsigned: Passed. + pow_signed: Passed. + pow_unsigned: Passed. + pr136: Passed. + pr142: Passed. + pr183: Passed - CO. + pr224: Passed. + pr224a: Passed. + pr243: Passed. + pr245: Passed. + pr245_std: Passed. + pr273: Passed. + pr298: Passed. + pr304: Passed. + pr307: Passed. + pr307a: Passed. + pr312: Passed. + pr338: Passed - CO. + pr355: Passed. + pr377: Passed. + pr434: Passed. + pr445: Passed. + pr478: Passed. + pr487: Passed. + pr492: Passed. + pr508: Passed. + pr509: Passed. + pr509b: Passed. + pr511: Passed. + pr513: Passed. + pr522: Passed. + pr524: Passed. + pr527: Passed. + pr528: Passed. + pr528b: Passed. + pr529: Passed. + pr530a: Passed. + pr530b: Passed. + pr530c: Passed. + pr531a: Passed. + pr531b: Passed. + pr532: Passed. + pr532b: Passed. + pr533: Passed. + pr538: Passed. + pr540: Passed. + pr540b: Passed. + pr540c: Passed. + pr541: Passed. + pr542: Passed. + pr544: Passed. + pr547: Passed. + pr556: Passed. + pr564: Passed. + pr569: Passed. + pr572: Passed. + pr572b: Passed. + pr578: Passed. + pr584: Passed. + pr585: Passed. + pr587: Passed. + pr590: Passed. + pr594: Passed. + pr596: Passed. + pr602: Passed. + pr617: Passed. + pr632: Passed. + pr673: Passed. + pr675: Passed. + pr678: Passed. + pr690: Passed. + pr693: Passed. + pr699: Passed. + pr699b: Passed. + pr704: Passed. + pr707: Passed. + pr708: Passed. + pr710: Passed. + pr718: Passed. + pr722: Passed. + pr729: Passed. + pr734: Passed. + pr735: Passed. + pr748: Passed. + pr751: Passed. + pr757: Passed. + pr772: Passed. + pr810: Passed. + pr812: Passed. + pr820: Passed. + pr823: Passed. + pr841: Passed. + pr842: Passed. + pr848: Passed. + pr856: Passed. + pr859: Passed. + pr860: Passed. + pr872: Passed. + pr902: Passed. + pr905: Passed. + pr910: Passed. + pr913: Passed. + pr923: Passed. + pr938: Passed. + pr938b: Passed. + pr938b_std: Passed. + pr941: Passed. + pr973: Passed. + pr978: Passed. + pr985: Passed. + pr987: Passed. + pr990: Passed. + pr991: Passed. + pr993: Passed. + pr995: Passed. + pr1002: Passed. + pr1002a: Passed. + pr1007: Passed. + pr1008: Passed. + pr1022: Passed. + pr1024: Passed. + pr1026: Passed. + pr1029: Passed. + pr1032: Passed. + pr1033: Passed. + pr1065: Passed. + pr1072: Passed. + pr1077: Passed. + pr1087: Passed. + pr1101: Passed. + pr1115: Passed. + pr1353345: Passed. + pr1353345b: Passed. + pr1367855: Passed. + pr1380261: Passed. + pr1403406: Passed. + pr1403406a: Passed. + pr1403406b: Passed. + pr1421777: Passed. + pr1444055: Passed. + pr1449749a: Passed. + pr1455873: Passed. + pr1465769: Passed. + pr1467825: Passed - CO. + pr1474283: Passed. + pr1474316: Passed. + pr1474318: Passed. + pr1476440: Passed. + pr1477190: Passed. + pr1478121: Passed. + pr1478988: Passed. + pr1489568: Passed. + pr1489570: Passed. + pr1491355: Passed. + pr1492075: Passed. + pr1508882: Passed. + pr1510724: Passed. + pr1515168: Passed. + pr1520314: Passed - CO. + pr1522570: Passed. + pr1530426: Passed. + pr1561597: Passed. + pr1565544: Passed. + pr1565699b: Passed. + pr1570451: Passed. + pr1570451b: Passed. + pr1570635: Passed. + pr1570635b: Passed. + pr1574175: Passed. + pr1581580: Passed. + pr1587634: Passed - CO. + pr1587669: Passed. + pr1589497: Passed. + pr1598445: Passed. + pr1601896: Passed. + pr1601898: Passed. + pr1603313: Passed. + pr1603918: Passed. + pr1612693: Passed. + pr1623097: Passed. + pr1625912: Passed. + pr1628288: Passed. + pr1628300: Passed. + pr1629683: Passed. + pr1632861: Passed. + pr1634526: Passed. + pr1636409: Passed. + pr1637208: Passed. + pr1638985: Passed. + pr1639060: Passed. + pr1639064: Passed. + pr1639064b: Passed. + pr1639968: Passed. + pr1639971: Passed. + pr1645277: Passed. + pr1645518: Passed. + pr1648365: Passed. + pr1650842: Passed. + pr1657307: Passed. + pr1661640: Passed. + pr1662508: Passed. + pr1664684: Passed. + pr1675789: Passed. + pr1675789b: Passed. + pr1676071: Passed. + pr1676836: Passed. + pr1682887: Passed. + pr1687193: Passed. + pr1688717: Passed. + pr1690058: Passed. + pr1691599b: Passed. + pr1691709: Passed. + pr1693890: Passed. + pr1693921: Passed. + pr1694413: Passed. + pr1694427: Passed. + pr1695257: Passed - CO. + pr1695309: Passed. + pr1695322: Passed. + pr1695334: Passed. + pr1696137: Passed. + pr1697250: Passed. + pr1697732: Passed. + pr1698499: Passed. + pr1698658: Passed. + pr1698659: Passed. + pr1698820: Passed. + pr1699444: Passed. + pr1699519: Passed. + pr1701855: Passed. + pr1701855b: Passed. + pr1701889: Passed. + pr1701921: Passed. + pr1702593: Passed. + pr1703120: Passed. + pr1703346: Passed. + pr1703959: Passed. + pr1704013: Passed - CE. + pr1704726a: Passed - CE. + pr1704726b: Passed. + pr1704726c: Passed - CE. + pr1704726d: Passed - CE. + pr1705027: Passed - CO. + pr1716276: Passed. + pr1717361: Passed. + pr1719055: Passed. + pr1723367: Passed. + pr1735724: Passed - CE. + pr1735822: Passed. + pr1735836: Passed. + pr1740476b: Passed. + pr1742910: Passed. + pr1745005: Passed. + pr1746401: Passed. + pr1746848: Passed. + pr1752353: Passed. + pr1752823a: Passed. + pr1752823b: Passed. + pr1755593: Passed. + pr1755629: Passed. + pr1758122: Passed. + pr1758135: Passed. + pr1763333: Passed - CE. + pr1770199: Passed. + pr1776485: Passed. + pr1777103: Passed. + pr1780480: Passed. + pr1784984: Passed. + pr1787394a: Passed. + pr1787394b: Passed. + pr1787423: Passed. + pr1787423b: Passed. + pr1787423c: Passed. + pr1792108: Passed. + pr1792152: Passed. + pr1792734: Passed. + pr1793157: Passed. + pr1794362: Passed. + pr1795005a: Passed. + pr1795005b: Passed. + pr1799904: Passed. + pr1804877: Passed. + pr1805837: Passed. + pr1812297: Passed. + pr1819452: Passed. + pr1820472: Passed. + pr1822658: Passed. + pr1823732: Passed. + pr1828642: Passed. + pr1830834: Passed. + pr1831724: Passed. + pr1832097a: Passed. + pr1832097b: Passed. + pr1833024: Passed - CE. + pr1833754: Passed - CE. + pr1841300: Passed. + pr1845683: Passed. + pr1851310: Passed. + pr1855504: Passed. + pr1861212a: Passed. + pr1862744a: Passed. + pr1862744b: Passed - CE. + pr1866215: Passed. + pr1866215b: Passed. + pr1867161a: Passed. + pr1867161b: Passed. + pr1867332: Passed - CO. + pr1868792: Passed. + pr1868991a: Passed. + pr1868991b: Passed - CO. + pr1869769: Passed. + pr1869772: Passed. + pr1869781: Passed. + pr1873146: Passed. + pr1875866: Passed. + pr1875866b: Passed. + pr1876798: Passed. + pr1877740: Passed. + pr1877743: Passed. + pr1878909: Passed. + pr1879226: Passed. + pr1883052: Passed. + pr1883052b: Passed. + pr1885847: Passed. + pr1887168: Passed. + pr1892959: Passed. + pr1892959b: Passed. + pr1898983: Passed. + pr1901125: Passed. + pr1903157: Passed - CO. + pr1903324: Passed. + pr1903343: Passed. + pr1903520: Passed. + pr1907192: Passed. + pr1912843: Passed. + pr1913918a: Passed. + pr1913918b: Passed. + pr1913918c: Passed. + pr1913937: Passed. + pr1916261: Passed. + pr1916261a: Passed - CE. + pr1921332: Passed - CO. + pr1924845: Passed. + pr1925356: Passed. + pr1925363a: Passed - CE. + pr1925363b: Passed - CE. + pr1932444: Passed. + pr1934744: Passed. + pr1936363: Passed. + pr1938138: Passed - CE. + pr1939165: Passed. + pr1946411: Passed. + pr1948110: Passed. + pr1948342: Passed. + pr1949025: Passed. + pr1950282: Passed. + pr1956211: Passed. + pr1958801: Passed. + pr1960545: Passed. + pr1960548: Passed. + pr1960558: Passed. + pr1960575: Passed. + pr1960596: Passed. + pr1960619: Passed. + pr1960625: Passed. + pr1960633: Passed. + pr1963240: Passed. + pr1963960: Passed. + pr1963962: Passed. + pr1971662a: Passed - CE. + pr1971662b: Passed - CE. + pr1978358: Passed. + pr1978358b: Passed. + pr1978358c: Passed. + pr1978358d: Passed. + pr1983762: Passed. + pr1985582: Passed. + pr1988302: Passed. + pr1988302b: Passed - CE. + pr1988310: Passed. + pr1990029: Passed. + pr1990164: Passed. + pr1990269: Passed. + pr1992244: Passed. + pr1992729: Passed. + pr1993479: Passed. + pr2001162: Passed. + pr2011429: Passed. + pr2013758: Passed. + pr2014673: Passed. + pr2015466: Passed. + pr2018235a: Passed. + pr2018235b: Passed. + pr2018305: Passed. + pr2019553: Passed. + pr2029336: Passed. + pr2030767: Passed. + pr2036953: Passed. + pr2038048: Passed. + pr2039632: Passed - CE. + pr2039694: Passed. + pr2043324: Passed. + pr2043585: Passed. + pr2051694: Passed - CE. + pr2051975: Passed - CE. + pr2053944: Passed. + pr2076363: Passed. + pr2076391: Passed. + pr2076425: Passed. + pr2085984: Passed. + pr2091455: Passed. + pr2109179: Passed. + pr2117473: Passed. + pr2117488: Passed. + pr2119622: Passed. + pr2121536: Passed. + pr2121536b: Passed. + pr2123190: Passed. + pr2132552: Passed. + pr2136787: Passed. + pr2138682: Passed. + pr2138979: Passed. + pr2138979b: Passed. + pr2138979c: Passed. + pr2138979d: Passed. + pr2139593: Passed. + pr2146620: Passed. + pr2146620b: Passed. + pr2146620c: Passed. + pr2146824: Passed. + pr2148401: Passed. + pr2152011: Passed. + pr2159630: Passed. + pr2166188: Passed. + pr2166311: Passed. + pr2169870: Passed. + pr2172606: Passed. + pr2172606b: Passed. + pr2181249: Passed. + pr2190323: Passed. + pr2201909: Passed. + pr2201909b: Passed. + pr2202706: Passed. + pr2202706b: Passed. + pr2202706c: Passed. + pr2202846a: Passed. + pr2202846b: Passed. + pr2202846c: Passed. + pr2208681: Passed. + pr2215342: Passed. + pr2219441: Passed. + pr2219441b: Passed. + pr2224845: Passed. + pr2224949: Passed. + pr2233180: Passed. + pr2233180b: Passed. + pr2233180c: Passed. + pr2233192: Passed. + pr2233192b: Passed. + pr2233192c: Passed. + pr2248925: Passed. + pr2251119: Passed. + pr2257003: Passed. + pr2257003b: Passed. + pr2270035: Passed. + pr2276163: Passed. + pr2281479: Passed. + pr2305307: Passed. + pr2305307b: Passed. + pr2305307c: Passed. + pr2306259: Passed. + pr2350934: Passed. + pr2350934b: Passed. + pr2350988: Passed. + pr2352834: Passed. + pr2355304: Passed. + pr2355304b: Passed. + pr2358264: Passed. + pr2358848: Passed. + pr2395378a: Passed - CE. + pr2395378b: Passed - CE. + pr2395378c: Passed - CE. + pr2395835: Passed. + pr2425055a: Passed. + pr2425055b: Passed. + pr2425055c: Passed. + pr2428890: Passed. + pr2428890b: Passed. + pr2434688: Passed. + pr2434688b: Passed. + pr2450244: Passed. + pr2453002: Passed. + pr2459681: Passed. + pr2470181a: Passed. + pr2470181b: Passed. + pr2503208: Passed. + pr2528915: Passed - CE. + pr2533175: Passed. + pr2579479: Passed. + pr2580730: Passed. + pr2593733: Passed. + pr2597278: Passed. + pr2597278b: Passed - CE. + pr2605006: Passed. + pr2673846: Passed. + pr2688910: Passed. + pr2709097: Passed. + pr2715547: Passed. + pr2715558: Passed. + pr2715558b: Passed. + pr2721213: Passed. + pr2722330a: Passed. + pr2722330b: Passed. + pr2722339a: Passed. + pr2722339b: Passed. + pr2723712: Passed. + pr2725700a: Passed. + pr2725700b: Passed. + pr2725700c: Passed. + pr2728032: Passed. + pr2728547: Passed. + pr2728812a: Passed. + pr2728812b: Passed - CE. + pr2728812c: Passed - CE. + pr2745281: Passed. + pr2781595: Passed. + pr2785294: Passed. + pr2788686: Passed. + pr2790236: Passed. + pr2792883: Passed - CE. + pr2792897: Passed. + pr2794144: Passed - CE. + pr2800985a: Passed. + pr2800985b: Passed - RE. + pr2801134: Passed. + pr2801662: Passed. + pr2809288: Passed - CE. + pr2815398a: Passed. + pr2815398a_std: Passed. + pr2815398b: Passed. + pr2818823: Passed. + pr2823414: Passed - CE. + pr2823711: Passed. + pr2824189: Passed. + pr2829776: Passed. + pr2829776b: Passed. + pr2832234: Passed. + pr2834340: Passed. + pr2834340b: Passed. + pr2835632a: Passed. + pr2835632b: Passed. + pr2837451: Passed. + pr2842185: Passed. + pr2842621: Passed. + pr2842621_std: Passed. + pr2848986: Passed - CE. + pr2849783: Passed. + pr2865563: Passed. + pr2877564: Passed - CE. + pr2883958: Passed. + pr2885048: Passed. + pr2890322: Passed. + pr2901556: Passed. + pr2909386a: Passed. + pr2909386b: Passed. + pr2909414: Passed. + pr2909555: Passed. + pr2913404: Passed. + pr2913416: Passed. + pr2913438a: Passed. + pr2913438b: Passed. + pr2913927: Passed. + pr2918095: Passed. + pr2922063: Passed. + pr2922063a: Passed. + pr2922063b: Passed. + pr2924354: Passed. + pr2929913: Passed. + pr2930506: Passed. + pr2937417: Passed. + pr2937417b: Passed. + pr2937417c: Passed. + pr2941939: Passed. + pr2943394: Passed. + pr2951657: Passed. + pr2969724: Passed. + pr2971207: Passed. + pr2972866: Passed. + pr2973532: Passed. + pr2974051: Passed. + pr2974216: Passed. + pr2974216b: Passed. + pr2974294: Passed. + pr2985542: Passed. + pr2986497: Passed - CO. + pr2986528: Passed. + pr2991457: Passed. + pr2991457b: Passed. + pr2994193: Passed. + pr2998515: Passed. + pr3011327: Passed. + pr3012758: Passed. + pr3015421: Passed - CE. + pr3022502: Passed. + pr3024131: Passed. + pr3039548: Passed. + pr3044843: Passed. + pr3054101a: Passed. + pr3054101b: Passed. + pr3054101c: Passed. + pr3054101d: Passed. + pr3054101e: Passed. + pr3054101f: Passed. + pr3054101g: Passed. + pr3054101h: Passed. + pr3061015a: Passed - CE. + pr3061015b: Passed - CE. + pr3061015c: Passed - CE. + pr3064375: Passed. + pr3064511: Passed. + pr3077640: Passed. + pr3078759: Passed - CO. + pr3098439: Passed. + pr3098439a: Passed. + pr3098439b: Passed. + pr3103880: Passed. + pr3104254: Passed. + pr3112073a: Passed - CE. + pr3149494: Passed. + pr3190941: Passed - CE. + pr3190948: Passed. + pr3194155: Passed. + pr3197861: Passed. + pr3197917: Passed. + pr3270320: Passed - CE. + pr3284821: Passed. + pr3292735: Passed. + pr3296466a: Passed. + pr3296466b: Passed. + pr3296466c: Passed. + pr3296466d: Passed. + pr3306516: Passed. + pr3309391: Passed. + pr3368642: Passed. + pr3409749: Passed. + pr3437290a: Passed. + pr3437290b: Passed. + pr3437290c: Passed. + pr3441576: Passed. + pr3445452: Passed. + pr3452808: Passed. + pr3465541: Passed. + pr3477107: Passed. + pr3499807: Passed. + pr3522653: Passed. + pr3527022: Passed. + pr3527694: Passed. + pr3534422: Passed. + pr3539372: Passed. + pr3549328: Passed - CE. + pr3557493: Passed. + pr3561350: Passed. + pr3563412: Passed. + pr3571573: Passed. + pr3582052: Passed. + pr3587570: Passed. + pr3592746: Passed. + prng: Passed. + ptest001: Passed. + ptest002: Passed. + ptest003: Passed. + ptest004: Passed. + ptest005: Passed. + ptest006: Passed. + ptest007: Passed. + ptest008: Passed. + ptest009: Passed. + ptest010: Passed. + ptest011: Passed. + pullupdown: Passed. + pullupdown2: Passed. + pullupdown3: Passed. + pv_undef_sig_sel: Passed. + qmark: Passed. + qmark1: Passed. + qmark3: Passed. + qmark5: Passed. + qmark6: Passed. + queue: Passed. + queue_fail: Passed - RE. + queue_stat: Passed. + ram16x1: Passed. + readmem-error: Passed. + readmem-invalid: Passed - RE. + readmemb1: Passed. + readmemb2: Passed. + readmemb3: Passed. + readmemh1: Passed. + readmemh1a: Passed. + readmemh2: Passed. + readmemh3: Passed. + readmemh4: Passed. + readmemh5: Passed - CE. + real: Passed. + real2: Passed. + real3: Passed. + real5: Passed. + real6: Passed. + real7: Passed. + real9: Passed. + real10: Passed. + real11: Passed. + real_assign_deassign: Passed. + real_concat_invalid2: Passed - CE. + real_delay: Passed. + real_events: Passed. + real_force_rel: Passed. + real_invalid_ops: Passed - CE. + real_logical: Passed. + real_reg_force_rel: Passed. + recursive_func: Passed. + recursive_task: Passed. + redef_net_error: Passed - CE. + redef_reg_error: Passed - CE. + repeat2: Passed. + repeat_expr_probe: Passed. + repl_zero_wid_fail: Passed - CE. + repl_zero_wid_pass: Passed. + resetall: Passed. + resetall2: Passed. + resolv1: Passed. + rise_fall_decay1: Passed. + rise_fall_decay2: Passed. + rise_fall_delay1: Passed. + rise_fall_delay2: Passed. + rise_fall_delay3: Passed. + rl_pow: Passed. + rnpmos: Passed. + rnpmos2: Passed. + rop: Passed. + rptconcat: Passed. + rtran: Passed. + rtranif0: Passed. + rtranif1: Passed. + scan-invalid: Passed - RE. + scanf: Passed. + scanf2: Passed. + scanf3: Passed. + scanf4: Passed. + sched1: Passed. + sched2: Passed. + schedule: Passed. + scope1: Passed. + scope2: Passed. + scope2b: Passed - CE. + scope4: Passed. + scope5: Passed. + scoped_events: Passed. + sdf1: Passed. + sdf2: Passed. + sdf3: Passed. + sdf4: Passed. + sdf5: Passed. + sdf6: Passed. + sdf7: Passed. + sdf8: Passed. + sdf_del_max: Passed. + sdf_del_min: Passed. + sdf_del_typ: Passed. + sdf_esc_id: Passed. + sdw_always1: Passed. + sdw_always2: Passed. + sdw_always3: Passed. + sdw_array: Passed. + sdw_assign: Passed. + sdw_dsbl: Passed. + sdw_force: Passed. + sdw_function1: Passed. + sdw_function2: Passed. + sdw_function3: Passed. + sdw_function4: Passed. + sdw_function5: Passed. + sdw_instmod1: Passed. + sdw_instmod2: Passed. + sdw_int: Passed. + sdw_lvalconcat: Passed. + sdw_param1: Passed. + sdw_param2: Passed. + sdw_release: Passed. + sdw_stmt002: Passed. + sdw_task1: Passed. + sdw_task2: Passed. + sel_rval_bit_ob: Passed. + sel_rval_part_ob: Passed. + select: Passed. + select2: Passed. + select3: Passed. + select4: Passed. + select5: Passed. + select6: Passed. + select7: Passed. + select8: Passed. + select_padding: Passed. + shellho1: Passed. + shift1: Passed. + shift2: Passed. + shift3: Passed. + shift4: Passed. + shift5: Passed. + shift_pad: Passed. + signed1: Passed. + signed2: Passed. + signed3: Passed. + signed4: Passed. + signed5: Passed. + signed6: Passed. + signed7: Passed. + signed8: Passed. + signed9: Passed. + signed10: Passed. + signed11: Passed. + signed12: Passed. + signed13: Passed. + signed_a: Passed. + signed_equality: Passed. + signed_net_display: Passed. + signed_part: Passed. + signed_pv: Passed. + sp2: Passed. + specify1: Passed - CO. + specify2: Passed. + specify3: Passed. + specify4: Passed. + specify5: Passed. + specify_01: Passed. + sqrt32: Passed. + sscanf_u: Passed. + sscanf_z: Passed. + stask_parm1: Passed. + stask_parm2: Passed. + stask_sens_null_arg: Passed. + string1: Passed. + string2: Passed. + string3: Passed. + string4: Passed. + string5: Passed. + string7: Passed. + string8: Passed. + string9: Passed. + string10: Passed. + string11: Passed. + string12: Passed. + supply1: Passed. + supply2: Passed. + switch_primitives: Passed. + sys_func_task_error: Passed - RE. + talu: Passed. + task-scope: Passed. + task3.14A: Passed. + task3.14B: Passed. + task3.14C: Passed. + task3.14D: Passed. + task3.14E: Passed. + task3.14F: Passed. + task_bypath: Passed. + task_inpad: Passed. + task_iotypes: Passed. + task_iotypes2: Passed. + task_mem: Passed. + task_noop: Passed. + task_noop2: Passed - CO. + task_omemw2: Passed. + task_omemw3: Passed - CO. + task_port_size: Passed. + task_scope: Passed. + tern1: Passed. + tern2: Passed - CO. + tern4: Passed. + tern5: Passed. + tern6: Passed. + tern7: Passed. + tern9: Passed. + tern10: Passed. + test_bufif0: Passed. + test_bufif1: Passed. + test_disphob: Passed. + test_dispwided: Passed. + test_extended: Passed. +test_mos_strength_reduction: Passed. + test_nmos: Passed. + test_notif0: Passed. + test_notif1: Passed. + test_pmos: Passed. + test_rnmos: Passed. + test_rpmos: Passed. + test_width: Passed. + time1: Passed. + time2: Passed. + time3: Passed. + time4: Passed. + time5: Passed. + time7: Passed. + time8: Passed. + timeform1: Passed. + timeform2: Passed. + timescale1: Passed. + timescale2: Passed. + timescale3: Passed - CE. + tran: Passed. + tranif0: Passed. + tranif1: Passed. + tran-keeper: Passed. + tri0: Passed. + tri0b: Passed. + tri1: Passed. + tri2: Passed. + tri3: Passed. + triand: Passed. + trior: Passed. + types1: Passed. + udp_bufg: Passed. + udp_bufg2: Passed. + udp_bx: Passed. + udp_delay_fail: Passed - CE. + udp_dff: Passed. + udp_dff_std: Passed. + udp_eval_arg: Passed. + udp_jkff: Passed. + udp_real_delay: Passed. + udp_sched: Passed. + udp_x: Passed. + unary_and: Passed. + unary_lnot1: Passed. + unary_lnot2: Passed. + unary_lnot3: Passed. + unary_minus: Passed. + unary_minus1: Passed. + unary_minus2: Passed. + unary_minus3: Passed. + unary_minus4: Passed. + unary_nand: Passed. + unary_nand2: Passed. + unary_nor: Passed. + unary_nor2: Passed. + unary_not: Passed. + unary_or: Passed. + unary_xnor1: Passed. + unary_xnor2: Passed. + unary_xor: Passed. + uncon_drive: Passed. + undef: Passed. + undef_lval_select: Passed. + undef_lval_select2: Passed. + undef_lval_select3a: Passed. + undef_lval_select3b: Passed - CE. + undef_lval_select3c: Passed - CE. + undef_lval_select4a: Passed. + undef_lval_select4b: Passed - CE. + undef_lval_select4c: Passed - CE. + undef_lval_select5: Passed. + undefined_shift: Passed. + urand_r: Passed. + urand_r2: Passed. + urand_r3: Passed. + uwire: Passed. + uwire2: Passed. + uwire_fail: Passed - CE. + vardly: Passed. + varlsfht: Passed. + varlsfht1: Passed. + varlsfht2: Passed. + varrshft: Passed. + varrshft1: Passed. + varrshft2: Passed. + vcd-dup: Passed. + vector: Passed. + verify_two_var_delays: Passed. + vvp_scalar_value: Passed. + wait1: Passed. + wait2: Passed. + wait3: Passed. + warn_opt_sys_tf: Passed - RE. + wildsense: Passed. + wildsense2: Passed. + wireadd1: Passed. + wireeq: Passed. + wirege: Passed. + wireland: Passed. + wirele: Passed. + wiremod1: Passed. + wiresl: Passed. + wiresl2: Passed. + wiresr: Passed. + wiresub1: Passed. + wirexor1: Passed. + writemem-error: Passed. + writemem-invalid: Passed - RE. + writememb1: Passed. + writememb2: Passed. + writememh1: Passed. + writememh2: Passed. + xnor_test: Passed. + z1: Passed. + z2: Passed. + zero_repl: Passed. + zero_repl_fail: Passed - CE. + cmpi: Passed. + analog1: ==> Failed - running iverilog. + analog2: ==> Failed - running iverilog. + br_gh99c: Passed. + cast_int_ams: Passed. + constfunc4_ams: Passed. + scaled_real: Passed. + test_vams_math: Passed. + value_range1: Passed. + value_range2: Passed. + value_range3: Passed - CE. + vams_abs1: Passed. + vams_abs2: Passed. + wreal: Passed. + always4A: Passed - CE. + always4B: Passed - CE. + always_comb: Passed. + always_comb_fail: Passed - CE. + always_comb_fail3: Passed - CE. + always_comb_fail4: Passed - CE. + always_comb_no_sens: Passed. + always_comb_rfunc: Passed. + always_comb_trig: Passed. + always_comb_warn: Passed. + always_ff: Passed. + always_ff_fail: Passed - CE. + always_ff_fail2: Passed - CE. + always_ff_fail3: Passed - CE. + always_ff_fail4: Passed - CE. + always_ff_no_sens: Passed - CE. + always_ff_warn: Passed. + always_ff_warn_sens: Passed. + always_latch: Passed. + always_latch_fail: Passed - CE. + always_latch_fail3: Passed - CE. + always_latch_fail4: Passed - CE. + always_latch_no_sens: Passed - CE. + always_latch_trig: Passed. + always_latch_warn: Passed. + array_size: Passed. + array_string: Passed. + array_unpacked_sysfunct: Passed. + array_packed: Passed. + assign_op_concat: Passed. + assign_op_type: Passed. + bitp1: Passed. + bits: Passed. + bits2: Passed. + br884: Passed. + br917a: Passed. + br917b: Passed. + br917c: Passed. + br917d: Passed. + br921: Passed. + br932a: Passed. + br932b: Passed. + br936: Passed. + br956: Passed. + br959: Passed. + br962: Passed. + br963: Passed. + br973: Passed. + br974a: Passed. + br974b: Passed. + br974c: Passed. + br975: Passed - CE. + br979: Passed. + br991b: Passed - CE. + br1003a: Passed. + br1003b: Passed. + br1003c: Passed. + br1003d: Passed. + br1004: Passed. + br1025: Passed. + br1027b: Passed. + br1027d: Passed. + br1027f: Passed. + br_gh4: Passed. + br_gh4a: Passed. + br_gh72a: Passed. + br_gh72b: Passed. + br_gh72b_fail: Passed - CE. + br_gh104a: Passed. + br_gh104b: Passed. + br_gh105a: Passed. + br_gh105b: Passed. + br_gh112a: Passed. + br_gh112b: Passed. + br_gh112c: Passed. + br_gh112d: Passed. + br_gh112e: Passed. + br_gh112f: Passed. + br_gh129: Passed. + br_gh130a: Passed - CE. + br_gh165: Passed. + br_gh164a: Passed. + br_gh164b: Passed. + br_gh164c: Passed. + br_gh164d: Passed. + br_gh164e: Passed. + br_gh167a: Passed. + br_gh167b: Passed. + br_gh177a: Passed. + br_gh177b: Passed. + br_gh194: Passed. + br_gh219: Passed. + br_gh220: Passed. + br_gh224: Passed. + br_gh226: Passed. + br_gh231: Passed. + br_gh243: Passed. + br_gh265: Passed - CE. + br_gh277b: Passed. + br_gh280: Passed. + br_gh281: Passed. + br_gh281b: Passed. + br_gh289a: Passed. + br_gh289b: Passed. + br_gh289c: Passed. + br_gh289d: Passed. + br_gh337: Passed. + br_gh361: Passed. + br_gh365: Passed. + br_gh366: Passed. + br_gh368: Passed. + br_gh374: Passed. + br_gh386a: Passed. + br_gh386b: Passed. + br_gh386c: Passed - CE. + br_gh388: Passed. + br_gh391: Passed. + br_gh411: Passed. + br_gh418: Passed. + br_gh433: Passed. + br_gh437: Passed. + br_gh440: Passed - CE. + br_gh443: Passed. + br_gh445: Passed. + br_gh461: Passed. + br_gh477: Passed. + br_gh478: Passed. + br_gh498: Passed. + br_gh508a: Passed. + br_gh527: Passed. + br_gh530: Passed - CO. + br_gh540: Passed. + br_gh553: Passed. + br_gh556: Passed. + br_gh568: Passed. + br_ml20171017: Passed. + br_ml20180227: Passed - CE. + br_ml20180309a: Passed. + br_ml20180309b: Passed. + br_ml20181012a: Passed - CE. + br_ml20181012b: Passed - CE. + br_ml20181012c: Passed - CE. + br_ml20181012d: Passed - CE. + br_ml20191221: Passed. + br_mw20200501: Passed. + case_priority: Passed. + case_unique: Passed. + cast_real: Passed. + cfunc_assign_op_mixed: Passed. + cfunc_assign_op_pv: Passed. + cfunc_assign_op_real: Passed. + cfunc_assign_op_vec: Passed. + clkgen_bit: Passed. + clkgen_logic: Passed. + clkgen_net: Passed. + clkgen_reg: Passed. + disable_fork_cmd: Passed. + display_bug: Passed. + edge: Passed. + enum_base_range: Passed. + enum_elem_ranges: Passed. + enum_dims_invalid: Passed - CE. + enum_next: Passed. + enum_ports: Passed. + enum_test1: Passed. + enum_test2: Passed. + enum_test3: Passed - CE. + enum_test4: Passed. + enum_test5: Passed - CE. + enum_test6: Passed - CE. + enum_test7: Passed - CE. + enum_test8: Passed. + enum_value_expr: Passed. + enum_values: Passed. + escaped_macro_name: Passed. + extra_semicolon: Passed. + fileline: Passed. + fileline2: Passed. + final: Passed. + final2: Passed. + first_last_num: Passed. + fork_join_any: Passed. + fork_join_dis: Passed. + fork_join_none: Passed. + fr49: Passed. + func_init_var1: Passed. + func_init_var2: Passed. + func_init_var3: Passed. + function10: Passed - CO. + function11: Passed - CE. + function12: Passed. + genvar_inc_dec: Passed. + ibit_test: Passed. + ibyte_test: Passed. + iint_test: Passed. + ilongint_test: Passed. + implicit_cast1: Passed. + implicit_cast2: Passed. + implicit_cast3: Passed. + implicit_cast4: Passed. + implicit_cast5: Passed. + implicit_cast6: Passed. + implicit_cast7: Passed. + implicit_cast8: Passed. + implicit_cast9: Passed. + implicit_cast10: Passed. + implicit_cast11: Passed. + implicit_cast12: Passed. + implicit_cast13: Passed. + implicit-port1: Passed. + implicit-port2: Passed - CE. + implicit-port3: Passed - CE. + implicit-port4: Passed. + implicit-port5: Passed. + implicit-port6: Passed - CE. + implicit-port7: Passed. + inc_dec_stmt: Passed. + int_param: Passed. + ishortint_test: Passed. + iuint1: Passed. + l_equiv: Passed. + l_equiv_ca: Passed. + l_equiv_const: Passed. + line_directive: Passed. + localparam_query: Passed. + localparam_type2: Passed. + logical_short_circuit: Passed. + logp2: Passed. + mod_inst_pkg: Passed. + named_begin: Passed. + named_begin_fail: Passed - CE. + named_fork: Passed. + named_fork_fail: Passed - CE. + packeda: Passed. + packeda2: Passed. + parameter_type2: Passed. + parpkg_test: Passed. + parpkg_test2: Passed. + parpkg_test3: Passed. + part_sel_port: Passed. + plus_5: Passed. + pr3366114: Passed. + pr3366217a: Passed - CE. + pr3366217b: Passed - CE. + pr3366217c: Passed - CE. + pr3366217d: Passed - CE. + pr3366217e: Passed. + pr3366217f: Passed. + pr3366217g: Passed - CE. + pr3366217h: Passed. + pr3366217i: Passed. + pr3390385: Passed. + pr3390385b: Passed. + pr3390385c: Passed. + pr3390385d: Passed. + pr3462145: Passed. + pr3515542: Passed - CE. + pr3534333: Passed. + pr3576165: Passed. + program2: Passed. + program2b: Passed. + program3: Passed. + program3a: Passed. + program3b: Passed - CE. + program4: Passed. + program5a: Passed - CE. + program5b: Passed - CE. + program_hello: Passed. + program_hello2: Passed - CE. + sbyte_test: Passed. + scalar_vector: Passed. + sf_countbits: Passed. + sf_countbits_fail: Passed - RE. + sf_countones: Passed. + sf_countones_fail: Passed - RE. + sf_isunknown: Passed. + sf_isunknown_fail: Passed - RE. + sf_onehot: Passed. + sf_onehot_fail: Passed - RE. + sf_onehot0: Passed. + sf_onehot0_fail: Passed - RE. + sformatf: Passed. + simple_byte: Passed. + simple_int: Passed. + simple_longint: Passed. + simple_shortint: Passed. + sint_test: Passed. + size_cast: Passed. + size_cast2: Passed. + size_cast3: Passed. + size_cast4: Passed. + size_cast5: Passed. + slongint_test: Passed. + sshortint_test: Passed. + string_events: Passed. + string_index: Passed. + struct1: Passed. + struct2: Passed. + struct3: Passed. + struct3b: Passed. + struct4: Passed. + struct5: Passed. + struct6: Passed. + struct7: Passed. + struct8: Passed. + struct9: Passed. + struct_packed_array: Passed. + struct_packed_array2: Passed. + struct_packed_sysfunct: Passed. + struct_packed_write_read2: Passed. + sv-constants: Passed. + sv_array_assign_pattern2: Passed. + sv_cast_integer: Passed. + sv_cast_integer2: Passed. + sv_cast_string: Passed. + sv_class1: Passed. + sv_class2: Passed. + sv_class3: Passed. + sv_class4: Passed. + sv_class5: Passed. + sv_class6: Passed. + sv_class7: Passed. + sv_class8: Passed. + sv_class9: Passed. + sv_class10: Passed. + sv_class11: Passed. + sv_class12: Passed. + sv_class13: Passed. + sv_class14: Passed. + sv_class15: Passed. + sv_class16: Passed. + sv_class17: Passed. + sv_class18: Passed. + sv_class19: Passed. + sv_class20: Passed. + sv_class21: Passed. + sv_class22: Passed. + sv_class23: Passed. + sv_class24: Passed. + sv_darray1: Passed. + sv_darray2: Passed. + sv_darray3: Passed. + sv_darray4: Passed. + sv_darray5: Passed. + sv_darray5b: Passed. + sv_darray6: Passed. + sv_darray_args1: Passed. + sv_darray_args2: Passed. + sv_darray_args2b: Passed. + sv_darray_args3: Passed. + sv_darray_args4: Passed. + sv_darray_decl_assign: Passed. + sv_darray_function: Passed. + sv_darray_signed: Passed. + sv_darray_word_size: Passed. + sv_default_port_value1: Passed. + sv_default_port_value2: Passed. + sv_default_port_value3: Passed - CE. + sv_end_label: Passed. + sv_end_label_fail: Passed - CE. + sv_end_labels: Passed. + sv_end_labels_bad: Passed - CE. + sv_enum1: Passed. + sv_for_variable: Passed. + sv_foreach1: Passed. + sv_foreach2: Passed. + sv_foreach3: Passed. + sv_foreach4: Passed. + sv_foreach5: Passed. + sv_immediate_assert: Passed. + sv_immediate_assume: Passed. + sv_macro: Passed. + sv_macro2: Passed. + sv_macro3a: Passed. + sv_macro3b: Passed. + sv_new_array_error: Passed - CE. + sv_package: Passed. + sv_package2: Passed. + sv_package3: Passed. + sv_package4: Passed. + sv_package5: Passed. + sv_packed_port1: Passed. + sv_packed_port2: Passed. + sv_param_port_list: Passed. + sv_pkg_class: Passed. + sv_port_default1: Passed. + sv_port_default2: Passed. + sv_port_default3: Passed. + sv_port_default4: Passed. + sv_port_default5: Passed. + sv_port_default6: Passed. + sv_port_default7: Passed. + sv_port_default8: Passed. + sv_port_default9: Passed. + sv_port_default10: Passed. + sv_port_default11: Passed. + sv_port_default12: Passed. + sv_port_default13: Passed - CE. + sv_port_default14: Passed - CE. + sv_queue1: Passed. + sv_queue2: Passed. + sv_queue3: Passed. + sv_queue_real: Passed. + sv_queue_real_bounded: Passed. + sv_queue_real_fail: Passed - CE. + sv_queue_string: Passed. + sv_queue_string_bounded: Passed. + sv_queue_string_fail: Passed - CE. + sv_queue_vec: Passed. + sv_queue_vec_bounded: Passed. + sv_queue_vec_fail: Passed - CE. + sv_root_class: Passed. + sv_root_func: Passed. + sv_root_task: Passed. + sv_string1: Passed. + sv_string2: Passed. + sv_string3: Passed. + sv_string4: Passed. + sv_string5: Passed. + sv_timeunit_prec1: Passed. + sv_timeunit_prec2: Passed. + sv_timeunit_prec3a: Passed. + sv_timeunit_prec3b: Passed. + sv_timeunit_prec3c: Passed. + sv_timeunit_prec3d: Passed. + sv_timeunit_prec4a: Passed. + sv_timeunit_prec4b: Passed. + sv_timeunit_prec_fail1: Passed - CE. + sv_timeunit_prec_fail2: Passed - CE. + sv_typedef_scope: Passed. + sv_union1: Passed. + sv_union1b: Passed. + sv_union2: Passed. + sv_union2b: Passed. + sv_union3: Passed. + sv_union3b: Passed. + sv_union4b: Passed. + sv_unit1b: Passed. + sv_unit1c: Passed. + sv_unit2b: Passed. + sv_unit3b: Passed. + sv_unit4b: Passed. + sv_unpacked_port: Passed. + sv_unpacked_port2: Passed. + sv_unpacked_wire: Passed. + sv_unpacked_wire2: Passed. + sv_uwire1: Passed. + sv_uwire2: Passed. + sv_uwire3: Passed. + sv_uwire4: Passed. + sv_var_init1: Passed. + sv_var_init2: Passed. + sv_wildcard_import1: Passed. + sv_wildcard_import2: Passed. + sv_wildcard_import3: Passed. + sv_wildcard_import4: Passed - CE. + sv_wildcard_import5: Passed - CE. + sv_wildcard_import6: Passed. + sv_wildcard_import7: Passed. + sys_func_as_task: Passed. + task_init_assign: Passed. + task_init_var1: Passed. + task_init_var2: Passed. + task_init_var3: Passed. + task_scope2: Passed. + test_inc_dec: Passed. + test_tliteral: Passed. + timeliteral: Passed. + two_state_display: Passed. + ubyte_test: Passed. + uint_test: Passed. + ulongint_test: Passed. + undef_lval_select_SV: Passed. + unp_array_typedef: Passed. + packed_dims_invalid_class: Passed - CE. + packed_dims_invalid_module: Passed - CE. + ushortint_test: Passed. + vvp_recv_vec4_pv: Passed. + wait_fork: Passed. + sf1289: Passed. + wild_cmp_const: Passed. + wild_cmp_net: Passed. + wild_cmp_var: Passed. + wild_cmp_err: Passed - CE. + wild_cmp_err2: Passed - CE. + gh161a: Passed. + gh161b: Passed. + pull371b: Passed. + br_gh175: Passed. + br_gh307: Passed. + br_gh383a: Passed. + br_gh383b: Passed. + br_gh383c: Passed. + br_gh390a: Passed - CE. + br_gh390b: Passed. + br_gh412: Passed. + br_gh414: Passed. + br_gh436: Passed. + br_gh451: Passed. + br_gh453: Passed. + br_gh460: Passed. + br942: Passed. + br943_944: Passed. + br985: Passed. + br986: Passed. + br987: Passed. + ivlh_event: Passed. + ivlh_rising_falling: Passed. + ivlh_textio: Passed. + test_dec2to4: Passed. + test_enumsystem: Passed. + test_forgen: Passed. + test_gxor: Passed. + test_mux2to1: Passed. + test_signal_init_assign: Passed. + test_system: Passed. + test_timebase: Passed. + test_varray1: Passed. + test_when_else: Passed. + test_work14: Passed. + vhdl_and104_stdlogic: Passed. + vhdl_and23_bit: Passed. + vhdl_and_gate: Passed. + vhdl_andg_bit: Passed. + vhdl_andg_stdlogic: Passed. + vhdl_array_of_array: Passed. + vhdl_case_multi: Passed. + vhdl_boolean: Passed. + vhdl_concat: Passed. + vhdl_concat_func: Passed. + vhdl_concurrent_assert: Passed. + vhdl_const_package: Passed. + vhdl_const_record: Passed. + vhdl_const_array: Passed. + vhdl_delay_assign: Passed. + vhdl_elab_range: Passed. + vhdl_eval_cond: Passed. + vhdl_expr1: Passed. + vhdl_generic_eval: Passed. + vhdl_fa4_test1: Passed. + vhdl_fa4_test2: Passed. + vhdl_fa4_test3: Passed. + vhdl_fa4_test4: Passed. + vhdl_file_open: Passed. + vhdl_generic_default: Passed. + vhdl_init: Passed. + vhdl_image_attr: Passed. + vhdl_inout: Passed. + vhdl_labeled_assign: Passed. + vhdl_lfcr: Passed. + vhdl_logic: Passed. + vhdl_loop: Passed. + vhdl_multidim_array: ==> Failed - running iverilog. + vhdl_nand104_stdlogic: Passed. + vhdl_nand23_bit: Passed. + vhdl_nandg_bit: Passed. + vhdl_nandg_stdlogic: Passed. + vhdl_nor104_stdlogic: Passed. + vhdl_nor23_bit: Passed. + vhdl_norg_bit: Passed. + vhdl_norg_stdlogic: Passed. + vhdl_not104_stdlogic: Passed. + vhdl_not23_bit: Passed. + vhdl_notfunc_stdlogic: Passed. + vhdl_notg_bit: Passed. + vhdl_notg_stdlogic: Passed. + vhdl_now: Passed. + vhdl_or104_stdlogic: Passed. + vhdl_or23_bit: Passed. + vhdl_org_bit: Passed. + vhdl_org_stdlogic: Passed. + vhdl_pow_rem: Passed. + vhdl_prefix_array: Passed. + vhdl_procedure: Passed. + vhdl_process_scope: Passed. + vhdl_rand23_bit: Passed. + vhdl_range: Passed. + vhdl_range_func: Passed. + vhdl_real: Passed. + vhdl_record_elab: Passed. + vhdl_reduce: Passed. + vhdl_report: Passed. + vhdl_resize: Passed. + vhdl_rtoi: Passed. + vhdl_sa1_test1: Passed. + vhdl_sa1_test2: Passed. + vhdl_sa1_test3: Passed. + vhdl_sadd23_bit: Passed. + vhdl_sadd23_stdlogic: Passed. + vhdl_sdiv23_bit: Passed. + vhdl_sdiv23_stdlogic: Passed. + vhdl_selected: Passed. + vhdl_shift: Passed. + vhdl_signals: Passed. + vhdl_smul23_bit: Passed. + vhdl_smul23_stdlogic: Passed. + vhdl_ssub23_bit: Passed. + vhdl_ssub23_stdlogic: Passed. + vhdl_struct_array: Passed. + vhdl_subtypes: Passed. + vhdl_subprogram: Passed. + vhdl_string: Passed. + vhdl_string_lim: Passed. + vhdl_test1: Passed. + vhdl_test2: Passed. + vhdl_test3: Passed. + vhdl_test4: Passed. + vhdl_test5: Passed. + vhdl_test6: Passed. + vhdl_test7: Passed. + vhdl_test8: Passed. + vhdl_test9: Passed. + vhdl_textio_write: Passed. + vhdl_textio_read: Passed. + vhdl_time: Passed. + vhdl_to_integer: Passed. + vhdl_uadd23_bit: Passed. + vhdl_uadd23_stdlogic: Passed. + vhdl_udiv23_bit: Passed. + vhdl_udiv23_stdlogic: Passed. + vhdl_umul23_bit: Passed. + vhdl_umul23_stdlogic: Passed. + vhdl_unary_minus: Passed. + vhdl_unbounded: Passed. + vhdl_unbounded_func: Passed. + vhdl_usub23_bit: Passed. + vhdl_usub23_stdlogic: Passed. + vhdl_var_init: Passed. + vhdl_wait: Passed. + vhdl_while: Passed. + vhdl_xnor104_stdlogic: Passed. + vhdl_xnor23_bit: Passed. + vhdl_xnorg_bit: Passed. + vhdl_xnorg_stdlogic: Passed. + vhdl_xor23_bit: Passed. + vhdl_xorg_bit: Passed. + vhdl_xorg_stdlogic: Passed. + work7: Passed. + work7b: Passed. + basicexpr: Passed. + basicexpr2: Passed. + basicexpr3: Passed. + basicexpr4: Passed. + basiclatch: Passed. + basicreg: Passed. + basicstate: Passed. + basicstate2: Passed. + blocksynth1: Passed. + blocksynth2: Passed. + blocksynth3: Passed. + br993a: Passed. + br993b: Passed. + br994: Passed. + br995: Passed - CE. + br_gh99v: Passed. + br_gh99w: Passed. + br_gh99x: Passed. + br_gh115: Passed. + br_gh306a: Passed - CE. + br_gh306b: Passed - CE. + case3: Passed. + case4: Passed. + case5: Passed. + case5-syn-fail: Passed - CE. + case6: Passed. + case7: Passed. + case_wo_default: Passed. + casesynth1: Passed. + casesynth2: Passed. + casesynth3: Passed. + casesynth4: Passed. + casesynth5: Passed. + casesynth6: Passed. + casesynth7: Passed. + casesynth8: Passed - CE. + casesynth9: Passed. + condit1: Passed. + conditsynth1: Passed. + conditsynth2: Passed. + conditsynth3: Passed. + dffsynth2: Passed. + dffsynth3: Passed. + dffsynth4: Passed. + dffsynth5: Passed. + dffsynth6: Passed. + dffsynth7: Passed. + dffsynth8: Passed - CE. + dffsynth9: Passed. + dffsynth10: Passed. + dffsynth11: Passed. + ff_dual_enable: Passed. + for_loop_synth: Passed. + for_loop_synth2: Passed. + if_part_no_else: Passed. + if_part_no_else2: Passed. + inside_synth: Passed. + inside_synth2: Passed. + inside_synth3: Passed. + land5: Passed. + lcatsynth: Passed. + memsynth4: Passed. + memsynth8: Passed. + multireg: Passed. + not_a_latch1: Passed. + not_a_latch2: Passed. + partselsynth: Passed. + pr519: Passed. + pr685: Passed. + shiftl: Passed. + sqrt32synth: Passed. + ssetclr1: Passed. + ssetclr2: Passed. + ssetclr3: Passed. + synth_if_no_else: Passed. + ufuncsynth1: Passed. +============================================================================ +Test results: + Total=2559, Passed=2553, Failed=3, Not Implemented=0, Expected Fail=3 diff --git a/ivtest/regression_report-fsv.txt b/ivtest/regression_report-fsv.txt new file mode 100644 index 000000000..48521a7c0 --- /dev/null +++ b/ivtest/regression_report-fsv.txt @@ -0,0 +1,2564 @@ +Running compiler/VVP tests for Icarus Verilog version: 12 (force SV). +---------------------------------------------------------------------------- + br1015a: ==> Failed - running iverilog. + br1027a: Passed. + br1027c: Passed. + br1027e: Passed. + br_gh25a: Passed. + br_gh25b: Passed. + br_gh567: Passed. + check_constant_3: Passed. + function4: Passed. + pr1963962: Passed. + pr3015421: Passed - CE. + resetall: Passed. + scope2b: Passed. + sys_func_task_error: Passed - RE. + br995: Passed. + br_gh306a: Passed. + br_gh306b: Passed. + case5-syn-fail: Passed. + casesynth7: Passed. + casesynth8: Passed. + dffsynth: Passed. + dffsynth8: Passed. + memsynth1: Passed. + memsynth2: Passed. + memsynth3: Passed. + memsynth5: Passed. + memsynth6: Passed. + memsynth7: Passed. + memsynth9: Passed. + mix_reset: Passed. + pr2590274a: Not Implemented. + pr2590274b: Not Implemented. + pr2590274c: Not Implemented. + array_lval_select3a: ==> Failed - running iverilog. + br605a: ==> Failed - output does not match gold file. + br605b: ==> Failed - output does not match gold file. + br971: ==> Failed - output does not match gold file. + br1005: ==> Failed - running iverilog. + br1015b: ==> Failed - running iverilog. + br_gh130b: ==> Failed - running iverilog. + br_gh386d: ==> Failed - running iverilog. + br_ml20150315b: ==> Failed - running iverilog. + sv_deferred_assert1: ==> Failed - running iverilog. + sv_deferred_assert2: ==> Failed - running iverilog. + sv_deferred_assume1: ==> Failed - running iverilog. + sv_deferred_assume2: ==> Failed - running iverilog. + case1: Passed. + case2: Passed. + casex_synth: Passed. + pr903: Passed. + pr1388974: Passed. + br_gh13a: Passed. + param-width: Passed. + br_gh383d: Passed. + ca_time_real: Passed. + delayed_sfunc: Passed. + localparam_type: Passed. + parameter_type: Passed. + pr1701890: Passed. + pr1864110a: Passed. + pr1864110b: Passed. + pr1864115: Passed. + macro_str_esc: Passed. + macro_with_args: Passed. + mcl1: Passed. + pr622: Passed. + pr639: Passed. + pr1741212: Passed. + pr1912112: Passed. + pr1925360: Passed. + repeat1: Passed. + pr2002443: Passed - CO. + constfunc6_ams: Passed. + non-polymorphic-abs: Passed. + pr3270320_ams: Passed - CE. + test_va_math: Passed. + va_math: Passed. + abstime: Passed. + bitsel: Passed. + bitsel10: Passed. + bitsel2: Passed. + bitsel3: Passed. + bitsel4: Passed. + bitsel5: Passed. + bitsel6: Passed. + bitsel7: Passed. + bitsel8: Passed. + bitsel9: Passed. + bitwidth3: Passed. + clog2: Passed. + clog2-signal: Passed. + param_vec: Passed. + param_vec2: Passed. + pr498: Passed. + pr721: Passed. + pr809: Passed. + pr809b: Passed. + pr979: Passed. + pr1000: Passed. + pr1609611: Passed. + pr1750870: Passed. + pr1765789: Passed. + pr1771903: Passed. + pr1793749: Passed. + pr1793749b: Passed. + pr1861212b: Passed. + pr1864110c: Passed. + pr2806449: Passed. + pr2877555: Passed. + real4: Passed. + realtobits: Passed. + specparam1: Passed. + specparam2: Passed. + tern3: Passed. + v2005_math: Passed. + deposit: Passed. + deposit_wire: Passed. + sysargs: Passed. + fatal_et_al: Passed. + fatal_et_al2: Passed - RE. + plus_arg_string: Passed. + fileio: Passed. + pr1494799: Passed. + pr2428890c: Passed. + sv_cast_darray: Passed. + br978: Passed. + br_ml20150424: Passed. + pr2509349a: Passed. + pr2509349b: Passed. + simparam: Passed. + blocking_repeat_ec: Passed. + ca_time_smtm: Passed. + nb_array_pv: Passed. + nb_ec_array: Passed. + nb_ec_array_pv: Passed. + nb_ec_pv: Passed. + nb_ec_pv2: Passed. + nb_ec_real: Passed. + nb_ec_vector: Passed. + pr2486350: Passed. + pr534: Passed. + stime: Passed. + swrite: Passed. + time6: Passed. + time6b: Passed. + time6c: Passed. + concat1: Passed. + concat2: Passed. + constconcat1: Passed. + constconcat2: Passed. + rptconcat2: Passed. + sdw_lvalconcat2: Passed. + bool1: Passed. + compare_bool_reg: Passed. + constfunc8: Passed. + binary_nand: Passed. + binary_nor: Passed. + pr1528093: Passed. + br_gh456: Passed. + ca_64delay: Passed. + ca_var_delay: Passed. + cast_real_signed: Passed. + cast_real_unsigned: Passed. + pr1861212c: Passed. + pr1873372: Passed. + pr1880003: Passed. + pr1898293: Passed. + pr2123158: Passed. + pr2453002b: Passed. + pr2456943: Passed. + pr2715748: Passed. + pr2806474: Passed. + pr2976242: Passed. + pr2976242b: Passed. + pr2976242c: Passed - CE. + real8: Passed. + real_array: Passed. + real_array_nb: Passed. + real_concat_invalid1: Passed - CE. + real_mod_in_ca: Passed. + real_op_fail: Passed - CE. + real_pulse_clean: Passed. + real_pwr_in_ca: Passed. + real_select_invalid: Passed - CE. + real_wire_array: Passed. + real_wire_force_rel: Passed. + tern8: Passed. + br_gh99e: Passed. + pull371: Passed. + sv-2val-nets: Passed. + pr2476430: Passed. + eofmt_percent: Passed. + br_gh377: Passed. + cmdline_parm1: Passed. + array_dump: Passed. + pr2859628: Passed. + big_int: Passed. + ca_pow_signed: Passed. + urand: Passed. + race: Passed. + automatic_error4: Passed - CE. + pr1909940: Passed. + pr1909940b: Passed. + unnamed_generate_block: Passed. + br_gh497b: Passed - CE. + br_gh497d: Passed - CE. + br_gh497f: Passed - CE. + addsr: Passed. + addwide: Passed. + always3.1.1A: Passed - CE. + always3.1.1B: Passed - CE. + always3.1.1C: Passed. + always3.1.1D: Passed. + always3.1.1E: Passed. + always3.1.1F: Passed. + always3.1.1G: Passed. + always3.1.1H: Passed. + always3.1.1I: Passed. + always3.1.1J: Passed. + always3.1.1K: Passed. + always3.1.2A: Passed - CE. + always3.1.2B: Passed - CE. + always3.1.2C: Passed - CE. + always3.1.2D: Passed - CE. + always3.1.2E: Passed - CE. + always3.1.2F: Passed - CE. + always3.1.2G: Passed - CE. + always3.1.2H: Passed - CE. + always3.1.2I: Passed - CE. + always3.1.3A: Passed - CE. + always3.1.3B: Passed - CE. + always3.1.3B2: Passed. + always3.1.3C: Passed - CE. + always3.1.3D: Passed - CE. + always3.1.3D2: Passed. + always3.1.3E: Passed - CE. + always3.1.3E2: Passed. + always3.1.3F: Passed - CE. + always3.1.3F2: Passed. + always3.1.3G: Passed - CE. + always3.1.3H: Passed - CE. + always3.1.3J: Passed - CE. + always3.1.4A: Passed. + always3.1.4B: Passed. + always3.1.4C: Passed. + always3.1.4D: Passed. + always3.1.4E: Passed. + always3.1.4F: Passed. + always3.1.4G: Passed. + always3.1.4H: Passed. + always3.1.4I: Passed. + always3.1.5A: Passed. + always3.1.5B: Passed. + always3.1.5C: Passed. + always3.1.5D: Passed. + always3.1.5E: Passed. + always3.1.5F: Passed. + always3.1.6A: Passed. + always3.1.6B: Passed. + always3.1.6C: Passed. + always3.1.6D: Passed. + always3.1.7A: Passed. + always3.1.7B: Passed. + always3.1.7C: Passed. + always3.1.7D: Passed. + always3.1.8A: Passed. + always3.1.9A: Passed - CE. + always3.1.9B: Passed - CE. + always3.1.9C: Passed. + always3.1.9D: Passed. + always3.1.10A: Passed - CE. + always3.1.11A: Passed. + always3.1.11B: Passed. + always3.1.12A: Passed. + always3.1.12B: Passed. + always3.1.12C: Passed. + always_star_array_lval: Passed. + andnot1: Passed. + arith-unknown: Passed. + array4: Passed. + array5: Passed - CE. + array6: Passed. + array7: Passed. + array_lval_select1: Passed. + array_lval_select2: Passed. + array_lval_select3b: Passed - CE. + array_lval_select3c: Passed. + array_lval_select4a: Passed. + array_lval_select4b: Passed - CE. + array_lval_select5: Passed. + array_lval_select6: Passed. + array_packed_2d: Passed. + array_select: Passed. + array_select_a: Passed. + array_word_check: Passed. + array_word_width: Passed. + array_word_width2: Passed. + assign3.2A: Passed. + assign3.2B: Passed. + assign3.2C: Passed. + assign3.2D: Passed. + assign3.2E: Passed. + assign_add: Passed. + assign_deassign_pv: Passed. + assign_delay: Passed. + assign_deq: Passed. + assign_ge: Passed. + assign_le: Passed. + assign_mem1: Passed. + assign_mem2: Passed. + assign_nb1: Passed. + assign_nb2: Passed. + assign_neq: Passed. + attrib: Passed. + attrib01_module: Passed. + attrib02_port_decl: Passed. + attrib03_parameter: Passed. + attrib04_net_var: Passed. + attrib05_port_conn: Passed. + attrib06_operator_suffix: Passed. + attrib07_func_call: Passed. + attrib08_mod_inst: Passed. + attrib09_case: Passed. + automatic_error1: Passed - CE. + automatic_error2: Passed - CE. + automatic_error3: Passed - CE. + automatic_error5: Passed - CE. + automatic_error6: Passed - CE. + automatic_error7: Passed - CE. + automatic_error8: Passed - CE. + automatic_error9: Passed - CE. + automatic_error10: Passed - CE. + automatic_error11: Passed - RE. + automatic_error12: Passed - RE. + automatic_error13: Passed - RE. + automatic_events: Passed. + automatic_events2: Passed. + automatic_events3: Passed. + automatic_task: Passed. + automatic_task2: Passed. + automatic_task3: Passed. + bitwidth: Passed. + bitwidth2: Passed. + blankport: Passed. + block_only_with_var_def: Passed. + bnot: Passed. + br916a: Passed. + br916b: Passed. + br918a: Passed. + br918b: Passed. + br918c: Passed. + br918d: Passed. + br919: Passed. + br924: Passed - CE. + br930: Passed - CO. + br931: Passed. + br935: Passed. + br937: Passed. + br946: Passed. + br947: Passed. + br948: Passed. + br955: Passed. + br960a: Passed. + br960b: Passed. + br960c: Passed. + br960d: Passed. + br961: Passed. + br961a: Passed - CE. + br965: Passed. + br967: Passed. + br968: Passed. + br972: Passed. + br977: Passed. + br982: Passed - CE. + br982a: Passed - CE. + br982b: Passed - CE. + br988: Passed. + br990: Passed. + br991a: Passed. + br999: Passed. + br1000: Passed. + br1001: Passed. + br1006: Passed. + br1007: Passed. + br1008: Passed. + br1019: Passed. + br1027: Passed. + br1029a: Passed. + br1029b: Passed. + br1029c: Passed - CE. + br_gh6: Passed. + br_gh7: Passed. + br_gh8: Passed. + br_gh9: Passed. + br_gh11: Passed - CO. + br_gh12: Passed. + br_gh13: Passed. + br_gh14: Passed. + br_gh15: Passed. + br_gh18: Passed. + br_gh19: Passed. + br_gh19a: Passed. + br_gh19b: Passed. + br_gh22: Passed. + br_gh26: Passed - CE. + br_gh28: Passed. + br_gh30: Passed. + br_gh33: Passed. + br_gh37: Passed. + br_gh60a: Passed - CE. + br_gh62: Passed - CE. + br_gh79: Passed - CE. + br_gh99a: Passed. + br_gh99b: Passed. + br_gh99d: Passed. + br_gh99f: Passed. + br_gh99g: Passed. + br_gh99h: Passed. + br_gh99i: Passed. + br_gh99j: Passed. + br_gh99k: Passed. + br_gh99l: Passed. + br_gh99m: Passed. + br_gh99o: Passed. + br_gh99p: Passed. + br_gh99q: Passed. + br_gh99r: Passed. + br_gh99s: Passed. + br_gh99t: Passed. + br_gh99u: Passed. + br_gh103: Passed. + br_gh127a: Passed. + br_gh127b: Passed. + br_gh127c: Passed. + br_gh127d: Passed. + br_gh127e: Passed. + br_gh127f: Passed. + br_gh142: Passed - CE. + br_gh152: Passed - CE. + br_gh157: Passed. + br_gh162: Passed. + br_gh163: Passed - CE. + br_gh198: Passed. + br_gh199a: Passed. + br_gh199b: Passed. + br_gh209: Passed. + br_gh230: Passed - RE. + br_gh244a: Passed. + br_gh244b: Passed. + br_gh277a: Passed. + br_gh283a: Passed. + br_gh283b: Passed. + br_gh283c: Passed. + br_gh309: Passed. + br_gh315: Passed. + br_gh316a: Passed. + br_gh316b: Passed. + br_gh316c: Passed. + br_gh330: Passed. + br_gh345: Passed. + br_gh356a: Passed. + br_gh356b: Passed. + br_gh435: Passed. + br_gh484: Passed. + br_gh497a: Passed. + br_gh497c: Passed. + br_gh497e: Passed. + br_gh508b: Passed. + br_gh515: Passed. + br_gh531: Passed. + br_gh533: Passed - CE. + br_ml20150315: Passed. + br_ml20150321: Passed - CE. + br_ml20150606: Passed. + br_mw20171108: Passed. + br_ml20190806a: Passed. + br_ml20190806b: Passed. + br_ml20190814: Passed. + bufif: Passed. + busbug: Passed. + ca_force: Passed. + ca_func: Passed. + ca_mult: Passed. + ca_pow_synth: Passed. + ca_pow_unsigned: Passed. + ca_real_logical: Passed. + ca_time: Passed. + case3.8A: Passed. + case3.8B: Passed. + case3.8C: Passed. + case3.8D: Passed. + casex3.9A: Passed. + casex3.9B: Passed. + casex3.9C: Passed. + casex3.9D: Passed. + casex3.9E: Passed. + casez3.10A: Passed. + casez3.10B: Passed. + casez3.10C: Passed. + casez3.10D: Passed. + casez3.10E: Passed. + cast_int: Passed. + check_constant_1: Passed - CE. + check_constant_2: Passed - CE. + check_constant_4: Passed - CE. + check_constant_5: Passed - CE. + check_constant_6: Passed - CE. + check_constant_7: Passed - CE. + check_constant_8: Passed - CE. + check_constant_9: Passed - CE. + check_constant_10: Passed - CE. + check_constant_11: Passed - CE. + check_constant_12: Passed - CE. + check_constant_13: Passed - CE. + check_constant_14: Passed - CE. + check_constant_15: Passed - CE. + check_constant_16: Passed - CE. + check_constant_17: Passed - CE. + check_constant_18: Passed - CE. + check_constant_19: Passed - CE. + check_constant_20: Passed - CE. + cmos: Passed. + comment1: Passed - CE. + comp1000: Passed. + comp1001: Passed. + comp1001_fail3: Passed. + comp1001_fail4: Passed. + comp1001_fail5: Passed. + complex_lidx: Passed. + con_tri: Passed. + concat3: Passed. + concat4: Passed. + concat_zero_wid_fail: Passed - CE. + concat_zero_wid_fail2: Passed. + cond_band: Passed. + cond_wide: Passed. + cond_wide2: Passed. + const: Passed. + const2: Passed. + const3: Passed. + const4: Passed. + constadd: Passed. + constadd2: Passed. + constadd3: Passed. + constfunc1: Passed. + constfunc2: Passed. + constfunc3: Passed. + constfunc4: Passed. + constfunc5: Passed. + constfunc6: Passed. + constfunc7: Passed. + constfunc9: Passed. + constfunc10: Passed. + constfunc11: Passed. + constfunc12: Passed. + constfunc13: Passed. + constfunc14: Passed. + constfunc15: Passed. + constmult: Passed. + consttern: Passed. + contrib8.1: Passed. + contrib8.2: Passed. + contrib8.3: Passed - CE. + contrib8.4: Passed. + contrib8.5: Passed. + countdrivers1: Passed. + countdrivers2: Passed. + countdrivers3: Passed. + countdrivers4: Passed. + countdrivers5: Passed. + cprop: Passed. + credence20041209: Passed. + dangling_port: Passed. + dcomp1: Passed. + deassign3.4A: Passed. + decl_assign1: Passed. + def_nettype: Passed. + def_nettype_none: Passed - CE. + define1: Passed. + defparam: Passed. + defparam2: Passed. + defparam3: Passed. + defparam3.5: Passed. + defparam4: Passed. + delay: Passed. + delay2: Passed. + delay3: Passed. + delay4: Passed. + delay5: Passed. + delay_assign_nb: Passed. + delay_assign_nb2: Passed. + delay_var: Passed. + delayed_comp_reduct: Passed. + dff1: Passed. + disable3.6A: Passed. + disable3.6B: Passed. + disable_cleanup: Passed. + disable_fork: Passed. + disblock: Passed. + disblock2: Passed. + disp_dec: Passed. + disp_dec2: Passed. + disp_leading_z: Passed. + disp_parm: Passed. + disp_part: Passed. + div16: Passed. + dotinid: Passed. + drive_strength: Passed. + drive_strength1: Passed. + drive_strength2: Passed. + drive_strength3: Passed. + dummy7: Passed. + dump_memword: Passed. + dumpvars: Passed. + eeq: Passed. + else1: Passed. + else2: Passed. + else3: Passed. + elsif_test: Passed. + eq: Passed. + escape1: Passed. + escape2a: Passed - CO. + escape2b: Passed - CO. + escape2c: Passed - CO. + escape3: Passed. + escape4: Passed. + escape4b: Passed. + event2: Passed. + event3: Passed. + event3.15: Passed. + event_array: Passed - CE. + event_list: Passed. + event_list2: Passed. + event_list3: Passed. + extend: Passed. + fdisplay1: Passed. + fdisplay2: Passed. + fdisplay3: Passed - RE. + fdisplay_fail_fd: Passed. + fdisplay_fail_mcd: Passed. + fifo: Passed. + fopen1: Passed. + fopen2: Passed. + for3.16A: Passed. + force1: Passed. + force2: Passed. + force3.17A: Passed. + force3.17B: Passed. + force3.17C: Passed. + force_lval_part: Passed. + force_release_reg_pv: Passed. + force_release_wire8_pv: Passed. + force_release_wire_pv: Passed. + fork1: Passed. + fork3.19A: Passed. + fork3.19B: Passed. + format: Passed. + fr47: Passed. + fread: Passed. + fread-error: Passed - RE. + fscanf_u: Passed. + fscanf_u_warn: Passed. + fscanf_z: Passed. + fscanf_z_warn: Passed. + function1: Passed. + function2: Passed. + function3: Passed. + function3.11B: Passed. + function3.11C: Passed. + function3.11D: Passed. + function3.11F: Passed. + function5: Passed - CO. + function6: Passed. + function7: Passed. + function8: Passed. + function9: Passed. + function_exp: Passed. + ga_and: Passed. + ga_mod: Passed. + ga_mod1: Passed. + ga_mod2: Passed. + ga_nand: Passed. + ga_nor: Passed. + ga_or: Passed. + ga_xnor: Passed. + ga_xor: Passed. + galan: Passed. + gate_connect1: Passed. + gate_connect2: Passed - CE. + gen_case_opt1: Passed. + gen_case_opt2: Passed. + gen_case_opt3: Passed. + gencrc: Passed. + generate_case: Passed. + generate_case2: Passed. + generate_case3: Passed. + generate_multi_loop: Passed. + genloop: Passed. + genvar_scopes: Passed. + hello1: Passed. + hier_ref_error: Passed - CE. + hierspace: Passed. + idiv1: Passed. + idiv2: Passed. + idiv3: Passed. + ifdef1: Passed. + ifdef2: Passed. + ifdef3: Passed. + ifdef4: Passed. + ifdef_fail: Passed - CE. + include1: Passed. + include2: Passed. + include3: Passed. + indef_width_concat: Passed - CE. + initmod: Passed. + initmod2: Passed. + inout: Passed. + inout2: Passed. + inout3: Passed. + inout4: Passed. + int_not_signext: Passed. + integer1lt: Passed. + integer2le: Passed. + integer3gt: Passed. + integer4ge: Passed. + integer5: Passed. + itor_rtoi: Passed. + land2: Passed. + land3: Passed. + land4: Passed. + landor1: Passed. + ldelay1: Passed. + ldelay2: Passed. + ldelay3: Passed. + ldelay4: Passed. + ldelay5: Passed. + lh_catadd: Passed. + lh_memcat: Passed. + lh_memcat2: Passed. + lh_memcat3: Passed. + lh_varindx: Passed. + lh_varindx2: Passed. + lh_varindx4: Passed. + lh_varindx5: Passed. + long_div: Passed. + macro2: Passed. + macro_redefinition: Passed. + macro_replacement: Passed. + macsub: Passed. + mangle: Passed. + mangle_1: Passed. + many_drivers: Passed. + mcl2: Passed. + mem1: Passed. + mem2port: Passed. + memassign: Passed. + memidx: Passed. + memidxrng: Passed. + meminit: Passed. + meminit2: Passed. + memport_bs: Passed. + memref: Passed. + mhead_task: Passed. + mixed_type_div_mod: Passed. + mixed_width_case: Passed. + modparam: Passed. + module3.12A: Passed. + module3.12B: Passed. + modulus: Passed. + modulus2: Passed. + monitor: Passed. + monitor2: Passed. + monitor3: Passed. + mult1: Passed. + mult16: Passed. + mult2: Passed. + multi_bit_strength: Passed. + multi_driver_delay: Passed. + multiply_large: Passed. + muxtest: Passed. + named_event_no_edges: Passed - CE. + nb_assign: Passed. + nb_delay: Passed. + nblkorder: Passed. + negative_genvar: Passed. + negvalue: Passed. + neq1: Passed. + nested_func: Passed. + nested_impl_event1: Passed. + nested_impl_event2: Passed. + no_if_statement: Passed - CE. + no_timescale_in_module: Passed - CE. + npmos: Passed. + npmos2: Passed. + onehot: Passed. + p_monta: Passed. + par_mismatch: Passed - CE. + param-extend: Passed. + param_add: Passed. + param_and: Passed. + param_and2: Passed. + param_band: Passed. + param_binv: Passed. + param_bor: Passed. + param_concat: Passed. + param_eq3: Passed. + param_expr: Passed. + param_mod: Passed. + param_select: Passed. + param_select2: Passed. + param_select3: Passed. + param_string: Passed. + param_tern: Passed. + param_tern2: Passed. + param_test1: Passed. + param_test2: Passed. + param_test3: Passed. + param_test4: Passed. + param_times: Passed. + patch1268: Passed. + pca1: Passed. + pic: Passed. + port-test2: Passed. + port-test3: Passed - CE. + port-test4a: Passed - CE. + port-test4b: Passed - CE. + port-test5: Passed. + port-test6: Passed. + port-test7: Passed. + posedge: Passed. + pow-ca: Passed. + pow-const: Passed. + pow-proc: Passed. + pow_ca_signed: Passed. + pow_ca_unsigned: Passed. + pow_reg_signed: Passed. + pow_reg_unsigned: Passed. + pow_signed: Passed. + pow_unsigned: Passed. + pr136: Passed. + pr142: Passed. + pr183: Passed - CO. + pr224: Passed. + pr224a: Passed. + pr243: Passed. + pr245: Passed. + pr245_std: Passed. + pr273: Passed. + pr298: Passed. + pr304: Passed. + pr307: Passed. + pr307a: Passed. + pr312: Passed. + pr338: Passed - CO. + pr355: Passed. + pr377: Passed. + pr434: Passed. + pr445: Passed. + pr478: Passed. + pr487: Passed. + pr492: Passed. + pr508: Passed. + pr509: Passed. + pr509b: Passed. + pr511: Passed. + pr513: Passed. + pr522: Passed. + pr524: Passed. + pr527: Passed. + pr528: Passed. + pr528b: Passed. + pr529: Passed. + pr530a: Passed. + pr530b: Passed. + pr530c: Passed. + pr531a: Passed. + pr531b: Passed. + pr532: Passed. + pr532b: Passed. + pr533: Passed. + pr538: Passed. + pr540: Passed. + pr540b: Passed. + pr540c: Passed. + pr541: Passed. + pr542: Passed. + pr544: Passed. + pr547: Passed. + pr556: Passed. + pr564: Passed. + pr569: Passed. + pr572: Passed. + pr572b: Passed. + pr578: Passed. + pr584: Passed. + pr585: Passed. + pr587: Passed. + pr590: Passed. + pr594: Passed. + pr596: Passed. + pr602: Passed. + pr617: Passed. + pr632: Passed. + pr673: Passed. + pr675: Passed. + pr678: Passed. + pr690: Passed. + pr693: Passed. + pr699: Passed. + pr699b: Passed. + pr704: Passed. + pr707: Passed. + pr708: Passed. + pr710: Passed. + pr718: Passed. + pr722: Passed. + pr729: Passed. + pr734: Passed. + pr735: Passed. + pr748: Passed. + pr751: Passed. + pr757: Passed. + pr772: Passed. + pr810: Passed. + pr812: Passed. + pr820: Passed. + pr823: Passed. + pr841: Passed. + pr842: Passed. + pr848: Passed. + pr856: Passed. + pr859: Passed. + pr860: Passed. + pr872: Passed. + pr902: Passed. + pr905: Passed. + pr910: Passed. + pr913: Passed. + pr923: Passed. + pr938: Passed. + pr938b: Passed. + pr938b_std: Passed. + pr941: Passed. + pr973: Passed. + pr978: Passed. + pr985: Passed. + pr987: Passed. + pr990: Passed. + pr991: Passed. + pr993: Passed. + pr995: Passed. + pr1002: Passed. + pr1002a: Passed. + pr1007: Passed. + pr1008: Passed. + pr1022: Passed. + pr1024: Passed. + pr1026: Passed. + pr1029: Passed. + pr1032: Passed. + pr1033: Passed. + pr1065: Passed. + pr1072: Passed. + pr1077: Passed. + pr1087: Passed. + pr1101: Passed. + pr1115: Passed. + pr1353345: Passed. + pr1353345b: Passed. + pr1367855: Passed. + pr1380261: Passed. + pr1403406: Passed. + pr1403406a: Passed. + pr1403406b: Passed. + pr1421777: Passed. + pr1444055: Passed. + pr1449749a: Passed. + pr1455873: Passed. + pr1465769: Passed. + pr1467825: Passed - CO. + pr1474283: Passed. + pr1474316: Passed. + pr1474318: Passed. + pr1476440: Passed. + pr1477190: Passed. + pr1478121: Passed. + pr1478988: Passed. + pr1489568: Passed. + pr1489570: Passed. + pr1491355: Passed. + pr1492075: Passed. + pr1508882: Passed. + pr1510724: Passed. + pr1515168: Passed. + pr1520314: Passed - CO. + pr1522570: Passed. + pr1530426: Passed. + pr1561597: Passed. + pr1565544: Passed. + pr1565699b: Passed. + pr1570451: Passed. + pr1570451b: Passed. + pr1570635: Passed. + pr1570635b: Passed. + pr1574175: Passed. + pr1581580: Passed. + pr1587634: Passed - CO. + pr1587669: Passed. + pr1589497: Passed. + pr1598445: Passed. + pr1601896: Passed. + pr1601898: Passed. + pr1603313: Passed. + pr1603918: Passed. + pr1612693: Passed. + pr1623097: Passed. + pr1625912: Passed. + pr1628288: Passed. + pr1628300: Passed. + pr1629683: Passed. + pr1632861: Passed. + pr1634526: Passed. + pr1636409: Passed. + pr1637208: Passed. + pr1638985: Passed. + pr1639060: Passed. + pr1639064: Passed. + pr1639064b: Passed. + pr1639968: Passed. + pr1639971: Passed. + pr1645277: Passed. + pr1645518: Passed. + pr1648365: Passed. + pr1650842: Passed. + pr1657307: Passed. + pr1661640: Passed. + pr1662508: Passed. + pr1664684: Passed. + pr1675789: Passed. + pr1675789b: Passed. + pr1676071: Passed. + pr1676836: Passed. + pr1682887: Passed. + pr1687193: Passed. + pr1688717: Passed. + pr1690058: Passed. + pr1691599b: Passed. + pr1691709: Passed. + pr1693890: Passed. + pr1693921: Passed. + pr1694413: Passed. + pr1694427: Passed. + pr1695257: Passed - CO. + pr1695309: Passed. + pr1695322: Passed. + pr1695334: Passed. + pr1696137: Passed. + pr1697250: Passed. + pr1697732: Passed. + pr1698499: Passed. + pr1698658: Passed. + pr1698659: Passed. + pr1698820: Passed. + pr1699444: Passed. + pr1699519: Passed. + pr1701855: Passed. + pr1701855b: Passed. + pr1701889: Passed. + pr1701921: Passed. + pr1702593: Passed. + pr1703120: Passed. + pr1703346: Passed. + pr1703959: Passed. + pr1704013: Passed - CE. + pr1704726a: Passed - CE. + pr1704726b: Passed. + pr1704726c: Passed - CE. + pr1704726d: Passed - CE. + pr1705027: Passed - CO. + pr1716276: Passed. + pr1717361: Passed. + pr1719055: Passed. + pr1723367: Passed. + pr1735724: Passed - CE. + pr1735822: Passed. + pr1735836: Passed. + pr1740476b: Passed. + pr1742910: Passed. + pr1745005: Passed. + pr1746401: Passed. + pr1746848: Passed. + pr1752353: Passed. + pr1752823a: Passed. + pr1752823b: Passed. + pr1755593: Passed. + pr1755629: Passed. + pr1758122: Passed. + pr1758135: Passed. + pr1763333: Passed - CE. + pr1770199: Passed. + pr1776485: Passed. + pr1777103: Passed. + pr1780480: Passed. + pr1784984: Passed. + pr1787394a: Passed. + pr1787394b: Passed. + pr1787423: Passed. + pr1787423b: Passed. + pr1787423c: Passed. + pr1792108: Passed. + pr1792152: Passed. + pr1792734: Passed. + pr1793157: Passed. + pr1794362: Passed. + pr1795005a: Passed. + pr1795005b: Passed. + pr1799904: Passed. + pr1804877: Passed. + pr1805837: Passed. + pr1812297: Passed. + pr1819452: Passed. + pr1820472: Passed. + pr1822658: Passed. + pr1823732: Passed. + pr1828642: Passed. + pr1830834: Passed. + pr1831724: Passed. + pr1832097a: Passed. + pr1832097b: Passed. + pr1833024: Passed - CE. + pr1833754: Passed - CE. + pr1841300: Passed. + pr1845683: Passed. + pr1851310: Passed. + pr1855504: Passed. + pr1861212a: Passed. + pr1862744a: Passed. + pr1862744b: Passed - CE. + pr1866215: Passed. + pr1866215b: Passed. + pr1867161a: Passed. + pr1867161b: Passed. + pr1867332: Passed - CO. + pr1868792: Passed. + pr1868991a: Passed. + pr1868991b: Passed - CO. + pr1869769: Passed. + pr1869772: Passed. + pr1869781: Passed. + pr1873146: Passed. + pr1875866: Passed. + pr1875866b: Passed. + pr1876798: Passed. + pr1877740: Passed. + pr1877743: Passed. + pr1878909: Passed. + pr1879226: Passed. + pr1883052: Passed. + pr1883052b: Passed. + pr1885847: Passed. + pr1887168: Passed. + pr1892959: Passed. + pr1892959b: Passed. + pr1898983: Passed. + pr1901125: Passed. + pr1903157: Passed - CO. + pr1903324: Passed. + pr1903343: Passed. + pr1903520: Passed. + pr1907192: Passed. + pr1912843: Passed. + pr1913918a: Passed. + pr1913918b: Passed. + pr1913918c: Passed. + pr1913937: Passed. + pr1916261: Passed. + pr1916261a: Passed - CE. + pr1921332: Passed - CO. + pr1924845: Passed. + pr1925356: Passed. + pr1925363a: Passed - CE. + pr1925363b: Passed - CE. + pr1932444: Passed. + pr1934744: Passed. + pr1936363: Passed. + pr1938138: Passed - CE. + pr1939165: Passed. + pr1946411: Passed. + pr1948110: Passed. + pr1948342: Passed. + pr1949025: Passed. + pr1950282: Passed. + pr1956211: Passed. + pr1958801: Passed. + pr1960545: Passed. + pr1960548: Passed. + pr1960558: Passed. + pr1960575: Passed. + pr1960596: Passed. + pr1960619: Passed. + pr1960625: Passed. + pr1960633: Passed. + pr1963240: Passed. + pr1963960: Passed. + pr1971662a: Passed - CE. + pr1971662b: Passed - CE. + pr1978358: Passed. + pr1978358b: Passed. + pr1978358c: Passed. + pr1978358d: Passed. + pr1983762: Passed. + pr1985582: Passed. + pr1988302: Passed. + pr1988302b: Passed - CE. + pr1988310: Passed. + pr1990029: Passed. + pr1990164: Passed. + pr1990269: Passed. + pr1992244: Passed. + pr1992729: Passed. + pr1993479: Passed. + pr2001162: Passed. + pr2011429: Passed. + pr2013758: Passed. + pr2014673: Passed. + pr2015466: Passed. + pr2018235a: Passed. + pr2018235b: Passed. + pr2018305: Passed. + pr2019553: Passed. + pr2029336: Passed. + pr2030767: Passed. + pr2036953: Passed. + pr2038048: Passed. + pr2039632: Passed - CE. + pr2039694: Passed. + pr2043324: Passed. + pr2043585: Passed. + pr2051694: Passed - CE. + pr2051975: Passed - CE. + pr2053944: Passed. + pr2076363: Passed. + pr2076391: Passed. + pr2076425: Passed. + pr2085984: Passed. + pr2091455: Passed. + pr2109179: Passed. + pr2117473: Passed. + pr2117488: Passed. + pr2119622: Passed. + pr2121536: Passed. + pr2121536b: Passed. + pr2123190: Passed. + pr2132552: Passed. + pr2136787: Passed. + pr2138682: Passed. + pr2138979: Passed. + pr2138979b: Passed. + pr2138979c: Passed. + pr2138979d: Passed. + pr2139593: Passed. + pr2146620: Passed. + pr2146620b: Passed. + pr2146620c: Passed. + pr2146824: Passed. + pr2148401: Passed. + pr2152011: Passed. + pr2159630: Passed. + pr2166188: Passed. + pr2166311: Passed. + pr2169870: Passed. + pr2172606: Passed. + pr2172606b: Passed. + pr2181249: Passed. + pr2190323: Passed. + pr2201909: Passed. + pr2201909b: Passed. + pr2202706: Passed. + pr2202706b: Passed. + pr2202706c: Passed. + pr2202846a: Passed. + pr2202846b: Passed. + pr2202846c: Passed. + pr2208681: Passed. + pr2215342: Passed. + pr2219441: Passed. + pr2219441b: Passed. + pr2224845: Passed. + pr2224949: Passed. + pr2233180: Passed. + pr2233180b: Passed. + pr2233180c: Passed. + pr2233192: Passed. + pr2233192b: Passed. + pr2233192c: Passed. + pr2248925: Passed. + pr2251119: Passed. + pr2257003: Passed. + pr2257003b: Passed. + pr2270035: Passed. + pr2276163: Passed. + pr2281479: Passed. + pr2305307: Passed. + pr2305307b: Passed. + pr2305307c: Passed. + pr2306259: Passed. + pr2350934: Passed. + pr2350934b: Passed. + pr2350988: Passed. + pr2352834: Passed. + pr2355304: Passed. + pr2355304b: Passed. + pr2358264: Passed. + pr2358848: Passed. + pr2395378a: Passed - CE. + pr2395378b: Passed - CE. + pr2395378c: Passed - CE. + pr2395835: Passed. + pr2425055a: Passed. + pr2425055b: Passed. + pr2425055c: Passed. + pr2428890: Passed. + pr2428890b: Passed. + pr2434688: Passed. + pr2434688b: Passed. + pr2450244: Passed. + pr2453002: Passed. + pr2459681: Passed. + pr2470181a: Passed. + pr2470181b: Passed. + pr2503208: Passed. + pr2528915: Passed - CE. + pr2533175: Passed. + pr2579479: Passed. + pr2580730: Passed. + pr2593733: Passed. + pr2597278: Passed. + pr2597278b: Passed - CE. + pr2605006: Passed. + pr2673846: Passed. + pr2688910: Passed. + pr2709097: Passed. + pr2715547: Passed. + pr2715558: Passed. + pr2715558b: Passed. + pr2721213: Passed. + pr2722330a: Passed. + pr2722330b: Passed. + pr2722339a: Passed. + pr2722339b: Passed. + pr2723712: Passed. + pr2725700a: Passed. + pr2725700b: Passed. + pr2725700c: Passed. + pr2728032: Passed. + pr2728547: Passed. + pr2728812a: Passed. + pr2728812b: Passed - CE. + pr2728812c: Passed - CE. + pr2745281: Passed. + pr2781595: Passed. + pr2785294: Passed. + pr2788686: Passed. + pr2790236: Passed. + pr2792883: Passed - CE. + pr2792897: Passed. + pr2794144: Passed - CE. + pr2800985a: Passed. + pr2800985b: Passed - RE. + pr2801134: Passed. + pr2801662: Passed. + pr2809288: Passed - CE. + pr2815398a: Passed. + pr2815398a_std: Passed. + pr2815398b: Passed. + pr2818823: Passed. + pr2823414: Passed - CE. + pr2823711: Passed. + pr2824189: Passed. + pr2829776: Passed. + pr2829776b: Passed. + pr2832234: Passed. + pr2834340: Passed. + pr2834340b: Passed. + pr2835632a: Passed. + pr2835632b: Passed. + pr2837451: Passed. + pr2842185: Passed. + pr2842621: Passed. + pr2842621_std: Passed. + pr2848986: Passed - CE. + pr2849783: Passed. + pr2865563: Passed. + pr2877564: Passed - CE. + pr2883958: Passed. + pr2885048: Passed. + pr2890322: Passed. + pr2901556: Passed. + pr2909386a: Passed. + pr2909386b: Passed. + pr2909414: Passed. + pr2909555: Passed. + pr2913404: Passed. + pr2913416: Passed. + pr2913438a: Passed. + pr2913438b: Passed. + pr2913927: Passed. + pr2918095: Passed. + pr2922063: Passed. + pr2922063a: Passed. + pr2922063b: Passed. + pr2924354: Passed. + pr2929913: Passed. + pr2930506: Passed. + pr2937417: Passed. + pr2937417b: Passed. + pr2937417c: Passed. + pr2941939: Passed. + pr2943394: Passed. + pr2951657: Passed. + pr2969724: Passed. + pr2971207: Passed. + pr2972866: Passed. + pr2973532: Passed. + pr2974051: Passed. + pr2974216: Passed. + pr2974216b: Passed. + pr2974294: Passed. + pr2985542: Passed. + pr2986497: Passed - CO. + pr2986528: Passed. + pr2991457: Passed. + pr2991457b: Passed. + pr2994193: Passed. + pr2998515: Passed. + pr3011327: Passed. + pr3012758: Passed. + pr3022502: Passed. + pr3024131: Passed. + pr3039548: Passed. + pr3044843: Passed. + pr3054101a: Passed. + pr3054101b: Passed. + pr3054101c: Passed. + pr3054101d: Passed. + pr3054101e: Passed. + pr3054101f: Passed. + pr3054101g: Passed. + pr3054101h: Passed. + pr3061015a: Passed - CE. + pr3061015b: Passed - CE. + pr3061015c: Passed - CE. + pr3064375: Passed. + pr3064511: Passed. + pr3077640: Passed. + pr3078759: Passed - CO. + pr3098439: Passed. + pr3098439a: Passed. + pr3098439b: Passed. + pr3103880: Passed. + pr3104254: Passed. + pr3112073a: Passed - CE. + pr3149494: Passed. + pr3190941: Passed - CE. + pr3190948: Passed. + pr3194155: Passed. + pr3197861: Passed. + pr3197917: Passed. + pr3270320: Passed - CE. + pr3284821: Passed. + pr3292735: Passed. + pr3296466a: Passed. + pr3296466b: Passed. + pr3296466c: Passed. + pr3296466d: Passed. + pr3306516: Passed. + pr3309391: Passed. + pr3368642: Passed. + pr3409749: Passed. + pr3437290a: Passed. + pr3437290b: Passed. + pr3437290c: Passed. + pr3441576: Passed. + pr3445452: Passed. + pr3452808: Passed. + pr3465541: Passed. + pr3477107: Passed. + pr3499807: Passed. + pr3522653: Passed. + pr3527022: Passed. + pr3527694: Passed. + pr3534422: Passed. + pr3539372: Passed. + pr3549328: Passed - CE. + pr3557493: Passed. + pr3561350: Passed. + pr3563412: Passed. + pr3571573: Passed. + pr3582052: Passed. + pr3587570: Passed. + pr3592746: Passed. + prng: Passed. + ptest001: Passed. + ptest002: Passed. + ptest003: Passed. + ptest004: Passed. + ptest005: Passed. + ptest006: Passed. + ptest007: Passed. + ptest008: Passed. + ptest009: Passed. + ptest010: Passed. + ptest011: Passed. + pullupdown: Passed. + pullupdown2: Passed. + pullupdown3: Passed. + pv_undef_sig_sel: Passed. + qmark: Passed. + qmark1: Passed. + qmark3: Passed. + qmark5: Passed. + qmark6: Passed. + queue: Passed. + queue_fail: Passed - RE. + queue_stat: Passed. + ram16x1: Passed. + readmem-error: Passed. + readmem-invalid: Passed - RE. + readmemb1: Passed. + readmemb2: Passed. + readmemb3: Passed. + readmemh1: Passed. + readmemh1a: Passed. + readmemh2: Passed. + readmemh3: Passed. + readmemh4: Passed. + readmemh5: Passed - CE. + real: Passed. + real2: Passed. + real3: Passed. + real5: Passed. + real6: Passed. + real7: Passed. + real9: Passed. + real10: Passed. + real11: Passed. + real_assign_deassign: Passed. + real_concat_invalid2: Passed - CE. + real_delay: Passed. + real_events: Passed. + real_force_rel: Passed. + real_invalid_ops: Passed - CE. + real_logical: Passed. + real_reg_force_rel: Passed. + recursive_func: Passed. + recursive_task: Passed. + redef_net_error: Passed - CE. + redef_reg_error: Passed - CE. + repeat2: Passed. + repeat_expr_probe: Passed. + repl_zero_wid_fail: Passed - CE. + repl_zero_wid_pass: Passed. + resetall2: Passed. + resolv1: Passed. + rise_fall_decay1: Passed. + rise_fall_decay2: Passed. + rise_fall_delay1: Passed. + rise_fall_delay2: Passed. + rise_fall_delay3: Passed. + rl_pow: Passed. + rnpmos: Passed. + rnpmos2: Passed. + rop: Passed. + rptconcat: Passed. + rtran: Passed. + rtranif0: Passed. + rtranif1: Passed. + scan-invalid: Passed - RE. + scanf: Passed. + scanf2: Passed. + scanf3: Passed. + scanf4: Passed. + sched1: Passed. + sched2: Passed. + schedule: Passed. + scope1: Passed. + scope2: Passed. + scope4: Passed. + scope5: Passed. + scoped_events: Passed. + sdf1: Passed. + sdf2: Passed. + sdf3: Passed. + sdf4: Passed. + sdf5: Passed. + sdf6: Passed. + sdf7: Passed. + sdf8: Passed. + sdf_del_max: Passed. + sdf_del_min: Passed. + sdf_del_typ: Passed. + sdf_esc_id: Passed. + sdw_always1: Passed. + sdw_always2: Passed. + sdw_always3: Passed. + sdw_array: Passed. + sdw_assign: Passed. + sdw_dsbl: Passed. + sdw_force: Passed. + sdw_function1: Passed. + sdw_function2: Passed. + sdw_function3: Passed. + sdw_function4: Passed. + sdw_function5: Passed. + sdw_instmod1: Passed. + sdw_instmod2: Passed. + sdw_int: Passed. + sdw_lvalconcat: Passed. + sdw_param1: Passed. + sdw_param2: Passed. + sdw_release: Passed. + sdw_stmt002: Passed. + sdw_task1: Passed. + sdw_task2: Passed. + sel_rval_bit_ob: Passed. + sel_rval_part_ob: Passed. + select: Passed. + select2: Passed. + select3: Passed. + select4: Passed. + select5: Passed. + select6: Passed. + select7: Passed. + select8: Passed. + select_padding: Passed. + shellho1: Passed. + shift1: Passed. + shift2: Passed. + shift3: Passed. + shift4: Passed. + shift5: Passed. + shift_pad: Passed. + signed1: Passed. + signed2: Passed. + signed3: Passed. + signed4: Passed. + signed5: Passed. + signed6: Passed. + signed7: Passed. + signed8: Passed. + signed9: Passed. + signed10: Passed. + signed11: Passed. + signed12: Passed. + signed13: Passed. + signed_a: Passed. + signed_equality: Passed. + signed_net_display: Passed. + signed_part: Passed. + signed_pv: Passed. + sp2: Passed. + specify1: Passed - CO. + specify2: Passed. + specify3: Passed. + specify4: Passed. + specify5: Passed. + specify_01: Passed. + sqrt32: Passed. + sscanf_u: Passed. + sscanf_z: Passed. + stask_parm1: Passed. + stask_parm2: Passed. + stask_sens_null_arg: Passed. + string1: Passed. + string2: Passed. + string3: Passed. + string4: Passed. + string5: Passed. + string7: Passed. + string8: Passed. + string9: Passed. + string10: Passed. + string11: Passed. + string12: Passed. + supply1: Passed. + supply2: Passed. + switch_primitives: Passed. + talu: Passed. + task-scope: Passed. + task3.14A: Passed. + task3.14B: Passed. + task3.14C: Passed. + task3.14D: Passed. + task3.14E: Passed. + task3.14F: Passed. + task_bypath: Passed. + task_inpad: Passed. + task_iotypes: Passed. + task_iotypes2: Passed. + task_mem: Passed. + task_noop: Passed. + task_noop2: Passed - CO. + task_omemw2: Passed. + task_omemw3: Passed - CO. + task_port_size: Passed. + task_scope: Passed. + tern1: Passed. + tern2: Passed - CO. + tern4: Passed. + tern5: Passed. + tern6: Passed. + tern7: Passed. + tern9: Passed. + tern10: Passed. + test_bufif0: Passed. + test_bufif1: Passed. + test_disphob: Passed. + test_dispwided: Passed. + test_extended: Passed. +test_mos_strength_reduction: Passed. + test_nmos: Passed. + test_notif0: Passed. + test_notif1: Passed. + test_pmos: Passed. + test_rnmos: Passed. + test_rpmos: Passed. + test_width: Passed. + time1: Passed. + time2: Passed. + time3: Passed. + time4: Passed. + time5: Passed. + time7: Passed. + time8: Passed. + timeform1: Passed. + timeform2: Passed. + timescale1: Passed. + timescale2: Passed. + timescale3: Passed - CE. + tran: Passed. + tranif0: Passed. + tranif1: Passed. + tran-keeper: Passed. + tri0: Passed. + tri0b: Passed. + tri1: Passed. + tri2: Passed. + tri3: Passed. + triand: Passed. + trior: Passed. + types1: Passed. + udp_bufg: Passed. + udp_bufg2: Passed. + udp_bx: Passed. + udp_delay_fail: Passed - CE. + udp_dff: Passed. + udp_dff_std: Passed. + udp_eval_arg: Passed. + udp_jkff: Passed. + udp_real_delay: Passed. + udp_sched: Passed. + udp_x: Passed. + unary_and: Passed. + unary_lnot1: Passed. + unary_lnot2: Passed. + unary_lnot3: Passed. + unary_minus: Passed. + unary_minus1: Passed. + unary_minus2: Passed. + unary_minus3: Passed. + unary_minus4: Passed. + unary_nand: Passed. + unary_nand2: Passed. + unary_nor: Passed. + unary_nor2: Passed. + unary_not: Passed. + unary_or: Passed. + unary_xnor1: Passed. + unary_xnor2: Passed. + unary_xor: Passed. + uncon_drive: Passed. + undef: Passed. + undef_lval_select: Passed. + undef_lval_select2: Passed. + undef_lval_select3a: Passed. + undef_lval_select3b: Passed - CE. + undef_lval_select3c: Passed - CE. + undef_lval_select4a: Passed. + undef_lval_select4b: Passed - CE. + undef_lval_select4c: Passed - CE. + undef_lval_select5: Passed. + undefined_shift: Passed. + urand_r: Passed. + urand_r2: Passed. + urand_r3: Passed. + uwire: Passed. + uwire2: Passed. + uwire_fail: Passed - CE. + vardly: Passed. + varlsfht: Passed. + varlsfht1: Passed. + varlsfht2: Passed. + varrshft: Passed. + varrshft1: Passed. + varrshft2: Passed. + vcd-dup: Passed. + vector: Passed. + verify_two_var_delays: Passed. + vvp_scalar_value: Passed. + wait1: Passed. + wait2: Passed. + wait3: Passed. + warn_opt_sys_tf: Passed - RE. + wildsense: Passed. + wildsense2: Passed. + wireadd1: Passed. + wireeq: Passed. + wirege: Passed. + wireland: Passed. + wirele: Passed. + wiremod1: Passed. + wiresl: Passed. + wiresl2: Passed. + wiresr: Passed. + wiresub1: Passed. + wirexor1: Passed. + writemem-error: Passed. + writemem-invalid: Passed - RE. + writememb1: Passed. + writememb2: Passed. + writememh1: Passed. + writememh2: Passed. + xnor_test: Passed. + z1: Passed. + z2: Passed. + zero_repl: Passed. + zero_repl_fail: Passed - CE. + cmpi: Passed. + analog1: ==> Failed - running iverilog. + analog2: ==> Failed - running iverilog. + br_gh99c: Passed. + cast_int_ams: Passed. + constfunc4_ams: Passed. + scaled_real: Passed. + test_vams_math: Passed. + value_range1: Passed. + value_range2: Passed. + value_range3: Passed - CE. + vams_abs1: Passed. + vams_abs2: Passed. + wreal: Passed. + always4A: Passed - CE. + always4B: Passed - CE. + always_comb: Passed. + always_comb_fail: Passed - CE. + always_comb_fail3: Passed - CE. + always_comb_fail4: Passed - CE. + always_comb_no_sens: Passed. + always_comb_rfunc: Passed. + always_comb_trig: Passed. + always_comb_warn: Passed. + always_ff: Passed. + always_ff_fail: Passed - CE. + always_ff_fail2: Passed - CE. + always_ff_fail3: Passed - CE. + always_ff_fail4: Passed - CE. + always_ff_no_sens: Passed - CE. + always_ff_warn: Passed. + always_ff_warn_sens: Passed. + always_latch: Passed. + always_latch_fail: Passed - CE. + always_latch_fail3: Passed - CE. + always_latch_fail4: Passed - CE. + always_latch_no_sens: Passed - CE. + always_latch_trig: Passed. + always_latch_warn: Passed. + array_size: Passed. + array_string: Passed. + array_unpacked_sysfunct: Passed. + array_packed: Passed. + assign_op_concat: Passed. + assign_op_type: Passed. + bitp1: Passed. + bits: Passed. + bits2: Passed. + br884: Passed. + br917a: Passed. + br917b: Passed. + br917c: Passed. + br917d: Passed. + br921: Passed. + br932a: Passed. + br932b: Passed. + br936: Passed. + br956: Passed. + br959: Passed. + br962: Passed. + br963: Passed. + br973: Passed. + br974a: Passed. + br974b: Passed. + br974c: Passed. + br975: Passed - CE. + br979: Passed. + br991b: Passed - CE. + br1003a: Passed. + br1003b: Passed. + br1003c: Passed. + br1003d: Passed. + br1004: Passed. + br1025: Passed. + br1027b: Passed. + br1027d: Passed. + br1027f: Passed. + br_gh4: Passed. + br_gh4a: Passed. + br_gh72a: Passed. + br_gh72b: Passed. + br_gh72b_fail: Passed - CE. + br_gh104a: Passed. + br_gh104b: Passed. + br_gh105a: Passed. + br_gh105b: Passed. + br_gh112a: Passed. + br_gh112b: Passed. + br_gh112c: Passed. + br_gh112d: Passed. + br_gh112e: Passed. + br_gh112f: Passed. + br_gh129: Passed. + br_gh130a: Passed - CE. + br_gh165: Passed. + br_gh164a: Passed. + br_gh164b: Passed. + br_gh164c: Passed. + br_gh164d: Passed. + br_gh164e: Passed. + br_gh167a: Passed. + br_gh167b: Passed. + br_gh177a: Passed. + br_gh177b: Passed. + br_gh194: Passed. + br_gh219: Passed. + br_gh220: Passed. + br_gh224: Passed. + br_gh226: Passed. + br_gh231: Passed. + br_gh243: Passed. + br_gh265: Passed - CE. + br_gh277b: Passed. + br_gh280: Passed. + br_gh281: Passed. + br_gh281b: Passed. + br_gh289a: Passed. + br_gh289b: Passed. + br_gh289c: Passed. + br_gh289d: Passed. + br_gh337: Passed. + br_gh361: Passed. + br_gh365: Passed. + br_gh366: Passed. + br_gh368: Passed. + br_gh374: Passed. + br_gh386a: Passed. + br_gh386b: Passed. + br_gh386c: Passed - CE. + br_gh388: Passed. + br_gh391: Passed. + br_gh411: Passed. + br_gh418: Passed. + br_gh433: Passed. + br_gh437: Passed. + br_gh440: Passed - CE. + br_gh443: Passed. + br_gh445: Passed. + br_gh461: Passed. + br_gh477: Passed. + br_gh478: Passed. + br_gh498: Passed. + br_gh508a: Passed. + br_gh527: Passed. + br_gh530: Passed - CO. + br_gh540: Passed. + br_gh553: Passed. + br_gh556: Passed. + br_gh568: Passed. + br_ml20171017: Passed. + br_ml20180227: Passed - CE. + br_ml20180309a: Passed. + br_ml20180309b: Passed. + br_ml20181012a: Passed - CE. + br_ml20181012b: Passed - CE. + br_ml20181012c: Passed - CE. + br_ml20181012d: Passed - CE. + br_ml20191221: Passed. + br_mw20200501: Passed. + case_priority: Passed. + case_unique: Passed. + cast_real: Passed. + cfunc_assign_op_mixed: Passed. + cfunc_assign_op_pv: Passed. + cfunc_assign_op_real: Passed. + cfunc_assign_op_vec: Passed. + clkgen_bit: Passed. + clkgen_logic: Passed. + clkgen_net: Passed. + clkgen_reg: Passed. + disable_fork_cmd: Passed. + display_bug: Passed. + edge: Passed. + enum_base_range: Passed. + enum_elem_ranges: Passed. + enum_dims_invalid: Passed - CE. + enum_next: Passed. + enum_ports: Passed. + enum_test1: Passed. + enum_test2: Passed. + enum_test3: Passed - CE. + enum_test4: Passed. + enum_test5: Passed - CE. + enum_test6: Passed - CE. + enum_test7: Passed - CE. + enum_test8: Passed. + enum_value_expr: Passed. + enum_values: Passed. + escaped_macro_name: Passed. + extra_semicolon: Passed. + fileline: Passed. + fileline2: Passed. + final: Passed. + final2: Passed. + first_last_num: Passed. + fork_join_any: Passed. + fork_join_dis: Passed. + fork_join_none: Passed. + fr49: Passed. + func_init_var1: Passed. + func_init_var2: Passed. + func_init_var3: Passed. + function10: Passed - CO. + function11: Passed - CE. + function12: Passed. + genvar_inc_dec: Passed. + ibit_test: Passed. + ibyte_test: Passed. + iint_test: Passed. + ilongint_test: Passed. + implicit_cast1: Passed. + implicit_cast2: Passed. + implicit_cast3: Passed. + implicit_cast4: Passed. + implicit_cast5: Passed. + implicit_cast6: Passed. + implicit_cast7: Passed. + implicit_cast8: Passed. + implicit_cast9: Passed. + implicit_cast10: Passed. + implicit_cast11: Passed. + implicit_cast12: Passed. + implicit_cast13: Passed. + implicit-port1: Passed. + implicit-port2: Passed - CE. + implicit-port3: Passed - CE. + implicit-port4: Passed. + implicit-port5: Passed. + implicit-port6: Passed - CE. + implicit-port7: Passed. + inc_dec_stmt: Passed. + int_param: Passed. + ishortint_test: Passed. + iuint1: Passed. + l_equiv: Passed. + l_equiv_ca: Passed. + l_equiv_const: Passed. + line_directive: Passed. + localparam_query: Passed. + localparam_type2: Passed. + logical_short_circuit: Passed. + logp2: Passed. + mod_inst_pkg: Passed. + named_begin: Passed. + named_begin_fail: Passed - CE. + named_fork: Passed. + named_fork_fail: Passed - CE. + packeda: Passed. + packeda2: Passed. + parameter_type2: Passed. + parpkg_test: Passed. + parpkg_test2: Passed. + parpkg_test3: Passed. + part_sel_port: Passed. + plus_5: Passed. + pr3366114: Passed. + pr3366217a: Passed - CE. + pr3366217b: Passed - CE. + pr3366217c: Passed - CE. + pr3366217d: Passed - CE. + pr3366217e: Passed. + pr3366217f: Passed. + pr3366217g: Passed - CE. + pr3366217h: Passed. + pr3366217i: Passed. + pr3390385: Passed. + pr3390385b: Passed. + pr3390385c: Passed. + pr3390385d: Passed. + pr3462145: Passed. + pr3515542: Passed - CE. + pr3534333: Passed. + pr3576165: Passed. + program2: Passed. + program2b: Passed. + program3: Passed. + program3a: Passed. + program3b: Passed - CE. + program4: Passed. + program5a: Passed - CE. + program5b: Passed - CE. + program_hello: Passed. + program_hello2: Passed - CE. + sbyte_test: Passed. + scalar_vector: Passed. + sf_countbits: Passed. + sf_countbits_fail: Passed - RE. + sf_countones: Passed. + sf_countones_fail: Passed - RE. + sf_isunknown: Passed. + sf_isunknown_fail: Passed - RE. + sf_onehot: Passed. + sf_onehot_fail: Passed - RE. + sf_onehot0: Passed. + sf_onehot0_fail: Passed - RE. + sformatf: Passed. + simple_byte: Passed. + simple_int: Passed. + simple_longint: Passed. + simple_shortint: Passed. + sint_test: Passed. + size_cast: Passed. + size_cast2: Passed. + size_cast3: Passed. + size_cast4: Passed. + size_cast5: Passed. + slongint_test: Passed. + sshortint_test: Passed. + string_events: Passed. + string_index: Passed. + struct1: Passed. + struct2: Passed. + struct3: Passed. + struct3b: Passed. + struct4: Passed. + struct5: Passed. + struct6: Passed. + struct7: Passed. + struct8: Passed. + struct9: Passed. + struct_packed_array: Passed. + struct_packed_array2: Passed. + struct_packed_sysfunct: Passed. + struct_packed_write_read2: Passed. + sv-constants: Passed. + sv_array_assign_pattern2: Passed. + sv_cast_integer: Passed. + sv_cast_integer2: Passed. + sv_cast_string: Passed. + sv_class1: Passed. + sv_class2: Passed. + sv_class3: Passed. + sv_class4: Passed. + sv_class5: Passed. + sv_class6: Passed. + sv_class7: Passed. + sv_class8: Passed. + sv_class9: Passed. + sv_class10: Passed. + sv_class11: Passed. + sv_class12: Passed. + sv_class13: Passed. + sv_class14: Passed. + sv_class15: Passed. + sv_class16: Passed. + sv_class17: Passed. + sv_class18: Passed. + sv_class19: Passed. + sv_class20: Passed. + sv_class21: Passed. + sv_class22: Passed. + sv_class23: Passed. + sv_class24: Passed. + sv_darray1: Passed. + sv_darray2: Passed. + sv_darray3: Passed. + sv_darray4: Passed. + sv_darray5: Passed. + sv_darray5b: Passed. + sv_darray6: Passed. + sv_darray_args1: Passed. + sv_darray_args2: Passed. + sv_darray_args2b: Passed. + sv_darray_args3: Passed. + sv_darray_args4: Passed. + sv_darray_decl_assign: Passed. + sv_darray_function: Passed. + sv_darray_signed: Passed. + sv_darray_word_size: Passed. + sv_default_port_value1: Passed. + sv_default_port_value2: Passed. + sv_default_port_value3: Passed - CE. + sv_end_label: Passed. + sv_end_label_fail: Passed - CE. + sv_end_labels: Passed. + sv_end_labels_bad: Passed - CE. + sv_enum1: Passed. + sv_for_variable: Passed. + sv_foreach1: Passed. + sv_foreach2: Passed. + sv_foreach3: Passed. + sv_foreach4: Passed. + sv_foreach5: Passed. + sv_immediate_assert: Passed. + sv_immediate_assume: Passed. + sv_macro: Passed. + sv_macro2: Passed. + sv_macro3a: Passed. + sv_macro3b: Passed. + sv_new_array_error: Passed - CE. + sv_package: Passed. + sv_package2: Passed. + sv_package3: Passed. + sv_package4: Passed. + sv_package5: Passed. + sv_packed_port1: Passed. + sv_packed_port2: Passed. + sv_param_port_list: Passed. + sv_pkg_class: Passed. + sv_port_default1: Passed. + sv_port_default2: Passed. + sv_port_default3: Passed. + sv_port_default4: Passed. + sv_port_default5: Passed. + sv_port_default6: Passed. + sv_port_default7: Passed. + sv_port_default8: Passed. + sv_port_default9: Passed. + sv_port_default10: Passed. + sv_port_default11: Passed. + sv_port_default12: Passed. + sv_port_default13: Passed - CE. + sv_port_default14: Passed - CE. + sv_queue1: Passed. + sv_queue2: Passed. + sv_queue3: Passed. + sv_queue_real: Passed. + sv_queue_real_bounded: Passed. + sv_queue_real_fail: Passed - CE. + sv_queue_string: Passed. + sv_queue_string_bounded: Passed. + sv_queue_string_fail: Passed - CE. + sv_queue_vec: Passed. + sv_queue_vec_bounded: Passed. + sv_queue_vec_fail: Passed - CE. + sv_root_class: Passed. + sv_root_func: Passed. + sv_root_task: Passed. + sv_string1: Passed. + sv_string2: Passed. + sv_string3: Passed. + sv_string4: Passed. + sv_string5: Passed. + sv_timeunit_prec1: Passed. + sv_timeunit_prec2: Passed. + sv_timeunit_prec3a: Passed. + sv_timeunit_prec3b: Passed. + sv_timeunit_prec3c: Passed. + sv_timeunit_prec3d: Passed. + sv_timeunit_prec4a: Passed. + sv_timeunit_prec4b: Passed. + sv_timeunit_prec_fail1: Passed - CE. + sv_timeunit_prec_fail2: Passed - CE. + sv_typedef_scope: Passed. + sv_union1: Passed. + sv_union1b: Passed. + sv_union2: Passed. + sv_union2b: Passed. + sv_union3: Passed. + sv_union3b: Passed. + sv_union4b: Passed. + sv_unit1b: Passed. + sv_unit1c: Passed. + sv_unit2b: Passed. + sv_unit3b: Passed. + sv_unit4b: Passed. + sv_unpacked_port: Passed. + sv_unpacked_port2: Passed. + sv_unpacked_wire: Passed. + sv_unpacked_wire2: Passed. + sv_uwire1: Passed. + sv_uwire2: Passed. + sv_uwire3: Passed. + sv_uwire4: Passed. + sv_var_init1: Passed. + sv_var_init2: Passed. + sv_wildcard_import1: Passed. + sv_wildcard_import2: Passed. + sv_wildcard_import3: Passed. + sv_wildcard_import4: Passed - CE. + sv_wildcard_import5: Passed - CE. + sv_wildcard_import6: Passed. + sv_wildcard_import7: Passed. + sys_func_as_task: Passed. + task_init_assign: Passed. + task_init_var1: Passed. + task_init_var2: Passed. + task_init_var3: Passed. + task_scope2: Passed. + test_inc_dec: Passed. + test_tliteral: Passed. + timeliteral: Passed. + two_state_display: Passed. + ubyte_test: Passed. + uint_test: Passed. + ulongint_test: Passed. + undef_lval_select_SV: Passed. + unp_array_typedef: Passed. + packed_dims_invalid_class: Passed - CE. + packed_dims_invalid_module: Passed - CE. + ushortint_test: Passed. + vvp_recv_vec4_pv: Passed. + wait_fork: Passed. + sf1289: Passed. + wild_cmp_const: Passed. + wild_cmp_net: Passed. + wild_cmp_var: Passed. + wild_cmp_err: Passed - CE. + wild_cmp_err2: Passed - CE. + gh161a: Passed. + gh161b: Passed. + pull371b: Passed. + br_gh175: Passed. + br_gh307: Passed. + br_gh383a: Passed. + br_gh383b: Passed. + br_gh383c: Passed. + br_gh390a: Passed - CE. + br_gh390b: Passed. + br_gh412: Passed. + br_gh414: Passed. + br_gh436: Passed. + br_gh451: Passed. + br_gh453: Passed. + br_gh460: Passed. + br942: Passed. + br943_944: Passed. + br985: Passed. + br986: Passed. + br987: Passed. + ivlh_event: Passed. + ivlh_rising_falling: Passed. + ivlh_textio: Passed. + test_dec2to4: Passed. + test_enumsystem: Passed. + test_forgen: Passed. + test_gxor: Passed. + test_mux2to1: Passed. + test_signal_init_assign: Passed. + test_system: Passed. + test_timebase: Passed. + test_varray1: Passed. + test_when_else: Passed. + test_work14: Passed. + vhdl_and104_stdlogic: Passed. + vhdl_and23_bit: Passed. + vhdl_and_gate: Passed. + vhdl_andg_bit: Passed. + vhdl_andg_stdlogic: Passed. + vhdl_array_of_array: Passed. + vhdl_case_multi: Passed. + vhdl_boolean: Passed. + vhdl_concat: Passed. + vhdl_concat_func: Passed. + vhdl_concurrent_assert: Passed. + vhdl_const_package: Passed. + vhdl_const_record: Passed. + vhdl_const_array: Passed. + vhdl_delay_assign: Passed. + vhdl_elab_range: Passed. + vhdl_eval_cond: Passed. + vhdl_expr1: Passed. + vhdl_generic_eval: Passed. + vhdl_fa4_test1: Passed. + vhdl_fa4_test2: Passed. + vhdl_fa4_test3: Passed. + vhdl_fa4_test4: Passed. + vhdl_file_open: Passed. + vhdl_generic_default: Passed. + vhdl_init: Passed. + vhdl_image_attr: Passed. + vhdl_inout: Passed. + vhdl_labeled_assign: Passed. + vhdl_lfcr: Passed. + vhdl_logic: Passed. + vhdl_loop: Passed. + vhdl_multidim_array: ==> Failed - running iverilog. + vhdl_nand104_stdlogic: Passed. + vhdl_nand23_bit: Passed. + vhdl_nandg_bit: Passed. + vhdl_nandg_stdlogic: Passed. + vhdl_nor104_stdlogic: Passed. + vhdl_nor23_bit: Passed. + vhdl_norg_bit: Passed. + vhdl_norg_stdlogic: Passed. + vhdl_not104_stdlogic: Passed. + vhdl_not23_bit: Passed. + vhdl_notfunc_stdlogic: Passed. + vhdl_notg_bit: Passed. + vhdl_notg_stdlogic: Passed. + vhdl_now: Passed. + vhdl_or104_stdlogic: Passed. + vhdl_or23_bit: Passed. + vhdl_org_bit: Passed. + vhdl_org_stdlogic: Passed. + vhdl_pow_rem: Passed. + vhdl_prefix_array: Passed. + vhdl_procedure: Passed. + vhdl_process_scope: Passed. + vhdl_rand23_bit: Passed. + vhdl_range: Passed. + vhdl_range_func: Passed. + vhdl_real: Passed. + vhdl_record_elab: Passed. + vhdl_reduce: Passed. + vhdl_report: Passed. + vhdl_resize: Passed. + vhdl_rtoi: Passed. + vhdl_sa1_test1: Passed. + vhdl_sa1_test2: Passed. + vhdl_sa1_test3: Passed. + vhdl_sadd23_bit: Passed. + vhdl_sadd23_stdlogic: Passed. + vhdl_sdiv23_bit: Passed. + vhdl_sdiv23_stdlogic: Passed. + vhdl_selected: Passed. + vhdl_shift: Passed. + vhdl_signals: Passed. + vhdl_smul23_bit: Passed. + vhdl_smul23_stdlogic: Passed. + vhdl_ssub23_bit: Passed. + vhdl_ssub23_stdlogic: Passed. + vhdl_struct_array: Passed. + vhdl_subtypes: Passed. + vhdl_subprogram: Passed. + vhdl_string: Passed. + vhdl_string_lim: Passed. + vhdl_test1: Passed. + vhdl_test2: Passed. + vhdl_test3: Passed. + vhdl_test4: Passed. + vhdl_test5: Passed. + vhdl_test6: Passed. + vhdl_test7: Passed. + vhdl_test8: Passed. + vhdl_test9: Passed. + vhdl_textio_write: Passed. + vhdl_textio_read: Passed. + vhdl_time: Passed. + vhdl_to_integer: Passed. + vhdl_uadd23_bit: Passed. + vhdl_uadd23_stdlogic: Passed. + vhdl_udiv23_bit: Passed. + vhdl_udiv23_stdlogic: Passed. + vhdl_umul23_bit: Passed. + vhdl_umul23_stdlogic: Passed. + vhdl_unary_minus: Passed. + vhdl_unbounded: Passed. + vhdl_unbounded_func: Passed. + vhdl_usub23_bit: Passed. + vhdl_usub23_stdlogic: Passed. + vhdl_var_init: Passed. + vhdl_wait: Passed. + vhdl_while: Passed. + vhdl_xnor104_stdlogic: Passed. + vhdl_xnor23_bit: Passed. + vhdl_xnorg_bit: Passed. + vhdl_xnorg_stdlogic: Passed. + vhdl_xor23_bit: Passed. + vhdl_xorg_bit: Passed. + vhdl_xorg_stdlogic: Passed. + work7: Passed. + work7b: Passed. + basicexpr: Passed. + basicexpr2: Passed. + basicexpr3: Passed. + basicexpr4: Passed. + basiclatch: Passed. + basicreg: Passed. + basicstate: Passed. + basicstate2: Passed. + blocksynth1: Passed. + blocksynth2: Passed. + blocksynth3: Passed. + br993a: Passed. + br993b: Passed. + br994: Passed. + br_gh99v: Passed. + br_gh99w: Passed. + br_gh99x: Passed. + br_gh115: Passed. + case3: Passed. + case4: Passed. + case5: Passed. + case6: Passed. + case7: Passed. + case_wo_default: Passed. + casesynth1: Passed. + casesynth2: Passed. + casesynth3: Passed. + casesynth4: Passed. + casesynth5: Passed. + casesynth6: Passed. + casesynth9: Passed. + condit1: Passed. + conditsynth1: Passed. + conditsynth2: Passed. + conditsynth3: Passed. + dffsynth2: Passed. + dffsynth3: Passed. + dffsynth4: Passed. + dffsynth5: Passed. + dffsynth6: Passed. + dffsynth7: Passed. + dffsynth9: Passed. + dffsynth10: Passed. + dffsynth11: Passed. + ff_dual_enable: Passed. + for_loop_synth: Passed. + for_loop_synth2: Passed. + if_part_no_else: Passed. + if_part_no_else2: Passed. + inside_synth: Passed. + inside_synth2: Passed. + inside_synth3: Passed. + land5: Passed. + lcatsynth: Passed. + memsynth4: Passed. + memsynth8: Passed. + multireg: Passed. + not_a_latch1: Passed. + not_a_latch2: Passed. + partselsynth: Passed. + pr519: Passed. + pr685: Passed. + shiftl: Passed. + sqrt32synth: Passed. + ssetclr1: Passed. + ssetclr2: Passed. + ssetclr3: Passed. + synth_if_no_else: Passed. + ufuncsynth1: Passed. +============================================================================ +Test results: + Total=2559, Passed=2539, Failed=17, Not Implemented=3, Expected Fail=0 diff --git a/ivtest/regression_report-strict.txt b/ivtest/regression_report-strict.txt new file mode 100644 index 000000000..349f70de4 --- /dev/null +++ b/ivtest/regression_report-strict.txt @@ -0,0 +1,2561 @@ +Running compiler/VVP tests for Icarus Verilog version: 12 (strict). +---------------------------------------------------------------------------- + dffsynth: Passed - CE. + memsynth1: Passed - CE. + memsynth2: Passed - CE. + memsynth3: Passed - CE. + memsynth5: Passed - CE. + memsynth6: Passed - CE. + memsynth7: Passed - CE. + memsynth9: Passed - CE. + mix_reset: Passed - CE. + case1: Passed. + case2: Passed. + casex_synth: Passed. + macro_str_esc: Passed. + macro_with_args: Passed. + mcl1: Passed. + pr622: Passed. + pr639: Passed. + pr1741212: Passed. + pr1912112: Passed. + pr1925360: Passed. + repeat1: Passed. + pr2002443: Passed - CO. + constfunc6_ams: Passed. + non-polymorphic-abs: Passed. + pr3270320_ams: Passed - CE. + test_va_math: Passed. + va_math: Passed. + abstime: Passed. + pr2590274a: Passed. + pr2590274b: Passed. + pr2590274c: Passed. + bitsel: Passed. + bitsel10: Passed. + bitsel2: Passed. + bitsel3: Passed. + bitsel4: Passed. + bitsel5: Passed. + bitsel6: Passed. + bitsel7: Passed. + bitsel8: Passed. + bitsel9: Passed. + bitwidth3: Passed. + clog2: Passed. + clog2-signal: Passed. + param_vec: Passed. + param_vec2: Passed. + pr498: Passed. + pr721: Passed. + pr809: Passed. + pr809b: Passed. + pr979: Passed. + pr1000: Passed. + pr1609611: Passed. + pr1750870: Passed. + pr1765789: Passed. + pr1771903: Passed. + pr1793749: Passed. + pr1793749b: Passed. + pr1861212b: Passed. + pr1864110c: Passed. + pr1864115: Passed. + pr2806449: Passed. + pr2877555: Passed. + real4: Passed. + realtobits: Passed. + specparam1: Passed. + specparam2: Passed. + tern3: Passed. + v2005_math: Passed. + deposit: Passed. + deposit_wire: Passed. + sysargs: Passed. + fatal_et_al: Passed. + fatal_et_al2: Passed - RE. + plus_arg_string: Passed. + fileio: Passed. + pr1494799: Passed. + pr2428890c: Passed. + sv_cast_darray: Passed. + br978: Passed. + br_ml20150424: Passed. + pr2509349a: Passed. + pr2509349b: Passed. + simparam: Passed. + blocking_repeat_ec: Passed. + ca_time_smtm: Passed. + nb_array_pv: Passed. + nb_ec_array: Passed. + nb_ec_array_pv: Passed. + nb_ec_pv: Passed. + nb_ec_pv2: Passed. + nb_ec_real: Passed. + nb_ec_vector: Passed. + pr2486350: Passed. + pr534: Passed. + stime: Passed. + swrite: Passed. + time6: Passed. + time6b: Passed. + time6c: Passed. + concat1: Passed. + concat2: Passed. + constconcat1: Passed. + constconcat2: Passed. + rptconcat2: Passed. + sdw_lvalconcat2: Passed. + bool1: Passed. + compare_bool_reg: Passed. + constfunc8: Passed. + binary_nand: Passed. + binary_nor: Passed. + pr1528093: Passed. + br_gh456: Passed. + ca_64delay: Passed. + ca_time_real: Passed. + ca_var_delay: Passed. + cast_real_signed: Passed. + cast_real_unsigned: Passed. + delayed_sfunc: Passed. + pr1861212c: Passed. + pr1864110a: Passed. + pr1864110b: Passed. + pr1873372: Passed. + pr1880003: Passed. + pr1898293: Passed. + pr2123158: Passed. + pr2453002b: Passed. + pr2456943: Passed. + pr2715748: Passed. + pr2806474: Passed. + pr2976242: Passed. + pr2976242b: Passed. + pr2976242c: Passed - CE. + real8: Passed. + real_array: Passed. + real_array_nb: Passed. + real_concat_invalid1: Passed - CE. + real_mod_in_ca: Passed. + real_op_fail: Passed - CE. + real_pulse_clean: Passed. + real_pwr_in_ca: Passed. + real_select_invalid: Passed - CE. + real_wire_array: Passed. + real_wire_force_rel: Passed. + tern8: Passed. + br_gh99e: Passed. + pull371: Passed. + sv-2val-nets: Passed. + pr2476430: Passed. + eofmt_percent: Passed. + br_gh377: Passed. + cmdline_parm1: Passed. + array_dump: Passed. + pr2859628: Passed. + big_int: Passed. + ca_pow_signed: Passed. + urand: Passed. + race: Passed. + automatic_error4: Passed - CE. + array_lval_select3a: Passed - CE. + br605a: Passed - expected fail. + br605b: Passed - expected fail. + br971: Passed - expected fail. + br1005: Passed - CE. + br1015b: Passed - CE. + br_gh130b: Passed - CE. + br_gh386d: Passed - CE. + br_ml20150315b: Passed - CE. + sv_deferred_assert1: Passed - CE. + sv_deferred_assert2: Passed - CE. + sv_deferred_assume1: Passed - CE. + sv_deferred_assume2: Passed - CE. + pr1909940: Passed. + pr1909940b: Passed. + unnamed_generate_block: Passed. + br_gh497b: Passed - CE. + br_gh497d: Passed - CE. + br_gh497f: Passed - CE. + addsr: Passed. + addwide: Passed. + always3.1.1A: Passed - CE. + always3.1.1B: Passed - CE. + always3.1.1C: Passed. + always3.1.1D: Passed. + always3.1.1E: Passed. + always3.1.1F: Passed. + always3.1.1G: Passed. + always3.1.1H: Passed. + always3.1.1I: Passed. + always3.1.1J: Passed. + always3.1.1K: Passed. + always3.1.2A: Passed - CE. + always3.1.2B: Passed - CE. + always3.1.2C: Passed - CE. + always3.1.2D: Passed - CE. + always3.1.2E: Passed - CE. + always3.1.2F: Passed - CE. + always3.1.2G: Passed - CE. + always3.1.2H: Passed - CE. + always3.1.2I: Passed - CE. + always3.1.3A: Passed - CE. + always3.1.3B: Passed - CE. + always3.1.3B2: Passed. + always3.1.3C: Passed - CE. + always3.1.3D: Passed - CE. + always3.1.3D2: Passed. + always3.1.3E: Passed - CE. + always3.1.3E2: Passed. + always3.1.3F: Passed - CE. + always3.1.3F2: Passed. + always3.1.3G: Passed - CE. + always3.1.3H: Passed - CE. + always3.1.3J: Passed - CE. + always3.1.4A: Passed. + always3.1.4B: Passed. + always3.1.4C: Passed. + always3.1.4D: Passed. + always3.1.4E: Passed. + always3.1.4F: Passed. + always3.1.4G: Passed. + always3.1.4H: Passed. + always3.1.4I: Passed. + always3.1.5A: Passed. + always3.1.5B: Passed. + always3.1.5C: Passed. + always3.1.5D: Passed. + always3.1.5E: Passed. + always3.1.5F: Passed. + always3.1.6A: Passed. + always3.1.6B: Passed. + always3.1.6C: Passed. + always3.1.6D: Passed. + always3.1.7A: Passed. + always3.1.7B: Passed. + always3.1.7C: Passed. + always3.1.7D: Passed. + always3.1.8A: Passed. + always3.1.9A: Passed - CE. + always3.1.9B: Passed - CE. + always3.1.9C: Passed. + always3.1.9D: Passed. + always3.1.10A: Passed - CE. + always3.1.11A: Passed. + always3.1.11B: Passed. + always3.1.12A: Passed. + always3.1.12B: Passed. + always3.1.12C: Passed. + always_star_array_lval: Passed. + andnot1: Passed. + arith-unknown: Passed. + array4: Passed. + array5: Passed - CE. + array6: Passed. + array7: Passed. + array_lval_select1: Passed. + array_lval_select2: Passed. + array_lval_select3b: Passed - CE. + array_lval_select3c: Passed. + array_lval_select4a: Passed. + array_lval_select4b: Passed - CE. + array_lval_select5: Passed. + array_lval_select6: Passed. + array_packed_2d: Passed. + array_select: Passed. + array_select_a: Passed. + array_word_check: Passed. + array_word_width: Passed. + array_word_width2: Passed. + assign3.2A: Passed. + assign3.2B: Passed. + assign3.2C: Passed. + assign3.2D: Passed. + assign3.2E: Passed. + assign_add: Passed. + assign_deassign_pv: Passed. + assign_delay: Passed. + assign_deq: Passed. + assign_ge: Passed. + assign_le: Passed. + assign_mem1: Passed. + assign_mem2: Passed. + assign_nb1: Passed. + assign_nb2: Passed. + assign_neq: Passed. + attrib: Passed. + attrib01_module: Passed. + attrib02_port_decl: Passed. + attrib03_parameter: Passed. + attrib04_net_var: Passed. + attrib05_port_conn: Passed. + attrib06_operator_suffix: Passed. + attrib07_func_call: Passed. + attrib08_mod_inst: Passed. + attrib09_case: Passed. + automatic_error1: Passed - CE. + automatic_error2: Passed - CE. + automatic_error3: Passed - CE. + automatic_error5: Passed - CE. + automatic_error6: Passed - CE. + automatic_error7: Passed - CE. + automatic_error8: Passed - CE. + automatic_error9: Passed - CE. + automatic_error10: Passed - CE. + automatic_error11: Passed - RE. + automatic_error12: Passed - RE. + automatic_error13: Passed - RE. + automatic_events: Passed. + automatic_events2: Passed. + automatic_events3: Passed. + automatic_task: Passed. + automatic_task2: Passed. + automatic_task3: Passed. + bitwidth: Passed. + bitwidth2: Passed. + blankport: Passed. + block_only_with_var_def: Passed. + bnot: Passed. + br916a: Passed. + br916b: Passed. + br918a: Passed. + br918b: Passed. + br918c: Passed. + br918d: Passed. + br919: Passed. + br924: Passed - CE. + br930: Passed - CO. + br931: Passed. + br935: Passed. + br937: Passed. + br946: Passed. + br947: Passed. + br948: Passed. + br955: Passed. + br960a: Passed. + br960b: Passed. + br960c: Passed. + br960d: Passed. + br961: Passed. + br961a: Passed - CE. + br965: Passed. + br967: Passed. + br968: Passed. + br972: Passed. + br977: Passed. + br982: Passed - CE. + br982a: Passed - CE. + br982b: Passed - CE. + br988: Passed. + br990: Passed. + br991a: Passed. + br999: Passed. + br1000: Passed. + br1001: Passed. + br1006: Passed. + br1007: Passed. + br1008: Passed. + br1015a: Passed - CE. + br1019: Passed. + br1027: Passed. + br1027a: Passed - CE. + br1027c: Passed - CE. + br1027e: Passed - CE. + br1029a: Passed. + br1029b: Passed. + br1029c: Passed - CE. + br_gh6: Passed. + br_gh7: Passed. + br_gh8: Passed. + br_gh9: Passed. + br_gh11: Passed - CO. + br_gh12: Passed. + br_gh13: Passed. + br_gh14: Passed. + br_gh15: Passed. + br_gh18: Passed. + br_gh19: Passed. + br_gh19a: Passed. + br_gh19b: Passed. + br_gh22: Passed. + br_gh25a: Passed - CE. + br_gh25b: Passed - CE. + br_gh26: Passed - CE. + br_gh28: Passed. + br_gh30: Passed. + br_gh33: Passed. + br_gh37: Passed. + br_gh60a: Passed - CE. + br_gh62: Passed - CE. + br_gh79: Passed - CE. + br_gh99a: Passed. + br_gh99b: Passed. + br_gh99d: Passed. + br_gh99f: Passed. + br_gh99g: Passed. + br_gh99h: Passed. + br_gh99i: Passed. + br_gh99j: Passed. + br_gh99k: Passed. + br_gh99l: Passed. + br_gh99m: Passed. + br_gh99o: Passed. + br_gh99p: Passed. + br_gh99q: Passed. + br_gh99r: Passed. + br_gh99s: Passed. + br_gh99t: Passed. + br_gh99u: Passed. + br_gh103: Passed. + br_gh127a: Passed. + br_gh127b: Passed. + br_gh127c: Passed. + br_gh127d: Passed. + br_gh127e: Passed. + br_gh127f: Passed. + br_gh142: Passed - CE. + br_gh152: Passed - CE. + br_gh157: Passed. + br_gh162: Passed. + br_gh163: Passed - CE. + br_gh198: Passed. + br_gh199a: Passed. + br_gh199b: Passed. + br_gh209: Passed. + br_gh230: Passed - RE. + br_gh244a: Passed. + br_gh244b: Passed. + br_gh277a: Passed. + br_gh283a: Passed. + br_gh283b: Passed. + br_gh283c: Passed. + br_gh309: Passed. + br_gh315: Passed. + br_gh316a: Passed. + br_gh316b: Passed. + br_gh316c: Passed. + br_gh330: Passed. + br_gh345: Passed. + br_gh356a: Passed. + br_gh356b: Passed. + br_gh435: Passed. + br_gh484: Passed. + br_gh497a: Passed. + br_gh497c: Passed. + br_gh497e: Passed. + br_gh508b: Passed. + br_gh515: Passed. + br_gh531: Passed. + br_gh533: Passed - CE. + br_gh567: Passed. + br_ml20150315: Passed. + br_ml20150321: Passed - CE. + br_ml20150606: Passed. + br_mw20171108: Passed. + br_ml20190806a: Passed. + br_ml20190806b: Passed. + br_ml20190814: Passed. + bufif: Passed. + busbug: Passed. + ca_force: Passed. + ca_func: Passed. + ca_mult: Passed. + ca_pow_synth: Passed. + ca_pow_unsigned: Passed. + ca_real_logical: Passed. + ca_time: Passed. + case3.8A: Passed. + case3.8B: Passed. + case3.8C: Passed. + case3.8D: Passed. + casex3.9A: Passed. + casex3.9B: Passed. + casex3.9C: Passed. + casex3.9D: Passed. + casex3.9E: Passed. + casez3.10A: Passed. + casez3.10B: Passed. + casez3.10C: Passed. + casez3.10D: Passed. + casez3.10E: Passed. + cast_int: Passed. + check_constant_1: Passed - CE. + check_constant_2: Passed - CE. + check_constant_3: Passed - CE. + check_constant_4: Passed - CE. + check_constant_5: Passed - CE. + check_constant_6: Passed - CE. + check_constant_7: Passed - CE. + check_constant_8: Passed - CE. + check_constant_9: Passed - CE. + check_constant_10: Passed - CE. + check_constant_11: Passed - CE. + check_constant_12: Passed - CE. + check_constant_13: Passed - CE. + check_constant_14: Passed - CE. + check_constant_15: Passed - CE. + check_constant_16: Passed - CE. + check_constant_17: Passed - CE. + check_constant_18: Passed - CE. + check_constant_19: Passed - CE. + check_constant_20: Passed - CE. + cmos: Passed. + comment1: Passed - CE. + comp1000: Passed. + comp1001: Passed. + comp1001_fail3: Passed. + comp1001_fail4: Passed. + comp1001_fail5: Passed. + complex_lidx: Passed. + con_tri: Passed. + concat3: Passed. + concat4: Passed. + concat_zero_wid_fail: Passed - CE. + concat_zero_wid_fail2: Passed. + cond_band: Passed. + cond_wide: Passed. + cond_wide2: Passed. + const: Passed. + const2: Passed. + const3: Passed. + const4: Passed. + constadd: Passed. + constadd2: Passed. + constadd3: Passed. + constfunc1: Passed. + constfunc2: Passed. + constfunc3: Passed. + constfunc4: Passed. + constfunc5: Passed. + constfunc6: Passed. + constfunc7: Passed. + constfunc9: Passed. + constfunc10: Passed. + constfunc11: Passed. + constfunc12: Passed. + constfunc13: Passed. + constfunc14: Passed. + constfunc15: Passed. + constmult: Passed. + consttern: Passed. + contrib8.1: Passed. + contrib8.2: Passed. + contrib8.3: Passed - CE. + contrib8.4: Passed. + contrib8.5: Passed. + countdrivers1: Passed. + countdrivers2: Passed. + countdrivers3: Passed. + countdrivers4: Passed. + countdrivers5: Passed. + cprop: Passed. + credence20041209: Passed. + dangling_port: Passed. + dcomp1: Passed. + deassign3.4A: Passed. + decl_assign1: Passed. + def_nettype: Passed. + def_nettype_none: Passed - CE. + define1: Passed. + defparam: Passed. + defparam2: Passed. + defparam3: Passed. + defparam3.5: Passed. + defparam4: Passed. + delay: Passed. + delay2: Passed. + delay3: Passed. + delay4: Passed. + delay5: Passed. + delay_assign_nb: Passed. + delay_assign_nb2: Passed. + delay_var: Passed. + delayed_comp_reduct: Passed. + dff1: Passed. + disable3.6A: Passed. + disable3.6B: Passed. + disable_cleanup: Passed. + disable_fork: Passed. + disblock: Passed. + disblock2: Passed. + disp_dec: Passed. + disp_dec2: Passed. + disp_leading_z: Passed. + disp_parm: Passed. + disp_part: Passed. + div16: Passed. + dotinid: Passed. + drive_strength: Passed. + drive_strength1: Passed. + drive_strength2: Passed. + drive_strength3: Passed. + dummy7: Passed. + dump_memword: Passed. + dumpvars: Passed. + eeq: Passed. + else1: Passed. + else2: Passed. + else3: Passed. + elsif_test: Passed. + eq: Passed. + escape1: Passed. + escape2a: Passed - CO. + escape2b: Passed - CO. + escape2c: Passed - CO. + escape3: Passed. + escape4: Passed. + escape4b: Passed. + event2: Passed. + event3: Passed. + event3.15: Passed. + event_array: Passed - CE. + event_list: Passed. + event_list2: Passed. + event_list3: Passed. + extend: Passed. + fdisplay1: Passed. + fdisplay2: Passed. + fdisplay3: Passed - RE. + fdisplay_fail_fd: Passed. + fdisplay_fail_mcd: Passed. + fifo: Passed. + fopen1: Passed. + fopen2: Passed. + for3.16A: Passed. + force1: Passed. + force2: Passed. + force3.17A: Passed. + force3.17B: Passed. + force3.17C: Passed. + force_lval_part: Passed. + force_release_reg_pv: Passed. + force_release_wire8_pv: Passed. + force_release_wire_pv: Passed. + fork1: Passed. + fork3.19A: Passed. + fork3.19B: Passed. + format: Passed. + fr47: Passed. + fread: Passed. + fread-error: Passed - RE. + fscanf_u: Passed. + fscanf_u_warn: Passed. + fscanf_z: Passed. + fscanf_z_warn: Passed. + function1: Passed. + function2: Passed. + function3: Passed. + function3.11B: Passed. + function3.11C: Passed. + function3.11D: Passed. + function3.11F: Passed. + function4: Passed - CE. + function5: Passed - CO. + function6: Passed. + function7: Passed. + function8: Passed. + function9: Passed. + function_exp: Passed. + ga_and: Passed. + ga_mod: Passed. + ga_mod1: Passed. + ga_mod2: Passed. + ga_nand: Passed. + ga_nor: Passed. + ga_or: Passed. + ga_xnor: Passed. + ga_xor: Passed. + galan: Passed. + gate_connect1: Passed. + gate_connect2: Passed - CE. + gen_case_opt1: Passed. + gen_case_opt2: Passed. + gen_case_opt3: Passed. + gencrc: Passed. + generate_case: Passed. + generate_case2: Passed. + generate_case3: Passed. + generate_multi_loop: Passed. + genloop: Passed. + genvar_scopes: Passed. + hello1: Passed. + hier_ref_error: Passed - CE. + hierspace: Passed. + idiv1: Passed. + idiv2: Passed. + idiv3: Passed. + ifdef1: Passed. + ifdef2: Passed. + ifdef3: Passed. + ifdef4: Passed. + ifdef_fail: Passed - CE. + include1: Passed. + include2: Passed. + include3: Passed. + indef_width_concat: Passed - CE. + initmod: Passed. + initmod2: Passed. + inout: Passed. + inout2: Passed. + inout3: Passed. + inout4: Passed. + int_not_signext: Passed. + integer1lt: Passed. + integer2le: Passed. + integer3gt: Passed. + integer4ge: Passed. + integer5: Passed. + itor_rtoi: Passed. + land2: Passed. + land3: Passed. + land4: Passed. + landor1: Passed. + ldelay1: Passed. + ldelay2: Passed. + ldelay3: Passed. + ldelay4: Passed. + ldelay5: Passed. + lh_catadd: Passed. + lh_memcat: Passed. + lh_memcat2: Passed. + lh_memcat3: Passed. + lh_varindx: Passed. + lh_varindx2: Passed. + lh_varindx4: Passed. + lh_varindx5: Passed. + localparam_type: Passed. + long_div: Passed. + macro2: Passed. + macro_redefinition: Passed. + macro_replacement: Passed. + macsub: Passed. + mangle: Passed. + mangle_1: Passed. + many_drivers: Passed. + mcl2: Passed. + mem1: Passed. + mem2port: Passed. + memassign: Passed. + memidx: Passed. + memidxrng: Passed. + meminit: Passed. + meminit2: Passed. + memport_bs: Passed. + memref: Passed. + mhead_task: Passed. + mixed_type_div_mod: Passed. + mixed_width_case: Passed. + modparam: Passed. + module3.12A: Passed. + module3.12B: Passed. + modulus: Passed. + modulus2: Passed. + monitor: Passed. + monitor2: Passed. + monitor3: Passed. + mult1: Passed. + mult16: Passed. + mult2: Passed. + multi_bit_strength: Passed. + multi_driver_delay: Passed. + multiply_large: Passed. + muxtest: Passed. + named_event_no_edges: Passed - CE. + nb_assign: Passed. + nb_delay: Passed. + nblkorder: Passed. + negative_genvar: Passed. + negvalue: Passed. + neq1: Passed. + nested_func: Passed. + nested_impl_event1: Passed. + nested_impl_event2: Passed. + no_if_statement: Passed - CE. + no_timescale_in_module: Passed - CE. + npmos: Passed. + npmos2: Passed. + onehot: Passed. + p_monta: Passed. + par_mismatch: Passed - CE. + param-extend: Passed. + param-width: Passed. + param_add: Passed. + param_and: Passed. + param_and2: Passed. + param_band: Passed. + param_binv: Passed. + param_bor: Passed. + param_concat: Passed. + param_eq3: Passed. + param_expr: Passed. + param_mod: Passed. + param_select: Passed. + param_select2: Passed. + param_select3: Passed. + param_string: Passed. + param_tern: Passed. + param_tern2: Passed. + param_test1: Passed. + param_test2: Passed. + param_test3: Passed. + param_test4: Passed. + param_times: Passed. + parameter_type: Passed. + patch1268: Passed. + pca1: Passed. + pic: Passed. + port-test2: Passed. + port-test3: Passed - CE. + port-test4a: Passed - CE. + port-test4b: Passed - CE. + port-test5: Passed. + port-test6: Passed. + port-test7: Passed. + posedge: Passed. + pow-ca: Passed. + pow-const: Passed. + pow-proc: Passed. + pow_ca_signed: Passed. + pow_ca_unsigned: Passed. + pow_reg_signed: Passed. + pow_reg_unsigned: Passed. + pow_signed: Passed. + pow_unsigned: Passed. + pr136: Passed. + pr142: Passed. + pr183: Passed - CO. + pr224: Passed. + pr224a: Passed. + pr243: Passed. + pr245: Passed. + pr245_std: Passed. + pr273: Passed. + pr298: Passed. + pr304: Passed. + pr307: Passed. + pr307a: Passed. + pr312: Passed. + pr338: Passed - CO. + pr355: Passed. + pr377: Passed. + pr434: Passed. + pr445: Passed. + pr478: Passed. + pr487: Passed. + pr492: Passed. + pr508: Passed. + pr509: Passed. + pr509b: Passed. + pr511: Passed. + pr513: Passed. + pr522: Passed. + pr524: Passed. + pr527: Passed. + pr528: Passed. + pr528b: Passed. + pr529: Passed. + pr530a: Passed. + pr530b: Passed. + pr530c: Passed. + pr531a: Passed. + pr531b: Passed. + pr532: Passed. + pr532b: Passed. + pr533: Passed. + pr538: Passed. + pr540: Passed. + pr540b: Passed. + pr540c: Passed. + pr541: Passed. + pr542: Passed. + pr544: Passed. + pr547: Passed. + pr556: Passed. + pr564: Passed. + pr569: Passed. + pr572: Passed. + pr572b: Passed. + pr578: Passed. + pr584: Passed. + pr585: Passed. + pr587: Passed. + pr590: Passed. + pr594: Passed. + pr596: Passed. + pr602: Passed. + pr617: Passed. + pr632: Passed. + pr673: Passed. + pr675: Passed. + pr678: Passed. + pr690: Passed. + pr693: Passed. + pr699: Passed. + pr699b: Passed. + pr704: Passed. + pr707: Passed. + pr708: Passed. + pr710: Passed. + pr718: Passed. + pr722: Passed. + pr729: Passed. + pr734: Passed. + pr735: Passed. + pr748: Passed. + pr751: Passed. + pr757: Passed. + pr772: Passed. + pr810: Passed. + pr812: Passed. + pr820: Passed. + pr823: Passed. + pr841: Passed. + pr842: Passed. + pr848: Passed. + pr856: Passed. + pr859: Passed. + pr860: Passed. + pr872: Passed. + pr902: Passed. + pr905: Passed. + pr910: Passed. + pr913: Passed. + pr923: Passed. + pr938: Passed. + pr938b: Passed. + pr938b_std: Passed. + pr941: Passed. + pr973: Passed. + pr978: Passed. + pr985: Passed. + pr987: Passed. + pr990: Passed. + pr991: Passed. + pr993: Passed. + pr995: Passed. + pr1002: Passed. + pr1002a: Passed. + pr1007: Passed. + pr1008: Passed. + pr1022: Passed. + pr1024: Passed. + pr1026: Passed. + pr1029: Passed. + pr1032: Passed. + pr1033: Passed. + pr1065: Passed. + pr1072: Passed. + pr1077: Passed. + pr1087: Passed. + pr1101: Passed. + pr1115: Passed. + pr1353345: Passed. + pr1353345b: Passed. + pr1367855: Passed. + pr1380261: Passed. + pr1403406: Passed. + pr1403406a: Passed. + pr1403406b: Passed. + pr1421777: Passed. + pr1444055: Passed. + pr1449749a: Passed. + pr1455873: Passed. + pr1465769: Passed. + pr1467825: Passed - CO. + pr1474283: Passed. + pr1474316: Passed. + pr1474318: Passed. + pr1476440: Passed. + pr1477190: Passed. + pr1478121: Passed. + pr1478988: Passed. + pr1489568: Passed. + pr1489570: Passed. + pr1491355: Passed. + pr1492075: Passed. + pr1508882: Passed. + pr1510724: Passed. + pr1515168: Passed. + pr1520314: Passed - CO. + pr1522570: Passed. + pr1530426: Passed. + pr1561597: Passed. + pr1565544: Passed. + pr1565699b: Passed. + pr1570451: Passed. + pr1570451b: Passed. + pr1570635: Passed. + pr1570635b: Passed. + pr1574175: Passed. + pr1581580: Passed. + pr1587634: Passed - CO. + pr1587669: Passed. + pr1589497: Passed. + pr1598445: Passed. + pr1601896: Passed. + pr1601898: Passed. + pr1603313: Passed. + pr1603918: Passed. + pr1612693: Passed. + pr1623097: Passed. + pr1625912: Passed. + pr1628288: Passed. + pr1628300: Passed. + pr1629683: Passed. + pr1632861: Passed. + pr1634526: Passed. + pr1636409: Passed. + pr1637208: Passed. + pr1638985: Passed. + pr1639060: Passed. + pr1639064: Passed. + pr1639064b: Passed. + pr1639968: Passed. + pr1639971: Passed. + pr1645277: Passed. + pr1645518: Passed. + pr1648365: Passed. + pr1650842: Passed. + pr1657307: Passed. + pr1661640: Passed. + pr1662508: Passed. + pr1664684: Passed. + pr1675789: Passed. + pr1675789b: Passed. + pr1676071: Passed. + pr1676836: Passed. + pr1682887: Passed. + pr1687193: Passed. + pr1688717: Passed. + pr1690058: Passed. + pr1691599b: Passed. + pr1691709: Passed. + pr1693890: Passed. + pr1693921: Passed. + pr1694413: Passed. + pr1694427: Passed. + pr1695257: Passed - CO. + pr1695309: Passed. + pr1695322: Passed. + pr1695334: Passed. + pr1696137: Passed. + pr1697250: Passed. + pr1697732: Passed. + pr1698499: Passed. + pr1698658: Passed. + pr1698659: Passed. + pr1698820: Passed. + pr1699444: Passed. + pr1699519: Passed. + pr1701855: Passed. + pr1701855b: Passed. + pr1701889: Passed. + pr1701890: Passed. + pr1701921: Passed. + pr1702593: Passed. + pr1703120: Passed. + pr1703346: Passed. + pr1703959: Passed. + pr1704013: Passed - CE. + pr1704726a: Passed - CE. + pr1704726b: Passed. + pr1704726c: Passed - CE. + pr1704726d: Passed - CE. + pr1705027: Passed - CO. + pr1716276: Passed. + pr1717361: Passed. + pr1719055: Passed. + pr1723367: Passed. + pr1735724: Passed - CE. + pr1735822: Passed. + pr1735836: Passed. + pr1740476b: Passed. + pr1742910: Passed. + pr1745005: Passed. + pr1746401: Passed. + pr1746848: Passed. + pr1752353: Passed. + pr1752823a: Passed. + pr1752823b: Passed. + pr1755593: Passed. + pr1755629: Passed. + pr1758122: Passed. + pr1758135: Passed. + pr1763333: Passed - CE. + pr1770199: Passed. + pr1776485: Passed. + pr1777103: Passed. + pr1780480: Passed. + pr1784984: Passed. + pr1787394a: Passed. + pr1787394b: Passed. + pr1787423: Passed. + pr1787423b: Passed. + pr1787423c: Passed. + pr1792108: Passed. + pr1792152: Passed. + pr1792734: Passed. + pr1793157: Passed. + pr1794362: Passed. + pr1795005a: Passed. + pr1795005b: Passed. + pr1799904: Passed. + pr1804877: Passed. + pr1805837: Passed. + pr1812297: Passed. + pr1819452: Passed. + pr1820472: Passed. + pr1822658: Passed. + pr1823732: Passed. + pr1828642: Passed. + pr1830834: Passed. + pr1831724: Passed. + pr1832097a: Passed. + pr1832097b: Passed. + pr1833024: Passed - CE. + pr1833754: Passed - CE. + pr1841300: Passed. + pr1845683: Passed. + pr1851310: Passed. + pr1855504: Passed. + pr1861212a: Passed. + pr1862744a: Passed. + pr1862744b: Passed - CE. + pr1866215: Passed. + pr1866215b: Passed. + pr1867161a: Passed. + pr1867161b: Passed. + pr1867332: Passed - CO. + pr1868792: Passed. + pr1868991a: Passed. + pr1868991b: Passed - CO. + pr1869769: Passed. + pr1869772: Passed. + pr1869781: Passed. + pr1873146: Passed. + pr1875866: Passed. + pr1875866b: Passed. + pr1876798: Passed. + pr1877740: Passed. + pr1877743: Passed. + pr1878909: Passed. + pr1879226: Passed. + pr1883052: Passed. + pr1883052b: Passed. + pr1885847: Passed. + pr1887168: Passed. + pr1892959: Passed. + pr1892959b: Passed. + pr1898983: Passed. + pr1901125: Passed. + pr1903157: Passed - CO. + pr1903324: Passed. + pr1903343: Passed. + pr1903520: Passed. + pr1907192: Passed. + pr1912843: Passed. + pr1913918a: Passed. + pr1913918b: Passed. + pr1913918c: Passed. + pr1913937: Passed. + pr1916261: Passed. + pr1916261a: Passed - CE. + pr1921332: Passed - CO. + pr1924845: Passed. + pr1925356: Passed. + pr1925363a: Passed - CE. + pr1925363b: Passed - CE. + pr1932444: Passed. + pr1934744: Passed. + pr1936363: Passed. + pr1938138: Passed - CE. + pr1939165: Passed. + pr1946411: Passed. + pr1948110: Passed. + pr1948342: Passed. + pr1949025: Passed. + pr1950282: Passed. + pr1956211: Passed. + pr1958801: Passed. + pr1960545: Passed. + pr1960548: Passed. + pr1960558: Passed. + pr1960575: Passed. + pr1960596: Passed. + pr1960619: Passed. + pr1960625: Passed. + pr1960633: Passed. + pr1963240: Passed. + pr1963960: Passed. + pr1963962: Passed. + pr1971662a: Passed - CE. + pr1971662b: Passed - CE. + pr1978358: Passed. + pr1978358b: Passed. + pr1978358c: Passed. + pr1978358d: Passed. + pr1983762: Passed. + pr1985582: Passed. + pr1988302: Passed. + pr1988302b: Passed - CE. + pr1988310: Passed. + pr1990029: Passed. + pr1990164: Passed. + pr1990269: Passed. + pr1992244: Passed. + pr1992729: Passed. + pr1993479: Passed. + pr2001162: Passed. + pr2011429: Passed. + pr2013758: Passed. + pr2014673: Passed. + pr2015466: Passed. + pr2018235a: Passed. + pr2018235b: Passed. + pr2018305: Passed. + pr2019553: Passed. + pr2029336: Passed. + pr2030767: Passed. + pr2036953: Passed. + pr2038048: Passed. + pr2039632: Passed - CE. + pr2039694: Passed. + pr2043324: Passed. + pr2043585: Passed. + pr2051694: Passed - CE. + pr2051975: Passed - CE. + pr2053944: Passed. + pr2076363: Passed. + pr2076391: Passed. + pr2076425: Passed. + pr2085984: Passed. + pr2091455: Passed. + pr2109179: Passed. + pr2117473: Passed. + pr2117488: Passed. + pr2119622: Passed. + pr2121536: Passed. + pr2121536b: Passed. + pr2123190: Passed. + pr2132552: Passed. + pr2136787: Passed. + pr2138682: Passed. + pr2138979: Passed. + pr2138979b: Passed. + pr2138979c: Passed. + pr2138979d: Passed. + pr2139593: Passed. + pr2146620: Passed. + pr2146620b: Passed. + pr2146620c: Passed. + pr2146824: Passed. + pr2148401: Passed. + pr2152011: Passed. + pr2159630: Passed. + pr2166188: Passed. + pr2166311: Passed. + pr2169870: Passed. + pr2172606: Passed. + pr2172606b: Passed. + pr2181249: Passed. + pr2190323: Passed. + pr2201909: Passed. + pr2201909b: Passed. + pr2202706: Passed. + pr2202706b: Passed. + pr2202706c: Passed. + pr2202846a: Passed. + pr2202846b: Passed. + pr2202846c: Passed. + pr2208681: Passed. + pr2215342: Passed. + pr2219441: Passed. + pr2219441b: Passed. + pr2224845: Passed. + pr2224949: Passed. + pr2233180: Passed. + pr2233180b: Passed. + pr2233180c: Passed. + pr2233192: Passed. + pr2233192b: Passed. + pr2233192c: Passed. + pr2248925: Passed. + pr2251119: Passed. + pr2257003: Passed. + pr2257003b: Passed. + pr2270035: Passed. + pr2276163: Passed. + pr2281479: Passed. + pr2305307: Passed. + pr2305307b: Passed. + pr2305307c: Passed. + pr2306259: Passed. + pr2350934: Passed. + pr2350934b: Passed. + pr2350988: Passed. + pr2352834: Passed. + pr2355304: Passed. + pr2355304b: Passed. + pr2358264: Passed. + pr2358848: Passed. + pr2395378a: Passed - CE. + pr2395378b: Passed - CE. + pr2395378c: Passed - CE. + pr2395835: Passed. + pr2425055a: Passed. + pr2425055b: Passed. + pr2425055c: Passed. + pr2428890: Passed. + pr2428890b: Passed. + pr2434688: Passed. + pr2434688b: Passed. + pr2450244: Passed. + pr2453002: Passed. + pr2459681: Passed. + pr2470181a: Passed. + pr2470181b: Passed. + pr2503208: Passed. + pr2528915: Passed - CE. + pr2533175: Passed. + pr2579479: Passed. + pr2580730: Passed. + pr2593733: Passed. + pr2597278: Passed. + pr2597278b: Passed - CE. + pr2605006: Passed. + pr2673846: Passed. + pr2688910: Passed. + pr2709097: Passed. + pr2715547: Passed. + pr2715558: Passed. + pr2715558b: Passed. + pr2721213: Passed. + pr2722330a: Passed. + pr2722330b: Passed. + pr2722339a: Passed. + pr2722339b: Passed. + pr2723712: Passed. + pr2725700a: Passed. + pr2725700b: Passed. + pr2725700c: Passed. + pr2728032: Passed. + pr2728547: Passed. + pr2728812a: Passed. + pr2728812b: Passed - CE. + pr2728812c: Passed - CE. + pr2745281: Passed. + pr2781595: Passed. + pr2785294: Passed. + pr2788686: Passed. + pr2790236: Passed. + pr2792883: Passed - CE. + pr2792897: Passed. + pr2794144: Passed - CE. + pr2800985a: Passed. + pr2800985b: Passed - RE. + pr2801134: Passed. + pr2801662: Passed. + pr2809288: Passed - CE. + pr2815398a: Passed. + pr2815398a_std: Passed. + pr2815398b: Passed. + pr2818823: Passed. + pr2823414: Passed - CE. + pr2823711: Passed. + pr2824189: Passed. + pr2829776: Passed. + pr2829776b: Passed. + pr2832234: Passed. + pr2834340: Passed. + pr2834340b: Passed. + pr2835632a: Passed. + pr2835632b: Passed. + pr2837451: Passed. + pr2842185: Passed. + pr2842621: Passed. + pr2842621_std: Passed. + pr2848986: Passed - CE. + pr2849783: Passed. + pr2865563: Passed. + pr2877564: Passed - CE. + pr2883958: Passed. + pr2885048: Passed. + pr2890322: Passed. + pr2901556: Passed. + pr2909386a: Passed. + pr2909386b: Passed. + pr2909414: Passed. + pr2909555: Passed. + pr2913404: Passed. + pr2913416: Passed. + pr2913438a: Passed. + pr2913438b: Passed. + pr2913927: Passed. + pr2918095: Passed. + pr2922063: Passed. + pr2922063a: Passed. + pr2922063b: Passed. + pr2924354: Passed. + pr2929913: Passed. + pr2930506: Passed. + pr2937417: Passed. + pr2937417b: Passed. + pr2937417c: Passed. + pr2941939: Passed. + pr2943394: Passed. + pr2951657: Passed. + pr2969724: Passed. + pr2971207: Passed. + pr2972866: Passed. + pr2973532: Passed. + pr2974051: Passed. + pr2974216: Passed. + pr2974216b: Passed. + pr2974294: Passed. + pr2985542: Passed. + pr2986497: Passed - CO. + pr2986528: Passed. + pr2991457: Passed. + pr2991457b: Passed. + pr2994193: Passed. + pr2998515: Passed. + pr3011327: Passed. + pr3012758: Passed. + pr3015421: Passed - CE. + pr3022502: Passed. + pr3024131: Passed. + pr3039548: Passed. + pr3044843: Passed. + pr3054101a: Passed. + pr3054101b: Passed. + pr3054101c: Passed. + pr3054101d: Passed. + pr3054101e: Passed. + pr3054101f: Passed. + pr3054101g: Passed. + pr3054101h: Passed. + pr3061015a: Passed - CE. + pr3061015b: Passed - CE. + pr3061015c: Passed - CE. + pr3064375: Passed. + pr3064511: Passed. + pr3077640: Passed. + pr3078759: Passed - CO. + pr3098439: Passed. + pr3098439a: Passed. + pr3098439b: Passed. + pr3103880: Passed. + pr3104254: Passed. + pr3112073a: Passed - CE. + pr3149494: Passed. + pr3190941: Passed - CE. + pr3190948: Passed. + pr3194155: Passed. + pr3197861: Passed. + pr3197917: Passed. + pr3270320: Passed - CE. + pr3284821: Passed. + pr3292735: Passed. + pr3296466a: Passed. + pr3296466b: Passed. + pr3296466c: Passed. + pr3296466d: Passed. + pr3306516: Passed. + pr3309391: Passed. + pr3368642: Passed. + pr3409749: Passed. + pr3437290a: Passed. + pr3437290b: Passed. + pr3437290c: Passed. + pr3441576: Passed. + pr3445452: Passed. + pr3452808: Passed. + pr3465541: Passed. + pr3477107: Passed. + pr3499807: Passed. + pr3522653: Passed. + pr3527022: Passed. + pr3527694: Passed. + pr3534422: Passed. + pr3539372: Passed. + pr3549328: Passed - CE. + pr3557493: Passed. + pr3561350: Passed. + pr3563412: Passed. + pr3571573: Passed. + pr3582052: Passed. + pr3587570: Passed. + pr3592746: Passed. + prng: Passed. + ptest001: Passed. + ptest002: Passed. + ptest003: Passed. + ptest004: Passed. + ptest005: Passed. + ptest006: Passed. + ptest007: Passed. + ptest008: Passed. + ptest009: Passed. + ptest010: Passed. + ptest011: Passed. + pullupdown: Passed. + pullupdown2: Passed. + pullupdown3: Passed. + pv_undef_sig_sel: Passed. + qmark: Passed. + qmark1: Passed. + qmark3: Passed. + qmark5: Passed. + qmark6: Passed. + queue: Passed. + queue_fail: Passed - RE. + queue_stat: Passed. + ram16x1: Passed. + readmem-error: Passed. + readmem-invalid: Passed - RE. + readmemb1: Passed. + readmemb2: Passed. + readmemb3: Passed. + readmemh1: Passed. + readmemh1a: Passed. + readmemh2: Passed. + readmemh3: Passed. + readmemh4: Passed. + readmemh5: Passed - CE. + real: Passed. + real2: Passed. + real3: Passed. + real5: Passed. + real6: Passed. + real7: Passed. + real9: Passed. + real10: Passed. + real11: Passed. + real_assign_deassign: Passed. + real_concat_invalid2: Passed - CE. + real_delay: Passed. + real_events: Passed. + real_force_rel: Passed. + real_invalid_ops: Passed - CE. + real_logical: Passed. + real_reg_force_rel: Passed. + recursive_func: Passed. + recursive_task: Passed. + redef_net_error: Passed - CE. + redef_reg_error: Passed - CE. + repeat2: Passed. + repeat_expr_probe: Passed. + repl_zero_wid_fail: Passed - CE. + repl_zero_wid_pass: Passed. + resetall: Passed. + resetall2: Passed. + resolv1: Passed. + rise_fall_decay1: Passed. + rise_fall_decay2: Passed. + rise_fall_delay1: Passed. + rise_fall_delay2: Passed. + rise_fall_delay3: Passed. + rl_pow: Passed. + rnpmos: Passed. + rnpmos2: Passed. + rop: Passed. + rptconcat: Passed. + rtran: Passed. + rtranif0: Passed. + rtranif1: Passed. + scan-invalid: Passed - RE. + scanf: Passed. + scanf2: Passed. + scanf3: Passed. + scanf4: Passed. + sched1: Passed. + sched2: Passed. + schedule: Passed. + scope1: Passed. + scope2: Passed. + scope2b: Passed - CE. + scope4: Passed. + scope5: Passed. + scoped_events: Passed. + sdf1: Passed. + sdf2: Passed. + sdf3: Passed. + sdf4: Passed. + sdf5: Passed. + sdf6: Passed. + sdf7: Passed. + sdf8: Passed. + sdf_del_max: Passed. + sdf_del_min: Passed. + sdf_del_typ: Passed. + sdf_esc_id: Passed. + sdw_always1: Passed. + sdw_always2: Passed. + sdw_always3: Passed. + sdw_array: Passed. + sdw_assign: Passed. + sdw_dsbl: Passed. + sdw_force: Passed. + sdw_function1: Passed. + sdw_function2: Passed. + sdw_function3: Passed. + sdw_function4: Passed. + sdw_function5: Passed. + sdw_instmod1: Passed. + sdw_instmod2: Passed. + sdw_int: Passed. + sdw_lvalconcat: Passed. + sdw_param1: Passed. + sdw_param2: Passed. + sdw_release: Passed. + sdw_stmt002: Passed. + sdw_task1: Passed. + sdw_task2: Passed. + sel_rval_bit_ob: Passed. + sel_rval_part_ob: Passed. + select: Passed. + select2: Passed. + select3: Passed. + select4: Passed. + select5: Passed. + select6: Passed. + select7: Passed. + select8: Passed. + select_padding: Passed. + shellho1: Passed. + shift1: Passed. + shift2: Passed. + shift3: Passed. + shift4: Passed. + shift5: Passed. + shift_pad: Passed. + signed1: Passed. + signed2: Passed. + signed3: Passed. + signed4: Passed. + signed5: Passed. + signed6: Passed. + signed7: Passed. + signed8: Passed. + signed9: Passed. + signed10: Passed. + signed11: Passed. + signed12: Passed. + signed13: Passed. + signed_a: Passed. + signed_equality: Passed. + signed_net_display: Passed. + signed_part: Passed. + signed_pv: Passed. + sp2: Passed. + specify1: Passed - CO. + specify2: Passed. + specify3: Passed. + specify4: Passed. + specify5: Passed. + specify_01: Passed. + sqrt32: Passed. + sscanf_u: Passed. + sscanf_z: Passed. + stask_parm1: Passed. + stask_parm2: Passed. + stask_sens_null_arg: Passed. + string1: Passed. + string2: Passed. + string3: Passed. + string4: Passed. + string5: Passed. + string7: Passed. + string8: Passed. + string9: Passed. + string10: Passed. + string11: Passed. + string12: Passed. + supply1: Passed. + supply2: Passed. + switch_primitives: Passed. + sys_func_task_error: Passed - RE. + talu: Passed. + task-scope: Passed. + task3.14A: Passed. + task3.14B: Passed. + task3.14C: Passed. + task3.14D: Passed. + task3.14E: Passed. + task3.14F: Passed. + task_bypath: Passed. + task_inpad: Passed. + task_iotypes: Passed. + task_iotypes2: Passed. + task_mem: Passed. + task_noop: Passed. + task_noop2: Passed - CO. + task_omemw2: Passed. + task_omemw3: Passed - CO. + task_port_size: Passed. + task_scope: Passed. + tern1: Passed. + tern2: Passed - CO. + tern4: Passed. + tern5: Passed. + tern6: Passed. + tern7: Passed. + tern9: Passed. + tern10: Passed. + test_bufif0: Passed. + test_bufif1: Passed. + test_disphob: Passed. + test_dispwided: Passed. + test_extended: Passed. +test_mos_strength_reduction: Passed. + test_nmos: Passed. + test_notif0: Passed. + test_notif1: Passed. + test_pmos: Passed. + test_rnmos: Passed. + test_rpmos: Passed. + test_width: Passed. + time1: Passed. + time2: Passed. + time3: Passed. + time4: Passed. + time5: Passed. + time7: Passed. + time8: Passed. + timeform1: Passed. + timeform2: Passed. + timescale1: Passed. + timescale2: Passed. + timescale3: Passed - CE. + tran: Passed. + tranif0: Passed. + tranif1: Passed. + tran-keeper: Passed. + tri0: Passed. + tri0b: Passed. + tri1: Passed. + tri2: Passed. + tri3: Passed. + triand: Passed. + trior: Passed. + types1: Passed. + udp_bufg: Passed. + udp_bufg2: Passed. + udp_bx: Passed. + udp_delay_fail: Passed - CE. + udp_dff: Passed. + udp_dff_std: Passed. + udp_eval_arg: Passed. + udp_jkff: Passed. + udp_real_delay: Passed. + udp_sched: Passed. + udp_x: Passed. + unary_and: Passed. + unary_lnot1: Passed. + unary_lnot2: Passed. + unary_lnot3: Passed. + unary_minus: Passed. + unary_minus1: Passed. + unary_minus2: Passed. + unary_minus3: Passed. + unary_minus4: Passed. + unary_nand: Passed. + unary_nand2: Passed. + unary_nor: Passed. + unary_nor2: Passed. + unary_not: Passed. + unary_or: Passed. + unary_xnor1: Passed. + unary_xnor2: Passed. + unary_xor: Passed. + uncon_drive: Passed. + undef: Passed. + undef_lval_select: Passed. + undef_lval_select2: Passed. + undef_lval_select3a: Passed. + undef_lval_select3b: Passed - CE. + undef_lval_select3c: Passed - CE. + undef_lval_select4a: Passed. + undef_lval_select4b: Passed - CE. + undef_lval_select4c: Passed - CE. + undef_lval_select5: Passed. + undefined_shift: Passed. + urand_r: Passed. + urand_r2: Passed. + urand_r3: Passed. + uwire: Passed. + uwire2: Passed. + uwire_fail: Passed - CE. + vardly: Passed. + varlsfht: Passed. + varlsfht1: Passed. + varlsfht2: Passed. + varrshft: Passed. + varrshft1: Passed. + varrshft2: Passed. + vcd-dup: Passed. + vector: Passed. + verify_two_var_delays: Passed. + vvp_scalar_value: Passed. + wait1: Passed. + wait2: Passed. + wait3: Passed. + warn_opt_sys_tf: Passed - RE. + wildsense: Passed. + wildsense2: Passed. + wireadd1: Passed. + wireeq: Passed. + wirege: Passed. + wireland: Passed. + wirele: Passed. + wiremod1: Passed. + wiresl: Passed. + wiresl2: Passed. + wiresr: Passed. + wiresub1: Passed. + wirexor1: Passed. + writemem-error: Passed. + writemem-invalid: Passed - RE. + writememb1: Passed. + writememb2: Passed. + writememh1: Passed. + writememh2: Passed. + xnor_test: Passed. + z1: Passed. + z2: Passed. + zero_repl: Passed. + zero_repl_fail: Passed - CE. + cmpi: Passed. + analog1: ==> Failed - running iverilog. + analog2: ==> Failed - running iverilog. + br_gh99c: Passed. + cast_int_ams: Passed. + constfunc4_ams: Passed. + scaled_real: Passed. + test_vams_math: Passed. + value_range1: Passed. + value_range2: Passed. + value_range3: Passed - CE. + vams_abs1: Passed. + vams_abs2: Passed. + wreal: Passed. + always4A: Passed - CE. + always4B: Passed - CE. + always_comb: Passed. + always_comb_fail: Passed - CE. + always_comb_fail3: Passed - CE. + always_comb_fail4: Passed - CE. + always_comb_no_sens: Passed. + always_comb_rfunc: Passed. + always_comb_trig: Passed. + always_comb_warn: Passed. + always_ff: Passed. + always_ff_fail: Passed - CE. + always_ff_fail2: Passed - CE. + always_ff_fail3: Passed - CE. + always_ff_fail4: Passed - CE. + always_ff_no_sens: Passed - CE. + always_ff_warn: Passed. + always_ff_warn_sens: Passed. + always_latch: Passed. + always_latch_fail: Passed - CE. + always_latch_fail3: Passed - CE. + always_latch_fail4: Passed - CE. + always_latch_no_sens: Passed - CE. + always_latch_trig: Passed. + always_latch_warn: Passed. + array_size: Passed. + array_string: Passed. + array_unpacked_sysfunct: Passed. + array_packed: Passed. + assign_op_concat: Passed. + assign_op_type: Passed. + bitp1: Passed. + bits: Passed. + bits2: Passed. + br884: Passed. + br917a: Passed. + br917b: Passed. + br917c: Passed. + br917d: Passed. + br921: Passed. + br932a: Passed. + br932b: Passed. + br936: Passed. + br956: Passed. + br959: Passed. + br962: Passed. + br963: Passed. + br973: Passed. + br974a: Passed. + br974b: Passed. + br974c: Passed. + br975: Passed - CE. + br979: Passed. + br991b: Passed - CE. + br1003a: Passed. + br1003b: Passed. + br1003c: Passed. + br1003d: Passed. + br1004: Passed. + br1025: Passed. + br1027b: Passed. + br1027d: Passed. + br1027f: Passed. + br_gh4: Passed. + br_gh4a: Passed. + br_gh72a: Passed. + br_gh72b: Passed. + br_gh72b_fail: Passed - CE. + br_gh104a: Passed. + br_gh104b: Passed. + br_gh105a: Passed. + br_gh105b: Passed. + br_gh112a: Passed. + br_gh112b: Passed. + br_gh112c: Passed. + br_gh112d: Passed. + br_gh112e: Passed. + br_gh112f: Passed. + br_gh129: Passed. + br_gh130a: Passed - CE. + br_gh165: Passed. + br_gh164a: Passed. + br_gh164b: Passed. + br_gh164c: Passed. + br_gh164d: Passed. + br_gh164e: Passed. + br_gh167a: Passed. + br_gh167b: Passed. + br_gh177a: Passed. + br_gh177b: Passed. + br_gh194: Passed. + br_gh219: Passed. + br_gh220: Passed. + br_gh224: Passed. + br_gh226: Passed. + br_gh231: Passed. + br_gh243: Passed. + br_gh265: Passed - CE. + br_gh277b: Passed. + br_gh280: Passed. + br_gh281: Passed. + br_gh281b: Passed. + br_gh289a: Passed. + br_gh289b: Passed. + br_gh289c: Passed. + br_gh289d: Passed. + br_gh337: Passed. + br_gh361: Passed. + br_gh365: Passed. + br_gh366: Passed. + br_gh368: Passed. + br_gh374: Passed. + br_gh386a: Passed. + br_gh386b: Passed. + br_gh386c: Passed - CE. + br_gh388: Passed. + br_gh391: Passed. + br_gh411: Passed. + br_gh418: Passed. + br_gh433: Passed. + br_gh437: Passed. + br_gh440: Passed - CE. + br_gh443: Passed. + br_gh445: Passed. + br_gh461: Passed. + br_gh477: Passed. + br_gh478: Passed. + br_gh498: Passed. + br_gh508a: Passed. + br_gh527: Passed. + br_gh530: Passed - CO. + br_gh540: Passed. + br_gh553: Passed. + br_gh556: Passed. + br_gh568: Passed. + br_ml20171017: Passed. + br_ml20180227: Passed - CE. + br_ml20180309a: Passed. + br_ml20180309b: Passed. + br_ml20181012a: Passed - CE. + br_ml20181012b: Passed - CE. + br_ml20181012c: Passed - CE. + br_ml20181012d: Passed - CE. + br_ml20191221: Passed. + br_mw20200501: Passed. + case_priority: Passed. + case_unique: Passed. + cast_real: Passed. + cfunc_assign_op_mixed: Passed. + cfunc_assign_op_pv: Passed. + cfunc_assign_op_real: Passed. + cfunc_assign_op_vec: Passed. + clkgen_bit: Passed. + clkgen_logic: Passed. + clkgen_net: Passed. + clkgen_reg: Passed. + disable_fork_cmd: Passed. + display_bug: Passed. + edge: Passed. + enum_base_range: Passed. + enum_elem_ranges: Passed. + enum_dims_invalid: Passed - CE. + enum_next: Passed. + enum_ports: Passed. + enum_test1: Passed. + enum_test2: Passed. + enum_test3: Passed - CE. + enum_test4: Passed. + enum_test5: Passed - CE. + enum_test6: Passed - CE. + enum_test7: Passed - CE. + enum_test8: Passed. + enum_value_expr: Passed. + enum_values: Passed. + escaped_macro_name: Passed. + extra_semicolon: Passed. + fileline: Passed. + fileline2: Passed. + final: Passed. + final2: Passed. + first_last_num: Passed. + fork_join_any: Passed. + fork_join_dis: Passed. + fork_join_none: Passed. + fr49: Passed. + func_init_var1: Passed. + func_init_var2: Passed. + func_init_var3: Passed. + function10: Passed - CO. + function11: Passed - CE. + function12: Passed. + genvar_inc_dec: Passed. + ibit_test: Passed. + ibyte_test: Passed. + iint_test: Passed. + ilongint_test: Passed. + implicit_cast1: Passed. + implicit_cast2: Passed. + implicit_cast3: Passed. + implicit_cast4: Passed. + implicit_cast5: Passed. + implicit_cast6: Passed. + implicit_cast7: Passed. + implicit_cast8: Passed. + implicit_cast9: Passed. + implicit_cast10: Passed. + implicit_cast11: Passed. + implicit_cast12: Passed. + implicit_cast13: Passed. + implicit-port1: Passed. + implicit-port2: Passed - CE. + implicit-port3: Passed - CE. + implicit-port4: Passed. + implicit-port5: Passed. + implicit-port6: Passed - CE. + implicit-port7: Passed. + inc_dec_stmt: Passed. + int_param: Passed. + ishortint_test: Passed. + iuint1: Passed. + l_equiv: Passed. + l_equiv_ca: Passed. + l_equiv_const: Passed. + line_directive: Passed. + localparam_query: Passed. + localparam_type2: Passed. + logical_short_circuit: Passed. + logp2: Passed. + mod_inst_pkg: Passed. + named_begin: Passed. + named_begin_fail: Passed - CE. + named_fork: Passed. + named_fork_fail: Passed - CE. + packeda: Passed. + packeda2: Passed. + parameter_type2: Passed. + parpkg_test: Passed. + parpkg_test2: Passed. + parpkg_test3: Passed. + part_sel_port: Passed. + plus_5: Passed. + pr3366114: Passed. + pr3366217a: Passed - CE. + pr3366217b: Passed - CE. + pr3366217c: Passed - CE. + pr3366217d: Passed - CE. + pr3366217e: Passed. + pr3366217f: Passed. + pr3366217g: Passed - CE. + pr3366217h: Passed. + pr3366217i: Passed. + pr3390385: Passed. + pr3390385b: Passed. + pr3390385c: Passed. + pr3390385d: Passed. + pr3462145: Passed. + pr3515542: Passed - CE. + pr3534333: Passed. + pr3576165: Passed. + program2: Passed. + program2b: Passed. + program3: Passed. + program3a: Passed. + program3b: Passed - CE. + program4: Passed. + program5a: Passed - CE. + program5b: Passed - CE. + program_hello: Passed. + program_hello2: Passed - CE. + sbyte_test: Passed. + scalar_vector: Passed. + sf_countbits: Passed. + sf_countbits_fail: Passed - RE. + sf_countones: Passed. + sf_countones_fail: Passed - RE. + sf_isunknown: Passed. + sf_isunknown_fail: Passed - RE. + sf_onehot: Passed. + sf_onehot_fail: Passed - RE. + sf_onehot0: Passed. + sf_onehot0_fail: Passed - RE. + sformatf: Passed. + simple_byte: Passed. + simple_int: Passed. + simple_longint: Passed. + simple_shortint: Passed. + sint_test: Passed. + size_cast: Passed. + size_cast2: Passed. + size_cast3: Passed. + size_cast4: Passed. + size_cast5: Passed. + slongint_test: Passed. + sshortint_test: Passed. + string_events: Passed. + string_index: Passed. + struct1: Passed. + struct2: Passed. + struct3: Passed. + struct3b: Passed. + struct4: Passed. + struct5: Passed. + struct6: Passed. + struct7: Passed. + struct8: Passed. + struct9: Passed. + struct_packed_array: Passed. + struct_packed_array2: Passed. + struct_packed_sysfunct: Passed. + struct_packed_write_read2: Passed. + sv-constants: Passed. + sv_array_assign_pattern2: Passed. + sv_cast_integer: Passed. + sv_cast_integer2: Passed. + sv_cast_string: Passed. + sv_class1: Passed. + sv_class2: Passed. + sv_class3: Passed. + sv_class4: Passed. + sv_class5: Passed. + sv_class6: Passed. + sv_class7: Passed. + sv_class8: Passed. + sv_class9: Passed. + sv_class10: Passed. + sv_class11: Passed. + sv_class12: Passed. + sv_class13: Passed. + sv_class14: Passed. + sv_class15: Passed. + sv_class16: Passed. + sv_class17: Passed. + sv_class18: Passed. + sv_class19: Passed. + sv_class20: Passed. + sv_class21: Passed. + sv_class22: Passed. + sv_class23: Passed. + sv_class24: Passed. + sv_darray1: Passed. + sv_darray2: Passed. + sv_darray3: Passed. + sv_darray4: Passed. + sv_darray5: Passed. + sv_darray5b: Passed. + sv_darray6: Passed. + sv_darray_args1: Passed. + sv_darray_args2: Passed. + sv_darray_args2b: Passed. + sv_darray_args3: Passed. + sv_darray_args4: Passed. + sv_darray_decl_assign: Passed. + sv_darray_function: Passed. + sv_darray_signed: Passed. + sv_darray_word_size: Passed. + sv_default_port_value1: Passed. + sv_default_port_value2: Passed. + sv_default_port_value3: Passed - CE. + sv_end_label: Passed. + sv_end_label_fail: Passed - CE. + sv_end_labels: Passed. + sv_end_labels_bad: Passed - CE. + sv_enum1: Passed. + sv_for_variable: Passed. + sv_foreach1: Passed. + sv_foreach2: Passed. + sv_foreach3: Passed. + sv_foreach4: Passed. + sv_foreach5: Passed. + sv_immediate_assert: Passed. + sv_immediate_assume: Passed. + sv_macro: Passed. + sv_macro2: Passed. + sv_macro3a: Passed. + sv_macro3b: Passed. + sv_new_array_error: Passed - CE. + sv_package: Passed. + sv_package2: Passed. + sv_package3: Passed. + sv_package4: Passed. + sv_package5: Passed. + sv_packed_port1: Passed. + sv_packed_port2: Passed. + sv_param_port_list: Passed. + sv_pkg_class: Passed. + sv_port_default1: Passed. + sv_port_default2: Passed. + sv_port_default3: Passed. + sv_port_default4: Passed. + sv_port_default5: Passed. + sv_port_default6: Passed. + sv_port_default7: Passed. + sv_port_default8: Passed. + sv_port_default9: Passed. + sv_port_default10: Passed. + sv_port_default11: Passed. + sv_port_default12: Passed. + sv_port_default13: Passed - CE. + sv_port_default14: Passed - CE. + sv_queue1: Passed. + sv_queue2: Passed. + sv_queue3: Passed. + sv_queue_real: Passed. + sv_queue_real_bounded: Passed. + sv_queue_real_fail: Passed - CE. + sv_queue_string: Passed. + sv_queue_string_bounded: Passed. + sv_queue_string_fail: Passed - CE. + sv_queue_vec: Passed. + sv_queue_vec_bounded: Passed. + sv_queue_vec_fail: Passed - CE. + sv_root_class: Passed. + sv_root_func: Passed. + sv_root_task: Passed. + sv_string1: Passed. + sv_string2: Passed. + sv_string3: Passed. + sv_string4: Passed. + sv_string5: Passed. + sv_timeunit_prec1: Passed. + sv_timeunit_prec2: Passed. + sv_timeunit_prec3a: Passed. + sv_timeunit_prec3b: Passed. + sv_timeunit_prec3c: Passed. + sv_timeunit_prec3d: Passed. + sv_timeunit_prec4a: Passed. + sv_timeunit_prec4b: Passed. + sv_timeunit_prec_fail1: Passed - CE. + sv_timeunit_prec_fail2: Passed - CE. + sv_typedef_scope: Passed. + sv_union1: Passed. + sv_union1b: Passed. + sv_union2: Passed. + sv_union2b: Passed. + sv_union3: Passed. + sv_union3b: Passed. + sv_union4b: Passed. + sv_unit1b: Passed. + sv_unit1c: Passed. + sv_unit2b: Passed. + sv_unit3b: Passed. + sv_unit4b: Passed. + sv_unpacked_port: Passed. + sv_unpacked_port2: Passed. + sv_unpacked_wire: Passed. + sv_unpacked_wire2: Passed. + sv_uwire1: Passed. + sv_uwire2: Passed. + sv_uwire3: Passed. + sv_uwire4: Passed. + sv_var_init1: Passed. + sv_var_init2: Passed. + sv_wildcard_import1: Passed. + sv_wildcard_import2: Passed. + sv_wildcard_import3: Passed. + sv_wildcard_import4: Passed - CE. + sv_wildcard_import5: Passed - CE. + sv_wildcard_import6: Passed. + sv_wildcard_import7: Passed. + sys_func_as_task: Passed. + task_init_assign: Passed. + task_init_var1: Passed. + task_init_var2: Passed. + task_init_var3: Passed. + task_scope2: Passed. + test_inc_dec: Passed. + test_tliteral: Passed. + timeliteral: Passed. + two_state_display: Passed. + ubyte_test: Passed. + uint_test: Passed. + ulongint_test: Passed. + undef_lval_select_SV: Passed. + unp_array_typedef: Passed. + packed_dims_invalid_class: Passed - CE. + packed_dims_invalid_module: Passed - CE. + ushortint_test: Passed. + vvp_recv_vec4_pv: Passed. + wait_fork: Passed. + sf1289: Passed. + wild_cmp_const: Passed. + wild_cmp_net: Passed. + wild_cmp_var: Passed. + wild_cmp_err: Passed - CE. + wild_cmp_err2: Passed - CE. + gh161a: Passed. + gh161b: Passed. + pull371b: Passed. + br_gh175: Passed. + br_gh307: Passed. + br_gh383a: Passed. + br_gh383b: Passed. + br_gh383c: Passed. + br_gh383d: Passed. + br_gh390a: Passed - CE. + br_gh390b: Passed. + br_gh412: Passed. + br_gh414: Passed. + br_gh436: Passed. + br_gh451: Passed. + br_gh453: Passed. + br_gh460: Passed. + br942: Passed. + br943_944: Passed. + br985: Passed. + br986: Passed. + br987: Passed. + ivlh_event: Passed. + ivlh_rising_falling: Passed. + ivlh_textio: Passed. + test_dec2to4: Passed. + test_enumsystem: Passed. + test_forgen: Passed. + test_gxor: Passed. + test_mux2to1: Passed. + test_signal_init_assign: Passed. + test_system: Passed. + test_timebase: Passed. + test_varray1: Passed. + test_when_else: Passed. + test_work14: Passed. + vhdl_and104_stdlogic: Passed. + vhdl_and23_bit: Passed. + vhdl_and_gate: Passed. + vhdl_andg_bit: Passed. + vhdl_andg_stdlogic: Passed. + vhdl_array_of_array: Passed. + vhdl_case_multi: Passed. + vhdl_boolean: Passed. + vhdl_concat: Passed. + vhdl_concat_func: Passed. + vhdl_concurrent_assert: Passed. + vhdl_const_package: Passed. + vhdl_const_record: Passed. + vhdl_const_array: Passed. + vhdl_delay_assign: Passed. + vhdl_elab_range: Passed. + vhdl_eval_cond: Passed. + vhdl_expr1: Passed. + vhdl_generic_eval: Passed. + vhdl_fa4_test1: Passed. + vhdl_fa4_test2: Passed. + vhdl_fa4_test3: Passed. + vhdl_fa4_test4: Passed. + vhdl_file_open: Passed. + vhdl_generic_default: Passed. + vhdl_init: Passed. + vhdl_image_attr: Passed. + vhdl_inout: Passed. + vhdl_labeled_assign: Passed. + vhdl_lfcr: Passed. + vhdl_logic: Passed. + vhdl_loop: Passed. + vhdl_multidim_array: ==> Failed - running iverilog. + vhdl_nand104_stdlogic: Passed. + vhdl_nand23_bit: Passed. + vhdl_nandg_bit: Passed. + vhdl_nandg_stdlogic: Passed. + vhdl_nor104_stdlogic: Passed. + vhdl_nor23_bit: Passed. + vhdl_norg_bit: Passed. + vhdl_norg_stdlogic: Passed. + vhdl_not104_stdlogic: Passed. + vhdl_not23_bit: Passed. + vhdl_notfunc_stdlogic: Passed. + vhdl_notg_bit: Passed. + vhdl_notg_stdlogic: Passed. + vhdl_now: Passed. + vhdl_or104_stdlogic: Passed. + vhdl_or23_bit: Passed. + vhdl_org_bit: Passed. + vhdl_org_stdlogic: Passed. + vhdl_pow_rem: Passed. + vhdl_prefix_array: Passed. + vhdl_procedure: Passed. + vhdl_process_scope: Passed. + vhdl_rand23_bit: Passed. + vhdl_range: Passed. + vhdl_range_func: Passed. + vhdl_real: Passed. + vhdl_record_elab: Passed. + vhdl_reduce: Passed. + vhdl_report: Passed. + vhdl_resize: Passed. + vhdl_rtoi: Passed. + vhdl_sa1_test1: Passed. + vhdl_sa1_test2: Passed. + vhdl_sa1_test3: Passed. + vhdl_sadd23_bit: Passed. + vhdl_sadd23_stdlogic: Passed. + vhdl_sdiv23_bit: Passed. + vhdl_sdiv23_stdlogic: Passed. + vhdl_selected: Passed. + vhdl_shift: Passed. + vhdl_signals: Passed. + vhdl_smul23_bit: Passed. + vhdl_smul23_stdlogic: Passed. + vhdl_ssub23_bit: Passed. + vhdl_ssub23_stdlogic: Passed. + vhdl_struct_array: Passed. + vhdl_subtypes: Passed. + vhdl_subprogram: Passed. + vhdl_string: Passed. + vhdl_string_lim: Passed. + vhdl_test1: Passed. + vhdl_test2: Passed. + vhdl_test3: Passed. + vhdl_test4: Passed. + vhdl_test5: Passed. + vhdl_test6: Passed. + vhdl_test7: Passed. + vhdl_test8: Passed. + vhdl_test9: Passed. + vhdl_textio_write: Passed. + vhdl_textio_read: Passed. + vhdl_time: Passed. + vhdl_to_integer: Passed. + vhdl_uadd23_bit: Passed. + vhdl_uadd23_stdlogic: Passed. + vhdl_udiv23_bit: Passed. + vhdl_udiv23_stdlogic: Passed. + vhdl_umul23_bit: Passed. + vhdl_umul23_stdlogic: Passed. + vhdl_unary_minus: Passed. + vhdl_unbounded: Passed. + vhdl_unbounded_func: Passed. + vhdl_usub23_bit: Passed. + vhdl_usub23_stdlogic: Passed. + vhdl_var_init: Passed. + vhdl_wait: Passed. + vhdl_while: Passed. + vhdl_xnor104_stdlogic: Passed. + vhdl_xnor23_bit: Passed. + vhdl_xnorg_bit: Passed. + vhdl_xnorg_stdlogic: Passed. + vhdl_xor23_bit: Passed. + vhdl_xorg_bit: Passed. + vhdl_xorg_stdlogic: Passed. + work7: Passed. + work7b: Passed. + basicexpr: Passed. + basicexpr2: Passed. + basicexpr3: Passed. + basicexpr4: Passed. + basiclatch: Passed. + basicreg: Passed. + basicstate: Passed. + basicstate2: Passed. + blocksynth1: Passed. + blocksynth2: Passed. + blocksynth3: Passed. + br993a: Passed. + br993b: Passed. + br994: Passed. + br995: Passed - CE. + br_gh99v: Passed. + br_gh99w: Passed. + br_gh99x: Passed. + br_gh115: Passed. + br_gh306a: Passed - CE. + br_gh306b: Passed - CE. + case3: Passed. + case4: Passed. + case5: Passed. + case5-syn-fail: Passed - CE. + case6: Passed. + case7: Passed. + case_wo_default: Passed. + casesynth1: Passed. + casesynth2: Passed. + casesynth3: Passed. + casesynth4: Passed. + casesynth5: Passed. + casesynth6: Passed. + casesynth7: Passed. + casesynth8: Passed - CE. + casesynth9: Passed. + condit1: Passed. + conditsynth1: Passed. + conditsynth2: Passed. + conditsynth3: Passed. + dffsynth2: Passed. + dffsynth3: Passed. + dffsynth4: Passed. + dffsynth5: Passed. + dffsynth6: Passed. + dffsynth7: Passed. + dffsynth8: Passed - CE. + dffsynth9: Passed. + dffsynth10: Passed. + dffsynth11: Passed. + ff_dual_enable: Passed. + for_loop_synth: Passed. + for_loop_synth2: Passed. + if_part_no_else: Passed. + if_part_no_else2: Passed. + inside_synth: Passed. + inside_synth2: Passed. + inside_synth3: Passed. + land5: Passed. + lcatsynth: Passed. + memsynth4: Passed. + memsynth8: Passed. + multireg: Passed. + not_a_latch1: Passed. + not_a_latch2: Passed. + partselsynth: Passed. + pr519: Passed. + pr685: Passed. + shiftl: Passed. + sqrt32synth: Passed. + ssetclr1: Passed. + ssetclr2: Passed. + ssetclr3: Passed. + synth_if_no_else: Passed. + ufuncsynth1: Passed. +============================================================================ +Test results: + Total=2556, Passed=2550, Failed=3, Not Implemented=0, Expected Fail=3 diff --git a/ivtest/regression_report-v10.txt b/ivtest/regression_report-v10.txt new file mode 100644 index 000000000..e48e54188 --- /dev/null +++ b/ivtest/regression_report-v10.txt @@ -0,0 +1,2482 @@ +Running compiler/VVP tests for Icarus Verilog version: 10. +---------------------------------------------------------------------------- + br975: Passed - CE. + pr1704726a: Passed - CE. + pr1704726c: Passed - CE. + pr1704726d: Passed - CE. + br_gh265: Passed - CE. + pr1698820: Passed. + fdisplay_fail_fd: Passed. + fdisplay_fail_mcd: Passed. + br_gh289a: Not Implemented. + br_gh289b: Passed - expected fail. + br_gh289c: Passed - expected fail. + br1003a: Passed. + br_ml20191221: Passed - CE. + br_gh281: Not Implemented. + br_gh281b: Not Implemented. + function10: Not Implemented. + function11: Not Implemented. + function12: Not Implemented. + gh161a: Not Implemented. + func_init_var2: Not Implemented. + br_ml20180227: Not Implemented. + resetall: Passed. + br1003b: Passed. + br1003c: Passed. + sv_timeunit_prec3b: Not Implemented. + sv_timeunit_prec4b: Not Implemented. + sv_timeunit_prec_fail1: Passed - CE. + sv_timeunit_prec_fail2: Passed - CE. + sv_unit1c: Not Implemented. + sv_unit2b: Not Implemented. + sv_unit3b: Not Implemented. + sv_unit4b: Not Implemented. + macro_redefinition: Not Implemented. + macro_replacement: Not Implemented. + br_ml20180309a: Not Implemented. + br_ml20180309b: Not Implemented. + br_gh337: Not Implemented. + br_gh365: Not Implemented. + string_events: Not Implemented. + br_gh366: Passed - expected fail. + sv_macro3: Passed - expected fail. + br_gh368: Not Implemented. + analog1: Not Implemented. + analog2: Not Implemented. + ivlh_textio: Not Implemented. + test_when_else: Not Implemented. + vhdl_concurrent_assert: Not Implemented. + vhdl_delay_assign: Not Implemented. + vhdl_elab_range: Not Implemented. + vhdl_eval_cond: Not Implemented. + vhdl_file_open: Not Implemented. + vhdl_image_attr: Not Implemented. + vhdl_lfcr: Not Implemented. + vhdl_loop: Not Implemented. + vhdl_multidim_array: Not Implemented. + vhdl_now: Not Implemented. + vhdl_pow_rem: Not Implemented. + vhdl_process_scope: Not Implemented. + vhdl_range: Not Implemented. + vhdl_resize: Not Implemented. + vhdl_shift: Not Implemented. + vhdl_string: Not Implemented. + vhdl_string_lim: Not Implemented. + vhdl_subtypes: Not Implemented. + vhdl_textio_write: Not Implemented. + vhdl_textio_read: Not Implemented. + vhdl_unary_minus: Not Implemented. + vhdl_wait: Not Implemented. + vhdl_while: Not Implemented. + always_comb: Not Implemented. + always_comb_fail: Not Implemented. + always_comb_fail3: Not Implemented. + always_comb_fail4: Not Implemented. + always_comb_no_sens: Not Implemented. + always_comb_rfunc: Not Implemented. + always_comb_trig: Not Implemented. + always_comb_warn: Not Implemented. + always_ff: Not Implemented. + always_ff_fail: Not Implemented. + always_ff_fail2: Not Implemented. + always_ff_fail3: Not Implemented. + always_ff_fail4: Not Implemented. + always_ff_no_sens: Not Implemented. + always_ff_warn: Not Implemented. + always_ff_warn_sens: Not Implemented. + always_latch: Not Implemented. + always_latch_fail: Not Implemented. + always_latch_fail3: Not Implemented. + always_latch_fail4: Not Implemented. + always_latch_no_sens: Not Implemented. + always_latch_trig: Not Implemented. + always_latch_warn: Not Implemented. + br1004: Not Implemented. + br_gh226: Passed - CE. + br_gh177a: Not Implemented. + br_gh177b: Not Implemented. + br_gh277b: Not Implemented. + case_priority: Not Implemented. + case_unique: Not Implemented. + genvar_inc_dec: Not Implemented. + gh161b: Not Implemented. + l_equiv: Not Implemented. + l_equiv_ca: Not Implemented. + l_equiv_const: Not Implemented. + sf_countbits: Not Implemented. + sf_countbits_fail: Not Implemented. + sf_countones: Not Implemented. + sf_countones_fail: Not Implemented. + sf_isunknown: Not Implemented. + sf_isunknown_fail: Not Implemented. + sf_onehot: Not Implemented. + sf_onehot_fail: Not Implemented. + sf_onehot0: Not Implemented. + sf_onehot0_fail: Not Implemented. + sformatf: Not Implemented. + sv_darray_decl_assign: Not Implemented. + sv_deferred_assert1: Not Implemented. + sv_deferred_assert2: Not Implemented. + sv_deferred_assume1: Not Implemented. + sv_deferred_assume2: Not Implemented. + sv_immediate_assert: Not Implemented. + sv_immediate_assume: Not Implemented. + sv_new_array_error: Not Implemented. + sv_param_port_list: Not Implemented. + sv_queue_real: Not Implemented. + sv_queue_real_bounded: Not Implemented. + sv_queue_real_fail: Not Implemented. + sv_queue_string: Not Implemented. + sv_queue_string_bounded: Not Implemented. + sv_queue_string_fail: Not Implemented. + sv_queue_vec: Not Implemented. + sv_queue_vec_bounded: Not Implemented. + sv_queue_vec_fail: Not Implemented. + sv_wildcard_import1: Not Implemented. + sv_wildcard_import2: Not Implemented. + sv_wildcard_import3: Not Implemented. + sv_wildcard_import4: Not Implemented. + sv_wildcard_import5: Not Implemented. + sv_wildcard_import6: Not Implemented. + sv_wildcard_import7: Not Implemented. + vvp_recv_vec4_pv: Passed - CE. + wild_cmp_const: Not Implemented. + wild_cmp_err: Not Implemented. + wild_cmp_err2: Not Implemented. + wild_cmp_net: Not Implemented. + wild_cmp_var: Not Implemented. + sv_cast_darray: Not Implemented. + sv_cast_darray-v10: Passed. + rtran: Not Implemented. + rtranif0: Not Implemented. + rtranif1: Not Implemented. + br1000: Passed. + br_ml20190814: Passed - expected fail. + br993a: Passed - CE. + br993b: Passed - CE. + br_gh115: Passed - CE. + basiclatch: Passed. + blocksynth2: Passed. + blocksynth3: Passed. + case1: Passed. + case2: Passed. + case4: Passed. + case5: Passed. + case5-syn-fail: Passed. + case6: Passed. + casesynth1: Passed. + casesynth2: Passed. + casesynth3: Passed. + casesynth7: Not Implemented. + casex_synth: Passed. + condit1: Passed. + conditsynth1: Passed. + conditsynth2: Passed. + conditsynth3: Passed. + dffsynth: Passed. + dffsynth3: Passed. + dffsynth4: Passed. + dffsynth9: Passed. + dffsynth10: Passed. + dffsynth11: Passed. + inside_synth: Passed. + inside_synth3: Passed. + memsynth1: Passed. + memsynth2: Passed. + memsynth3: Passed. + memsynth5: Passed. + memsynth6: Passed. + memsynth7: Passed. + memsynth9: Passed. + mix_reset: Passed. + multireg: Passed. + sqrt32synth: Passed. + ssetclr3: Passed. + pr903: Passed. + pr1388974: Passed. + br_gh13a: Passed. + param-width: Passed. + ca_time: Passed. + delayed_sfunc: Passed. + localparam_type: Passed. + parameter_type: Passed. + pr1701890: Passed. + pr1864110a: Passed. + pr1864110b: Passed. + pr1864115: Passed. + fileline: Passed. + fileline2: ==> Failed - output does not match gold file. + macro_str_esc: Passed. + macro_with_args: Passed. + mcl1: Passed. + pr622: Passed. + pr639: Passed. + pr1741212: Passed. + pr1912112: Passed. + pr1925360: Passed. + repeat1: Passed. + pr2002443: Passed - CO. + abstime: Passed. + pr2590274a: Passed. + pr2590274b: Passed. + pr2590274c: Passed. + bitsel: Passed. + bitsel10: Passed. + bitsel2: Passed. + bitsel3: Passed. + bitsel4: Passed. + bitsel5: Passed. + bitsel6: Passed. + bitsel7: Passed. + bitsel8: Passed. + bitsel9: Passed. + bitwidth3: Passed. + clog2: Passed. + clog2-signal: Passed. + param_vec: Passed. + param_vec2: Passed. + pr498: Passed. + pr721: Passed. + pr809: Passed. + pr809b: Passed. + pr979: Passed. + pr1000: Passed. + pr1609611: Passed. + pr1750870: Passed. + pr1765789: Passed. + pr1771903: Passed. + pr1793749: Passed. + pr1793749b: Passed. + pr1861212b: Passed. + pr1864110c: Passed. + pr2806449: Passed. + pr2877555: Passed. + real4: Passed. + realtobits: Passed. + specparam1: Passed. + specparam2: Passed. + tern3: Passed. + v2005_math: Passed. + fatal_et_al: Passed. + fatal_et_al2: Passed. + pr1494799: Passed. + pr2428890c: Passed. + br978: Passed. + br_ml20150424: Passed. + constfunc6: Passed. + pr2728032: Passed. + test_va_math: Passed. + va_math: Passed. + pr2509349a: Passed. + pr2509349b: Passed. + simparam: Passed. + blocking_repeat_ec: Passed. + nb_array_pv: Passed. + nb_ec_array: Passed. + nb_ec_array_pv: Passed. + nb_ec_pv: Passed. + nb_ec_pv2: Passed. + nb_ec_real: Passed. + nb_ec_vector: Passed. + pr2486350: Passed. + pr534: Passed. + stime: Passed. + swrite: Passed. + time6: Passed. + time6b: Passed. + time6c: Passed. + concat1: Passed. + concat2: Passed. + constconcat1: Passed. + constconcat2: Passed. + rptconcat2: Passed. + sdw_lvalconcat2: Passed. + bool1: Passed. + compare_bool_reg: Passed. + constfunc8: Passed. + binary_nand: Passed. + binary_nor: Passed. + array_lval_select4a: Passed. + array_lval_select5: Passed. + ca_64delay: Passed. + ca_var_delay: Passed. + cast_real_signed: Passed. + cast_real_unsigned: Passed. + pr1861212c: Passed. + pr1873372: Passed. + pr1880003: Passed. + pr1898293: Passed. + pr2123158: Passed. + pr2453002b: Passed. + pr2456943: Passed. + pr2715748: Passed. + pr2806474: Passed. + pr2976242: Passed. + pr2976242b: Passed. + pr2976242c: Passed - CE. + real8: Passed. + real_array: Passed. + real_array_nb: Passed. + real_concat_invalid1: Passed - CE. + real_mod_in_ca: Passed. + real_op_fail: Passed - CE. + real_pulse_clean: Passed. + real_pwr_in_ca: Passed. + real_select_invalid: Passed - CE. + real_wire_array: Passed. + real_wire_force_rel: Passed. + tern8: Passed. + pr2476430: Passed. + cmdline_parm1: Passed. + array_dump: Passed. + pr2859628: Passed. + race: Passed. + automatic_error4: Passed - CE. + pr1909940: Passed. + pr1909940b: Passed. + unnamed_generate_block: Passed. + addsr: Passed. + addwide: Passed. + always3.1.1A: Passed - CE. + always3.1.1B: Passed - CE. + always3.1.1C: Passed. + always3.1.1D: Passed. + always3.1.1E: Passed. + always3.1.1F: Passed. + always3.1.1G: Passed. + always3.1.1H: Passed. + always3.1.1I: Passed. + always3.1.1J: Passed. + always3.1.1K: Passed. + always3.1.2A: Passed - CE. + always3.1.2B: Passed - CE. + always3.1.2C: Passed - CE. + always3.1.2D: Passed - CE. + always3.1.2E: Passed - CE. + always3.1.2F: Passed - CE. + always3.1.2G: Passed - CE. + always3.1.2H: Passed - CE. + always3.1.2I: Passed - CE. + always3.1.3A: Passed - CE. + always3.1.3B: Passed - CE. + always3.1.3B2: Passed. + always3.1.3C: Passed - CE. + always3.1.3D: Passed - CE. + always3.1.3D2: Passed. + always3.1.3E: Passed - CE. + always3.1.3E2: Passed. + always3.1.3F: Passed - CE. + always3.1.3F2: Passed. + always3.1.3G: Passed - CE. + always3.1.3H: Passed - CE. + always3.1.3J: Passed - CE. + always3.1.4A: Passed. + always3.1.4B: Passed. + always3.1.4C: Passed. + always3.1.4D: Passed. + always3.1.4E: Passed. + always3.1.4F: Passed. + always3.1.4G: Passed. + always3.1.4H: Passed. + always3.1.4I: Passed. + always3.1.5A: Passed. + always3.1.5B: Passed. + always3.1.5C: Passed. + always3.1.5D: Passed. + always3.1.5E: Passed. + always3.1.5F: Passed. + always3.1.6A: Passed. + always3.1.6B: Passed. + always3.1.6C: Passed. + always3.1.6D: Passed. + always3.1.7A: Passed. + always3.1.7B: Passed. + always3.1.7C: Passed. + always3.1.7D: Passed. + always3.1.8A: Passed. + always3.1.9A: Passed - CE. + always3.1.9B: Passed - CE. + always3.1.9C: Passed. + always3.1.9D: Passed. + always3.1.10A: Passed - CE. + always3.1.11A: Passed. + always3.1.11B: Passed. + always3.1.12A: Passed. + always3.1.12B: Passed. + always3.1.12C: Passed. + always_star_array_lval: Passed. + andnot1: Passed. + arith-unknown: Passed. + array4: Passed. + array5: Passed - CE. + array6: Passed. + array7: Passed. + array_lval_select1: Passed. + array_lval_select2: Passed. + array_lval_select3a: Passed - CE. + array_lval_select3a-: Passed. + array_lval_select3b: Passed - CE. + array_lval_select4b: Passed - CE. + array_lval_select6: Passed. + array_packed_2d: Passed. + array_select: Passed. + array_select_a: Passed. + array_word_check: Passed. + array_word_width: Passed. + array_word_width2: Passed. + assign3.2A: Passed. + assign3.2B: Passed. + assign3.2C: Passed. + assign3.2D: Passed. + assign3.2E: Passed. + assign_add: Passed. + assign_deassign_pv: Passed. + assign_delay: Passed. + assign_deq: Passed. + assign_ge: Passed. + assign_le: Passed. + assign_mem1: Passed. + assign_mem2: Passed. + assign_nb1: Passed. + assign_nb2: Passed. + assign_neq: Passed. + attrib: Passed. + attrib01_module: Passed. + attrib02_port_decl: Passed. + attrib03_parameter: Passed. + attrib04_net_var: Passed. + attrib05_port_conn: Passed. + attrib06_operator_suffix: Passed. + attrib07_func_call: Passed. + attrib08_mod_inst: Passed. + attrib09_case: Passed. + automatic_error1: Passed - CE. + automatic_error2: Passed - CE. + automatic_error3: Passed - CE. + automatic_error5: Passed - CE. + automatic_error6: Passed - CE. + automatic_error7: Passed - CE. + automatic_error8: Passed - CE. + automatic_error9: Passed - CE. + automatic_error10: Passed - CE. + automatic_error11: Passed. + automatic_error12: Passed. + automatic_error13: Passed. + automatic_events: Passed. + automatic_events2: Passed. + automatic_events3: Passed. + automatic_task: Passed. + automatic_task2: Passed. + automatic_task3: Passed. + big_int: Passed. + bitwidth: Passed. + bitwidth2: Passed. + blankport: Passed. + block_only_with_var_def: Passed. + bnot: Passed. + br605a: ==> Failed - output does not match gold file. + br605b: ==> Failed - output does not match gold file. + br916a: Passed. + br916b: Passed. + br918a: Passed. + br918b: Passed. + br918c: Passed. + br918d: Passed. + br919: Passed. + br924: Passed - CE. + br930: Passed - CO. + br931: Passed. + br935: Passed. + br937: Passed. + br946: Passed. + br947: Passed. + br948: Passed. + br955: Passed. + br960a: Passed. + br960b: Passed. + br960c: Passed. + br960d: Passed. + br961: Passed. + br961a: Passed - CE. + br965: Passed. + br967: Passed. + br968: Passed. + br971: ==> Failed - output does not match gold file. + br972: Passed. + br977: Passed. + br982: Passed - CE. + br982a: Passed - CE. + br982b: Passed - CE. + br988: Passed. + br990: Passed. + br991a: Passed. + br999: Passed. + br1001: Passed. + br1006: Passed. + br1007: Passed. + br1008: Passed. + br1015a: Passed - CE. + br1019: Passed. + br1027: Passed. + br1027a: Passed - CE. + br1027c: Passed - CE. + br1027e: Passed - CE. + br1029a: Passed. + br1029b: Passed. + br1029c: Passed - CE. + br_gh6: Passed. + br_gh7: Passed. + br_gh8: Passed. + br_gh9: Passed. + br_gh11: Passed - CO. + br_gh12: Passed. + br_gh13: Passed. + br_gh14: Passed. + br_gh15: Passed. + br_gh18: Passed. + br_gh19: Passed. + br_gh19a: Passed. + br_gh19b: Passed. + br_gh22: Passed. + br_gh25a: Passed - CE. + br_gh25b: Passed - CE. + br_gh26: Passed - CE. + br_gh28: Passed. + br_gh30: Passed. + br_gh33: Passed. + br_gh37: Passed. + br_gh60a: Passed - CE. + br_gh62: Passed - CE. + br_gh79: Passed - CE. + br_gh99a: Passed. + br_gh99b: Passed. + br_gh99d: Passed. + br_gh99f: Passed. + br_gh99g: Passed. + br_gh99h: Passed. + br_gh99i: Passed. + br_gh99j: Passed. + br_gh99k: Passed. + br_gh99l: Passed. + br_gh99m: Passed. + br_gh99o: Passed. + br_gh99p: Passed. + br_gh99q: Passed. + br_gh99r: Passed. + br_gh99s: Passed. + br_gh99t: Passed. + br_gh99u: Passed. + br_gh103: Passed. + br_gh127a: Passed. + br_gh127b: Passed. + br_gh127c: Passed. + br_gh127d: Passed. + br_gh127e: Passed. + br_gh127f: Passed. + br_gh142: Passed - CE. + br_gh152: Passed - CE. + br_gh157: Passed. + br_gh162: Passed. + br_gh163: Passed - CE. + br_gh198: Passed. + br_gh199a: Passed. + br_gh199b: Passed. + br_gh209: Passed. + br_gh230: Passed. + br_gh244a: Passed. + br_gh244b: Passed. + br_gh277a: Passed. + br_gh283a: Passed. + br_gh283b: Passed. + br_gh283c: Passed. + br_gh309: Passed. + br_gh315: Passed. + br_gh316a: Passed. + br_gh316b: Passed. + br_gh316c: Passed. + br_gh330: Passed. + br_gh345: Passed. + br_gh356a: Passed. + br_gh356b: Passed. + br_ml20150315: Passed. + br_ml20150321: Passed - CE. + br_ml20150606: Passed. + br_mw20171108: Passed. + br_ml20190806a: Passed. + br_ml20190806b: Passed. + bufif: Passed. + busbug: Passed. + ca_force: Passed. + ca_func: Passed. + ca_mult: Passed. + ca_pow_signed: Passed. + ca_pow_synth: Passed. + ca_pow_unsigned: Passed. + ca_real_logical: Passed. + case3.8A: Passed. + case3.8B: Passed. + case3.8C: Passed. + case3.8D: Passed. + casex3.9A: Passed. + casex3.9B: Passed. + casex3.9C: Passed. + casex3.9D: Passed. + casex3.9E: Passed. + casez3.10A: Passed. + casez3.10B: Passed. + casez3.10C: Passed. + casez3.10D: Passed. + casez3.10E: Passed. + check_constant_1: Passed - CE. + check_constant_2: Passed - CE. + check_constant_3: Passed - CE. + check_constant_4: Passed - CE. + check_constant_5: Passed - CE. + check_constant_6: Passed - CE. + check_constant_7: Passed - CE. + check_constant_8: Passed - CE. + check_constant_9: Passed - CE. + check_constant_10: Passed - CE. + check_constant_11: Passed - CE. + check_constant_12: Passed - CE. + check_constant_13: Passed - CE. + check_constant_14: Passed - CE. + check_constant_15: Passed - CE. + check_constant_16: Passed - CE. + check_constant_17: Passed - CE. + check_constant_18: Passed - CE. + check_constant_19: Passed - CE. + check_constant_20: Passed - CE. + cmos: Passed. + comment1: Passed. + comp1000: Passed. + comp1001: Passed. + comp1001_fail3: Passed. + comp1001_fail4: Passed. + comp1001_fail5: Passed. + complex_lidx: Passed. + con_tri: Passed. + concat3: Passed. + concat4: Passed. + concat_zero_wid_fail: Passed - CE. + concat_zero_wid_fail2: Passed. + cond_band: Passed. + cond_wide: Passed. + cond_wide2: Passed. + const: Passed. + const2: Passed. + const3: Passed. + const4: Passed. + constadd: Passed. + constadd2: Passed. + constadd3: Passed. + constfunc1: Passed. + constfunc2: Passed. + constfunc3: Passed. + constfunc5: Passed. + constfunc7: Passed. + constfunc9: Passed. + constfunc10: Passed. + constfunc11: Passed. + constfunc12: Passed. + constfunc13: Passed. + constfunc14: Passed. + constfunc15: Passed. + constmult: Passed. + consttern: Passed. + contrib8.1: Passed. + contrib8.2: Passed. + contrib8.3: Passed - CE. + contrib8.4: Passed. + contrib8.5: Passed. + countdrivers1: Passed. + countdrivers2: Passed. + countdrivers3: Passed. + countdrivers4: Passed. + countdrivers5: Passed. + cprop: Passed. + credence20041209: Passed. + dangling_port: Passed. + dcomp1: Passed. + deassign3.4A: Passed. + decl_assign1: Passed. + def_nettype: Passed. + def_nettype_none: Passed - CE. + define1: Passed. + defparam: Passed. + defparam2: Passed. + defparam3: Passed. + defparam3.5: Passed. + defparam4: Passed. + delay: Passed. + delay2: Passed. + delay3: Passed. + delay4: Passed. + delay5: Passed. + delay_assign_nb: Passed. + delay_assign_nb2: Passed. + delay_var: Passed. + delayed_comp_reduct: Passed. + deposit: Passed. + deposit_wire: Passed. + dff1: Passed. + disable3.6A: Passed. + disable3.6B: Passed. + disable_cleanup: Passed. + disable_fork: Passed. + disblock: Passed. + disblock2: Passed. + disp_dec: Passed. + disp_dec2: Passed. + disp_leading_z: Passed. + disp_parm: Passed. + disp_part: Passed. + div16: Passed. + dotinid: Passed. + drive_strength: Passed. + drive_strength1: Passed. + drive_strength2: Passed. + drive_strength3: Passed. + dummy7: Passed. + dump_memword: Passed. + dumpvars: Passed. + eeq: Passed. + else1: Passed. + else2: Passed. + else3: Passed. + elsif_test: Passed. + eofmt_percent: Passed. + eq: Passed. + escape1: Passed. + escape2a: Passed - CO. + escape2b: Passed - CO. + escape2c: Passed - CO. + escape3: Passed. + escape4: Passed. + escape4b: Passed. + event2: Passed. + event3: Passed. + event3.15: Passed. + event_array: Passed - CE. + event_list: Passed. + event_list2: Passed. + event_list3: Passed. + extend: Passed. + fdisplay1: Passed. + fdisplay2: Passed. + fdisplay3: Passed. + fifo: Passed. + fileio: Passed. + fopen1: Passed. + fopen2: Passed. + for3.16A: Passed. + force1: Passed. + force2: Passed. + force3.17A: Passed. + force3.17B: Passed. + force3.17C: Passed. + force_lval_part: Passed. + force_release_reg_pv: Passed. + force_release_wire8_pv: Passed. + force_release_wire_pv: Passed. + fork1: Passed. + fork3.19A: Passed. + fork3.19B: Passed. + format: Passed. + fr47: Passed. + fread: Passed. + fread-error: Passed. + fscanf_u: Passed. + fscanf_u_warn: Passed. + fscanf_z: Passed. + fscanf_z_warn: Passed. + function1: Passed. + function2: Passed. + function3: Passed. + function3.11B: Passed. + function3.11C: Passed. + function3.11D: Passed. + function3.11F: Passed. + function4: Passed - CE. + function5: Passed - CO. + function6: Passed. + function7: Passed. + function8: Passed. + function9: Passed. + function_exp: Passed. + ga_and: Passed. + ga_mod: Passed. + ga_mod1: Passed. + ga_mod2: Passed. + ga_nand: Passed. + ga_nor: Passed. + ga_or: Passed. + ga_xnor: Passed. + ga_xor: Passed. + galan: Passed. + gate_connect1: Passed. + gate_connect2: Passed - CE. + gen_case_opt1: Passed. + gen_case_opt2: Passed. + gen_case_opt3: Passed. + gencrc: Passed. + generate_case: Passed. + generate_case2: Passed. + generate_case3: Passed. + generate_multi_loop: Passed. + genloop: Passed. + genvar_scopes: Passed. + hello1: Passed. + hier_ref_error: Passed - CE. + hierspace: Passed. + idiv1: Passed. + idiv2: Passed. + idiv3: Passed. + ifdef1: Passed. + ifdef2: Passed. + ifdef3: Passed. + ifdef4: Passed. + include1: Passed. + include2: Passed. + include3: Passed. + indef_width_concat: Passed - CE. + initmod: Passed. + initmod2: Passed. + inout: Passed. + inout2: Passed. + inout3: Passed. + inout4: Passed. + int_not_signext: Passed. + integer1lt: Passed. + integer2le: Passed. + integer3gt: Passed. + integer4ge: Passed. + integer5: Passed. + itor_rtoi: Passed. + land2: Passed. + land3: Passed. + land4: Passed. + landor1: Passed. + ldelay1: Passed. + ldelay2: Passed. + ldelay3: Passed. + ldelay4: Passed. + ldelay5: Passed. + lh_catadd: Passed. + lh_memcat: Passed. + lh_memcat2: Passed. + lh_memcat3: Passed. + lh_varindx: Passed. + lh_varindx2: Passed. + lh_varindx4: Passed. + lh_varindx5: Passed. + long_div: Passed. + macro2: Passed. + macsub: Passed. + mangle: Passed. + mangle_1: Passed. + many_drivers: Passed. + mcl2: Passed. + mem1: Passed. + mem2port: Passed. + memassign: Passed. + memidx: Passed. + memidxrng: Passed. + meminit: Passed. + meminit2: Passed. + memport_bs: Passed. + memref: Passed. + mhead_task: Passed. + mixed_type_div_mod: Passed. + mixed_width_case: Passed. + modparam: Passed. + module3.12A: Passed. + module3.12B: Passed. + modulus: Passed. + modulus2: Passed. + monitor: Passed. + monitor2: Passed. + monitor3: Passed. + mult1: Passed. + mult16: Passed. + mult2: Passed. + multi_bit_strength: Passed. + multi_driver_delay: Passed. + multiply_large: Passed. + muxtest: Passed. + named_event_no_edges: Passed - CE. + nb_assign: Passed. + nb_delay: Passed. + nblkorder: Passed. + negative_genvar: Passed. + negvalue: Passed. + neq1: Passed. + nested_func: Passed. + nested_impl_event1: Passed. + nested_impl_event2: Passed. + no_if_statement: Passed - CE. + no_timescale_in_module: Passed - CE. + non-polymorphic-abs: Passed. + npmos: Passed. + npmos2: Passed. + onehot: Passed. + p_monta: Passed. + par_mismatch: Passed - CE. + param-extend: Passed. + param_add: Passed. + param_and: Passed. + param_and2: Passed. + param_band: Passed. + param_binv: Passed. + param_bor: Passed. + param_concat: Passed. + param_eq3: Passed. + param_expr: Passed. + param_mod: Passed. + param_select: Passed. + param_select2: Passed. + param_select3: Passed. + param_string: Passed. + param_tern: Passed. + param_tern2: Passed. + param_test1: Passed. + param_test2: Passed. + param_test3: Passed - CO. + param_test4: Passed. + param_times: Passed. + patch1268: Passed. + pca1: Passed. + pic: Passed. + port-test2: Passed. + port-test3: Passed - CE. + port-test4a: Passed - CE. + port-test4b: Passed - CE. + port-test5: Passed. + port-test6: Passed. + port-test7: Passed. + posedge: Passed. + pow-ca: Passed. + pow-const: Passed. + pow-proc: Passed. + pow_ca_signed: Passed. + pow_ca_unsigned: Passed. + pow_reg_signed: Passed. + pow_reg_unsigned: Passed. + pow_signed: Passed. + pow_unsigned: Passed. + pr136: Passed. + pr142: Passed. + pr183: Passed - CO. + pr224: Passed. + pr224a: Passed. + pr243: Passed. + pr245: Passed. + pr245_std: Passed. + pr273: Passed. + pr298: Passed. + pr304: Passed. + pr307: Passed. + pr307a: Passed. + pr312: Passed. + pr338: Passed - CO. + pr355: Passed. + pr377: Passed. + pr434: Passed. + pr445: Passed. + pr478: Passed. + pr487: Passed. + pr492: Passed. + pr508: Passed. + pr509: Passed. + pr509b: Passed. + pr511: Passed. + pr513: Passed. + pr522: Passed. + pr524: Passed. + pr527: Passed. + pr528: Passed. + pr528b: Passed. + pr529: Passed. + pr530a: Passed. + pr530b: Passed. + pr530c: Passed. + pr531a: Passed. + pr531b: Passed. + pr532: Passed. + pr532b: Passed. + pr533: Passed. + pr538: Passed. + pr540: Passed. + pr540b: Passed. + pr540c: Passed. + pr541: Passed. + pr542: Passed. + pr544: Passed. + pr547: Passed. + pr556: Passed. + pr564: Passed. + pr569: Passed. + pr572: Passed. + pr572b: Passed. + pr578: Passed. + pr584: Passed. + pr585: Passed. + pr587: Passed. + pr590: Passed. + pr594: Passed. + pr596: Passed. + pr602: Passed. + pr617: Passed. + pr632: Passed. + pr673: Passed. + pr675: Passed. + pr678: Passed. + pr690: Passed. + pr693: Passed. + pr699: Passed. + pr699b: Passed. + pr704: Passed. + pr707: Passed. + pr708: Passed. + pr710: Passed. + pr718: Passed. + pr722: Passed. + pr729: Passed. + pr734: Passed. + pr735: Passed. + pr748: Passed. + pr751: Passed. + pr757: Passed. + pr772: Passed. + pr810: Passed. + pr812: Passed. + pr820: Passed. + pr823: Passed. + pr841: Passed. + pr842: Passed. + pr848: Passed. + pr856: Passed. + pr859: Passed. + pr860: Passed. + pr872: Passed. + pr902: Passed. + pr905: Passed. + pr910: Passed. + pr913: Passed. + pr923: Passed. + pr938: Passed. + pr938b: Passed. + pr938b_std: Passed. + pr941: Passed. + pr973: Passed. + pr978: Passed. + pr985: Passed. + pr987: Passed. + pr990: Passed. + pr991: Passed. + pr993: Passed. + pr995: Passed. + pr1002: Passed. + pr1002a: Passed. + pr1007: Passed. + pr1008: Passed. + pr1022: Passed. + pr1024: Passed. + pr1026: Passed. + pr1029: Passed. + pr1032: Passed. + pr1033: Passed. + pr1065: Passed. + pr1072: Passed. + pr1077: Passed. + pr1087: Passed. + pr1101: Passed. + pr1115: Passed. + pr1353345: Passed. + pr1353345b: Passed. + pr1367855: Passed. + pr1380261: Passed. + pr1403406: Passed. + pr1403406a: Passed. + pr1403406b: Passed. + pr1421777: Passed. + pr1444055: Passed. + pr1449749a: Passed. + pr1455873: Passed. + pr1465769: Passed. + pr1467825: Passed - CO. + pr1474283: Passed. + pr1474316: Passed. + pr1474318: Passed. + pr1476440: Passed. + pr1477190: Passed. + pr1478121: Passed. + pr1478988: Passed. + pr1489568: Passed. + pr1489570: Passed. + pr1491355: Passed. + pr1492075: Passed. + pr1508882: Passed. + pr1510724: Passed. + pr1515168: Passed. + pr1520314: Passed - CO. + pr1522570: Passed. + pr1528093: Passed. + pr1530426: Passed. + pr1561597: Passed. + pr1565544: Passed. + pr1565699b: Passed. + pr1570451: Passed. + pr1570451b: Passed. + pr1570635: Passed. + pr1570635b: Passed. + pr1574175: Passed. + pr1581580: Passed. + pr1587634: Passed - CO. + pr1587669: Passed. + pr1589497: Passed. + pr1598445: Passed. + pr1601896: Passed. + pr1601898: Passed. + pr1603313: Passed. + pr1603918: Passed. + pr1612693: Passed. + pr1623097: Passed. + pr1625912: Passed. + pr1628288: Passed. + pr1628300: Passed. + pr1629683: Passed. + pr1632861: Passed. + pr1634526: Passed. + pr1636409: Passed. + pr1637208: Passed. + pr1638985: Passed. + pr1639060: Passed. + pr1639064: Passed. + pr1639064b: Passed. + pr1639968: Passed. + pr1639971: Passed. + pr1645277: Passed. + pr1645518: Passed. + pr1648365: Passed. + pr1650842: Passed. + pr1657307: Passed. + pr1661640: Passed. + pr1662508: Passed. + pr1664684: Passed. + pr1675789: Passed. + pr1675789b: Passed. + pr1676071: Passed. + pr1676836: Passed. + pr1682887: Passed. + pr1687193: Passed. + pr1688717: Passed. + pr1690058: Passed. + pr1691599b: Passed. + pr1691709: Passed. + pr1693890: Passed. + pr1693921: Passed. + pr1694413: Passed. + pr1694427: Passed. + pr1695257: Passed - CO. + pr1695309: Passed. + pr1695322: Passed. + pr1695334: Passed. + pr1696137: Passed. + pr1697250: Passed. + pr1697732: Passed. + pr1698499: Passed. + pr1698658: Passed. + pr1698659: Passed. + pr1699444: Passed. + pr1699519: Passed. + pr1701855: Passed. + pr1701855b: Passed. + pr1701889: Passed. + pr1701921: Passed. + pr1702593: Passed. + pr1703120: Passed. + pr1703346: Passed. + pr1703959: Passed. + pr1704013: Passed - CE. + pr1704726b: Passed. + pr1705027: Passed - CO. + pr1716276: Passed. + pr1717361: Passed. + pr1719055: Passed. + pr1723367: Passed. + pr1735724: Passed - CE. + pr1735822: Passed. + pr1735836: Passed. + pr1740476b: Passed. + pr1742910: Passed. + pr1745005: Passed. + pr1746401: Passed. + pr1746848: Passed. + pr1752353: Passed. + pr1752823a: Passed. + pr1752823b: Passed. + pr1755593: Passed. + pr1755629: Passed. + pr1758122: Passed. + pr1758135: Passed. + pr1763333: Passed - CE. + pr1770199: Passed. + pr1776485: Passed. + pr1777103: Passed. + pr1780480: Passed. + pr1784984: Passed. + pr1787394a: Passed. + pr1787394b: Passed. + pr1787423: Passed. + pr1787423b: Passed. + pr1787423c: Passed. + pr1792108: Passed. + pr1792152: Passed. + pr1792734: Passed. + pr1793157: Passed. + pr1794362: Passed. + pr1795005a: Passed. + pr1795005b: Passed. + pr1799904: Passed. + pr1804877: Passed. + pr1805837: Passed. + pr1812297: Passed. + pr1819452: Passed. + pr1820472: Passed. + pr1822658: Passed. + pr1823732: Passed. + pr1828642: Passed. + pr1830834: Passed. + pr1831724: Passed. + pr1832097a: Passed. + pr1832097b: Passed. + pr1833024: Passed - CE. + pr1833754: Passed - CE. + pr1841300: Passed. + pr1845683: Passed. + pr1851310: Passed. + pr1855504: Passed. + pr1861212a: Passed. + pr1862744a: Passed. + pr1862744b: Passed - CE. + pr1866215: Passed. + pr1866215b: Passed. + pr1867161a: Passed. + pr1867161b: Passed. + pr1867332: Passed - CO. + pr1868792: Passed. + pr1868991a: Passed. + pr1868991b: Passed - CO. + pr1869769: Passed. + pr1869772: Passed. + pr1869781: Passed. + pr1873146: Passed. + pr1875866: Passed. + pr1875866b: Passed. + pr1876798: Passed. + pr1877740: Passed. + pr1877743: Passed. + pr1878909: Passed. + pr1879226: Passed. + pr1883052: Passed. + pr1883052b: Passed. + pr1885847: Passed. + pr1887168: Passed. + pr1892959: Passed. + pr1892959b: Passed. + pr1898983: Passed. + pr1901125: Passed. + pr1903157: Passed - CO. + pr1903324: Passed. + pr1903343: Passed. + pr1903520: Passed. + pr1907192: Passed. + pr1912843: Passed. + pr1913918a: Passed. + pr1913918b: Passed. + pr1913918c: Passed. + pr1913937: Passed. + pr1916261: Passed. + pr1921332: Passed - CO. + pr1924845: Passed. + pr1925356: Passed. + pr1925363a: Passed - CE. + pr1925363b: Passed - CE. + pr1932444: Passed. + pr1934744: Passed. + pr1936363: Passed. + pr1938138: Passed - CE. + pr1939165: Passed. + pr1946411: Passed. + pr1948110: Passed. + pr1948342: Passed. + pr1949025: Passed. + pr1950282: Passed. + pr1956211: Passed. + pr1958801: Passed. + pr1960545: Passed. + pr1960548: Passed. + pr1960558: Passed. + pr1960575: Passed. + pr1960596: Passed. + pr1960619: Passed. + pr1960625: Passed. + pr1960633: Passed. + pr1963240: Passed. + pr1963960: Passed. + pr1963962: Passed. + pr1971662a: Passed - CE. + pr1971662b: Passed - CE. + pr1978358: Passed. + pr1978358b: Passed. + pr1978358c: Passed. + pr1978358d: Passed. + pr1983762: Passed. + pr1985582: Passed. + pr1988302: Passed. + pr1988302b: Passed - CE. + pr1988310: Passed. + pr1990029: Passed. + pr1990164: Passed. + pr1990269: Passed. + pr1992244: Passed. + pr1992729: Passed. + pr1993479: Passed. + pr2001162: Passed. + pr2011429: Passed. + pr2013758: Passed. + pr2014673: Passed. + pr2015466: Passed. + pr2018235a: Passed. + pr2018235b: Passed. + pr2018305: Passed. + pr2019553: Passed. + pr2029336: Passed. + pr2030767: Passed. + pr2036953: Passed. + pr2038048: Passed. + pr2039632: Passed - CE. + pr2039694: Passed. + pr2043324: Passed. + pr2043585: Passed. + pr2051694: Passed - CE. + pr2051975: Passed - CE. + pr2053944: Passed. + pr2076363: Passed. + pr2076391: Passed. + pr2076425: Passed. + pr2085984: Passed. + pr2091455: Passed. + pr2109179: Passed. + pr2117473: Passed. + pr2117488: Passed. + pr2119622: Passed. + pr2121536: Passed. + pr2121536b: Passed. + pr2123190: Passed. + pr2132552: Passed. + pr2136787: Passed. + pr2138682: Passed. + pr2138979: Passed. + pr2138979b: Passed. + pr2138979c: Passed. + pr2138979d: Passed. + pr2139593: Passed. + pr2146620: Passed. + pr2146620b: Passed. + pr2146620c: Passed. + pr2146824: Passed. + pr2148401: Passed. + pr2152011: Passed. + pr2159630: Passed. + pr2166188: Passed. + pr2166311: Passed. + pr2169870: Passed. + pr2172606: Passed. + pr2172606b: Passed. + pr2181249: Passed. + pr2190323: Passed. + pr2201909: Passed. + pr2201909b: Passed. + pr2202706: Passed. + pr2202706b: Passed. + pr2202706c: Passed. + pr2202846a: Passed. + pr2202846b: Passed. + pr2202846c: Passed. + pr2208681: Passed. + pr2215342: Passed. + pr2219441: Passed. + pr2219441b: Passed. + pr2224845: Passed. + pr2224949: Passed. + pr2233180: Passed. + pr2233180b: Passed. + pr2233180c: Passed. + pr2233192: Passed. + pr2233192b: Passed. + pr2233192c: Passed. + pr2248925: Passed. + pr2251119: Passed. + pr2257003: Passed. + pr2257003b: Passed. + pr2270035: Passed. + pr2276163: Passed. + pr2281479: Passed. + pr2305307: Passed. + pr2305307b: Passed. + pr2305307c: Passed. + pr2306259: Passed. + pr2350934: Passed. + pr2350934b: Passed. + pr2350988: Passed. + pr2352834: Passed. + pr2355304: Passed. + pr2355304b: Passed. + pr2358264: Passed. + pr2358848: Passed. + pr2395378a: Passed - CE. + pr2395378b: Passed - CE. + pr2395378c: Passed - CE. + pr2395835: Passed. + pr2425055a: Passed. + pr2425055b: Passed. + pr2425055c: Passed. + pr2428890: Passed. + pr2428890b: Passed. + pr2434688: Passed. + pr2434688b: Passed. + pr2450244: Passed. + pr2453002: Passed. + pr2459681: Passed. + pr2470181a: Passed. + pr2470181b: Passed. + pr2503208: Passed. + pr2528915: Passed - CE. + pr2533175: Passed. + pr2579479: Passed. + pr2580730: Passed. + pr2593733: Passed. + pr2597278: Passed. + pr2597278b: Passed - CE. + pr2605006: Passed. + pr2673846: Passed. + pr2688910: Passed. + pr2709097: Passed. + pr2715547: Passed. + pr2715558: Passed. + pr2715558b: Passed. + pr2721213: Passed. + pr2722330a: Passed. + pr2722330b: Passed. + pr2722339a: Passed. + pr2722339b: Passed. + pr2723712: Passed. + pr2725700a: Passed. + pr2725700b: Passed. + pr2725700c: Passed. + pr2728547: Passed. + pr2728812a: Passed. + pr2728812b: Passed - CE. + pr2728812c: Passed - CE. + pr2745281: Passed. + pr2781595: Passed. + pr2785294: Passed. + pr2788686: Passed. + pr2790236: Passed. + pr2792883: Passed - CE. + pr2792897: Passed. + pr2794144: Passed - CE. + pr2800985a: Passed. + pr2800985b: Passed. + pr2801134: Passed. + pr2801662: Passed. + pr2809288: Passed - CE. + pr2815398a: Passed. + pr2815398a_std: Passed. + pr2815398b: Passed. + pr2818823: Passed. + pr2823414: Passed - CE. + pr2823711: Passed. + pr2824189: Passed. + pr2829776: Passed. + pr2829776b: Passed. + pr2832234: Passed. + pr2834340: Passed. + pr2834340b: Passed. + pr2835632a: Passed. + pr2835632b: Passed. + pr2837451: Passed. + pr2842185: Passed. + pr2842621: Passed. + pr2842621_std: Passed. + pr2848986: Passed - CE. + pr2849783: Passed. + pr2865563: Passed. + pr2877564: Passed - CE. + pr2883958: Passed. + pr2885048: Passed. + pr2890322: Passed. + pr2901556: Passed. + pr2909386a: Passed. + pr2909386b: Passed. + pr2909414: Passed. + pr2909555: Passed. + pr2913404: Passed. + pr2913416: Passed. + pr2913438a: Passed. + pr2913438b: Passed. + pr2913927: Passed. + pr2918095: Passed. + pr2922063: Passed. + pr2922063a: Passed. + pr2922063b: Passed. + pr2924354: Passed. + pr2929913: Passed. + pr2930506: Passed. + pr2937417: Passed. + pr2937417b: Passed. + pr2937417c: Passed. + pr2941939: Passed. + pr2943394: Passed. + pr2951657: Passed. + pr2969724: Passed. + pr2971207: Passed. + pr2972866: Passed. + pr2973532: Passed. + pr2974051: Passed. + pr2974216: Passed. + pr2974216b: Passed. + pr2974294: Passed. + pr2985542: Passed. + pr2986497: Passed - CO. + pr2986528: Passed. + pr2991457: Passed. + pr2991457b: Passed. + pr2994193: Passed. + pr2998515: Passed. + pr3011327: Passed. + pr3012758: Passed. + pr3015421: Passed - CE. + pr3022502: Passed. + pr3024131: Passed. + pr3039548: Passed. + pr3044843: Passed. + pr3054101a: Passed. + pr3054101b: Passed. + pr3054101c: Passed. + pr3054101d: Passed. + pr3054101e: Passed. + pr3054101f: Passed. + pr3054101g: Passed. + pr3054101h: Passed. + pr3061015a: Passed - CE. + pr3061015b: Passed - CE. + pr3061015c: Passed - CE. + pr3064375: Passed. + pr3064511: Passed. + pr3077640: Passed. + pr3078759: Passed - CO. + pr3098439: Passed. + pr3098439a: Passed. + pr3098439b: Passed. + pr3103880: Passed. + pr3104254: Passed. + pr3112073a: Passed - CE. + pr3149494: Passed. + pr3190941: Passed - CE. + pr3190948: Passed. + pr3194155: Passed. + pr3197861: Passed. + pr3197917: Passed. + pr3270320: Passed - CE. + pr3284821: Passed. + pr3292735: Passed. + pr3296466a: Passed. + pr3296466b: Passed. + pr3296466c: Passed. + pr3296466d: Passed. + pr3306516: Passed. + pr3309391: Passed. + pr3368642: Passed. + pr3409749: Passed. + pr3437290a: Passed. + pr3437290b: Passed. + pr3437290c: Passed. + pr3441576: Passed. + pr3445452: Passed. + pr3452808: Passed. + pr3465541: Passed. + pr3477107: Passed. + pr3499807: Passed. + pr3522653: Passed. + pr3527022: Passed. + pr3527694: Passed. + pr3534422: Passed. + pr3539372: Passed. + pr3549328: Passed - CE. + pr3557493: Passed. + pr3561350: Passed. + pr3563412: Passed. + pr3571573: Passed. + pr3582052: Passed. + pr3587570: Passed. + pr3592746: Passed. + prng: Passed. + ptest001: Passed. + ptest002: Passed. + ptest003: Passed. + ptest004: Passed. + ptest005: Passed. + ptest006: Passed. + ptest007: Passed. + ptest008: Passed. + ptest009: Passed. + ptest010: Passed. + ptest011: Passed. + pullupdown: Passed. + pullupdown2: Passed. + pullupdown3: Passed. + pv_undef_sig_sel: Passed. + qmark: Passed. + qmark1: Passed. + qmark3: Passed. + qmark5: Passed. + qmark6: Passed. + queue: Passed. + queue_fail: Passed. + queue_stat: Passed. + ram16x1: Passed. + readmem-error: Passed. + readmem-invalid: Passed. + readmemb1: Passed. + readmemb2: Passed. + readmemb3: Passed. + readmemh1: Passed. + readmemh1a: Passed. + readmemh2: Passed. + readmemh3: Passed. + readmemh4: Passed. + readmemh5: Passed - CE. + real: Passed. + real2: Passed. + real3: Passed. + real5: Passed. + real6: Passed. + real7: Passed. + real9: Passed. + real10: Passed. + real11: Passed. + real_assign_deassign: Passed. + real_concat_invalid2: Passed - CE. + real_delay: Passed. + real_events: Passed. + real_force_rel: Passed. + real_invalid_ops: Passed - CE. + real_logical: Passed. + real_reg_force_rel: Passed. + recursive_func: Passed. + recursive_task: Passed. + repeat2: Passed. + repeat_expr_probe: Passed. + repl_zero_wid_fail: Passed - CE. + repl_zero_wid_pass: Passed. + resetall2: Passed. + resolv1: Passed. + rise_fall_decay1: Passed. + rise_fall_decay2: Passed. + rise_fall_delay1: Passed. + rise_fall_delay2: Passed. + rise_fall_delay3: Passed. + rl_pow: Passed. + rnpmos: Passed. + rnpmos2: Passed. + rop: Passed. + rptconcat: Passed. + scan-invalid: Passed. + scanf: Passed. + scanf2: Passed. + scanf3: Passed. + scanf4: Passed. + sched1: Passed. + sched2: Passed. + schedule: Passed. + scope1: Passed. + scope2: Passed. + scope2b: Passed - CE. + scope4: Passed. + scope5: Passed. + scoped_events: Passed. + sdf1: Passed. + sdf2: Passed. + sdf3: Passed. + sdf4: Passed. + sdf5: Passed. + sdf6: Passed. + sdf7: Passed. + sdf8: Passed. + sdf_del_max: Passed. + sdf_del_min: Passed. + sdf_del_typ: Passed. + sdf_esc_id: Passed. + sdw_always1: Passed. + sdw_always2: Passed. + sdw_always3: Passed. + sdw_array: Passed. + sdw_assign: Passed. + sdw_dsbl: Passed. + sdw_force: Passed. + sdw_function1: Passed. + sdw_function2: Passed. + sdw_function3: Passed. + sdw_function4: Passed. + sdw_function5: Passed. + sdw_instmod1: Passed. + sdw_instmod2: Passed. + sdw_int: Passed. + sdw_lvalconcat: Passed. + sdw_param1: Passed. + sdw_param2: Passed. + sdw_release: Passed. + sdw_stmt002: Passed. + sdw_task1: Passed. + sdw_task2: Passed. + sel_rval_bit_ob: Passed. + sel_rval_part_ob: Passed. + select: Passed. + select2: Passed. + select3: Passed. + select4: Passed. + select5: Passed. + select6: Passed. + select7: Passed. + select8: Passed. + select_padding: Passed. + shellho1: Passed. + shift1: Passed. + shift2: Passed. + shift3: Passed. + shift4: Passed. + shift5: Passed. + shift_pad: Passed. + signed1: Passed. + signed2: Passed. + signed3: Passed. + signed4: Passed. + signed5: Passed. + signed6: Passed. + signed7: Passed. + signed8: Passed. + signed9: Passed. + signed10: Passed. + signed11: Passed. + signed12: Passed. + signed13: Passed. + signed_a: Passed. + signed_equality: Passed. + signed_net_display: Passed. + signed_part: Passed. + signed_pv: Passed. + sp2: Passed. + specify1: Passed - CO. + specify2: Passed. + specify3: Passed. + specify4: Passed. + specify5: Passed. + specify_01: Passed. + sqrt32: Passed. + sscanf_u: Passed. + sscanf_z: Passed. + stask_parm1: Passed. + stask_parm2: Passed. + stask_sens_null_arg: Passed. + string1: Passed. + string2: Passed. + string3: Passed. + string4: Passed. + string5: Passed. + string7: Passed. + string8: Passed. + string9: Passed. + string10: Passed. + string11: Passed. + supply1: Passed. + supply2: Passed. + switch_primitives: Passed. + sys_func_task_error: Passed - RE. + sysargs: Passed. + talu: Passed. + task-scope: Passed. + task3.14A: Passed. + task3.14B: Passed. + task3.14C: Passed. + task3.14D: Passed. + task3.14E: Passed. + task3.14F: Passed. + task_bypath: Passed. + task_inpad: Passed. + task_iotypes: Passed. + task_iotypes2: Passed. + task_mem: Passed. + task_noop: Passed. + task_noop2: Passed - CO. + task_omemw2: Passed. + task_omemw3: Passed - CO. + task_port_size: Passed. + task_scope: Passed. + tern1: Passed. + tern2: Passed - CO. + tern4: Passed. + tern5: Passed. + tern6: Passed. + tern7: Passed. + tern9: Passed. + tern10: Passed. + test_bufif0: Passed. + test_bufif1: Passed. + test_disphob: Passed. + test_dispwided: Passed. + test_extended: Passed. +test_mos_strength_reduction: Passed. + test_nmos: Passed. + test_notif0: Passed. + test_notif1: Passed. + test_pmos: Passed. + test_rnmos: Passed. + test_rpmos: Passed. + test_width: Passed. + time1: Passed. + time2: Passed. + time3: Passed. + time4: Passed. + time5: Passed. + time7: Passed. + time8: Passed. + timeform1: Passed. + timeform2: Passed. + timescale1: Passed. + timescale2: Passed. + timescale3: Passed - CE. + tran: Passed. + tranif0: Passed. + tranif1: Passed. + tran-keeper: Passed. + tri0: Passed. + tri0b: Passed. + tri1: Passed. + tri2: Passed. + tri3: Passed. + triand: Passed. + trior: Passed. + types1: Passed. + udp_bufg: Passed. + udp_bufg2: Passed. + udp_bx: Passed. + udp_delay_fail: Passed - CE. + udp_dff: Passed. + udp_dff_std: Passed. + udp_eval_arg: Passed. + udp_jkff: Passed. + udp_real_delay: Passed. + udp_sched: Passed. + udp_x: Passed. + unary_and: Passed. + unary_lnot1: Passed. + unary_lnot2: Passed. + unary_lnot3: Passed. + unary_minus: Passed. + unary_minus1: Passed. + unary_minus2: Passed. + unary_minus3: Passed. + unary_minus4: Passed. + unary_nand: Passed. + unary_nand2: Passed. + unary_nor: Passed. + unary_nor2: Passed. + unary_not: Passed. + unary_or: Passed. + unary_xnor1: Passed. + unary_xnor2: Passed. + unary_xor: Passed. + uncon_drive: Passed. + undef: Passed. + undef_lval_select: Passed. + undef_lval_select2: Passed. + undef_lval_select3a: Passed. + undef_lval_select3b: Passed - CE. + undef_lval_select3c: Passed - CE. + undef_lval_select4a: Passed. + undef_lval_select4b: Passed - CE. + undef_lval_select4c: Passed - CE. + undef_lval_select5: Passed. + undefined_shift: Passed. + urand: Passed. + urand_r: Passed. + urand_r2: Passed. + urand_r3: Passed. + uwire: Passed. + uwire2: Passed. + uwire_fail: Passed - CE. + vardly: Passed. + varlsfht: Passed. + varlsfht1: Passed. + varlsfht2: Passed. + varrshft: Passed. + varrshft1: Passed. + varrshft2: Passed. + vcd-dup: Passed. + vector: Passed. + verify_two_var_delays: Passed. + vvp_scalar_value: Passed. + wait1: Passed. + wait2: Passed. + wait3: Passed. + warn_opt_sys_tf: Passed. + wildsense: Passed. + wildsense2: Passed. + wireadd1: Passed. + wireeq: Passed. + wirege: Passed. + wireland: Passed. + wirele: Passed. + wiremod1: Passed. + wiresl: Passed. + wiresl2: Passed. + wiresr: Passed. + wiresub1: Passed. + wirexor1: Passed. + writemem-error: Passed. + writemem-invalid: Passed. + writememb1: Passed. + writememb2: Passed. + writememh1: Passed. + writememh2: Passed. + xnor_test: Passed. + z1: Passed. + z2: Passed. + zero_repl: Passed. + zero_repl_fail: Passed - CE. + cmpi: Passed. + br_gh99c: Passed. + cast_int: Passed. + constfunc4: Passed. + scaled_real: Passed. + test_vams_math: Passed. + value_range1: Passed. + value_range2: Passed. + value_range3: Passed - CE. + vams_abs1: Passed. + vams_abs2: Passed. + wreal: Passed. + always4A: Passed - CE. + always4B: Passed - CE. + array_size: Passed. + array_string: Passed. + array_unpacked_sysfunct: Passed. + assign_op_concat: Passed. + assign_op_type: Passed. + bitp1: Passed. + bits: Passed. + bits2: Passed. + br884: Passed. + br917a: Passed. + br917b: Passed. + br917c: Passed. + br917d: Passed. + br921: Passed. + br932a: Passed. + br932b: Passed. + br936: Passed. + br956: Passed. + br959: Passed. + br962: Passed. + br963: Passed. + br973: Passed. + br974a: Passed. + br974b: Passed. + br974c: Passed. + br979: Passed. + br991b: Passed - CE. + br1003d: Passed. + br1005: Passed - CE. + br1015b: Passed - CE. + br1025: Passed. + br1027b: Passed. + br1027d: Passed. + br1027f: Passed. + br_gh4: Passed. + br_gh4a: Passed. + br_gh72a: Passed. + br_gh72b: Passed. + br_gh99e: Passed. + br_gh104a: Passed. + br_gh104b: Passed. + br_gh105a: Passed. + br_gh105b: Passed. + br_gh112a: Passed. + br_gh112b: Passed. + br_gh112c: Passed. + br_gh112d: Passed. + br_gh112e: Passed. + br_gh112f: Passed. + br_gh129: Passed. + br_gh130a: Passed - CE. + br_gh130b: Passed - CE. + br_gh165: Passed. + br_gh164a: Passed. + br_gh164b: Passed. + br_gh164c: Passed. + br_gh164d: Passed. + br_gh164e: Passed. + br_gh167a: Passed. + br_gh167b: Passed. + br_gh194: Passed. + br_gh219: Passed. + br_gh220: Passed. + br_gh224: Passed. + br_gh231: Passed. + br_gh243: Passed. + br_gh280: Passed. + br_gh289d: Passed. + br_gh361: Passed. + br_ml20150315b: Passed - CE. + br_ml20171017: Passed. + br_ml20181012a: Passed - CE. + br_ml20181012b: Passed - CE. + br_ml20181012c: Passed - CE. + br_ml20181012d: Passed - CE. + br_mw20200501: Passed. + cast_real: Passed. + cfunc_assign_op_mixed: Passed. + cfunc_assign_op_pv: Passed. + cfunc_assign_op_real: Passed. + cfunc_assign_op_vec: Passed. + clkgen_bit: Passed. + clkgen_logic: Passed. + clkgen_net: Passed. + clkgen_reg: Passed. + disable_fork_cmd: Passed. + display_bug: Passed. + enum_base_range: Passed. + enum_elem_ranges: Passed. + enum_next: Passed. + enum_ports: Passed. + enum_test1: Passed. + enum_test2: Passed. + enum_test3: Passed - CE. + enum_test4: Passed. + enum_test5: Passed - CE. + enum_test6: Passed - CE. + enum_test7: Passed - CE. + enum_test8: Passed. + enum_value_expr: Passed. + enum_values: Passed. + final: Passed. + final2: Passed. + first_last_num: Passed. + fork_join_any: Passed. + fork_join_dis: Passed. + fork_join_none: Passed. + fr49: Passed. + func_init_var1: Passed. + func_init_var3: Passed. + ibit_test: Passed. + ibyte_test: Passed. + iint_test: Passed. + ilongint_test: Passed. + implicit_cast1: Passed. + implicit_cast2: Passed. + implicit_cast3: Passed. + implicit_cast4: Passed. + implicit_cast5: Passed. + implicit_cast6: Passed. + implicit_cast7: Passed. + implicit_cast8: Passed. + implicit_cast9: Passed. + implicit_cast10: Passed. + implicit_cast11: Passed. + implicit_cast12: Passed. + implicit_cast13: Passed. + implicit-port1: Passed. + implicit-port2: Passed - CE. + implicit-port3: Passed - CE. + implicit-port4: Passed. + implicit-port5: Passed. + implicit-port6: Passed - CE. + implicit-port7: Passed. + inc_dec_stmt: Passed. + int_param: Passed. + ishortint_test: Passed. + iuint1: Passed. + localparam_query: Passed. + localparam_type2: Passed. + logp2: Passed. + mod_inst_pkg: Passed. + named_begin: Passed. + named_begin_fail: Passed - CE. + named_fork: Passed. + named_fork_fail: Passed - CE. + packeda: Passed. + packeda2: Passed. + parameter_type2: Passed. + parpkg_test: Passed. + parpkg_test2: Passed. + parpkg_test3: Passed. + part_sel_port: Passed. + plus_5: Passed. + plus_arg_string: Passed. + pr3366114: Passed. + pr3366217a: Passed - CE. + pr3366217b: Passed - CE. + pr3366217c: Passed - CE. + pr3366217d: Passed - CE. + pr3366217e: Passed. + pr3366217f: Passed. + pr3366217g: Passed - CE. + pr3366217h: Passed. + pr3366217i: Passed. + pr3390385: Passed. + pr3390385b: Passed. + pr3390385c: Passed. + pr3390385d: Passed. + pr3462145: Passed. + pr3515542: Passed - CE. + pr3534333: Passed. + pr3576165: Passed. + program2: Passed. + program2b: Passed - CE. + program3: Passed. + program3a: Passed - CE. + program3b: Passed - CE. + program4: Passed. + program5a: Passed - CE. + program5b: Passed - CE. + program_hello: Passed. + program_hello2: Passed - CE. + sbyte_test: Passed. + simple_byte: Passed. + simple_int: Passed. + simple_longint: Passed. + simple_shortint: Passed. + sint_test: Passed. + size_cast: Passed. + size_cast2: Passed. + size_cast3: Passed. + size_cast4: Passed. + size_cast5: Passed. + slongint_test: Passed. + sshortint_test: Passed. + string_index: Passed. + struct1: Passed. + struct2: Passed. + struct3: Passed. + struct3b: Passed. + struct4: Passed. + struct5: Passed. + struct6: Passed. + struct7: Passed. + struct8: Passed. + struct9: Passed. + struct_packed_array: Passed. + struct_packed_array2: Passed. + struct_packed_sysfunct: Passed. + struct_packed_write_read2: Passed. + sv-2val-nets: Passed. + sv-constants: Passed. + sv_array_assign_pattern2: Passed. + sv_cast_integer: Passed. + sv_cast_integer2: Passed. + sv_cast_string: Passed. + sv_class1: Passed. + sv_class2: Passed. + sv_class3: Passed. + sv_class4: Passed. + sv_class5: Passed. + sv_class6: Passed. + sv_class7: Passed. + sv_class8: Passed. + sv_class9: Passed. + sv_class10: Passed. + sv_class11: Passed. + sv_class12: Passed. + sv_class13: Passed. + sv_class14: Passed. + sv_class15: Passed. + sv_class16: Passed. + sv_class17: Passed. + sv_class18: Passed. + sv_class19: Passed. + sv_class20: Passed. + sv_class21: Passed. + sv_class22: Passed. + sv_class23: Passed. + sv_class24: Passed. + sv_darray1: Passed. + sv_darray2: Passed. + sv_darray3: Passed. + sv_darray4: Passed. + sv_darray5: Passed. + sv_darray5b: Passed. + sv_darray6: Passed. + sv_darray_args1: Passed. + sv_darray_args2: Passed. + sv_darray_args2b: Passed. + sv_darray_args3: Passed. + sv_darray_args4: Passed. + sv_darray_function: Passed. + sv_darray_signed: Passed. + sv_darray_word_size: Passed. + sv_end_label: Passed. + sv_end_label_fail: Passed - CE. + sv_end_labels: Passed. + sv_end_labels_bad: Passed - CE. + sv_enum1: Passed. + sv_for_variable: Passed. + sv_foreach1: Passed. + sv_foreach2: Passed. + sv_foreach3: Passed. + sv_foreach4: Passed. + sv_foreach5: Passed. + sv_macro: Passed. + sv_macro2: Passed. + sv_package: Passed. + sv_package2: Passed. + sv_package3: Passed. + sv_package4: Passed. + sv_package5: Passed. + sv_packed_port1: Passed. + sv_packed_port2: Passed. + sv_pkg_class: Passed. + sv_port_default1: Passed. + sv_port_default2: Passed. + sv_port_default3: Passed. + sv_port_default4: Passed. + sv_port_default5: Passed. + sv_port_default6: Passed. + sv_port_default7: Passed. + sv_port_default8: Passed. + sv_port_default9: Passed. + sv_port_default10: Passed. + sv_port_default11: Passed. + sv_port_default12: Passed. + sv_port_default13: Passed - CE. + sv_port_default14: Passed - CE. + sv_queue1: Passed. + sv_queue2: Passed. + sv_queue3: Passed. + sv_root_class: Passed. + sv_root_func: Passed. + sv_root_task: Passed. + sv_string1: Passed. + sv_string2: Passed. + sv_string3: Passed. + sv_string4: Passed. + sv_string5: Passed. + sv_timeunit_prec1: Passed. + sv_timeunit_prec2: Passed. + sv_timeunit_prec3a: Passed. + sv_timeunit_prec3c: Passed. + sv_timeunit_prec3d: Passed. + sv_timeunit_prec4a: Passed. + sv_typedef_scope: Passed. + sv_union1: Passed. + sv_union1b: Passed. + sv_union2: Passed. + sv_union2b: Passed. + sv_union3: Passed. + sv_union3b: Passed. + sv_union4b: Passed. + sv_unit1b: Passed. + sv_unpacked_port: Passed. + sv_unpacked_port2: Passed. + sv_unpacked_wire: Passed. + sv_unpacked_wire2: Passed. + sv_uwire1: Passed. + sv_uwire2: Passed. + sv_uwire3: Passed. + sv_uwire4: Passed. + sv_var_init1: Passed. + sv_var_init2: Passed. + sys_func_as_task: Passed. + task_init_assign: Passed. + task_init_var1: Passed. + task_init_var2: Passed. + task_init_var3: Passed. + task_scope2: Passed. + test_inc_dec: Passed. + test_tliteral: Passed. + two_state_display: Passed. + ubyte_test: Passed. + uint_test: Passed. + ulongint_test: Passed. + undef_lval_select_SV: Passed. + unp_array_typedef: Passed. + ushortint_test: Passed. + wait_fork: Passed. + sf1289: Passed. + br942: Passed. + br943_944: Passed. + br985: Passed. + br986: Passed. + br987: Passed. + ivlh_event: Passed. + ivlh_rising_falling: Passed. + test_dec2to4: Passed. + test_enumsystem: Passed. + test_forgen: Passed. + test_gxor: Passed. + test_mux2to1: Passed. + test_signal_init_assign: Passed. + test_system: Passed. + test_timebase: Passed. + test_varray1: Passed. + test_work14: Passed. + vhdl_and104_stdlogic: Passed. + vhdl_and23_bit: Passed. + vhdl_and_gate: Passed. + vhdl_andg_bit: Passed. + vhdl_andg_stdlogic: Passed. + vhdl_array_of_array: Passed. + vhdl_case_multi: Passed. + vhdl_boolean: Passed. + vhdl_concat: Passed. + vhdl_concat_func: Passed. + vhdl_const_package: Passed. + vhdl_const_record: Passed. + vhdl_const_array: Passed. + vhdl_expr1: Passed. + vhdl_generic_eval: Passed. + vhdl_fa4_test1: Passed. + vhdl_fa4_test2: Passed. + vhdl_fa4_test3: Passed. + vhdl_fa4_test4: Passed. + vhdl_generic_default: Passed. + vhdl_init: Passed. + vhdl_inout: Passed. + vhdl_labeled_assign: Passed. + vhdl_logic: Passed. + vhdl_nand104_stdlogic: Passed. + vhdl_nand23_bit: Passed. + vhdl_nandg_bit: Passed. + vhdl_nandg_stdlogic: Passed. + vhdl_nor104_stdlogic: Passed. + vhdl_nor23_bit: Passed. + vhdl_norg_bit: Passed. + vhdl_norg_stdlogic: Passed. + vhdl_not104_stdlogic: Passed. + vhdl_not23_bit: Passed. + vhdl_notfunc_stdlogic: Passed. + vhdl_notg_bit: Passed. + vhdl_notg_stdlogic: Passed. + vhdl_or104_stdlogic: Passed. + vhdl_or23_bit: Passed. + vhdl_org_bit: Passed. + vhdl_org_stdlogic: Passed. + vhdl_prefix_array: Passed. + vhdl_procedure: Passed. + vhdl_rand23_bit: Passed. + vhdl_range_func: Passed. + vhdl_real: Passed. + vhdl_record_elab: Passed. + vhdl_reduce: Passed. + vhdl_report: Passed. + vhdl_rtoi: Passed. + vhdl_sa1_test1: Passed. + vhdl_sa1_test2: Passed. + vhdl_sa1_test3: Passed. + vhdl_sadd23_bit: Passed. + vhdl_sadd23_stdlogic: Passed. + vhdl_sdiv23_bit: Passed. + vhdl_sdiv23_stdlogic: Passed. + vhdl_selected: Passed. + vhdl_signals: Passed. + vhdl_smul23_bit: Passed. + vhdl_smul23_stdlogic: Passed. + vhdl_ssub23_bit: Passed. + vhdl_ssub23_stdlogic: Passed. + vhdl_struct_array: Passed. + vhdl_subprogram: Passed. + vhdl_test1: Passed. + vhdl_test2: Passed. + vhdl_test3: Passed. + vhdl_test4: Passed. + vhdl_test5: Passed. + vhdl_test6: Passed. + vhdl_test7: Passed. + vhdl_test8: Passed. + vhdl_test9: Passed. + vhdl_time: Passed. + vhdl_to_integer: Passed. + vhdl_uadd23_bit: Passed. + vhdl_uadd23_stdlogic: Passed. + vhdl_udiv23_bit: Passed. + vhdl_udiv23_stdlogic: Passed. + vhdl_umul23_bit: Passed. + vhdl_umul23_stdlogic: Passed. + vhdl_unbounded: Passed. + vhdl_unbounded_func: Passed. + vhdl_usub23_bit: Passed. + vhdl_usub23_stdlogic: Passed. + vhdl_var_init: Passed. + vhdl_xnor104_stdlogic: Passed. + vhdl_xnor23_bit: Passed. + vhdl_xnorg_bit: Passed. + vhdl_xnorg_stdlogic: Passed. + vhdl_xor23_bit: Passed. + vhdl_xorg_bit: Passed. + vhdl_xorg_stdlogic: Passed. + work7: Passed. + work7b: Passed. + basicexpr: Passed. + basicexpr2: Passed. + basicexpr3: Passed. + basicexpr4: Passed. + basicreg: Passed. + basicstate: Passed. + basicstate2: Passed. + blocksynth1: Passed. + br994: Passed. + br995: Passed - CE. + br_gh99v: Passed. + br_gh99w: Passed. + br_gh99x: Passed. + br_gh306a: Passed - CE. + br_gh306b: Passed - CE. + case3: Passed. + case7: Passed. + case_wo_default: Passed. + casesynth4: Passed. + casesynth5: Passed. + casesynth6: Passed. + casesynth8: Passed - CE. + casesynth9: Passed. + dffsynth2: Passed. + dffsynth5: Passed. + dffsynth6: Passed. + dffsynth7: Passed. + dffsynth8: Passed - CE. + ff_dual_enable: Passed. + for_loop_synth: Passed. + for_loop_synth2: Passed. + if_part_no_else: Passed. + if_part_no_else2: Passed. + inside_synth2: Passed. + land5: Passed. + lcatsynth: Passed. + memsynth4: Passed. + memsynth8: Passed. + not_a_latch1: Passed. + not_a_latch2: Passed. + partselsynth: Passed. + pr519: Passed. + pr685: Passed. + shiftl: Passed. + ssetclr1: Passed. + ssetclr2: Passed. + synth_if_no_else: Passed. + ufuncsynth1: Passed. +============================================================================ +Test results: + Total=2477, Passed=2338, Failed=4, Not Implemented=130, Expected Fail=5 diff --git a/ivtest/regression_report-v11.txt b/ivtest/regression_report-v11.txt new file mode 100644 index 000000000..f2f06d9f4 --- /dev/null +++ b/ivtest/regression_report-v11.txt @@ -0,0 +1,2560 @@ +Running compiler/VVP tests for Icarus Verilog version: 11. +---------------------------------------------------------------------------- + param_test3: Passed. + eofmt_percent: Passed. + pr1916261a: Passed. + comment1: Passed. + line_directive: Passed - expected fail. + program2b: Passed - CE. + program3a: Passed - CE. + sv_default_port_value1: Passed - CE. + sv_default_port_value2: Passed - CE. + sv_default_port_value3: Passed - CE. + br_gh440: Passed - CE. + dffsynth: Passed - CE. + memsynth1: Passed - CE. + memsynth2: Passed - CE. + memsynth3: Passed - CE. + memsynth5: Passed - CE. + memsynth6: Passed - CE. + memsynth7: Passed - CE. + memsynth9: Passed - CE. + mix_reset: Passed - CE. + case1: Passed. + case2: Passed. + casex_synth: Passed. + automatic_error11: Passed. + automatic_error12: Passed. + automatic_error13: Passed. + br_gh230: Passed. + fdisplay3: Passed. + fread-error: Passed. + pr2800985b: Passed. + queue_fail: Passed. + readmem-invalid: Passed. + scan-invalid: Passed. + warn_opt_sys_tf: Passed. + writemem-invalid: Passed. + sf_countbits_fail: Passed. + sf_countones_fail: Passed. + sf_isunknown_fail: Passed. + sf_onehot_fail: Passed. + sf_onehot0_fail: Passed. + analog1: Not Implemented. + analog2: Not Implemented. + br605a: Not Implemented. + br605b: Not Implemented. + br971: Not Implemented. + br_gh72b_fail: Not Implemented. + br_gh175: Not Implemented. + br_gh307: Not Implemented. + br_gh383a: Not Implemented. + br_gh383b: Not Implemented. + br_gh383c: Not Implemented. + br_gh383d: Not Implemented. + br_gh390a: Not Implemented. + br_gh390b: Not Implemented. + br_gh412: Not Implemented. + br_gh414: Not Implemented. + br_gh436: Not Implemented. + br_gh453: Not Implemented. + br_gh460: Not Implemented. + br_gh478: Not Implemented. + br_gh527: Not Implemented. + edge: Not Implemented. + fileline2: Not Implemented. + ifdef_fail: Not Implemented. + scalar_vector: Not Implemented. + string12: Not Implemented. + sv_deferred_assert1: Not Implemented. + sv_deferred_assert2: Not Implemented. + sv_deferred_assume1: Not Implemented. + sv_deferred_assume2: Not Implemented. + timeliteral: Not Implemented. + vhdl_multidim_array: Not Implemented. + pr903: Passed. + pr1388974: Passed. + br_gh13a: Passed. + param-width: Passed. + ca_time_real: Passed. + delayed_sfunc: Passed. + localparam_type: Passed. + parameter_type: Passed. + pr1701890: Passed. + pr1864110a: Passed. + pr1864110b: Passed. + pr1864115: Passed. + macro_str_esc: Passed. + macro_with_args: Passed. + mcl1: Passed. + pr622: Passed. + pr639: Passed. + pr1741212: Passed. + pr1912112: Passed. + pr1925360: Passed. + repeat1: Passed. + pr2002443: Passed - CO. + constfunc6_ams: Passed. + non-polymorphic-abs: Passed. + pr3270320_ams: Passed - CE. + test_va_math: Passed. + va_math: Passed. + abstime: Passed. + pr2590274a: Passed. + pr2590274b: Passed. + pr2590274c: Passed. + bitsel: Passed. + bitsel10: Passed. + bitsel2: Passed. + bitsel3: Passed. + bitsel4: Passed. + bitsel5: Passed. + bitsel6: Passed. + bitsel7: Passed. + bitsel8: Passed. + bitsel9: Passed. + bitwidth3: Passed. + clog2: Passed. + clog2-signal: Passed. + param_vec: Passed. + param_vec2: Passed. + pr498: Passed. + pr721: Passed. + pr809: Passed. + pr809b: Passed. + pr979: Passed. + pr1000: Passed. + pr1609611: Passed. + pr1750870: Passed. + pr1765789: Passed. + pr1771903: Passed. + pr1793749: Passed. + pr1793749b: Passed. + pr1861212b: Passed. + pr1864110c: Passed. + pr2806449: Passed. + pr2877555: Passed. + real4: Passed. + realtobits: Passed. + specparam1: Passed. + specparam2: Passed. + tern3: Passed. + v2005_math: Passed. + deposit: Passed. + deposit_wire: Passed. + sysargs: Passed. + fatal_et_al: Passed. + fatal_et_al2: Passed - RE. + plus_arg_string: Passed. + fileio: Passed. + pr1494799: Passed. + pr2428890c: Passed. + sv_cast_darray: Passed. + br978: Passed. + br_ml20150424: Passed. + pr2509349a: Passed. + pr2509349b: Passed. + simparam: Passed. + blocking_repeat_ec: Passed. + ca_time_smtm: Passed. + nb_array_pv: Passed. + nb_ec_array: Passed. + nb_ec_array_pv: Passed. + nb_ec_pv: Passed. + nb_ec_pv2: Passed. + nb_ec_real: Passed. + nb_ec_vector: Passed. + pr2486350: Passed. + pr534: Passed. + stime: Passed. + swrite: Passed. + time6: Passed. + time6b: Passed. + time6c: Passed. + concat1: Passed. + concat2: Passed. + constconcat1: Passed. + constconcat2: Passed. + rptconcat2: Passed. + sdw_lvalconcat2: Passed. + bool1: Passed. + compare_bool_reg: Passed. + constfunc8: Passed. + binary_nand: Passed. + binary_nor: Passed. + pr1528093: Passed. + br_gh456: Passed. + ca_64delay: Passed. + ca_var_delay: Passed. + cast_real_signed: Passed. + cast_real_unsigned: Passed. + pr1861212c: Passed. + pr1873372: Passed. + pr1880003: Passed. + pr1898293: Passed. + pr2123158: Passed. + pr2453002b: Passed. + pr2456943: Passed. + pr2715748: Passed. + pr2806474: Passed. + pr2976242: Passed. + pr2976242b: Passed. + pr2976242c: Passed - CE. + real8: Passed. + real_array: Passed. + real_array_nb: Passed. + real_concat_invalid1: Passed - CE. + real_mod_in_ca: Passed. + real_op_fail: Passed - CE. + real_pulse_clean: Passed. + real_pwr_in_ca: Passed. + real_select_invalid: Passed - CE. + real_wire_array: Passed. + real_wire_force_rel: Passed. + tern8: Passed. + br_gh99e: Passed. + pull371: Passed. + sv-2val-nets: Passed. + pr2476430: Passed. + br_gh377: Passed. + cmdline_parm1: Passed. + array_dump: Passed. + pr2859628: Passed. + big_int: Passed. + ca_pow_signed: Passed. + urand: Passed. + race: Passed. + automatic_error4: Passed - CE. + array_lval_select3a: Passed - CE. + br1005: Passed - CE. + br1015b: Passed - CE. + br_gh130b: Passed - CE. + br_gh386d: Passed - CE. + br_ml20150315b: Passed - CE. + pr1909940: Passed. + pr1909940b: Passed. + unnamed_generate_block: Passed. + br_gh497b: Passed - CE. + br_gh497d: Passed - CE. + br_gh497f: Passed - CE. + addsr: Passed. + addwide: Passed. + always3.1.1A: Passed - CE. + always3.1.1B: Passed - CE. + always3.1.1C: Passed. + always3.1.1D: Passed. + always3.1.1E: Passed. + always3.1.1F: Passed. + always3.1.1G: Passed. + always3.1.1H: Passed. + always3.1.1I: Passed. + always3.1.1J: Passed. + always3.1.1K: Passed. + always3.1.2A: Passed - CE. + always3.1.2B: Passed - CE. + always3.1.2C: Passed - CE. + always3.1.2D: Passed - CE. + always3.1.2E: Passed - CE. + always3.1.2F: Passed - CE. + always3.1.2G: Passed - CE. + always3.1.2H: Passed - CE. + always3.1.2I: Passed - CE. + always3.1.3A: Passed - CE. + always3.1.3B: Passed - CE. + always3.1.3B2: Passed. + always3.1.3C: Passed - CE. + always3.1.3D: Passed - CE. + always3.1.3D2: Passed. + always3.1.3E: Passed - CE. + always3.1.3E2: Passed. + always3.1.3F: Passed - CE. + always3.1.3F2: Passed. + always3.1.3G: Passed - CE. + always3.1.3H: Passed - CE. + always3.1.3J: Passed - CE. + always3.1.4A: Passed. + always3.1.4B: Passed. + always3.1.4C: Passed. + always3.1.4D: Passed. + always3.1.4E: Passed. + always3.1.4F: Passed. + always3.1.4G: Passed. + always3.1.4H: Passed. + always3.1.4I: Passed. + always3.1.5A: Passed. + always3.1.5B: Passed. + always3.1.5C: Passed. + always3.1.5D: Passed. + always3.1.5E: Passed. + always3.1.5F: Passed. + always3.1.6A: Passed. + always3.1.6B: Passed. + always3.1.6C: Passed. + always3.1.6D: Passed. + always3.1.7A: Passed. + always3.1.7B: Passed. + always3.1.7C: Passed. + always3.1.7D: Passed. + always3.1.8A: Passed. + always3.1.9A: Passed - CE. + always3.1.9B: Passed - CE. + always3.1.9C: Passed. + always3.1.9D: Passed. + always3.1.10A: Passed - CE. + always3.1.11A: Passed. + always3.1.11B: Passed. + always3.1.12A: Passed. + always3.1.12B: Passed. + always3.1.12C: Passed. + always_star_array_lval: Passed. + andnot1: Passed. + arith-unknown: Passed. + array4: Passed. + array5: Passed - CE. + array6: Passed. + array7: Passed. + array_lval_select1: Passed. + array_lval_select2: Passed. + array_lval_select3b: Passed - CE. + array_lval_select3c: Passed. + array_lval_select4a: Passed. + array_lval_select4b: Passed - CE. + array_lval_select5: Passed. + array_lval_select6: Passed. + array_packed_2d: Passed. + array_select: Passed. + array_select_a: Passed. + array_word_check: Passed. + array_word_width: Passed. + array_word_width2: Passed. + assign3.2A: Passed. + assign3.2B: Passed. + assign3.2C: Passed. + assign3.2D: Passed. + assign3.2E: Passed. + assign_add: Passed. + assign_deassign_pv: Passed. + assign_delay: Passed. + assign_deq: Passed. + assign_ge: Passed. + assign_le: Passed. + assign_mem1: Passed. + assign_mem2: Passed. + assign_nb1: Passed. + assign_nb2: Passed. + assign_neq: Passed. + attrib: Passed. + attrib01_module: Passed. + attrib02_port_decl: Passed. + attrib03_parameter: Passed. + attrib04_net_var: Passed. + attrib05_port_conn: Passed. + attrib06_operator_suffix: Passed. + attrib07_func_call: Passed. + attrib08_mod_inst: Passed. + attrib09_case: Passed. + automatic_error1: Passed - CE. + automatic_error2: Passed - CE. + automatic_error3: Passed - CE. + automatic_error5: Passed - CE. + automatic_error6: Passed - CE. + automatic_error7: Passed - CE. + automatic_error8: Passed - CE. + automatic_error9: Passed - CE. + automatic_error10: Passed - CE. + automatic_events: Passed. + automatic_events2: Passed. + automatic_events3: Passed. + automatic_task: Passed. + automatic_task2: Passed. + automatic_task3: Passed. + bitwidth: Passed. + bitwidth2: Passed. + blankport: Passed. + block_only_with_var_def: Passed. + bnot: Passed. + br916a: Passed. + br916b: Passed. + br918a: Passed. + br918b: Passed. + br918c: Passed. + br918d: Passed. + br919: Passed. + br924: Passed - CE. + br930: Passed - CO. + br931: Passed. + br935: Passed. + br937: Passed. + br946: Passed. + br947: Passed. + br948: Passed. + br955: Passed. + br960a: Passed. + br960b: Passed. + br960c: Passed. + br960d: Passed. + br961: Passed. + br961a: Passed - CE. + br965: Passed. + br967: Passed. + br968: Passed. + br972: Passed. + br977: Passed. + br982: Passed - CE. + br982a: Passed - CE. + br982b: Passed - CE. + br988: Passed. + br990: Passed. + br991a: Passed. + br999: Passed. + br1000: Passed. + br1001: Passed. + br1006: Passed. + br1007: Passed. + br1008: Passed. + br1015a: Passed - CE. + br1019: Passed. + br1027: Passed. + br1027a: Passed - CE. + br1027c: Passed - CE. + br1027e: Passed - CE. + br1029a: Passed. + br1029b: Passed. + br1029c: Passed - CE. + br_gh6: Passed. + br_gh7: Passed. + br_gh8: Passed. + br_gh9: Passed. + br_gh11: Passed - CO. + br_gh12: Passed. + br_gh13: Passed. + br_gh14: Passed. + br_gh15: Passed. + br_gh18: Passed. + br_gh19: Passed. + br_gh19a: Passed. + br_gh19b: Passed. + br_gh22: Passed. + br_gh25a: Passed - CE. + br_gh25b: Passed - CE. + br_gh26: Passed - CE. + br_gh28: Passed. + br_gh30: Passed. + br_gh33: Passed. + br_gh37: Passed. + br_gh60a: Passed - CE. + br_gh62: Passed - CE. + br_gh79: Passed - CE. + br_gh99a: Passed. + br_gh99b: Passed. + br_gh99d: Passed. + br_gh99f: Passed. + br_gh99g: Passed. + br_gh99h: Passed. + br_gh99i: Passed. + br_gh99j: Passed. + br_gh99k: Passed. + br_gh99l: Passed. + br_gh99m: Passed. + br_gh99o: Passed. + br_gh99p: Passed. + br_gh99q: Passed. + br_gh99r: Passed. + br_gh99s: Passed. + br_gh99t: Passed. + br_gh99u: Passed. + br_gh103: Passed. + br_gh127a: Passed. + br_gh127b: Passed. + br_gh127c: Passed. + br_gh127d: Passed. + br_gh127e: Passed. + br_gh127f: Passed. + br_gh142: Passed - CE. + br_gh152: Passed - CE. + br_gh157: Passed. + br_gh162: Passed. + br_gh163: Passed - CE. + br_gh198: Passed. + br_gh199a: Passed. + br_gh199b: Passed. + br_gh209: Passed. + br_gh244a: Passed. + br_gh244b: Passed. + br_gh277a: Passed. + br_gh283a: Passed. + br_gh283b: Passed. + br_gh283c: Passed. + br_gh309: Passed. + br_gh315: Passed. + br_gh316a: Passed. + br_gh316b: Passed. + br_gh316c: Passed. + br_gh330: Passed. + br_gh345: Passed. + br_gh356a: Passed. + br_gh356b: Passed. + br_gh435: Passed. + br_gh484: Passed. + br_gh497a: Passed. + br_gh497c: Passed. + br_gh497e: Passed. + br_gh508b: Passed. + br_gh515: Passed. + br_gh531: Passed. + br_gh533: Passed - CE. + br_gh567: Passed. + br_ml20150315: Passed. + br_ml20150321: Passed - CE. + br_ml20150606: Passed. + br_mw20171108: Passed. + br_ml20190806a: Passed. + br_ml20190806b: Passed. + br_ml20190814: Passed. + bufif: Passed. + busbug: Passed. + ca_force: Passed. + ca_func: Passed. + ca_mult: Passed. + ca_pow_synth: Passed. + ca_pow_unsigned: Passed. + ca_real_logical: Passed. + ca_time: Passed. + case3.8A: Passed. + case3.8B: Passed. + case3.8C: Passed. + case3.8D: Passed. + casex3.9A: Passed. + casex3.9B: Passed. + casex3.9C: Passed. + casex3.9D: Passed. + casex3.9E: Passed. + casez3.10A: Passed. + casez3.10B: Passed. + casez3.10C: Passed. + casez3.10D: Passed. + casez3.10E: Passed. + cast_int: Passed. + check_constant_1: Passed - CE. + check_constant_2: Passed - CE. + check_constant_3: Passed - CE. + check_constant_4: Passed - CE. + check_constant_5: Passed - CE. + check_constant_6: Passed - CE. + check_constant_7: Passed - CE. + check_constant_8: Passed - CE. + check_constant_9: Passed - CE. + check_constant_10: Passed - CE. + check_constant_11: Passed - CE. + check_constant_12: Passed - CE. + check_constant_13: Passed - CE. + check_constant_14: Passed - CE. + check_constant_15: Passed - CE. + check_constant_16: Passed - CE. + check_constant_17: Passed - CE. + check_constant_18: Passed - CE. + check_constant_19: Passed - CE. + check_constant_20: Passed - CE. + cmos: Passed. + comp1000: Passed. + comp1001: Passed. + comp1001_fail3: Passed. + comp1001_fail4: Passed. + comp1001_fail5: Passed. + complex_lidx: Passed. + con_tri: Passed. + concat3: Passed. + concat4: Passed. + concat_zero_wid_fail: Passed - CE. + concat_zero_wid_fail2: Passed. + cond_band: Passed. + cond_wide: Passed. + cond_wide2: Passed. + const: Passed. + const2: Passed. + const3: Passed. + const4: Passed. + constadd: Passed. + constadd2: Passed. + constadd3: Passed. + constfunc1: Passed. + constfunc2: Passed. + constfunc3: Passed. + constfunc4: Passed. + constfunc5: Passed. + constfunc6: Passed. + constfunc7: Passed. + constfunc9: Passed. + constfunc10: Passed. + constfunc11: Passed. + constfunc12: Passed. + constfunc13: Passed. + constfunc14: Passed. + constfunc15: Passed. + constmult: Passed. + consttern: Passed. + contrib8.1: Passed. + contrib8.2: Passed. + contrib8.3: Passed - CE. + contrib8.4: Passed. + contrib8.5: Passed. + countdrivers1: Passed. + countdrivers2: Passed. + countdrivers3: Passed. + countdrivers4: Passed. + countdrivers5: Passed. + cprop: Passed. + credence20041209: Passed. + dangling_port: Passed. + dcomp1: Passed. + deassign3.4A: Passed. + decl_assign1: Passed. + def_nettype: Passed. + def_nettype_none: Passed - CE. + define1: Passed. + defparam: Passed. + defparam2: Passed. + defparam3: Passed. + defparam3.5: Passed. + defparam4: Passed. + delay: Passed. + delay2: Passed. + delay3: Passed. + delay4: Passed. + delay5: Passed. + delay_assign_nb: Passed. + delay_assign_nb2: Passed. + delay_var: Passed. + delayed_comp_reduct: Passed. + dff1: Passed. + disable3.6A: Passed. + disable3.6B: Passed. + disable_cleanup: Passed. + disable_fork: Passed. + disblock: Passed. + disblock2: Passed. + disp_dec: Passed. + disp_dec2: Passed. + disp_leading_z: Passed. + disp_parm: Passed. + disp_part: Passed. + div16: Passed. + dotinid: Passed. + drive_strength: Passed. + drive_strength1: Passed. + drive_strength2: Passed. + drive_strength3: Passed. + dummy7: Passed. + dump_memword: Passed. + dumpvars: Passed. + eeq: Passed. + else1: Passed. + else2: Passed. + else3: Passed. + elsif_test: Passed. + eq: Passed. + escape1: Passed. + escape2a: Passed - CO. + escape2b: Passed - CO. + escape2c: Passed - CO. + escape3: Passed. + escape4: Passed. + escape4b: Passed. + event2: Passed. + event3: Passed. + event3.15: Passed. + event_array: Passed - CE. + event_list: Passed. + event_list2: Passed. + event_list3: Passed. + extend: Passed. + fdisplay1: Passed. + fdisplay2: Passed. + fdisplay_fail_fd: Passed. + fdisplay_fail_mcd: Passed. + fifo: Passed. + fopen1: Passed. + fopen2: Passed. + for3.16A: Passed. + force1: Passed. + force2: Passed. + force3.17A: Passed. + force3.17B: Passed. + force3.17C: Passed. + force_lval_part: Passed. + force_release_reg_pv: Passed. + force_release_wire8_pv: Passed. + force_release_wire_pv: Passed. + fork1: Passed. + fork3.19A: Passed. + fork3.19B: Passed. + format: Passed. + fr47: Passed. + fread: Passed. + fscanf_u: Passed. + fscanf_u_warn: Passed. + fscanf_z: Passed. + fscanf_z_warn: Passed. + function1: Passed. + function2: Passed. + function3: Passed. + function3.11B: Passed. + function3.11C: Passed. + function3.11D: Passed. + function3.11F: Passed. + function4: Passed - CE. + function5: Passed - CO. + function6: Passed. + function7: Passed. + function8: Passed. + function9: Passed. + function_exp: Passed. + ga_and: Passed. + ga_mod: Passed. + ga_mod1: Passed. + ga_mod2: Passed. + ga_nand: Passed. + ga_nor: Passed. + ga_or: Passed. + ga_xnor: Passed. + ga_xor: Passed. + galan: Passed. + gate_connect1: Passed. + gate_connect2: Passed - CE. + gen_case_opt1: Passed. + gen_case_opt2: Passed. + gen_case_opt3: Passed. + gencrc: Passed. + generate_case: Passed. + generate_case2: Passed. + generate_case3: Passed. + generate_multi_loop: Passed. + genloop: Passed. + genvar_scopes: Passed. + hello1: Passed. + hier_ref_error: Passed - CE. + hierspace: Passed. + idiv1: Passed. + idiv2: Passed. + idiv3: Passed. + ifdef1: Passed. + ifdef2: Passed. + ifdef3: Passed. + ifdef4: Passed. + include1: Passed. + include2: Passed. + include3: Passed. + indef_width_concat: Passed - CE. + initmod: Passed. + initmod2: Passed. + inout: Passed. + inout2: Passed. + inout3: Passed. + inout4: Passed. + int_not_signext: Passed. + integer1lt: Passed. + integer2le: Passed. + integer3gt: Passed. + integer4ge: Passed. + integer5: Passed. + itor_rtoi: Passed. + land2: Passed. + land3: Passed. + land4: Passed. + landor1: Passed. + ldelay1: Passed. + ldelay2: Passed. + ldelay3: Passed. + ldelay4: Passed. + ldelay5: Passed. + lh_catadd: Passed. + lh_memcat: Passed. + lh_memcat2: Passed. + lh_memcat3: Passed. + lh_varindx: Passed. + lh_varindx2: Passed. + lh_varindx4: Passed. + lh_varindx5: Passed. + long_div: Passed. + macro2: Passed. + macro_redefinition: Passed. + macro_replacement: Passed. + macsub: Passed. + mangle: Passed. + mangle_1: Passed. + many_drivers: Passed. + mcl2: Passed. + mem1: Passed. + mem2port: Passed. + memassign: Passed. + memidx: Passed. + memidxrng: Passed. + meminit: Passed. + meminit2: Passed. + memport_bs: Passed. + memref: Passed. + mhead_task: Passed. + mixed_type_div_mod: Passed. + mixed_width_case: Passed. + modparam: Passed. + module3.12A: Passed. + module3.12B: Passed. + modulus: Passed. + modulus2: Passed. + monitor: Passed. + monitor2: Passed. + monitor3: Passed. + mult1: Passed. + mult16: Passed. + mult2: Passed. + multi_bit_strength: Passed. + multi_driver_delay: Passed. + multiply_large: Passed. + muxtest: Passed. + named_event_no_edges: Passed - CE. + nb_assign: Passed. + nb_delay: Passed. + nblkorder: Passed. + negative_genvar: Passed. + negvalue: Passed. + neq1: Passed. + nested_func: Passed. + nested_impl_event1: Passed. + nested_impl_event2: Passed. + no_if_statement: Passed - CE. + no_timescale_in_module: Passed - CE. + npmos: Passed. + npmos2: Passed. + onehot: Passed. + p_monta: Passed. + par_mismatch: Passed - CE. + param-extend: Passed. + param_add: Passed. + param_and: Passed. + param_and2: Passed. + param_band: Passed. + param_binv: Passed. + param_bor: Passed. + param_concat: Passed. + param_eq3: Passed. + param_expr: Passed. + param_mod: Passed. + param_select: Passed. + param_select2: Passed. + param_select3: Passed. + param_string: Passed. + param_tern: Passed. + param_tern2: Passed. + param_test1: Passed. + param_test2: Passed. + param_test4: Passed. + param_times: Passed. + patch1268: Passed. + pca1: Passed. + pic: Passed. + port-test2: Passed. + port-test3: Passed - CE. + port-test4a: Passed - CE. + port-test4b: Passed - CE. + port-test5: Passed. + port-test6: Passed. + port-test7: Passed. + posedge: Passed. + pow-ca: Passed. + pow-const: Passed. + pow-proc: Passed. + pow_ca_signed: Passed. + pow_ca_unsigned: Passed. + pow_reg_signed: Passed. + pow_reg_unsigned: Passed. + pow_signed: Passed. + pow_unsigned: Passed. + pr136: Passed. + pr142: Passed. + pr183: Passed - CO. + pr224: Passed. + pr224a: Passed. + pr243: Passed. + pr245: Passed. + pr245_std: Passed. + pr273: Passed. + pr298: Passed. + pr304: Passed. + pr307: Passed. + pr307a: Passed. + pr312: Passed. + pr338: Passed - CO. + pr355: Passed. + pr377: Passed. + pr434: Passed. + pr445: Passed. + pr478: Passed. + pr487: Passed. + pr492: Passed. + pr508: Passed. + pr509: Passed. + pr509b: Passed. + pr511: Passed. + pr513: Passed. + pr522: Passed. + pr524: Passed. + pr527: Passed. + pr528: Passed. + pr528b: Passed. + pr529: Passed. + pr530a: Passed. + pr530b: Passed. + pr530c: Passed. + pr531a: Passed. + pr531b: Passed. + pr532: Passed. + pr532b: Passed. + pr533: Passed. + pr538: Passed. + pr540: Passed. + pr540b: Passed. + pr540c: Passed. + pr541: Passed. + pr542: Passed. + pr544: Passed. + pr547: Passed. + pr556: Passed. + pr564: Passed. + pr569: Passed. + pr572: Passed. + pr572b: Passed. + pr578: Passed. + pr584: Passed. + pr585: Passed. + pr587: Passed. + pr590: Passed. + pr594: Passed. + pr596: Passed. + pr602: Passed. + pr617: Passed. + pr632: Passed. + pr673: Passed. + pr675: Passed. + pr678: Passed. + pr690: Passed. + pr693: Passed. + pr699: Passed. + pr699b: Passed. + pr704: Passed. + pr707: Passed. + pr708: Passed. + pr710: Passed. + pr718: Passed. + pr722: Passed. + pr729: Passed. + pr734: Passed. + pr735: Passed. + pr748: Passed. + pr751: Passed. + pr757: Passed. + pr772: Passed. + pr810: Passed. + pr812: Passed. + pr820: Passed. + pr823: Passed. + pr841: Passed. + pr842: Passed. + pr848: Passed. + pr856: Passed. + pr859: Passed. + pr860: Passed. + pr872: Passed. + pr902: Passed. + pr905: Passed. + pr910: Passed. + pr913: Passed. + pr923: Passed. + pr938: Passed. + pr938b: Passed. + pr938b_std: Passed. + pr941: Passed. + pr973: Passed. + pr978: Passed. + pr985: Passed. + pr987: Passed. + pr990: Passed. + pr991: Passed. + pr993: Passed. + pr995: Passed. + pr1002: Passed. + pr1002a: Passed. + pr1007: Passed. + pr1008: Passed. + pr1022: Passed. + pr1024: Passed. + pr1026: Passed. + pr1029: Passed. + pr1032: Passed. + pr1033: Passed. + pr1065: Passed. + pr1072: Passed. + pr1077: Passed. + pr1087: Passed. + pr1101: Passed. + pr1115: Passed. + pr1353345: Passed. + pr1353345b: Passed. + pr1367855: Passed. + pr1380261: Passed. + pr1403406: Passed. + pr1403406a: Passed. + pr1403406b: Passed. + pr1421777: Passed. + pr1444055: Passed. + pr1449749a: Passed. + pr1455873: Passed. + pr1465769: Passed. + pr1467825: Passed - CO. + pr1474283: Passed. + pr1474316: Passed. + pr1474318: Passed. + pr1476440: Passed. + pr1477190: Passed. + pr1478121: Passed. + pr1478988: Passed. + pr1489568: Passed. + pr1489570: Passed. + pr1491355: Passed. + pr1492075: Passed. + pr1508882: Passed. + pr1510724: Passed. + pr1515168: Passed. + pr1520314: Passed - CO. + pr1522570: Passed. + pr1530426: Passed. + pr1561597: Passed. + pr1565544: Passed. + pr1565699b: Passed. + pr1570451: Passed. + pr1570451b: Passed. + pr1570635: Passed. + pr1570635b: Passed. + pr1574175: Passed. + pr1581580: Passed. + pr1587634: Passed - CO. + pr1587669: Passed. + pr1589497: Passed. + pr1598445: Passed. + pr1601896: Passed. + pr1601898: Passed. + pr1603313: Passed. + pr1603918: Passed. + pr1612693: Passed. + pr1623097: Passed. + pr1625912: Passed. + pr1628288: Passed. + pr1628300: Passed. + pr1629683: Passed. + pr1632861: Passed. + pr1634526: Passed. + pr1636409: Passed. + pr1637208: Passed. + pr1638985: Passed. + pr1639060: Passed. + pr1639064: Passed. + pr1639064b: Passed. + pr1639968: Passed. + pr1639971: Passed. + pr1645277: Passed. + pr1645518: Passed. + pr1648365: Passed. + pr1650842: Passed. + pr1657307: Passed. + pr1661640: Passed. + pr1662508: Passed. + pr1664684: Passed. + pr1675789: Passed. + pr1675789b: Passed. + pr1676071: Passed. + pr1676836: Passed. + pr1682887: Passed. + pr1687193: Passed. + pr1688717: Passed. + pr1690058: Passed. + pr1691599b: Passed. + pr1691709: Passed. + pr1693890: Passed. + pr1693921: Passed. + pr1694413: Passed. + pr1694427: Passed. + pr1695257: Passed - CO. + pr1695309: Passed. + pr1695322: Passed. + pr1695334: Passed. + pr1696137: Passed. + pr1697250: Passed. + pr1697732: Passed. + pr1698499: Passed. + pr1698658: Passed. + pr1698659: Passed. + pr1698820: Passed. + pr1699444: Passed. + pr1699519: Passed. + pr1701855: Passed. + pr1701855b: Passed. + pr1701889: Passed. + pr1701921: Passed. + pr1702593: Passed. + pr1703120: Passed. + pr1703346: Passed. + pr1703959: Passed. + pr1704013: Passed - CE. + pr1704726a: Passed - CE. + pr1704726b: Passed. + pr1704726c: Passed - CE. + pr1704726d: Passed - CE. + pr1705027: Passed - CO. + pr1716276: Passed. + pr1717361: Passed. + pr1719055: Passed. + pr1723367: Passed. + pr1735724: Passed - CE. + pr1735822: Passed. + pr1735836: Passed. + pr1740476b: Passed. + pr1742910: Passed. + pr1745005: Passed. + pr1746401: Passed. + pr1746848: Passed. + pr1752353: Passed. + pr1752823a: Passed. + pr1752823b: Passed. + pr1755593: Passed. + pr1755629: Passed. + pr1758122: Passed. + pr1758135: Passed. + pr1763333: Passed - CE. + pr1770199: Passed. + pr1776485: Passed. + pr1777103: Passed. + pr1780480: Passed. + pr1784984: Passed. + pr1787394a: Passed. + pr1787394b: Passed. + pr1787423: Passed. + pr1787423b: Passed. + pr1787423c: Passed. + pr1792108: Passed. + pr1792152: Passed. + pr1792734: Passed. + pr1793157: Passed. + pr1794362: Passed. + pr1795005a: Passed. + pr1795005b: Passed. + pr1799904: Passed. + pr1804877: Passed. + pr1805837: Passed. + pr1812297: Passed. + pr1819452: Passed. + pr1820472: Passed. + pr1822658: Passed. + pr1823732: Passed. + pr1828642: Passed. + pr1830834: Passed. + pr1831724: Passed. + pr1832097a: Passed. + pr1832097b: Passed. + pr1833024: Passed - CE. + pr1833754: Passed - CE. + pr1841300: Passed. + pr1845683: Passed. + pr1851310: Passed. + pr1855504: Passed. + pr1861212a: Passed. + pr1862744a: Passed. + pr1862744b: Passed - CE. + pr1866215: Passed. + pr1866215b: Passed. + pr1867161a: Passed. + pr1867161b: Passed. + pr1867332: Passed - CO. + pr1868792: Passed. + pr1868991a: Passed. + pr1868991b: Passed - CO. + pr1869769: Passed. + pr1869772: Passed. + pr1869781: Passed. + pr1873146: Passed. + pr1875866: Passed. + pr1875866b: Passed. + pr1876798: Passed. + pr1877740: Passed. + pr1877743: Passed. + pr1878909: Passed. + pr1879226: Passed. + pr1883052: Passed. + pr1883052b: Passed. + pr1885847: Passed. + pr1887168: Passed. + pr1892959: Passed. + pr1892959b: Passed. + pr1898983: Passed. + pr1901125: Passed. + pr1903157: Passed - CO. + pr1903324: Passed. + pr1903343: Passed. + pr1903520: Passed. + pr1907192: Passed. + pr1912843: Passed. + pr1913918a: Passed. + pr1913918b: Passed. + pr1913918c: Passed. + pr1913937: Passed. + pr1916261: Passed. + pr1921332: Passed - CO. + pr1924845: Passed. + pr1925356: Passed. + pr1925363a: Passed - CE. + pr1925363b: Passed - CE. + pr1932444: Passed. + pr1934744: Passed. + pr1936363: Passed. + pr1938138: Passed - CE. + pr1939165: Passed. + pr1946411: Passed. + pr1948110: Passed. + pr1948342: Passed. + pr1949025: Passed. + pr1950282: Passed. + pr1956211: Passed. + pr1958801: Passed. + pr1960545: Passed. + pr1960548: Passed. + pr1960558: Passed. + pr1960575: Passed. + pr1960596: Passed. + pr1960619: Passed. + pr1960625: Passed. + pr1960633: Passed. + pr1963240: Passed. + pr1963960: Passed. + pr1963962: Passed. + pr1971662a: Passed - CE. + pr1971662b: Passed - CE. + pr1978358: Passed. + pr1978358b: Passed. + pr1978358c: Passed. + pr1978358d: Passed. + pr1983762: Passed. + pr1985582: Passed. + pr1988302: Passed. + pr1988302b: Passed - CE. + pr1988310: Passed. + pr1990029: Passed. + pr1990164: Passed. + pr1990269: Passed. + pr1992244: Passed. + pr1992729: Passed. + pr1993479: Passed. + pr2001162: Passed. + pr2011429: Passed. + pr2013758: Passed. + pr2014673: Passed. + pr2015466: Passed. + pr2018235a: Passed. + pr2018235b: Passed. + pr2018305: Passed. + pr2019553: Passed. + pr2029336: Passed. + pr2030767: Passed. + pr2036953: Passed. + pr2038048: Passed. + pr2039632: Passed - CE. + pr2039694: Passed. + pr2043324: Passed. + pr2043585: Passed. + pr2051694: Passed - CE. + pr2051975: Passed - CE. + pr2053944: Passed. + pr2076363: Passed. + pr2076391: Passed. + pr2076425: Passed. + pr2085984: Passed. + pr2091455: Passed. + pr2109179: Passed. + pr2117473: Passed. + pr2117488: Passed. + pr2119622: Passed. + pr2121536: Passed. + pr2121536b: Passed. + pr2123190: Passed. + pr2132552: Passed. + pr2136787: Passed. + pr2138682: Passed. + pr2138979: Passed. + pr2138979b: Passed. + pr2138979c: Passed. + pr2138979d: Passed. + pr2139593: Passed. + pr2146620: Passed. + pr2146620b: Passed. + pr2146620c: Passed. + pr2146824: Passed. + pr2148401: Passed. + pr2152011: Passed. + pr2159630: Passed. + pr2166188: Passed. + pr2166311: Passed. + pr2169870: Passed. + pr2172606: Passed. + pr2172606b: Passed. + pr2181249: Passed. + pr2190323: Passed. + pr2201909: Passed. + pr2201909b: Passed. + pr2202706: Passed. + pr2202706b: Passed. + pr2202706c: Passed. + pr2202846a: Passed. + pr2202846b: Passed. + pr2202846c: Passed. + pr2208681: Passed. + pr2215342: Passed. + pr2219441: Passed. + pr2219441b: Passed. + pr2224845: Passed. + pr2224949: Passed. + pr2233180: Passed. + pr2233180b: Passed. + pr2233180c: Passed. + pr2233192: Passed. + pr2233192b: Passed. + pr2233192c: Passed. + pr2248925: Passed. + pr2251119: Passed. + pr2257003: Passed. + pr2257003b: Passed. + pr2270035: Passed. + pr2276163: Passed. + pr2281479: Passed. + pr2305307: Passed. + pr2305307b: Passed. + pr2305307c: Passed. + pr2306259: Passed. + pr2350934: Passed. + pr2350934b: Passed. + pr2350988: Passed. + pr2352834: Passed. + pr2355304: Passed. + pr2355304b: Passed. + pr2358264: Passed. + pr2358848: Passed. + pr2395378a: Passed - CE. + pr2395378b: Passed - CE. + pr2395378c: Passed - CE. + pr2395835: Passed. + pr2425055a: Passed. + pr2425055b: Passed. + pr2425055c: Passed. + pr2428890: Passed. + pr2428890b: Passed. + pr2434688: Passed. + pr2434688b: Passed. + pr2450244: Passed. + pr2453002: Passed. + pr2459681: Passed. + pr2470181a: Passed. + pr2470181b: Passed. + pr2503208: Passed. + pr2528915: Passed - CE. + pr2533175: Passed. + pr2579479: Passed. + pr2580730: Passed. + pr2593733: Passed. + pr2597278: Passed. + pr2597278b: Passed - CE. + pr2605006: Passed. + pr2673846: Passed. + pr2688910: Passed. + pr2709097: Passed. + pr2715547: Passed. + pr2715558: Passed. + pr2715558b: Passed. + pr2721213: Passed. + pr2722330a: Passed. + pr2722330b: Passed. + pr2722339a: Passed. + pr2722339b: Passed. + pr2723712: Passed. + pr2725700a: Passed. + pr2725700b: Passed. + pr2725700c: Passed. + pr2728032: Passed. + pr2728547: Passed. + pr2728812a: Passed. + pr2728812b: Passed - CE. + pr2728812c: Passed - CE. + pr2745281: Passed. + pr2781595: Passed. + pr2785294: Passed. + pr2788686: Passed. + pr2790236: Passed. + pr2792883: Passed - CE. + pr2792897: Passed. + pr2794144: Passed - CE. + pr2800985a: Passed. + pr2801134: Passed. + pr2801662: Passed. + pr2809288: Passed - CE. + pr2815398a: Passed. + pr2815398a_std: Passed. + pr2815398b: Passed. + pr2818823: Passed. + pr2823414: Passed - CE. + pr2823711: Passed. + pr2824189: Passed. + pr2829776: Passed. + pr2829776b: Passed. + pr2832234: Passed. + pr2834340: Passed. + pr2834340b: Passed. + pr2835632a: Passed. + pr2835632b: Passed. + pr2837451: Passed. + pr2842185: Passed. + pr2842621: Passed. + pr2842621_std: Passed. + pr2848986: Passed - CE. + pr2849783: Passed. + pr2865563: Passed. + pr2877564: Passed - CE. + pr2883958: Passed. + pr2885048: Passed. + pr2890322: Passed. + pr2901556: Passed. + pr2909386a: Passed. + pr2909386b: Passed. + pr2909414: Passed. + pr2909555: Passed. + pr2913404: Passed. + pr2913416: Passed. + pr2913438a: Passed. + pr2913438b: Passed. + pr2913927: Passed. + pr2918095: Passed. + pr2922063: Passed. + pr2922063a: Passed. + pr2922063b: Passed. + pr2924354: Passed. + pr2929913: Passed. + pr2930506: Passed. + pr2937417: Passed. + pr2937417b: Passed. + pr2937417c: Passed. + pr2941939: Passed. + pr2943394: Passed. + pr2951657: Passed. + pr2969724: Passed. + pr2971207: Passed. + pr2972866: Passed. + pr2973532: Passed. + pr2974051: Passed. + pr2974216: Passed. + pr2974216b: Passed. + pr2974294: Passed. + pr2985542: Passed. + pr2986497: Passed - CO. + pr2986528: Passed. + pr2991457: Passed. + pr2991457b: Passed. + pr2994193: Passed. + pr2998515: Passed. + pr3011327: Passed. + pr3012758: Passed. + pr3015421: Passed - CE. + pr3022502: Passed. + pr3024131: Passed. + pr3039548: Passed. + pr3044843: Passed. + pr3054101a: Passed. + pr3054101b: Passed. + pr3054101c: Passed. + pr3054101d: Passed. + pr3054101e: Passed. + pr3054101f: Passed. + pr3054101g: Passed. + pr3054101h: Passed. + pr3061015a: Passed - CE. + pr3061015b: Passed - CE. + pr3061015c: Passed - CE. + pr3064375: Passed. + pr3064511: Passed. + pr3077640: Passed. + pr3078759: Passed - CO. + pr3098439: Passed. + pr3098439a: Passed. + pr3098439b: Passed. + pr3103880: Passed. + pr3104254: Passed. + pr3112073a: Passed - CE. + pr3149494: Passed. + pr3190941: Passed - CE. + pr3190948: Passed. + pr3194155: Passed. + pr3197861: Passed. + pr3197917: Passed. + pr3270320: Passed - CE. + pr3284821: Passed. + pr3292735: Passed. + pr3296466a: Passed. + pr3296466b: Passed. + pr3296466c: Passed. + pr3296466d: Passed. + pr3306516: Passed. + pr3309391: Passed. + pr3368642: Passed. + pr3409749: Passed. + pr3437290a: Passed. + pr3437290b: Passed. + pr3437290c: Passed. + pr3441576: Passed. + pr3445452: Passed. + pr3452808: Passed. + pr3465541: Passed. + pr3477107: Passed. + pr3499807: Passed. + pr3522653: Passed. + pr3527022: Passed. + pr3527694: Passed. + pr3534422: Passed. + pr3539372: Passed. + pr3549328: Passed - CE. + pr3557493: Passed. + pr3561350: Passed. + pr3563412: Passed. + pr3571573: Passed. + pr3582052: Passed. + pr3587570: Passed. + pr3592746: Passed. + prng: Passed. + ptest001: Passed. + ptest002: Passed. + ptest003: Passed. + ptest004: Passed. + ptest005: Passed. + ptest006: Passed. + ptest007: Passed. + ptest008: Passed. + ptest009: Passed. + ptest010: Passed. + ptest011: Passed. + pullupdown: Passed. + pullupdown2: Passed. + pullupdown3: Passed. + pv_undef_sig_sel: Passed. + qmark: Passed. + qmark1: Passed. + qmark3: Passed. + qmark5: Passed. + qmark6: Passed. + queue: Passed. + queue_stat: Passed. + ram16x1: Passed. + readmem-error: Passed. + readmemb1: Passed. + readmemb2: Passed. + readmemb3: Passed. + readmemh1: Passed. + readmemh1a: Passed. + readmemh2: Passed. + readmemh3: Passed. + readmemh4: Passed. + readmemh5: Passed - CE. + real: Passed. + real2: Passed. + real3: Passed. + real5: Passed. + real6: Passed. + real7: Passed. + real9: Passed. + real10: Passed. + real11: Passed. + real_assign_deassign: Passed. + real_concat_invalid2: Passed - CE. + real_delay: Passed. + real_events: Passed. + real_force_rel: Passed. + real_invalid_ops: Passed - CE. + real_logical: Passed. + real_reg_force_rel: Passed. + recursive_func: Passed. + recursive_task: Passed. + redef_net_error: Passed - CE. + redef_reg_error: Passed - CE. + repeat2: Passed. + repeat_expr_probe: Passed. + repl_zero_wid_fail: Passed - CE. + repl_zero_wid_pass: Passed. + resetall: Passed. + resetall2: Passed. + resolv1: Passed. + rise_fall_decay1: Passed. + rise_fall_decay2: Passed. + rise_fall_delay1: Passed. + rise_fall_delay2: Passed. + rise_fall_delay3: Passed. + rl_pow: Passed. + rnpmos: Passed. + rnpmos2: Passed. + rop: Passed. + rptconcat: Passed. + rtran: Passed. + rtranif0: Passed. + rtranif1: Passed. + scanf: Passed. + scanf2: Passed. + scanf3: Passed. + scanf4: Passed. + sched1: Passed. + sched2: Passed. + schedule: Passed. + scope1: Passed. + scope2: Passed. + scope2b: Passed - CE. + scope4: Passed. + scope5: Passed. + scoped_events: Passed. + sdf1: Passed. + sdf2: Passed. + sdf3: Passed. + sdf4: Passed. + sdf5: Passed. + sdf6: Passed. + sdf7: Passed. + sdf8: Passed. + sdf_del_max: Passed. + sdf_del_min: Passed. + sdf_del_typ: Passed. + sdf_esc_id: Passed. + sdw_always1: Passed. + sdw_always2: Passed. + sdw_always3: Passed. + sdw_array: Passed. + sdw_assign: Passed. + sdw_dsbl: Passed. + sdw_force: Passed. + sdw_function1: Passed. + sdw_function2: Passed. + sdw_function3: Passed. + sdw_function4: Passed. + sdw_function5: Passed. + sdw_instmod1: Passed. + sdw_instmod2: Passed. + sdw_int: Passed. + sdw_lvalconcat: Passed. + sdw_param1: Passed. + sdw_param2: Passed. + sdw_release: Passed. + sdw_stmt002: Passed. + sdw_task1: Passed. + sdw_task2: Passed. + sel_rval_bit_ob: Passed. + sel_rval_part_ob: Passed. + select: Passed. + select2: Passed. + select3: Passed. + select4: Passed. + select5: Passed. + select6: Passed. + select7: Passed. + select8: Passed. + select_padding: Passed. + shellho1: Passed. + shift1: Passed. + shift2: Passed. + shift3: Passed. + shift4: Passed. + shift5: Passed. + shift_pad: Passed. + signed1: Passed. + signed2: Passed. + signed3: Passed. + signed4: Passed. + signed5: Passed. + signed6: Passed. + signed7: Passed. + signed8: Passed. + signed9: Passed. + signed10: Passed. + signed11: Passed. + signed12: Passed. + signed13: Passed. + signed_a: Passed. + signed_equality: Passed. + signed_net_display: Passed. + signed_part: Passed. + signed_pv: Passed. + sp2: Passed. + specify1: Passed - CO. + specify2: Passed. + specify3: Passed. + specify4: Passed. + specify5: Passed. + specify_01: Passed. + sqrt32: Passed. + sscanf_u: Passed. + sscanf_z: Passed. + stask_parm1: Passed. + stask_parm2: Passed. + stask_sens_null_arg: Passed. + string1: Passed. + string2: Passed. + string3: Passed. + string4: Passed. + string5: Passed. + string7: Passed. + string8: Passed. + string9: Passed. + string10: Passed. + string11: Passed. + supply1: Passed. + supply2: Passed. + switch_primitives: Passed. + sys_func_task_error: Passed - RE. + talu: Passed. + task-scope: Passed. + task3.14A: Passed. + task3.14B: Passed. + task3.14C: Passed. + task3.14D: Passed. + task3.14E: Passed. + task3.14F: Passed. + task_bypath: Passed. + task_inpad: Passed. + task_iotypes: Passed. + task_iotypes2: Passed. + task_mem: Passed. + task_noop: Passed. + task_noop2: Passed - CO. + task_omemw2: Passed. + task_omemw3: Passed - CO. + task_port_size: Passed. + task_scope: Passed. + tern1: Passed. + tern2: Passed - CO. + tern4: Passed. + tern5: Passed. + tern6: Passed. + tern7: Passed. + tern9: Passed. + tern10: Passed. + test_bufif0: Passed. + test_bufif1: Passed. + test_disphob: Passed. + test_dispwided: Passed. + test_extended: Passed. +test_mos_strength_reduction: Passed. + test_nmos: Passed. + test_notif0: Passed. + test_notif1: Passed. + test_pmos: Passed. + test_rnmos: Passed. + test_rpmos: Passed. + test_width: Passed. + time1: Passed. + time2: Passed. + time3: Passed. + time4: Passed. + time5: Passed. + time7: Passed. + time8: Passed. + timeform1: Passed. + timeform2: Passed. + timescale1: Passed. + timescale2: Passed. + timescale3: Passed - CE. + tran: Passed. + tranif0: Passed. + tranif1: Passed. + tran-keeper: Passed. + tri0: Passed. + tri0b: Passed. + tri1: Passed. + tri2: Passed. + tri3: Passed. + triand: Passed. + trior: Passed. + types1: Passed. + udp_bufg: Passed. + udp_bufg2: Passed. + udp_bx: Passed. + udp_delay_fail: Passed - CE. + udp_dff: Passed. + udp_dff_std: Passed. + udp_eval_arg: Passed. + udp_jkff: Passed. + udp_real_delay: Passed. + udp_sched: Passed. + udp_x: Passed. + unary_and: Passed. + unary_lnot1: Passed. + unary_lnot2: Passed. + unary_lnot3: Passed. + unary_minus: Passed. + unary_minus1: Passed. + unary_minus2: Passed. + unary_minus3: Passed. + unary_minus4: Passed. + unary_nand: Passed. + unary_nand2: Passed. + unary_nor: Passed. + unary_nor2: Passed. + unary_not: Passed. + unary_or: Passed. + unary_xnor1: Passed. + unary_xnor2: Passed. + unary_xor: Passed. + uncon_drive: Passed. + undef: Passed. + undef_lval_select: Passed. + undef_lval_select2: Passed. + undef_lval_select3a: Passed. + undef_lval_select3b: Passed - CE. + undef_lval_select3c: Passed - CE. + undef_lval_select4a: Passed. + undef_lval_select4b: Passed - CE. + undef_lval_select4c: Passed - CE. + undef_lval_select5: Passed. + undefined_shift: Passed. + urand_r: Passed. + urand_r2: Passed. + urand_r3: Passed. + uwire: Passed. + uwire2: Passed. + uwire_fail: Passed - CE. + vardly: Passed. + varlsfht: Passed. + varlsfht1: Passed. + varlsfht2: Passed. + varrshft: Passed. + varrshft1: Passed. + varrshft2: Passed. + vcd-dup: Passed. + vector: Passed. + verify_two_var_delays: Passed. + vvp_scalar_value: Passed. + wait1: Passed. + wait2: Passed. + wait3: Passed. + wildsense: Passed. + wildsense2: Passed. + wireadd1: Passed. + wireeq: Passed. + wirege: Passed. + wireland: Passed. + wirele: Passed. + wiremod1: Passed. + wiresl: Passed. + wiresl2: Passed. + wiresr: Passed. + wiresub1: Passed. + wirexor1: Passed. + writemem-error: Passed. + writememb1: Passed. + writememb2: Passed. + writememh1: Passed. + writememh2: Passed. + xnor_test: Passed. + z1: Passed. + z2: Passed. + zero_repl: Passed. + zero_repl_fail: Passed - CE. + cmpi: Passed. + br_gh99c: Passed. + cast_int_ams: Passed. + constfunc4_ams: Passed. + scaled_real: Passed. + test_vams_math: Passed. + value_range1: Passed. + value_range2: Passed. + value_range3: Passed - CE. + vams_abs1: Passed. + vams_abs2: Passed. + wreal: Passed. + always4A: Passed - CE. + always4B: Passed - CE. + always_comb: Passed. + always_comb_fail: Passed - CE. + always_comb_fail3: Passed - CE. + always_comb_fail4: Passed - CE. + always_comb_no_sens: Passed. + always_comb_rfunc: Passed. + always_comb_trig: Passed. + always_comb_warn: Passed. + always_ff: Passed. + always_ff_fail: Passed - CE. + always_ff_fail2: Passed - CE. + always_ff_fail3: Passed - CE. + always_ff_fail4: Passed - CE. + always_ff_no_sens: Passed - CE. + always_ff_warn: Passed. + always_ff_warn_sens: Passed. + always_latch: Passed. + always_latch_fail: Passed - CE. + always_latch_fail3: Passed - CE. + always_latch_fail4: Passed - CE. + always_latch_no_sens: Passed - CE. + always_latch_trig: Passed. + always_latch_warn: Passed. + array_size: Passed. + array_string: Passed. + array_unpacked_sysfunct: Passed. + assign_op_concat: Passed. + assign_op_type: Passed. + bitp1: Passed. + bits: Passed. + bits2: Passed. + br884: Passed. + br917a: Passed. + br917b: Passed. + br917c: Passed. + br917d: Passed. + br921: Passed. + br932a: Passed. + br932b: Passed. + br936: Passed. + br956: Passed. + br959: Passed. + br962: Passed. + br963: Passed. + br973: Passed. + br974a: Passed. + br974b: Passed. + br974c: Passed. + br975: Passed - CE. + br979: Passed. + br991b: Passed - CE. + br1003a: Passed. + br1003b: Passed. + br1003c: Passed. + br1003d: Passed. + br1004: Passed. + br1025: Passed. + br1027b: Passed. + br1027d: Passed. + br1027f: Passed. + br_gh4: Passed. + br_gh4a: Passed. + br_gh72a: Passed. + br_gh72b: Passed. + br_gh104a: Passed. + br_gh104b: Passed. + br_gh105a: Passed. + br_gh105b: Passed. + br_gh112a: Passed. + br_gh112b: Passed. + br_gh112c: Passed. + br_gh112d: Passed. + br_gh112e: Passed. + br_gh112f: Passed. + br_gh129: Passed. + br_gh130a: Passed - CE. + br_gh165: Passed. + br_gh164a: Passed. + br_gh164b: Passed. + br_gh164c: Passed. + br_gh164d: Passed. + br_gh164e: Passed. + br_gh167a: Passed. + br_gh167b: Passed. + br_gh177a: Passed. + br_gh177b: Passed. + br_gh194: Passed. + br_gh219: Passed. + br_gh220: Passed. + br_gh224: Passed. + br_gh226: Passed. + br_gh231: Passed. + br_gh243: Passed. + br_gh265: Passed - CE. + br_gh277b: Passed. + br_gh280: Passed. + br_gh281: Passed. + br_gh281b: Passed. + br_gh289a: Passed. + br_gh289b: Passed. + br_gh289c: Passed. + br_gh289d: Passed. + br_gh337: Passed. + br_gh361: Passed. + br_gh365: Passed. + br_gh366: Passed. + br_gh368: Passed. + br_gh374: Passed. + br_gh386a: Passed. + br_gh386b: Passed. + br_gh386c: Passed - CE. + br_gh388: Passed. + br_gh391: Passed. + br_gh411: Passed. + br_gh418: Passed. + br_gh433: Passed. + br_gh437: Passed. + br_gh443: Passed. + br_gh445: Passed. + br_gh461: Passed. + br_gh477: Passed. + br_gh498: Passed. + br_gh508a: Passed. + br_gh530: Passed - CO. + br_gh540: Passed. + br_gh553: Passed. + br_gh556: Passed. + br_gh568: Passed. + br_ml20171017: Passed. + br_ml20180227: Passed - CE. + br_ml20180309a: Passed. + br_ml20180309b: Passed. + br_ml20181012a: Passed - CE. + br_ml20181012b: Passed - CE. + br_ml20181012c: Passed - CE. + br_ml20181012d: Passed - CE. + br_ml20191221: Passed. + br_mw20200501: Passed. + case_priority: Passed. + case_unique: Passed. + cast_real: Passed. + cfunc_assign_op_mixed: Passed. + cfunc_assign_op_pv: Passed. + cfunc_assign_op_real: Passed. + cfunc_assign_op_vec: Passed. + clkgen_bit: Passed. + clkgen_logic: Passed. + clkgen_net: Passed. + clkgen_reg: Passed. + disable_fork_cmd: Passed. + display_bug: Passed. + enum_base_range: Passed. + enum_elem_ranges: Passed. + enum_next: Passed. + enum_ports: Passed. + enum_test1: Passed. + enum_test2: Passed. + enum_test3: Passed - CE. + enum_test4: Passed. + enum_test5: Passed - CE. + enum_test6: Passed - CE. + enum_test7: Passed - CE. + enum_test8: Passed. + enum_value_expr: Passed. + enum_values: Passed. + escaped_macro_name: Passed. + extra_semicolon: Passed. + fileline: Passed. + final: Passed. + final2: Passed. + first_last_num: Passed. + fork_join_any: Passed. + fork_join_dis: Passed. + fork_join_none: Passed. + fr49: Passed. + func_init_var1: Passed. + func_init_var2: Passed. + func_init_var3: Passed. + function10: Passed - CO. + function11: Passed - CE. + function12: Passed. + genvar_inc_dec: Passed. + ibit_test: Passed. + ibyte_test: Passed. + iint_test: Passed. + ilongint_test: Passed. + implicit_cast1: Passed. + implicit_cast2: Passed. + implicit_cast3: Passed. + implicit_cast4: Passed. + implicit_cast5: Passed. + implicit_cast6: Passed. + implicit_cast7: Passed. + implicit_cast8: Passed. + implicit_cast9: Passed. + implicit_cast10: Passed. + implicit_cast11: Passed. + implicit_cast12: Passed. + implicit_cast13: Passed. + implicit-port1: Passed. + implicit-port2: Passed - CE. + implicit-port3: Passed - CE. + implicit-port4: Passed. + implicit-port5: Passed. + implicit-port6: Passed - CE. + implicit-port7: Passed. + inc_dec_stmt: Passed. + int_param: Passed. + ishortint_test: Passed. + iuint1: Passed. + l_equiv: Passed. + l_equiv_ca: Passed. + l_equiv_const: Passed. + localparam_query: Passed. + localparam_type2: Passed. + logical_short_circuit: Passed. + logp2: Passed. + mod_inst_pkg: Passed. + named_begin: Passed. + named_begin_fail: Passed - CE. + named_fork: Passed. + named_fork_fail: Passed - CE. + packeda: Passed. + packeda2: Passed. + parameter_type2: Passed. + parpkg_test: Passed. + parpkg_test2: Passed. + parpkg_test3: Passed. + part_sel_port: Passed. + plus_5: Passed. + pr3366114: Passed. + pr3366217a: Passed - CE. + pr3366217b: Passed - CE. + pr3366217c: Passed - CE. + pr3366217d: Passed - CE. + pr3366217e: Passed. + pr3366217f: Passed. + pr3366217g: Passed - CE. + pr3366217h: Passed. + pr3366217i: Passed. + pr3390385: Passed. + pr3390385b: Passed. + pr3390385c: Passed. + pr3390385d: Passed. + pr3462145: Passed. + pr3515542: Passed - CE. + pr3534333: Passed. + pr3576165: Passed. + program2: Passed. + program3: Passed. + program3b: Passed - CE. + program4: Passed. + program5a: Passed - CE. + program5b: Passed - CE. + program_hello: Passed. + program_hello2: Passed - CE. + sbyte_test: Passed. + sf_countbits: Passed. + sf_countones: Passed. + sf_isunknown: Passed. + sf_onehot: Passed. + sf_onehot0: Passed. + sformatf: Passed. + simple_byte: Passed. + simple_int: Passed. + simple_longint: Passed. + simple_shortint: Passed. + sint_test: Passed. + size_cast: Passed. + size_cast2: Passed. + size_cast3: Passed. + size_cast4: Passed. + size_cast5: Passed. + slongint_test: Passed. + sshortint_test: Passed. + string_events: Passed. + string_index: Passed. + struct1: Passed. + struct2: Passed. + struct3: Passed. + struct3b: Passed. + struct4: Passed. + struct5: Passed. + struct6: Passed. + struct7: Passed. + struct8: Passed. + struct9: Passed. + struct_packed_array: Passed. + struct_packed_array2: Passed. + struct_packed_sysfunct: Passed. + struct_packed_write_read2: Passed. + sv-constants: Passed. + sv_array_assign_pattern2: Passed. + sv_cast_integer: Passed. + sv_cast_integer2: Passed. + sv_cast_string: Passed. + sv_class1: Passed. + sv_class2: Passed. + sv_class3: Passed. + sv_class4: Passed. + sv_class5: Passed. + sv_class6: Passed. + sv_class7: Passed. + sv_class8: Passed. + sv_class9: Passed. + sv_class10: Passed. + sv_class11: Passed. + sv_class12: Passed. + sv_class13: Passed. + sv_class14: Passed. + sv_class15: Passed. + sv_class16: Passed. + sv_class17: Passed. + sv_class18: Passed. + sv_class19: Passed. + sv_class20: Passed. + sv_class21: Passed. + sv_class22: Passed. + sv_class23: Passed. + sv_class24: Passed. + sv_darray1: Passed. + sv_darray2: Passed. + sv_darray3: Passed. + sv_darray4: Passed. + sv_darray5: Passed. + sv_darray5b: Passed. + sv_darray6: Passed. + sv_darray_args1: Passed. + sv_darray_args2: Passed. + sv_darray_args2b: Passed. + sv_darray_args3: Passed. + sv_darray_args4: Passed. + sv_darray_decl_assign: Passed. + sv_darray_function: Passed. + sv_darray_signed: Passed. + sv_darray_word_size: Passed. + sv_end_label: Passed. + sv_end_label_fail: Passed - CE. + sv_end_labels: Passed. + sv_end_labels_bad: Passed - CE. + sv_enum1: Passed. + sv_for_variable: Passed. + sv_foreach1: Passed. + sv_foreach2: Passed. + sv_foreach3: Passed. + sv_foreach4: Passed. + sv_foreach5: Passed. + sv_immediate_assert: Passed. + sv_immediate_assume: Passed. + sv_macro: Passed. + sv_macro2: Passed. + sv_macro3a: Passed. + sv_macro3b: Passed. + sv_new_array_error: Passed - CE. + sv_package: Passed. + sv_package2: Passed. + sv_package3: Passed. + sv_package4: Passed. + sv_package5: Passed. + sv_packed_port1: Passed. + sv_packed_port2: Passed. + sv_param_port_list: Passed. + sv_pkg_class: Passed. + sv_port_default1: Passed. + sv_port_default2: Passed. + sv_port_default3: Passed. + sv_port_default4: Passed. + sv_port_default5: Passed. + sv_port_default6: Passed. + sv_port_default7: Passed. + sv_port_default8: Passed. + sv_port_default9: Passed. + sv_port_default10: Passed. + sv_port_default11: Passed. + sv_port_default12: Passed. + sv_port_default13: Passed - CE. + sv_port_default14: Passed - CE. + sv_queue1: Passed. + sv_queue2: Passed. + sv_queue3: Passed. + sv_queue_real: Passed. + sv_queue_real_bounded: Passed. + sv_queue_real_fail: Passed - CE. + sv_queue_string: Passed. + sv_queue_string_bounded: Passed. + sv_queue_string_fail: Passed - CE. + sv_queue_vec: Passed. + sv_queue_vec_bounded: Passed. + sv_queue_vec_fail: Passed - CE. + sv_root_class: Passed. + sv_root_func: Passed. + sv_root_task: Passed. + sv_string1: Passed. + sv_string2: Passed. + sv_string3: Passed. + sv_string4: Passed. + sv_string5: Passed. + sv_timeunit_prec1: Passed. + sv_timeunit_prec2: Passed. + sv_timeunit_prec3a: Passed. + sv_timeunit_prec3b: Passed. + sv_timeunit_prec3c: Passed. + sv_timeunit_prec3d: Passed. + sv_timeunit_prec4a: Passed. + sv_timeunit_prec4b: Passed. + sv_timeunit_prec_fail1: Passed - CE. + sv_timeunit_prec_fail2: Passed - CE. + sv_typedef_scope: Passed. + sv_union1: Passed. + sv_union1b: Passed. + sv_union2: Passed. + sv_union2b: Passed. + sv_union3: Passed. + sv_union3b: Passed. + sv_union4b: Passed. + sv_unit1b: Passed. + sv_unit1c: Passed. + sv_unit2b: Passed. + sv_unit3b: Passed. + sv_unit4b: Passed. + sv_unpacked_port: Passed. + sv_unpacked_port2: Passed. + sv_unpacked_wire: Passed. + sv_unpacked_wire2: Passed. + sv_uwire1: Passed. + sv_uwire2: Passed. + sv_uwire3: Passed. + sv_uwire4: Passed. + sv_var_init1: Passed. + sv_var_init2: Passed. + sv_wildcard_import1: Passed. + sv_wildcard_import2: Passed. + sv_wildcard_import3: Passed. + sv_wildcard_import4: Passed - CE. + sv_wildcard_import5: Passed - CE. + sv_wildcard_import6: Passed. + sv_wildcard_import7: Passed. + sys_func_as_task: Passed. + task_init_assign: Passed. + task_init_var1: Passed. + task_init_var2: Passed. + task_init_var3: Passed. + task_scope2: Passed. + test_inc_dec: Passed. + test_tliteral: Passed. + two_state_display: Passed. + ubyte_test: Passed. + uint_test: Passed. + ulongint_test: Passed. + undef_lval_select_SV: Passed. + unp_array_typedef: Passed. + ushortint_test: Passed. + vvp_recv_vec4_pv: Passed. + wait_fork: Passed. + sf1289: Passed. + wild_cmp_const: Passed. + wild_cmp_net: Passed. + wild_cmp_var: Passed. + wild_cmp_err: Passed - CE. + wild_cmp_err2: Passed - CE. + gh161a: Passed. + gh161b: Passed. + pull371b: Passed. + br_gh451: Passed. + br942: Passed. + br943_944: Passed. + br985: Passed. + br986: Passed. + br987: Passed. + ivlh_event: Passed. + ivlh_rising_falling: Passed. + ivlh_textio: Passed. + test_dec2to4: Passed. + test_enumsystem: Passed. + test_forgen: Passed. + test_gxor: Passed. + test_mux2to1: Passed. + test_signal_init_assign: Passed. + test_system: Passed. + test_timebase: Passed. + test_varray1: Passed. + test_when_else: Passed. + test_work14: Passed. + vhdl_and104_stdlogic: Passed. + vhdl_and23_bit: Passed. + vhdl_and_gate: Passed. + vhdl_andg_bit: Passed. + vhdl_andg_stdlogic: Passed. + vhdl_array_of_array: Passed. + vhdl_case_multi: Passed. + vhdl_boolean: Passed. + vhdl_concat: Passed. + vhdl_concat_func: Passed. + vhdl_concurrent_assert: Passed. + vhdl_const_package: Passed. + vhdl_const_record: Passed. + vhdl_const_array: Passed. + vhdl_delay_assign: Passed. + vhdl_elab_range: Passed. + vhdl_eval_cond: Passed. + vhdl_expr1: Passed. + vhdl_generic_eval: Passed. + vhdl_fa4_test1: Passed. + vhdl_fa4_test2: Passed. + vhdl_fa4_test3: Passed. + vhdl_fa4_test4: Passed. + vhdl_file_open: Passed. + vhdl_generic_default: Passed. + vhdl_init: Passed. + vhdl_image_attr: Passed. + vhdl_inout: Passed. + vhdl_labeled_assign: Passed. + vhdl_lfcr: Passed. + vhdl_logic: Passed. + vhdl_loop: Passed. + vhdl_nand104_stdlogic: Passed. + vhdl_nand23_bit: Passed. + vhdl_nandg_bit: Passed. + vhdl_nandg_stdlogic: Passed. + vhdl_nor104_stdlogic: Passed. + vhdl_nor23_bit: Passed. + vhdl_norg_bit: Passed. + vhdl_norg_stdlogic: Passed. + vhdl_not104_stdlogic: Passed. + vhdl_not23_bit: Passed. + vhdl_notfunc_stdlogic: Passed. + vhdl_notg_bit: Passed. + vhdl_notg_stdlogic: Passed. + vhdl_now: Passed. + vhdl_or104_stdlogic: Passed. + vhdl_or23_bit: Passed. + vhdl_org_bit: Passed. + vhdl_org_stdlogic: Passed. + vhdl_pow_rem: Passed. + vhdl_prefix_array: Passed. + vhdl_procedure: Passed. + vhdl_process_scope: Passed. + vhdl_rand23_bit: Passed. + vhdl_range: Passed. + vhdl_range_func: Passed. + vhdl_real: Passed. + vhdl_record_elab: Passed. + vhdl_reduce: Passed. + vhdl_report: Passed. + vhdl_resize: Passed. + vhdl_rtoi: Passed. + vhdl_sa1_test1: Passed. + vhdl_sa1_test2: Passed. + vhdl_sa1_test3: Passed. + vhdl_sadd23_bit: Passed. + vhdl_sadd23_stdlogic: Passed. + vhdl_sdiv23_bit: Passed. + vhdl_sdiv23_stdlogic: Passed. + vhdl_selected: Passed. + vhdl_shift: Passed. + vhdl_signals: Passed. + vhdl_smul23_bit: Passed. + vhdl_smul23_stdlogic: Passed. + vhdl_ssub23_bit: Passed. + vhdl_ssub23_stdlogic: Passed. + vhdl_struct_array: Passed. + vhdl_subtypes: Passed. + vhdl_subprogram: Passed. + vhdl_string: Passed. + vhdl_string_lim: Passed. + vhdl_test1: Passed. + vhdl_test2: Passed. + vhdl_test3: Passed. + vhdl_test4: Passed. + vhdl_test5: Passed. + vhdl_test6: Passed. + vhdl_test7: Passed. + vhdl_test8: Passed. + vhdl_test9: Passed. + vhdl_textio_write: Passed. + vhdl_textio_read: Passed. + vhdl_time: Passed. + vhdl_to_integer: Passed. + vhdl_uadd23_bit: Passed. + vhdl_uadd23_stdlogic: Passed. + vhdl_udiv23_bit: Passed. + vhdl_udiv23_stdlogic: Passed. + vhdl_umul23_bit: Passed. + vhdl_umul23_stdlogic: Passed. + vhdl_unary_minus: Passed. + vhdl_unbounded: Passed. + vhdl_unbounded_func: Passed. + vhdl_usub23_bit: Passed. + vhdl_usub23_stdlogic: Passed. + vhdl_var_init: Passed. + vhdl_wait: Passed. + vhdl_while: Passed. + vhdl_xnor104_stdlogic: Passed. + vhdl_xnor23_bit: Passed. + vhdl_xnorg_bit: Passed. + vhdl_xnorg_stdlogic: Passed. + vhdl_xor23_bit: Passed. + vhdl_xorg_bit: Passed. + vhdl_xorg_stdlogic: Passed. + work7: Passed. + work7b: Passed. + basicexpr: Passed. + basicexpr2: Passed. + basicexpr3: Passed. + basicexpr4: Passed. + basiclatch: Passed. + basicreg: Passed. + basicstate: Passed. + basicstate2: Passed. + blocksynth1: Passed. + blocksynth2: Passed. + blocksynth3: Passed. + br993a: Passed. + br993b: Passed. + br994: Passed. + br995: Passed - CE. + br_gh99v: Passed. + br_gh99w: Passed. + br_gh99x: Passed. + br_gh115: Passed. + br_gh306a: Passed - CE. + br_gh306b: Passed - CE. + case3: Passed. + case4: Passed. + case5: Passed. + case5-syn-fail: Passed - CE. + case6: Passed. + case7: Passed. + case_wo_default: Passed. + casesynth1: Passed. + casesynth2: Passed. + casesynth3: Passed. + casesynth4: Passed. + casesynth5: Passed. + casesynth6: Passed. + casesynth7: Passed. + casesynth8: Passed - CE. + casesynth9: Passed. + condit1: Passed. + conditsynth1: Passed. + conditsynth2: Passed. + conditsynth3: Passed. + dffsynth2: Passed. + dffsynth3: Passed. + dffsynth4: Passed. + dffsynth5: Passed. + dffsynth6: Passed. + dffsynth7: Passed. + dffsynth8: Passed - CE. + dffsynth9: Passed. + dffsynth10: Passed. + dffsynth11: Passed. + ff_dual_enable: Passed. + for_loop_synth: Passed. + for_loop_synth2: Passed. + if_part_no_else: Passed. + if_part_no_else2: Passed. + inside_synth: Passed. + inside_synth2: Passed. + inside_synth3: Passed. + land5: Passed. + lcatsynth: Passed. + memsynth4: Passed. + memsynth8: Passed. + multireg: Passed. + not_a_latch1: Passed. + not_a_latch2: Passed. + partselsynth: Passed. + pr519: Passed. + pr685: Passed. + shiftl: Passed. + sqrt32synth: Passed. + ssetclr1: Passed. + ssetclr2: Passed. + ssetclr3: Passed. + synth_if_no_else: Passed. + ufuncsynth1: Passed. +============================================================================ +Test results: + Total=2555, Passed=2522, Failed=0, Not Implemented=32, Expected Fail=1 diff --git a/ivtest/regression_report-vlog95.txt b/ivtest/regression_report-vlog95.txt new file mode 100644 index 000000000..1e13fe41e --- /dev/null +++ b/ivtest/regression_report-vlog95.txt @@ -0,0 +1,2564 @@ +Running vlog95 compiler/VVP tests for Icarus Verilog version: 12. +---------------------------------------------------------------------------- + always_comb_rfunc: Passed - CE. + automatic_error11: Passed - CE. + automatic_error12: Passed - CE. + automatic_error13: Passed - CE. + automatic_events: Passed - CE. + automatic_events2: Passed - CE. + automatic_events3: Passed - CE. + automatic_task: Passed - CE. + automatic_task2: Passed - CE. + automatic_task3: Passed - CE. + br942: Passed - CE. + br_gh531: Passed - CE. + def_nettype: Passed - CE. + func_init_var1: Passed - CE. + func_init_var2: Passed - CE. + func_init_var3: Passed - CE. + nested_func: Passed - CE. + pr2169870: Passed - CE. + pr2172606b: Passed - CE. + pr2276163: Passed - CE. + pr2929913: Passed - CE. + real_events: Passed - CE. + recursive_func: Passed - CE. + recursive_task: Passed - CE. + task_init_var1: Passed - CE. + task_init_var2: Passed - CE. + task_init_var3: Passed - CE. + test_work14: Passed - CE. + vhdl_elab_range: Passed - CE. + vhdl_notfunc_stdlogic: Passed - CE. + vhdl_procedure: Passed - CE. + vhdl_range_func: Passed - CE. + vhdl_report: Passed - CE. + vhdl_subprogram: Passed - CE. + vhdl_unbounded_func: Passed - CE. + array_lval_select4a: Passed - CE. + array_lval_select4b: Passed - CE. + array_lval_select5: Passed - CE. + array_lval_select6: Passed - CE. + br_gh456: Passed - CE. + ca_64delay: Passed - CE. + ca_time_real: Passed - CE. + ca_var_delay: Passed - CE. + cast_real: Passed - CE. + cast_real_signed: Passed - CE. + cast_real_unsigned: Passed - CE. + sv_cast_integer: Passed. + sv_cast_integer2: Passed. + sv_cast_string: Passed - CE. + clog2: Passed - CE. + delayed_sfunc: Passed - CE. + implicit_cast4: Passed - CE. + implicit_cast5: Passed - CE. + implicit_cast6: Passed - CE. + implicit_cast12: Passed - CE. + implicit_cast13: Passed - CE. + pr1861212c: Passed - CE. + pr1864110a: Passed - CE. + pr1864110b: Passed - CE. + pr1864110c: Passed - CE. + pr1864115: Passed - CE. + pr1873372: Passed - CE. + pr1880003: Passed - CE. + pr1898293: Passed - CE. + pr2123158: Passed - CE. + pr2123190: Passed - CE. + pr2453002b: Passed - CE. + pr2456943: Passed - CE. + pr2806474: Passed - CE. + pr2976242: Passed - CE. + pr2976242b: Passed - CE. + real8: Passed - CE. + real_mod_in_ca: Passed - CE. + real_pulse_clean: Passed - CE. + real_pwr_in_ca: Passed - CE. + real_wire_array: Passed - CE. + real_wire_force_rel: Passed - CE. + tern8: Passed - CE. + v2005_math: Passed - CE. + vams_abs2: Passed - CE. + vhdl_real: Passed - CE. + vhdl_unbounded: Passed - CE. + wreal: Passed - CE. + pr1528093: Passed - CE. + br_gh9: Passed - CE. + br_gh244a: Passed - CE. + br_gh244b: Passed - CE. + ca_pow_signed: Passed - CE. + br_mw20171108: Passed - CE. + ca_pow_synth: Passed - CE. + ca_pow_unsigned: Passed - CE. + constfunc3: Passed - CE. + pow_ca_signed: Passed - CE. + pow_ca_unsigned: Passed - CE. + pow_reg_signed: Passed - CE. + pow_reg_unsigned: Passed - CE. + pow_signed: Passed - CE. + pow_unsigned: Passed - CE. + pow-ca: Passed - CE. + pow-proc: Passed - CE. + pr2352834: Passed - CE. + pr2823711: Passed - CE. + pr2909386b: Passed - CE. + rl_pow: Passed - CE. + vhdl_pow_rem: Passed - CE. + sf_countbits: Passed - RE. + sf_countbits_fail: Passed - RE. + sf_countones: Passed - RE. + sf_countones_fail: Passed - RE. + sf_isunknown: Passed - RE. + sf_isunknown_fail: Passed - RE. + sf_onehot: Passed - RE. + sf_onehot_fail: Passed - RE. + sf_onehot0: Passed - RE. + sf_onehot0_fail: Passed - RE. + array_lval_select1: Passed. + array_lval_select2: Passed. + array_lval_select3a: Passed - TE. + array_lval_select3b: Passed - CE. + array_lval_select3c: Passed. + array_select: Passed - CE. + array_select_a: Passed - CE. + array_unpacked_sysfunct: Passed - CE. + array_word_width2: Passed - CE. + br1008: Passed - CE. + br1019: Passed - CE. + br_gh556: Passed - CE. + br_ml20171017: Passed - CE. + genvar_scopes: Passed - CE. + meminit2: Passed - CE. + memsynth4: Passed - CE. + negative_genvar: Passed - CE. + pr1565544: Passed - CE. + pr1657307: Passed - CE. + pr1695322: Passed - CE. + pr1701855b: Passed - CE. + pr1703346: Passed - CE. + pr1740476b: Passed - CE. + pr1758122: Passed - CE. + pr1799904: Passed - CE. + pr1820472: Passed - CE. + pr1868792: Passed - CE. + pr1876798: Passed - CE. + pr1903324: Passed - CE. + pr2011429: Passed - CE. + pr2076391: Passed - CE. + pr2201909: Passed - CE. + pr2201909b: Passed - CE. + pr2166311: Passed - CE. + pr2715748: Passed - CE. + pr2815398b: Passed - CE. + pr3054101g: Passed - CE. + pr3054101h: Passed - CE. + pr3592746: Passed - CE. + real_array: Passed - CE. + real_array_nb: Passed - CE. + scan-invalid: Passed - CE. + sel_rval_bit_ob: Passed - CE. + sel_rval_part_ob: Passed - CE. + signed_net_display: Passed - CE. + sv_unpacked_port: Passed - CE. + sv_unpacked_port2: Passed - CE. + sv_unpacked_wire: Passed - CE. + sv_unpacked_wire2: Passed - CE. + concat4: Passed - expected fail. + br_gh443: Passed - CE. + final: Passed - CE. + final2: Passed - CE. + program_hello: Passed - CE. + program2: Passed - CE. + program2b: Passed - CE. + program3: Passed - CE. + program3a: Passed - CE. + program4: Passed - CE. + array_string: Passed - CE. + br932a: Passed - CE. + br932b: Passed - CE. + br_gh4: Passed - CE. + br_gh175: Passed - CE. + br_gh194: Passed - CE. + br_gh365: Passed - CE. + br_gh453: Passed - CE. + br_ml20180309a: Passed - CE. + br_ml20180309b: Passed - CE. + ivlh_textio: Passed - CE. + plus_arg_string: Passed - CE. + sformatf: Passed - CE. + string_events: Passed - CE. + string_index: Passed - CE. + sv_macro: Passed - CE. + sv_string1: Passed - CE. + sv_string2: Passed - CE. + sv_string3: Passed - CE. + sv_string4: Passed - CE. + sv_string5: Passed - CE. + vhdl_string_lim: Passed - CE. + vhdl_textio_write: Passed - CE. + vhdl_textio_read: Passed - CE. + always_comb_warn: Passed - CE. + always_ff_warn: Passed - CE. + always_latch_warn: Passed - CE. + br962: Passed - CE. + br963: Passed - CE. + br_gh164a: Passed - CE. + br_gh164b: Passed - CE. + br_gh164c: Passed - CE. + br_gh164d: Passed - CE. + br_gh164e: Passed - CE. + br_gh383a: Passed - CE. + br_gh383b: Passed - CE. + br_gh383c: Passed - CE. + br_gh383d: Passed - CE. + br_gh460: Passed - CE. + br_ml20191221: Passed - CE. + sv_array_assign_pattern2: Passed - CE. + sv_cast_darray: Passed - CE. + sv_darray1: Passed - CE. + sv_darray2: Passed - CE. + sv_darray3: Passed - CE. + sv_darray4: Passed - CE. + sv_darray5: Passed - CE. + sv_darray5b: Passed - CE. + sv_darray6: Passed - CE. + sv_darray_args1: Passed - CE. + sv_darray_args2: Passed - CE. + sv_darray_args2b: Passed - CE. + sv_darray_args3: Passed - CE. + sv_darray_args4: Passed - CE. + sv_darray_decl_assign: Passed - CE. + sv_darray_function: Passed - CE. + sv_darray_signed: Passed - CE. + sv_darray_word_size: Passed - CE. + sv_new_array_error: Passed - CE. + unp_array_typedef: Passed - CE. + br959: Passed - CE. + br1003a: Passed - CE. + br1004: Passed - CE. + br_gh104a: Passed - CE. + br_gh167a: Passed - CE. + br_gh167b: Passed - CE. + br_gh177a: Passed - CE. + br_gh177b: Passed - CE. + br_gh388: Passed - CE. + br_gh390b: Passed - CE. + br_gh391: Passed - CE. + br_gh437: Passed - CE. + br_gh445: Passed - CE. + br_gh461: Passed - CE. + sv_class1: Passed - CE. + sv_class2: Passed - CE. + sv_class3: Passed - CE. + sv_class4: Passed - CE. + sv_class5: Passed - CE. + sv_class6: Passed - CE. + sv_class7: Passed - CE. + sv_class8: Passed - CE. + sv_class9: Passed - CE. + sv_class10: Passed - CE. + sv_class11: Passed - CE. + sv_class12: Passed - CE. + sv_class13: Passed - CE. + sv_class14: Passed - CE. + sv_class15: Passed - CE. + sv_class16: Passed - CE. + sv_class17: Passed - CE. + sv_class18: Passed - CE. + sv_class19: Passed - CE. + sv_class20: Passed - CE. + sv_class21: Passed - CE. + sv_class22: Passed - CE. + sv_class23: Passed - CE. + sv_class24: Passed - CE. + sv_end_label: Passed - CE. + sv_foreach2: Passed - CE. + sv_foreach3: Passed - CE. + sv_foreach4: Passed - CE. + sv_pkg_class: Passed - CE. + sv_port_default1: Passed - CE. + sv_port_default2: Passed - CE. + sv_port_default3: Passed - CE. + sv_port_default4: Passed - CE. + sv_port_default5: Passed - CE. + sv_port_default6: Passed - CE. + sv_port_default7: Passed - CE. + sv_port_default8: Passed - CE. + sv_port_default9: Passed - CE. + sv_root_class: Passed - CE. + sv_unit2b: Passed - CE. + sv_unit3b: Passed - CE. + sv_unit4b: Passed - CE. + sv_uwire1: Passed - TE. + sv_uwire2: Passed - TE. + vvp_recv_vec4_pv: Passed - TE. + sv_var_init1: Passed - expected fail. + sv_var_init2: Passed - TE. + always4A: Passed - CE. + always4B: Passed - CE. + br936: Passed - CE. + br_gh165: Passed - CE. + br_gh368: Passed - CE. + br_gh412: Passed - CE. + br_gh414: Passed - CE. + br_gh436: Passed - CE. + br_mw20200501: Passed - CE. + disable_fork_cmd: Passed - CE. + enum_next: Passed - CE. + enum_test1: Passed - CE. + fork_join_any: Passed - CE. + fork_join_dis: Passed - CE. + fork_join_none: Passed - CE. + logical_short_circuit: Passed - CE. + plus_5: Passed - CE. + pr3366217f: Passed - CE. + pr3366217h: Passed - CE. + pr3366217i: Passed - CE. + pr3390385: Passed - CE. + pr3390385b: Passed - CE. + pr3390385c: Passed - CE. + pr3390385d: Passed - CE. + pr3462145: Passed - CE. + wait_fork: Passed - CE. + wild_cmp_err: Passed - CE. + wild_cmp_err2: Passed - CE. + wild_cmp_net: Passed - CE. + wild_cmp_var: Passed - CE. + br_gh337: Passed - expected fail. + ibit_test: Passed - expected fail. + ibyte_test: Passed - expected fail. + iint_test: Passed - expected fail. + ilongint_test: Passed - expected fail. + ishortint_test: Passed - expected fail. + sbyte_test: Passed - expected fail. + sint_test: Passed - expected fail. + slongint_test: Passed - expected fail. + sshortint_test: Passed - expected fail. + ubyte_test: Passed - expected fail. + uint_test: Passed - expected fail. + ulongint_test: Passed - expected fail. + ushortint_test: Passed - expected fail. + br_gh99e: Passed - expected fail. + implicit_cast1: Passed - expected fail. + implicit_cast2: Passed - expected fail. + implicit_cast3: Passed - expected fail. + implicit_cast8: Passed - expected fail. + implicit_cast10: Passed - expected fail. + implicit_cast11: Passed - expected fail. + partselsynth: Passed - TE. + pr1723367: Passed - TE. + generate_multi_loop: Not Implemented. + pr3194155: Not Implemented. + pr3452808: Not Implemented. + bitsel5: Passed - CE. + pr751: Passed - CE. + vhdl_var_init: Passed - CE. + size_cast4: Passed - expected fail. + br_gh219: Passed - expected fail. + rise_fall_decay2: Passed - CE. + array_packed_2d: Passed. + br_gh112c: Passed. + br_gh112d: Passed. + br_gh162: Passed - TE. + vhdl_concat_func: Passed - expected fail. + vhdl_resize: Passed - expected fail. + pr2159630: Passed - expected fail. + analog1: Passed - CE. + analog2: Passed - CE. + br955: Passed - CE. + br988: Passed - CE. + br_gh345: Passed - CE. + br_gh567: Passed - CE. + br_gh568: Passed - CE. + complex_lidx: Passed - CE. + defparam3: Passed - CE. + defparam4: Passed - CE. + gen_case_opt1: Passed - CE. + gen_case_opt2: Passed - CE. + gen_case_opt3: Passed - CE. + genloop: Passed - CE. + generate_case: Passed - CE. + generate_case2: Passed - CE. + generate_case3: Passed - CE. + genvar_inc_dec: Passed - CE. + packeda2: Passed - CE. + pr1565699b: Passed - CE. + pr1623097: Passed - CE. + pr1676071: Passed - CE. + pr1691599b: Passed - CE. + pr1695309: Passed - CE. + pr1704726b: Passed - CE. + pr1755629: Passed - CE. + pr1828642: Passed - CE. + pr1956211: Passed - CE. + pr1960625: Passed - CE. + pr1988302: Passed - CE. + pr1988310: Passed - CE. + pr2018235a: Passed - CE. + pr2091455: Passed - CE. + pr2109179: Passed - CE. + pr2138682: Passed - CE. + pr2257003: Passed - CE. + pr2257003b: Passed - CE. + pr2306259: Passed - CE. + pr2350934: Passed - CE. + pr2350934b: Passed - CE. + pr2350988: Passed - CE. + pr2355304: Passed - CE. + pr2728812a: Passed - CE. + pr2815398a: Passed - CE. + pr2815398a_std: Passed - CE. + pr2909414: Passed - CE. + pr2924354: Passed - CE. + pr3011327: Passed - CE. + pr3409749: Passed - CE. + pr3437290b: Passed - CE. + pr3527694: Passed - CE. + pr3534422: Passed - CE. + pr3557493: Passed - CE. + scoped_events: Passed - CE. + sv_packed_port1: Passed - CE. + sv_packed_port2: Passed - CE. + br_gh433: Passed - CE. + sv_queue1: Passed - CE. + sv_queue2: Passed - CE. + sv_queue3: Passed - CE. + sv_queue_real: Passed - CE. + sv_queue_real_bounded: Passed - CE. + sv_queue_real_fail: Passed - CE. + sv_queue_string: Passed - CE. + sv_queue_string_bounded: Passed - CE. + sv_queue_string_fail: Passed - CE. + sv_queue_vec: Passed - CE. + sv_queue_vec_bounded: Passed - CE. + sv_queue_vec_fail: Passed - CE. + test_forgen: Passed - CE. + test_gxor: Passed - CE. + test_varray1: Passed - CE. + unnamed_generate_block: Passed - CE. + always_ff_warn_sens: Passed - CE. + bitsel6: Passed - CE. + bitsel7: Passed - CE. + pr3054101a: Passed - CE. + pr3054101b: Passed - CE. + pr2835632b: Passed - CE. + pr3054101c: Passed - CE. + pr3054101d: Passed - CE. + pr3054101e: Passed - CE. + pr3054101f: Passed - CE. + signed_part: Passed - CE. + bitsel10: Passed - CE. + br918c: Passed - CE. + br965: Passed - CE. + br_gh127b: Passed - CE. + br_gh127c: Passed - CE. + br_gh127e: Passed - CE. + br_gh127f: Passed - CE. + br_gh315: Passed - CE. + br_gh316c: Passed - CE. + br_gh356a: Passed - CE. + br_gh356b: Passed - CE. + countdrivers3: Passed - CE. + inout: Passed - TE. + inout2: Passed - CE. + inout3: Passed - CE. + inout4: Passed - CE. + pr1444055: Passed - CE. + pr1478121: Passed - CE. + pr2219441: Passed - CE. + pr3296466a: Passed - CE. + pr3296466b: Passed - CE. + pr3296466d: Passed - CE. + rise_fall_delay3: Passed - CE. + tri2: Passed - CE. + basicexpr: Passed - TE. + basicstate: Passed - TE. + basicstate2: Passed - TE. + br993a: Passed - TE. + br993b: Passed - TE. + br994: Passed - TE. + br_gh99v: Passed - TE. + br_gh99w: Passed - TE. + br_gh99x: Passed - TE. + casesynth1: Passed - TE. + casesynth2: Passed - TE. + casesynth3: Passed - TE. + casesynth7: Passed - TE. + conditsynth1: Passed - TE. + conditsynth2: Passed - TE. + conditsynth3: Passed - TE. + dffsynth6: Passed - TE. + dffsynth9: Passed - TE. + dffsynth10: Passed - TE. + inside_synth2: Passed - TE. + multireg: Passed - TE. + shiftl: Passed - TE. + ufuncsynth1: Passed - TE. + pr685: Passed - TE. + dffsynth7: Passed - CE. + dffsynth11: Passed - CE. + sqrt32synth: Passed - CE. + pr1830834: Passed - expected fail. + vhdl_loop: Passed - CO. + br916a: Passed. + br916b: Passed. + br1003b: Passed. + br1003c: Passed. + br1003d: Passed. + br1007: Passed. + br_gh230: Passed - RE. + eofmt_percent: Passed. + fatal_et_al: Passed. + fdisplay3: Passed - RE. + fdisplay_fail_fd: Passed. + fdisplay_fail_mcd: Passed. + format: Passed. + fread-error: Passed - RE. + fscanf_u_warn: Passed. + fscanf_z_warn: Passed. + localparam_type: Passed. + parameter_type: Passed. + mem1: Passed. + pic: Passed. + pr910: Passed. + pr1698820: Passed. + pr1819452: Passed. + pr2509349a: Passed. + pr2509349b: Passed. + pr2800985b: Passed - RE. + queue_fail: Passed - RE. + readmem-invalid: Passed - RE. + simparam: Passed - expected fail. + sv_immediate_assert: Passed. + sv_immediate_assume: Passed. + swrite: Passed. + sys_func_task_error: Passed - RE. + sys_func_as_task: Passed - RE. + warn_opt_sys_tf: Passed - RE. + writemem-error: Passed. + writemem-invalid: Passed - RE. + array6: Passed. + assign_op_type: Passed. + bitp1: Passed. + bits: Passed. + bits2: Passed. + br884: Passed. + br917a: Passed. + br917b: Passed. + br917c: Passed. + br917d: Passed. + br943_944: Passed. + br985: Passed. + br1025: Passed. + br_gh8: Passed. + br_gh99c: Passed. + br_gh99r: Passed. + br_gh112e: Passed. + br_gh112f: Passed. + br_gh129: Passed. + br_gh198: Passed. + br_gh199a: Passed. + br_gh199b: Passed. + br_gh231: Passed. + br_gh281: Passed. + br_gh281b: Passed. + br_gh283a: Passed. + br_gh283b: Passed. + br_gh283c: Passed. + br_gh289b: Passed. + br_gh477: Passed. + br_gh540: Passed. + ca_mult: Passed. + cast_int: Passed. + cast_int_ams: Passed. + cfunc_assign_op_vec: Passed. + constfunc4: Passed. + constfunc4_ams: Passed. + constfunc6: Passed. + constfunc6_ams: Passed. + constfunc7: Passed. + constfunc13: Passed. + constfunc14: Passed. + enum_elem_ranges: Passed. + enum_value_expr: Passed. + enum_values: Passed. + enum_ports: ==> Failed - running iverilog (translated). + extend: Passed. + first_last_num: Passed. + fr49: Passed. + function12: Passed. + implicit_cast7: Passed. + implicit_cast9: Passed. + inc_dec_stmt: Passed. + int_param: Passed. + iuint1: Passed. + logp2: Passed. + mixed_width_case: Passed. + mod_inst_pkg: Passed. + packeda: Passed. + pr1033: Passed. + pr1380261: Passed. + pr1494799: Passed. + pr1589497: Passed. + pr1603313: Passed. + pr1717361: Passed. + pr1719055: Passed. + pr1793749: Passed. + pr1879226: Passed. + pr1883052: Passed. + pr1883052b: Passed. + pr1950282: Passed. + pr1958801: Passed. + pr1993479: Passed. + pr2030767: Passed. + pr2117473: Passed. + pr2121536: Passed. + pr2121536b: Passed. + pr2152011: Passed. + pr2233180: Passed. + pr2233180b: Passed. + pr2233180c: Passed. + pr2233192: Passed. + pr2233192b: Passed. + pr2233192c: Passed. + pr2425055b: Passed. + pr2425055c: Passed. + pr2722330a: Passed. + pr2722330b: Passed. + pr2909555: Passed. + pr2913416: Passed. + pr2913438b: Passed. + pr2922063: Passed. + pr2922063a: Passed. + pr2922063b: Passed. + pr2986528: Passed. + pr2998515: Passed. + pr3104254: Passed. + pr3284821: Passed. + pr3292735: Passed. + pr3366217e: Passed. + pr748: Passed. + pull371: Passed. + pull371b: Passed. + sf1289: Passed. + shift2: Passed. + shift3: Passed. + shift5: Passed. + signed1: Passed. + signed4: Passed. + signed6: Passed. + signed7: Passed. + signed8: Passed. + signed9: Passed. + signed12: Passed. + signed_a: Passed. + signed_pv: Passed. + simple_byte: Passed. + simple_int: Passed. + simple_longint: Passed. + simple_shortint: Passed. + size_cast3: Passed. + size_cast5: Passed. + struct_packed_array: Passed. + struct_packed_array2: Passed. + sv_for_variable: Passed. + sv_foreach1: Passed. + sv_foreach5: Passed. + sv_package: Passed. + sv_package2: Passed. + sv_package5: Passed. + sv_port_default10: Passed. + sv_port_default11: Passed. + sv_root_func: Passed. + sv_root_task: Passed. + test_dispwided: Passed. + test_inc_dec: Passed. + test_enumsystem: Passed. + vhdl_boolean: Passed. + vhdl_file_open: Passed. + vhdl_prefix_array: Passed. + vhdl_range: Passed. + vhdl_rtoi: Passed. + vhdl_shift: Passed. + vhdl_to_integer: Passed. + test_system: Passed. + test_tliteral: Passed. + vhdl_test8: Passed. + vhdl_test9: Passed. + two_state_display: Passed. + undefined_shift: Passed. + vams_abs1: Passed. + vhdl_concurrent_assert: Passed. + vhdl_const_record: Passed. + vhdl_delay_assign: Passed. + vhdl_image_attr: Passed. + vhdl_process_scope: Passed. + vhdl_sadd23_bit: Passed. + vhdl_sdiv23_bit: Passed. + vhdl_ssub23_bit: Passed. + vhdl_smul23_bit: Passed. + vhdl_sadd23_stdlogic: Passed. + vhdl_sdiv23_stdlogic: Passed. + vhdl_ssub23_stdlogic: Passed. + vhdl_smul23_stdlogic: Passed. + vhdl_test3: Passed. + vhdl_subtypes: Passed. + vhdl_unary_minus: Passed. + vhdl_while: Passed. + br919: Passed. + br968: Passed. + concat3: Passed. + l_equiv: Passed. + l_equiv_ca: Passed. + mult2: Passed. + pr757: Passed. + pr1002: Passed. + pr1002a: Passed. + pr1522570: Passed. + pr1698499: Passed. + pr1793749b: Passed. + pr1795005a: Passed. + pr1795005b: Passed. + pr1823732: Passed. + pr1841300: Passed. + pr1845683: Passed. + pr1960558: Passed. + pr1960619: Passed. + pr1963240: Passed. + pr1990164: Passed. + pr2136787: Passed. + pr2138979: Passed. + pr2138979b: Passed. + pr2138979c: Passed. + pr2138979d: Passed - expected fail. + pr2722339a: Passed. + pr2722339b: Passed. + pr2901556: Passed. + pr2913404: Passed. + pr3077640: Passed. + select_padding: Passed. + shift4: Passed. + signed5: Passed. + signed10: Passed. + signed13: Passed. + readmem-error: Passed. + param_select3: Passed. + select5: Passed. + pr487: Passed. + big_int: Passed. + pr2673846: Passed. + pr2029336: Passed. + urand: Passed. + casesynth6: Passed. + case_priority: Passed. + case_unique: Passed. + br_gh377: Passed. + dffsynth: Passed - CE. + memsynth1: Passed - CE. + memsynth2: Passed - CE. + memsynth3: Passed - CE. + memsynth5: Passed - CE. + memsynth6: Passed - CE. + memsynth7: Passed - CE. + memsynth9: Passed - CE. + mix_reset: Passed - CE. + case1: Passed. + case2: Passed. + casex_synth: Passed. + pr903: Passed. + pr1388974: Passed. + br_gh13a: Passed. + param-width: Passed. + pr1701890: Passed. + macro_str_esc: Passed. + macro_with_args: Passed. + mcl1: Passed. + pr622: Passed. + pr639: Passed. + pr1741212: Passed. + pr1912112: Passed. + pr1925360: Passed. + repeat1: Passed. + pr2002443: Passed - CO. + non-polymorphic-abs: Passed. + pr3270320_ams: Passed - CE. + test_va_math: Passed. + va_math: Passed. + abstime: Passed. + pr2590274a: Passed. + pr2590274b: Passed. + pr2590274c: Passed. + bitsel: Passed. + bitsel2: Passed. + bitsel3: Passed. + bitsel4: Passed. + bitsel8: Passed. + bitsel9: Passed. + bitwidth3: Passed. + clog2-signal: Passed. + param_vec: Passed. + param_vec2: Passed. + pr498: Passed. + pr721: Passed. + pr809: Passed. + pr809b: Passed. + pr979: Passed. + pr1000: Passed. + pr1609611: Passed. + pr1750870: Passed. + pr1765789: Passed. + pr1771903: Passed. + pr1861212b: Passed. + pr2806449: Passed. + pr2877555: Passed. + real4: Passed. + realtobits: Passed. + specparam1: Passed. + specparam2: Passed. + tern3: Passed. + deposit: Passed. + deposit_wire: Passed. + sysargs: Passed. + fatal_et_al2: Passed - RE. + fileio: Passed. + pr2428890c: Passed. + br978: Passed. + br_ml20150424: Passed. + blocking_repeat_ec: Passed. + ca_time_smtm: Passed. + nb_array_pv: Passed. + nb_ec_array: Passed. + nb_ec_array_pv: Passed. + nb_ec_pv: Passed. + nb_ec_pv2: Passed. + nb_ec_real: Passed. + nb_ec_vector: Passed. + pr2486350: Passed. + pr534: Passed. + stime: Passed. + time6: Passed. + time6b: Passed. + time6c: Passed. + concat1: Passed. + concat2: Passed. + constconcat1: Passed. + constconcat2: Passed. + rptconcat2: Passed. + sdw_lvalconcat2: Passed. + bool1: Passed. + compare_bool_reg: Passed. + constfunc8: Passed. + binary_nand: Passed. + binary_nor: Passed. + pr2976242c: Passed - CE. + real_concat_invalid1: Passed - CE. + real_op_fail: Passed - CE. + real_select_invalid: Passed - CE. + sv-2val-nets: Passed. + pr2476430: Passed. + cmdline_parm1: Passed. + array_dump: Passed. + pr2859628: Passed. + race: Passed. + automatic_error4: Passed - CE. + br605a: Passed - expected fail. + br605b: Passed - expected fail. + br971: Passed - expected fail. + br1005: Passed - CE. + br1015b: Passed - CE. + br_gh130b: Passed - CE. + br_gh386d: Passed - CE. + br_ml20150315b: Passed - CE. + sv_deferred_assert1: Passed - CE. + sv_deferred_assert2: Passed - CE. + sv_deferred_assume1: Passed - CE. + sv_deferred_assume2: Passed - CE. + pr1909940: Passed. + pr1909940b: Passed. + br_gh497b: Passed - CE. + br_gh497d: Passed - CE. + br_gh497f: Passed - CE. + addsr: Passed. + addwide: Passed. + always3.1.1A: Passed - CE. + always3.1.1B: Passed - CE. + always3.1.1C: Passed. + always3.1.1D: Passed. + always3.1.1E: Passed. + always3.1.1F: Passed. + always3.1.1G: Passed. + always3.1.1H: Passed. + always3.1.1I: Passed. + always3.1.1J: Passed. + always3.1.1K: Passed. + always3.1.2A: Passed - CE. + always3.1.2B: Passed - CE. + always3.1.2C: Passed - CE. + always3.1.2D: Passed - CE. + always3.1.2E: Passed - CE. + always3.1.2F: Passed - CE. + always3.1.2G: Passed - CE. + always3.1.2H: Passed - CE. + always3.1.2I: Passed - CE. + always3.1.3A: Passed - CE. + always3.1.3B: Passed - CE. + always3.1.3B2: Passed. + always3.1.3C: Passed - CE. + always3.1.3D: Passed - CE. + always3.1.3D2: Passed. + always3.1.3E: Passed - CE. + always3.1.3E2: Passed. + always3.1.3F: Passed - CE. + always3.1.3F2: Passed. + always3.1.3G: Passed - CE. + always3.1.3H: Passed - CE. + always3.1.3J: Passed - CE. + always3.1.4A: Passed. + always3.1.4B: Passed. + always3.1.4C: Passed. + always3.1.4D: Passed. + always3.1.4E: Passed. + always3.1.4F: Passed. + always3.1.4G: Passed. + always3.1.4H: Passed. + always3.1.4I: Passed. + always3.1.5A: Passed. + always3.1.5B: Passed. + always3.1.5C: Passed. + always3.1.5D: Passed. + always3.1.5E: Passed. + always3.1.5F: Passed. + always3.1.6A: Passed. + always3.1.6B: Passed. + always3.1.6C: Passed. + always3.1.6D: Passed. + always3.1.7A: Passed. + always3.1.7B: Passed. + always3.1.7C: Passed. + always3.1.7D: Passed. + always3.1.8A: Passed. + always3.1.9A: Passed - CE. + always3.1.9B: Passed - CE. + always3.1.9C: Passed. + always3.1.9D: Passed. + always3.1.10A: Passed - CE. + always3.1.11A: Passed. + always3.1.11B: Passed. + always3.1.12A: Passed. + always3.1.12B: Passed. + always3.1.12C: Passed. + always_star_array_lval: Passed. + andnot1: Passed. + arith-unknown: Passed. + array4: Passed. + array5: Passed - CE. + array7: Passed. + array_word_check: Passed. + array_word_width: Passed. + assign3.2A: Passed. + assign3.2B: Passed. + assign3.2C: Passed. + assign3.2D: Passed. + assign3.2E: Passed. + assign_add: Passed. + assign_deassign_pv: Passed. + assign_delay: Passed. + assign_deq: Passed. + assign_ge: Passed. + assign_le: Passed. + assign_mem1: Passed. + assign_mem2: Passed. + assign_nb1: Passed. + assign_nb2: Passed. + assign_neq: Passed. + attrib: Passed. + attrib01_module: Passed. + attrib02_port_decl: Passed. + attrib03_parameter: Passed. + attrib04_net_var: Passed. + attrib05_port_conn: Passed. + attrib06_operator_suffix: Passed. + attrib07_func_call: Passed. + attrib08_mod_inst: Passed. + attrib09_case: Passed. + automatic_error1: Passed - CE. + automatic_error2: Passed - CE. + automatic_error3: Passed - CE. + automatic_error5: Passed - CE. + automatic_error6: Passed - CE. + automatic_error7: Passed - CE. + automatic_error8: Passed - CE. + automatic_error9: Passed - CE. + automatic_error10: Passed - CE. + bitwidth: Passed. + bitwidth2: Passed. + blankport: Passed. + block_only_with_var_def: Passed. + bnot: Passed. + br918a: Passed. + br918b: Passed. + br918d: Passed. + br924: Passed - CE. + br930: Passed - CO. + br931: Passed. + br935: Passed. + br937: Passed. + br946: Passed. + br947: Passed. + br948: Passed. + br960a: Passed. + br960b: Passed. + br960c: Passed. + br960d: Passed. + br961: Passed. + br961a: Passed - CE. + br967: Passed. + br972: Passed. + br977: Passed. + br982: Passed - CE. + br982a: Passed - CE. + br982b: Passed - CE. + br990: Passed. + br991a: Passed. + br999: Passed. + br1000: Passed. + br1001: Passed. + br1006: Passed. + br1015a: Passed - CE. + br1027: Passed. + br1027a: Passed - CE. + br1027c: Passed - CE. + br1027e: Passed - CE. + br1029a: Passed. + br1029b: Passed. + br1029c: Passed - CE. + br_gh6: Passed. + br_gh7: Passed. + br_gh11: Passed - CO. + br_gh12: Passed. + br_gh13: Passed. + br_gh14: Passed. + br_gh15: Passed. + br_gh18: Passed. + br_gh19: Passed. + br_gh19a: Passed. + br_gh19b: Passed. + br_gh22: Passed. + br_gh25a: Passed - CE. + br_gh25b: Passed - CE. + br_gh26: Passed - CE. + br_gh28: Passed. + br_gh30: Passed. + br_gh33: Passed. + br_gh37: Passed. + br_gh60a: Passed - CE. + br_gh62: Passed - CE. + br_gh79: Passed - CE. + br_gh99a: Passed. + br_gh99b: Passed. + br_gh99d: Passed. + br_gh99f: Passed. + br_gh99g: Passed. + br_gh99h: Passed. + br_gh99i: Passed. + br_gh99j: Passed. + br_gh99k: Passed. + br_gh99l: Passed. + br_gh99m: Passed. + br_gh99o: Passed. + br_gh99p: Passed. + br_gh99q: Passed. + br_gh99s: Passed. + br_gh99t: Passed. + br_gh99u: Passed. + br_gh103: Passed. + br_gh127a: Passed. + br_gh127d: Passed. + br_gh142: Passed - CE. + br_gh152: Passed - CE. + br_gh157: Passed. + br_gh163: Passed - CE. + br_gh209: Passed. + br_gh277a: Passed. + br_gh309: Passed. + br_gh316a: Passed. + br_gh316b: Passed. + br_gh330: Passed. + br_gh435: Passed. + br_gh484: Passed. + br_gh497a: Passed. + br_gh497c: Passed. + br_gh497e: Passed. + br_gh508b: Passed. + br_gh515: Passed. + br_gh533: Passed - CE. + br_ml20150315: Passed. + br_ml20150321: Passed - CE. + br_ml20150606: Passed. + br_ml20190806a: Passed. + br_ml20190806b: Passed. + br_ml20190814: Passed. + bufif: Passed. + busbug: Passed. + ca_force: Passed. + ca_func: Passed. + ca_real_logical: Passed. + ca_time: Passed. + case3.8A: Passed. + case3.8B: Passed. + case3.8C: Passed. + case3.8D: Passed. + casex3.9A: Passed. + casex3.9B: Passed. + casex3.9C: Passed. + casex3.9D: Passed. + casex3.9E: Passed. + casez3.10A: Passed. + casez3.10B: Passed. + casez3.10C: Passed. + casez3.10D: Passed. + casez3.10E: Passed. + check_constant_1: Passed - CE. + check_constant_2: Passed - CE. + check_constant_3: Passed - CE. + check_constant_4: Passed - CE. + check_constant_5: Passed - CE. + check_constant_6: Passed - CE. + check_constant_7: Passed - CE. + check_constant_8: Passed - CE. + check_constant_9: Passed - CE. + check_constant_10: Passed - CE. + check_constant_11: Passed - CE. + check_constant_12: Passed - CE. + check_constant_13: Passed - CE. + check_constant_14: Passed - CE. + check_constant_15: Passed - CE. + check_constant_16: Passed - CE. + check_constant_17: Passed - CE. + check_constant_18: Passed - CE. + check_constant_19: Passed - CE. + check_constant_20: Passed - CE. + cmos: Passed. + comment1: Passed - CE. + comp1000: Passed. + comp1001: Passed. + comp1001_fail3: Passed. + comp1001_fail4: Passed. + comp1001_fail5: Passed. + con_tri: Passed. + concat_zero_wid_fail: Passed - CE. + concat_zero_wid_fail2: Passed. + cond_band: Passed. + cond_wide: Passed. + cond_wide2: Passed. + const: Passed. + const2: Passed. + const3: Passed. + const4: Passed. + constadd: Passed. + constadd2: Passed. + constadd3: Passed. + constfunc1: Passed. + constfunc2: Passed. + constfunc5: Passed. + constfunc9: Passed. + constfunc10: Passed. + constfunc11: Passed. + constfunc12: Passed. + constfunc15: Passed. + constmult: Passed. + consttern: Passed. + contrib8.1: Passed. + contrib8.2: Passed. + contrib8.3: Passed - CE. + contrib8.4: Passed. + contrib8.5: Passed. + countdrivers1: Passed. + countdrivers2: Passed. + countdrivers4: Passed. + countdrivers5: Passed. + cprop: Passed. + credence20041209: Passed. + dangling_port: Passed. + dcomp1: Passed. + deassign3.4A: Passed. + decl_assign1: Passed. + def_nettype_none: Passed - CE. + define1: Passed. + defparam: Passed. + defparam2: Passed. + defparam3.5: Passed. + delay: Passed. + delay2: Passed. + delay3: Passed. + delay4: Passed. + delay5: Passed. + delay_assign_nb: Passed. + delay_assign_nb2: Passed. + delay_var: Passed. + delayed_comp_reduct: Passed. + dff1: Passed. + disable3.6A: Passed. + disable3.6B: Passed. + disable_cleanup: Passed. + disable_fork: Passed. + disblock: Passed. + disblock2: Passed. + disp_dec: Passed. + disp_dec2: Passed. + disp_leading_z: Passed. + disp_parm: Passed. + disp_part: Passed. + div16: Passed. + dotinid: Passed. + drive_strength: Passed. + drive_strength1: Passed. + drive_strength2: Passed. + drive_strength3: Passed. + dummy7: Passed. + dump_memword: Passed. + dumpvars: Passed. + eeq: Passed. + else1: Passed. + else2: Passed. + else3: Passed. + elsif_test: Passed. + eq: Passed. + escape1: Passed. + escape2a: Passed - CO. + escape2b: Passed - CO. + escape2c: Passed - CO. + escape3: Passed. + escape4: Passed. + escape4b: Passed. + event2: Passed. + event3: Passed. + event3.15: Passed. + event_array: Passed - CE. + event_list: Passed. + event_list2: Passed. + event_list3: Passed. + fdisplay1: Passed. + fdisplay2: Passed. + fifo: Passed. + fopen1: Passed. + fopen2: Passed. + for3.16A: Passed. + force1: Passed. + force2: Passed. + force3.17A: Passed. + force3.17B: Passed. + force3.17C: Passed. + force_lval_part: Passed. + force_release_reg_pv: Passed. + force_release_wire8_pv: Passed. + force_release_wire_pv: Passed. + fork1: Passed. + fork3.19A: Passed. + fork3.19B: Passed. + fr47: Passed. + fread: Passed. + fscanf_u: Passed. + fscanf_z: Passed. + function1: Passed. + function2: Passed. + function3: Passed. + function3.11B: Passed. + function3.11C: Passed. + function3.11D: Passed. + function3.11F: Passed. + function4: Passed - CE. + function5: Passed - CO. + function6: Passed. + function7: Passed. + function8: Passed. + function9: Passed. + function_exp: Passed. + ga_and: Passed. + ga_mod: Passed. + ga_mod1: Passed. + ga_mod2: Passed. + ga_nand: Passed. + ga_nor: Passed. + ga_or: Passed. + ga_xnor: Passed. + ga_xor: Passed. + galan: Passed. + gate_connect1: Passed. + gate_connect2: Passed - CE. + gencrc: Passed. + hello1: Passed. + hier_ref_error: Passed - CE. + hierspace: Passed. + idiv1: Passed. + idiv2: Passed. + idiv3: Passed. + ifdef1: Passed. + ifdef2: Passed. + ifdef3: Passed. + ifdef4: Passed. + ifdef_fail: Passed - CE. + include1: Passed. + include2: Passed. + include3: Passed. + indef_width_concat: Passed - CE. + initmod: Passed. + initmod2: Passed. + int_not_signext: Passed. + integer1lt: Passed. + integer2le: Passed. + integer3gt: Passed. + integer4ge: Passed. + integer5: Passed. + itor_rtoi: Passed. + land2: Passed. + land3: Passed. + land4: Passed. + landor1: Passed. + ldelay1: Passed. + ldelay2: Passed. + ldelay3: Passed. + ldelay4: Passed. + ldelay5: Passed. + lh_catadd: Passed. + lh_memcat: Passed. + lh_memcat2: Passed. + lh_memcat3: Passed. + lh_varindx: Passed. + lh_varindx2: Passed. + lh_varindx4: Passed. + lh_varindx5: Passed. + long_div: Passed. + macro2: Passed. + macro_redefinition: Passed. + macro_replacement: Passed. + macsub: Passed. + mangle: Passed. + mangle_1: Passed. + many_drivers: Passed. + mcl2: Passed. + mem2port: Passed. + memassign: Passed. + memidx: Passed. + memidxrng: Passed. + meminit: Passed. + memport_bs: Passed. + memref: Passed. + mhead_task: Passed. + mixed_type_div_mod: Passed. + modparam: Passed. + module3.12A: Passed. + module3.12B: Passed. + modulus: Passed. + modulus2: Passed. + monitor: Passed. + monitor2: Passed. + monitor3: Passed. + mult1: Passed. + mult16: Passed. + multi_bit_strength: Passed. + multi_driver_delay: Passed. + multiply_large: Passed. + muxtest: Passed. + named_event_no_edges: Passed - CE. + nb_assign: Passed. + nb_delay: Passed. + nblkorder: Passed. + negvalue: Passed. + neq1: Passed. + nested_impl_event1: Passed. + nested_impl_event2: Passed. + no_if_statement: Passed - CE. + no_timescale_in_module: Passed - CE. + npmos: Passed. + npmos2: Passed. + onehot: Passed. + p_monta: Passed. + par_mismatch: Passed - CE. + param-extend: Passed. + param_add: Passed. + param_and: Passed. + param_and2: Passed. + param_band: Passed. + param_binv: Passed. + param_bor: Passed. + param_concat: Passed. + param_eq3: Passed. + param_expr: Passed. + param_mod: Passed. + param_select: Passed. + param_select2: Passed. + param_string: Passed. + param_tern: Passed. + param_tern2: Passed. + param_test1: Passed. + param_test2: Passed. + param_test3: Passed. + param_test4: Passed. + param_times: Passed. + patch1268: Passed. + pca1: Passed. + port-test2: Passed. + port-test3: Passed - CE. + port-test4a: Passed - CE. + port-test4b: Passed - CE. + port-test5: Passed. + port-test6: Passed. + port-test7: Passed. + posedge: Passed. + pow-const: Passed. + pr136: Passed. + pr142: Passed. + pr183: Passed - CO. + pr224: Passed. + pr224a: Passed. + pr243: Passed. + pr245: Passed. + pr245_std: Passed. + pr273: Passed. + pr298: Passed. + pr304: Passed. + pr307: Passed. + pr307a: Passed. + pr312: Passed. + pr338: Passed - CO. + pr355: Passed. + pr377: Passed. + pr434: Passed. + pr445: Passed. + pr478: Passed. + pr492: Passed. + pr508: Passed. + pr509: Passed. + pr509b: Passed. + pr511: Passed. + pr513: Passed. + pr522: Passed. + pr524: Passed. + pr527: Passed. + pr528: Passed. + pr528b: Passed. + pr529: Passed. + pr530a: Passed. + pr530b: Passed. + pr530c: Passed. + pr531a: Passed. + pr531b: Passed. + pr532: Passed. + pr532b: Passed. + pr533: Passed. + pr538: Passed. + pr540: Passed. + pr540b: Passed. + pr540c: Passed. + pr541: Passed. + pr542: Passed. + pr544: Passed. + pr547: Passed. + pr556: Passed. + pr564: Passed. + pr569: Passed. + pr572: Passed. + pr572b: Passed. + pr578: Passed. + pr584: Passed. + pr585: Passed. + pr587: Passed. + pr590: Passed. + pr594: Passed. + pr596: Passed. + pr602: Passed. + pr617: Passed. + pr632: Passed. + pr673: Passed. + pr675: Passed. + pr678: Passed. + pr690: Passed. + pr693: Passed. + pr699: Passed. + pr699b: Passed. + pr704: Passed. + pr707: Passed. + pr708: Passed. + pr710: Passed. + pr718: Passed. + pr722: Passed. + pr729: Passed. + pr734: Passed. + pr735: Passed. + pr772: Passed. + pr810: Passed. + pr812: Passed. + pr820: Passed. + pr823: Passed. + pr841: Passed. + pr842: Passed. + pr848: Passed. + pr856: Passed. + pr859: Passed. + pr860: Passed. + pr872: Passed. + pr902: Passed. + pr905: Passed. + pr913: Passed. + pr923: Passed. + pr938: Passed. + pr938b: Passed. + pr938b_std: Passed. + pr941: Passed. + pr973: Passed. + pr978: Passed. + pr985: Passed. + pr987: Passed. + pr990: Passed. + pr991: Passed. + pr993: Passed. + pr995: Passed. + pr1007: Passed. + pr1008: Passed. + pr1022: Passed. + pr1024: Passed. + pr1026: Passed. + pr1029: Passed. + pr1032: Passed. + pr1065: Passed. + pr1072: Passed. + pr1077: Passed. + pr1087: Passed. + pr1101: Passed. + pr1115: Passed. + pr1353345: Passed. + pr1353345b: Passed. + pr1367855: Passed. + pr1403406: Passed. + pr1403406a: Passed. + pr1403406b: Passed. + pr1421777: Passed. + pr1449749a: Passed. + pr1455873: Passed. + pr1465769: Passed. + pr1467825: Passed - CO. + pr1474283: Passed. + pr1474316: Passed. + pr1474318: Passed. + pr1476440: Passed. + pr1477190: Passed. + pr1478988: Passed. + pr1489568: Passed. + pr1489570: Passed. + pr1491355: Passed. + pr1492075: Passed. + pr1508882: Passed. + pr1510724: Passed. + pr1515168: Passed. + pr1520314: Passed - CO. + pr1530426: Passed. + pr1561597: Passed. + pr1570451: Passed. + pr1570451b: Passed. + pr1570635: Passed. + pr1570635b: Passed. + pr1574175: Passed. + pr1581580: Passed. + pr1587634: Passed - CO. + pr1587669: Passed. + pr1598445: Passed. + pr1601896: Passed. + pr1601898: Passed. + pr1603918: Passed. + pr1612693: Passed. + pr1625912: Passed. + pr1628288: Passed. + pr1628300: Passed. + pr1629683: Passed. + pr1632861: Passed. + pr1634526: Passed. + pr1636409: Passed. + pr1637208: Passed. + pr1638985: Passed. + pr1639060: Passed. + pr1639064: Passed. + pr1639064b: Passed. + pr1639968: Passed. + pr1639971: Passed. + pr1645277: Passed. + pr1645518: Passed. + pr1648365: Passed. + pr1650842: Passed. + pr1661640: Passed. + pr1662508: Passed. + pr1664684: Passed. + pr1675789: Passed. + pr1675789b: Passed. + pr1676836: Passed. + pr1682887: Passed. + pr1687193: Passed. + pr1688717: Passed. + pr1690058: Passed. + pr1691709: Passed. + pr1693890: Passed. + pr1693921: Passed. + pr1694413: Passed. + pr1694427: Passed. + pr1695257: Passed - CO. + pr1695334: Passed. + pr1696137: Passed. + pr1697250: Passed. + pr1697732: Passed. + pr1698658: Passed. + pr1698659: Passed. + pr1699444: Passed. + pr1699519: Passed. + pr1701855: Passed. + pr1701889: Passed. + pr1701921: Passed. + pr1702593: Passed. + pr1703120: Passed. + pr1703959: Passed. + pr1704013: Passed - CE. + pr1704726a: Passed - CE. + pr1704726c: Passed - CE. + pr1704726d: Passed - CE. + pr1705027: Passed - CO. + pr1716276: Passed. + pr1735724: Passed - CE. + pr1735822: Passed. + pr1735836: Passed. + pr1742910: Passed. + pr1745005: Passed. + pr1746401: Passed. + pr1746848: Passed. + pr1752353: Passed. + pr1752823a: Passed. + pr1752823b: Passed. + pr1755593: Passed. + pr1758135: Passed. + pr1763333: Passed - CE. + pr1770199: Passed. + pr1776485: Passed. + pr1777103: Passed. + pr1780480: Passed. + pr1784984: Passed. + pr1787394a: Passed. + pr1787394b: Passed. + pr1787423: Passed. + pr1787423b: Passed. + pr1787423c: Passed. + pr1792108: Passed. + pr1792152: Passed. + pr1792734: Passed. + pr1793157: Passed. + pr1794362: Passed. + pr1804877: Passed. + pr1805837: Passed. + pr1812297: Passed. + pr1822658: Passed. + pr1831724: Passed. + pr1832097a: Passed. + pr1832097b: Passed. + pr1833024: Passed - CE. + pr1833754: Passed - CE. + pr1851310: Passed. + pr1855504: Passed. + pr1861212a: Passed. + pr1862744a: Passed. + pr1862744b: Passed - CE. + pr1866215: Passed. + pr1866215b: Passed. + pr1867161a: Passed. + pr1867161b: Passed. + pr1867332: Passed - CO. + pr1868991a: Passed. + pr1868991b: Passed - CO. + pr1869769: Passed. + pr1869772: Passed. + pr1869781: Passed. + pr1873146: Passed. + pr1875866: Passed. + pr1875866b: Passed. + pr1877740: Passed. + pr1877743: Passed. + pr1878909: Passed. + pr1885847: Passed. + pr1887168: Passed. + pr1892959: Passed. + pr1892959b: Passed. + pr1898983: Passed. + pr1901125: Passed. + pr1903157: Passed - CO. + pr1903343: Passed. + pr1903520: Passed. + pr1907192: Passed. + pr1912843: Passed. + pr1913918a: Passed. + pr1913918b: Passed. + pr1913918c: Passed. + pr1913937: Passed. + pr1916261: Passed. + pr1916261a: Passed - CE. + pr1921332: Passed - CO. + pr1924845: Passed. + pr1925356: Passed. + pr1925363a: Passed - CE. + pr1925363b: Passed - CE. + pr1932444: Passed. + pr1934744: Passed. + pr1936363: Passed. + pr1938138: Passed - CE. + pr1939165: Passed. + pr1946411: Passed. + pr1948110: Passed. + pr1948342: Passed. + pr1949025: Passed. + pr1960545: Passed. + pr1960548: Passed. + pr1960575: Passed. + pr1960596: Passed. + pr1960633: Passed. + pr1963960: Passed. + pr1963962: Passed. + pr1971662a: Passed - CE. + pr1971662b: Passed - CE. + pr1978358: Passed. + pr1978358b: Passed. + pr1978358c: Passed. + pr1978358d: Passed. + pr1983762: Passed. + pr1985582: Passed. + pr1988302b: Passed - CE. + pr1990029: Passed. + pr1990269: Passed. + pr1992244: Passed. + pr1992729: Passed. + pr2001162: Passed. + pr2013758: Passed. + pr2014673: Passed. + pr2015466: Passed. + pr2018235b: Passed. + pr2018305: Passed. + pr2019553: Passed. + pr2036953: Passed. + pr2038048: Passed. + pr2039632: Passed - CE. + pr2039694: Passed. + pr2043324: Passed. + pr2043585: Passed. + pr2051694: Passed - CE. + pr2051975: Passed - CE. + pr2053944: Passed. + pr2076363: Passed. + pr2076425: Passed. + pr2085984: Passed. + pr2117488: Passed. + pr2119622: Passed. + pr2132552: Passed. + pr2139593: Passed. + pr2146620: Passed. + pr2146620b: Passed. + pr2146620c: Passed. + pr2146824: Passed. + pr2148401: Passed. + pr2166188: Passed. + pr2172606: Passed. + pr2181249: Passed. + pr2190323: Passed. + pr2202706: Passed. + pr2202706b: Passed. + pr2202706c: Passed. + pr2202846a: Passed. + pr2202846b: Passed. + pr2202846c: Passed. + pr2208681: Passed. + pr2215342: Passed. + pr2219441b: Passed. + pr2224845: Passed. + pr2224949: Passed. + pr2248925: Passed. + pr2251119: Passed. + pr2270035: Passed. + pr2281479: Passed. + pr2305307: Passed. + pr2305307b: Passed. + pr2305307c: Passed. + pr2355304b: Passed. + pr2358264: Passed. + pr2358848: Passed. + pr2395378a: Passed - CE. + pr2395378b: Passed - CE. + pr2395378c: Passed - CE. + pr2395835: Passed. + pr2425055a: Passed. + pr2428890: Passed. + pr2428890b: Passed. + pr2434688: Passed. + pr2434688b: Passed. + pr2450244: Passed. + pr2453002: Passed. + pr2459681: Passed. + pr2470181a: Passed. + pr2470181b: Passed. + pr2503208: Passed. + pr2528915: Passed - CE. + pr2533175: Passed. + pr2579479: Passed. + pr2580730: Passed. + pr2593733: Passed. + pr2597278: Passed. + pr2597278b: Passed - CE. + pr2605006: Passed. + pr2688910: Passed. + pr2709097: Passed. + pr2715547: Passed. + pr2715558: Passed. + pr2715558b: Passed. + pr2721213: Passed. + pr2723712: Passed. + pr2725700a: Passed. + pr2725700b: Passed. + pr2725700c: Passed. + pr2728032: Passed. + pr2728547: Passed. + pr2728812b: Passed - CE. + pr2728812c: Passed - CE. + pr2745281: Passed. + pr2781595: Passed. + pr2785294: Passed. + pr2788686: Passed. + pr2790236: Passed. + pr2792883: Passed - CE. + pr2792897: Passed. + pr2794144: Passed - CE. + pr2800985a: Passed. + pr2801134: Passed. + pr2801662: Passed. + pr2809288: Passed - CE. + pr2818823: Passed. + pr2823414: Passed - CE. + pr2824189: Passed. + pr2829776: Passed. + pr2829776b: Passed. + pr2832234: Passed. + pr2834340: Passed. + pr2834340b: Passed. + pr2835632a: Passed. + pr2837451: Passed. + pr2842185: Passed. + pr2842621: Passed. + pr2842621_std: Passed. + pr2848986: Passed - CE. + pr2849783: Passed. + pr2865563: Passed. + pr2877564: Passed - CE. + pr2883958: Passed. + pr2885048: Passed. + pr2890322: Passed. + pr2909386a: Passed. + pr2913438a: Passed. + pr2913927: Passed. + pr2918095: Passed. + pr2930506: Passed. + pr2937417: Passed. + pr2937417b: Passed. + pr2937417c: Passed. + pr2941939: Passed. + pr2943394: Passed. + pr2951657: Passed. + pr2969724: Passed. + pr2971207: Passed. + pr2972866: Passed. + pr2973532: Passed. + pr2974051: Passed. + pr2974216: Passed. + pr2974216b: Passed. + pr2974294: Passed. + pr2985542: Passed. + pr2986497: Passed - CO. + pr2991457: Passed. + pr2991457b: Passed. + pr2994193: Passed. + pr3012758: Passed. + pr3015421: Passed - CE. + pr3022502: Passed. + pr3024131: Passed. + pr3039548: Passed. + pr3044843: Passed. + pr3061015a: Passed - CE. + pr3061015b: Passed - CE. + pr3061015c: Passed - CE. + pr3064375: Passed. + pr3064511: Passed. + pr3078759: Passed - CO. + pr3098439: Passed. + pr3098439a: Passed. + pr3098439b: Passed. + pr3103880: Passed. + pr3112073a: Passed - CE. + pr3149494: Passed. + pr3190941: Passed - CE. + pr3190948: Passed. + pr3197861: Passed. + pr3197917: Passed. + pr3270320: Passed - CE. + pr3296466c: Passed. + pr3306516: Passed. + pr3309391: Passed. + pr3368642: Passed. + pr3437290a: Passed. + pr3437290c: Passed. + pr3441576: Passed. + pr3445452: Passed. + pr3465541: Passed. + pr3477107: Passed. + pr3499807: Passed. + pr3522653: Passed. + pr3527022: Passed. + pr3539372: Passed. + pr3549328: Passed - CE. + pr3561350: Passed. + pr3563412: Passed. + pr3571573: Passed. + pr3582052: Passed. + pr3587570: Passed. + prng: Passed. + ptest001: Passed. + ptest002: Passed. + ptest003: Passed. + ptest004: Passed. + ptest005: Passed. + ptest006: Passed. + ptest007: Passed. + ptest008: Passed. + ptest009: Passed. + ptest010: Passed. + ptest011: Passed. + pullupdown: Passed. + pullupdown2: Passed. + pullupdown3: Passed. + pv_undef_sig_sel: Passed. + qmark: Passed. + qmark1: Passed. + qmark3: Passed. + qmark5: Passed. + qmark6: Passed. + queue: Passed. + queue_stat: Passed. + ram16x1: Passed. + readmemb1: Passed. + readmemb2: Passed. + readmemb3: Passed. + readmemh1: Passed. + readmemh1a: Passed. + readmemh2: Passed. + readmemh3: Passed. + readmemh4: Passed. + readmemh5: Passed - CE. + real: Passed. + real2: Passed. + real3: Passed. + real5: Passed. + real6: Passed. + real7: Passed. + real9: Passed. + real10: Passed. + real11: Passed. + real_assign_deassign: Passed. + real_concat_invalid2: Passed - CE. + real_delay: Passed. + real_force_rel: Passed. + real_invalid_ops: Passed - CE. + real_logical: Passed. + real_reg_force_rel: Passed. + redef_net_error: Passed - CE. + redef_reg_error: Passed - CE. + repeat2: Passed. + repeat_expr_probe: Passed. + repl_zero_wid_fail: Passed - CE. + repl_zero_wid_pass: Passed. + resetall: Passed. + resetall2: Passed. + resolv1: Passed. + rise_fall_decay1: Passed. + rise_fall_delay1: Passed. + rise_fall_delay2: Passed. + rnpmos: Passed. + rnpmos2: Passed. + rop: Passed. + rptconcat: Passed. + rtran: Passed. + rtranif0: Passed. + rtranif1: Passed. + scanf: Passed. + scanf2: Passed. + scanf3: Passed. + scanf4: Passed. + sched1: Passed. + sched2: Passed. + schedule: Passed. + scope1: Passed. + scope2: Passed. + scope2b: Passed - CE. + scope4: Passed. + scope5: Passed. + sdf1: Passed. + sdf2: Passed. + sdf3: Passed. + sdf4: Passed. + sdf5: Passed. + sdf6: Passed. + sdf7: Passed. + sdf8: Passed. + sdf_del_max: Passed. + sdf_del_min: Passed. + sdf_del_typ: Passed. + sdf_esc_id: Passed. + sdw_always1: Passed. + sdw_always2: Passed. + sdw_always3: Passed. + sdw_array: Passed. + sdw_assign: Passed. + sdw_dsbl: Passed. + sdw_force: Passed. + sdw_function1: Passed. + sdw_function2: Passed. + sdw_function3: Passed. + sdw_function4: Passed. + sdw_function5: Passed. + sdw_instmod1: Passed. + sdw_instmod2: Passed. + sdw_int: Passed. + sdw_lvalconcat: Passed. + sdw_param1: Passed. + sdw_param2: Passed. + sdw_release: Passed. + sdw_stmt002: Passed. + sdw_task1: Passed. + sdw_task2: Passed. + select: Passed. + select2: Passed. + select3: Passed. + select4: Passed. + select6: Passed. + select7: Passed. + select8: Passed. + shellho1: Passed. + shift1: Passed. + shift_pad: Passed. + signed2: Passed. + signed3: Passed. + signed11: Passed. + signed_equality: Passed. + sp2: Passed. + specify1: Passed - CO. + specify2: Passed. + specify3: Passed. + specify4: Passed. + specify5: Passed. + specify_01: Passed. + sqrt32: Passed. + sscanf_u: Passed. + sscanf_z: Passed. + stask_parm1: Passed. + stask_parm2: Passed. + stask_sens_null_arg: Passed. + string1: Passed. + string2: Passed. + string3: Passed. + string4: Passed. + string5: Passed. + string7: Passed. + string8: Passed. + string9: Passed. + string10: Passed. + string11: Passed. + string12: Passed. + supply1: Passed. + supply2: Passed. + switch_primitives: Passed. + talu: Passed. + task-scope: Passed. + task3.14A: Passed. + task3.14B: Passed. + task3.14C: Passed. + task3.14D: Passed. + task3.14E: Passed. + task3.14F: Passed. + task_bypath: Passed. + task_inpad: Passed. + task_iotypes: Passed. + task_iotypes2: Passed. + task_mem: Passed. + task_noop: Passed. + task_noop2: Passed - CO. + task_omemw2: Passed. + task_omemw3: Passed - CO. + task_port_size: Passed. + task_scope: Passed. + tern1: Passed. + tern2: Passed - CO. + tern4: Passed. + tern5: Passed. + tern6: Passed. + tern7: Passed. + tern9: Passed. + tern10: Passed. + test_bufif0: Passed. + test_bufif1: Passed. + test_disphob: Passed. + test_extended: Passed. +test_mos_strength_reduction: Passed. + test_nmos: Passed. + test_notif0: Passed. + test_notif1: Passed. + test_pmos: Passed. + test_rnmos: Passed. + test_rpmos: Passed. + test_width: Passed. + time1: Passed. + time2: Passed. + time3: Passed. + time4: Passed. + time5: Passed. + time7: Passed. + time8: Passed. + timeform1: Passed. + timeform2: Passed. + timescale1: Passed. + timescale2: Passed. + timescale3: Passed - CE. + tran: Passed. + tranif0: Passed. + tranif1: Passed. + tran-keeper: Passed. + tri0: Passed. + tri0b: Passed. + tri1: Passed. + tri3: Passed. + triand: Passed. + trior: Passed. + types1: Passed. + udp_bufg: Passed. + udp_bufg2: Passed. + udp_bx: Passed. + udp_delay_fail: Passed - CE. + udp_dff: Passed. + udp_dff_std: Passed. + udp_eval_arg: Passed. + udp_jkff: Passed. + udp_real_delay: Passed. + udp_sched: Passed. + udp_x: Passed. + unary_and: Passed. + unary_lnot1: Passed. + unary_lnot2: Passed. + unary_lnot3: Passed. + unary_minus: Passed. + unary_minus1: Passed. + unary_minus2: Passed. + unary_minus3: Passed. + unary_minus4: Passed. + unary_nand: Passed. + unary_nand2: Passed. + unary_nor: Passed. + unary_nor2: Passed. + unary_not: Passed. + unary_or: Passed. + unary_xnor1: Passed. + unary_xnor2: Passed. + unary_xor: Passed. + uncon_drive: Passed. + undef: Passed. + undef_lval_select: Passed. + undef_lval_select2: Passed. + undef_lval_select3a: Passed. + undef_lval_select3b: Passed - CE. + undef_lval_select3c: Passed - CE. + undef_lval_select4a: Passed. + undef_lval_select4b: Passed - CE. + undef_lval_select4c: Passed - CE. + undef_lval_select5: Passed. + urand_r: Passed. + urand_r2: Passed. + urand_r3: Passed. + uwire: Passed. + uwire2: Passed. + uwire_fail: Passed - CE. + vardly: Passed. + varlsfht: Passed. + varlsfht1: Passed. + varlsfht2: Passed. + varrshft: Passed. + varrshft1: Passed. + varrshft2: Passed. + vcd-dup: Passed. + vector: Passed. + verify_two_var_delays: Passed. + vvp_scalar_value: Passed. + wait1: Passed. + wait2: Passed. + wait3: Passed. + wildsense: Passed. + wildsense2: Passed. + wireadd1: Passed. + wireeq: Passed. + wirege: Passed. + wireland: Passed. + wirele: Passed. + wiremod1: Passed. + wiresl: Passed. + wiresl2: Passed. + wiresr: Passed. + wiresub1: Passed. + wirexor1: Passed. + writememb1: Passed. + writememb2: Passed. + writememh1: Passed. + writememh2: Passed. + xnor_test: Passed. + z1: Passed. + z2: Passed. + zero_repl: Passed. + zero_repl_fail: Passed - CE. + cmpi: Passed. + scaled_real: Passed. + test_vams_math: Passed. + value_range1: Passed. + value_range2: Passed. + value_range3: Passed - CE. + always_comb: Passed. + always_comb_fail: Passed - CE. + always_comb_fail3: Passed - CE. + always_comb_fail4: Passed - CE. + always_comb_no_sens: Passed. + always_comb_trig: Passed. + always_ff: Passed. + always_ff_fail: Passed - CE. + always_ff_fail2: Passed - CE. + always_ff_fail3: Passed - CE. + always_ff_fail4: Passed - CE. + always_ff_no_sens: Passed - CE. + always_latch: Passed. + always_latch_fail: Passed - CE. + always_latch_fail3: Passed - CE. + always_latch_fail4: Passed - CE. + always_latch_no_sens: Passed - CE. + always_latch_trig: Passed. + array_size: Passed. + array_packed: Passed. + assign_op_concat: Passed. + br921: Passed. + br956: Passed. + br973: Passed. + br974a: Passed. + br974b: Passed. + br974c: Passed. + br975: Passed - CE. + br979: Passed. + br991b: Passed - CE. + br1027b: Passed. + br1027d: Passed. + br1027f: Passed. + br_gh4a: Passed. + br_gh72a: Passed. + br_gh72b: Passed. + br_gh72b_fail: Passed - CE. + br_gh104b: Passed. + br_gh105a: Passed. + br_gh105b: Passed. + br_gh112a: Passed. + br_gh112b: Passed. + br_gh130a: Passed - CE. + br_gh220: Passed. + br_gh224: Passed. + br_gh226: Passed. + br_gh243: Passed. + br_gh265: Passed - CE. + br_gh277b: Passed. + br_gh280: Passed. + br_gh289a: Passed. + br_gh289c: Passed. + br_gh289d: Passed. + br_gh361: Passed. + br_gh366: Passed. + br_gh374: Passed. + br_gh386a: Passed. + br_gh386b: Passed. + br_gh386c: Passed - CE. + br_gh411: Passed. + br_gh418: Passed. + br_gh440: Passed - CE. + br_gh478: Passed. + br_gh498: Passed. + br_gh508a: Passed. + br_gh527: Passed. + br_gh530: Passed - CO. + br_gh553: Passed. + br_ml20180227: Passed - CE. + br_ml20181012a: Passed - CE. + br_ml20181012b: Passed - CE. + br_ml20181012c: Passed - CE. + br_ml20181012d: Passed - CE. + cfunc_assign_op_mixed: Passed. + cfunc_assign_op_pv: Passed. + cfunc_assign_op_real: Passed. + clkgen_bit: Passed. + clkgen_logic: Passed. + clkgen_net: Passed. + clkgen_reg: Passed. + display_bug: Passed. + edge: Passed. + enum_base_range: Passed. + enum_dims_invalid: Passed - CE. + enum_test2: Passed. + enum_test3: Passed - CE. + enum_test4: Passed. + enum_test5: Passed - CE. + enum_test6: Passed - CE. + enum_test7: Passed - CE. + enum_test8: Passed. + escaped_macro_name: Passed. + extra_semicolon: Passed. + fileline: Passed. + fileline2: Passed. + function10: Passed - CO. + function11: Passed - CE. + implicit-port1: Passed. + implicit-port2: Passed - CE. + implicit-port3: Passed - CE. + implicit-port4: Passed. + implicit-port5: Passed. + implicit-port6: Passed - CE. + implicit-port7: Passed. + l_equiv_const: Passed. + line_directive: Passed. + localparam_query: Passed. + localparam_type2: Passed. + named_begin: Passed. + named_begin_fail: Passed - CE. + named_fork: Passed. + named_fork_fail: Passed - CE. + parameter_type2: Passed. + parpkg_test: Passed. + parpkg_test2: Passed. + parpkg_test3: Passed. + part_sel_port: Passed. + pr3366114: Passed. + pr3366217a: Passed - CE. + pr3366217b: Passed - CE. + pr3366217c: Passed - CE. + pr3366217d: Passed - CE. + pr3366217g: Passed - CE. + pr3515542: Passed - CE. + pr3534333: Passed. + pr3576165: Passed. + program3b: Passed - CE. + program5a: Passed - CE. + program5b: Passed - CE. + program_hello2: Passed - CE. + scalar_vector: Passed. + size_cast: Passed. + size_cast2: Passed. + struct1: Passed. + struct2: Passed. + struct3: Passed. + struct3b: Passed. + struct4: Passed. + struct5: Passed. + struct6: Passed. + struct7: Passed. + struct8: Passed. + struct9: Passed. + struct_packed_sysfunct: Passed. + struct_packed_write_read2: Passed. + sv-constants: Passed. + sv_default_port_value1: Passed. + sv_default_port_value2: Passed. + sv_default_port_value3: Passed - CE. + sv_end_label_fail: Passed - CE. + sv_end_labels: Passed. + sv_end_labels_bad: Passed - CE. + sv_enum1: Passed. + sv_macro2: Passed. + sv_macro3a: Passed. + sv_macro3b: Passed. + sv_package3: Passed. + sv_package4: Passed. + sv_param_port_list: Passed. + sv_port_default12: Passed. + sv_port_default13: Passed - CE. + sv_port_default14: Passed - CE. + sv_timeunit_prec1: Passed. + sv_timeunit_prec2: Passed. + sv_timeunit_prec3a: Passed. + sv_timeunit_prec3b: Passed. + sv_timeunit_prec3c: Passed. + sv_timeunit_prec3d: Passed. + sv_timeunit_prec4a: Passed. + sv_timeunit_prec4b: Passed. + sv_timeunit_prec_fail1: Passed - CE. + sv_timeunit_prec_fail2: Passed - CE. + sv_typedef_scope: Passed. + sv_union1: Passed. + sv_union1b: Passed. + sv_union2: Passed. + sv_union2b: Passed. + sv_union3: Passed. + sv_union3b: Passed. + sv_union4b: Passed. + sv_unit1b: Passed. + sv_unit1c: Passed. + sv_uwire3: Passed. + sv_uwire4: Passed. + sv_wildcard_import1: Passed. + sv_wildcard_import2: Passed. + sv_wildcard_import3: Passed. + sv_wildcard_import4: Passed - CE. + sv_wildcard_import5: Passed - CE. + sv_wildcard_import6: Passed. + sv_wildcard_import7: Passed. + task_init_assign: Passed. + task_scope2: Passed. + timeliteral: Passed. + undef_lval_select_SV: Passed. + packed_dims_invalid_class: Passed - CE. + packed_dims_invalid_module: Passed - CE. + wild_cmp_const: Passed. + gh161a: Passed. + gh161b: Passed. + br_gh307: Passed. + br_gh390a: Passed - CE. + br_gh451: Passed. + br986: Passed. + br987: Passed. + ivlh_event: Passed. + ivlh_rising_falling: Passed. + test_dec2to4: Passed. + test_mux2to1: Passed. + test_signal_init_assign: Passed. + test_timebase: Passed. + test_when_else: Passed. + vhdl_and104_stdlogic: Passed. + vhdl_and23_bit: Passed. + vhdl_and_gate: Passed. + vhdl_andg_bit: Passed. + vhdl_andg_stdlogic: Passed. + vhdl_array_of_array: Passed. + vhdl_case_multi: Passed. + vhdl_concat: Passed. + vhdl_const_package: Passed. + vhdl_const_array: Passed. + vhdl_eval_cond: Passed. + vhdl_expr1: Passed. + vhdl_generic_eval: Passed. + vhdl_fa4_test1: Passed. + vhdl_fa4_test2: Passed. + vhdl_fa4_test3: Passed. + vhdl_fa4_test4: Passed. + vhdl_generic_default: Passed. + vhdl_init: Passed. + vhdl_inout: Passed. + vhdl_labeled_assign: Passed. + vhdl_lfcr: Passed. + vhdl_logic: Passed. + vhdl_multidim_array: ==> Failed - running iverilog. + vhdl_nand104_stdlogic: Passed. + vhdl_nand23_bit: Passed. + vhdl_nandg_bit: Passed. + vhdl_nandg_stdlogic: Passed. + vhdl_nor104_stdlogic: Passed. + vhdl_nor23_bit: Passed. + vhdl_norg_bit: Passed. + vhdl_norg_stdlogic: Passed. + vhdl_not104_stdlogic: Passed. + vhdl_not23_bit: Passed. + vhdl_notg_bit: Passed. + vhdl_notg_stdlogic: Passed. + vhdl_now: Passed. + vhdl_or104_stdlogic: Passed. + vhdl_or23_bit: Passed. + vhdl_org_bit: Passed. + vhdl_org_stdlogic: Passed. + vhdl_rand23_bit: Passed. + vhdl_record_elab: Passed. + vhdl_reduce: Passed. + vhdl_sa1_test1: Passed. + vhdl_sa1_test2: Passed. + vhdl_sa1_test3: Passed. + vhdl_selected: Passed. + vhdl_signals: Passed. + vhdl_struct_array: Passed. + vhdl_string: Passed. + vhdl_test1: Passed. + vhdl_test2: Passed. + vhdl_test4: Passed. + vhdl_test5: Passed. + vhdl_test6: Passed. + vhdl_test7: Passed. + vhdl_time: Passed. + vhdl_uadd23_bit: Passed. + vhdl_uadd23_stdlogic: Passed. + vhdl_udiv23_bit: Passed. + vhdl_udiv23_stdlogic: Passed. + vhdl_umul23_bit: Passed. + vhdl_umul23_stdlogic: Passed. + vhdl_usub23_bit: Passed. + vhdl_usub23_stdlogic: Passed. + vhdl_wait: Passed. + vhdl_xnor104_stdlogic: Passed. + vhdl_xnor23_bit: Passed. + vhdl_xnorg_bit: Passed. + vhdl_xnorg_stdlogic: Passed. + vhdl_xor23_bit: Passed. + vhdl_xorg_bit: Passed. + vhdl_xorg_stdlogic: Passed. + work7: Passed. + work7b: Passed. + basicexpr2: Passed. + basicexpr3: Passed. + basicexpr4: Passed. + basiclatch: Passed. + basicreg: Passed. + blocksynth1: Passed. + blocksynth2: Passed. + blocksynth3: Passed. + br995: Passed - CE. + br_gh115: Passed. + br_gh306a: Passed - CE. + br_gh306b: Passed - CE. + case3: Passed. + case4: Passed. + case5: Passed. + case5-syn-fail: Passed - CE. + case6: Passed. + case7: Passed. + case_wo_default: Passed. + casesynth4: Passed. + casesynth5: Passed. + casesynth8: Passed - CE. + casesynth9: Passed. + condit1: Passed. + dffsynth2: Passed. + dffsynth3: Passed. + dffsynth4: Passed. + dffsynth5: Passed. + dffsynth8: Passed - CE. + ff_dual_enable: Passed. + for_loop_synth: Passed. + for_loop_synth2: Passed. + if_part_no_else: Passed. + if_part_no_else2: Passed. + inside_synth: Passed. + inside_synth3: Passed. + land5: Passed. + lcatsynth: Passed. + memsynth8: Passed. + not_a_latch1: Passed. + not_a_latch2: Passed. + pr519: Passed. + ssetclr1: Passed. + ssetclr2: Passed. + ssetclr3: Passed. + synth_if_no_else: Passed. +============================================================================ +Test results: + Total=2559, Passed=2520, Failed=2, Not Implemented=3, Expected Fail=34 diff --git a/ivtest/src/alloca.h b/ivtest/src/alloca.h new file mode 100644 index 000000000..0421a57e9 --- /dev/null +++ b/ivtest/src/alloca.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) Tony Bybell 1999-2000. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#ifndef VCD_ALLOCA_H +#define VCD_ALLOCA_H +#include + +/* + * if your system really doesn't have alloca() at all, + * you can force functionality by using malloc + * instead. but note that you're going to have some + * memory leaks because of it. you have been warned. + */ + +#ifdef _MSC_VER + #define alloca _alloca +#endif + +#ifndef __sun__ + #ifndef alloca + #define alloca __alloca + #endif +#else + #include +#endif + +#define wave_alloca alloca + +#endif diff --git a/ivtest/src/analyzer.h b/ivtest/src/analyzer.h new file mode 100644 index 000000000..0119ec0fa --- /dev/null +++ b/ivtest/src/analyzer.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) Tony Bybell 1999-2000. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#ifndef VCD_ANALYZER_H +#define VCD_ANALYZER_H + +#include +#include +#include "alloca.h" +#include "debug.h" + + +typedef struct Node *nptr; +typedef struct HistEnt *hptr; +typedef struct Bits *bptr; +typedef struct VectorEnt *vptr; +typedef struct BitVector *bvptr; + +typedef unsigned long Ulong; +typedef unsigned int Uint; + + +typedef struct HistEnt +{ +hptr next; /* next transition in history */ +TimeType time; /* time of transition */ +unsigned char flags; /* so far only set on glitch/real condition */ + +union + { + unsigned char val; /* value: "0XZ1"[val] */ + char *vector; /* pointer to a whole vector */ + } v; + +} HistEnt; + +enum HistEntFlagBits +{ HIST_GLITCH_B, HIST_REAL_B, HIST_STRING_B +}; + +#define HIST_GLITCH (1<time; + +if((obj<=key)&&(obj>max_compare_time)) + { + max_compare_time=obj; + max_compare_pos=cpos; + max_compare_index=(hptr *)s2; + } + +delta=key-obj; +if(delta<0) rv=-1; +else if(delta>0) rv=1; +else rv=0; + +return(rv); +} + +hptr bsearch_node(nptr n, TimeType key) +{ +max_compare_time=-2; max_compare_pos=NULL; max_compare_index=NULL; + +bsearch(&key, n->harray, n->numhist, sizeof(hptr), compar_histent); +if((!max_compare_pos)||(max_compare_time<0)) + { + max_compare_pos=n->harray[1]; /* aix bsearch fix */ + max_compare_index=&(n->harray[1]); + } + +return(max_compare_pos); +} + +/*****************************************************************************************/ + +static int compar_facs(const void *key, const void *v2) +{ +struct symbol *s2; +int rc; + +s2=*((struct symbol **)v2); +rc=sigcmp((char *)key,s2->name); +return(rc); +} + +struct symbol *bsearch_facs(struct globals *obj, char *ascii) +{ +struct symbol **rc; + +if ((!ascii)||(!strlen(ascii))) return(NULL); +rc=(struct symbol **)bsearch(ascii, obj->facs, obj->numfacs, sizeof(struct symbol *), compar_facs); +if(rc) return(*rc); else return(NULL); +} diff --git a/ivtest/src/bsearch.h b/ivtest/src/bsearch.h new file mode 100644 index 000000000..8f7eec8c8 --- /dev/null +++ b/ivtest/src/bsearch.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) Tony Bybell 1999-2000. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#ifndef VCD_BSEARCH_NODES_VECTORS_H +#define VCD_BSEARCH_NODES_VECTORS_H + +#include "globals.h" + +hptr bsearch_node(nptr n, TimeType key); +vptr bsearch_vector(bvptr b, TimeType key); +char *bsearch_trunc(char *ascii, int maxlen); +struct symbol *bsearch_facs(struct globals *obj, char *ascii); + +#endif diff --git a/ivtest/src/debug.c b/ivtest/src/debug.c new file mode 100644 index 000000000..7465b7811 --- /dev/null +++ b/ivtest/src/debug.c @@ -0,0 +1,214 @@ +/* + * Copyright (c) Tony Bybell 1999-2000. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + + +/* + * debug.c 01feb99ajb + * malloc debugs added on 13jul99ajb + */ +#include "debug.h" + +#define DEB_FAIL 333 + +#undef free_2 + +#ifdef DEBUG_MALLOC /* normally this should be undefined..this is *only* for finding stray allocations/frees */ + static struct memchunk *mem=NULL; + static size_t mem_total=0; + static int mem_chunks=0; + + static void mem_addnode(void *ptr, size_t size) + { + struct memchunk *m; + + m=(struct memchunk *)malloc(sizeof(struct memchunk)); + m->ptr=ptr; + m->size=size; + m->next=mem; + + mem=m; + mem_total+=size; + mem_chunks++; + + fprintf(stderr,"mem_addnode: TC:%05d TOT:%010d PNT:%010p LEN:+%d\n",mem_chunks,mem_total,ptr,size); + } + + static void mem_freenode(void *ptr) + { + struct memchunk *m, *mprev=NULL; + m=mem; + + while(m) + { + if(m->ptr==ptr) + { + if(mprev) + { + mprev->next=m->next; + } + else + { + mem=m->next; + } + + mem_total=mem_total-m->size; + mem_chunks--; + fprintf(stderr,"mem_freenode: TC:%05d TOT:%010d PNT:%010p LEN:-%d\n",mem_chunks,mem_total,ptr,m->size); + free(m); + return; + } + mprev=m; + m=m->next; + } + + fprintf(stderr,"mem_freenode: PNT:%010p *INVALID*\n",ptr); + sleep(1); + } +#endif + + +/* + * wrapped malloc family... + */ +void *malloc_2(size_t size) +{ +void *ret; +ret=malloc(size); +if(ret) + { + DEBUG_M(mem_addnode(ret,size)); + return(ret); + } + else + { + fprintf(stderr, "FATAL ERROR : Out of memory, sorry.\n"); + exit(DEB_FAIL); + } +} + +void *realloc_2(void *ptr, size_t size) +{ +void *ret; +ret=realloc(ptr, size); +if(ret) + { + DEBUG_M(mem_freenode(ptr)); + DEBUG_M(mem_addnode(ret,size)); + return(ret); + } + else + { + fprintf(stderr, "FATAL ERROR : Out of memory, sorry.\n"); + exit(DEB_FAIL); + } +} + +void *calloc_2(size_t nmemb, size_t size) +{ +void *ret; +ret=calloc(nmemb, size); +if(ret) + { + DEBUG_M(mem_addnode(ret, nmemb*size)); + return(ret); + } + else + { + fprintf(stderr, "FATAL ERROR: Out of memory, sorry.\n"); + exit(DEB_FAIL); + } +} + + +#ifdef DEBUG_MALLOC_LINES +void free_2(void *ptr, char *filename, int lineno) +{ +if(ptr) + { + DEBUG_M(mem_freenode(ptr)); + free(ptr); + } + else + { + fprintf(stderr, "WARNING: Attempt to free NULL pointer caught: \"%s\", line %d.\n", filename, lineno); + } +} +#else +void free_2(void *ptr) +{ +if(ptr) + { + DEBUG_M(mem_freenode(ptr)); + free(ptr); + } + else + { + fprintf(stderr, "WARNING: Attempt to free NULL pointer caught.\n"); + } +} +#endif + + +/* + * atoi 64-bit version.. + * y/on default to '1' + * n/nonnum default to '0' + */ +char *atoi_cont_ptr=NULL; + +TimeType atoi_64(char *str) +{ +TimeType val=0; +unsigned char ch, nflag=0; + +atoi_cont_ptr=NULL; + +switch(*str) + { + case 'y': + case 'Y': + return(LLDescriptor(1)); + + case 'o': + case 'O': + str++; + ch=*str; + if((ch=='n')||(ch=='N')) + return(LLDescriptor(1)); + else return(LLDescriptor(0)); + + case 'n': + case 'N': + return(LLDescriptor(0)); + break; + + default: + break; + } + +while((ch=*(str++))) + { + if((ch>='0')&&(ch<='9')) + { + val=(val*10+(ch&15)); + } + else + if((ch=='-')&&(val==0)&&(!nflag)) + { + nflag=1; + } + else + if(val) + { + atoi_cont_ptr=str-1; + break; + } + } +return(nflag?(-val):val); +} diff --git a/ivtest/src/debug.h b/ivtest/src/debug.h new file mode 100644 index 000000000..90e8cbdef --- /dev/null +++ b/ivtest/src/debug.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) Tony Bybell 1999-2000 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#ifndef VCD_DEBUG_H +#define VCD_DEBUG_H + +#include +#include +#include + +struct memchunk +{ +struct memchunk *next; +void *ptr; +size_t size; +}; + + +/* + * If you have problems viewing traces (mangled timevalues), + * make sure that you use longs rather than the glib 64-bit + * types... + */ +#ifdef G_HAVE_GINT64 + typedef gint64 TimeType; + typedef guint64 UTimeType; + + #ifndef _MSC_VER + #define LLDescriptor(x) x##LL + #define ULLDescriptor(x) x##ULL + #define TTFormat "%lld" + #define UTTFormat "%llu" + #else + #define LLDescriptor(x) x##i64 + #define ULLDescriptor(x) x##i64 + #define TTFormat "%I64d" + #define UTTFormat "%I64u" + #endif + + #define WAVE_MINZOOM (LLDescriptor(-4000000000)) +#else + typedef long TimeType; + typedef unsigned long UTimeType; + + #define TTFormat "%d" + #define UTTFormat "%u" + + #define LLDescriptor(x) x + #define ULLDescriptor(x) x + + #define WAVE_MINZOOM (LLDescriptor(-20000000)) +#endif + +#ifdef DEBUG_PRINTF +#define DEBUG(x) x +#else +#define DEBUG(x) +#endif + +#ifdef DEBUG_MALLOC +#define DEBUG_M(x) x +#else +#define DEBUG_M(x) +#endif + + +#ifdef DEBUG_MALLOC_LINES +void free_2(void *ptr, char *filename, int lineno); +#define free_2(x) free_2((x),__FILE__,__LINE__) +#else +void free_2(void *ptr); +#endif + + +void *malloc_2(size_t size); +void *realloc_2(void *ptr, size_t size); +void *calloc_2(size_t nmemb, size_t size); + +TimeType atoi_64(char *str); +extern char *atoi_cont_ptr; /* for unformat_time()'s parse continue for the time unit */ + +#undef WAVE_USE_SIGCMP_INFINITE_PRECISION /* define this for slow sigcmp with infinite digit accuracy */ +#define WAVE_OPT_SKIP 1 /* make larger for more accel on traces */ + +#endif diff --git a/ivtest/src/globals.c b/ivtest/src/globals.c new file mode 100644 index 000000000..fd036836d --- /dev/null +++ b/ivtest/src/globals.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) Tony Bybell 1999-2000. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#include "globals.h" +#include "misc.h" + +struct globals *make_vcd_class(void) +{ +struct globals *g; + +g=(struct globals *)calloc_2(1, sizeof(struct globals)); + +g->sym=NULL; +g->facs=NULL; +g->facs_are_sorted=0; + +g->numfacs=0; +g->regions=0; +g->longestname=0; + +g->firstnode=NULL; +g->curnode=NULL; + +g->hier_delimeter='.'; +g->autocoalesce=1; + +g->vcd_explicit_zero_subscripts=-1; +g->convert_to_reals=0; +g->atomic_vectors=1; + +g->vcd_handle=NULL; +g->vcd_is_compressed=0; + +g->vcdbyteno=0; +g->header_over=0; +g->dumping_off=0; +g->start_time=-1; +g->end_time=-1; +g->current_time=-1; +g->time_scale=1; + +g->count_glitches=0; +g->num_glitches=0; +g->num_glitch_regions=0; + +g->vcd_hier_delimeter[0]=0; +g->vcd_hier_delimeter[1]=0; + +g->pv=NULL; +g->rootv=NULL; + +g->slistroot=NULL; +g->slistcurr=NULL; +g->slisthier=NULL; +g->slisthier_len=0; + +g->T_MAX_STR=1024; +g->yytext=NULL; +g->yylen=0; +g->yylen_cache=0; + +g->vcdsymroot=NULL; +g->vcdsymcurr=NULL; +g->sorted=NULL; + +g->numsyms=0; + +g->he_curr=NULL; +g->he_fini=NULL; + +g->vcdbuf=NULL; +g->vst=NULL; +g->vend=NULL; + +g->varsplit=NULL; +g->vsplitcurr=NULL; + +g->var_prevch=0; + +g->currenttime=0; +g->max_time=0; +g->min_time=-1; +g->time_dimension='n'; + +g->sym=(struct symbol **)calloc_2(SYMPRIME,sizeof(struct symbol *)); + +return(g); +} diff --git a/ivtest/src/globals.h b/ivtest/src/globals.h new file mode 100644 index 000000000..3f4ce1c54 --- /dev/null +++ b/ivtest/src/globals.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) Tony Bybell 1999-2000. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#ifndef WAVE_GLOBALS_H +#define WAVE_GLOBALS_H + +#include +#include +#include +#include +#include "alloca.h" +#include "debug.h" + +struct globals +{ +struct symbol **sym; +struct symbol **facs; +char facs_are_sorted; + +int numfacs; +int regions; +int longestname; + +struct symbol *firstnode; /* 1st sym in aet */ +struct symbol *curnode; /* current loaded sym in aet loader */ + +char hier_delimeter; +char autocoalesce; + +int vcd_explicit_zero_subscripts; /* 0=yes, -1=no */ +char convert_to_reals; +char atomic_vectors; + +FILE *vcd_handle; +char vcd_is_compressed; + +int vcdbyteno; /* really should be size_t, but this is only used for debugging mangled traces */ +int header_over; +int dumping_off; +TimeType start_time; +TimeType end_time; +TimeType current_time; +TimeType time_scale; /* multiplier is 1, 10, 100 */ + +int count_glitches; /* set to 1 if we want to enable glitch code */ +int num_glitches; +int num_glitch_regions; + +char vcd_hier_delimeter[2]; /* fill in after rc reading code */ + +struct vcdsymbol *pv, *rootv; + +struct slist *slistroot, *slistcurr; +char *slisthier; +int slisthier_len; + +int T_MAX_STR; /* was originally a const..now it reallocs */ +char *yytext; +int yylen, yylen_cache; + +struct vcdsymbol *vcdsymroot, *vcdsymcurr; +struct vcdsymbol **sorted; + +int numsyms; + +struct HistEnt *he_curr, *he_fini; + +char *vcdbuf, *vst, *vend; + +char *varsplit, *vsplitcurr; + +int var_prevch; + +TimeType currenttime, max_time, min_time; +char time_dimension; +}; + + +struct globals *make_vcd_class(void); + + +#endif diff --git a/ivtest/src/main.c b/ivtest/src/main.c new file mode 100644 index 000000000..13a0c8726 --- /dev/null +++ b/ivtest/src/main.c @@ -0,0 +1,212 @@ +/* + * Copyright (c) Tony Bybell 1999-2000 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + + +/* + * vcdiff.c 12apr00 ajb + */ +#include +#include "misc.h" +#include "globals.h" +#include "vcd.h" + +int compare_symbols(TimeType max0, TimeType max1, struct symbol *s0, struct symbol *s1) +{ +hptr h0, h1; +TimeType t0, t1; +int rc=0; + +h0=&(s0->n->head); +h1=&(s1->n->head); + +if(!s0->n->ext) + { + /* bit case */ + while((h0)&&(h1)) + { + t0=h0->time; + t1=h1->time; + if((t0>max0)||(t1>max0)||(t0>max1)||(t1>max1)) break; + + if (h0->v.val!=h1->v.val) + { + fprintf(stdout, "*** '%s' value mismatch: "TTFormat"='%c' vs "TTFormat"='%c'\n", s0->name, h0->time, "0xz1"[h0->v.val], h1->time, "0xz1"[h1->v.val]); + rc+=1; + } + + if((h0->next)&&(h1->next)) + { + if(t0==t1) + { + h0=h0->next; + h1=h1->next; + } + else + if(t0next; + } + else + { + h1=h1->next; + } + continue; + } + else + { + return(rc); + } + } + } + else + { + /* vec case */ + while((h0)&&(h1)) + { + t0=h0->time; + t1=h1->time; + if((t0>max0)||(t1>max0)||(t0>max1)||(t1>max1)) break; + + if ((h0->time>=0)&&(h1->time>=0)) + if ((h0->flags&(HIST_REAL|HIST_STRING))==(h1->flags&(HIST_REAL|HIST_STRING))) + { + if((h0->flags&HIST_REAL)&&(!(h0->flags&HIST_STRING))) + { + if(*((double *)h0->v.vector)!=*((double *)h1->v.vector)) + { + fprintf(stdout, "*** '%s' value mismatch: "TTFormat"='%f' vs "TTFormat"='%f'\n", s0->name, h0->time, *((double *)h0->v.vector), h1->time, *((double *)h1->v.vector)); + rc+=1; + } + } + else + { + if((h0->v.vector)&&(h1->v.vector)) + { + if(strcmp(h0->v.vector, h1->v.vector)) + { + fprintf(stdout, "*** '%s' value mismatch: "TTFormat"='%s' vs "TTFormat"='%s'\n", s0->name, h0->time, h0->v.vector, h1->time, h1->v.vector); + rc+=1; + } + } + } + } + + if((h0->next)&&(h1->next)) + { + if(t0==t1) + { + h0=h0->next; + h1=h1->next; + } + else + if(t0next; + } + else + { + h1=h1->next; + } + continue; + } + else + { + return(rc); + } + } + } + +return(rc); +} + + +/* + * the meat and potatoes... + */ +int main(int argc, char **argv) +{ +int i, j; +struct globals *v[2]; +int warnings=0; + +if(argc<3) + { + fprintf(stderr, "Usage\n-----\n"); + fprintf(stderr, "%s file1 file2\n\n",argv[0]); + fprintf(stderr,"Using -vcd as a filename accepts input from stdin.\n"); + exit(VCD_FAIL); + } + + +if((!strcmp("-vcd",argv[1]))&&(!strcmp("-vcd",argv[2]))) + { + fprintf(stderr, "Can only accept stdin input for one file, exiting\n"); + exit(VCD_FAIL); + } + +for(i=0;i<2;i++) + { + v[i]=make_vcd_class(); + vcd_main(v[i],argv[i+1]); + fprintf(stdout,"\n"); + } + +if((v[0]->numfacs)!=(v[1]->numfacs)) + { + fprintf(stdout, "*** Number of symbols differ: %d vs %d.\n\n",v[0]->numfacs, v[1]->numfacs); + warnings++; + } + +for(i=0;i<2;i++) + { + for(j=0;jnumfacs;j++) + { + struct symbol *as; + + as=symfind(v[1-i],v[i]->facs[j]->name); + if(!as) + { + fprintf(stdout, "*** '%s' not found in '%s'\n",v[i]->facs[j]->name, argv[2-i]); + warnings++; + } + else + { + struct ExtNode *en0, *en1; + en0=v[i]->facs[j]->n->ext; + en1=as->n->ext; + + if( ((!en0)&&(!en1)) || ( ((en0)&&(en1)) && (en0->msi==en1->msi) && (en0->lsi==en1->lsi) ) ) + { + v[i]->facs[j]->altsym=as; + } + else + { + fprintf(stdout, "*** '%s' size/direction mismatch\n", v[i]->facs[j]->name); + warnings++; + } + } + } + } + + +for(j=0;jnumfacs;j++) + { + struct symbol *s, *as; + + s=v[0]->facs[j]; + as=s->altsym; + if(as) + { + warnings+=compare_symbols(v[0]->max_time, v[1]->max_time, s, as); + } + } + +printf("\nEncountered %d warnings, exiting.\n",warnings); +exit(warnings?VCD_FAIL:0); +} diff --git a/ivtest/src/misc.c b/ivtest/src/misc.c new file mode 100644 index 000000000..7ce61f606 --- /dev/null +++ b/ivtest/src/misc.c @@ -0,0 +1,252 @@ +/* + * Copyright (c) Tony Bybell 1999-2000. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#include "misc.h" +#include "bsearch.h" + + +/* + * Generic hash function for symbol names... + */ +int hash(char *s) +{ +char *p; +unsigned int h=0, g; +for(p=s;*p;p++) + { + h=(h<<4)+(*p); + if((g=h&0xf0000000)) + { + h=h^(g>>24); + h=h^g; + } + } +return(h%SYMPRIME); +} + + +/* + * add symbol to table. no duplicate checking + * is necessary as aet's are "correct." + */ +struct symbol *symadd(struct globals *obj, char *name, int hv) +{ +struct symbol *s; + +s=(struct symbol *)calloc_2(1,sizeof(struct symbol)); +strcpy(s->name=(char *)malloc_2(strlen(name)+1),name); +s->next=obj->sym[hv]; +obj->sym[hv]=s; +return(s); +} + + +/* + * find a slot already in the table... + */ +struct symbol *symfind(struct globals *obj, char *s) +{ +int hv; +struct symbol *temp; + +if(!obj->facs_are_sorted) + { + hv=hash(s); + if(!(temp=obj->sym[hv])) return(NULL); /* no hash entry, add here wanted to add */ + + while(temp) + { + if(!strcmp(temp->name,s)) + { + return(temp); /* in table already */ + } + if(!temp->next) break; + temp=temp->next; + } + + return(NULL); /* not found, add here if you want to add*/ + } + else /* no sense hashing if the facs table is built */ + { + DEBUG(printf("BSEARCH: %s\n",s)); + return(bsearch_facs(obj, s)); + } +} + + +/* + * compares two facilities a la strcmp but preserves + * numbers for comparisons + * + * there are two flavors..the slow and accurate to any + * arbitrary number of digits version (first) and the + * fast one good to 2**31-1. we default to the faster + * version since there's probably no real need to + * process ints larger than two billion anyway... + */ + +#ifdef WAVE_USE_SIGCMP_INFINITE_PRECISION +int sigcmp(char *s1, char *s2) +{ +char *n1, *n2; +unsigned char c1, c2; +int len1, len2; + +for(;;) + { + c1=(unsigned char)*s1; + c2=(unsigned char)*s2; + + if((c1==0)&&(c2==0)) return(0); + if((c1>='0')&&(c1<='9')&&(c2>='0')&&(c2<='9')) + { + n1=s1; n2=s2; + len1=len2=0; + + do { + len1++; + c1=(unsigned char)*(n1++); + } while((c1>='0')&&(c1<='9')); + if(!c1) n1--; + + do { + len2++; + c2=(unsigned char)*(n2++); + } while((c2>='0')&&(c2<='9')); + if(!c2) n2--; + + do { + if(len1==len2) + { + c1=(unsigned char)*(s1++); + len1--; + c2=(unsigned char)*(s2++); + len2--; + } + else + if(len1='0')&&(c1>='0')) + { + u1=(int)(c1&15); + u2=(int)(c2&15); + + while(((c2=(unsigned char)*s2)>='0')&&(c2<='9')) + { + u2*=10; + u2+=(unsigned int)(c2&15); + s2++; + } + + while(((c2=(unsigned char)*s1)>='0')&&(c2<='9')) + { + u1*=10; + u1+=(unsigned int)(c2&15); + s1++; + } + + if(u1==u2) continue; + else return((int)u1-(int)u2); + } + else + { + if(c1!=c2) return((int)c1-(int)c2); + } + } +} +#endif + + +/* + * Quicksort algorithm from p154 of + * "Introduction to Algorithms" by Cormen, Leiserson, and Rivest. + * 05-jul-97bsi + */ + +int partition(struct symbol **a, int p, int r) +{ +struct symbol *x, *t; +int i,j; + +x=a[p]; +i=p-1; +j=r+1; + +while(1) + { + do + { + j--; + } while(sigcmp(a[j]->name,x->name)>0); + + do { + i++; + } while(sigcmp(a[i]->name,x->name)<0); + + if(i +#include +#include +#include +#include "alloca.h" +#include "analyzer.h" +#include "debug.h" +#include "globals.h" + +#define SYMPRIME 4093 +#define WAVE_DECOMPRESSOR "gzip -cd " /* zcat alone doesn't cut it for AIX */ + +struct symbol +{ +struct symbol *altsym; /* points to sym in alt vcd file */ + +struct symbol *nextinaet;/* for aet node chaining */ +struct HistEnt *h; /* points to previous one */ + +struct symbol *vec_root, *vec_chain; + +struct symbol *next; /* for hash chain */ +char *name; + +struct Node *n; +}; + + +struct symbol *symfind(struct globals *, char *); +struct symbol *symadd(struct globals *, char *, int); +int hash(char *s); + +int sigcmp(char *, char *); +void quicksort(struct symbol **, int, int); + + +extern struct symbol **sym, **facs; +extern char facs_are_sorted; +extern int numfacs; +extern int regions; +extern struct symbol *firstnode; +extern struct symbol *curnode; +extern int longestname; +extern char hier_delimeter; + +#endif diff --git a/ivtest/src/vcd.c b/ivtest/src/vcd.c new file mode 100644 index 000000000..831a5408e --- /dev/null +++ b/ivtest/src/vcd.c @@ -0,0 +1,1985 @@ +/* + * Copyright (c) Tony Bybell 1999-2000. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + + +/* + * vcd.c 23jan99ajb + * evcd parts 29jun99ajb + * profiler optimizations 15jul99ajb + * more profiler optimizations 25jan00ajb + * finsim parameter fix 26jan00ajb + * vector rechaining code 03apr00ajb + * multiple var section code 06apr00ajb + * stripped from gtkwave 09apr00ajb + */ +#include "vcd.h" + +#undef VCD_BSEARCH_IS_PERFECT /* bsearch is imperfect under linux, but OK under AIX */ + +/******************************************************************/ + +static void add_histent(struct globals *obj, TimeType time, struct Node *n, char ch, int regadd, char *vector); +static void add_tail_histents(struct globals *obj); +static void vcd_build_symbols(struct globals *obj); +static void vcd_cleanup(struct globals *obj); +static void evcd_strcpy(char *dst, char *src); + +/******************************************************************/ + +enum Tokens { T_VAR, T_END, T_SCOPE, T_UPSCOPE, + T_COMMENT, T_DATE, T_DUMPALL, T_DUMPOFF, T_DUMPON, + T_DUMPVARS, T_ENDDEFINITIONS, + T_DUMPPORTS, T_DUMPPORTSOFF, T_DUMPPORTSON, T_DUMPPORTSALL, + T_TIMESCALE, T_VERSION, T_VCDCLOSE, + T_EOF, T_STRING, T_UNKNOWN_KEY }; + +char *tokens[]={ "var", "end", "scope", "upscope", + "comment", "date", "dumpall", "dumpoff", "dumpon", + "dumpvars", "enddefinitions", + "dumpports", "dumpportsoff", "dumpportson", "dumpportsall", + "timescale", "version", "vcdclose", + "", "", "" }; + +#define NUM_TOKENS 18 + +#define T_GET(x) tok=get_token(x);if((tok==T_END)||(tok==T_EOF))break; + +/******************************************************************/ + +enum VarTypes { V_EVENT, V_PARAMETER, + V_INTEGER, V_REAL, V_REG, V_SUPPLY0, + V_SUPPLY1, V_TIME, V_TRI, V_TRIAND, V_TRIOR, + V_TRIREG, V_TRI0, V_TRI1, V_WAND, V_WIRE, V_WOR, V_PORT, + V_END, V_LB, V_COLON, V_RB, V_STRING }; + +char *vartypes[]={ "event", "parameter", + "integer", "real", "reg", "supply0", + "supply1", "time", "tri", "triand", "trior", + "trireg", "tri0", "tri1", "wand", "wire", "wor", "port", + "$end", "", "", "", ""}; + +#define NUM_VTOKENS 19 + +/******************************************************************/ + +/* + * histent structs are NEVER freed so this is OK.. + */ +#define VCD_HISTENT_GRANULARITY 100 + +static struct HistEnt *histent_calloc(struct globals *obj) +{ +if(obj->he_curr==obj->he_fini) + { + obj->he_curr=(struct HistEnt *)calloc_2(VCD_HISTENT_GRANULARITY, sizeof(struct HistEnt)); + obj->he_fini=obj->he_curr+VCD_HISTENT_GRANULARITY; + } + +return(obj->he_curr++); +} + +/******************************************************************/ + +static struct queuedevent *queuedevents=NULL; + +/******************************************************************/ + +/* + * bsearch compare + */ +static int vcdsymbsearchcompare(const void *s1, const void *s2) +{ +char *v1; +struct vcdsymbol *v2; + +v1=(char *)s1; +v2=*((struct vcdsymbol **)s2); + +return(strcmp(v1, v2->id)); +} + + +/* + * actual bsearch + */ +static struct vcdsymbol *bsearch_vcd(struct globals *obj, char *key) +{ +struct vcdsymbol **v; +struct vcdsymbol *t; + +v=(struct vcdsymbol **)bsearch(key, obj->sorted, obj->numsyms, + sizeof(struct vcdsymbol *), vcdsymbsearchcompare); + +if(v) + { + #ifndef VCD_BSEARCH_IS_PERFECT + for(;;) + { + t=*v; + + if((v==obj->sorted)||(strcmp((*(--v))->id, key))) + { + return(t); + } + } + #else + return(*v); + #endif + } + else + { + return(NULL); + } +} + + +/* + * sort on vcdsymbol pointers + */ +static int vcdsymcompare(const void *s1, const void *s2) +{ +struct vcdsymbol *v1, *v2; + +v1=*((struct vcdsymbol **)s1); +v2=*((struct vcdsymbol **)s2); + +return(strcmp(v1->id, v2->id)); +} + + +/* + * create sorted (by id) table + */ +static void create_sorted_table(struct globals *obj) +{ +struct vcdsymbol *v; +struct vcdsymbol **pnt; + +if(obj->sorted) + { + free_2(obj->sorted); /* this means we saw a 2nd enddefinition chunk! */ + } + +if(obj->numsyms) + { + pnt=obj->sorted=(struct vcdsymbol **)calloc_2(obj->numsyms, sizeof(struct vcdsymbol *)); + v=obj->vcdsymroot; + while(v) + { + *(pnt++)=v; + v=v->next; + } + + qsort(obj->sorted, obj->numsyms, sizeof(struct vcdsymbol *), vcdsymcompare); + } +} + +/******************************************************************/ + +/* + * single char get inlined/optimized + */ +static void getch_alloc(struct globals *obj) +{ +obj->vend=obj->vst=obj->vcdbuf=(char *)calloc_2(1,VCD_BSIZ); +} + +static void getch_free(struct globals *obj) +{ +free_2(obj->vcdbuf); +obj->vcdbuf=obj->vst=obj->vend=NULL; +} + + +static int getch_fetch(struct globals *obj) +{ +size_t rd; + +if(feof(obj->vcd_handle)||errno) return(-1); + +obj->vcdbyteno+=(obj->vend-obj->vcdbuf); +rd=fread(obj->vcdbuf, sizeof(char), VCD_BSIZ, obj->vcd_handle); +obj->vend=(obj->vst=obj->vcdbuf)+rd; + +if(!rd) return(-1); + +return((int)(*(obj->vst++))); +} + +#define getch(x) ((x->vst!=x->vend)?((int)(*(x->vst++))):(getch_fetch(x))) + + +static int getch_patched(struct globals *obj) +{ +char ch; + +ch=*obj->vsplitcurr; +if(!ch) + { + return(-1); + } + else + { + obj->vsplitcurr++; + return((int)ch); + } +} + +/* + * simple tokenizer + */ +static int get_token(struct globals *obj) +{ +int ch; +int i, len=0; +int is_string=0; + +for(;;) + { + ch=getch(obj); + if(ch<0) return(T_EOF); + if(ch<=' ') continue; /* val<=' ' is a quick whitespace check */ + break; /* (take advantage of fact that vcd is text) */ + } +if(ch=='$') + { + obj->yytext[len++]=ch; + for(;;) + { + ch=getch(obj); + if(ch<0) return(T_EOF); + if(ch<=' ') continue; + break; + } + } + else + { + is_string=1; + } + +for(obj->yytext[len++]=ch;;obj->yytext[len++]=ch) + { + if(len==obj->T_MAX_STR) + { + obj->yytext=(char *)realloc_2(obj->yytext, (obj->T_MAX_STR=obj->T_MAX_STR*2)+1); + } + ch=getch(obj); + if(ch<=' ') break; + } +obj->yytext[len]=0; /* terminator */ + +if(is_string) + { + obj->yylen=len; + return(T_STRING); + } + +for(i=0;iyytext+1,tokens[i])) + { + return(i); + } + } + +return(T_UNKNOWN_KEY); +} + + +static int get_vartoken_patched(struct globals *obj) +{ +int ch; +int i, len=0; + +if(!obj->var_prevch) + { + for(;;) + { + ch=getch_patched(obj); + if(ch<0) { free_2(obj->varsplit); obj->varsplit=NULL; return(V_END); } + if((ch==' ')||(ch=='\t')||(ch=='\n')||(ch=='\r')) continue; + break; + } + } + else + { + ch=obj->var_prevch; + obj->var_prevch=0; + } + +if(ch=='[') return(V_LB); +if(ch==':') return(V_COLON); +if(ch==']') return(V_RB); + +for(obj->yytext[len++]=ch;;obj->yytext[len++]=ch) + { + if(len==obj->T_MAX_STR) + { + obj->yytext=(char *)realloc_2(obj->yytext, (obj->T_MAX_STR=obj->T_MAX_STR*2)+1); + } + ch=getch_patched(obj); + if(ch<0) break; + if((ch==':')||(ch==']')) + { + obj->var_prevch=ch; + break; + } + } +obj->yytext[len]=0; /* terminator */ + +for(i=0;iyytext,vartypes[i])) + { + if(ch<0) { free_2(obj->varsplit); obj->varsplit=NULL; } + return(i); + } + } + +obj->yylen=len; +if(ch<0) { free_2(obj->varsplit); obj->varsplit=NULL; } +return(V_STRING); +} + +static int get_vartoken(struct globals *obj) +{ +int ch; +int i, len=0; + +if(obj->varsplit) + { + int rc=get_vartoken_patched(obj); + if(rc!=V_END) return(rc); + obj->var_prevch=0; + } + +if(!obj->var_prevch) + { + for(;;) + { + ch=getch(obj); + if(ch<0) return(V_END); + if((ch==' ')||(ch=='\t')||(ch=='\n')||(ch=='\r')) continue; + break; + } + } + else + { + ch=obj->var_prevch; + obj->var_prevch=0; + } + +if(ch=='[') return(V_LB); +if(ch==':') return(V_COLON); +if(ch==']') return(V_RB); + +for(obj->yytext[len++]=ch;;obj->yytext[len++]=ch) + { + if(len==obj->T_MAX_STR) + { + obj->yytext=(char *)realloc_2(obj->yytext, (obj->T_MAX_STR=obj->T_MAX_STR*2)+1); + } + ch=getch(obj); + if((ch==' ')||(ch=='\t')||(ch=='\n')||(ch=='\r')||(ch<0)) break; + if((ch=='[')&&(obj->yytext[0]!='\\')) + { + obj->varsplit=obj->yytext+len; /* keep looping so we get the *last* one */ + } + else + if(((ch==':')||(ch==']'))&&(!obj->varsplit)&&(obj->yytext[0]!='\\')) + { + obj->var_prevch=ch; + break; + } + } +obj->yytext[len]=0; /* absolute terminator */ +if((obj->varsplit)&&(obj->yytext[len-1]==']')) + { + char *vst; + vst=malloc_2(strlen(obj->varsplit)+1); + strcpy(vst, obj->varsplit); + + *obj->varsplit=0x00; /* zero out var name at the left bracket */ + len=obj->varsplit-obj->yytext; + + obj->varsplit=obj->vsplitcurr=vst; + obj->var_prevch=0; + } + else + { + obj->varsplit=NULL; + } + +for(i=0;iyytext,vartypes[i])) + { + return(i); + } + } + +obj->yylen=len; +return(V_STRING); +} + +static int get_strtoken(struct globals *obj) +{ +int ch; +int len=0; + +if(!obj->var_prevch) + { + for(;;) + { + ch=getch(obj); + if(ch<0) return(V_END); + if((ch==' ')||(ch=='\t')||(ch=='\n')||(ch=='\r')) continue; + break; + } + } + else + { + ch=obj->var_prevch; + obj->var_prevch=0; + } + +for(obj->yytext[len++]=ch;;obj->yytext[len++]=ch) + { + if(len==obj->T_MAX_STR) + { + obj->yytext=(char *)realloc_2(obj->yytext, (obj->T_MAX_STR=obj->T_MAX_STR*2)+1); + } + ch=getch(obj); + if((ch==' ')||(ch=='\t')||(ch=='\n')||(ch=='\r')||(ch<0)) break; + } +obj->yytext[len]=0; /* terminator */ + +obj->yylen=len; +return(V_STRING); +} + +static void sync_end(struct globals *obj, char *hdr) +{ +int tok; + +if(hdr) DEBUG(fprintf(stderr,"%s",hdr)); +for(;;) + { + tok=get_token(obj); + if((tok==T_END)||(tok==T_EOF)) break; + if(hdr)DEBUG(fprintf(stderr," %s",yytext)); + } +if(hdr) DEBUG(fprintf(stderr,"\n")); +} + +static char *build_slisthier(struct globals *obj) +{ +struct slist *s; +int len=0; + +if(!obj->slistroot) + { + if(obj->slisthier) + { + free_2(obj->slisthier); + } + + obj->slisthier_len=0; + obj->slisthier=(char *)malloc_2(1); + *obj->slisthier=0; + return(obj->slisthier); + } + +s=obj->slistroot; len=0; +while(s) + { + len+=s->len+(s->next?1:0); + s=s->next; + } + +obj->slisthier=(char *)malloc_2((obj->slisthier_len=len)+1); +s=obj->slistroot; len=0; +while(s) + { + strcpy(obj->slisthier+len,s->str); + len+=s->len; + if(s->next) + { + strcpy(obj->slisthier+len,obj->vcd_hier_delimeter); + len++; + } + s=s->next; + } +return(obj->slisthier); +} + + +void append_vcd_slisthier(struct globals *obj, char *str) +{ +struct slist *s; +s=(struct slist *)calloc_2(1,sizeof(struct slist)); +s->len=strlen(str); +s->str=(char *)malloc_2(s->len+1); +strcpy(s->str,str); + +if(obj->slistcurr) + { + obj->slistcurr->next=s; + obj->slistcurr=s; + } + else + { + obj->slistcurr=obj->slistroot=s; + } + +build_slisthier(obj); +DEBUG(fprintf(stderr, "SCOPE: %s\n",obj->slisthier)); +} + + +static void parse_valuechange(struct globals *obj) +{ +struct vcdsymbol *v; +char *vector; +int vlen; + +switch(obj->yytext[0]) + { + case '0': + case '1': + case 'x': + case 'X': + case 'z': + case 'Z': + if(obj->yylen>1) + { + v=bsearch_vcd(obj, obj->yytext+1); + if(!v) + { + fprintf(stderr,"Near byte %d, Unknown VCD identifier: '%s'\n",obj->vcdbyteno+(obj->vst-obj->vcdbuf),obj->yytext+1); + } + else + { + if(v->vartype!=V_EVENT) + { + v->value[0]=obj->yytext[0]; + DEBUG(fprintf(stderr,"%s = '%c'\n",v->name,v->value[0])); + add_histent(obj, obj->current_time,v->narray[0],v->value[0],1, NULL); + } + else + { + v->value[0]=(obj->dumping_off)?'x':'1'; /* only '1' is relevant */ + if(obj->current_time!=(v->ev->last_event_time+1)) + { + /* dump degating event */ + DEBUG(fprintf(stderr,"#"TTFormat" %s = '%c' (event)\n",v->ev->last_event_time+1,v->name,'0')); + add_histent(obj, v->ev->last_event_time+1,v->narray[0],'0',1, NULL); + } + DEBUG(fprintf(stderr,"%s = '%c' (event)\n",v->name,v->value[0])); + add_histent(obj, obj->current_time,v->narray[0],v->value[0],1, NULL); + v->ev->last_event_time=obj->current_time; + } + } + } + else + { + fprintf(stderr,"Near byte %d, Malformed VCD identifier\n", obj->vcdbyteno+(obj->vst-obj->vcdbuf)); + } + break; + + case 'b': + case 'B': + { + /* extract binary number then.. */ + vector=malloc_2(obj->yylen_cache=obj->yylen); + strcpy(vector,obj->yytext+1); + vlen=obj->yylen-1; + + get_strtoken(obj); + v=bsearch_vcd(obj, obj->yytext); + if(!v) + { + fprintf(stderr,"Near byte %d, Unknown identifier: '%s'\n",obj->vcdbyteno+(obj->vst-obj->vcdbuf), obj->yytext); + free_2(vector); + } + else + { + if((obj->convert_to_reals)&&(v->vartype==V_REAL)) + { + double *d; + char *pnt; + char ch; + TimeType k=0; + + pnt=vector; + while((ch=*(pnt++))) { k=(k<<1)|((ch=='1')?1:0); } + free_2(vector); + + d=malloc_2(sizeof(double)); + *d=(double)k; + + if(!v) + { + fprintf(stderr,"Near byte %d, Unknown identifier: '%s'\n",obj->vcdbyteno+(obj->vst-obj->vcdbuf), obj->yytext); + free_2(d); + } + else + { + add_histent(obj, obj->current_time, v->narray[0],'g',1,(char *)d); + } + break; + } + + if(vlensize) /* fill in left part */ + { + char extend; + int i, fill; + + extend=(vector[0]=='1')?'0':vector[0]; + + fill=v->size-vlen; + for(i=0;ivalue[i]=extend; + } + strcpy(v->value+fill,vector); + } + else if(vlen==v->size) /* straight copy */ + { + strcpy(v->value,vector); + } + else /* too big, so copy only right half */ + { + int skip; + + skip=vlen-v->size; + strcpy(v->value,vector+skip); + } + DEBUG(fprintf(stderr,"%s = '%s'\n",v->name, v->value)); + + if((v->size==1)||(!obj->atomic_vectors)) + { + int i; + for(i=0;isize;i++) + { + add_histent(obj, obj->current_time, v->narray[i],v->value[i],1, NULL); + } + free_2(vector); + } + else + { + if(obj->yylen_cache!=(v->size+1)) + { + free_2(vector); + vector=malloc_2(v->size+1); + } + strcpy(vector,v->value); + add_histent(obj, obj->current_time, v->narray[0],0,1,vector); + } + + } + break; + } + + case 'p': + /* extract port dump value.. */ + vector=malloc_2(obj->yylen_cache=obj->yylen); + strcpy(vector,obj->yytext+1); + vlen=obj->yylen-1; + + get_strtoken(obj); /* throw away 0_strength_component */ + get_strtoken(obj); /* throw away 0_strength_component */ + get_strtoken(obj); /* this is the id */ + v=bsearch_vcd(obj, obj->yytext); + if(!v) + { + fprintf(stderr,"Near byte %d, Unknown identifier: '%s'\n",obj->vcdbyteno+(obj->vst-obj->vcdbuf), obj->yytext); + free_2(vector); + } + else + { + if((obj->convert_to_reals)&&(v->vartype==V_REAL)) /* should never happen, but just in case.. */ + { + double *d; + char *pnt; + char ch; + TimeType k=0; + + pnt=vector; + while((ch=*(pnt++))) { k=(k<<1)|((ch=='1')?1:0); } + free_2(vector); + + d=malloc_2(sizeof(double)); + *d=(double)k; + + if(!v) + { + fprintf(stderr,"Near byte %d, Unknown identifier: '%s'\n",obj->vcdbyteno+(obj->vst-obj->vcdbuf), obj->yytext); + free_2(d); + } + else + { + add_histent(obj, obj->current_time, v->narray[0],'g',1,(char *)d); + } + break; + } + + if(vlensize) /* fill in left part */ + { + char extend; + int i, fill; + + extend='0'; + + fill=v->size-vlen; + for(i=0;ivalue[i]=extend; + } + evcd_strcpy(v->value+fill,vector); + } + else if(vlen==v->size) /* straight copy */ + { + evcd_strcpy(v->value,vector); + } + else /* too big, so copy only right half */ + { + int skip; + + skip=vlen-v->size; + evcd_strcpy(v->value,vector+skip); + } + DEBUG(fprintf(stderr,"%s = '%s'\n",v->name, v->value)); + + if((v->size==1)||(!obj->atomic_vectors)) + { + int i; + for(i=0;isize;i++) + { + add_histent(obj, obj->current_time, v->narray[i],v->value[i],1, NULL); + } + free_2(vector); + } + else + { + if(obj->yylen_cachesize) + { + free_2(vector); + vector=malloc_2(v->size+1); + } + strcpy(vector,v->value); + add_histent(obj, obj->current_time, v->narray[0],0,1,vector); + } + } + break; + + + case 'r': + case 'R': + { + double *d; + + d=malloc_2(sizeof(double)); + sscanf(obj->yytext+1,"%lg",d); + + get_strtoken(obj); + v=bsearch_vcd(obj, obj->yytext); + if(!v) + { + fprintf(stderr,"Near byte %d, Unknown identifier: '%s'\n",obj->vcdbyteno+(obj->vst-obj->vcdbuf), obj->yytext); + free_2(d); + } + else + { + add_histent(obj, obj->current_time, v->narray[0],'g',1,(char *)d); + } + + break; + } + +#ifndef STRICT_VCD_ONLY + case 's': + case 'S': + { + char *d; + + d=(char *)malloc_2(obj->yylen); + strcpy(d, obj->yytext+1); + + get_strtoken(obj); + v=bsearch_vcd(obj, obj->yytext); + if(!v) + { + fprintf(stderr,"Near byte %d, Unknown identifier: '%s'\n",obj->vcdbyteno+(obj->vst-obj->vcdbuf), obj->yytext); + free_2(d); + } + else + { + add_histent(obj, obj->current_time, v->narray[0],'s',1,(char *)d); + } + + break; + } +#endif + } + +} + + +static void evcd_strcpy(char *dst, char *src) +{ +static char *evcd="DUNZduLHXTlh01?FAaBbCcf"; +static char *vcd="01xz0101xz0101xzxxxxxxx"; + +char ch; +int i; + +while((ch=*src)) + { + for(i=0;i<23;i++) + { + if(evcd[i]==ch) + { + *dst=vcd[i]; + break; + } + } + if(i==23) *dst='x'; + + src++; + dst++; + } + +*dst=0; /* null terminate destination */ +} + + +static void vcd_parse(struct globals *obj) +{ +int tok; + +for(;;) + { + switch(tok=get_token(obj)) + { + case T_COMMENT: + sync_end(obj, "COMMENT:"); + break; + case T_DATE: + sync_end(obj, "DATE:"); + break; + case T_VERSION: + sync_end(obj, "VERSION:"); + break; + case T_TIMESCALE: + { + int vtok; + int i; + char prefix=' '; + + vtok=get_token(obj); + if((vtok==T_END)||(vtok==T_EOF)) break; + obj->time_scale=atoi_64(obj->yytext); + if(!obj->time_scale) obj->time_scale=1; + for(i=0;iyylen;i++) + { + if((obj->yytext[i]<'0')||(obj->yytext[i]>'9')) + { + prefix=obj->yytext[i]; + break; + } + } + if(prefix==' ') + { + vtok=get_token(obj); + if((vtok==T_END)||(vtok==T_EOF)) break; + prefix=obj->yytext[0]; + } + switch(prefix) + { + case ' ': + case 'm': + case 'u': + case 'n': + case 'p': + case 'f': + obj->time_dimension=prefix; + break; + case 's': + obj->time_dimension=' '; + break; + default: /* unknown */ + obj->time_dimension='n'; + break; + } + + DEBUG(fprintf(stderr,"TIMESCALE: "TTFormat" %cs\n",obj->time_scale, obj->time_dimension)); + sync_end(obj, NULL); + } + break; + case T_SCOPE: + T_GET(obj); + T_GET(obj); + if(tok==T_STRING) + { + struct slist *s; + s=(struct slist *)calloc_2(1,sizeof(struct slist)); + s->len=obj->yylen; + s->str=(char *)malloc_2(obj->yylen+1); + strcpy(s->str,obj->yytext); + + if(obj->slistcurr) + { + obj->slistcurr->next=s; + obj->slistcurr=s; + } + else + { + obj->slistcurr=obj->slistroot=s; + } + + build_slisthier(obj); + DEBUG(fprintf(stderr, "SCOPE: %s\n",obj->slisthier)); + } + sync_end(obj, NULL); + break; + case T_UPSCOPE: + if(obj->slistroot) + { + struct slist *s; + + s=obj->slistroot; + if(!s->next) + { + free_2(s->str); + free_2(s); + obj->slistroot=obj->slistcurr=NULL; + } + else + for(;;) + { + if(!s->next->next) + { + free_2(s->next->str); + free_2(s->next); + s->next=NULL; + obj->slistcurr=s; + break; + } + s=s->next; + } + build_slisthier(obj); + DEBUG(fprintf(stderr, "SCOPE: %s\n",obj->slisthier)); + } + sync_end(obj, NULL); + break; + case T_VAR: + if((obj->header_over)&&(0)) + { + fprintf(stderr,"$VAR encountered after $ENDDEFINITIONS near byte %d. VCD is malformed, exiting.\n",obj->vcdbyteno+(obj->vst-obj->vcdbuf)); + exit(VCD_FAIL); + } + else + { + int vtok; + struct vcdsymbol *v=NULL; + + obj->var_prevch=0; + obj->varsplit=NULL; + vtok=get_vartoken(obj); + if(vtok>V_PORT) goto bail; + + v=(struct vcdsymbol *)calloc_2(1,sizeof(struct vcdsymbol)); + v->vartype=vtok; + v->msi=v->lsi=obj->vcd_explicit_zero_subscripts; /* indicate [un]subscripted status */ + + if(vtok==V_PORT) + { + vtok=get_vartoken(obj); + if(vtok==V_STRING) + { + v->size=atoi_64(obj->yytext); + if(!v->size) v->size=1; + } + else + if(vtok==V_LB) + { + vtok=get_vartoken(obj); + if(vtok==V_END) goto err; + if(vtok!=V_STRING) goto err; + v->msi=atoi_64(obj->yytext); + vtok=get_vartoken(obj); + if(vtok==V_RB) + { + v->lsi=v->msi; + v->size=1; + } + else + { + if(vtok!=V_COLON) goto err; + vtok=get_vartoken(obj); + if(vtok!=V_STRING) goto err; + v->lsi=atoi_64(obj->yytext); + vtok=get_vartoken(obj); + if(vtok!=V_RB) goto err; + + if(v->msi>v->lsi) + { + v->size=v->msi-v->lsi+1; + } + else + { + v->size=v->lsi-v->msi+1; + } + } + } + else goto err; + + vtok=get_strtoken(obj); + if(vtok==V_END) goto err; + v->id=(char *)malloc_2(obj->yylen+1); + strcpy(v->id, obj->yytext); + + vtok=get_vartoken(obj); + if(vtok!=V_STRING) goto err; + if(obj->slisthier_len) + { + v->name=(char *)malloc_2(obj->slisthier_len+1+obj->yylen+1); + strcpy(v->name,obj->slisthier); + strcpy(v->name+obj->slisthier_len,obj->vcd_hier_delimeter); + strcpy(v->name+obj->slisthier_len+1,obj->yytext); + } + else + { + v->name=(char *)malloc_2(obj->yylen+1); + strcpy(v->name,obj->yytext); + } + + if(obj->pv) + { + if(!strcmp(obj->pv->name,v->name)) + { + obj->pv->chain=v; + v->root=obj->rootv; + if(obj->pv==obj->rootv) obj->pv->root=obj->rootv; + } + else + { + obj->rootv=v; + } + } + else + { + obj->rootv=v; + } + obj->pv=v; + } + else /* regular vcd var, not an evcd port var */ + { + vtok=get_vartoken(obj); + if(vtok==V_END) goto err; + v->size=atoi_64(obj->yytext); + if(!v->size) v->size=1; + vtok=get_strtoken(obj); + if(vtok==V_END) goto err; + v->id=(char *)malloc_2(obj->yylen+1); + strcpy(v->id, obj->yytext); + + vtok=get_vartoken(obj); + if(vtok!=V_STRING) goto err; + if(obj->slisthier_len) + { + v->name=(char *)malloc_2(obj->slisthier_len+1+obj->yylen+1); + strcpy(v->name,obj->slisthier); + strcpy(v->name+obj->slisthier_len,obj->vcd_hier_delimeter); + strcpy(v->name+obj->slisthier_len+1,obj->yytext); + } + else + { + v->name=(char *)malloc_2(obj->yylen+1); + strcpy(v->name,obj->yytext); + } + + if(obj->pv) + { + if(!strcmp(obj->pv->name,v->name)) + { + obj->pv->chain=v; + v->root=obj->rootv; + if(obj->pv==obj->rootv) obj->pv->root=obj->rootv; + } + else + { + obj->rootv=v; + } + } + else + { + obj->rootv=v; + } + obj->pv=v; + + vtok=get_vartoken(obj); + if(vtok==V_END) goto dumpv; + if(vtok!=V_LB) goto err; + vtok=get_vartoken(obj); + if(vtok!=V_STRING) goto err; + v->msi=atoi_64(obj->yytext); + vtok=get_vartoken(obj); + if(vtok==V_RB) + { + v->lsi=v->msi; + goto dumpv; + } + if(vtok!=V_COLON) goto err; + vtok=get_vartoken(obj); + if(vtok!=V_STRING) goto err; + v->lsi=atoi_64(obj->yytext); + vtok=get_vartoken(obj); + if(vtok!=V_RB) goto err; + } + + dumpv: + if((v->vartype==V_REAL)||((obj->convert_to_reals)&&((v->vartype==V_INTEGER)||(v->vartype==V_PARAMETER)))) + { + v->vartype=V_REAL; + v->size=1; /* override any data we parsed in */ + v->msi=v->lsi=0; + } + else + if((v->size>1)&&(v->msi<=0)&&(v->lsi<=0)) + { + if(v->vartype==V_EVENT) + { + v->size=1; + } + else + { + /* any criteria for the direction here? */ + v->msi=v->size-1; + v->lsi=0; + } + } + else + if((v->msi>v->lsi)&&((v->msi-v->lsi+1)!=v->size)) + { + if((v->vartype!=V_EVENT)&&(v->vartype!=V_PARAMETER)) goto err; + v->size=v->msi-v->lsi+1; + } + else + if((v->lsi>=v->msi)&&((v->lsi-v->msi+1)!=v->size)) + { + if((v->vartype!=V_EVENT)&&(v->vartype!=V_PARAMETER)) goto err; + v->size=v->msi-v->lsi+1; + } + + /* initial conditions */ + v->value=(char *)malloc_2(v->size+1); + v->value[v->size]=0; + v->narray=(struct Node **)calloc_2(v->size,sizeof(struct Node *)); + { + int i; + if(obj->atomic_vectors) + { + for(i=0;isize;i++) + { + v->value[i]='x'; + } + v->narray[0]=(struct Node *)calloc_2(1,sizeof(struct Node)); + v->narray[0]->head.time=-1; + v->narray[0]->head.v.val=1; + } + else + { + for(i=0;isize;i++) + { + v->value[i]='x'; + + v->narray[i]=(struct Node *)calloc_2(1,sizeof(struct Node)); + v->narray[i]->head.time=-1; + v->narray[i]->head.v.val=1; + } + } + } + + if(v->vartype==V_EVENT) + { + struct queuedevent *q; + v->ev=q=(struct queuedevent *)calloc_2(1,sizeof(struct queuedevent)); + q->sym=v; + q->last_event_time=-1; + q->next=queuedevents; + queuedevents=q; + } + + if(!obj->vcdsymroot) + { + obj->vcdsymroot=obj->vcdsymcurr=v; + } + else + { + obj->vcdsymcurr->next=v; + obj->vcdsymcurr=v; + } + obj->numsyms++; + + DEBUG(fprintf(stderr,"VAR %s %d %s %s[%d:%d]\n", + vartypes[v->vartype], v->size, v->id, v->name, + v->msi, v->lsi)); + goto bail; + err: + if(v) + { + if(v->name) free_2(v->name); + if(v->id) free_2(v->id); + if(v->value) free_2(v->value); + free_2(v); + } + + bail: + if(vtok!=V_END) sync_end(obj, NULL); + break; + } + case T_ENDDEFINITIONS: + obj->header_over=1; /* do symbol table management here */ + create_sorted_table(obj); + if(!obj->sorted) + { + fprintf(stderr, "No symbols in VCD file..nothing to do!\n"); + exit(VCD_FAIL); + } + break; + case T_STRING: + if(obj->header_over) + { + /* catchall for events when header over */ + if(obj->yytext[0]=='#') + { + TimeType time; + time=atoi_64(obj->yytext+1); + + if(obj->start_time<0) + { + obj->start_time=time; + } + + obj->current_time=time; + if(obj->end_timeend_time=time; /* in case of malformed vcd files */ + DEBUG(fprintf(stderr,"#"TTFormat"\n",time)); + } + else + { + parse_valuechange(obj); + } + } + break; + case T_DUMPALL: /* dump commands modify vals anyway so */ + case T_DUMPPORTSALL: + break; /* just loop through.. */ + case T_DUMPOFF: + case T_DUMPPORTSOFF: + obj->dumping_off=1; + break; + case T_DUMPON: + case T_DUMPPORTSON: + obj->dumping_off=0; + break; + case T_DUMPVARS: + case T_DUMPPORTS: + break; + case T_VCDCLOSE: + break; /* next token will be '#' time related followed by $end */ + case T_END: /* either closure for dump commands or */ + break; /* it's spurious */ + case T_UNKNOWN_KEY: + sync_end(obj, NULL); /* skip over unknown keywords */ + break; + case T_EOF: + return; + default: + DEBUG(fprintf(stderr,"UNKNOWN TOKEN\n")); + } + } +} + + +/*******************************************************************************/ + +void add_histent(struct globals *obj, TimeType time, struct Node *n, char ch, int regadd, char *vector) +{ +struct HistEnt *he; +char heval; + +if(!vector) +{ +if(!n->curr) + { + he=histent_calloc(obj); + he->time=-1; + he->v.val=1; + + n->curr=he; + n->head.next=he; + + add_histent(obj, time,n,ch,regadd, vector); + } + else + { + if(regadd) { time*=(obj->time_scale); } + + if(ch=='0') heval=0; else + if(ch=='1') heval=3; else + if((ch=='x')||(ch=='X')) heval=1; else + heval=2; + + if((n->curr->v.val!=heval)||(time==obj->start_time)) /* same region == go skip */ + { + if((n->curr->time==time)&&(obj->count_glitches)) + { + DEBUG(printf("Warning: Glitch at time ["TTFormat"] Signal [%p], Value [%c->%c].\n", + time, n, "0XZ1"[n->curr->v.val], ch)); + n->curr->v.val=heval; /* we have a glitch! */ + + obj->num_glitches++; + if(!(n->curr->flags&HIST_GLITCH)) + { + n->curr->flags|=HIST_GLITCH; /* set the glitch flag */ + obj->num_glitch_regions++; + } + } + else + { + he=histent_calloc(obj); + he->time=time; + he->v.val=heval; + + n->curr->next=he; + n->curr=he; + obj->regions+=regadd; + } + } + } +} +else +{ +switch(ch) + { + case 's': /* string */ + { + if(!n->curr) + { + he=histent_calloc(obj); + he->flags=(HIST_STRING|HIST_REAL); + he->time=-1; + he->v.vector=NULL; + + n->curr=he; + n->head.next=he; + + add_histent(obj, time,n,ch,regadd, vector); + } + else + { + if(regadd) { time*=(obj->time_scale); } + + if((n->curr->time==time)&&(obj->count_glitches)) + { + DEBUG(printf("Warning: String Glitch at time ["TTFormat"] Signal [%p].\n", + time, n)); + if(n->curr->v.vector) free_2(n->curr->v.vector); + n->curr->v.vector=vector; /* we have a glitch! */ + + obj->num_glitches++; + if(!(n->curr->flags&HIST_GLITCH)) + { + n->curr->flags|=HIST_GLITCH; /* set the glitch flag */ + obj->num_glitch_regions++; + } + } + else + { + he=histent_calloc(obj); + he->flags=(HIST_STRING|HIST_REAL); + he->time=time; + he->v.vector=vector; + + n->curr->next=he; + n->curr=he; + obj->regions+=regadd; + } + } + break; + } + case 'g': /* real number */ + { + if(!n->curr) + { + he=histent_calloc(obj); + he->flags=HIST_REAL; + he->time=-1; + he->v.vector=NULL; + + n->curr=he; + n->head.next=he; + + add_histent(obj, time,n,ch,regadd, vector); + } + else + { + if(regadd) { time*=(obj->time_scale); } + + if( + (n->curr->v.vector&&vector&&(*(double *)n->curr->v.vector!=*(double *)vector)) + ||(time==obj->start_time) + ||(!n->curr->v.vector) + ) /* same region == go skip */ + { + if((n->curr->time==time)&&(obj->count_glitches)) + { + DEBUG(printf("Warning: Real number Glitch at time ["TTFormat"] Signal [%p].\n", + time, n)); + if(n->curr->v.vector) free_2(n->curr->v.vector); + n->curr->v.vector=vector; /* we have a glitch! */ + + obj->num_glitches++; + if(!(n->curr->flags&HIST_GLITCH)) + { + n->curr->flags|=HIST_GLITCH; /* set the glitch flag */ + obj->num_glitch_regions++; + } + } + else + { + he=histent_calloc(obj); + he->flags=HIST_REAL; + he->time=time; + he->v.vector=vector; + + n->curr->next=he; + n->curr=he; + obj->regions+=regadd; + } + } + else + { + free_2(vector); + } + } + break; + } + default: + { + if(!n->curr) + { + he=histent_calloc(obj); + he->time=-1; + he->v.vector=NULL; + + n->curr=he; + n->head.next=he; + + add_histent(obj, time,n,ch,regadd, vector); + } + else + { + if(regadd) { time*=(obj->time_scale); } + + if( + (n->curr->v.vector&&vector&&(strcmp(n->curr->v.vector,vector))) + ||(time==obj->start_time) + ||(!n->curr->v.vector) + ) /* same region == go skip */ + { + if((n->curr->time==time)&&(obj->count_glitches)) + { + DEBUG(printf("Warning: Glitch at time ["TTFormat"] Signal [%p], Value [%c->%c].\n", + time, n, "0XZ1"[n->curr->v.val], ch)); + if(n->curr->v.vector) free_2(n->curr->v.vector); + n->curr->v.vector=vector; /* we have a glitch! */ + + obj->num_glitches++; + if(!(n->curr->flags&HIST_GLITCH)) + { + n->curr->flags|=HIST_GLITCH; /* set the glitch flag */ + obj->num_glitch_regions++; + } + } + else + { + he=histent_calloc(obj); + he->time=time; + he->v.vector=vector; + + n->curr->next=he; + n->curr=he; + obj->regions+=regadd; + } + } + else + { + free_2(vector); + } + } + break; + } + } +} + +} + + +static void add_tail_histents(struct globals *obj) +{ +int i,j; + +/* dump out any pending events 1st */ +struct queuedevent *q; +q=queuedevents; +while(q) + { + struct vcdsymbol *v; + + v=q->sym; + if(obj->current_time!=(v->ev->last_event_time+1)) + { + /* dump degating event */ + DEBUG(fprintf(stderr,"#"TTFormat" %s = '%c' (event)\n",v->ev->last_event_time+1,v->name,'0')); + add_histent(obj, v->ev->last_event_time+1,v->narray[0],'0',1, NULL); + } + q=q->next; + } + +/* then do 'x' trailers */ + +for(i=0;inumsyms;i++) + { + struct vcdsymbol *v; + v=obj->sorted[i]; + if(v->vartype==V_REAL) + { + double *d; + + d=malloc_2(sizeof(double)); + *d=1.0; + add_histent(obj, MAX_HISTENT_TIME-1, v->narray[0], 'g', 0, (char *)d); + } + else + if((v->size==1)||(!obj->atomic_vectors)) + for(j=0;jsize;j++) + { + add_histent(obj, MAX_HISTENT_TIME-1, v->narray[j], 'x', 0, NULL); + } + else + { + add_histent(obj, MAX_HISTENT_TIME-1, v->narray[0], 'x', 0, (char *)calloc_2(1,sizeof(char))); + } + } + + +for(i=0;inumsyms;i++) + { + struct vcdsymbol *v; + v=obj->sorted[i]; + if(v->vartype==V_REAL) + { + double *d; + + d=malloc_2(sizeof(double)); + *d=0.0; + add_histent(obj, MAX_HISTENT_TIME, v->narray[0], 'g', 0, (char *)d); + } + else + if((v->size==1)||(!obj->atomic_vectors)) + for(j=0;jsize;j++) + { + add_histent(obj, MAX_HISTENT_TIME, v->narray[j], 'z', 0, NULL); + } + else + { + add_histent(obj, MAX_HISTENT_TIME, v->narray[0], 'z', 0, (char *)calloc_2(1,sizeof(char))); + } + } +} + +/*******************************************************************************/ + +static void vcd_build_symbols(struct globals *obj) +{ +int i,j; +int max_slen=-1; +struct sym_chain *sym_chain=NULL, *sym_curr=NULL; + +for(i=0;inumsyms;i++) + { + struct vcdsymbol *v, *vprime; + int msi; + int delta; + + { + char *str; + int slen; + int substnode; + + v=obj->sorted[i]; + msi=v->msi; + delta=((v->lsi-v->msi)<0)?-1:1; + substnode=0; + + slen=strlen(v->name); + str=(slen>max_slen)?(wave_alloca((max_slen=slen)+32)):(str); /* more than enough */ + strcpy(str,v->name); + + if(v->msi>=0) + { + strcpy(str+slen,obj->vcd_hier_delimeter); + slen++; + } + + if((vprime=bsearch_vcd(obj, v->id))!=v) /* hash mish means dup net */ + { + if(v->size!=vprime->size) + { + fprintf(stderr,"ERROR: Duplicate IDs with differing width: %s %s\n", v->name, vprime->name); + } + else + { + substnode=1; + } + } + + if(((v->size==1)||(!obj->atomic_vectors))&&(v->vartype!=V_REAL)) + { + struct symbol *s; + + for(j=0;jsize;j++) + { + if(v->msi>=0) + { + if(!obj->vcd_explicit_zero_subscripts) + sprintf(str+slen,"%d",msi); + else + sprintf(str+slen-1,"[%d]",msi); + } + if(!symfind(obj, str)) + { + s=symadd(obj, str,hash(str)); + + s->n=v->narray[j]; + if(substnode) + { + struct Node *n, *n2; + + n=s->n; + n2=vprime->narray[j]; + /* nname stays same */ + n->head=n2->head; + n->curr=n2->curr; + /* harray calculated later */ + n->numhist=n2->numhist; + } + + s->n->nname=s->name; + s->h=s->n->curr; + if(!obj->firstnode) + { + obj->firstnode=obj->curnode=s; + } + else + { + obj->curnode->nextinaet=s; + obj->curnode=s; + } + + obj->numfacs++; + DEBUG(fprintf(stderr,"Added: %s\n",str)); + } + else + { + fprintf(stderr,"Warning: %s is a duplicate net name.\n",str); + } + msi+=delta; + } + + if((j==1)&&(v->root)) + { + s->vec_root=(struct symbol *)v->root; /* these will get patched over */ + s->vec_chain=(struct symbol *)v->chain; /* these will get patched over */ + v->sym_chain=s; + + if(!sym_chain) + { + sym_curr=(struct sym_chain *)calloc_2(1,sizeof(struct sym_chain)); + sym_chain=sym_curr; + } + else + { + sym_curr->next=(struct sym_chain *)calloc_2(1,sizeof(struct sym_chain)); + sym_curr=sym_curr->next; + } + sym_curr->val=s; + } + } + else /* atomic vector */ + { + if(v->vartype!=V_REAL) + { + sprintf(str+slen-1,"[%d:%d]",v->msi,v->lsi); + } + else + { + *(str+slen-1)=0; + } + if(!symfind(obj, str)) + { + struct symbol *s; + + s=symadd(obj, str,hash(str)); + + s->n=v->narray[0]; + if(substnode) + { + struct Node *n, *n2; + + n=s->n; + n2=vprime->narray[0]; + /* nname stays same */ + n->head=n2->head; + n->curr=n2->curr; + /* harray calculated later */ + n->numhist=n2->numhist; + n->ext=n2->ext; + } + else + { + struct ExtNode *en; + en=(struct ExtNode *)malloc_2(sizeof(struct ExtNode)); + en->msi=v->msi; + en->lsi=v->lsi; + + s->n->ext=en; + } + + s->n->nname=s->name; + s->h=s->n->curr; + if(!obj->firstnode) + { + obj->firstnode=obj->curnode=s; + } + else + { + obj->curnode->nextinaet=s; + obj->curnode=s; + } + + obj->numfacs++; + DEBUG(fprintf(stderr,"Added: %s\n",str)); + } + else + { + fprintf(stderr,"Warning: %s is a duplicate net name.\n",str); + } + } + } + } + +if(sym_chain) + { + sym_curr=sym_chain; + while(sym_curr) + { + sym_curr->val->vec_root= ((struct vcdsymbol *)sym_curr->val->vec_root)->sym_chain; + + if ((struct vcdsymbol *)sym_curr->val->vec_chain) + sym_curr->val->vec_chain=((struct vcdsymbol *)sym_curr->val->vec_chain)->sym_chain; + + DEBUG(printf("Link: ('%s') '%s' -> '%s'\n",sym_curr->val->vec_root->name, sym_curr->val->name, sym_curr->val->vec_chain?sym_curr->val->vec_chain->name:"(END)")); + + sym_chain=sym_curr; + sym_curr=sym_curr->next; + free_2(sym_chain); + } + } +} + +/*******************************************************************************/ + +void vcd_sortfacs(struct globals *obj) +{ +int i; + +obj->facs=(struct symbol **)malloc_2(obj->numfacs*sizeof(struct symbol *)); +obj->curnode=obj->firstnode; +for(i=0;inumfacs;i++) + { + char *subst, ch; + int len; + + obj->facs[i]=obj->curnode; + if((len=strlen(subst=obj->curnode->name))>obj->longestname) obj->longestname=len; + obj->curnode=obj->curnode->nextinaet; + while((ch=(*subst))) + { + if(ch==obj->hier_delimeter) { *subst=0x01; } /* forces sort at hier boundaries */ + subst++; + } + } +quicksort(obj->facs,0,obj->numfacs-1); + +for(i=0;inumfacs;i++) + { + char *subst, ch; + + subst=obj->facs[i]->name; + while((ch=(*subst))) + { + if(ch==0x01) { *subst=obj->hier_delimeter; } /* restore back to normal */ + subst++; + } + +#ifdef DEBUG_FACILITIES + printf("%-4d %s\n",i,obj->facs[i]->name); +#endif + } + +obj->facs_are_sorted=1; +} + +/*******************************************************************************/ + +static void vcd_cleanup(struct globals *obj) +{ +int i; +struct slist *s, *s2; + +if(obj->sorted) + { + for(i=0;inumsyms;i++) + { + struct vcdsymbol *v; + v=obj->sorted[i]; + if(v) + { + if(v->name) free_2(v->name); + if(v->id) free_2(v->id); + if(v->value) free_2(v->value); + if(v->ev) free_2(v->ev); + if(v->narray) free_2(v->narray); + free_2(v); + } + } + free_2(obj->sorted); obj->sorted=NULL; + } + +if(obj->slisthier) { free_2(obj->slisthier); obj->slisthier=NULL; } +s=obj->slistroot; +while(s) + { + s2=s->next; + if(s->str)free_2(s->str); + free_2(s); + s=s2; + } + +obj->slistroot=obj->slistcurr=NULL; obj->slisthier_len=0; +queuedevents=NULL; /* deallocated in the symbol stuff */ + +if(obj->vcd_is_compressed) + { + pclose(obj->vcd_handle); + } + else + { + fclose(obj->vcd_handle); + } + +if(obj->yytext) + { + free_2(obj->yytext); + obj->yytext=NULL; + } +} + +/*******************************************************************************/ + +TimeType vcd_main(struct globals *obj, char *fname) +{ +int flen; + +obj->pv=obj->rootv=NULL; +obj->vcd_hier_delimeter[0]=obj->hier_delimeter; + +errno=0; /* reset in case it's set for some reason */ + +printf("Processing '%s'\n",fname); +obj->yytext=(char *)malloc_2(obj->T_MAX_STR+1); + +flen=strlen(fname); +if (((flen>2)&&(!strcmp(fname+flen-3,".gz")))|| + ((flen>3)&&(!strcmp(fname+flen-4,".zip")))) + { + char *str; + int dlen; + dlen=strlen(WAVE_DECOMPRESSOR); + str=wave_alloca(strlen(fname)+dlen+1); + strcpy(str,WAVE_DECOMPRESSOR); + strcpy(str+dlen,fname); + obj->vcd_handle=popen(str,"r"); + obj->vcd_is_compressed=~0; + } + else + { + if(strcmp("-vcd",fname)) + { + obj->vcd_handle=fopen(fname,"rb"); + } + else + { + obj->vcd_handle=stdin; + } + obj->vcd_is_compressed=0; + } + +if(!obj->vcd_handle) + { + fprintf(stderr, "Error opening %s .vcd file '%s'.\n", + obj->vcd_is_compressed?"compressed":"", fname); + exit(VCD_FAIL); + } + +getch_alloc(obj); /* alloc membuff for vcd getch buffer */ + +build_slisthier(obj); +vcd_parse(obj); +add_tail_histents(obj); + +vcd_build_symbols(obj); +vcd_sortfacs(obj); +vcd_cleanup(obj); + +printf("Found %d symbols.\n", obj->numfacs); +printf("["TTFormat"] start time.\n["TTFormat"] end time.\n", obj->start_time, obj->end_time); +if(obj->num_glitches) printf("Warning: encountered %d glitch%s across %d glitch region%s.\n", + obj->num_glitches, (obj->num_glitches!=1)?"es":"", + obj->num_glitch_regions, (obj->num_glitch_regions!=1)?"s":""); + +getch_free(obj); /* free membuff for vcd getch buffer */ + +obj->min_time=obj->start_time*obj->time_scale; +obj->max_time=obj->end_time*obj->time_scale; + +if(obj->min_time==obj->max_time) + { + fprintf(stderr, "VCD times range is equal to zero. Exiting.\n"); + exit(VCD_FAIL); + } + +return(obj->max_time); +} + +/*******************************************************************************/ diff --git a/ivtest/src/vcd.h b/ivtest/src/vcd.h new file mode 100644 index 000000000..de2970e7f --- /dev/null +++ b/ivtest/src/vcd.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) Tony Bybell 1999-2000. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#ifndef VCD_VCD_H +#define VCD_VCD_H + +#include +#include + +#ifndef _MSC_VER +#include +#endif + +#include +#include +#include +#include +#include "misc.h" +#include "alloca.h" +#include "debug.h" +#include "globals.h" + +#define VCD_BSIZ 32768 /* size of getch() emulation buffer--this val should be ok */ +#define VCD_FAIL 666 + +TimeType vcd_main(struct globals *obj, char *fname); +void append_vcd_slisthier(struct globals *obj, char *str); + +struct sym_chain +{ +struct sym_chain *next; +struct symbol *val; +}; + +struct slist +{ +struct slist *next; +char *str; +int len; +}; + + +struct vcdsymbol +{ +struct vcdsymbol *root, *chain; +struct symbol *sym_chain; + +struct vcdsymbol *next; +char *name; +char *id; +unsigned char vartype; +int msi, lsi; +int size; +char *value; +struct queuedevent *ev; /* only if vartype==V_EVENT */ +struct Node **narray; +}; + + +struct queuedevent +{ +struct queuedevent *next; +struct vcdsymbol *sym; +TimeType last_event_time; /* make +1 == 0 if there's not an event there too */ +}; + +extern char autocoalesce; +extern int vcd_explicit_zero_subscripts; /* 0=yes, -1=no */ +extern char convert_to_reals; +extern char atomic_vectors; +extern char hier_delimeter; + +extern TimeType currenttime; +extern TimeType max_time; +extern TimeType min_time; +extern char time_dimension; + +#endif diff --git a/ivtest/sv_regress.list b/ivtest/sv_regress.list new file mode 100644 index 000000000..dc834464a --- /dev/null +++ b/ivtest/sv_regress.list @@ -0,0 +1,71 @@ +# +# Copyright (c) 1999 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# +# Format of the file +# +# testname testtype directory +# +# The is the verilog file name minus an extension. It may contain +# an optional version prefix separated from the name with a ":". The test +# suite will use a version specific test instead of the default case. +# +# The can be one of the following: +# +# normal: Normal results expected, i.e it should compile and execute +# producing at least a single line with PASSED. +# +# CO: Compile Only - Compile the file to the default output type. +# +# CN: Compile Null - Compile with the null target. Similar to CO. +# +# CE: Compile with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# RE: Runtime with Errors - We EXPECT errors - we're checking +# illegal syntax +# +# EF: Expected fail - We EXPECT this test to fail - only use +# with older versions of Icarus. +# +# NI: Not implemented. Only use for version specific tests. +# +# is where the .v file is located. +# +# An optional fourth and fifth argument can be supplied. +# +# The fourth argument may be one of the following. +# +# modulename - Defines the top level module +# gold=filename - Compare a gold file against the generated log file. +# diff=filename1:filename2:skip_ln - Compare the two files for equality. +# Skip the first lines or none. +# +# If a is given you can supply a fifth argument for the +# gold or diff commands. +# + +struct_packed_write_read normal,-g2009 ivltests +struct_packed_value_list normal,-g2009 ivltests + +array_packed_write_read normal,-g2009 ivltests +array_packed_value_list normal,-g2009 ivltests +array_packed_sysfunct normal,-g2009 ivltests + +sv_literals normal,-g2009 ivltests +sv_parameter_type normal,-g2009 ivltests +sv_interface normal,-g2009 ivltests diff --git a/ivtest/update_msys2_report.pl b/ivtest/update_msys2_report.pl new file mode 100755 index 000000000..b77212ce0 --- /dev/null +++ b/ivtest/update_msys2_report.pl @@ -0,0 +1,90 @@ +#!/usr/bin/env perl +# +# Script to automatically generate regression_report-msys2.txt +# from regression_report-devel.txt and regress-msys2.list. + +#use strict; + +use lib './perl-lib'; + +use RegressionList; + +my $version = $ARGV[0] || 'devel'; + +read_regression_list("regress-msys2.list", "any", 0, ""); + +my $input_name = 'regression_report-' . $version . '.txt'; +open(my $input, '<', $input_name) + or die "ERROR - can't open '$input_name'"; + +my $output_name = 'regression_report-msys2-' . $version . '.txt'; +open(my $output, '>', $output_name) + or die "ERROR - can't open '$output_name'"; + +# Copy header. +my $line_count = 0; +while (my $line = <$input>) { + print $output $line; + last if ++$line_count == 2; +} + +# Output results for MSYS2 test exceptions. +my $passed = 0; +my $failed = 0; +my $not_impl = 0; +my $exp_fail = 0; +my %skip_test; +foreach my $name (@testlist) { + seek($input, 0, 0); + while (my $line = <$input>) { + my ($prefix, $result) = split(':', $line); + my $test_name = $prefix =~ s/^\s+//r; # strip leading spaces + next if $test_name ne $name; + if ($testtype{$test_name} eq "NI") { + print $output "$prefix: Not Implemented.\n"; + $not_impl++; + } elsif ($testtype{$test_name} eq "EF") { + print $output "$prefix: Passed - expected fail.\n"; + $exp_fail++; + } elsif ($testtype{$test_name} eq "CO") { + print $output "$prefix: Passed - CO.\n"; + $passed++; + } elsif ($testtype{$test_name} eq "CE") { + print $output "$prefix: Passed - CE.\n"; + $passed++; + } elsif ($testtype{$test_name} eq "RE") { + print $output "$prefix: Passed - RE.\n"; + $passed++; + } else { + print $output "$prefix: Passed.\n"; + $passed++; + } + } + $skip_test{$name} = 1; +} + +# Output remaining results. +seek($input, 0, 0); +while (my $line = <$input>) { + my ($prefix, $result) = split(':', $line); + next if !$result; + my $test_name = $prefix =~ s/^\s+//r; # strip leading spaces + next if $skip_test{$test_name}; + if ($line =~ /Not Implemented/) { + $not_impl++; + } elsif ($line =~ /expected fail/) { + $exp_fail++; + } elsif ($line =~ /Failed/) { + $failed++; + } elsif ($line =~ /Passed/) { + $passed++; + } else { + next; + } + print $output $line; +} + +my $total = $passed + $failed + $not_impl + $exp_fail; + +print $output "=" x 76 . "\n"; +print $output "Test results:\n Total=$total, Passed=$passed, Failed=$failed, Not Implemented=$not_impl, Expected Fail=$exp_fail\n"; diff --git a/ivtest/vhdl_gold/bitsel.gold b/ivtest/vhdl_gold/bitsel.gold new file mode 100644 index 000000000..4c91686e7 --- /dev/null +++ b/ivtest/vhdl_gold/bitsel.gold @@ -0,0 +1,8 @@ +bitsel.vhd:24:7:@0ms:(report note): '1' +bitsel.vhd:24:7:@0ms:(report note): '0' +bitsel.vhd:24:7:@0ms:(report note): '0' +bitsel.vhd:24:7:@0ms:(report note): '1' +bitsel.vhd:24:7:@0ms:(report note): '0' +bitsel.vhd:24:7:@0ms:(report note): '1' +bitsel.vhd:24:7:@0ms:(report note): '1' +bitsel.vhd:24:7:@0ms:(report note): '0' diff --git a/ivtest/vhdl_gold/function1.gold b/ivtest/vhdl_gold/function1.gold new file mode 100644 index 000000000..09b860b02 --- /dev/null +++ b/ivtest/vhdl_gold/function1.gold @@ -0,0 +1,2 @@ +function1.vhd:37:5:@0ms:(report note): 8 = sum(3, 5) +function1.vhd:38:5:@0ms:(report note): PASSED diff --git a/ivtest/vhdl_gold/mux2.gold b/ivtest/vhdl_gold/mux2.gold new file mode 100644 index 000000000..e0576b50a --- /dev/null +++ b/ivtest/vhdl_gold/mux2.gold @@ -0,0 +1,4 @@ +mux2.vhd:52:5:@0ms:(report note): 'U' +mux2.vhd:52:5:@0ms:(report note): '1' +mux2.vhd:52:5:@1ms:(report note): '0' +mux2.vhd:52:5:@2ms:(report note): '1' diff --git a/ivtest/vhdl_gold/signed4.gold b/ivtest/vhdl_gold/signed4.gold new file mode 100644 index 000000000..79fca4ff6 --- /dev/null +++ b/ivtest/vhdl_gold/signed4.gold @@ -0,0 +1,3 @@ +signed4.vhd:22:5:@0ms:(report note): x = 3 (should be 3) +signed4.vhd:24:5:@0ms:(report note): y = -3 (should be -3) +signed4.vhd:28:5:@0ms:(report note): x = 253 (should be 253) diff --git a/ivtest/vhdl_gold/simple_gen.gold b/ivtest/vhdl_gold/simple_gen.gold new file mode 100644 index 000000000..90c283de9 --- /dev/null +++ b/ivtest/vhdl_gold/simple_gen.gold @@ -0,0 +1,5 @@ +simple_gen.vhd:71:5:@1ms:(report note): 1 +simple_gen.vhd:72:5:@1ms:(report note): 2 +simple_gen.vhd:73:5:@1ms:(report note): 3 +simple_gen.vhd:74:5:@1ms:(report note): 4 +simple_gen.vhd:75:5:@1ms:(report note): 5 diff --git a/ivtest/vhdl_reg.pl b/ivtest/vhdl_reg.pl new file mode 100755 index 000000000..d1ea46f5a --- /dev/null +++ b/ivtest/vhdl_reg.pl @@ -0,0 +1,239 @@ +#!/usr/bin/env perl +# +# Regression script for VHDL output. Based on vvp_reg.pl. +# +# This script is based on code with the following Copyright. +# +# Copyright (c) 1999-2020 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +use lib './perl-lib'; + +use RegressionList; +use Diff; +use Reporting; +use Environment; + + +# +# Main script +# +&open_report_file('vhdl_regression_report.txt'); +my ($suffix, $strict, $with_valg, $force_sv) = &get_args; +my $ver = &get_ivl_version($suffix); +my $msg = $with_valg ? " (with valgrind)" : ""; +&print_rpt("Running VHDL tests for Icarus Verilog version: $ver$msg.\n"); +&print_rpt("-" x 70 . "\n"); +if ($#ARGV != -1) { + my $regress_fn = &get_regress_fn; + &read_regression_list($regress_fn, $ver, $force_sv, ""); +} else { + &read_regression_list("vhdl_regress.list", $ver, $force_sv, ""); +} +&execute_regression($suffix, $with_valg); +&close_report_file; + + +# +# execute_regression sequentially compiles and executes each test in +# the regression. It then checks that the output matches the gold file. +# +sub execute_regression { + my $sfx = shift(@_); + my $with_valg = shift(@_); + my ($tname, $total, $passed, $failed, $expected_fail, $not_impl, + $len, $cmd, $diff_file, $outfile, $unit); + + $total = 0; + $passed = 0; + $failed = 0; + $expected_fail = 0; + $not_impl = 0; + $len = 0; + + # Check for the VHDL output directory + mkdir 'vhdl' unless (-d 'vhdl'); + + foreach $tname (@testlist) { + $len = length($tname) if (length($tname) > $len); + } + + foreach $tname (@testlist) { + next if ($tname eq ""); # Skip test that have been replaced. + + $total++; + &print_rpt(sprintf("%${len}s: ", $tname)); + if ($diff{$tname} ne "" and -e $diff{$tname}) { + unlink $diff{$tname} or + die "Error: unable to remove old diff file $diff{$tname}.\n"; + } + if (-e "log/$tname.log") { + unlink "log/$tname.log" or + die "Error: unable to remove old log file log/$tname.log.\n"; + } + + if ($testtype{$tname} eq "NI") { + &print_rpt("Not Implemented.\n"); + $not_impl++; + next; + } + + # Store all the output in the vhdl subdirectory for debugging + $outfile = "vhdl/$tname.vhd"; + + # + # Build up the iverilog command line and run it. + # + $cmd = $with_valg ? "valgrind --trace-children=yes " : ""; + $cmd .= "iverilog$sfx -t vhdl -o $outfile $args{$tname}"; + $cmd .= " -s $testmod{$tname}" if ($testmod{$tname} ne ""); + $cmd .= " ./$srcpath{$tname}/$tname.v > log/$tname.log 2>&1"; + #print "$cmd\n"; + if (system("$cmd")) { + if ($testtype{$tname} eq "CE") { + # Check if the system command core dumped! + if ($? >> 8 & 128) { + &print_rpt("==> Failed - CE (core dump).\n"); + $failed++; + } else { + &print_rpt("Passed - CE.\n"); + $passed++; + } + next; + } + + # Check the log file for an un-translatable construct error + # We report this separately so we can distinguish between + # expected and unexpected failures + $cmd = "grep -q -i -E '(no vhdl translation|cannot be translated)' log/$tname.log"; + if (system($cmd) == 0) { + &print_rpt("==> Failed - No VHDL translation.\n"); + $not_impl++; + next; + } + else { + &print_rpt("==> Failed - running iverilog.\n"); + $failed++; + next; + } + } + + # + # Compile the output with GHDL + # + $cmd = "(cd vhdl ; ghdl -a $tname.vhd) >> log/$tname.log 2>&1"; + #print "$cmd\n"; + if (system("$cmd")) { + if ($testtype{$tname} eq "CE") { + # Check if the system command core dumped! + if ($? >> 8 & 128) { + &print_rpt("==> Failed - CE (core dump).\n"); + $failed++; + } else { + &print_rpt("Passed - CE.\n"); + $passed++; + } + next; + } + &print_rpt("==> Failed - running ghdl.\n"); + $failed++; + next; + } + + # The CO test type now includes compilation of the VHDL + if ($testtype{$tname} eq "CO") { + &print_rpt("Passed - CO.\n"); + $passed++; + next; + } + + # Try to guess the name of the primary VHDL unit + # ghdl -f lists all the units in a file: take the first one + ($unit) = `ghdl -f $outfile` =~ /^entity (\w+)/; + unless ($unit) { + &print_rpt("==> Failed -- cannot determine primary VHDL unit.\n"); + $failed++; + next; + } + #print "primary unit is $unit\n"; + + # Elaborate the primary unit to produce and executable + # Could elaborate and run in a single step, but this should + # provide better error detection. + $cmd = "(cd vhdl ; ghdl -e $unit) >> log/$tname.log 2>&1"; + #print "$cmd\n"; + if (system($cmd)) { + &print_rpt("==> Failed - running ghdl elaboration step.\n"); + $failed++; + next; + } + + # Finally, run the exectutable + $cmd = "(cd vhdl ; ghdl -r $unit --stop-delta=10000) >> log/$tname.log 2>&1"; + #print "$cmd\n"; + if (system($cmd)) { + if ($testtype{$tname} eq "RE") { + &print_rpt("Passed - RE.\n"); + $passed++; + next; + } + else { + # If the log contains `SIMULATION FINISHED' then + # this is OK + $cmd = "grep -q 'SIMULATION FINISHED' log/$tname.log"; + if (system($cmd)) { + &print_rpt("==> Failed - simulating VHDL.\n"); + $failed++; + next; + } + } + } + + if ($diff{$tname} ne "") { + $diff_file = $diff{$tname} + } else { + $diff_file = "log/$tname.log"; + } +# print "diff $gold{$tname}, $diff_file, $offset{$tname}\n"; + if (diff($gold{$tname}, $diff_file, $offset{$tname})) { + if ($testtype{$tname} eq "EF") { + &print_rpt("Passed - expected fail.\n"); + $expected_fail++; + next; + } + &print_rpt("==> Failed - output does not match gold file.\n"); + $failed++; + next; + } + + &print_rpt("Passed.\n"); + $passed++; + + } continue { + if ($tname ne "") { + # Remove GHDL temporary files + my $tmpfiles = './vhdl/*.o ./vhdl/work-obj93.cf'; + $tmpfiles .= " ./vhdl/$unit" if $unit; + system("rm -f $tmpfiles") and + die "Error: failed to remove temporary files.\n"; + } + } + + &print_rpt("=" x 70 . "\n"); + &print_rpt("Test results:\n Total=$total, Passed=$passed, Failed=$failed,". + " Not Implemented=$not_impl, Expected Fail=$expected_fail\n"); +} diff --git a/ivtest/vhdl_regress.list b/ivtest/vhdl_regress.list new file mode 100644 index 000000000..af7384f8c --- /dev/null +++ b/ivtest/vhdl_regress.list @@ -0,0 +1,346 @@ +hello1 normal ivltests + +mux2 normal vhdl_tests diff=log/mux2.log:vhdl_gold/mux2.gold +dff normal vhdl_tests +counter normal vhdl_tests +assign normal vhdl_tests +blocking normal vhdl_tests +constassign normal vhdl_tests +readout normal vhdl_tests +autof normal vhdl_tests +generics normal vhdl_tests + +partpv CO vhdl_tests + +case1 normal ivltests +case2 normal ivltests +case3 normal ivltests +case4 normal ivltests +case5 normal ivltests +case6 normal ivltests +case7 normal ivltests + +case3.8A normal ivltests +case3.8B normal ivltests +case3.8C normal ivltests +case3.8D normal ivltests + +blocksynth1 normal ivltests +casesynth1 normal ivltests +casesynth2 normal ivltests +casesynth3 normal ivltests +casex_synth normal ivltests + +dffsynth normal ivltests +dffsynth2 normal ivltests +dffsynth4 normal ivltests + +inside_synth3 normal ivltests + +memsynth1 normal ivltests +memsynth2 normal ivltests +memsynth3 normal ivltests +memsynth4 normal ivltests +memsynth5 normal ivltests +memsynth7 normal ivltests +memsynth8 normal ivltests +memsynth9 normal ivltests + +multireg normal ivltests +condit1 normal ivltests +conditsynth1 normal ivltests +conditsynth2 normal ivltests +conditsynth3 normal ivltests +basiclatch normal ivltests +basicstate normal ivltests +basicstate2 normal ivltests + +ssetclr1 normal ivltests +ssetclr2 normal ivltests +ssetclr3 normal ivltests + +always3.1.11A normal ivltests +always3.1.11B normal ivltests + +always3.1.1C normal ivltests +always3.1.1D normal ivltests +always3.1.1E normal ivltests +always3.1.1F normal ivltests + +always3.1.4A normal ivltests +always3.1.4D normal ivltests +always3.1.4E normal ivltests +always3.1.4G normal ivltests + +always3.1.5A normal ivltests +always3.1.5B normal ivltests +always3.1.5C normal ivltests +always3.1.5D normal ivltests +always3.1.5E normal ivltests +always3.1.5F normal ivltests + +always3.1.6D normal ivltests + +always3.1.7A normal ivltests +always3.1.7B normal ivltests +always3.1.7C normal ivltests +always3.1.7D normal ivltests + +always3.1.8A normal ivltests + +function3.11B normal ivltests +function3.11C normal ivltests +function3.11D normal ivltests +function3.11F normal ivltests + +module3.12A normal ivltests +module3.12B normal ivltests +muxtest normal ivltests + +ptest001 normal ivltests +ptest002 normal ivltests +ptest003 normal ivltests +ptest004 normal ivltests +ptest005 normal ivltests +ptest006 normal ivltests +ptest007 normal ivltests +ptest008 normal ivltests +ptest009 normal ivltests +ptest010 normal ivltests + +qmark normal ivltests +qmark1 normal ivltests +qmark3 normal ivltests +qmark5 normal ivltests +qmark6 normal ivltests + +sdw_always1 normal ivltests +sdw_always2 normal ivltests +sdw_always3 normal ivltests +sdw_assign normal ivltests +sdw_function1 normal ivltests +sdw_function2 noraml ivltests +sdw_function3 normal ivltests +sdw_function4 normal ivltests +sdw_function5 normal ivltests +sdw_task1 normal ivltests +sdw_task2 normal ivltests +sdw_int normal ivltests +sdw_lvalconcat2 normal ivltests +sdw_param1 normal ivltests +sdw_param2 normal ivltests +sdw_stmt002 normal ivltests +sdw_array normal ivltests +sdw_instmod1 normal ivltests +sdw_instmod2 normal ivltests +sdw_lvalconcat normal ivltests + +task3.14A normal ivltests +task3.14B normal ivltests +task3.14C normal ivltests +task3.14D normal ivltests +task3.14E normal ivltests + +z1 normal ivltests +z2 normal ivltests +landor1 normal ivltests +land2 normal ivltests +land3 normal ivltests +contrib8.1 normal ivltests +contrib8.2 normal ivltests +contrib8.4 normal ivltests +dff1 normal ivltests +fifo normal contrib +gencrc normal contrib +idiv2 normal ivltests +event_list2 normal ivltests +timescale1 normal ivltests + +integer1lt normal ivltests +integer2le normal ivltests +integer3gt normal ivltests +integer4ge normal ivltests + +time1 normal ivltests +time3 normal ivltests +time8 normal ivltests + +wireadd1 normal ivltests +wiresl normal ivltests +wiresr normal ivltests +wiresub1 normal ivltests +wirexor1 normal ivltests +wirele normal ivltests +wirege normal ivltests +wireeq normal ivltests + +andnot1 normal ivltests +constmult normal ivltests +constadd normal ivltests +constadd2 normal ivltests +constadd3 normal ivltests +consttern normal ivltests +talu normal ivltests + +udp_bufg normal ivltests +udp_bufg2 normal ivltests + +unary_not normal ivltests +unary_and normal ivltests +unary_nand normal ivltests +unary_nand2 normal ivltests +unary_or normal ivltests +unary_nor normal ivltests +unary_nor2 normal ivltests +unary_xor normal ivltests +unary_xnor1 normal ivltests +unary_xnor2 normal ivltests +unary_minus normal ivltests +unary_minus2 normal ivltests +unary_minus3 normal ivltests +unary_minus4 normal ivltests + +pr2224949 normal ivltests +pr2281479 normal ivltests +pr2281519 CO vhdl_tests +pr2147135a CO vhdl_tests +pr2147135b CO vhdl_tests +pr2391405 CO vhdl_tests +pr2362426 normal vhdl_tests + +ga_and normal ivltests +ga_or normal ivltests +ga_xor normal ivltests +ga_nand normal ivltests +ga_nor normal ivltests +ga_xnor normal ivltests + +binary_nand normal ivltests +binary_nor normal ivltests +rptconcat normal ivltests +rptconcat2 normal ivltests + +inout normal ivltests +modparam normal ivltests +port-test2 normal ivltests +scope2 normal ivltests +scope2b normal ivltests + +tri0 normal ivltests +tri0b normal ivltests +tri1 normal ivltests + +posedge normal ivltests +nblkorder normal ivltests +task_inpad normal ivltests +cond_band normal ivltests +cond_wide normal ivltests +cond_wide2 normal ivltests +wildsense normal ivltests +wildsense2 normal ivltests +assign_mem1 normal ivltests +meminit normal ivltests +meminit2 normal ivltests +task_noop normal ivltests +task_bypath normal ivltests +task_iotypes normal ivltests +assign_nb1 normal ivltests +assign_nb2 normal ivltests +assign_delay normal ivltests +define1 normal ivltests + +delay2 normal ivltests +delay3 normal ivltests +delay4 normal ivltests +delay5 normal ivltests +delay_assign_nb normal ivltests +delay_assign_nb2 normal ivltests +ldelay1 normal ivltests +ldelay2 normal ivltests +ldelay3 normal ivltests +ldelay5 normal ivltests + +wireland normal ivltests +param_concat normal ivltests +param_select normal ivltests +param_select2 normal ivltests +param_select3 normal ivltests +param_times normal ivltests + +function1 normal ivltests diff=log/function1.log:vhdl_gold/function1.gold +function_exp normal ivltests + +addsr normal ivltests +tern1 normal ivltests +tern4 normal ivltests +tern6 normal ivltests +tern7 normal ivltests +tern9 normal ivltests +tern10 normal ivltests +bnot normal ivltests +stask_parm1 normal ivltests +task_omemw2 normal ivltests + +lh_varindx2 normal ivltests +lh_varindx4 normal ivltests +lh_varindx5 normal ivltests +lh_catadd normal ivltests + +signed1 normal ivltests +signed2 normal ivltests +signed3 normal ivltests +signed4 noraml ivltests diff=log/signed4.log:vhdl_gold/signed4.gold +signed5 normal ivltests +signed6 normal ivltests +signed7 normal ivltests +signed9 normal ivltests +signed11 normal ivltests + +repeat2 normal ivltests +decl_assign1 normal ivltests + +shift2 normal ivltests + + +# Out of order from here + +pr1903520 normal ivltests +pr142 normal ivltests + +bitsel normal ivltests diff=log/bitsel.log:vhdl_gold/bitsel.gold +bitsel2 normal ivltests +bitsel3 normal ivltests +bitsel4 normal ivltests +bitsel5 normal ivltests + +select normal ivltests +uwire normal ivltests +xnor_test normal ivltests + +pr2202846a normal ivltests +pr2202846b normal ivltests +pr2202846c normal ivltests + +pr2489116 normal vhdl_tests +pr2489237 CO vhdl_tests +pr2516774 normal vhdl_tests +pr2516774b CO vhdl_tests +pr2527366 CO vhdl_tests +pr2529315 CO vhdl_tests +pr2529315b CO vhdl_tests +pr2531370 CO vhdl_tests +pr2526768 normal vhdl_tests +pr2536040 CO vhdl_tests +pr2541625 normal vhdl_tests +pr2534491 normal vhdl_tests +pr2554173 CO vhdl_tests +pr2555813 CO vhdl_tests +pr2555813b CO vhdl_tests +pr2554029 CO vhdl_tests +pr2554124 CO vhdl_tests +simple_gen normal vhdl_tests diff=log/simple_gen.log:vhdl_gold/simple_gen.gold +pr2911213 normal vhdl_tests +reserved normal vhdl_tests +pr2555831 normal vhdl_tests +pr2661101 normal vhdl_tests +pr3397689 normal vhdl_tests diff --git a/ivtest/vhdl_regression_report-devel.txt b/ivtest/vhdl_regression_report-devel.txt new file mode 100644 index 000000000..9ce2bda9e --- /dev/null +++ b/ivtest/vhdl_regression_report-devel.txt @@ -0,0 +1,299 @@ +Running VHDL tests for Icarus Verilog version: 0.10. +---------------------------------------------------------------------- + hello1: Passed. + mux2: Passed. + dff: Passed. + counter: Passed. + assign: Passed. + blocking: Passed. + constassign: Passed. + readout: Passed. + autof: Passed. + generics: Passed. + partpv: Passed - CO. + case1: Passed. + case2: Passed. + case3: Passed. + case4: Passed. + case5: Passed. + case6: Passed. + case7: Passed. + case3.8A: Passed. + case3.8B: Passed. + case3.8C: Passed. + case3.8D: Passed. + blocksynth1: Passed. + casesynth1: Passed. + casesynth2: Passed. + casesynth3: Passed. + casex_synth: Passed. + dffsynth: Passed. + dffsynth2: Passed. + dffsynth4: Passed. + inside_synth3: Passed. + memsynth1: Passed. + memsynth2: Passed. + memsynth3: Passed. + memsynth4: Passed. + memsynth5: Passed. + memsynth7: Passed. + memsynth8: Passed. + memsynth9: Passed. + multireg: Passed. + condit1: Passed. + conditsynth1: Passed. + conditsynth2: Passed. + conditsynth3: Passed. + basiclatch: Passed. + basicstate: Passed. + basicstate2: Passed. + ssetclr1: Passed. + ssetclr2: Passed. + ssetclr3: Passed. + always3.1.11A: Passed. + always3.1.11B: Passed. + always3.1.1C: Passed. + always3.1.1D: Passed. + always3.1.1E: Passed. + always3.1.1F: Passed. + always3.1.4A: Passed. + always3.1.4D: Passed. + always3.1.4E: Passed. + always3.1.4G: Passed. + always3.1.5A: Passed. + always3.1.5B: Passed. + always3.1.5C: Passed. + always3.1.5D: Passed. + always3.1.5E: Passed. + always3.1.5F: Passed. + always3.1.6D: Passed. + always3.1.7A: Passed. + always3.1.7B: Passed. + always3.1.7C: Passed. + always3.1.7D: Passed. + always3.1.8A: Passed. + function3.11B: Passed. + function3.11C: Passed. + function3.11D: Passed. + function3.11F: Passed. + module3.12A: Passed. + module3.12B: Passed. + muxtest: Passed. + ptest001: Passed. + ptest002: Passed. + ptest003: Passed. + ptest004: Passed. + ptest005: Passed. + ptest006: Passed. + ptest007: Passed. + ptest008: Passed. + ptest009: Passed. + ptest010: Passed. + qmark: Passed. + qmark1: Passed. + qmark3: Passed. + qmark5: Passed. + qmark6: Passed. + sdw_always1: Passed. + sdw_always2: Passed. + sdw_always3: Passed. + sdw_assign: Passed. + sdw_function1: Passed. + sdw_function2: Passed. + sdw_function3: Passed. + sdw_function4: Passed. + sdw_function5: Passed. + sdw_task1: Passed. + sdw_task2: Passed. + sdw_int: Passed. + sdw_lvalconcat2: Passed. + sdw_param1: Passed. + sdw_param2: Passed. + sdw_stmt002: Passed. + sdw_array: Passed. + sdw_instmod1: Passed. + sdw_instmod2: Passed. + sdw_lvalconcat: Passed. + task3.14A: Passed. + task3.14B: Passed. + task3.14C: Passed. + task3.14D: Passed. + task3.14E: Passed. + z1: Passed. + z2: Passed. + landor1: Passed. + land2: Passed. + land3: Passed. + contrib8.1: Passed. + contrib8.2: Passed. + contrib8.4: Passed. + dff1: Passed. + fifo: Passed. + gencrc: Passed. + idiv2: Passed. + event_list2: Passed. + timescale1: Passed. + integer1lt: Passed. + integer2le: Passed. + integer3gt: Passed. + integer4ge: Passed. + time1: Passed. + time3: Passed. + time8: Passed. + wireadd1: Passed. + wiresl: Passed. + wiresr: Passed. + wiresub1: Passed. + wirexor1: Passed. + wirele: Passed. + wirege: Passed. + wireeq: Passed. + andnot1: Passed. + constmult: Passed. + constadd: Passed. + constadd2: Passed. + constadd3: Passed. + consttern: Passed. + talu: Passed. + udp_bufg: Passed. + udp_bufg2: Passed. + unary_not: Passed. + unary_and: Passed. + unary_nand: Passed. + unary_nand2: Passed. + unary_or: Passed. + unary_nor: Passed. + unary_nor2: Passed. + unary_xor: Passed. + unary_xnor1: Passed. + unary_xnor2: Passed. + unary_minus: Passed. + unary_minus2: Passed. + unary_minus3: Passed. + unary_minus4: Passed. + pr2224949: Passed. + pr2281479: Passed. + pr2281519: Passed - CO. + pr2147135a: Passed - CO. + pr2147135b: Passed - CO. + pr2391405: Passed - CO. + pr2362426: Passed. + ga_and: Passed. + ga_or: Passed. + ga_xor: Passed. + ga_nand: Passed. + ga_nor: Passed. + ga_xnor: Passed. + binary_nand: Passed. + binary_nor: Passed. + rptconcat: Passed. + rptconcat2: Passed. + inout: Passed. + modparam: Passed. + port-test2: Passed. + scope2: Passed. + scope2b: Passed. + tri0: ==> Failed - output does not match gold file. + tri0b: ==> Failed - output does not match gold file. + tri1: ==> Failed - output does not match gold file. + posedge: Passed. + nblkorder: Passed. + task_inpad: Passed. + cond_band: Passed. + cond_wide: Passed. + cond_wide2: Passed. + wildsense: Passed. + wildsense2: Passed. + assign_mem1: Passed. + meminit: Passed. + meminit2: Passed. + task_noop: Passed. + task_bypath: Passed. + task_iotypes: Passed. + assign_nb1: Passed. + assign_nb2: Passed. + assign_delay: Passed. + define1: Passed. + delay2: Passed. + delay3: Passed. + delay4: Passed. + delay5: Passed. + delay_assign_nb: Passed. +delay_assign_nb2: Passed. + ldelay1: Passed. + ldelay2: Passed. + ldelay3: Passed. + ldelay5: Passed. + wireland: Passed. + param_concat: Passed. + param_select: Passed. + param_select2: Passed. + param_select3: Passed. + param_times: Passed. + function1: Passed. + function_exp: Passed. + addsr: Passed. + tern1: Passed. + tern4: Passed. + tern6: Passed. + tern7: Passed. + tern9: Passed. + tern10: Passed. + bnot: Passed. + stask_parm1: Passed. + task_omemw2: Passed. + lh_varindx2: Passed. + lh_varindx4: Passed. + lh_varindx5: Passed. + lh_catadd: Passed. + signed1: Passed. + signed2: Passed. + signed3: Passed. + signed4: Passed. + signed5: Passed. + signed6: Passed. + signed7: Passed. + signed9: Passed. + signed11: Passed. + repeat2: Passed. + decl_assign1: Passed. + shift2: Passed. + pr1903520: Passed. + pr142: Passed. + bitsel: Passed. + bitsel2: Passed. + bitsel3: Passed. + bitsel4: Passed. + bitsel5: Passed. + select: Passed. + uwire: Passed. + xnor_test: Passed. + pr2202846a: Passed. + pr2202846b: Passed. + pr2202846c: Passed. + pr2489116: Passed. + pr2489237: Passed - CO. + pr2516774: Passed. + pr2516774b: Passed - CO. + pr2527366: Passed - CO. + pr2529315: Passed - CO. + pr2529315b: Passed - CO. + pr2531370: Passed - CO. + pr2526768: Passed. + pr2536040: Passed - CO. + pr2541625: Passed. + pr2534491: Passed. + pr2554173: Passed - CO. + pr2555813: Passed - CO. + pr2555813b: Passed - CO. + pr2554029: Passed - CO. + pr2554124: Passed - CO. + simple_gen: Passed. + pr2911213: Passed. + reserved: Passed. + pr2555831: Passed. + pr2661101: Passed. + pr3397689: Passed. +====================================================================== +Test results: + Total=294, Passed=291, Failed=3, Not Implemented=0, Expected Fail=0 diff --git a/ivtest/vhdl_tests/assign.v b/ivtest/vhdl_tests/assign.v new file mode 100644 index 000000000..aac0c0a15 --- /dev/null +++ b/ivtest/vhdl_tests/assign.v @@ -0,0 +1,35 @@ +/* + * Basics tests of continuous assignment. + */ +module testbench(); + reg [3:0] a, b; + integer c, d; + wire [3:0] x, y, z; + + assign x = a + b + b; + assign y = b - a; + assign z = a + (a * b); + + initial begin + a <= 4'h2; + b <= 4'h3; + #1; + if (x !== 4'h8) + begin + $display("FAILED -- 2 + 3 + 3 !== 8"); + $finish; + end + if (y !== 4'h1) + begin + $display("FAILED -- 3 - 2 !== 1"); + $finish; + end + if (z !== 4'h8) + begin + $display("FAILED -- 2 + (2 * 3) !== 8"); + $finish; + end + $display("PASSED"); + end + +endmodule // testbench diff --git a/ivtest/vhdl_tests/autof.v b/ivtest/vhdl_tests/autof.v new file mode 100644 index 000000000..9ee401870 --- /dev/null +++ b/ivtest/vhdl_tests/autof.v @@ -0,0 +1,21 @@ +// This is a simple test of automatic functions +module autof(); + reg [7:0] result; + + function automatic [7:0] fact; + input [7:0] n; + if (n == 0) + fact = 1; + else + fact = n * fact(n-1); + endfunction // fact + + initial begin + result = fact(4); + if (result == 24) + $display("PASSED"); + else + $display("FAILED -- Expected 24 but got %d", result); + end + +endmodule // autof diff --git a/ivtest/vhdl_tests/blocking.v b/ivtest/vhdl_tests/blocking.v new file mode 100644 index 000000000..19ab017d0 --- /dev/null +++ b/ivtest/vhdl_tests/blocking.v @@ -0,0 +1,38 @@ +module testbench(); + reg [3:0] a, b; + + initial begin + a = 1; + b = 2; + #1; + a = a + b; + b = a + b; + if (a !== 3) + begin + $display("FAILED -- a !== 3"); + $finish; + end + if (b !== 5) + begin + $display("FAILED -- b !== 5"); + $finish; + end + #2; + $display("PASSED"); + end // initial begin + + initial begin + #2; + if (a !== 3) + begin + $display("FAILED -- a (signal) !== 3"); + $finish; + end + if (b !== 5) + begin + $display("FAILED -- b (signal) !== 5"); + $finish; + end + end + +endmodule // testbench diff --git a/ivtest/vhdl_tests/constassign.v b/ivtest/vhdl_tests/constassign.v new file mode 100644 index 000000000..400075159 --- /dev/null +++ b/ivtest/vhdl_tests/constassign.v @@ -0,0 +1,16 @@ +// A very simple test to check continuous assignment +// of a constant +module main(); + wire p; + + assign p = 1; + + initial begin + #1; + if (p == 1) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule // main diff --git a/ivtest/vhdl_tests/counter.v b/ivtest/vhdl_tests/counter.v new file mode 100644 index 000000000..b53a25b9a --- /dev/null +++ b/ivtest/vhdl_tests/counter.v @@ -0,0 +1,38 @@ +module testbench(); + wire [3:0] q; + reg clr, clk, enable; + + counter uut(q, clr, clk); + + always @(clk) + if (enable) + #1 clk <= !clk; + + initial begin + enable <= 1; + clk <= 0; + clr <= 1; + #2; + clr <= 0; + #7; + enable <= 0; + if (q == 4'b0011) + $display("PASSED"); + else + $display("FAILED -- counter not correct (%d)", q); + end + +endmodule // testbench + +module counter(q, clr, clk); + output [3:0] q; + input clr, clk; + reg [3:0] q; + + always @(posedge clk or posedge clr) + if (clr) + q <= 4'b0000; + else + q <= q + 1'b1; + +endmodule // counter diff --git a/ivtest/vhdl_tests/dff.v b/ivtest/vhdl_tests/dff.v new file mode 100644 index 000000000..5a33b57ee --- /dev/null +++ b/ivtest/vhdl_tests/dff.v @@ -0,0 +1,64 @@ +/* + * A D-type flip-flop to check synchronous logic works + * correctly. + */ + +module testbench; + reg d, clk, rst, enable; + wire q, q_bar; + + dff uut(q, q_bar, d, clk, rst); + + initial clk <= 0; + + always @(clk) + if (enable) + #1 clk <= !clk; + + initial begin + enable <= 1; + rst <= 1; + d <= 1'bx; + #2; + if (q !== 0) + begin + $display("FAILED -- Not reset"); + $finish; + end + rst <= 0; + d <= 1'b1; + #2; + if (q !== 1) + begin + $display("FAILED -- q not 1 as expected"); + $finish; + end + d <= 1'b0; + #2; + if (q !== 0) + begin + $display("FAILED -- q not 0 as expected"); + $finish; + end + rst <= 1; + #2; + enable <= 0; // Alternative to using $finish + $display("PASSED"); + end + +endmodule // testbench + +module dff(q, q_bar, d, clk, rst); + output q, q_bar; + input d, clk, rst; + reg q; + + always @(posedge clk or posedge rst) + if (rst) + q <= 1'b0; + else + q <= d; + + not(q_bar, q); + +endmodule // dff diff --git a/ivtest/vhdl_tests/generics.v b/ivtest/vhdl_tests/generics.v new file mode 100644 index 000000000..2a3d0dd67 --- /dev/null +++ b/ivtest/vhdl_tests/generics.v @@ -0,0 +1,52 @@ +// A few simple tests of translating parameters to generics +module top(); + wire [7:0] v1, v2, v3; + wire [7:0] w1, w2, w3; + + child c1(v1, w1); + child c2(v2, w2); + child c3(v3, w3); + + defparam c1.MY_VALUE = 6; + defparam c2.MY_VALUE = 44; + + initial begin + #2; + $display("c1 reg value: %d", v1); + $display("c2 reg value: %d", v2); + $display("c3 reg value: %d", v3); + $display("c1 wire value: %d", w1); + $display("c2 wire value: %d", w2); + $display("c3 wire value: %d", w3); + if (v1 !== 6) + $display("FAILED - v1 !== 6"); + else if (v2 !== 44) + $display("FAILED - v2 !== 44"); + else if (v3 !== 12) + $display("FAILED - v3 !== 12"); + else if (w1 !== 7) + $display("FAILED - v1 !== 7"); + else if (w2 !== 45) + $display("FAILED - v2 !== 45"); + else if (w3 !== 13) + $display("FAILED - v3 !== 13"); + else + $display("PASSED"); + end + +endmodule // top + +module child(value, value_w); + output [7:0] value, value_w; + reg [7:0] value; + + parameter MY_VALUE = 12; + + assign value_w = MY_VALUE + 1; + + // Make a non-trivial process + initial begin + #1; + value <= MY_VALUE; + end +endmodule // child diff --git a/ivtest/vhdl_tests/mux2.v b/ivtest/vhdl_tests/mux2.v new file mode 100644 index 000000000..c562ecdcc --- /dev/null +++ b/ivtest/vhdl_tests/mux2.v @@ -0,0 +1,37 @@ +/* + * A simple test of some of the structural elements. + */ + +module testbench; + wire o; + reg i0, i1, sel; + + mux2 uut(o, i0, i1, sel); + + initial begin + i0 <= 1; + i1 <= 0; + sel <= 0; + #1; + sel <= 1; + #1; + i1 <= 1; + #1; + end + + always @(o) + $display(o); + +endmodule // testbench + +module mux2(c, a, b, s); + input a, b, s; + output c; + wire s_bar, a_and_s_bar, b_and_s; + + not(s_bar, s); + and(a_and_s_bar, a, s_bar); + and(b_and_s, b, s); + or(c, a_and_s_bar, b_and_s); + +endmodule // mux2 diff --git a/ivtest/vhdl_tests/partpv.v b/ivtest/vhdl_tests/partpv.v new file mode 100644 index 000000000..1dabf6da5 --- /dev/null +++ b/ivtest/vhdl_tests/partpv.v @@ -0,0 +1,15 @@ +// This test is intended to generate a IVL_LPM_SELECT_PV +// in the `b' port map + +module top; + + wire [7:0] foo; + + bot b( .q(foo[3:0]) ); + +endmodule // top + +module bot(q); + output [3:0] q; + +endmodule diff --git a/ivtest/vhdl_tests/pr2147135a.v b/ivtest/vhdl_tests/pr2147135a.v new file mode 100644 index 000000000..8cb89b01e --- /dev/null +++ b/ivtest/vhdl_tests/pr2147135a.v @@ -0,0 +1,11 @@ +module test(); + wire d; + wire [5:0] f; + b u1 (.c({d, f})); +endmodule + +module b (c); + +output [6:0] c; + +endmodule diff --git a/ivtest/vhdl_tests/pr2147135b.v b/ivtest/vhdl_tests/pr2147135b.v new file mode 100644 index 000000000..2d5c65f15 --- /dev/null +++ b/ivtest/vhdl_tests/pr2147135b.v @@ -0,0 +1,16 @@ +module test( clk, a, b ); + +input clk; +output [0:0] a; + output b; +reg [0:0] a; + reg b; + +integer i = 5; + +always @(posedge clk) begin + a[i] <= 1'b0; + b <= 1'b0; +end + +endmodule diff --git a/ivtest/vhdl_tests/pr2281519.v b/ivtest/vhdl_tests/pr2281519.v new file mode 100644 index 000000000..6bbff5b66 --- /dev/null +++ b/ivtest/vhdl_tests/pr2281519.v @@ -0,0 +1,8 @@ +module test(); + wire clk; + reg [8:0] lowp2_tmp; + reg [8:0] lowp2_out; + always @(posedge clk) begin + lowp2_out <= ( {lowp2_tmp[8], lowp2_tmp} ) >> 1; + end +endmodule diff --git a/ivtest/vhdl_tests/pr2362426.v b/ivtest/vhdl_tests/pr2362426.v new file mode 100644 index 000000000..d3f35e36e --- /dev/null +++ b/ivtest/vhdl_tests/pr2362426.v @@ -0,0 +1,32 @@ +module test(); +reg c; + + a #(1) ua( .c(c), .b(h)); + + initial begin + c = 0; + #1 c = 1; + #1 c = 0; + $display("PASSED"); + end + +endmodule +module a( + c, + b, + ); + parameter e = 2; + + input c; + output [e-1:0] b; + + reg [e-1:0] f; + reg [e-1:0] g; + reg [e-1:0] b; + integer d; + + always @(posedge c) begin + for(d=0; d 0; n = n - 1) begin + fact = fact * n; + end + endfunction // for + + initial begin + r = fact(5); + $display("fact(5) = %d", r); + if (r == 120) + $display("PASSED"); + else + $display("FAILED"); + end +endmodule // top diff --git a/ivtest/vhdl_tests/pr2516774b.v b/ivtest/vhdl_tests/pr2516774b.v new file mode 100644 index 000000000..69beac1c0 --- /dev/null +++ b/ivtest/vhdl_tests/pr2516774b.v @@ -0,0 +1,80 @@ +// This slightly convoluted module used to cause an argument-size +// mismatch in the call to the function extend_data + +module test (c); + + parameter MAX_SIZE = 32; + + input c; + + reg [MAX_SIZE-1:0] d, + e, + f; + reg [7:0] g; + + wire h; + + always @(posedge h or negedge c) + if (~c) + f <= #2 {MAX_SIZE{1'b0}}; + else + case (g) + 8'h18 : + f <= #2 hw(d, e); + default : + f <= #2 {MAX_SIZE{1'b0}}; + endcase + + parameter FALSE_RESULT = {MAX_SIZE{1'b0}}, + TRUE_RESULT = FALSE_RESULT | 1'b1; + + function integer sign_of; + + input [2*MAX_SIZE-1:0] data; + input size; + + reg [2*MAX_SIZE-1:0] data; + integer size; + + if (data[size-1]===1'b1) + sign_of = -1; + else + sign_of = 1; + endfunction + + function [2*MAX_SIZE-1:0] extend_data; + + input [2*MAX_SIZE-1:0] data; + input size; + input new_size; + input extend; + + reg [2*MAX_SIZE-1:0] data; + integer size, + new_size; + reg extend; + + for (extend_data = data ; new_size-size>0 ; new_size=new_size-1) + extend_data[new_size-1] = extend & data[size-1]; + endfunction + + function [MAX_SIZE-1:0] hw; + input [MAX_SIZE-1:0] a; + input [MAX_SIZE-1:0] b; + + reg [MAX_SIZE-1:0] a, + b; + + reg [MAX_SIZE:0] diff; + + begin + diff = extend_data(b, MAX_SIZE, MAX_SIZE+1, 1'b1) - + extend_data(a, MAX_SIZE, MAX_SIZE+1, 1'b1); + if (sign_of(diff, MAX_SIZE+1)==-1) + hw = TRUE_RESULT; + else + hw = FALSE_RESULT; + end + endfunction + +endmodule diff --git a/ivtest/vhdl_tests/pr2526768.v b/ivtest/vhdl_tests/pr2526768.v new file mode 100644 index 000000000..0836f59c4 --- /dev/null +++ b/ivtest/vhdl_tests/pr2526768.v @@ -0,0 +1,57 @@ +module top(); + wire [7:0] Z, CO; + reg [7:0] A, B, CI; + reg ok; + + test test(Z, CO, A, B, CI); + + task check; + input [7:0] want_z, want_co; + begin + $display("A = %d, B = %d, CI = %d", A, B, CI); + $display("==> Z = %d, CO = %d", Z, CO); + $display("??? Z = %d, CO = %d", want_z, want_co); + if (want_co !== CO || want_z !== Z) begin + $display("FAILED"); + ok = 0; + end + $display; + end + endtask // check + + + initial begin + ok = 1; + A = 0; + B = 0; + CI = 0; + #1 check(0, 0); + + A = 4; + #1 check(4, 0); + + B = 251; + #1 check(255, 0); + + if (ok) + $display("PASSED"); + end + +endmodule // top + +module test (Z, CO, A, B, CI); + parameter width=8; + + input [width-1:0] A, B, CI; + output [width-1:0] Z, CO; + + reg [width-1:0] Z, CO; + + integer i; + + always @(A or B or CI) begin + for(i=0; i < width; i=i+1) + {CO[i],Z[i]} = A[i] + B[i] + CI[i]; + end + +endmodule diff --git a/ivtest/vhdl_tests/pr2527366.v b/ivtest/vhdl_tests/pr2527366.v new file mode 100644 index 000000000..1f5187f27 --- /dev/null +++ b/ivtest/vhdl_tests/pr2527366.v @@ -0,0 +1,6 @@ +module test(input b); + a ua(.BISTEA(b), .BISTEB(b)); +endmodule // test + +module a (input BISTEA, input BISTEB); +endmodule // a diff --git a/ivtest/vhdl_tests/pr2529315.v b/ivtest/vhdl_tests/pr2529315.v new file mode 100644 index 000000000..726488713 --- /dev/null +++ b/ivtest/vhdl_tests/pr2529315.v @@ -0,0 +1,16 @@ +module test ( +input clk_dma, +input rst_dma_n, + +input wr_valid, +input wr_trans, +input wr_flush, + +output wr_ready); + +wire buf_wr_wstrb; + +assign buf_wr_wstrb = wr_ready && wr_valid; +assign wr_ready = wr_flush ; + +endmodule diff --git a/ivtest/vhdl_tests/pr2529315b.v b/ivtest/vhdl_tests/pr2529315b.v new file mode 100644 index 000000000..04d9dd0f1 --- /dev/null +++ b/ivtest/vhdl_tests/pr2529315b.v @@ -0,0 +1,72 @@ +module test ( + Z, + CO32, + A, + B, + CI); + +input[63:0] A; +input[63:0] B; +input CI; +output[63:0] Z; +output CO32; + +wire[31:0] Z1; +wire[31:0] Z2; + +adder32 add0( + .Z(Z[31:0]), + .A(A[31:0]), + .B(B[31:0]), + .CI(CI)); + +carry32 car0( + .CO (CO32), + .A (A[31:0]), + .B (B[31:0]), + .CI (CI)); + +adder32 add1( + .Z (Z1), + .A (A[63:32]), + .B (B[63:32]), + .CI (1'b0)); + +adder32 add2( + .Z (Z2), + .A (A[63:32]), + .B (B[63:32]), + .CI (1'b1)); + +assign Z[63:32] = CO32 ? Z2 : Z1; + +endmodule +module adder32 ( + Z, + A, + B, + CI); + +input[31:0] A; +input[31:0] B; +input CI; +output [31:0] Z; + +assign Z = A + B + CI; + +endmodule +module carry32 ( + CO, + A, + B, + CI); + +input[31:0] A; +input[31:0] B; +input CI; +output CO; + +wire[31:0] unused; +assign {CO, unused} = A + B + CI; + +endmodule diff --git a/ivtest/vhdl_tests/pr2531370.v b/ivtest/vhdl_tests/pr2531370.v new file mode 100644 index 000000000..537ef5402 --- /dev/null +++ b/ivtest/vhdl_tests/pr2531370.v @@ -0,0 +1,5 @@ +module test(); + +initial + $display("Error: %m"); +endmodule diff --git a/ivtest/vhdl_tests/pr2534491.v b/ivtest/vhdl_tests/pr2534491.v new file mode 100644 index 000000000..d380429b8 --- /dev/null +++ b/ivtest/vhdl_tests/pr2534491.v @@ -0,0 +1,14 @@ +module test (); + + initial begin : local_vars + integer i, sum; + sum = 0; + for (i = 1; i <= 10; i = i + 1) + sum = sum + i; + $display("sum(1..10) = %d", sum); + if (sum == 55) + $display("PASSED"); + else + $display("FAILED"); + end +endmodule diff --git a/ivtest/vhdl_tests/pr2536040.v b/ivtest/vhdl_tests/pr2536040.v new file mode 100644 index 000000000..197ed1a90 --- /dev/null +++ b/ivtest/vhdl_tests/pr2536040.v @@ -0,0 +1,4 @@ +module test ( input a, input _b_, output A, output b__); + assign A = a; + assign b__ = _b_; +endmodule diff --git a/ivtest/vhdl_tests/pr2541625.v b/ivtest/vhdl_tests/pr2541625.v new file mode 100644 index 000000000..9651669eb --- /dev/null +++ b/ivtest/vhdl_tests/pr2541625.v @@ -0,0 +1,24 @@ +module top(); + wire out1, out2; + + child c1(1, 0, out1); + child c2(1, 1, out2); + + initial begin + #1; + if (out1 !== 0) + $display("FAILED -- out1 !== 0"); + else if (out2 !== 1) + $display("FAILED -- out2 !== 1"); + else + $display("PASSED"); + end + +endmodule // top + +module child(in1, in2, out); + input in1, in2; + output out; + + assign out = in1 & in2; +endmodule // child diff --git a/ivtest/vhdl_tests/pr2554029.v b/ivtest/vhdl_tests/pr2554029.v new file mode 100644 index 000000000..9d9b4f90c --- /dev/null +++ b/ivtest/vhdl_tests/pr2554029.v @@ -0,0 +1,11 @@ +module test(); + a a (.pi(pi)); +endmodule // test + +module a(input pi); + assign Pi = pi; + b b(.Pi(Pi)); +endmodule // a + +module b(input Pi); +endmodule diff --git a/ivtest/vhdl_tests/pr2554124.v b/ivtest/vhdl_tests/pr2554124.v new file mode 100644 index 000000000..eb09fdad4 --- /dev/null +++ b/ivtest/vhdl_tests/pr2554124.v @@ -0,0 +1,10 @@ +module test(); + wire b; + a a( .b_buf(b), + .b (b)); +endmodule // test + + +module a(output b_buf, input b); + assign b_buf = 1'b0; +endmodule // a diff --git a/ivtest/vhdl_tests/pr2554173.v b/ivtest/vhdl_tests/pr2554173.v new file mode 100644 index 000000000..bde05896d --- /dev/null +++ b/ivtest/vhdl_tests/pr2554173.v @@ -0,0 +1,10 @@ +module test(); + a a_( + .b_buf(b), + .b (b) + ); +endmodule // test + +module a(b, b_buf); + input b, b_buf; +endmodule // a_ diff --git a/ivtest/vhdl_tests/pr2555813.v b/ivtest/vhdl_tests/pr2555813.v new file mode 100644 index 000000000..8d6adf78e --- /dev/null +++ b/ivtest/vhdl_tests/pr2555813.v @@ -0,0 +1,12 @@ +module test(); + wire a, b; + a__a a_( + .b_buf(b), + .b (a) + ); +endmodule + +module a__a(b_buf, b); +output b_buf; +input b; +endmodule diff --git a/ivtest/vhdl_tests/pr2555813b.v b/ivtest/vhdl_tests/pr2555813b.v new file mode 100644 index 000000000..5ba2e05b8 --- /dev/null +++ b/ivtest/vhdl_tests/pr2555813b.v @@ -0,0 +1,12 @@ +module test(); + wire x, y; +a__a a_( +.b_buf(y), +.b (x) +); +endmodule + +module a__a(b_buf, b); +output b_buf; +input b; +endmodule // a__a diff --git a/ivtest/vhdl_tests/pr2555831.v b/ivtest/vhdl_tests/pr2555831.v new file mode 100644 index 000000000..53015a312 --- /dev/null +++ b/ivtest/vhdl_tests/pr2555831.v @@ -0,0 +1,31 @@ +module top (); + reg [31:0] din; + wire [31:0] dout; + + test t(din, dout); + + initial begin + din = 5; + #1; + $display("dout=%d", dout); + if (dout == 5) + $display("PASSED"); + else + $display("FAILED"); + end + +endmodule // top + +module test ( din, dout); + input [31:0] din; + output [31:0] dout; + buff #(1) d0_1 ( .in(din[0:0]), .out(dout[0:0])); + buff #(32) d0_32 ( .in(din[31:0]), .out(dout[31:0])); +endmodule // test + +module buff (out, in); + parameter SIZE=1; + output [SIZE-1:0] out; + input [SIZE-1:0] in; + assign out[SIZE-1:0] = in[SIZE-1:0]; +endmodule // buff diff --git a/ivtest/vhdl_tests/pr2661101.v b/ivtest/vhdl_tests/pr2661101.v new file mode 100644 index 000000000..613785192 --- /dev/null +++ b/ivtest/vhdl_tests/pr2661101.v @@ -0,0 +1,20 @@ +module top(); + reg [7:0] a, a_a, a__a; + + initial begin + a = 1; + #1; + a_a = 2; + #1; + a__a = 3; + #1; + + if (a == 1 && a_a == 2 && a__a == 3) + $display("PASSED"); + else + $display("FAILED"); + + $finish; + end + +endmodule // top diff --git a/ivtest/vhdl_tests/pr2911213.v b/ivtest/vhdl_tests/pr2911213.v new file mode 100644 index 000000000..1330d76db --- /dev/null +++ b/ivtest/vhdl_tests/pr2911213.v @@ -0,0 +1,48 @@ +module top(); + + reg [3:0] a; + reg [4:0] b; + wire [8:0] y; + + functest uut(a, b, y); + + initial begin + a = 3'b101; + b = 4'b0101; + #1; + if (y == 8'b10100101) + $display("PASSED"); + else + $display("FAILED y = %b", y); + end + +endmodule // top + + +module functest ( + operand_a, + operand_b, + + result_y + ); + + input [3:0] operand_a; + input [4:0] operand_b; + output [8:0] result_y; + + function [8:0] concat_this; + input [3:0] op_s; + input [4:0] op_l; + + concat_this = {op_s, op_l}; + endfunction + + reg [8:0] result_y_wire; + +always @ (operand_a or operand_b) begin + result_y_wire = concat_this(operand_a, operand_b); +end + +assign result_y = result_y_wire; + +endmodule diff --git a/ivtest/vhdl_tests/pr3397689.v b/ivtest/vhdl_tests/pr3397689.v new file mode 100644 index 000000000..b4a9e1fad --- /dev/null +++ b/ivtest/vhdl_tests/pr3397689.v @@ -0,0 +1,59 @@ +module top(); + reg p_clk, rst_in, reg_req_t; + wire out; + + weird_ff uut(p_clk, rst_in, reg_req_t, out); + + initial begin + p_clk = 0; + rst_in = 1; + reg_req_t = 0; + #1; + rst_in = 0; + #1; + p_clk = 1; + #2; + p_clk = 0; + $display("%d", out); + if (out != 1'bx) begin + $display("FAILED 1 - ff was reset"); + $finish; + end + #1; + rst_in = 1; + #1; + p_clk = 1; + #1; + p_clk = 0; + $display("%d", out); + if (out != 1'b0) begin + $display("FAILED 2 - ff was not reset"); + $finish; + end + $display("PASSED"); + end + +endmodule // top + +module weird_ff(p_clk, rst_in, reg_req_t, out); + input p_clk; + input rst_in; + input reg_req_t; + output out; + + reg [1:0] wr_req_pipe; + + parameter G_ASYNC_RESET = 0; + + wire a_rst = (G_ASYNC_RESET != 0) ? rst_in : 1'b0; + wire s_rst = (G_ASYNC_RESET == 0) ? rst_in : 1'b0; + + always @(posedge p_clk or posedge a_rst) + if (a_rst | s_rst) + wr_req_pipe <= 'b0; + else + wr_req_pipe <= {wr_req_pipe, reg_req_t}; + + assign out = wr_req_pipe[1]; + +endmodule // weird_ff diff --git a/ivtest/vhdl_tests/readout.v b/ivtest/vhdl_tests/readout.v new file mode 100644 index 000000000..f20976790 --- /dev/null +++ b/ivtest/vhdl_tests/readout.v @@ -0,0 +1,32 @@ +// This causes GHDL to fail with 'port "p" cannot be read' +// since the code generator does not yet identify p as an +// internal signal as well as a port. +module top; + wire ign; + + a inst(ign); + +endmodule // top + +module a(p); + output p; + + b inst(p); + + initial begin + #1; + if (p !== 1) + $display("FAILED -- p !== 1"); + else + $display("PASSED"); + $finish; + end + +endmodule // a + +module b(q); + output q; + + assign q = 1; + +endmodule // b diff --git a/ivtest/vhdl_tests/reserved.v b/ivtest/vhdl_tests/reserved.v new file mode 100644 index 000000000..277a6020e --- /dev/null +++ b/ivtest/vhdl_tests/reserved.v @@ -0,0 +1,16 @@ +module top(); + + register loop(); + process signal(); + +endmodule // top + +module register(); + +endmodule // register + +module process(); + + initial $display("PASSED"); + +endmodule // process diff --git a/ivtest/vhdl_tests/simple_gen.v b/ivtest/vhdl_tests/simple_gen.v new file mode 100644 index 000000000..16046af5e --- /dev/null +++ b/ivtest/vhdl_tests/simple_gen.v @@ -0,0 +1,30 @@ +// A simple generate example for VHDL conversion +module main(); + wire [39:0] data; + integer j; + + generate + genvar i; + for (i = 0; i < 4; i = i + 1) begin + inc u(data[(i+1)*8 - 1:i*8], data[(i+2)*8 - 1:(i+1)*8]); + end + endgenerate + + assign data[7:0] = 1; + + initial begin + #1; + $display(data[7:0]); + $display(data[15:8]); + $display(data[23:16]); + $display(data[31:24]); + $display(data[39:32]); + end +endmodule // simple_gen + +module inc(in, out); + input [7:0] in; + output [7:0] out; + + assign out = in + 1; +endmodule // inc diff --git a/ivtest/vlog95_reg.pl b/ivtest/vlog95_reg.pl new file mode 100755 index 000000000..47056014d --- /dev/null +++ b/ivtest/vlog95_reg.pl @@ -0,0 +1,294 @@ +#!/usr/bin/env perl +# +# Script to handle regression for normal Verilog files. +# +# This script is based on code with the following Copyright. +# +# Copyright (c) 1999-2020 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +use lib './perl-lib'; + +use RegressionList; +use Diff; +use Reporting; +use Environment; + + +# +# Main script +# +&open_report_file; +my ($suffix, $strict, $with_valg, $force_sv) = &get_args; +my $ver = &get_ivl_version($suffix); +my $opt = $force_sv ? " (force SV)" : ""; +my $msg = $with_valg ? " (with valgrind)" : ""; +&print_rpt("Running vlog95 compiler/VVP tests for Icarus Verilog " . + "version: $ver$opt$msg.\n"); +&print_rpt("-" x 76 . "\n"); +if ($#ARGV != -1) { + my $regress_fn = &get_regress_fn; + &read_regression_list($regress_fn, $ver, $force_sv, ""); + +} else { + if ($force_sv) { + &read_regression_list("regress-fsv.list", $ver, $force_sv, ""); + } + &read_regression_list("regress-vlog95.list", $ver, $force_sv, ""); + &read_regression_list("regress-v$ver.list", $ver, $force_sv, ""); + &read_regression_list("regress-ivl2.list", $ver, $force_sv, ""); + &read_regression_list("regress-ivl1.list", $ver, $force_sv, ""); + &read_regression_list("regress-vlg.list", $ver, $force_sv, ""); + &read_regression_list("regress-vams.list", $ver, $force_sv, ""); + if ($ver >= 10) { + &read_regression_list("regress-sv.list", $ver, $force_sv, ""); + &read_regression_list("regress-vhdl.list", $ver, $force_sv, ""); + } + if ($ver == 0.9) { + &read_regression_list("regress-synth.list", $ver, $force_sv, ""); + } else { + &read_regression_list("regress-synth.list", $ver, $force_sv, "-S"); + } +} +&execute_regression($suffix, $with_valg); +&close_report_file; + + +# +# execute_regression sequentially compiles and executes each test in +# the regression. It then checks that the output matches the gold file. +# +sub execute_regression { + my $sfx = shift(@_); + my $with_valg = shift(@_); + my ($tname, $total, $passed, $failed, $expected_fail, $not_impl, + $len, $cmd, $diff_file); + + $total = 0; + $passed = 0; + $failed = 0; + $expected_fail = 0; + $not_impl = 0; + $len = 0; + + foreach $tname (@testlist) { + $len = length($tname) if (length($tname) > $len); + } + + # Make sure we have a log and work directory. + if (! -d 'log') { + mkdir 'log' or die "Error: unable to create log directory.\n"; + } + if (! -d 'work') { + mkdir 'work' or die "Error: unable to create work directory.\n"; + } + + foreach $tname (@testlist) { + my $pass_type; + next if ($tname eq ""); # Skip test that have been replaced. + + $total++; + &print_rpt(sprintf("%${len}s: ", $tname)); + if ($diff{$tname} ne "" and -e $diff{$tname}) { + unlink $diff{$tname} or + die "Error: unable to remove old diff file $diff{$tname}.\n"; + } + if (-e "log/$tname.log") { + unlink "log/$tname.log" or + die "Error: unable to remove old log file log/$tname.log.\n"; + } + + if ($testtype{$tname} eq "NI") { + &print_rpt("Not Implemented.\n"); + $not_impl++; + next; + } + + if (! -e "./$srcpath{$tname}/$tname.v") { + &print_rpt("Failed - missing source file.\n"); + $failed++; + next; + } + + # + # Build up the iverilog command line and run it. + # + $pass_type = 0; + $cmd = $with_valg ? "valgrind --trace-children=yes " : ""; + $cmd .= "iverilog$sfx -o vlog95.v"; + $cmd .= " -s $testmod{$tname}" if ($testmod{$tname} ne ""); + $cmd .= $testtype{$tname} eq "CN" ? " -t null" : " -t vlog95"; + $cmd .= " -pfileline=1 -pspacing=4" if ($testtype{$tname} ne "CN"); + $cmd .= " -D__ICARUS_UNSIZED__ $args{$tname}"; + $cmd .= " ./$srcpath{$tname}/$tname.v > log/$tname.log 2>&1"; +# print "$cmd\n"; + if (system("$cmd")) { + if ($testtype{$tname} eq "CE") { + # Check if the system command core dumped! + if ($? >> 8 & 128) { + &print_rpt("==> Failed - CE (core dump).\n"); + $failed++; + next; + } else { + $pass_type = 1; + } + } else { + &print_rpt("==> Failed - running iverilog.\n"); + $failed++; + next; + } + } else { + if ($testtype{$tname} eq "CE") { + &print_rpt("==> Failed - CE (no error reported).\n"); + $failed++; + next; + } + } + + if ($testtype{$tname} eq "CO") { + &print_rpt("Passed - CO.\n"); + $passed++; + next; + } + if ($testtype{$tname} eq "CN") { + &print_rpt("Passed - CN.\n"); + $passed++; + next; + } + + # Run the translated Verilog code. All compile errors should + # already be handled. Remove the -S flag if it exists along + # with any included source file(s) and any -f arguments. The + # -pallowsigned flag and the various generation flags should + # also be removed. If we had -pallowsigned=1 then use the + # -g2001-noconfig to get signed/unsigned otherwise use -g1995. + my $gen_flag; + if($args{$tname} =~ m/-pallowsigned=1/) { + $gen_flag = "-g2001-noconfig"; + } else { + $gen_flag = "-g1995"; + } + $args{$tname} =~ s/-S//; + $args{$tname} =~ s/\S+\.vhd//g; + $args{$tname} =~ s/\S+\.v//g; + $args{$tname} =~ s/-f\S+//g; + $args{$tname} =~ s/-pallowsigned=1//g; + $args{$tname} =~ s/-g2001(-noconfig)?//g; + $args{$tname} =~ s/-g2005(-sv)?//g; + $args{$tname} =~ s/-g2009//g; + $args{$tname} =~ s/-g2012//g; + $args{$tname} =~ s/-gverilog-ams//g; + $cmd = "iverilog$sfx -o vsim $gen_flag $args{$tname}"; + $cmd .= " -s $testmod{$tname}" if ($testmod{$tname} ne ""); + $cmd .= " vlog95.v >> log/$tname.log 2>&1"; +# print "$cmd\n"; + if ($pass_type == 0 and system("$cmd")) { + if ($testtype{$tname} eq "TE") { + # Check if the system command core dumped! + if ($? >> 8 & 128) { + &print_rpt("==> Failed - TE (core dump).\n"); + $failed++; + next; + } else { + $pass_type = 3; + } + } else { + &print_rpt("==> Failed - running iverilog (translated).\n"); + $failed++; + next; + } + } + + $cmd = "vvp$sfx vsim $plargs{$tname} >> log/$tname.log 2>&1"; +# print "$cmd\n"; + if ($pass_type == 0 and system("$cmd")) { + if ($testtype{$tname} eq "RE") { + # Check if the system command core dumped! + if ($? >> 8 & 128) { + &print_rpt("==> Failed - RE (core dump).\n"); + $failed++; + next; + } else { + $pass_type = 2; + } + } else { + &print_rpt("==> Failed - running vvp.\n"); + $failed++; + next; + } + } + + if ($diff{$tname} ne "") { + $diff_file = $diff{$tname} + } else { + if ($pass_type == 1) { + &print_rpt("Passed - CE.\n"); + $passed++; + next; + } elsif ($pass_type == 2) { + &print_rpt("Passed - RE.\n"); + $passed++; + next; + } elsif ($pass_type == 3) { + &print_rpt("Passed - TE.\n"); + $passed++; + next; + } + $diff_file = "log/$tname.log"; + } +# print "diff $gold{$tname}, $diff_file, $offset{$tname}, $unordered{$tname}\n"; + if (diff($gold{$tname}, $diff_file, $offset{$tname}, $unordered{$tname})) { + if ($testtype{$tname} eq "EF") { + &print_rpt("Passed - expected fail.\n"); + $expected_fail++; + next; + } + &print_rpt("==> Failed -"); + if ($pass_type == 1) { + &print_rpt(" CE -"); + } elsif ($pass_type == 2) { + &print_rpt(" RE -"); + } elsif ($pass_type == 3) { + &print_rpt(" TE -"); + } + &print_rpt(" output does not match gold file.\n"); + $failed++; + next; + } + + if ($pass_type == 1) { + &print_rpt("Passed - CE.\n"); + } elsif ($pass_type == 2) { + &print_rpt("Passed - RE.\n"); + } elsif ($pass_type == 3) { + &print_rpt("Passed - TE.\n"); + } else { + &print_rpt("Passed.\n"); + } + $passed++; + + } continue { + if ($tname ne "") { + system("rm -f ./vlog95.v ./vsim") and + die "Error: failed to remove temporary file.\n"; + } + } + + &print_rpt("=" x 76 . "\n"); + &print_rpt("Test results:\n Total=$total, Passed=$passed, Failed=$failed,". + " Not Implemented=$not_impl, Expected Fail=$expected_fail\n"); +} diff --git a/ivtest/vpi/br_gh117.c b/ivtest/vpi/br_gh117.c new file mode 100644 index 000000000..1f9a5ae86 --- /dev/null +++ b/ivtest/vpi/br_gh117.c @@ -0,0 +1,73 @@ +#include + +PLI_INT32 readWriteSynch(p_cb_data cb_data) +{ + vpi_printf("Read write - current time %d\n", cb_data->time->low); + return 0; +} + +PLI_INT32 readOnlySynch(p_cb_data cb_data) +{ + vpi_printf("Read only - current time %d\n", cb_data->time->low); + return 0; +} + +PLI_INT32 afterDelay(p_cb_data cb_data) +{ + s_cb_data cb_data_s; + s_vpi_time time_s; + PLI_INT32 time = cb_data != NULL ? cb_data->time->low : 0; + PLI_INT32 period = 10; + + if (time < 50) + { + vpi_printf("After delay - current time %d\n", time); + + // set null pointers + cb_data_s.obj = NULL; + cb_data_s.value = NULL; + cb_data_s.user_data = NULL; + + // time + cb_data_s.time = &time_s; + time_s.type = vpiSimTime; + time_s.high = 0; + + // register read_write_synch + time_s.low = 1; + cb_data_s.reason = cbReadWriteSynch; + cb_data_s.cb_rtn = readWriteSynch; + vpi_free_object(vpi_register_cb(&cb_data_s)); + + // register read_only_synch + time_s.low = period-1; + cb_data_s.reason = cbReadOnlySynch; + cb_data_s.cb_rtn = readOnlySynch; + vpi_free_object(vpi_register_cb(&cb_data_s)); + + // register next time step + time_s.low = period; + cb_data_s.reason = cbAfterDelay; + cb_data_s.cb_rtn = afterDelay; + vpi_free_object(vpi_register_cb(&cb_data_s)); + } + else + { + vpi_printf("Finish sim - current time %d\n", time); + + // finish simulation + vpi_control(vpiFinish, 0); + } + return 0; +} + +void registerCallbacks(void) +{ + vpi_printf("Register callbacks\n"); + afterDelay(NULL); +} + +void (*vlog_startup_routines[])(void) = { + registerCallbacks, + 0 +}; diff --git a/ivtest/vpi/br_gh117.v b/ivtest/vpi/br_gh117.v new file mode 100644 index 000000000..8713f1a99 --- /dev/null +++ b/ivtest/vpi/br_gh117.v @@ -0,0 +1,7 @@ +module cb(); + +always begin + #1; +end + +endmodule diff --git a/ivtest/vpi/br_gh141.c b/ivtest/vpi/br_gh141.c new file mode 100644 index 000000000..061010eab --- /dev/null +++ b/ivtest/vpi/br_gh141.c @@ -0,0 +1,50 @@ +#include +#include "veriuser.h" +#include "acc_user.h" + +static int calltf(int ud, int reason) +{ + (void)ud; + (void)reason; + + tf_asynchon(); + + return 0; +} + +static int misctf(int ud, int reason, int paramvc) +{ + handle hdl1; + handle hdl2; + s_setval_value val; + s_setval_delay dly; + + (void)ud; + (void)paramvc; + + io_printf("misctf called for reason %d\n", reason); + + hdl1 = acc_handle_tfarg(1); + assert(hdl1); + hdl2 = acc_handle_tfarg(2); + assert(hdl2); + if (reason == reason_paramvc && paramvc == 1) { + val.format = accIntVal; + (void)acc_fetch_value(hdl1, "%%", &val); + dly.model = accNoDelay; + (void)acc_set_value(hdl2, &val, &dly); + } + return 0; +} + +s_tfcell veriusertfs[2] = { + {usertask, 0, 0, 0, calltf, misctf, "$background_copy", 1, 0, 0, {0} }, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0} } +}; + +static void veriusertfs_register(void) +{ + veriusertfs_register_table(veriusertfs); +} + +void (*vlog_startup_routines[])(void) = { &veriusertfs_register, 0 }; diff --git a/ivtest/vpi/br_gh141.v b/ivtest/vpi/br_gh141.v new file mode 100644 index 000000000..2a44f2c7f --- /dev/null +++ b/ivtest/vpi/br_gh141.v @@ -0,0 +1,17 @@ +module test; + +reg [15:0] x; +reg [15:0] y; + +initial begin + x = 0; + y = 0; + $monitor(x,,y); + $background_copy(x, y); + #1 $display("started background copy"); + #1 x = 1; + #1 x = 2; + #1 $display("finished background copy"); +end + +endmodule diff --git a/ivtest/vpi/br_gh169.c b/ivtest/vpi/br_gh169.c new file mode 100644 index 000000000..2abe4d362 --- /dev/null +++ b/ivtest/vpi/br_gh169.c @@ -0,0 +1,71 @@ +# include +# include +# include +# include + +static void list_vars(vpiHandle scope) +{ + vpiHandle iter; + vpiHandle item; + + iter = vpi_iterate(vpiNet, scope); + if (iter) { + while ( (item = vpi_scan(iter)) ) { + vpi_printf(" wire %s\n", vpi_get_str(vpiFullName, item)); + } + } + + iter = vpi_iterate(vpiReg, scope); + if (iter) { + while ( (item = vpi_scan(iter)) ) { + vpi_printf(" reg %s\n", vpi_get_str(vpiFullName, item)); + } + } + + iter = vpi_iterate(vpiRealVar, scope); + if (iter) { + while ( (item = vpi_scan(iter)) ) { + vpi_printf(" real %s\n", vpi_get_str(vpiFullName, item)); + } + } + + iter = vpi_iterate(vpiInternalScope, scope); + if (iter) { + while ( (item = vpi_scan(iter)) ) { + vpi_printf("scope %s\n", vpi_get_str(vpiFullName, item)); + list_vars(item); + } + } +} + +static PLI_INT32 list_vars_calltf(PLI_BYTE8*xx) +{ + vpiHandle iter = vpi_iterate(vpiModule, NULL); + vpiHandle item; + + (void)xx; /* Parameter is not used. */ + + while ( (item = vpi_scan(iter)) ) { + vpi_printf("scope %s\n", vpi_get_str(vpiName, item)); + list_vars(item); + } + return 0; +} + +static void list_vars_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$list_vars"; + tf_data.calltf = list_vars_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = "$list_vars"; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[])(void) = { + list_vars_register, + 0 +}; diff --git a/ivtest/vpi/br_gh169a.v b/ivtest/vpi/br_gh169a.v new file mode 100644 index 000000000..51ae5599d --- /dev/null +++ b/ivtest/vpi/br_gh169a.v @@ -0,0 +1,24 @@ +module dut1(input wire i1, output reg o1); + +always @* o1 = i1; + +endmodule + +module dut2(input wire i2, output reg o2); + +always @* o2 = i2; + +endmodule + +module test(); + +wire a, b, c; + +dut2 dut2(a, b); +dut1 dut1(b, c); + +initial begin + $list_vars; +end + +endmodule diff --git a/ivtest/vpi/br_gh169b.v b/ivtest/vpi/br_gh169b.v new file mode 100644 index 000000000..40deaaeba --- /dev/null +++ b/ivtest/vpi/br_gh169b.v @@ -0,0 +1,24 @@ +module dut1(input real i1, output real o1); + +assign o1 = i1; + +endmodule + +module dut2(input real i2, output real o2); + +assign o2 = i2; + +endmodule + +module test(); + +real a, b, c; + +dut2 dut2(a, b); +dut1 dut1(b, c); + +initial begin + $list_vars; +end + +endmodule diff --git a/ivtest/vpi/br_gh184.v b/ivtest/vpi/br_gh184.v new file mode 100644 index 000000000..1f3dbf331 --- /dev/null +++ b/ivtest/vpi/br_gh184.v @@ -0,0 +1,44 @@ +// When registering a simulation time callback, some simulators interpret +// the specified time value as relative to the current simulation time. To +// support this case, define the macro CB_TIME_IS_RELATIVE when compiling +// this module. + +module main; + + integer val1, val2; + + initial begin + val1 = 0; + val2 = 1; + #1; + $poke_at_simtime(val1, 1, 10); + $poke_at_simtime(val2, 2, 10); + +`ifdef CB_TIME_IS_RELATIVE + #1; +`endif + #8; + if (val1 !== 0) begin + $display("FAILED -- val1==%0d before delayed poke", val1); + $finish; + end + if (val2 !== 1) begin + $display("FAILED -- val2==%0d before delayed poke", val2); + $finish; + end + + #1; + if (val1 !== 1) begin + $display("FAILED -- val1==%0d: poke didn't happen", val1); + $finish; + end + if (val2 !== 2) begin + $display("FAILED -- val2==%0d: poke didn't happen", val2); + $finish; + end + + $display("PASSED"); + $finish(0); + end + +endmodule // main diff --git a/ivtest/vpi/br_gh235.c b/ivtest/vpi/br_gh235.c new file mode 100644 index 000000000..f12d5e051 --- /dev/null +++ b/ivtest/vpi/br_gh235.c @@ -0,0 +1,37 @@ +#include +#include "vpi_user.h" + +static PLI_INT32 atEndOfCompile(s_cb_data *data) +{ + vpiHandle handle; + s_vpi_time time = { vpiSimTime, 0, 0, 0 }; + s_vpi_value value; + + (void)data; /* Parameter is not used. */ + + handle = vpi_handle_by_name("test.flag", 0); + assert(handle); + + value.format = vpiIntVal; + value.value.integer = 1; + vpi_put_value(handle, &value, &time, vpiPureTransportDelay); + + return 0; +} + +static void vpiRegister(void) +{ + s_cb_data cb_data; + s_vpi_time time = { vpiSuppressTime, 0, 0, 0 }; + + cb_data.time = &time; + cb_data.value = 0; + cb_data.user_data = 0; + cb_data.obj = 0; + cb_data.reason = cbEndOfCompile; + cb_data.cb_rtn = atEndOfCompile; + + vpi_register_cb(&cb_data); +} + +void (*vlog_startup_routines[]) (void) = { vpiRegister, 0}; diff --git a/ivtest/vpi/br_gh235.v b/ivtest/vpi/br_gh235.v new file mode 100644 index 000000000..b655eb0a8 --- /dev/null +++ b/ivtest/vpi/br_gh235.v @@ -0,0 +1,15 @@ +module test; + +typedef enum reg { FALSE = 1'b0, TRUE = 1'b1 } boolean; + +boolean flag; + +initial begin + #1 $display("%b", flag); + if (flag === TRUE) + $display("PASSED"); + else + $display("FAILED"); +end + +endmodule diff --git a/ivtest/vpi/br_gh308.c b/ivtest/vpi/br_gh308.c new file mode 100644 index 000000000..222d46ad6 --- /dev/null +++ b/ivtest/vpi/br_gh308.c @@ -0,0 +1,46 @@ +# include +# include + +static int test_calltf(char*user_data) +{ + s_vpi_value value; + + (void)user_data; /* Parameter is not used. */ + + vpiHandle vec_handle = vpi_handle_by_name("test.vec", 0); + + vpiHandle msb_handle = vpi_handle(vpiLeftRange, vec_handle); + vpiHandle lsb_handle = vpi_handle(vpiRightRange, vec_handle); + + assert(msb_handle); + assert(lsb_handle); + + value.format = vpiBinStrVal; + vpi_get_value(msb_handle, &value); + vpi_printf("msb = 'b_%s\n", value.value.str); + + value.format = vpiBinStrVal; + vpi_get_value(lsb_handle, &value); + vpi_printf("lsb = 'b_%s\n", value.value.str); + + return 0; +} + +static void vpi_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.calltf = test_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.tfname = "$test"; + tf_data.user_data = 0; + + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[])(void) = { + vpi_register, + 0 +}; diff --git a/ivtest/vpi/br_gh308.v b/ivtest/vpi/br_gh308.v new file mode 100644 index 000000000..0588b8ae1 --- /dev/null +++ b/ivtest/vpi/br_gh308.v @@ -0,0 +1,10 @@ +module test; + +reg [31:0] vec; + +initial begin + vec = 0; // make sure vec is not pruned + $test; +end + +endmodule diff --git a/ivtest/vpi/br_gh317.c b/ivtest/vpi/br_gh317.c new file mode 100644 index 000000000..94f3d251d --- /dev/null +++ b/ivtest/vpi/br_gh317.c @@ -0,0 +1,49 @@ +#include "vpi_user.h" + +static void get_type(char *obj, vpiHandle scope) +{ + vpiHandle hand; + + vpi_printf("Looking for \"%s\": ", obj); + + hand = vpi_handle_by_name(obj, scope); + if (hand) vpi_printf("found \"%s\"\n", vpi_get_str(vpiName, hand)); + else vpi_printf("Not found\n"); +} + +static PLI_INT32 CompileTF(PLI_BYTE8 *x) +{ + (void)x; /* Parameter is not used. */ + vpiHandle callh = vpi_handle(vpiSysTfCall, 0); + vpiHandle scope = vpi_handle(vpiScope, callh); + + get_type("\\esc.port", scope); + get_type("\\esc.port ", scope); + get_type("\\esc.mod .\\esc.inm .\\esc.port", NULL); + get_type("\\esc.mod .\\esc.inm .\\esc.port ", NULL); + get_type("\\esc.val", scope); + get_type("\\esc.val ", scope); + get_type("\\esc.mod .\\esc.inm .\\esc.val", NULL); + get_type("\\esc.mod .\\esc.inm .\\esc.val ", NULL); + get_type("\\esc.mod .\\esc.inm .normal", NULL); + get_type("\\esc.mod .inst.\\esc.id", NULL); + get_type("\\esc.mod .inst.\\esc.id ", NULL); + get_type("\\esc.mod .inst.normal", NULL); + + return 0; +} + +static void my_Register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$print_if_found"; + tf_data.calltf = 0; + tf_data.compiletf = CompileTF; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[]) (void) = { +my_Register, 0}; diff --git a/ivtest/vpi/br_gh317.v b/ivtest/vpi/br_gh317.v new file mode 100644 index 000000000..5f307bc5f --- /dev/null +++ b/ivtest/vpi/br_gh317.v @@ -0,0 +1,23 @@ +module \esc.mod ; + \esc.sub \esc.inm (1'b1); + sub inst(); +endmodule + +module \esc.sub (input wire \esc.port ); + reg \esc.val ; + reg normal; + initial begin + $print_if_found(); + normal = 1'b0; + \esc.val = 1'b1; + end +endmodule + +module sub; + reg \esc.id ; + reg normal; + initial begin + normal = 1'b1; + \esc.id = 1'b0; + end +endmodule diff --git a/ivtest/vpi/br_gh496.c b/ivtest/vpi/br_gh496.c new file mode 100644 index 000000000..6eae1ca8b --- /dev/null +++ b/ivtest/vpi/br_gh496.c @@ -0,0 +1,56 @@ +# include +# include +# include +# include + +static PLI_INT32 list_packages_calltf(PLI_BYTE8*xx) +{ + vpiHandle iter = vpi_iterate(vpiPackage, NULL); + vpiHandle item; + + (void)xx; /* Parameter is not used. */ + + while ( (item = vpi_scan(iter)) ) { + vpi_printf("package %s\n", vpi_get_str(vpiName, item)); + } + return 0; +} + +static PLI_INT32 list_modules_calltf(PLI_BYTE8*xx) +{ + vpiHandle iter = vpi_iterate(vpiModule, NULL); + vpiHandle item; + + (void)xx; /* Parameter is not used. */ + + while ( (item = vpi_scan(iter)) ) { + vpi_printf("module %s\n", vpi_get_str(vpiName, item)); + } + return 0; +} + +static void list_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$list_packages"; + tf_data.calltf = list_packages_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = "$list_packages"; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.tfname = "$list_modules"; + tf_data.calltf = list_modules_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = "$list_modules"; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[])(void) = { + list_register, + 0 +}; diff --git a/ivtest/vpi/br_gh496.v b/ivtest/vpi/br_gh496.v new file mode 100644 index 000000000..4369ea19d --- /dev/null +++ b/ivtest/vpi/br_gh496.v @@ -0,0 +1,24 @@ +package p1; + +endpackage + +module m1; + +endmodule + +package p2; + +endpackage + +module m2; + +endmodule + +module test; + +initial begin + $list_packages; + $list_modules; +end + +endmodule diff --git a/ivtest/vpi/br_gh59.c b/ivtest/vpi/br_gh59.c new file mode 100644 index 000000000..c164f191a --- /dev/null +++ b/ivtest/vpi/br_gh59.c @@ -0,0 +1,81 @@ +#include +#include "vpi_user.h" + +static PLI_INT32 +EndOfCompile(s_cb_data *data) +{ + s_vpi_time timerec = { vpiSimTime, 0, 0, 0 }; + s_vpi_value val; + + vpiHandle b0_handle; + vpiHandle wr_handle; + vpiHandle in_handle; + + (void)data; /* Parameter is not used. */ + + b0_handle = vpi_handle_by_name("test.B0", 0); + assert(b0_handle); + + wr_handle = vpi_handle_by_name("test.WR", 0); + assert(wr_handle); + + in_handle = vpi_handle_by_name("test.IN", 0); + assert(in_handle); + + timerec.low = 500; + val.value.str = "01"; + val.format = vpiBinStrVal; + vpi_put_value(in_handle, &val, &timerec, vpiInertialDelay); + + val.value.str = "zz"; + val.format = vpiBinStrVal; + vpi_put_value(b0_handle, &val, &timerec, vpiInertialDelay); + + val.format = vpiIntVal; + + val.value.integer = 0; + vpi_put_value(wr_handle, &val, &timerec, vpiInertialDelay); + + timerec.low = 500; + val.value.integer = 0; + vpi_put_value(wr_handle, &val, &timerec, vpiInertialDelay); + + val.value.integer = 1; + timerec.low = 1000; + vpi_put_value(wr_handle, &val, &timerec, vpiInertialDelay); + + timerec.low = 1500; + vpi_put_value(wr_handle, &val, &timerec, vpiInertialDelay); + + timerec.low = 2000; + val.value.integer = 0; + vpi_put_value(wr_handle, &val, &timerec, vpiInertialDelay); + + timerec.low = 3000; + val.value.integer = 0; + vpi_put_value(wr_handle, &val, &timerec, vpiInertialDelay); + + return 0; +} + + +static void +VPIRegister(void) +{ + s_cb_data cb_data; + s_vpi_time timerec = { vpiSuppressTime, 0, 0, 0 }; + + cb_data.time = &timerec; + cb_data.value = 0; + cb_data.user_data = 0; + cb_data.obj = 0; + cb_data.reason = cbEndOfCompile; + cb_data.cb_rtn = EndOfCompile; + + vpi_register_cb(&cb_data); +} + +void (*vlog_startup_routines[])(void) = { + VPIRegister, + 0 +}; diff --git a/ivtest/vpi/br_gh59.v b/ivtest/vpi/br_gh59.v new file mode 100644 index 000000000..42c9cfbf3 --- /dev/null +++ b/ivtest/vpi/br_gh59.v @@ -0,0 +1,13 @@ +`timescale 1 ns / 1 ns + +module test( + inout wire [1:0] B0, + input wire WR, + input wire [1:0] IN +); + +assign B0 = WR ? 2'bz : IN; + +initial $monitor("%b %b %b %0t", IN, WR, B0, $time); + +endmodule diff --git a/ivtest/vpi/br_gh73a.v b/ivtest/vpi/br_gh73a.v new file mode 100644 index 000000000..01c34a9da --- /dev/null +++ b/ivtest/vpi/br_gh73a.v @@ -0,0 +1,35 @@ +module partsel(inout wire [1:0] part); + +assign part = 2'bz; + +endmodule + + +module test(); + +wire [3:0] full; + +partsel sel(full[1:0]); + +initial begin + #1 $peek(full); + #0 $display("display : %b %b", full, sel.part); + #1 $force(full); + #1 $peek(full); + #0 $display("display : %b %b", full, sel.part); + #1 $release(full); + #0 $display("display : %b %b", full, sel.part); + #1 $force(full); + #1 $peek(full); + #0 $display("display : %b %b", full, sel.part); + #1 $poke(full); + #1 $peek(full); + #0 $display("display : %b %b", full, sel.part); + #1 $release(full); + #0 $display("display : %b %b", full, sel.part); + #1 $poke(full); + #1 $peek(full); + #0 $display("display : %b %b", full, sel.part); +end + +endmodule diff --git a/ivtest/vpi/br_gh73b.v b/ivtest/vpi/br_gh73b.v new file mode 100644 index 000000000..737293bd7 --- /dev/null +++ b/ivtest/vpi/br_gh73b.v @@ -0,0 +1,35 @@ +module partsel(inout wire [1:0] part); + +assign part = 2'bz; + +endmodule + + +module test(); + +wire [3:0] full; + +partsel sel(full[2:1]); + +initial begin + #1 $peek(full[2:1]); + #0 $display("display : %b %b", sel.part, full); + #1 $force(full[2:1]); + #1 $peek(full[2:1]); + #0 $display("display : %b %b", sel.part, full); + #1 $release(full[2:1]); + #0 $display("display : %b %b", sel.part, full); + #1 $force(full[2:1]); + #1 $peek(full[2:1]); + #0 $display("display : %b %b", sel.part, full); + #1 $poke(full[2:1]); + #1 $peek(full[2:1]); + #0 $display("display : %b %b", sel.part, full); + #1 $release(full[2:1]); + #0 $display("display : %b %b", sel.part, full); + #1 $poke(full[2:1]); + #1 $peek(full[2:1]); + #0 $display("display : %b %b", sel.part, full); +end + +endmodule diff --git a/ivtest/vpi/br_ml20191013.c b/ivtest/vpi/br_ml20191013.c new file mode 100644 index 000000000..051af33b7 --- /dev/null +++ b/ivtest/vpi/br_ml20191013.c @@ -0,0 +1,209 @@ +/********************************************************************** + * $pow example -- PLI application using VPI routines + * + * C source to calculate the result of a number to the power of an + * exponent. The result is returned as a 32-bit integer. + * + * Usage: result = $pow(,); + * + * For the book, "The Verilog PLI Handbook" by Stuart Sutherland + * Copyright 1999 & 2001, Kluwer Academic Publishers, Norwell, MA, USA + * Contact: www.wkap.il + * Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA + * Contact: www.sutherland-hdl.com + *********************************************************************/ + +#define VPI_1995 0 /* set to non-zero for Verilog-1995 compatibility */ + +#include /* ANSI C standard library */ +#include /* ANSI C standard input/output library */ +#include /* ANSI C standard arguments library */ +#include "vpi_user.h" /* IEEE 1364 PLI VPI routine library */ + +#if VPI_1995 +#include "../vpi_1995_compat.h" /* kludge new Verilog-2001 routines */ +#endif + +/* prototypes of PLI application routine names */ +#ifdef IVERILOG_V0_8 +static PLI_INT32 PLIbook_PowSizetf(char *user_data); +static PLI_INT32 PLIbook_PowCalltf(char *user_data); +static PLI_INT32 PLIbook_PowCompiletf(char *user_data); +#else +static PLI_INT32 PLIbook_PowSizetf(PLI_BYTE8 *user_data); +static PLI_INT32 PLIbook_PowCalltf(PLI_BYTE8 *user_data); +static PLI_INT32 PLIbook_PowCompiletf(PLI_BYTE8 *user_data); +#endif +static PLI_INT32 PLIbook_PowStartOfSim(s_cb_data *callback_data); + +/********************************************************************** + * $pow Registration Data + * (add this function name to the vlog_startup_routines array) + *********************************************************************/ +void PLIbook_pow_register(void) +{ + s_vpi_systf_data tf_data; + s_cb_data cb_data_s; + vpiHandle callback_handle; + + tf_data.type = vpiSysFunc; + tf_data.sysfunctype = vpiSysFuncSized; + tf_data.tfname = "$pow"; + tf_data.calltf = PLIbook_PowCalltf; + tf_data.compiletf = PLIbook_PowCompiletf; + tf_data.sizetf = PLIbook_PowSizetf; + tf_data.user_data = NULL; + vpi_register_systf(&tf_data); + + cb_data_s.reason = cbStartOfSimulation; + cb_data_s.cb_rtn = PLIbook_PowStartOfSim; + cb_data_s.obj = NULL; + cb_data_s.time = NULL; + cb_data_s.value = NULL; + cb_data_s.user_data = NULL; + callback_handle = vpi_register_cb(&cb_data_s); + vpi_free_object(callback_handle); /* don't need callback handle */ +} + +/********************************************************************** + * Sizetf application + *********************************************************************/ +#ifdef IVERILOG_V0_8 +static PLI_INT32 PLIbook_PowSizetf(char *user_data) +#else +static PLI_INT32 PLIbook_PowSizetf(PLI_BYTE8 *user_data) +#endif +{ + (void)user_data; /* Parameter is not used. */ + //vpi_printf("\n$pow PLI sizetf function.\n\n"); + return(32); /* $pow returns 32-bit values */ +} + +/********************************************************************** + * compiletf application to verify valid systf args. + *********************************************************************/ +#ifdef IVERILOG_V0_8 +static PLI_INT32 PLIbook_PowCompiletf(char *user_data) +#else +static PLI_INT32 PLIbook_PowCompiletf(PLI_BYTE8 *user_data) +#endif +{ + vpiHandle systf_handle, arg_itr, arg_handle; + PLI_INT32 tfarg_type; + int err_flag = 0; + + (void)user_data; /* Parameter is not used. */ + + vpi_printf("\n$pow PLI compiletf function.\n\n"); + + do { /* group all tests, so can break out of group on error */ + systf_handle = vpi_handle(vpiSysTfCall, NULL); + arg_itr = vpi_iterate(vpiArgument, systf_handle); + if (arg_itr == NULL) { + vpi_printf("ERROR: $pow requires 2 arguments; has none\n"); + err_flag = 1; + break; + } + arg_handle = vpi_scan(arg_itr); + tfarg_type = vpi_get(vpiType, arg_handle); + if ( (tfarg_type != vpiReg) && + (tfarg_type != vpiIntegerVar) && + (tfarg_type != vpiConstant) ) { + vpi_printf("ERROR: $pow arg1 must be number, variable or net\n"); + err_flag = 1; + break; + } + arg_handle = vpi_scan(arg_itr); + if (arg_handle == NULL) { + vpi_printf("ERROR: $pow requires 2nd argument\n"); + err_flag = 1; + break; + } + tfarg_type = vpi_get(vpiType, arg_handle); + if ( (tfarg_type != vpiReg) && + (tfarg_type != vpiIntegerVar) && + (tfarg_type != vpiConstant) ) { + vpi_printf("ERROR: $pow arg2 must be number, variable or net\n"); + err_flag = 1; + break; + } + if (vpi_scan(arg_itr) != NULL) { + vpi_printf("ERROR: $pow requires 2 arguments; has too many\n"); + vpi_free_object(arg_itr); + err_flag = 1; + break; + } + } while (0 == 1); /* end of test group; only executed once */ + + if (err_flag) { + vpi_control(vpiFinish, 1); /* abort simulation */ + } + return(0); +} + +/********************************************************************** + * calltf to calculate base to power of exponent and return result. + *********************************************************************/ +#include +#ifdef IVERILOG_V0_8 +static PLI_INT32 PLIbook_PowCalltf(char *user_data) +#else +static PLI_INT32 PLIbook_PowCalltf(PLI_BYTE8 *user_data) +#endif +{ + s_vpi_value value_s; + vpiHandle systf_handle, arg_itr, arg_handle; + PLI_INT32 base, expo; + double result; + + (void)user_data; /* Parameter is not used. */ + + vpi_printf("\n$pow PLI calltf function.\n\n"); + + systf_handle = vpi_handle(vpiSysTfCall, NULL); + arg_itr = vpi_iterate(vpiArgument, systf_handle); + if (arg_itr == NULL) { + vpi_printf("ERROR: $pow failed to obtain systf arg handles\n"); + return(0); + } + + /* read base from systf arg 1 (compiletf has already verified) */ + arg_handle = vpi_scan(arg_itr); + value_s.format = vpiIntVal; + vpi_get_value(arg_handle, &value_s); + base = value_s.value.integer; + + /* read exponent from systf arg 2 (compiletf has already verified) */ + arg_handle = vpi_scan(arg_itr); + vpi_free_object(arg_itr); /* not calling scan until returns null */ + vpi_get_value(arg_handle, &value_s); + expo = value_s.value.integer; + + /* calculate result of base to power of exponent */ + result = pow( (double)base, (double)expo ); + + /* write result to simulation as return value $pow */ + value_s.value.integer = (PLI_INT32)result; + vpi_put_value(systf_handle, &value_s, NULL, vpiNoDelay); + return(0); +} + +/********************************************************************** + * Start-of-simulation application + *********************************************************************/ +static PLI_INT32 PLIbook_PowStartOfSim(s_cb_data *callback_data) +{ + (void)callback_data; /* Parameter is not used. */ + vpi_printf("\n$pow StartOfSim callback.\n\n"); + return(0); +} +/*********************************************************************/ + + +void (*vlog_startup_routines[])(void) = +{ + /*** add user entries here ***/ + PLIbook_pow_register, + //PLIbook_test_user_data_register, + 0 /*** final entry must be 0 ***/ +}; diff --git a/ivtest/vpi/br_ml20191013.v b/ivtest/vpi/br_ml20191013.v new file mode 100644 index 000000000..aede1e5e4 --- /dev/null +++ b/ivtest/vpi/br_ml20191013.v @@ -0,0 +1,32 @@ +/********************************************************************** + * $pow example -- Verilog HDL test bench. + * + * Verilog test bench to test the $pow PLI application. + * + * For the book, "The Verilog PLI Handbook" by Stuart Sutherland + * Copyright 1999 & 2001, Kluwer Academic Publishers, Norwell, MA, USA + * Contact: www.wkap.il + * Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA + * Contact: www.sutherland-hdl.com + *********************************************************************/ +`timescale 1ns / 1ns +module test; + + reg [31:0] result; + reg a, b; + + initial + begin + $display("Start simulation pow_test.v"); + a = 1; + b = 0; + + /* Test $pow with valid values */ + #1 $display("$pow(2,3) returns %d", $pow(2,3)); + #1 result = $pow(a,b); + #1 $display("$pow(a,b) returns %d (a=%d b=%d)", result, a, b); + #1 $finish(0); + end + +endmodule +/*********************************************************************/ diff --git a/ivtest/vpi/by_index.c b/ivtest/vpi/by_index.c new file mode 100644 index 000000000..ae5f951be --- /dev/null +++ b/ivtest/vpi/by_index.c @@ -0,0 +1,112 @@ +#include +#include "vpi_user.h" + +static PLI_INT32 check_val_calltf(ICARUS_VPI_CONST PLI_BYTE8*name) +{ + (void) name; /* Not used */ + vpiHandle callh = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, callh); + vpiHandle item, index, value; + s_vpi_value val; + + assert(argv); + item = vpi_scan(argv); + assert(item); + index = vpi_scan(argv); + assert(index); + value = vpi_scan(argv); + assert(value); + vpi_free_object(argv); + + PLI_INT32 i_idx; + val.format = vpiIntVal; + vpi_get_value(index, &val); + i_idx = val.value.integer; + + vpiHandle sel; + sel = vpi_handle_by_index(item, i_idx); + assert(sel); + + vpi_printf("The index is %d\n", vpi_get(vpiIndex, sel)); + vpi_printf("The type is %s\n", vpi_get_str(vpiType, sel)); + + vpi_printf("%s ", vpi_get_str(vpiName, sel)); + + val.format = vpiObjTypeVal; + vpi_get_value(value, &val); + + if (val.format == vpiRealVal) { + vpi_printf("=> %.2f == ", val.value.real); + val.format = vpiRealVal; + vpi_get_value(sel, &val); + vpi_printf("%.2f\n", val.value.real); + } else { + val.format = vpiDecStrVal; + vpi_get_value(value, &val); + vpi_printf("=> %s == ", val.value.str); + val.format = vpiDecStrVal; + vpi_get_value(sel, &val); + vpi_printf("%s\n", val.value.str); + } + + return 0; +} +static PLI_INT32 put_val_calltf(ICARUS_VPI_CONST PLI_BYTE8*name) +{ + (void) name; /* Not used */ + vpiHandle callh = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, callh); + vpiHandle item, index, value; + s_vpi_value val; + + assert(argv); + item = vpi_scan(argv); + assert(item); + index = vpi_scan(argv); + assert(index); + value = vpi_scan(argv); + assert(value); + vpi_free_object(argv); + + PLI_INT32 i_idx; + val.format = vpiIntVal; + vpi_get_value(index, &val); + i_idx = val.value.integer; + + vpiHandle sel; + sel = vpi_handle_by_index(item, i_idx); + assert(sel); + + val.format = vpiObjTypeVal; + vpi_get_value(value, &val); + assert (val.format != vpiRealVal); + val.format = vpiIntVal; + vpi_get_value(value, &val); + vpi_put_value(sel, &val, NULL, vpiNoDelay); + + return 0; +} + +static void check_val_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$check_val"; + tf_data.calltf = check_val_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.tfname = "$put_val"; + tf_data.calltf = put_val_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[])(void) = { + check_val_register, + 0 +}; diff --git a/ivtest/vpi/by_index.v b/ivtest/vpi/by_index.v new file mode 100644 index 000000000..25d676729 --- /dev/null +++ b/ivtest/vpi/by_index.v @@ -0,0 +1,38 @@ +module top; + reg [8:1] val; + wire [1:4] wval; + reg [3:0] wdrv; + real r_arr [1:8]; + integer i_arr [8:1]; + integer lp; + + assign wval = wdrv; + + initial begin + wdrv = 4'b1010; + for (lp=1; lp<=8; lp=lp+1) begin + val[lp] = lp % 2; + r_arr[lp] = lp + 0.25; + i_arr[lp] = lp - 1; + end + + #1; + $check_val(val, 3, 1); + $check_val(wval, 4, 0); + $check_val(r_arr, 5, 5.25); + $check_val(i_arr, 2, 1); + $display("Original value is %b", val); + $put_val(val, 2, 1); + $put_val(val, 1, 0); + $display(" New value is %b", val); + $display("Original net value is %b", wval); + $put_val(wval, 2, 1); + $put_val(wval, 1, 0); + $display(" New net value is %b", wval); + #1; + // Verify that an update overrides the put value + wdrv = 4'b1001; + $display(" net value is now %b", wval); + end + +endmodule diff --git a/ivtest/vpi/by_name.c b/ivtest/vpi/by_name.c new file mode 100644 index 000000000..3b07b74ab --- /dev/null +++ b/ivtest/vpi/by_name.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test verifies some functionality of vpi_handle_by_name() + */ +#include +#include +#include "vpi_user.h" + +static void FindHandleByName(void) +{ + int i; + vpiHandle hand; + char *s[] = { + "top0", + "top0.t_my", + "top0.f_my", + "top0.r", + "top0.t", + "top0.e", + "top0.i", + "top0.init", + "top0.lvl1_0", + "top0.lvl1_1", + "top0.lvl1_0.lvl2.t_my", + "top0.lvl1_0.lvl2.f_my", + "top0.lvl1_0.lvl2.r", + "top0.lvl1_0.lvl2.t", + "top0.lvl1_0.lvl2.e", + "top0.lvl1_0.lvl2.i", + "top0.lvl1_0.lvl2.init", + "top1", + "noexsist", + "top1.noexsist", + "top1.lvl1.noexsist", + 0 + }; + + for (i=0; s[i]; i++) { + vpi_printf("Looking up %s: ", s[i]); + hand = vpi_handle_by_name(s[i], NULL); + if (hand) + vpi_printf("Found name = %s, type = %d\n", + vpi_get_str(vpiName, hand), (int)vpi_get(vpiType, hand)); + else + vpi_printf("*** Not found ***\n"); + } +} + +#ifdef IVERILOG_V0_8 +static PLI_INT32 CompileTF(char *x) +#else +static PLI_INT32 CompileTF(PLI_BYTE8 *x) +#endif +{ + (void)x; /* Parameter is not used. */ + FindHandleByName(); + return 0; +} + +static void my_Register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$test"; + tf_data.calltf = 0; + tf_data.compiletf = CompileTF; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[]) (void) = { my_Register, 0}; diff --git a/ivtest/vpi/by_name.v b/ivtest/vpi/by_name.v new file mode 100644 index 000000000..8c7115504 --- /dev/null +++ b/ivtest/vpi/by_name.v @@ -0,0 +1,82 @@ +// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// +module lvl2; + reg r; + time t; + event e; + integer i; + + task t_my; + r = 1'b0; + endtask + + function f_my; + input in; + begin + f_my = !in; + end + endfunction + + initial begin: init + t_my; + r = f_my(r); + r = f_my(i); + r = f_my(t); + ->e; + end +endmodule + +module lvl1; + lvl2 lvl2(); +endmodule + +module top0; + reg r; + time t; + event e; + integer i; + + task t_my; + r = 1'b0; + endtask + + function f_my; + input in; + begin + f_my = !in; + end + endfunction + + initial begin: init + t_my; + r = f_my(r); + r = f_my(i); + r = f_my(t); + ->e; + end + + lvl1 lvl1_0(); + lvl1 lvl1_1(); +endmodule + + +module top1; + initial begin: init + $test; + end +endmodule diff --git a/ivtest/vpi/callback1.c b/ivtest/vpi/callback1.c new file mode 100644 index 000000000..b31760f2c --- /dev/null +++ b/ivtest/vpi/callback1.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2002 Mike Runyan, Michael Ruff + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +#include +#include "vpi_user.h" + +static PLI_INT32 +my_EndOfCompile(p_cb_data cb_data) +{ + vpi_printf ("EndOfCompile %s\n", cb_data->user_data); + return 0; +} + +static PLI_INT32 +my_StartOfSimulation(p_cb_data cb_data) +{ + vpi_printf ("StartOfSimulation %s\n", cb_data->user_data); + return 0; +} + +static PLI_INT32 +my_EndOfSimulation(p_cb_data cb_data) +{ + vpi_printf ("EndOfSimulation %s\n", cb_data->user_data); + return 0; +} + +static void +my_Register(void) +{ + s_cb_data cb_data; + cb_data.time = NULL; + + vpi_printf("Registering Callbacks\n"); + + // first register + cb_data.reason = cbEndOfCompile; + cb_data.cb_rtn = my_EndOfCompile; + cb_data.user_data = "EOC"; + vpi_register_cb(&cb_data); + + cb_data.reason = cbStartOfSimulation; + cb_data.cb_rtn = my_StartOfSimulation; + cb_data.user_data = "SOS"; + vpi_register_cb(&cb_data); + + cb_data.reason = cbEndOfSimulation; + cb_data.cb_rtn = my_EndOfSimulation; + cb_data.user_data = "EOS"; + vpi_register_cb(&cb_data); + + // second register + cb_data.reason = cbEndOfCompile; + cb_data.cb_rtn = my_EndOfCompile; + cb_data.user_data = "EOC"; + vpi_register_cb(&cb_data); + + cb_data.reason = cbStartOfSimulation; + cb_data.cb_rtn = my_StartOfSimulation; + cb_data.user_data = "SOS"; + vpi_register_cb(&cb_data); + + cb_data.reason = cbEndOfSimulation; + cb_data.cb_rtn = my_EndOfSimulation; + cb_data.user_data = "EOS"; + vpi_register_cb(&cb_data); +} + +void (*vlog_startup_routines[])(void) = { + my_Register, + 0 +}; diff --git a/ivtest/vpi/callback1.v b/ivtest/vpi/callback1.v new file mode 100644 index 000000000..65057d1df --- /dev/null +++ b/ivtest/vpi/callback1.v @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2002 Mike Runyan, Michael Ruff + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +module test; +initial $display("Hello World"); +endmodule diff --git a/ivtest/vpi/celldefine.c b/ivtest/vpi/celldefine.c new file mode 100644 index 000000000..489f4588b --- /dev/null +++ b/ivtest/vpi/celldefine.c @@ -0,0 +1,32 @@ +#include "vpi_user.h" + +static PLI_INT32 calltf(PLI_BYTE8 *data) +{ + vpiHandle callh = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, callh); + vpiHandle mod = vpi_scan(argv); + + (void)data; /* Parameter is not used. */ + + vpi_free_object(argv); + + vpi_printf("Module instance %s is%s a cell.\n", + vpi_get_str(vpiFullName, mod), + vpi_get(vpiCellInstance, mod) ? "" : " not"); + return 0; +} + +static void vpi_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$is_cell"; + tf_data.calltf = calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[]) (void) = {vpi_register, 0}; diff --git a/ivtest/vpi/celldefine.v b/ivtest/vpi/celldefine.v new file mode 100644 index 000000000..8cbd5dd8a --- /dev/null +++ b/ivtest/vpi/celldefine.v @@ -0,0 +1,43 @@ +module top; + reg pass; + reg in; + wire out, outb; + + lower_cell dutb(outb, in); + lower_no_cell dut(out, in); + + always @(outb) begin + if (outb !== ~in) begin + $display("FAILED outb at time %t, expected %b, got %b", $time, ~in, outb); + pass = 1'b0; + end + end + + always @(out) begin + if (out !== in) begin + $display("FAILED out at time %t, expected %b, got %b", $time, in, out); + pass = 1'b0; + end + end + + initial begin + pass = 1'b1; + #1 in = 1'b0; + #1 in = 1'b1; + #1 in = 1'b0; + + #1 if (pass) $display("Verilog checking was OK."); + $is_cell(dut); + $is_cell(dutb); + end +endmodule + +`celldefine +module lower_cell(output out, input in); + not(out, in); +endmodule +`endcelldefine + +module lower_no_cell(output out, input in); + buf(out, in); +endmodule diff --git a/ivtest/vpi/check_version.c b/ivtest/vpi/check_version.c new file mode 100644 index 000000000..7fec91c2f --- /dev/null +++ b/ivtest/vpi/check_version.c @@ -0,0 +1,114 @@ +/* + * This test verifies the the vpi_get_vlog_info() call returns the + * version information correctly. This does not currently work in + * V0.8 so it is marked NI. + */ +#include "vpi_user.h" +#include +#include + +static PLI_INT32 compiletf(PLI_BYTE8 *name) +{ + vpiHandle callh, argv, arg; + callh = vpi_handle(vpiSysTfCall, 0); + argv = vpi_iterate(vpiArgument, callh); + + /* Check that there is an argument. */ + if (argv == 0) { + vpi_printf("ERROR: %s:%d: ", vpi_get_str(vpiFile, callh), + (int)vpi_get(vpiLineNo, callh)); + vpi_printf("%s() requires a single vector argument!", name); + vpi_control(vpiFinish, 1); + return 0; + } + arg = vpi_scan(argv); + if (arg == 0) { + vpi_printf("ERROR: %s:%d: ", vpi_get_str(vpiFile, callh), + (int)vpi_get(vpiLineNo, callh)); + vpi_printf("%s() requires a single vector argument!", name); + vpi_control(vpiFinish, 1); + return 0; + } + + /* Check that the argument is a register with at least 640 bits. */ + if (vpi_get(vpiType, arg) != vpiReg) { + vpi_printf("ERROR: %s:%d: ", vpi_get_str(vpiFile, callh), + (int)vpi_get(vpiLineNo, callh)); + vpi_printf("%s() requires a vector argument!", name); + vpi_free_object(argv); + vpi_control(vpiFinish, 1); + return 0; + } + if (vpi_get(vpiSize, arg) < 640) { + vpi_printf("ERROR: %s:%d: ", vpi_get_str(vpiFile, callh), + (int)vpi_get(vpiLineNo, callh)); + vpi_printf("%s() vector is too small need 640 bits!", name); + vpi_free_object(argv); + vpi_control(vpiFinish, 1); + return 0; + } + + /* We only take one argument. */ + arg = vpi_scan(argv); + if (arg != 0) { + vpi_printf("ERROR: %s:%d: ", vpi_get_str(vpiFile, callh), + (int)vpi_get(vpiLineNo, callh)); + vpi_printf("%s() only takes one argument!", name); + vpi_free_object(argv); + vpi_control(vpiFinish, 1); + return 0; + } + + return 0; +} + +static PLI_INT32 calltf(PLI_BYTE8 *name) +{ + vpiHandle callh, argv, reg; + s_vpi_vlog_info info; + s_vpi_value val; + PLI_INT32 ret; + char *str, *cp; + + callh = vpi_handle(vpiSysTfCall, 0); + argv = vpi_iterate(vpiArgument, callh); + reg = vpi_scan(argv); + vpi_free_object(argv); + + /* Get the Verilog version information. */ + ret = vpi_get_vlog_info(&info); + if (ret == 0) { + vpi_printf("ERROR: %s:%d: ", vpi_get_str(vpiFile, callh), + (int)vpi_get(vpiLineNo, callh)); + vpi_printf("%s() failed to get verilog information!", name); + vpi_control(vpiFinish, 1); + } + + /* For Icarus we can just return everything before the space to + * get the version and subversion. */ + str = strdup(info.version); + cp = strchr(str, ' '); + if (cp) + *cp = '\0'; + val.format = vpiStringVal; + val.value.str = str; + vpi_put_value(reg, &val, 0, vpiNoDelay); + free(str); + + return 0; +} + +static void my_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$get_version"; + tf_data.calltf = calltf; + tf_data.compiletf = compiletf; + tf_data.sizetf = 0; + tf_data.user_data = "$get_version"; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[]) (void) = { my_register, 0}; diff --git a/ivtest/vpi/check_version.v b/ivtest/vpi/check_version.v new file mode 100644 index 000000000..5f581108d --- /dev/null +++ b/ivtest/vpi/check_version.v @@ -0,0 +1,18 @@ +module top; + reg [80*8:1] simp_str, info_str; + real ver, subver; + initial begin + ver = $simparam("simulatorVersion"); + subver = $simparam("simulatorSubversion"); + // For 0.9 only use one digit after the decimal point. + if (ver < 1.0) $swrite(simp_str, "%0.1f.%0.0f", ver, subver); + // For the rest, 10 and above, use no digits after the decimal point. + else $swrite(simp_str, "%0.0f.%0.0f", ver, subver); + $get_version(info_str); + if (simp_str !== info_str) begin + $display("FAILED"); + $display("$simparam version: '%0s'", simp_str); + $display("vpi_get_vlog_info version: '%0s'", info_str); + end else $display("The two versions matched!"); + end +endmodule diff --git a/ivtest/vpi/display_array.c b/ivtest/vpi/display_array.c new file mode 100644 index 000000000..f52288d19 --- /dev/null +++ b/ivtest/vpi/display_array.c @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2014-2021 CERN + * @author Maciej Suminski + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +# include +# include +# include + +static PLI_INT32 display_array_calltf(ICARUS_VPI_CONST PLI_BYTE8*name) +{ + (void)name; /* Parameter is not used. */ + + vpiHandle callh = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv, array, cell, l_range, r_range; + s_vpi_value val; + + /* Fetch arguments */ + argv = vpi_iterate(vpiArgument, callh); + assert(argv); + array = vpi_scan(argv); + assert(array); + vpi_free_object(argv); + + int array_size = vpi_get(vpiSize, array); + if(array_size < 0) { + vpi_printf("ERROR: Arrays cannot have negative size"); + vpi_control(vpiFinish, 0); + return 0; + } + + /* Test range handles */ + l_range = vpi_handle(vpiLeftRange, array); + r_range = vpi_handle(vpiRightRange, array); + val.format = vpiIntVal; + vpi_get_value(l_range, &val); + int left = val.value.integer; + vpi_get_value(r_range, &val); + int right = val.value.integer; + assert(right - left + 1 == array_size); + /*vpi_printf("array range: %d to %d\n", left, right);*/ + + /* Test accessing cells by index */ + vpi_printf("{ "); + int i; + for(i = 0; i < array_size; ++i) { + cell = vpi_handle_by_index(array, i); + val.format = vpiObjTypeVal; + vpi_get_value(cell, &val); + + if(val.format == vpiRealVal) + vpi_printf("%f", val.value.real); + else if(val.format == vpiStringVal) + vpi_printf("%s", val.value.str); + else { // convenient way to handle all other formats + val.format = vpiDecStrVal; + vpi_get_value(cell, &val); // sorry for another vpi call + vpi_printf("%s", val.value.str); + } + + if(i != array_size - 1) vpi_printf(", "); + } + vpi_printf(" }\n"); + + return 0; +} + +static PLI_INT32 increase_array_vals_calltf(ICARUS_VPI_CONST PLI_BYTE8*name) +{ + (void)name; /* Parameter is not used. */ + + vpiHandle callh = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv, array, array_iterator, cell; + PLI_INT32 iter_type; + s_vpi_value val; + + /* Fetch arguments */ + argv = vpi_iterate(vpiArgument, callh); + assert(argv); + array = vpi_scan(argv); + assert(array); + vpi_free_object(argv); + + switch(vpi_get(vpiType, array)) { + case vpiArrayType: + case vpiRegArray: + iter_type = vpiReg; + break; + + case vpiMemory: + iter_type = vpiMemoryWord; + break; + + default: + vpi_printf("sorry: increase_array_vals: missing iterator for " + "the given array type\n"); + return 0; + } + + /* Test accessing cells with iterators */ + array_iterator = vpi_iterate(iter_type, array); + while((cell = vpi_scan(array_iterator))) { + /* Test format recognition */ + val.format = vpiObjTypeVal; + vpi_get_value(cell, &val); + + /* Increase the read value */ + switch(val.format) { + case vpiIntVal: + ++val.value.integer; + break; + + case vpiVectorVal: + /* Only support a single aval */ + assert((uint32_t)val.value.vector->aval < UINT_MAX); + assert(val.value.vector->bval == 0); + ++val.value.vector->aval; + break; + + case vpiRealVal: + ++val.value.real; + break; + + case vpiStringVal: + { + char*s = val.value.str; + while(*s) ++*s++; // oh yeah, I love C + } + break; + + default: + vpi_printf("sorry: increase_array_vals: format not implemented\n"); + return 0; + } + + /* Test data write */ + vpi_put_value(cell, &val, 0, vpiNoDelay); + } + + return 0; +} + + +static PLI_INT32 one_arg_array_compiletf(ICARUS_VPI_CONST PLI_BYTE8*user_data) +{ + (void) user_data; /* Parameter is not used. */ + + vpiHandle systf_handle, arg_iterator, arg_handle; + PLI_INT32 arg_type; + + /* obtain a handle to the system task instance */ + systf_handle = vpi_handle(vpiSysTfCall, NULL); + if (systf_handle == NULL) { + vpi_printf("ERROR: $display_array failed to obtain systf handle\n"); + vpi_control(vpiFinish,0); /* abort simulation */ + return 0; + } + + /* obtain handles to system task arguments */ + arg_iterator = vpi_iterate(vpiArgument, systf_handle); + if (arg_iterator == NULL) { + vpi_printf("ERROR: $display_array requires exactly 1 argument\n"); + vpi_control(vpiFinish, 0); + return 0; + } + + /* check the type of object in system task arguments */ + arg_handle = vpi_scan(arg_iterator); + if (vpi_scan(arg_iterator) != NULL) { /* are there more arguments? */ + vpi_printf("ERROR: $display_array takes only 1 argument\n"); + vpi_free_object(arg_iterator); + vpi_control(vpiFinish, 0); + return 0; + } + + arg_type = vpi_get(vpiType, arg_handle); + if (arg_type != vpiArrayType && arg_type != vpiRegArray && + arg_type != vpiMemory) { + vpi_printf("%d", arg_type); // TODO remove + vpi_printf("ERROR: $display_array works only with arrays\n"); + vpi_free_object(arg_iterator); + vpi_control(vpiFinish, 0); + return 0; + } + + return 0; +} + +static void test_array_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$display_array"; + tf_data.calltf = display_array_calltf; + tf_data.compiletf = one_arg_array_compiletf; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.tfname = "$increase_array_vals"; + tf_data.calltf = increase_array_vals_calltf; + tf_data.compiletf = one_arg_array_compiletf; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); +} + +/* + * This is a table of register functions. This table is the external + * symbol that the simulator looks for when loading this .vpi module. + */ +void (*vlog_startup_routines[])(void) = { + test_array_register, + 0 +}; diff --git a/ivtest/vpi/display_array.v b/ivtest/vpi/display_array.v new file mode 100644 index 000000000..e4fdf1af1 --- /dev/null +++ b/ivtest/vpi/display_array.v @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2014 CERN + * @author Maciej Suminski + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +// Test for VPI functions handling dynamic arrays + +module main(); +initial + begin + int int_darray[]; + real real_darray[]; + bit [63:0] bit_darray[]; + string string_darray[]; + + int_darray = new[4]; + int_darray = '{1, 2, 3, 4}; + $display_array(int_darray); + $increase_array_vals(int_darray); + $display_array(int_darray); + + real_darray = new[2]; + real_darray = '{2.2, 2.3}; + $increase_array_vals(real_darray); + $display_array(real_darray); + + bit_darray = new[4]; + bit_darray = '{64'hdeadbeefcafebabe, 64'h0badc0dec0dec0de, + 64'h0123456789abcdef, 64'hfedcba9876543210}; + $increase_array_vals(bit_darray); + $display_array(bit_darray); + + string_darray = new[4]; + string_darray = '{"test string", "another one", "yet one more", "the last one"}; + $increase_array_vals(string_darray); + $display_array(string_darray); + end +endmodule diff --git a/ivtest/vpi/event1.c b/ivtest/vpi/event1.c new file mode 100644 index 000000000..c1e8373af --- /dev/null +++ b/ivtest/vpi/event1.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2003 Michael Ruff (mruff at chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test that named events are passed properly to system tasks. + */ +#include +#include +#include "vpi_user.h" + +static int num; + +#ifdef IVERILOG_V0_8 +static PLI_INT32 CompileTF(char *x) +#else +static PLI_INT32 CompileTF(PLI_BYTE8 *x) +#endif +{ + vpiHandle sys = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle arg; + int first = 1; + + (void)x; /* Parameter is not used. */ + + vpi_printf("%s (", vpi_get_str(vpiName, sys)); + while ((arg = vpi_scan(argv))) { + if (!first) + vpi_printf(", "); + else + first = 0; + vpi_printf("%s [type = %d]", + vpi_get_str(vpiFullName, arg), (int)vpi_get(vpiType, arg)); + if (vpi_get(vpiType, arg) == vpiNamedEvent) num++; + } + vpi_printf(")\n"); + if (num == 2) vpi_printf("PASSED\n"); + return 0; +} + +static void Register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$test"; + tf_data.calltf = 0; + tf_data.compiletf = CompileTF; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[]) (void) = { Register, 0}; diff --git a/ivtest/vpi/event1.v b/ivtest/vpi/event1.v new file mode 100644 index 000000000..bba36aa10 --- /dev/null +++ b/ivtest/vpi/event1.v @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2003 Michael Ruff (mruff at chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * Test that named events are passed properly to system tasks. + */ +module test(); + + event evt, evt2; + + initial begin + //->evt; + $test(evt, evt2, test); + end + +endmodule diff --git a/ivtest/vpi/event2.c b/ivtest/vpi/event2.c new file mode 100644 index 000000000..b3aa52088 --- /dev/null +++ b/ivtest/vpi/event2.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2003 Michael Ruff (mruff at chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test verifies deletion of event callbacks + */ + +#include +#include "vpi_user.h" + +static vpiHandle Handle; + +static PLI_INT32 +Callback(s_cb_data *data) +{ + s_vpi_time t; + static int count = 0; + + (void)data; /* Parameter is not used. */ + + t.type = vpiScaledRealTime; + vpi_get_time(0, &t); + + vpi_printf("Callback @ %.1f\n", t.real); + + if (count>1) { + vpi_printf("vpi_remove_cb returned %d @ %.1f\n", + (int)vpi_remove_cb(Handle), t.real); + } + + count++; + + return 0; +} + +static PLI_INT32 +CallbackRegister(s_cb_data *data) +{ + vpiHandle hand; + s_cb_data cb_data; + s_vpi_time timerec = { vpiSimTime, 0, 0, 0 }; + + (void)data; /* Parameter is not used. */ + + hand = vpi_handle_by_name("test.e", 0); + assert(hand); + + cb_data.time = &timerec; + cb_data.value = 0; + cb_data.user_data = (char *)hand; + cb_data.obj = hand; + cb_data.reason = cbValueChange; + cb_data.cb_rtn = Callback; + Handle = vpi_register_cb(&cb_data); + + return (0); +} + + +static void +VPIRegister(void) +{ + s_cb_data cb_data; + s_vpi_time timerec = { vpiSuppressTime, 0, 0, 0 }; + + cb_data.time = &timerec; + cb_data.value = 0; + cb_data.user_data = 0; + cb_data.obj = 0; + cb_data.reason = cbEndOfCompile; + cb_data.cb_rtn = CallbackRegister; + + vpi_register_cb(&cb_data); +} + +void (*vlog_startup_routines[]) (void) = { VPIRegister, 0}; diff --git a/ivtest/vpi/event2.v b/ivtest/vpi/event2.v new file mode 100644 index 000000000..fa8180eb8 --- /dev/null +++ b/ivtest/vpi/event2.v @@ -0,0 +1,9 @@ +module test; + event e; + initial begin + repeat (5) begin + #10; + ->e; + end + end +endmodule diff --git a/ivtest/vpi/final.c b/ivtest/vpi/final.c new file mode 100644 index 000000000..7a888c6d1 --- /dev/null +++ b/ivtest/vpi/final.c @@ -0,0 +1,28 @@ +#include +#include + +static PLI_INT32 end_of_sim_cb(struct t_cb_data *x) +{ + (void)x; /* Parameter is not used. */ + + vpi_printf("In VPI cbEndOfSimulation callback.\n"); + return 0; +} + +static void cb_register(void) +{ + s_cb_data cb_data; + memset(&cb_data, 0, sizeof(s_cb_data)); + cb_data.reason = cbEndOfSimulation; + cb_data.cb_rtn = end_of_sim_cb; + vpi_register_cb(&cb_data); +} + +/* + * This is a table of register functions. This table is the external + * symbol that the simulator looks for when loading this .vpi module. + */ +void (*vlog_startup_routines[])(void) = { + cb_register, + 0 +}; diff --git a/ivtest/vpi/final.v b/ivtest/vpi/final.v new file mode 100644 index 000000000..b26fcb982 --- /dev/null +++ b/ivtest/vpi/final.v @@ -0,0 +1,4 @@ +module tb; +initial $finish(0); +final $display("In final statement."); +endmodule diff --git a/ivtest/vpi/find_sig.c b/ivtest/vpi/find_sig.c new file mode 100644 index 000000000..a17c36053 --- /dev/null +++ b/ivtest/vpi/find_sig.c @@ -0,0 +1,39 @@ + +/* + */ +# include +# include + +static int sn_calltf(char*user_data) +{ + vpiHandle obj = vpi_handle_by_name("xor_try.unused", 0); + + (void)user_data; /* Parameter is not used. */ + + if (obj==0) { + vpi_printf("FAILED -- no xor_try.unused\n"); + return 0; + } + + vpi_printf("PASSED\n"); + return 0; +} + +static void vpi_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.calltf = sn_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.tfname = "$sn"; + tf_data.user_data = 0; + + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[])(void) = { + vpi_register, + 0 +}; diff --git a/ivtest/vpi/find_sig.v b/ivtest/vpi/find_sig.v new file mode 100644 index 000000000..c1def4388 --- /dev/null +++ b/ivtest/vpi/find_sig.v @@ -0,0 +1,9 @@ +//--------------------------------------------------------------------------- +// +//--------------------------------------------------------------------------- + module xor_try; + + (* ivl_do_not_elide *) reg unused; + initial $sn; + endmodule + diff --git a/ivtest/vpi/force.c b/ivtest/vpi/force.c new file mode 100644 index 000000000..da6c5655e --- /dev/null +++ b/ivtest/vpi/force.c @@ -0,0 +1,133 @@ +# include +# include + +static PLI_INT32 peek_calltf(PLI_BYTE8 *xx) +{ + s_vpi_value val; + + vpiHandle sys = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle arg; + + (void)xx; + + arg = vpi_scan(argv); + vpi_free_object(argv); /* Free iterator since we did not scan to NULL. */ + assert(arg != 0); + + val.value.str = ""; + val.format = vpiBinStrVal; + vpi_get_value(arg, &val); + vpi_printf("peek : %s\n", val.value.str); + + return 0; +} + +static int count = 0; + +static PLI_INT32 poke_calltf(PLI_BYTE8 *xx) +{ + s_vpi_value val; + + vpiHandle sys = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle arg; + + (void)xx; + + arg = vpi_scan(argv); + vpi_free_object(argv); /* Free iterator since we did not scan to NULL. */ + assert(arg != 0); + + val.value.integer = count++; + val.format = vpiIntVal; + vpi_put_value(arg, &val, 0, vpiNoDelay); + vpi_printf("poke : %d\n", val.value.integer); + + return 0; +} + +static PLI_INT32 force_calltf(PLI_BYTE8 *xx) +{ + s_vpi_value val; + + vpiHandle sys = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle arg; + + (void)xx; + + arg = vpi_scan(argv); + vpi_free_object(argv); /* Free iterator since we did not scan to NULL. */ + assert(arg != 0); + + val.value.str = "10"; + val.format = vpiBinStrVal; + vpi_put_value(arg, &val, 0, vpiForceFlag); + vpi_printf("force : %s\n", val.value.str); + + return 0; +} + +static PLI_INT32 release_calltf(PLI_BYTE8 *xx) +{ + s_vpi_value val; + + vpiHandle sys = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle arg; + + (void)xx; + + arg = vpi_scan(argv); + vpi_free_object(argv); /* Free iterator since we did not scan to NULL. */ + assert(arg != 0); + + val.format = vpiBinStrVal; + vpi_put_value(arg, &val, 0, vpiReleaseFlag); + vpi_printf("release : %s\n", val.value.str); + + return 0; +} + +void peekpoke_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$peek"; + tf_data.calltf = peek_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.tfname = "$poke"; + tf_data.calltf = poke_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.tfname = "$force"; + tf_data.calltf = force_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.tfname = "$release"; + tf_data.calltf = release_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); +} + +/* + * This is a table of register functions. This table is the external + * symbol that the simulator looks for when loading this .vpi module. + */ +void (*vlog_startup_routines[])(void) = { + peekpoke_register, + 0 +}; diff --git a/ivtest/vpi/force_real.c b/ivtest/vpi/force_real.c new file mode 100644 index 000000000..64bb27d31 --- /dev/null +++ b/ivtest/vpi/force_real.c @@ -0,0 +1,133 @@ +# include +# include + +static PLI_INT32 peek_calltf(PLI_BYTE8 *xx) +{ + s_vpi_value val; + + vpiHandle sys = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle arg; + + (void)xx; + + arg = vpi_scan(argv); + vpi_free_object(argv); /* Free iterator since we did not scan to NULL. */ + assert(arg != 0); + + val.value.real = 0.0; + val.format = vpiRealVal; + vpi_get_value(arg, &val); + vpi_printf("peek : %f\n", val.value.real); + + return 0; +} + +static int count = 1.0; + +static PLI_INT32 poke_calltf(PLI_BYTE8 *xx) +{ + s_vpi_value val; + + vpiHandle sys = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle arg; + + (void)xx; + + arg = vpi_scan(argv); + vpi_free_object(argv); /* Free iterator since we did not scan to NULL. */ + assert(arg != 0); + + val.value.real = count; count += 1.0; + val.format = vpiRealVal; + vpi_put_value(arg, &val, 0, vpiNoDelay); + vpi_printf("poke : %f\n", val.value.real); + + return 0; +} + +static PLI_INT32 force_calltf(PLI_BYTE8 *xx) +{ + s_vpi_value val; + + vpiHandle sys = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle arg; + + (void)xx; + + arg = vpi_scan(argv); + vpi_free_object(argv); /* Free iterator since we did not scan to NULL. */ + assert(arg != 0); + + val.value.real = 3.0; + val.format = vpiRealVal; + vpi_put_value(arg, &val, 0, vpiForceFlag); + vpi_printf("force : %f\n", val.value.real); + + return 0; +} + +static PLI_INT32 release_calltf(PLI_BYTE8 *xx) +{ + s_vpi_value val; + + vpiHandle sys = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle arg; + + (void)xx; + + arg = vpi_scan(argv); + vpi_free_object(argv); /* Free iterator since we did not scan to NULL. */ + assert(arg != 0); + + val.format = vpiRealVal; + vpi_put_value(arg, &val, 0, vpiReleaseFlag); + vpi_printf("release : %f\n", val.value.real); + + return 0; +} + +void peekpoke_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$peek"; + tf_data.calltf = peek_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.tfname = "$poke"; + tf_data.calltf = poke_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.tfname = "$force"; + tf_data.calltf = force_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.tfname = "$release"; + tf_data.calltf = release_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); +} + +/* + * This is a table of register functions. This table is the external + * symbol that the simulator looks for when loading this .vpi module. + */ +void (*vlog_startup_routines[])(void) = { + peekpoke_register, + 0 +}; diff --git a/ivtest/vpi/force_reg.v b/ivtest/vpi/force_reg.v new file mode 100644 index 000000000..e1d1905fa --- /dev/null +++ b/ivtest/vpi/force_reg.v @@ -0,0 +1,29 @@ +module test(); + +reg [1:0] IN; +wire [1:0] OUT; + +assign OUT = IN; + +initial begin + #1 $peek(IN); + #0 $display("display : %b", OUT); + #1 $force(IN); + #1 $peek(IN); + #0 $display("display : %b", OUT); + #1 $release(IN); + #0 $display("display : %b", OUT); + #1 $force(IN); + #1 $peek(IN); + #0 $display("display : %b", OUT); + #1 $poke(IN); + #1 $peek(IN); + #0 $display("display : %b", OUT); + #1 $release(IN); + #0 $display("display : %b", OUT); + #1 $poke(IN); + #1 $peek(IN); + #0 $display("display : %b", OUT); +end + +endmodule diff --git a/ivtest/vpi/force_reg_pv.v b/ivtest/vpi/force_reg_pv.v new file mode 100644 index 000000000..34524eca8 --- /dev/null +++ b/ivtest/vpi/force_reg_pv.v @@ -0,0 +1,29 @@ +module test(); + +reg [3:0] IN; +wire [3:0] OUT; + +assign OUT = IN; + +initial begin + #1 $peek(IN[2:1]); + #0 $display("display :%b", OUT); + #1 $force(IN[2:1]); + #1 $peek(IN[2:1]); + #0 $display("display :%b", OUT); + #1 $release(IN[2:1]); + #0 $display("display :%b", OUT); + #1 $force(IN[2:1]); + #1 $peek(IN[2:1]); + #0 $display("display :%b", OUT); + #1 $poke(IN[2:1]); + #1 $peek(IN[2:1]); + #0 $display("display :%b", OUT); + #1 $release(IN[2:1]); + #0 $display("display :%b", OUT); + #1 $poke(IN[2:1]); + #1 $peek(IN[2:1]); + #0 $display("display :%b", OUT); +end + +endmodule diff --git a/ivtest/vpi/force_reg_real.v b/ivtest/vpi/force_reg_real.v new file mode 100644 index 000000000..e87361987 --- /dev/null +++ b/ivtest/vpi/force_reg_real.v @@ -0,0 +1,29 @@ +module test(); + +real IN; +wire real OUT; + +assign OUT = IN; + +initial begin + #1 $peek(IN); + #0 $display("display : %f", OUT); + #1 $force(IN); + #1 $peek(IN); + #0 $display("display : %f", OUT); + #1 $release(IN); + #0 $display("display : %f", OUT); + #1 $force(IN); + #1 $peek(IN); + #0 $display("display : %f", OUT); + #1 $poke(IN); + #1 $peek(IN); + #0 $display("display : %f", OUT); + #1 $release(IN); + #0 $display("display : %f", OUT); + #1 $poke(IN); + #1 $peek(IN); + #0 $display("display : %f", OUT); +end + +endmodule diff --git a/ivtest/vpi/force_wire.v b/ivtest/vpi/force_wire.v new file mode 100644 index 000000000..b61faca32 --- /dev/null +++ b/ivtest/vpi/force_wire.v @@ -0,0 +1,29 @@ +module test(); + +wire [1:0] IN; +wire [1:0] OUT; + +assign OUT = IN; + +initial begin + #1 $peek(IN); + #0 $display("display : %b", OUT); + #1 $force(IN); + #1 $peek(IN); + #0 $display("display : %b", OUT); + #1 $release(IN); + #0 $display("display : %b", OUT); + #1 $force(IN); + #1 $peek(IN); + #0 $display("display : %b", OUT); + #1 $poke(IN); + #1 $peek(IN); + #0 $display("display : %b", OUT); + #1 $release(IN); + #0 $display("display : %b", OUT); + #1 $poke(IN); + #1 $peek(IN); + #0 $display("display : %b", OUT); +end + +endmodule diff --git a/ivtest/vpi/force_wire_pv.v b/ivtest/vpi/force_wire_pv.v new file mode 100644 index 000000000..5793d569b --- /dev/null +++ b/ivtest/vpi/force_wire_pv.v @@ -0,0 +1,29 @@ +module test(); + +wire [3:0] IN; +wire [3:0] OUT; + +assign OUT = IN; + +initial begin + #1 $peek(IN[2:1]); + #0 $display("display :%b", OUT); + #1 $force(IN[2:1]); + #1 $peek(IN[2:1]); + #0 $display("display :%b", OUT); + #1 $release(IN[2:1]); + #0 $display("display :%b", OUT); + #1 $force(IN[2:1]); + #1 $peek(IN[2:1]); + #0 $display("display :%b", OUT); + #1 $poke(IN[2:1]); + #1 $peek(IN[2:1]); + #0 $display("display :%b", OUT); + #1 $release(IN[2:1]); + #0 $display("display :%b", OUT); + #1 $poke(IN[2:1]); + #1 $peek(IN[2:1]); + #0 $display("display :%b", OUT); +end + +endmodule diff --git a/ivtest/vpi/force_wire_real.v b/ivtest/vpi/force_wire_real.v new file mode 100644 index 000000000..460013793 --- /dev/null +++ b/ivtest/vpi/force_wire_real.v @@ -0,0 +1,29 @@ +module test(); + +wire real IN; +wire real OUT; + +assign OUT = IN; + +initial begin + #1 $peek(IN); + #0 $display("display : %f", OUT); + #1 $force(IN); + #1 $peek(IN); + #0 $display("display : %f", OUT); + #1 $release(IN); + #0 $display("display : %f", OUT); + #1 $force(IN); + #1 $peek(IN); + #0 $display("display : %f", OUT); + #1 $poke(IN); + #1 $peek(IN); + #0 $display("display : %f", OUT); + #1 $release(IN); + #0 $display("display : %f", OUT); + #1 $poke(IN); + #1 $peek(IN); + #0 $display("display : %f", OUT); +end + +endmodule diff --git a/ivtest/vpi/genblk_direct.v b/ivtest/vpi/genblk_direct.v new file mode 100644 index 000000000..e271c4539 --- /dev/null +++ b/ivtest/vpi/genblk_direct.v @@ -0,0 +1,201 @@ +module test; + +// test name collisions +parameter genblk1 = 0; +localparam genblk2 = 0; + +typedef reg genblk3; + +reg genblk4; +wire genblk5; +event genblk6; + +class genblk7; +endclass + +function genblk8(); +endfunction; + +task genblk9; +endtask + +parameter TRUE = 1; + +genvar i; +genvar j; + +for (i = 0; i < 2; i = i + 1) + reg r1 = 1; + +for (i = 0; i < 2; i = i + 1) + for (j = 0; j < 2; j = j + 1) + reg r2 = 1; + +for (i = 0; i < 2; i = i + 1) + case (TRUE) + 0: reg r3a = 1; + 1: reg r3b = 1; + endcase + +for (i = 0; i < 2; i = i + 1) + if (TRUE) + reg r4a = 1; + else + reg r4b = 1; + +for (i = 0; i < 2; i = i + 1) + if (!TRUE) + reg r5a = 1; + else if (TRUE) + reg r5b = 1; + else + reg r5c = 1; + +for (i = 0; i < 2; i = i + 1) + if (!TRUE) + reg r6a = 1; + else if (!TRUE) + reg r6b = 1; + else + reg r6c = 1; + +case (TRUE) + 0: reg r7a = 1; + 1: reg r7b = 1; +endcase + +case (TRUE) + 0: case (TRUE) + 0: reg r8a = 1; + 1: reg r8b = 1; + endcase + 1: case (TRUE) + 0: reg r8c = 1; + 1: reg r8d = 1; + endcase +endcase + +case (TRUE) + 0: if (TRUE) + reg r9a = 1; + else + reg r9b = 1; + 1: if (TRUE) + reg r9c = 1; + else + reg r9d = 1; +endcase + +case (TRUE) + 0: if (!TRUE) + reg r10a = 1; + else if (TRUE) + reg r10b = 1; + else + reg r10c = 1; + 1: if (!TRUE) + reg r10d = 1; + else if (TRUE) + reg r10e = 1; + else + reg r10f = 1; +endcase + +case (TRUE) + 0: if (!TRUE) + reg r11a = 1; + else if (!TRUE) + reg r11b = 1; + else + reg r11c = 1; + 1: if (!TRUE) + reg r11d = 1; + else if (!TRUE) + reg r11e = 1; + else + reg r11f = 1; +endcase + +if (TRUE) + reg r12a = 1; +else + reg r12b = 1; + +if (!TRUE) + reg r13a = 1; +else if (TRUE) + reg r13b = 1; +else + reg r13c = 1; + +if (!TRUE) + reg r14a = 1; +else if (!TRUE) + reg r14b = 1; +else + reg r14c = 1; + +if (TRUE) + if (TRUE) + reg r15a = 1; + else + reg r15b = 1; +else + reg r15c = 1; + +if (TRUE) + if (!TRUE) + reg r16a = 1; + else + reg r16b = 1; +else + reg r16c = 1; + +if (TRUE) + case (TRUE) + 0: reg r17a = 1; + 1: reg r17b = 1; + endcase +else + case (TRUE) + 0: reg r17c = 1; + 1: reg r17d = 1; + endcase + +if (!TRUE) + case (TRUE) + 0: reg r18a = 1; + 1: reg r18b = 1; + endcase +else if (TRUE) + case (TRUE) + 0: reg r18c = 1; + 1: reg r18d = 1; + endcase +else + case (TRUE) + 0: reg r18e = 1; + 1: reg r18f = 1; + endcase + +if (!TRUE) + case (TRUE) + 0: reg r19a = 1; + 1: reg r19b = 1; + endcase +else if (!TRUE) + case (TRUE) + 0: reg r19c = 1; + 1: reg r19d = 1; + endcase +else + case (TRUE) + 0: reg r19e = 1; + 1: reg r19f = 1; + endcase + +initial begin + $list_regs; +end + +endmodule diff --git a/ivtest/vpi/genblk_named.v b/ivtest/vpi/genblk_named.v new file mode 100644 index 000000000..2b278fe82 --- /dev/null +++ b/ivtest/vpi/genblk_named.v @@ -0,0 +1,461 @@ +module test; + +parameter TRUE = 1; + +genvar i; +genvar j; + +for (i = 0; i < 2; i = i + 1) begin : l1 + reg r1 = 1; +end + +for (i = 0; i < 2; i = i + 1) begin : l2 + for (j = 0; j < 2; j = j + 1) begin : l1 + reg r2 = 1; + end +end + +for (i = 0; i < 2; i = i + 1) begin : l3 + case (TRUE) + 0: begin : c1 + reg r3a = 1; + end + 1: begin : c1 + reg r3b = 1; + end + endcase +end + +for (i = 0; i < 2; i = i + 1) begin : l4 + if (TRUE) + begin : i1 + reg r4a = 1; + end + else + begin : i1 + reg r4b = 1; + end +end + +for (i = 0; i < 2; i = i + 1) begin : l5 + if (!TRUE) + begin : i1 + reg r5a = 1; + end + else + begin : i1 + if (TRUE) + begin : i1 + reg r5b = 1; + end + else + begin : i1 + reg r5c = 1; + end + end +end + +for (i = 0; i < 2; i = i + 1) begin : l6 + if (!TRUE) + begin : i1 + reg r6a = 1; + end + else + begin : i1 + if (!TRUE) + begin : i1 + reg r6b = 1; + end + else + begin : i1 + reg r6c = 1; + end + end +end + +case (TRUE) + 0: begin : c1 + reg r7a = 1; + end + 1: begin : c1 + reg r7b = 1; + end +endcase + +case (TRUE) + 0: begin : c2 + case (TRUE) + 0: begin : c1 + reg r8a = 1; + end + 1: begin : c1 + reg r8b = 1; + end + endcase + end + 1: begin : c2 + case (TRUE) + 0: begin : c1 + reg r8c = 1; + end + 1: begin : c1 + reg r8d = 1; + end + endcase + end +endcase + +case (TRUE) + 0: begin : c3 + if (TRUE) + begin : i1 + reg r9a = 1; + end + else + begin : i1 + reg r9b = 1; + end + end + 1: begin : c3 + if (TRUE) + begin : i1 + reg r9c = 1; + end + else + begin : i1 + reg r9d = 1; + end + end +endcase + +case (TRUE) + 0: begin : c4 + if (!TRUE) + begin : i1 + reg r10a = 1; + end + else + begin : i1 + if (TRUE) + begin : i1 + reg r10b = 1; + end + else + begin : i1 + reg r10c = 1; + end + end + end + 1: begin : c4 + if (!TRUE) + begin : i1 + reg r10d = 1; + end + else + begin : i1 + if (TRUE) + begin : i1 + reg r10e = 1; + end + else + begin : i1 + reg r10f = 1; + end + end + end +endcase + +case (TRUE) + 0: begin : c5 + if (!TRUE) + begin : i1 + reg r11a = 1; + end + else + begin : i1 + if (!TRUE) + begin : i1 + reg r11b = 1; + end + else + begin : i1 + reg r11c = 1; + end + end + end + 1: begin : c5 + if (!TRUE) + begin : i1 + reg r11d = 1; + end + else + begin : i1 + if (!TRUE) + begin : i1 + reg r11e = 1; + end + else + begin : i1 + reg r11f = 1; + end + end + end +endcase + +case (TRUE) + 0: begin : c6 + if (!TRUE) + begin : i1 + reg r12a = 1; + end + else if (TRUE) + begin : i1 + reg r12b = 1; + end + else + begin : i1 + reg r12c = 1; + end + end + 1: begin : c6 + if (!TRUE) + begin : i1 + reg r12d = 1; + end + else if (TRUE) + begin : i1 + reg r12e = 1; + end + else + begin : i1 + reg r12f = 1; + end + end +endcase + +case (TRUE) + 0: begin : c7 + if (!TRUE) + begin : i1 + reg r13a = 1; + end + else if (!TRUE) + begin : i1 + reg r13b = 1; + end + else + begin : i1 + reg r13c = 1; + end + end + 1: begin : c7 + if (!TRUE) + begin : i1 + reg r13d = 1; + end + else if (!TRUE) + begin : i1 + reg r13e = 1; + end + else + begin : i1 + reg r13f = 1; + end + end +endcase + +if (TRUE) + begin : i01 + reg r14a = 1; + end +else + begin : i01 + reg r14b = 1; + end + +if (!TRUE) + begin : i02 + reg r15a = 1; + end +else + begin : i02 + if (TRUE) + begin : i1 + reg r15b = 1; + end + else + begin : i1 + reg r15c = 1; + end + end + +if (!TRUE) + begin : i03 + reg r16a = 1; + end +else + begin : i03 + if (!TRUE) + begin : i1 + reg r16b = 1; + end + else + begin : i1 + reg r16c = 1; + end + end + +if (!TRUE) + begin : i04 + reg r17a = 1; + end +else if (TRUE) + begin : i04 + reg r17b = 1; + end +else + begin : i04 + reg r17c = 1; + end + +if (!TRUE) + begin : i05 + reg r18a = 1; + end +else if (!TRUE) + begin : i05 + reg r18b = 1; + end +else + begin : i05 + reg r18c = 1; + end + +if (TRUE) + begin : i06 + if (TRUE) + begin : i1 + reg r19a = 1; + end + else + begin : i1 + reg r19b = 1; + end + end +else + begin : i06 + reg r19c = 1; + end + +if (TRUE) + begin : i07 + if (!TRUE) + begin : i1 + reg r20a = 1; + end + else + begin : i1 + reg r20b = 1; + end + end +else + begin : i07 + reg r20c = 1; + end + +if (TRUE) + begin : i08 + case (TRUE) + 0: begin : c1 + reg r21a = 1; + end + 1: begin : c1 + reg r21b = 1; + end + endcase + end +else + begin : i08 + case (TRUE) + 0: begin : c1 + reg r21c = 1; + end + 1: begin : c1 + reg r21d = 1; + end + endcase + end + +if (!TRUE) + begin : i09 + case (TRUE) + 0: begin : c1 + reg r22a = 1; + end + 1: begin : c1 + reg r22b = 1; + end + endcase + end +else if (TRUE) + begin : i09 + case (TRUE) + 0: begin : c1 + reg r22c = 1; + end + 1: begin : c1 + reg r22d = 1; + end + endcase + end +else + begin : i09 + case (TRUE) + 0: begin : c1 + reg r22e = 1; + end + 1: begin : c1 + reg r22f = 1; + end + endcase + end + +if (!TRUE) + begin : i10 + case (TRUE) + 0: begin : c1 + reg r23a = 1; + end + 1: begin : c1 + reg r23b = 1; + end + endcase + end +else if (!TRUE) + begin : i10 + case (TRUE) + 0: begin : c1 + reg r23c = 1; + end + 1: begin : c1 + reg r23d = 1; + end + endcase + end +else + begin : i10 + case (TRUE) + 0: begin : c1 + reg r23e = 1; + end + 1: begin : c1 + reg r23f = 1; + end + endcase + end + +initial begin + $list_regs; +end + +endmodule diff --git a/ivtest/vpi/genblk_names.c b/ivtest/vpi/genblk_names.c new file mode 100644 index 000000000..d413f145e --- /dev/null +++ b/ivtest/vpi/genblk_names.c @@ -0,0 +1,54 @@ +#include +#include +#include "vpi_user.h" + +static void display_scope(vpiHandle scope) +{ + vpiHandle iter; + vpiHandle item; + + iter = vpi_iterate(vpiReg, scope); + if (iter) { + while ( (item = vpi_scan(iter)) ) { + vpi_printf("reg %s\n", vpi_get_str(vpiFullName, item)); + } + } + + if (scope) { + iter = vpi_iterate(vpiInternalScope, scope); + } else { + iter = vpi_iterate(vpiModule, NULL); + } + if (iter) { + while ( (item = vpi_scan(iter)) ) { + display_scope(item); + } + } +} + +static PLI_INT32 list_regs_calltf(PLI_BYTE8*xx) +{ + (void)xx; /* Parameter is not used. */ + + display_scope(NULL); + + return 0; +} + +static void list_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$list_regs"; + tf_data.calltf = list_regs_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.user_data = "$list_regs"; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[])(void) = { + list_register, + 0 +}; diff --git a/ivtest/vpi/genblk_unnamed.v b/ivtest/vpi/genblk_unnamed.v new file mode 100644 index 000000000..6b6097341 --- /dev/null +++ b/ivtest/vpi/genblk_unnamed.v @@ -0,0 +1,472 @@ +module test; + +// force leading zero on outer scope genblk numbers +localparam genblk1 = 0; +localparam genblk2 = 0; +localparam genblk3 = 0; +localparam genblk4 = 0; +localparam genblk5 = 0; +localparam genblk6 = 0; +localparam genblk7 = 0; +localparam genblk8 = 0; +localparam genblk9 = 0; + +parameter TRUE = 1; + +genvar i; +genvar j; + +for (i = 0; i < 2; i = i + 1) begin + reg r1 = 1; +end + +for (i = 0; i < 2; i = i + 1) begin + for (j = 0; j < 2; j = j + 1) begin + reg r2 = 1; + end +end + +for (i = 0; i < 2; i = i + 1) begin + case (TRUE) + 0: begin + reg r3a = 1; + end + 1: begin + reg r3b = 1; + end + endcase +end + +for (i = 0; i < 2; i = i + 1) begin + if (TRUE) + begin + reg r4a = 1; + end + else + begin + reg r4b = 1; + end +end + +for (i = 0; i < 2; i = i + 1) begin + if (!TRUE) + begin + reg r5a = 1; + end + else + begin + if (TRUE) + begin + reg r5b = 1; + end + else + begin + reg r5c = 1; + end + end +end + +for (i = 0; i < 2; i = i + 1) begin + if (!TRUE) + begin + reg r6a = 1; + end + else + begin + if (!TRUE) + begin + reg r6b = 1; + end + else + begin + reg r6c = 1; + end + end +end + +case (TRUE) + 0: begin + reg r7a = 1; + end + 1: begin + reg r7b = 1; + end +endcase + +case (TRUE) + 0: begin + case (TRUE) + 0: begin + reg r8a = 1; + end + 1: begin + reg r8b = 1; + end + endcase + end + 1: begin + case (TRUE) + 0: begin + reg r8c = 1; + end + 1: begin + reg r8d = 1; + end + endcase + end +endcase + +case (TRUE) + 0: begin + if (TRUE) + begin + reg r9a = 1; + end + else + begin + reg r9b = 1; + end + end + 1: begin + if (TRUE) + begin + reg r9c = 1; + end + else + begin + reg r9d = 1; + end + end +endcase + +case (TRUE) + 0: begin + if (!TRUE) + begin + reg r10a = 1; + end + else + begin + if (TRUE) + begin + reg r10b = 1; + end + else + begin + reg r10c = 1; + end + end + end + 1: begin + if (!TRUE) + begin + reg r10d = 1; + end + else + begin + if (TRUE) + begin + reg r10e = 1; + end + else + begin + reg r10f = 1; + end + end + end +endcase + +case (TRUE) + 0: begin + if (!TRUE) + begin + reg r11a = 1; + end + else + begin + if (!TRUE) + begin + reg r11b = 1; + end + else + begin + reg r11c = 1; + end + end + end + 1: begin + if (!TRUE) + begin + reg r11d = 1; + end + else + begin + if (!TRUE) + begin + reg r11e = 1; + end + else + begin + reg r11f = 1; + end + end + end +endcase + +case (TRUE) + 0: begin + if (!TRUE) + begin + reg r12a = 1; + end + else if (TRUE) + begin + reg r12b = 1; + end + else + begin + reg r12c = 1; + end + end + 1: begin + if (!TRUE) + begin + reg r12d = 1; + end + else if (TRUE) + begin + reg r12e = 1; + end + else + begin + reg r12f = 1; + end + end +endcase + +case (TRUE) + 0: begin + if (!TRUE) + begin + reg r13a = 1; + end + else if (!TRUE) + begin + reg r13b = 1; + end + else + begin + reg r13c = 1; + end + end + 1: begin + if (!TRUE) + begin + reg r13d = 1; + end + else if (!TRUE) + begin + reg r13e = 1; + end + else + begin + reg r13f = 1; + end + end +endcase + +if (TRUE) + begin + reg r14a = 1; + end +else + begin + reg r14b = 1; + end + +if (!TRUE) + begin + reg r15a = 1; + end +else + begin + if (TRUE) + begin + reg r15b = 1; + end + else + begin + reg r15c = 1; + end + end + +if (!TRUE) + begin + reg r16a = 1; + end +else + begin + if (!TRUE) + begin + reg r16b = 1; + end + else + begin + reg r16c = 1; + end + end + +if (!TRUE) + begin + reg r17a = 1; + end +else if (TRUE) + begin + reg r17b = 1; + end +else + begin + reg r17c = 1; + end + +if (!TRUE) + begin + reg r18a = 1; + end +else if (!TRUE) + begin + reg r18b = 1; + end +else + begin + reg r18c = 1; + end + +if (TRUE) + begin + if (TRUE) + begin + reg r19a = 1; + end + else + begin + reg r19b = 1; + end + end +else + begin + reg r19c = 1; + end + +if (TRUE) + begin + if (!TRUE) + begin + reg r20a = 1; + end + else + begin + reg r20b = 1; + end + end +else + begin + reg r20c = 1; + end + +if (TRUE) + begin + case (TRUE) + 0: begin + reg r21a = 1; + end + 1: begin + reg r21b = 1; + end + endcase + end +else + begin + case (TRUE) + 0: begin + reg r21c = 1; + end + 1: begin + reg r21d = 1; + end + endcase + end + +if (!TRUE) + begin + case (TRUE) + 0: begin + reg r22a = 1; + end + 1: begin + reg r22b = 1; + end + endcase + end +else if (TRUE) + begin + case (TRUE) + 0: begin + reg r22c = 1; + end + 1: begin + reg r22d = 1; + end + endcase + end +else + begin + case (TRUE) + 0: begin + reg r22e = 1; + end + 1: begin + reg r22f = 1; + end + endcase + end + +if (!TRUE) + begin + case (TRUE) + 0: begin + reg r23a = 1; + end + 1: begin + reg r23b = 1; + end + endcase + end +else if (!TRUE) + begin + case (TRUE) + 0: begin + reg r23c = 1; + end + 1: begin + reg r23d = 1; + end + endcase + end +else + begin + case (TRUE) + 0: begin + reg r23e = 1; + end + 1: begin + reg r23f = 1; + end + endcase + end + +initial begin + $list_regs; +end + +endmodule diff --git a/ivtest/vpi/getp.c b/ivtest/vpi/getp.c new file mode 100644 index 000000000..3085d69ee --- /dev/null +++ b/ivtest/vpi/getp.c @@ -0,0 +1,40 @@ +#include "veriuser.h" + +static int +calltf(int ud, int reason) +{ + int i; + PLI_BYTE8 *inst = tf_getinstance(); + + (void)ud; /* Parameter is not used. */ + (void)reason; /* Parameter is not used. */ + + for (i = 1; i < 5; i++) { + io_printf("tf_getp(%d)\t\t-> %d\n", i, (int)tf_getp(i)); + io_printf("tf_igetp(%d,inst)\t-> %d\n", i, (int)tf_igetp(i,inst)); + io_printf("tf_getrealp(%d)\t\t-> %f\n", i, tf_getrealp(i)); + io_printf("tf_igetrealp(%d,inst)\t-> %f\n", + i, tf_igetrealp(i,inst)); + } + + return 0; +} + +static int sizetf(int ud, int reason) +{ + (void)ud; /* Parameter is not used. */ + (void)reason; /* Parameter is not used. */ + return 32; +} + +s_tfcell veriusertfs[2] = { + {usertask, 0, 0, sizetf, calltf, 0, "$mytest", 1, 0, 0, {0} }, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0} } +}; + +static void veriusertfs_register(void) +{ + veriusertfs_register_table(veriusertfs); +} + +void (*vlog_startup_routines[])(void) = { &veriusertfs_register, 0 }; diff --git a/ivtest/vpi/getp.v b/ivtest/vpi/getp.v new file mode 100644 index 000000000..6c5a351b2 --- /dev/null +++ b/ivtest/vpi/getp.v @@ -0,0 +1,5 @@ +module test; + initial begin + $mytest(1,9.6,3); + end +endmodule diff --git a/ivtest/vpi/hello_poke.c b/ivtest/vpi/hello_poke.c new file mode 100644 index 000000000..d2b6fb922 --- /dev/null +++ b/ivtest/vpi/hello_poke.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2001 Picture Elements, Inc. + * Stephen Williams (steve@picturel.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +# include +# include + +#ifdef IVERILOG_V0_8 +static PLI_INT32 my_hello_calltf(char *xx) +#else +static PLI_INT32 my_hello_calltf(PLI_BYTE8 *xx) +#endif +{ + s_vpi_value value; + + (void)xx; /* Parameter is not used. */ + + vpiHandle sys = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle arg; + + if (argv == 0) { + vpi_printf("ERROR: $hello_poke requires one argument\n"); + vpi_sim_control(vpiFinish, 1); + return 0; + } + + arg = vpi_scan(argv); + assert(arg != 0); + + value.format = vpiStringVal; + value.value.str = "Hello"; + + vpi_put_value(arg, &value, 0, vpiNoDelay); + + arg = vpi_scan(argv); + if (arg != 0) { + vpi_printf("ERROR: too many arguments to $hello_poke\n"); + vpi_sim_control(vpiFinish, 1); + } + + return 0; +} + +static void my_hello_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$hello_poke"; + tf_data.calltf = my_hello_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); +} + +/* + * This is a table of register functions. This table is the external + * symbol that the simulator looks for when loading this .vpi module. + */ +void (*vlog_startup_routines[])(void) = { + my_hello_register, + 0 +}; diff --git a/ivtest/vpi/hello_poke.v b/ivtest/vpi/hello_poke.v new file mode 100644 index 000000000..9b1cf51d9 --- /dev/null +++ b/ivtest/vpi/hello_poke.v @@ -0,0 +1,23 @@ +module main; + + reg [5*8-1 : 0] hello; + + initial begin + hello = "XXXXX"; + + if (hello !== "XXXXX") begin + $display("FAILED -- X = %h", hello); + $finish; + end + + $hello_poke(hello); + + if (hello !== "Hello") begin + $display("FAILED -- Hello = %h", hello); + $finish; + end + + $display("PASSED"); + end // initial begin + +endmodule // main diff --git a/ivtest/vpi/hello_tf.c b/ivtest/vpi/hello_tf.c new file mode 100644 index 000000000..8566ad03d --- /dev/null +++ b/ivtest/vpi/hello_tf.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +# include +# include + +#ifdef IVERILOG_V0_8 +static PLI_INT32 my_hello_calltf(char *xx) +#else +static PLI_INT32 my_hello_calltf(PLI_BYTE8 *xx) +#endif +{ + (void)xx; /* Parameter is not used. */ + io_printf("Hello World, from VPI.\n"); + return 0; +} + +static void my_hello_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$my_hello"; + tf_data.calltf = my_hello_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); +} + +/* + * This is a table of register functions. This table is the external + * symbol that the simulator looks for when loading this .vpi module. + */ +void (*vlog_startup_routines[])(void) = { + my_hello_register, + 0 +}; diff --git a/ivtest/vpi/hello_tf.v b/ivtest/vpi/hello_tf.v new file mode 100644 index 000000000..1c73ec986 --- /dev/null +++ b/ivtest/vpi/hello_tf.v @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + /* + * Here we have the canonical "Hello, World" program written in Verilog, + * with VPI. It uses the hello_vpi.vpi module that is compiled from + * the hello_vpi.c program also in this directory. See the + * hello_vpi.c for instructions on how to compile it. + * + * Compile this program with the command: + * + * iverilog -ohello_vpi hello_vpi.vl + * + * After churning for a little while, the program will create the output + * file "hello" which is compiled, linked and ready to run. Run this + * program like so: + * + * vvp -M. -mhello_vpi hello_vpi + * + * and the program will print the message to its output. Easy! For + * more on how to make the iverilog command work, see the iverilog + * manual page. + */ + +module main(); + +initial + begin + $my_hello; + $finish(0); + end + +endmodule diff --git a/ivtest/vpi/hello_vpi.c b/ivtest/vpi/hello_vpi.c new file mode 100644 index 000000000..06ad374cd --- /dev/null +++ b/ivtest/vpi/hello_vpi.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This file contains an example VPI module to demonstrate the tools + * to create vpi modules. To compile this module, use the iverilog-vpi + * command like so: + * + * iverilog-vpi hello_vpi.c + * + * The result is the hello_vpi.vpi module. See the hello_vpi.vl + * program for example Verilog code to call this module. + */ + +# include + +#ifdef IVERILOG_V0_8 +static PLI_INT32 my_hello_calltf(char *xx) +#else +static PLI_INT32 my_hello_calltf(PLI_BYTE8 *xx) +#endif +{ + (void)xx; /* Parameter is not used. */ + vpi_printf("Hello World, from VPI.\n"); + return 0; +} + +static void my_hello_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$my_hello"; + tf_data.calltf = my_hello_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); +} + +/* + * This is a table of register functions. This table is the external + * symbol that the simulator looks for when loading this .vpi module. + */ +void (*vlog_startup_routines[])(void) = { + my_hello_register, + 0 +}; diff --git a/ivtest/vpi/hello_vpi.v b/ivtest/vpi/hello_vpi.v new file mode 100644 index 000000000..1c73ec986 --- /dev/null +++ b/ivtest/vpi/hello_vpi.v @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2002 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + /* + * Here we have the canonical "Hello, World" program written in Verilog, + * with VPI. It uses the hello_vpi.vpi module that is compiled from + * the hello_vpi.c program also in this directory. See the + * hello_vpi.c for instructions on how to compile it. + * + * Compile this program with the command: + * + * iverilog -ohello_vpi hello_vpi.vl + * + * After churning for a little while, the program will create the output + * file "hello" which is compiled, linked and ready to run. Run this + * program like so: + * + * vvp -M. -mhello_vpi hello_vpi + * + * and the program will print the message to its output. Easy! For + * more on how to make the iverilog command work, see the iverilog + * manual page. + */ + +module main(); + +initial + begin + $my_hello; + $finish(0); + end + +endmodule diff --git a/ivtest/vpi/listparams.c b/ivtest/vpi/listparams.c new file mode 100644 index 000000000..2bc0d21a9 --- /dev/null +++ b/ivtest/vpi/listparams.c @@ -0,0 +1,88 @@ +# include +# include +# include +# include + +#ifdef IVERILOG_V0_8 +static PLI_INT32 listparams_compiletf(char*name) +#else +static PLI_INT32 listparams_compiletf(PLI_BYTE8*name) +#endif +{ + (void)name; /* Parameter is not used. */ + return 0; +} + +static void param_by_name(vpiHandle scope, const char*key) +{ + vpiHandle iter = vpi_iterate(vpiParameter, scope); + vpiHandle item; + + while ( (item = vpi_scan(iter)) ) { + + s_vpi_value value; + + if (strcmp(key, vpi_get_str(vpiName,item)) != 0) + continue; + + vpi_printf("%8s: ", vpi_get_str(vpiName, item)); + + switch (vpi_get(vpiConstType, item)) { + case vpiStringConst: + value.format = vpiStringVal; + vpi_get_value(item, &value); + vpi_printf("%s", value.value.str); + break; + case vpiBinaryConst: + value.format = vpiBinStrVal; + vpi_get_value(item, &value); + vpi_printf("%s", value.value.str); + break; + default: + break; + } + + vpi_printf("\n"); + } +} + +#ifdef IVERILOG_V0_8 +static PLI_INT32 listparams_calltf(char*name) +#else +static PLI_INT32 listparams_calltf(PLI_BYTE8*name) +#endif +{ + vpiHandle sys = vpi_handle(vpiSysTfCall,0); + vpiHandle scope= vpi_handle(vpiScope, sys); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle item; + + (void)name; /* Parameter is not used. */ + + while ( (item = vpi_scan(argv)) ) { + s_vpi_value value; + value.format = vpiStringVal; + vpi_get_value(item, &value); + param_by_name(scope, value.value.str); + } + + return 0; +} + +static void listparams_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$listparams"; + tf_data.calltf = listparams_calltf; + tf_data.compiletf = listparams_compiletf; + tf_data.sizetf = 0; + tf_data.user_data = "$listparams"; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[])(void) = { + listparams_register, + 0 +}; diff --git a/ivtest/vpi/listparams.v b/ivtest/vpi/listparams.v new file mode 100644 index 000000000..e6b75acd2 --- /dev/null +++ b/ivtest/vpi/listparams.v @@ -0,0 +1,28 @@ +// Copyright (c) 2006 Stephen Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + + parameter foo = 4'b0101; + parameter str = "String Text"; + + initial begin + $listparams("foo", "str"); + end + +endmodule // main diff --git a/ivtest/vpi/memmon.c b/ivtest/vpi/memmon.c new file mode 100644 index 000000000..440a69409 --- /dev/null +++ b/ivtest/vpi/memmon.c @@ -0,0 +1,96 @@ +# include +# include + +#ifdef IVERILOG_V0_8 +static PLI_INT32 memmonitor_compiletf(char*name) +#else +static PLI_INT32 memmonitor_compiletf(PLI_BYTE8*name) +#endif +{ + vpiHandle sys = vpi_handle(vpiSysTfCall,0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle arg; + + if (argv == 0) { + vpi_printf("ERROR: %s expects at least 1 argument.\n", name); + vpi_control(vpiFinish, 1); + return 0; + } + + while ( (arg = vpi_scan(argv)) ) { + if (vpi_get(vpiType, arg) != vpiMemory) { + vpi_printf("ERROR: %s expects only memory arguments\n", name); + vpi_control(vpiFinish, 1); + return 0; + } + } + + return 0; +} + +static PLI_INT32 callback(struct t_cb_data*cb) +{ + vpi_printf("ValueChange: index=%d, value=%s\n", + (int)cb->index, cb->value->value.str); + return 0; +} + +static PLI_INT32 cleanup(struct t_cb_data*cb) +{ + free(cb->value); + return 0; +} + +#ifdef IVERILOG_V0_8 +static PLI_INT32 memmonitor_calltf(char*name) +#else +static PLI_INT32 memmonitor_calltf(PLI_BYTE8*name) +#endif +{ + vpiHandle sys = vpi_handle(vpiSysTfCall,0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle arg; + + (void)name; /* Parameter is not used. */ + + while ( (arg = vpi_scan(argv)) ) { + s_cb_data cb_data; + + cb_data.reason = cbValueChange; + cb_data.cb_rtn = callback; + cb_data.obj = arg; + cb_data.time = 0; + cb_data.value = malloc(sizeof(struct t_vpi_value)); + cb_data.index = 0; + cb_data.user_data = 0; + + cb_data.value->format = vpiBinStrVal; + cb_data.value->value.str = 0; + + vpi_register_cb(&cb_data); + + cb_data.reason = cbEndOfSimulation; + cb_data.cb_rtn = cleanup; + vpi_register_cb(&cb_data); + } + + return 0; +} + +static void memmonitor_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$memmonitor"; + tf_data.calltf = memmonitor_calltf; + tf_data.compiletf = memmonitor_compiletf; + tf_data.sizetf = 0; + tf_data.user_data = "$memmonitor"; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[])(void) = { + memmonitor_register, + 0 +}; diff --git a/ivtest/vpi/memmon.v b/ivtest/vpi/memmon.v new file mode 100644 index 000000000..b4ad4e3b9 --- /dev/null +++ b/ivtest/vpi/memmon.v @@ -0,0 +1,33 @@ +// Copyright (c) 2006 Stephen Williams +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module main; + + reg [7:0] mem [0:1]; + + initial begin + mem[0] = 0; + mem[1] = 1; + $memmonitor(mem); + + #1 mem[0] = 4; + #1 mem[1] = 5; + #1 $finish(0); + end + +endmodule // main diff --git a/ivtest/vpi/memwide.cc b/ivtest/vpi/memwide.cc new file mode 100644 index 000000000..b2b190be0 --- /dev/null +++ b/ivtest/vpi/memwide.cc @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com) + * Michael Runyan (mrunyan at chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test verifies named events can be peeked and poked. + */ + +#include +#include +#include +#include "vpi_user.h" + +static s_vpi_time suppress_time = { vpiSuppressTime, 0, 0, 0 }; + +static vpiHandle findReg(const char *name_); +static vpiHandle findMem(const char *name_); + +extern "C" PLI_INT32 +CallbackPeek(s_cb_data * /*data*/) +{ + vpiHandle handle; + + vpi_printf("!!!C++: callback\n"); + + // Find big_reg + if((handle=findReg("big_reg"))) { + unsigned size=vpi_get(vpiSize,handle); + vpi_printf("!!!C++: %s size is %d\n",vpi_get_str(vpiName,handle),size); + + s_vpi_value value; + + value.format=vpiVectorVal; + value.value.vector=NULL; + + vpi_get_value(handle,&value); + + for(unsigned i=0;(i*32) %s\n", tf_mipname()); + io_printf("tf_imipname(inst)\t-> %s\n", tf_imipname(inst)); + + return 0; +} + +static int sizetf(int ud, int reason) +{ + (void)ud; /* Parameter is not used. */ + (void)reason; /* Parameter is not used. */ + return 32; +} + +s_tfcell veriusertfs[2] = { + {usertask, 0, 0, sizetf, calltf, 0, "$mytest", 1, 0, 0, {0} }, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0} } +}; + + +static void veriusertfs_register(void) +{ + veriusertfs_register_table(veriusertfs); +} + +void (*vlog_startup_routines[])(void) = { &veriusertfs_register, 0 }; diff --git a/ivtest/vpi/mipname.v b/ivtest/vpi/mipname.v new file mode 100644 index 000000000..9a4ca75dc --- /dev/null +++ b/ivtest/vpi/mipname.v @@ -0,0 +1,13 @@ +module test3; + initial #1 $mytest; +endmodule + +module test2; + initial #2 $mytest; + test3 t3(); +endmodule + +module test; + initial #3 $mytest; + test2 t2(); +endmodule diff --git a/ivtest/vpi/myscope.c b/ivtest/vpi/myscope.c new file mode 100644 index 000000000..5e570f8d8 --- /dev/null +++ b/ivtest/vpi/myscope.c @@ -0,0 +1,38 @@ + +/* + */ +# include +# include + +static int sn_calltf(char*user_data) +{ + vpiHandle scope = vpi_handle(vpiScope, 0); + + (void)user_data; /* Parameter is not used. */ + + assert(scope); + + + vpi_printf("My scope name: %s (s.b. xor_try)\n", + vpi_get_str(vpiFullName, scope)); + return 0; +} + +static void vpi_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.calltf = sn_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.tfname = "$sn"; + tf_data.user_data = 0; + + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[])(void) = { + vpi_register, + 0 +}; diff --git a/ivtest/vpi/myscope.v b/ivtest/vpi/myscope.v new file mode 100644 index 000000000..c336c8389 --- /dev/null +++ b/ivtest/vpi/myscope.v @@ -0,0 +1,17 @@ +//--------------------------------------------------------------------------- +// +//--------------------------------------------------------------------------- + module xor_try; + + reg [1:0] inp_xor; // The two-bit inputs to the XOR + reg out_xor; // The XOR output + reg clk; + + initial begin clk = 1'b1; #10 $sn; #160 $finish(0); end + always #50 clk = ~clk; + // The clock + + always @(posedge clk) out_xor = #1 (inp_xor[0] ^ inp_xor[1]); + // The actual operation + endmodule + diff --git a/ivtest/vpi/myscope2.c b/ivtest/vpi/myscope2.c new file mode 100644 index 000000000..ca2c806b2 --- /dev/null +++ b/ivtest/vpi/myscope2.c @@ -0,0 +1,54 @@ + +/* + */ +# include +# include + +static char * instance = 0; +static int sn_calltf(int user_data, int reason) +{ + int high_time, low_time; + + (void)user_data; /* Parameter is not used. */ + + io_printf("... sn_calltf(reason=%d)\n", reason); + low_time = tf_igetlongtime(&high_time,instance); + io_printf("high_time=%d, low_time=%d\n", high_time, low_time); + return 0; +} + +int ise_vls_misc(int data, int reason, int paramvc) +{ + (void)paramvc; /* Parameter is not used. */ + + io_printf("... ise_vls_misc(reason=%d)\n", reason); + if (reason != reason_endofcompile) + return sn_calltf(data, reason); + else + return 0; +} + +int ise_startup(int data, int reason) +{ + (void)data; /* Parameter is not used. */ + + instance = tf_getinstance(); + io_printf("... ise_startup(reason=%d)\n", reason); + tf_isynchronize(instance); + return 1; +} + +static s_tfcell sn[2] = { + {usertask, 0, ise_startup, 0, sn_calltf, ise_vls_misc, "$sn", 1, 0, 0, {0} }, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0} } +}; + +static void veriusertfs_register(void) +{ + veriusertfs_register_table(sn); +} + +void (*vlog_startup_routines[])(void) = { + &veriusertfs_register, + 0 +}; diff --git a/ivtest/vpi/myscope2.v b/ivtest/vpi/myscope2.v new file mode 100644 index 000000000..c336c8389 --- /dev/null +++ b/ivtest/vpi/myscope2.v @@ -0,0 +1,17 @@ +//--------------------------------------------------------------------------- +// +//--------------------------------------------------------------------------- + module xor_try; + + reg [1:0] inp_xor; // The two-bit inputs to the XOR + reg out_xor; // The XOR output + reg clk; + + initial begin clk = 1'b1; #10 $sn; #160 $finish(0); end + always #50 clk = ~clk; + // The clock + + always @(posedge clk) out_xor = #1 (inp_xor[0] ^ inp_xor[1]); + // The actual operation + endmodule + diff --git a/ivtest/vpi/nulls1.c b/ivtest/vpi/nulls1.c new file mode 100644 index 000000000..4d666e43c --- /dev/null +++ b/ivtest/vpi/nulls1.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com) + * Michael Runyan (mrunyan at chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, +USA + */ + +#include "vpi_user.h" +#include + +PLI_INT32 +ValueChange(p_cb_data cb_data) +{ + static s_vpi_time get_time = { vpiSimTime, 0, 0, 0 }; + + (void)cb_data; /* Parameter is not used. */ + + vpi_get_time(NULL,&get_time); + vpi_printf("%6d: Value Change\n", (int)get_time.low); + return(0); +} + +#ifdef IVERILOG_V0_8 +PLI_INT32 CompileTF(char *user_data) +#else +PLI_INT32 CompileTF(PLI_BYTE8 *user_data) +#endif +{ + s_cb_data cb_data; + vpiHandle call_h=vpi_handle(vpiSysTfCall,NULL); + vpiHandle arg_i,arg_h; + + (void)user_data; /* Parameter is not used. */ + + // Get First Argument and Setup Value Change Callback + arg_i=vpi_iterate(vpiArgument,call_h); + arg_h=vpi_scan(arg_i); + vpi_free_object(arg_i); + + cb_data.reason = cbValueChange; + cb_data.cb_rtn = ValueChange; + cb_data.value = NULL; + cb_data.time = NULL; + cb_data.user_data = NULL; + cb_data.obj = arg_h; + vpi_register_cb(&cb_data); + + return(0); +} + +static void my_Register(void) +{ + s_vpi_systf_data tf_data; + + vpi_printf("Registering Callbacks\n"); + + // Register the $Verbench call + tf_data.type = vpiSysTask; + tf_data.user_data = 0; + tf_data.sizetf = NULL; + tf_data.tfname = "$vpi_call"; + tf_data.calltf = NULL; + tf_data.compiletf = CompileTF; + vpi_register_systf(&tf_data); + +} + +void (*vlog_startup_routines[]) (void) = { +my_Register, 0}; diff --git a/ivtest/vpi/nulls1.v b/ivtest/vpi/nulls1.v new file mode 100644 index 000000000..a823da5ae --- /dev/null +++ b/ivtest/vpi/nulls1.v @@ -0,0 +1,35 @@ +// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com) +// Michael Runyan (mrunyan at chiaro.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module test; + reg foo; + + initial begin + #0 foo=0; + forever #10 foo=~foo; + end + + initial begin + #101 $finish(0); + end + + initial + #1 $vpi_call(foo); + +endmodule diff --git a/ivtest/vpi/pokereg.cc b/ivtest/vpi/pokereg.cc new file mode 100644 index 000000000..17a43afa8 --- /dev/null +++ b/ivtest/vpi/pokereg.cc @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com) + * Michael Runyan (mrunyan at chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include +#include +#include +#include "vpi_user.h" + +static struct str_s { + int format; + const char *str; +} words[4] = { + {vpiBinStrVal, "x001x001"}, + {vpiOctStrVal, "0x2"}, + {vpiDecStrVal, "3"}, + {vpiHexStrVal, "x4"} +}; + +#ifdef IVERILOG_V0_8 +extern "C" PLI_INT32 RegPeek(char *) +#else +extern "C" PLI_INT32 RegPeek(PLI_BYTE8 *) +#endif +{ + vpiHandle mod_h, iterate, handle; + vpiHandle reg_h[5]; + s_vpi_value value; + int index; + + vpi_printf("RegPeek Callback\n"); + + // get top module handle + iterate = vpi_iterate(vpiModule, NULL); + if (iterate == NULL) return -1; + mod_h = vpi_scan(iterate); + vpi_free_object(iterate); + + // Get register + iterate = vpi_iterate(vpiReg, mod_h); + if (iterate == NULL) return -1; + for (index = 0; index < 5; index++) reg_h[index] = NULL; + while ((handle = vpi_scan(iterate))) { + if (!strcmp("r_peek_1", vpi_get_str(vpiName, handle))) { + reg_h[0] = handle; + } else if (!strcmp("r_peek_2", vpi_get_str(vpiName, handle))) { + reg_h[1] = handle; + } else if (!strcmp("r_peek_3", vpi_get_str(vpiName, handle))) { + reg_h[2] = handle; + } else if (!strcmp("r_peek_4", vpi_get_str(vpiName, handle))) { + reg_h[3] = handle; + } else if (!strcmp("r_peek_5", vpi_get_str(vpiName, handle))) { + reg_h[4] = handle; + } + } + + // Get value + for (index = 0; index < 5; index++) { + // Print out info + value.format=vpiBinStrVal; + vpi_get_value(reg_h[index], &value); + vpi_printf("%3d: 'b_%s,", index, value.value.str); + + value.format=vpiOctStrVal; + vpi_get_value(reg_h[index], &value); + vpi_printf(" 'o_%s,", value.value.str); + + value.format=vpiDecStrVal; + vpi_get_value(reg_h[index], &value); + vpi_printf(" 'd_%s,", value.value.str); + + value.format=vpiHexStrVal; + vpi_get_value(reg_h[index], &value); + vpi_printf(" 'h_%s\n", value.value.str); + } + + return 0; +} + +#ifdef IVERILOG_V0_8 +extern "C" PLI_INT32 RegPoke(char *) +#else +extern "C" PLI_INT32 RegPoke(PLI_BYTE8 *) +#endif +{ + vpiHandle mod_h, iterate, handle; + vpiHandle reg_h[5]; + s_vpi_value value; + int index; + + vpi_printf("RegPoke Callback\n"); + + // get top module handle + iterate = vpi_iterate(vpiModule, NULL); + if (iterate == NULL) return -1; + mod_h = vpi_scan(iterate); + vpi_free_object(iterate); + + // Get register + iterate = vpi_iterate(vpiReg, mod_h); + if (iterate == NULL) return -1; + for (index = 0; index < 5; index++) reg_h[index] = NULL; + while ((handle = vpi_scan(iterate))) { + if (!strcmp("r_poke_1", vpi_get_str(vpiName, handle))) { + reg_h[0] = handle; + } else if (!strcmp("r_poke_2", vpi_get_str(vpiName, handle))) { + reg_h[1] = handle; + } else if (!strcmp("r_poke_3", vpi_get_str(vpiName, handle))) { + reg_h[2] = handle; + } else if (!strcmp("r_poke_4", vpi_get_str(vpiName, handle))) { + reg_h[3] = handle; + } else if (!strcmp("r_poke_5", vpi_get_str(vpiName, handle))) { + reg_h[4] = handle; + } + } + + // Poke register using integer and strings + for (index = 0; index < 5; index++) { + if (index < 4) { + value.format=words[index].format; + value.value.str=strdup(words[index].str); + vpi_printf("%3d: %s\n", index, value.value.str); + } else { + value.format=vpiIntVal; + value.value.integer = 69; + vpi_printf("%3d: %d\n", index, (int)value.value.integer); + } + vpi_put_value(reg_h[index], &value, NULL, vpiNoDelay); + if (index < 4) free(value.value.str); + } + + return 0; +} + +extern "C" void +RegisterCallbacks(void) +{ + s_vpi_systf_data tf_data; + + vpi_printf("Registering Callbacks\n"); + + tf_data.type = vpiSysTask; + tf_data.tfname = "$regpoke"; + tf_data.calltf = RegPoke; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); + + tf_data.tfname = "$regpeek"; + tf_data.calltf = RegPeek; + vpi_register_systf(&tf_data); +} + +#ifdef __SUNPRO_CC +extern "C" +#endif +void (*vlog_startup_routines[])() = +{ + RegisterCallbacks, + 0 +}; diff --git a/ivtest/vpi/pokereg.v b/ivtest/vpi/pokereg.v new file mode 100644 index 000000000..3cc4f9534 --- /dev/null +++ b/ivtest/vpi/pokereg.v @@ -0,0 +1,64 @@ +// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com) +// Michael Runyan (mrunyan at chiaro.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module test; + + reg [7:0] r_poke_1, r_poke_2, r_poke_3, r_poke_4, r_poke_5; + reg [7:0] r_peek_1, r_peek_2, r_peek_3, r_peek_4, r_peek_5; + + task f_copy; + begin + // twizzle copy + r_peek_1 = r_poke_2; + r_peek_2 = r_poke_3; + r_peek_3 = r_poke_4; + r_peek_4 = r_poke_5; + r_peek_5 = r_poke_1; + end + endtask + + task f_dump; + integer i; + begin + $display("Verilog compare r_poke <=> r_peek"); + $display (" 'b_%b <=> 'b_%b%s", + r_poke_1, r_peek_5, r_poke_1 !== r_peek_5 ? " - ERROR" : ""); + $display (" 'b_%b <=> 'b_%b%s", + r_poke_2, r_peek_1, r_poke_2 !== r_peek_1 ? " - ERROR" : ""); + $display (" 'b_%b <=> 'b_%b%s", + r_poke_3, r_peek_2, r_poke_3 !== r_peek_2 ? " - ERROR" : ""); + $display (" 'b_%b <=> 'b_%b%s", + r_poke_4, r_peek_3, r_poke_4 !== r_peek_3 ? " - ERROR" : ""); + $display (" 'b_%b <=> 'b_%b%s", + r_poke_5, r_peek_4, r_poke_5 !== r_peek_4 ? " - ERROR" : ""); + end + endtask + + initial begin + #0; + $regpoke; + #10; + f_copy; + #10; + $regpeek; + #10; + f_dump; + end + +endmodule diff --git a/ivtest/vpi/pokevent.cc b/ivtest/vpi/pokevent.cc new file mode 100644 index 000000000..0e4cba053 --- /dev/null +++ b/ivtest/vpi/pokevent.cc @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com) + * Michael Runyan (mrunyan at chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test verifies named events can be peeked and poked. + */ + +#include +#include +#include +#include "vpi_user.h" + +extern "C" PLI_INT32 +CallbackPeek(s_cb_data *data) { + + static s_vpi_time zero_delay = { vpiNoDelay, 0, 0, 0 }; + + vpi_printf(" callback\n"); + + // Toggle poke event + vpiHandle poke_e = *(vpiHandle *)data->user_data; + vpi_put_value(poke_e, NULL, &zero_delay, vpiInertialDelay); + + return 0; +} + +static vpiHandle +FindPoke(const char *name) +{ + vpiHandle module, iterate, handle; + + // get top module handle + iterate = vpi_iterate(vpiModule, NULL); + if (iterate == NULL) return NULL; + module = vpi_scan(iterate); + vpi_free_object(iterate); + + // find named event + handle = NULL; + iterate = vpi_iterate(vpiNamedEvent, module); + if (iterate != NULL) { + while ((handle = vpi_scan(iterate))) { + if (!strcmp(name, vpi_get_str(vpiName, handle))) { + vpi_free_object(iterate); + break; + } + } + } + + return handle; +} + +static void +RegisterPeek(const char *name, vpiHandle poke) +{ + vpiHandle module, iterate, handle; + s_cb_data vc_cb_data; + static vpiHandle user_data = poke; + + // get top module handle + iterate = vpi_iterate(vpiModule, NULL); + if (iterate == NULL) return; + module = vpi_scan(iterate); + vpi_free_object(iterate); + + // find named event + handle = NULL; + iterate = vpi_iterate(vpiNamedEvent, module); + if (iterate != NULL) { + while ((handle = vpi_scan(iterate))) { + if (!strcmp(name, vpi_get_str(vpiName, handle))) { + vpi_free_object(iterate); + break; + } + } + } + + // Register callback + vc_cb_data.time = NULL; + vc_cb_data.value = NULL; + vc_cb_data.user_data = (char *)&user_data; + vc_cb_data.obj = handle; + vc_cb_data.reason = cbValueChange; + vc_cb_data.cb_rtn = CallbackPeek; + vpi_register_cb(&vc_cb_data); +} + +extern "C" PLI_INT32 +EndofCompile(s_cb_data * /*cb_data*/) +{ + RegisterPeek("e_Peek", FindPoke("e_Poke")); + return 0; +} + +extern "C" void my_Register(void) +{ + s_cb_data cb_data; + + vpi_printf("!!!C++: Registering Callbacks\n"); + + cb_data.time = NULL; + cb_data.value = NULL; + cb_data.user_data = (char *) NULL; + cb_data.obj = NULL; + cb_data.reason = cbEndOfCompile; + cb_data.cb_rtn = EndofCompile; + vpi_register_cb(&cb_data); +} + +#ifdef __SUNPRO_CC +extern "C" +#endif +void (*vlog_startup_routines[]) () = { + my_Register, + 0 +}; diff --git a/ivtest/vpi/pokevent.v b/ivtest/vpi/pokevent.v new file mode 100644 index 000000000..a9fce6859 --- /dev/null +++ b/ivtest/vpi/pokevent.v @@ -0,0 +1,20 @@ +module test; + + event e_Peek; + event e_Poke; + + initial begin + // $dumpvars; + #0; + ->e_Poke; + #51 $finish(0); + end + + always @(e_Poke) begin + $display("e_Poke received @ %0t", $time); + #10; + $display("e_Peek asserted @ %0t", $time); + ->e_Peek; + end + +endmodule diff --git a/ivtest/vpi/ports_params.c b/ivtest/vpi/ports_params.c new file mode 100644 index 000000000..dbb02c747 --- /dev/null +++ b/ivtest/vpi/ports_params.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2012 Andrew Stevens wackston@googlemail.com + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +#include +#include "vpi_user.h" + + +static void checkParams(void) +{ + vpiHandle mod_i = vpi_iterate(vpiModule, NULL) ; + assert( mod_i != NULL ); + vpiHandle module = vpi_scan(mod_i); + assert( module != NULL ); + vpi_free_object(mod_i); + + vpiHandle param_i = vpi_iterate(vpiParameter, module) ; + assert( param_i != NULL ); + vpiHandle parameter; + while ( (parameter=vpi_scan(param_i))!=NULL) + { + char *name =vpi_get_str(vpiName, parameter) ; + int type = vpi_get(vpiConstType, parameter) ; + printf( "PARAM NAME=%s type=%d ", name, type ); + s_vpi_value val ; + + switch(type) + { + case vpiDecConst: + case vpiBinaryConst: + case vpiOctConst: + case vpiHexConst: val.format = vpiIntVal ; + vpi_get_value(parameter, &val) ; + printf( "value=(INT)%d ", val.value.integer ); + break ; + + case vpiRealConst: val.format = vpiRealVal ; + vpi_get_value(parameter, &val) ; + printf( "value=(REAL)%g ", val.value.real ); + break ; + + case vpiStringConst: val.format = vpiStringVal ; + vpi_get_value(parameter, &val) ; + printf( "value=(STR)\"%s\" ", val.value.str ); + break; + default: printf( "value= " ); + break ; + } + + + int local =vpi_get(vpiLocalParam, parameter)!=0 ; + printf( "local=%s\n", local ? "yes" : "no" ); + } +} + + + +static void checkPorts(void) +{ + vpiHandle mod_i = vpi_iterate(vpiModule, NULL) ; + assert( mod_i != 0 ); + vpiHandle module = vpi_scan(mod_i); + assert( module != 0 ); + vpi_free_object(mod_i) ; + + + vpiHandle port_i = vpi_iterate(vpiPort, module) ; + vpiHandle port ; + while ( (port=vpi_scan(port_i))!=NULL) + { + char *portName = vpi_get_str(vpiName, port) ; + int portIndex = vpi_get(vpiPortIndex, port) ; + PLI_INT32 dir = vpi_get(vpiDirection, port) ; + PLI_INT32 size = vpi_get(vpiSize, port) ; + + printf( "PORT name=%s index=%d dir=%d size=%d\n", portName, portIndex, dir, size ); + } +} + + + +static PLI_INT32 checkPortsParams(struct t_cb_data*cb) +{ + (void)cb; /* Parameter is not used. */ + + checkParams(); + checkPorts(); + return 0; +} + + +static void setCallback(void) +{ + s_cb_data cb ; /* setup a callback for start of simulation */ + cb.reason = cbStartOfSimulation ; + cb.cb_rtn = checkPortsParams; + cb.user_data = "checkPortsParams" ; + cb.obj = NULL ; + cb.time = NULL ; + cb.value = NULL ; + + vpi_register_cb(&cb) ; +} + + +void (*vlog_startup_routines[]) (void) = { setCallback, 0}; diff --git a/ivtest/vpi/ports_params.v b/ivtest/vpi/ports_params.v new file mode 100644 index 000000000..9562e9137 --- /dev/null +++ b/ivtest/vpi/ports_params.v @@ -0,0 +1,75 @@ +`timescale 1ns/1ns + +`define DAC_MSB 7 +`define ADC_MSB 15 + +`define NSEC 1 +`define USEC (`NSEC*1000) +`define MSEC (`USEC*1000) + + +// TOPLEVEL TO STIMULATE +module toy_toplevel( + input wire [`ADC_MSB:0] V_load_adc, + input wire V_load_valid, + output reg pwm, + output reg [`DAC_MSB:0] V_src + ) ; + + parameter time STARTUP_DELAY = 2 * `MSEC; + + parameter real ADC_RANGE = 32.0; + parameter real ADC_OFFSET = -ADC_RANGE/2.0; + parameter real DAC_RANGE = 16.0; + parameter real DAC_OFFSET = -DAC_RANGE/2.0; + parameter real UPDATE_FREQ_MHZ = 1.0; + parameter time CLOCK_INTERVAL = `USEC / UPDATE_FREQ_MHZ; + + reg clk = 0; + reg ls_only = 0; + real V_load = 0.0; + + function real decode_value( input real base, input real range, input integer msb, input integer value ); + begin + decode_value = base + range * value / $itor(1<< (msb+1)); + end + endfunction + + function integer encode_value( input real base, input real range, input integer msb, input real value ); + begin + encode_value = (value -base) * $itor(1<< (msb+1)) / range; + end + endfunction + + always @( posedge(V_load_valid) ) + begin + V_load = decode_value( ADC_OFFSET, ADC_RANGE, `ADC_MSB, V_load_adc ); + end + + initial + begin + clk = 0; + ls_only = 0; + #( `USEC * 1 ); + # ( CLOCK_INTERVAL/4 ); + $finish(0); // Stop things for VPI unit test... + forever + begin + # ( CLOCK_INTERVAL/2 ); + clk <= ! clk; + end + + end + + always @clk + begin + ls_only= (V_load >2.5); + pwm <= clk | ls_only; + end + + initial + begin + V_src = encode_value( DAC_OFFSET, DAC_RANGE, `DAC_MSB, 7.2 ); + end + +endmodule diff --git a/ivtest/vpi/pr1693971.c b/ivtest/vpi/pr1693971.c new file mode 100644 index 000000000..320e2adc3 --- /dev/null +++ b/ivtest/vpi/pr1693971.c @@ -0,0 +1,209 @@ +/********************************************************************** + * $my_pow example -- PLI application using VPI routines + * + * C source to calculate the result of a number to the power of an + * exponent. The result is returned as a 32-bit integer. + * + * Usage: result = $my_pow(,); + * + * For the book, "The Verilog PLI Handbook" by Stuart Sutherland + * Copyright 1999 & 2001, Kluwer Academic Publishers, Norwell, MA, USA + * Contact: www.wkap.il + * Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA + * Contact: www.sutherland-hdl.com + *********************************************************************/ + +#define VPI_1995 0 /* set to non-zero for Verilog-1995 compatibility */ + +#include /* ANSI C standard library */ +#include /* ANSI C standard input/output library */ +#include /* ANSI C standard arguments library */ +#include "vpi_user.h" /* IEEE 1364 PLI VPI routine library */ + +#if VPI_1995 +#include "../vpi_1995_compat.h" /* kludge new Verilog-2001 routines */ +#endif + +/* prototypes of PLI application routine names */ +#ifdef IVERILOG_V0_8 +static PLI_INT32 PLIbook_PowSizetf(char *user_data); +static PLI_INT32 PLIbook_PowCalltf(char *user_data); +static PLI_INT32 PLIbook_PowCompiletf(char *user_data); +#else +static PLI_INT32 PLIbook_PowSizetf(PLI_BYTE8 *user_data); +static PLI_INT32 PLIbook_PowCalltf(PLI_BYTE8 *user_data); +static PLI_INT32 PLIbook_PowCompiletf(PLI_BYTE8 *user_data); +#endif +static PLI_INT32 PLIbook_PowStartOfSim(s_cb_data *callback_data); + +/********************************************************************** + * $my_pow Registration Data + * (add this function name to the vlog_startup_routines array) + *********************************************************************/ +void PLIbook_pow_register(void) +{ + s_vpi_systf_data tf_data; + s_cb_data cb_data_s; + vpiHandle callback_handle; + + tf_data.type = vpiSysFunc; + tf_data.sysfunctype = vpiSysFuncSized; + tf_data.tfname = "$my_pow"; + tf_data.calltf = PLIbook_PowCalltf; + tf_data.compiletf = PLIbook_PowCompiletf; + tf_data.sizetf = PLIbook_PowSizetf; + tf_data.user_data = NULL; + vpi_register_systf(&tf_data); + + cb_data_s.reason = cbStartOfSimulation; + cb_data_s.cb_rtn = PLIbook_PowStartOfSim; + cb_data_s.obj = NULL; + cb_data_s.time = NULL; + cb_data_s.value = NULL; + cb_data_s.user_data = NULL; + callback_handle = vpi_register_cb(&cb_data_s); + vpi_free_object(callback_handle); /* don't need callback handle */ +} + +/********************************************************************** + * Sizetf application + *********************************************************************/ +#ifdef IVERILOG_V0_8 +static PLI_INT32 PLIbook_PowSizetf(char *user_data) +#else +static PLI_INT32 PLIbook_PowSizetf(PLI_BYTE8 *user_data) +#endif +{ + (void)user_data; /* Parameter is not used. */ + //vpi_printf("\n$my_pow PLI sizetf function.\n\n"); + return(32); /* $my_pow returns 32-bit values */ +} + +/********************************************************************** + * compiletf application to verify valid systf args. + *********************************************************************/ +#ifdef IVERILOG_V0_8 +static PLI_INT32 PLIbook_PowCompiletf(char *user_data) +#else +static PLI_INT32 PLIbook_PowCompiletf(PLI_BYTE8 *user_data) +#endif +{ + vpiHandle systf_handle, arg_itr, arg_handle; + PLI_INT32 tfarg_type; + int err_flag = 0; + + (void)user_data; /* Parameter is not used. */ + + vpi_printf("\n$my_pow PLI compiletf function.\n\n"); + + do { /* group all tests, so can break out of group on error */ + systf_handle = vpi_handle(vpiSysTfCall, NULL); + arg_itr = vpi_iterate(vpiArgument, systf_handle); + if (arg_itr == NULL) { + vpi_printf("ERROR: $my_pow requires 2 arguments; has none\n"); + err_flag = 1; + break; + } + arg_handle = vpi_scan(arg_itr); + tfarg_type = vpi_get(vpiType, arg_handle); + if ( (tfarg_type != vpiReg) && + (tfarg_type != vpiIntegerVar) && + (tfarg_type != vpiConstant) ) { + vpi_printf("ERROR: $my_pow arg1 must be number, variable or net\n"); + err_flag = 1; + break; + } + arg_handle = vpi_scan(arg_itr); + if (arg_handle == NULL) { + vpi_printf("ERROR: $my_pow requires 2nd argument\n"); + err_flag = 1; + break; + } + tfarg_type = vpi_get(vpiType, arg_handle); + if ( (tfarg_type != vpiReg) && + (tfarg_type != vpiIntegerVar) && + (tfarg_type != vpiConstant) ) { + vpi_printf("ERROR: $my_pow arg2 must be number, variable or net\n"); + err_flag = 1; + break; + } + if (vpi_scan(arg_itr) != NULL) { + vpi_printf("ERROR: $my_pow requires 2 arguments; has too many\n"); + vpi_free_object(arg_itr); + err_flag = 1; + break; + } + } while (0 == 1); /* end of test group; only executed once */ + + if (err_flag) { + vpi_control(vpiFinish, 1); /* abort simulation */ + } + return(0); +} + +/********************************************************************** + * calltf to calculate base to power of exponent and return result. + *********************************************************************/ +#include +#ifdef IVERILOG_V0_8 +static PLI_INT32 PLIbook_PowCalltf(char *user_data) +#else +static PLI_INT32 PLIbook_PowCalltf(PLI_BYTE8 *user_data) +#endif +{ + s_vpi_value value_s; + vpiHandle systf_handle, arg_itr, arg_handle; + PLI_INT32 base, expo; + double result; + + (void)user_data; /* Parameter is not used. */ + + //vpi_printf("\n$my_pow PLI calltf function.\n\n"); + + systf_handle = vpi_handle(vpiSysTfCall, NULL); + arg_itr = vpi_iterate(vpiArgument, systf_handle); + if (arg_itr == NULL) { + vpi_printf("ERROR: $my_pow failed to obtain systf arg handles\n"); + return(0); + } + + /* read base from systf arg 1 (compiletf has already verified) */ + arg_handle = vpi_scan(arg_itr); + value_s.format = vpiIntVal; + vpi_get_value(arg_handle, &value_s); + base = value_s.value.integer; + + /* read exponent from systf arg 2 (compiletf has already verified) */ + arg_handle = vpi_scan(arg_itr); + vpi_free_object(arg_itr); /* not calling scan until returns null */ + vpi_get_value(arg_handle, &value_s); + expo = value_s.value.integer; + + /* calculate result of base to power of exponent */ + result = pow( (double)base, (double)expo ); + + /* write result to simulation as return value $my_pow */ + value_s.value.integer = (PLI_INT32)result; + vpi_put_value(systf_handle, &value_s, NULL, vpiNoDelay); + return(0); +} + +/********************************************************************** + * Start-of-simulation application + *********************************************************************/ +static PLI_INT32 PLIbook_PowStartOfSim(s_cb_data *callback_data) +{ + (void)callback_data; /* Parameter is not used. */ + vpi_printf("\n$my_pow StartOfSim callback.\n\n"); + return(0); +} +/*********************************************************************/ + + +void (*vlog_startup_routines[])(void) = +{ + /*** add user entries here ***/ + PLIbook_pow_register, + //PLIbook_test_user_data_register, + 0 /*** final entry must be 0 ***/ +}; diff --git a/ivtest/vpi/pr1693971.v b/ivtest/vpi/pr1693971.v new file mode 100644 index 000000000..b3f2915ac --- /dev/null +++ b/ivtest/vpi/pr1693971.v @@ -0,0 +1,41 @@ +/********************************************************************** + * $my_pow example -- Verilog HDL test bench. + * + * Verilog test bench to test the $my_pow PLI application. + * + * For the book, "The Verilog PLI Handbook" by Stuart Sutherland + * Copyright 1999 & 2001, Kluwer Academic Publishers, Norwell, MA, USA + * Contact: www.wkap.il + * Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA + * Contact: www.sutherland-hdl.com + *********************************************************************/ +`timescale 1ns / 1ns +module test; + reg [32:0] result; + reg a, b; + + buf i1 (c,a); + initial + begin + $display("Start simulation pow_test.v"); + a = 1; + b = 0; + /* Test $my_pow with invalid arguments */ + /* These invalid calls will need to be commented out to use */ + /* the valid calls to $my_pow in simulation */ +// #1 result = $my_pow; +// #1 result = $my_pow(); +// #1 result = $my_pow(1); +// #1 result = $my_pow(2,i1); +// #1 result = $my_pow(1,2,3); + + /* Test $my_pow with valid values */ + #1 $display("$my_pow(2,3) returns %d", $my_pow(2,3)); + #1 result = $my_pow(a,b); + #1 $display("$my_pow(a,b) returns %d (a=%d b=%d)", result, a, b); +// #1 $stop; + #1 $finish(0); + end + +endmodule +/*********************************************************************/ diff --git a/ivtest/vpi/pr2048463.c b/ivtest/vpi/pr2048463.c new file mode 100644 index 000000000..da397165b --- /dev/null +++ b/ivtest/vpi/pr2048463.c @@ -0,0 +1,202 @@ +/********************************************************************** + * $my_monitor example -- PLI application using VPI routines + * + * C source to place value change callbacks on all nets in a module + * instance, and print the simulation time and new value whenever + * any net changes value. + * + * Usage: $my_monitor(); + * + * For the book, "The Verilog PLI Handbook" by Stuart Sutherland + * Copyright 1999 & 2001, Kluwer Academic Publishers, Norwell, MA, USA + * Contact: www.wkap.il + * Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA + * Contact: www.sutherland-hdl.com + *********************************************************************/ + + +#include /* ANSI C standard library */ +#include /* ANSI C standard input/output library */ +#include /* ANSI C standard arguments library */ +#include +#include /* IEEE 1364 PLI VPI routine library */ + + + + +/* prototypes of routines in this PLI application */ +PLI_INT32 PLIbook_MyMonitor_calltf(PLI_BYTE8 *user_data); +PLI_INT32 PLIbook_MyMonitor_compiletf(PLI_BYTE8 *user_data); +PLI_INT32 PLIbook_MyMonitor_callback(p_cb_data cb_data_p); + + +/* To make this memory clean we need to keep a list of the allocated + * names so we can free them at EOS. */ +static char** name_list = 0; +static unsigned name_count = 0; + +static PLI_INT32 sys_end_of_simulation(p_cb_data cb_data) +{ + unsigned idx; + + (void)cb_data; /* Parameter is not used. */ + + for (idx = 0; idx < name_count; idx += 1) { + free(name_list[idx]); + } + free(name_list); + name_list = 0; + name_count = 0; + + return 0; +} + +/********************************************************************** + * VPI Registration Data + *********************************************************************/ +void PLIbook_MyMonitor_register(void) +{ + s_vpi_systf_data tf_data; + s_cb_data cb_data; + + tf_data.type = vpiSysTask; + tf_data.sysfunctype = 0; + tf_data.tfname = "$my_monitor"; + tf_data.calltf = PLIbook_MyMonitor_calltf; + tf_data.compiletf = PLIbook_MyMonitor_compiletf; + tf_data.sizetf = NULL; + tf_data.user_data = NULL; + vpi_register_systf(&tf_data); + + cb_data.reason = cbEndOfSimulation; + cb_data.time = 0; + cb_data.cb_rtn = sys_end_of_simulation; + cb_data.user_data = "system"; + vpi_register_cb(&cb_data); +} + + +void (*vlog_startup_routines[])(void) = { + PLIbook_MyMonitor_register, + 0 +}; + +/* dummy +loadvpi= boostrap routine - mimics old style exec all routines */ +/* in standard PLI vlog_startup_routines table */ +void vpi_compat_bootstrap(void) +{ + int i; + + for (i = 0;; i++) + { + if (vlog_startup_routines[i] == NULL) break; + vlog_startup_routines[i](); + } +} + + +/********************************************************************** + * compiletf application + *********************************************************************/ +PLI_INT32 PLIbook_MyMonitor_compiletf(PLI_BYTE8 *user_data) +{ + vpiHandle systf_handle, arg_iterator, arg_handle; + PLI_INT32 tfarg_type; + + (void)user_data; /* Parameter is not used. */ + + /* obtain a handle to the system task instance */ + systf_handle = vpi_handle(vpiSysTfCall, NULL); + + /* obtain handles to system task arguments */ + arg_iterator = vpi_iterate(vpiArgument, systf_handle); + if (arg_iterator == NULL) { + vpi_printf("ERROR: $my_monitor requires 1 argument\n"); + vpi_control(vpiFinish, 1); /* abort simulation */ + return(0); + } + + /* check the type of object in system task arguments */ + arg_handle = vpi_scan(arg_iterator); + tfarg_type = vpi_get(vpiType, arg_handle); + if (tfarg_type != vpiModule) { + vpi_printf("ERROR: $my_monitor arg1 must be module instance\n"); + vpi_free_object(arg_iterator); /* free iterator memory */ + vpi_control(vpiFinish, 1); /* abort simulation */ + return(0); + } + + /* check that there is only 1 system task argument */ + arg_handle = vpi_scan(arg_iterator); + if (arg_handle != NULL) { + vpi_printf("ERROR: $my_monitor can only have 1 argument\n"); + vpi_free_object(arg_iterator); /* free iterator memory */ + vpi_control(vpiFinish, 1); /* abort simulation */ + return(0); + } + return(0); /* no syntax errors detected */ +} + +/********************************************************************** + * calltf routine + *********************************************************************/ +PLI_INT32 PLIbook_MyMonitor_calltf(PLI_BYTE8 *user_data) +{ + vpiHandle systf_h, arg_itr, mod_h, net_itr, net_h, cb_h; + s_vpi_time time_s; + s_vpi_value value_s; + s_cb_data cb_data_s; + PLI_BYTE8 *net_name_temp, *net_name_keep; + + (void)user_data; /* Parameter is not used. */ + + /* setup value change callback options */ + time_s.type = vpiScaledRealTime; + value_s.format = vpiBinStrVal; + + cb_data_s.reason = cbValueChange; + cb_data_s.cb_rtn = PLIbook_MyMonitor_callback; + cb_data_s.time = &time_s; + cb_data_s.value = &value_s; + + /* obtain a handle to the system task instance */ + systf_h = vpi_handle(vpiSysTfCall, NULL); + + /* obtain handle to system task argument */ + /* compiletf has already verified only 1 arg with correct type */ + arg_itr = vpi_iterate(vpiArgument, systf_h); + mod_h = vpi_scan(arg_itr); + vpi_free_object(arg_itr); /* free iterator--did not scan to null */ + + /* add value change callback for each net in module named in tfarg */ + vpi_printf("\nAdding monitors to all nets in module %s:\n\n", + vpi_get_str(vpiDefName, mod_h)); + + net_itr = vpi_iterate(vpiNet, mod_h); + while ((net_h = vpi_scan(net_itr)) != NULL) { + net_name_temp = vpi_get_str(vpiFullName, net_h); + net_name_keep = malloc(strlen((char *)net_name_temp)+1); + strcpy((char *)net_name_keep, (char *)net_name_temp); + cb_data_s.obj = net_h; + cb_data_s.user_data = net_name_keep; + name_count += 1; + name_list = (char **)realloc(name_list, name_count*sizeof(char **)); + name_list[name_count-1] = net_name_keep; + cb_h = vpi_register_cb(&cb_data_s); + vpi_free_object(cb_h); /* don't need callback handle */ + } + return(0); +} + +/********************************************************************** + * Value change callback application + *********************************************************************/ +PLI_INT32 PLIbook_MyMonitor_callback(p_cb_data cb_data_p) +{ + vpi_printf("At time %0.2f", cb_data_p->time->real); + vpi_printf(":\t %s", cb_data_p->user_data); + vpi_printf(" = %s\n", cb_data_p->value->value.str); + return(0); +} + +/*********************************************************************/ diff --git a/ivtest/vpi/pr2048463.v b/ivtest/vpi/pr2048463.v new file mode 100644 index 000000000..bd3c442d4 --- /dev/null +++ b/ivtest/vpi/pr2048463.v @@ -0,0 +1,61 @@ +/********************************************************************** + * $my_monitor example -- Verilog HDL test bench. + * + * Verilog test bench to test the $my_monitor PLI application. + * + * For the book, "The Verilog PLI Handbook" by Stuart Sutherland + * Copyright 1999 & 2001, Kluwer Academic Publishers, Norwell, MA, USA + * Contact: www.wkap.il + * Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA + * Contact: www.sutherland-hdl.com + *********************************************************************/ +`timescale 1ns / 1ns +module test; + reg a, b, ci, clk; + wire sum, co; + + addbit i1 (a, b, ci, sum, co); + + initial + $my_monitor(i1); + + initial + begin + #0 a = 0; + #0 b = 0; + #0 ci = 0; + #10 a = 1; + #10 a = 0; + #10 b = 1; + #10 a = 1; + #10 $finish(0); + end + +endmodule + +/*** A gate level 1 bit adder model ***/ +`timescale 1ns / 1ns +module addbit (a, b, ci, sum, co); + input a, b, ci; + output sum, co; + + wire a, b, ci, sum, co, + n1, n2, n3; + +/* + assign n1 = a ^ b; + assign sum = n1 ^ ci; + assign n2 = a & b; + assign n3 = n1 & ci; + assign co = n2 | n3; +*/ + // Gate delays are used to ensure the signal changes occur in a + // defined order. + xor #1 (n1, a, b); + and #2 (n2, a, b); + and #3 (n3, n1, ci); + xor #4 (sum, n1, ci); + or #4 (co, n2, n3); + +endmodule +/*********************************************************************/ diff --git a/ivtest/vpi/pr2314742.c b/ivtest/vpi/pr2314742.c new file mode 100644 index 000000000..cd8176fba --- /dev/null +++ b/ivtest/vpi/pr2314742.c @@ -0,0 +1,158 @@ +#include +#include +#include +#include + +/* + * This file exercises an error + */ + +static int chkvpierr(void) +{ + s_vpi_error_info info; + int level; + + if ((level = vpi_chk_error(&info)) != 0) { + fprintf(stderr, "+++ VPI ERROR +++ level %d\n", level); + fprintf(stderr, "+++ MESS: %s\n", info.message); + fprintf(stderr, "+++ PROD: %s\n", info.product); + fprintf(stderr, "+++ CODE: %s\n", info.code); + fprintf(stderr, "+++ FILE: %s\n", info.file); + fprintf(stderr, "+++\n"); + } + return level; +} + +#ifdef IVERILOG_V0_8 +static PLI_INT32 xxx_compiletf(char *user_data) +#else +static PLI_INT32 xxx_compiletf(PLI_BYTE8 *user_data) +#endif +{ + (void)user_data; /* Parameter is not used. */ + return 0; +} + +char charbuf[100]; + +#ifdef IVERILOG_V0_8 +static PLI_INT32 xxx_calltf(char *user_data) +#else +static PLI_INT32 xxx_calltf(PLI_BYTE8 *user_data) +#endif +{ + vpiHandle systf_h; + s_vpi_value vpival; /* get/set register values */ + s_vpi_time t; + vpiHandle arg_iterator; + int i; + vpiHandle argi[100]; + + (void)user_data; /* Parameter is not used. */ + + /* Get handle to this instance, look up our workarea */ + systf_h = vpi_handle(vpiSysTfCall, NULL); + chkvpierr(); + + arg_iterator = vpi_iterate(vpiArgument, systf_h); + chkvpierr(); + i = 0; + + if (arg_iterator == NULL) { + fprintf(stderr, "ERROR: missing argument list to $example(...)"); + } + + /* Copy args pointers into argi array */ + while ((argi[i] = vpi_scan(arg_iterator)) != NULL) { + chkvpierr(); + i++; + } + /* iterator is exhausted, no need to free */ + + /* Fill in the time struct */ + t.type = vpiScaledRealTime; + t.high = 0; + t.low = 0; + t.real = 10.0; + + /* Fill in the value struct */ + vpival.format = vpiBinStrVal; + vpival.value.str = charbuf; + + /* + * This is where the real work happens. We are called in an intial + * block and we schedule three "set-values" at times 10, 20 and 30 + * to args 0, 1 and 2. The charbuf gets shared among the three + * calls, even though it shouldn't and the values are not distinct. + */ + + /* Write this value to argi[0] at time 10.0 */ + strcpy(charbuf, "01010101"); + vpi_put_value(argi[0], &vpival, &t, vpiTransportDelay); + + /* Write this value to argi[1] at time 20.0 */ + strcpy(charbuf, "x1x1x1x1"); + t.real = 20.0; + vpi_put_value(argi[1], &vpival, &t, vpiTransportDelay); + + /* Write this value to argi[2] at time 30.0 */ + strcpy(charbuf, "0xz101xz"); + t.real = 30.0; + vpi_put_value(argi[2], &vpival, &t, vpiTransportDelay); + + return 0; +} + + +static void xxx_register(void) +{ + s_vpi_systf_data tfdata; + + vpi_printf("+++ in XXX_REGISTER\n"); + + tfdata.type = vpiSysFunc; + + /* + * TOM: sysfunctype field seems to be problematic for different simulators! + * some simulators simply don't register callback if subtype missing. + * + * Icarus - doesn't implement vpiSizedFunc, so use vpiIntFunct. + * CVER - use vpiIntFunc + * MTI - use vpiSizedFunc or vpiIntFunc. + * XL/NC - doesn't matter + * VCS - doesn't matter + * + */ + + tfdata.sysfunctype = vpiIntFunc; + /* tfdata.sysfunctype = vpiSizedFunc; */ + + tfdata.tfname = "$example"; + tfdata.calltf = xxx_calltf; + tfdata.compiletf = xxx_compiletf; + /* tfdata.sizetf = xxx_sizetf; */ + tfdata.sizetf = 0; + tfdata.user_data = 0; + + vpi_register_systf(&tfdata); + chkvpierr(); +} + + + + +static void xxx_startup(void) +{ + vpi_printf("*** Registering XXX PLI functions.\n"); + xxx_register(); +} + +/** + * + * + **/ + +void (*vlog_startup_routines[])(void) = { + xxx_startup, + 0 +}; diff --git a/ivtest/vpi/pr2314742.v b/ivtest/vpi/pr2314742.v new file mode 100644 index 000000000..1dc9591e0 --- /dev/null +++ b/ivtest/vpi/pr2314742.v @@ -0,0 +1,29 @@ +module top; + + reg [7:0] a; + reg [7:0] b; + reg [7:0] c; + + integer retcode; + + + initial + begin + #0; // avoid T0 race + a = 0; + b = 0; + c = 0; + /* Use VPI to set values on these registers */ + retcode = $example(a, b, c); + end + + always @(a) + $display("%t The value of A is: %b", $time, a); + + always @(b) + $display("%t The value of B is: %b", $time, b); + + always @(c) + $display("%t The value of C is: %b", $time, c); + +endmodule // top diff --git a/ivtest/vpi/pr2966059.c b/ivtest/vpi/pr2966059.c new file mode 100644 index 000000000..019d8337c --- /dev/null +++ b/ivtest/vpi/pr2966059.c @@ -0,0 +1,53 @@ +#include "vpi_user.h" + +#ifdef IVERILOG_V0_8 +static PLI_INT32 number_compiletf(char *x) +#else +static PLI_INT32 number_compiletf(PLI_BYTE8 *x) +#endif +{ + vpiHandle callh = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, callh); + vpiHandle arg; + char *name; + + s_vpi_value var; + + (void)x; /* Parameter is not used. */ + + if (argv == 0) { + vpi_printf("ERROR: missing required numeric argument.\n"), + vpi_control(vpiFinish, 1); + return 0; + } + arg = vpi_scan(argv); + + /* Check to see what vpi_get_value does during compiletf. */ + name = vpi_get_str(vpiName, arg); + vpi_printf("vpi_get_value (%s):\n", name ? name : ""); + var.format = vpiObjTypeVal; + vpi_get_value(arg, &var); + vpi_printf(" format = %d\n", (int) var.format); + var.format = vpiDecStrVal; + vpi_get_value(arg, &var); + vpi_printf(" value = %s\n", var.value.str); + + vpi_free_object(argv); + return 0; +} + +static void local_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$check_number"; + tf_data.calltf = 0; + tf_data.compiletf = number_compiletf; + tf_data.sizetf = 0; + tf_data.user_data = 0; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[]) (void) = { +local_register, 0}; diff --git a/ivtest/vpi/pr2966059.v b/ivtest/vpi/pr2966059.v new file mode 100644 index 000000000..13652b660 --- /dev/null +++ b/ivtest/vpi/pr2966059.v @@ -0,0 +1,31 @@ +module top; + parameter ip = 1; + parameter rp = 2.0; + parameter sp = "\003"; + + real rlval; + wire real wreal; + reg [3:0] rval; + wire [3:0] wval; + assign wval = 2; + + initial begin + rval = 4'b1001; + rlval = 2.0; + $check_number(1); + $check_number(ip); + $check_number(2.0); + $check_number(rp); + $check_number("\003"); + $check_number(sp); + + $check_number(rlval); + $check_number(rlval+1); + $check_number(wreal); + $check_number(wreal+1); + $check_number(rval); + $check_number(rval+1); + $check_number(wval); + $check_number(wval+1); + end +endmodule diff --git a/ivtest/vpi/pr2971220.c b/ivtest/vpi/pr2971220.c new file mode 100644 index 000000000..fcbc0ce5f --- /dev/null +++ b/ivtest/vpi/pr2971220.c @@ -0,0 +1,245 @@ +#include "string.h" +#include "vpi_user.h" + +/* + * Not all systems support passing a system task/function call handle + * to vpi_get_systf_info(). All should support vpiUserSystf. You can + * only get the vpiUserSystf handle when vpiUserDefn is 1 (true). + */ + +/* + * Set the following when compiling if the call handle is not supported: + * SYSTF_INFO_CALLH_NOT_SUPPORTED + */ + +static vpiHandle registered_task_as; +static vpiHandle registered_func_as; + +/* These tasks/functions do not take any arguments. */ +static PLI_INT32 sys_compiletf(PLI_BYTE8 *name) +{ + vpiHandle callh = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, callh); + + if (argv) { + vpi_printf("ERROR: %s:%d: ", vpi_get_str(vpiFile, callh), + (int)vpi_get(vpiLineNo, callh)); + vpi_printf("%s does not take any arguments.\n", name); + vpi_free_object(argv); + vpi_control(vpiFinish, 1); + } + + return 0; +} + +/* Helper function to print the function type as a string value. */ +static const char *func_type(PLI_INT32 type) +{ + char *res = 0; + switch (type) { + case vpiIntFunc: + res = "vpiIntFunc"; + break; + case vpiRealFunc: + res = "vpiRealFunc"; + break; + case vpiTimeFunc: + res = "vpiTimeFunc"; + break; + case vpiSizedFunc: + res = "vpiSizedFunc"; + break; + case vpiSizedSignedFunc: + res = "vpiSizedSignedFunc"; + break; + default: + res = ""; + break; + } + return res; +} + +/* The calltf routine for the task check. */ +static PLI_INT32 sys_check_sys_task_calltf(PLI_BYTE8 *name) +{ + vpiHandle callh = vpi_handle(vpiSysTfCall, 0); + PLI_INT32 res; + s_vpi_systf_data tf_data; + vpiHandle iter; + + /* Check the stashed handle. */ + vpi_get_systf_info(registered_task_as, &tf_data); + vpi_printf("registered as: %s - %s\n", + vpi_get_str(vpiType, registered_task_as), + tf_data.tfname); + + /* Check to see if vpiUserDefn is set correctly. */ + res = vpi_get(vpiUserDefn, callh); + vpi_printf(" vpiUserDefn: is "); + if (res != 1) { + vpi_printf("undefined (%d)!\n", (int)res); + } else { + vpi_printf("defined.\n"); + + /* Check vpi_get_systf_info (just check the name). */ + vpi_get_systf_info(vpi_handle(vpiUserSystf, callh), &tf_data); + vpi_printf(" vpi_get_systf_info: "); + if (strcmp(tf_data.tfname, name)) { + vpi_printf("failed.\n"); + } else { + vpi_printf("passed.\n"); + } +#ifdef SYSTF_INFO_CALLH_NOT_SUPPORTED + vpi_printf(" vpi_get_systf_info (callh): not supported.\n"); +#else + /* This is not supported by all simulators. */ + vpi_get_systf_info(callh, &tf_data); + vpi_printf(" vpi_get_systf_info (callh): "); + if (strcmp(tf_data.tfname, name)) { + vpi_printf("failed.\n"); + } else { + vpi_printf("passed.\n"); + } +#endif + } + + /* Look for all the user defined system tasks/functions. */ + vpi_printf("Looking for all user defined system tasks/functions:\n"); + iter = vpi_iterate(vpiUserSystf, 0); + if (iter) { + vpiHandle val; + while ((val = vpi_scan(iter))) { + vpi_get_systf_info(val, &tf_data); + vpi_printf(" Found "); + if (tf_data.type == vpiSysTask) vpi_printf("task"); + else vpi_printf("function (%s)", + func_type(tf_data.sysfunctype)); + vpi_printf(" %s - %s", + vpi_get_str(vpiType, val), + tf_data.tfname); + if (vpi_compare_objects(val, registered_task_as)) { + vpi_printf(" *****> caller"); + } + vpi_printf(".\n"); + } + vpi_printf("Done.\n"); + } else { + vpi_printf(" No user defined system tasks/functions found!\n"); + } + + return 0; +} + +/* The calltf routine for the function check. */ +static PLI_INT32 sys_check_sys_func_calltf(PLI_BYTE8 *name) +{ + vpiHandle callh = vpi_handle(vpiSysTfCall, 0); + PLI_INT32 res; + s_vpi_systf_data tf_data; + + /* Check the stashed handle. */ + vpi_get_systf_info(registered_func_as, &tf_data); + vpi_printf("registered as: %s - %s\n", + vpi_get_str(vpiType, registered_func_as), + tf_data.tfname); + + /* Check to see if vpiUserDefn is set correctly. */ + res = vpi_get(vpiUserDefn, callh); + vpi_printf(" vpiUserDefn: "); + if (res != 1) { + vpi_printf("is undefined (%d)!\n", (int)res); + } else { + vpi_printf("is defined.\n"); + + /* Check vpi_get_systf_info (just check the name). */ + vpi_get_systf_info(vpi_handle(vpiUserSystf, callh), &tf_data); + vpi_printf(" vpi_get_systf_info: "); + if (strcmp(tf_data.tfname, name)) { + vpi_printf("failed.\n"); + } else { + vpi_printf("passed.\n"); + } +#ifdef SYSTF_INFO_CALLH_NOT_SUPPORTED + vpi_printf(" vpi_get_systf_info (callh): not supported.\n"); +#else + /* This is not supported by all simulators. */ + vpi_get_systf_info(callh, &tf_data); + vpi_printf(" vpi_get_systf_info (callh): "); + if (strcmp(tf_data.tfname, name)) { + vpi_printf("failed.\n"); + } else { + vpi_printf("passed.\n"); + } +#endif + } + + /* We would normally put a value for a function, but since we're + * not testing that with this code we'll just use the default + * value (0). */ + return 0; +} + +/* A simple task to add a few more definitions to the vpiUserSystf list. */ +static PLI_INT32 sys_hello_calltf(PLI_BYTE8 *name) +{ + vpiHandle callh = vpi_handle(vpiSysTfCall, 0); + vpi_printf("Hello from %s at %s:%d.\n", name, + vpi_get_str(vpiFile, callh), + (int)vpi_get(vpiLineNo, callh)); + return 0; +} + +static void register_check_systf(void) +{ + vpiHandle res; + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.calltf = sys_check_sys_task_calltf; + tf_data.compiletf = sys_compiletf; + tf_data.sizetf = 0; + tf_data.tfname = "$check_sys_task"; + tf_data.user_data = "$check_sys_task";; + registered_task_as = vpi_register_systf(&tf_data); + + tf_data.type = vpiSysFunc; + tf_data.sysfunctype = vpiSysFuncInt; + tf_data.calltf = sys_check_sys_func_calltf; + tf_data.compiletf = sys_compiletf; + tf_data.sizetf = 0; + tf_data.tfname = "$check_sys_func"; + tf_data.user_data = "$check_sys_func";; + registered_func_as = vpi_register_systf(&tf_data); + + tf_data.type = vpiSysTask; + tf_data.calltf = sys_hello_calltf; + tf_data.compiletf = sys_compiletf; + tf_data.sizetf = 0; + tf_data.tfname = "$hello"; + tf_data.user_data = "$hello";; + res = vpi_register_systf(&tf_data); + /* Icarus does not need this, but it should not be an error either. */ + vpi_free_object(res); + + +// Does this work on all simulators? I would expect vpi_printf() to be OK, +// but vpi_get_systf_info() could be suspect. + vpi_get_systf_info(registered_task_as, &tf_data); + vpi_printf("--> registered task as: %s.\n", tf_data.tfname); + vpi_get_systf_info(registered_func_as, &tf_data); + vpi_printf("--> registered func as: %s.\n", tf_data.tfname); +} + +void (*vlog_startup_routines[])(void) = { + register_check_systf, + 0 +}; + +/* This is needed by other simulators. */ +void vpi_bootstrap(void) +{ + int i; + for (i = 0; vlog_startup_routines[i]; i += 1) { + vlog_startup_routines[i](); + } +} diff --git a/ivtest/vpi/pr2971220.v b/ivtest/vpi/pr2971220.v new file mode 100644 index 000000000..a367ba33c --- /dev/null +++ b/ivtest/vpi/pr2971220.v @@ -0,0 +1,9 @@ +module top; + integer res; + initial begin + $hello; + $check_sys_task; + res = $check_sys_func; + $hello; + end +endmodule diff --git a/ivtest/vpi/pr521.c b/ivtest/vpi/pr521.c new file mode 100644 index 000000000..78747c52c --- /dev/null +++ b/ivtest/vpi/pr521.c @@ -0,0 +1,37 @@ +#include +#include + +char *veriuser_version_str = "Test PLI v0.1 "; + +static int pli_test(int ud, int reason) +{ + int a; + + (void)ud; /* Parameter is not used. */ + (void)reason; /* Parameter is not used. */ + + a = tf_getp(1); + printf ("PLI Parameter received 0x%x\n",a); + return 0; +} + +static int return_32(int ud, int reason) +{ + (void)ud; /* Parameter is not used. */ + (void)reason; /* Parameter is not used. */ + + return (32); +} + + +s_tfcell veriusertfs[] = { + {userfunction, 0, 0, return_32, pli_test, 0, "$pli_test", 1, 0, 0, {0} }, + /* all entry must be entered before this line */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0} } /* this must be the last entry */ +}; + +static void veriusertfs_register(void) { + veriusertfs_register_table(veriusertfs); +} + +void (*vlog_startup_routines[])(void) = { &veriusertfs_register, 0 }; diff --git a/ivtest/vpi/pr521.v b/ivtest/vpi/pr521.v new file mode 100644 index 000000000..c4a7bf152 --- /dev/null +++ b/ivtest/vpi/pr521.v @@ -0,0 +1,17 @@ +module pli_test; + +wire [15:0] a = 16'h4321; +wire [ 7:0] b = a[15:8]; + +integer rc; + +initial + begin + #1 /* Allow the continuous assignments above to settle. */ ; + $display("Passing parameter to PLI routine: 0x%x",a[15:8]); + rc = $pli_test(a[15:8]); + $display("Passing parameter to PLI routine: 0x%x",b); + rc = $pli_test(b); + end + +endmodule diff --git a/ivtest/vpi/pr686.c b/ivtest/vpi/pr686.c new file mode 100644 index 000000000..a3e62b73f --- /dev/null +++ b/ivtest/vpi/pr686.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +# include "vpi_user.h" +# include + +static PLI_INT32 next_sim_time_callback(struct t_cb_data*cb) +{ + vpiHandle obj = (vpiHandle)cb->user_data; + s_vpi_value val; + s_vpi_time tim; + + val.format = vpiIntVal; + vpi_get_value(obj, &val); + + tim.type = vpiSimTime; + vpi_get_time(obj, &tim); + + vpi_printf("Callback time=%d %s=%d\n", (int)tim.low, + vpi_get_str(vpiName, obj), + (int)val.value.integer); + return 0; +} + +#ifdef IVERILOG_V0_8 +static PLI_INT32 test_next_compiletf(char *name) +#else +static PLI_INT32 test_next_compiletf(PLI_BYTE8 *name) +#endif +{ + (void)name; /* Parameter is not used. */ + return 0; +} + +#ifdef IVERILOG_V0_8 +static PLI_INT32 test_next_calltf(char *name) +#else +static PLI_INT32 test_next_calltf(PLI_BYTE8 *name) +#endif +{ + vpiHandle sys, argv, value; + + (void)name; /* Parameter is not used. */ + + sys = vpi_handle(vpiSysTfCall, 0); + assert(sys); + + argv = vpi_iterate(vpiArgument, sys); + assert(argv); + + for (value = vpi_scan(argv) ; value ; value = vpi_scan(argv)) { + s_cb_data cb; + cb.reason = cbNextSimTime; + cb.cb_rtn = next_sim_time_callback; + cb.user_data = (char*)value; + vpi_register_cb(&cb); + } + + return 0; +} + +static void register_functions(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$test_next_sim_time"; + tf_data.calltf = test_next_calltf; + tf_data.compiletf = test_next_compiletf; + tf_data.sizetf = 0; + tf_data.user_data = ""; + + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[])(void) = { + register_functions, + 0 +}; diff --git a/ivtest/vpi/pr686.v b/ivtest/vpi/pr686.v new file mode 100644 index 000000000..fe1f834ff --- /dev/null +++ b/ivtest/vpi/pr686.v @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +module main; + + reg [3:0] foo; + + initial begin + foo = 0; + foo <= 1; + // This will display 1 at time=1 + $test_next_sim_time(foo); + $strobe("foo should be 0: %d", foo); + #1 foo <= #4 2; + $strobe("foo should be 1: %d", foo); + $test_next_sim_time(foo); + #5 $display("foo is finally %d", foo); + end + +endmodule // main diff --git a/ivtest/vpi/pr723.c b/ivtest/vpi/pr723.c new file mode 100644 index 000000000..239f63b35 --- /dev/null +++ b/ivtest/vpi/pr723.c @@ -0,0 +1,40 @@ +#include +#include "vpi_user.h" + +#ifdef IVERILOG_V0_8 +static PLI_INT32 calltf(char *data) +#else +static PLI_INT32 calltf(PLI_BYTE8 *data) +#endif +{ + int i; + + (void)data; /* Parameter is not used. */ + + for (i = 0; i < 31; i++) { + if (vpi_mcd_name(1U< +#include "vpi_user.h" + +static PLI_INT32 +EndOfCompile(s_cb_data *data) +{ + vpiHandle hand; + s_vpi_time timerec = { vpiSimTime, 0, 0, 0 }; + s_vpi_value val; + int i; + + (void)data; /* Parameter is not used. */ + + hand = vpi_handle_by_name("test.r", 0); + assert(hand); + + // Get current state + val.format = vpiIntVal; + vpi_get_value(hand, &val); + + // Add a few transitions + for (i = 0; i < 6; i++) { + + if (i < 3) { + // delay 10+i time units + timerec.low = 1000 * (i + 1); + } else { + timerec.type = vpiScaledRealTime; + timerec.low = 0; + timerec.real = 10000.0 * (i+1); + } + + // Toggle state + val.value.integer ^= 1; + + // Put new state + vpi_put_value(hand, &val, &timerec, vpiPureTransportDelay); + } + + return 0; +} + + +static void +VPIRegister(void) +{ + s_cb_data cb_data; + s_vpi_time timerec = { vpiSuppressTime, 0, 0, 0 }; + + cb_data.time = &timerec; + cb_data.value = 0; + cb_data.user_data = 0; + cb_data.obj = 0; + cb_data.reason = cbEndOfCompile; + cb_data.cb_rtn = EndOfCompile; + + vpi_register_cb(&cb_data); +} + +void (*vlog_startup_routines[]) (void) = { VPIRegister, 0}; diff --git a/ivtest/vpi/putvalue.v b/ivtest/vpi/putvalue.v new file mode 100644 index 000000000..22a79d7d7 --- /dev/null +++ b/ivtest/vpi/putvalue.v @@ -0,0 +1,15 @@ +/* + * This test verifies vpiPureTransportDelay functionality + */ + +`timescale 1 ns / 1 ps +module test; + reg r; + initial begin + $monitor(" r = ", r); + #0.1 r = 1'b0; + #100000 $finish(0); + end + always @(r) $display(" r = %b @ %0t", r, $time); + +endmodule diff --git a/ivtest/vpi/range1.c b/ivtest/vpi/range1.c new file mode 100644 index 000000000..39d51eb02 --- /dev/null +++ b/ivtest/vpi/range1.c @@ -0,0 +1,57 @@ + +/* + */ +# include +# include + +static int sn_calltf(char*user_data) +{ + s_vpi_value value; + + int left_value; + int right_value; + + (void)user_data; /* Parameter is not used. */ + + /* Get the handle of an object that we know to be present. */ + vpiHandle xor_hand = vpi_handle_by_name("xor_try.inp_xor",0); + + /* The object is a vector, get the expressions for the left + and right range values. */ + vpiHandle left_hand = vpi_handle(vpiLeftRange, xor_hand); + vpiHandle right_hand = vpi_handle(vpiRightRange, xor_hand); + + assert(left_hand); + assert(right_hand); + + /* Extract the values from the expressions. */ + value.format = vpiIntVal; + vpi_get_value(left_hand, &value); + left_value = value.value.integer; + + value.format = vpiIntVal; + vpi_get_value(right_hand, &value); + right_value = value.value.integer; + + vpi_printf("Dimensions of xor_try.inp_xor: [%d:%d]\n", left_value, right_value); + return 0; +} + +static void vpi_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.calltf = sn_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + tf_data.tfname = "$sn"; + tf_data.user_data = 0; + + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[])(void) = { + vpi_register, + 0 +}; diff --git a/ivtest/vpi/range1.v b/ivtest/vpi/range1.v new file mode 100644 index 000000000..b621676d6 --- /dev/null +++ b/ivtest/vpi/range1.v @@ -0,0 +1,17 @@ +//--------------------------------------------------------------------------- +// +//--------------------------------------------------------------------------- + module xor_try; + + reg [1:0] inp_xor; // The two-bit inputs to the XOR + reg out_xor; // The XOR output + reg clk; + + initial begin clk = 1'b1; $sn; #160 $finish(0); end + always #50 clk = ~clk; + // The clock + + always @(posedge clk) out_xor = #1 (inp_xor[0] ^ inp_xor[1]); + // The actual operation + endmodule + diff --git a/ivtest/vpi/realcb.c b/ivtest/vpi/realcb.c new file mode 100644 index 000000000..59914c7da --- /dev/null +++ b/ivtest/vpi/realcb.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This program tests change callbacks on real variables. + */ +# include +# include + +static PLI_INT32 watchreal_cb(p_cb_data cb) +{ + s_vpi_value value; + vpiHandle arg = (vpiHandle) (cb->user_data); + + value.format = vpiRealVal; + vpi_get_value(arg, &value); + assert(value.format == vpiRealVal); + + vpi_printf("watchreal: %s = %f\n", + vpi_get_str(vpiName, arg), + value.value.real); + + return 0; +} + +#ifdef IVERILOG_V0_8 +static PLI_INT32 my_watchreal_calltf(char *xx) +#else +static PLI_INT32 my_watchreal_calltf(PLI_BYTE8 *xx) +#endif +{ + struct t_cb_data cb; + struct t_vpi_time timerec; + + (void)xx; /* Parameter is not used. */ + + vpiHandle sys = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + + vpiHandle arg; + + timerec.type = vpiSimTime; + timerec.low = 0; + timerec.high = 0; + + while (0 != (arg = vpi_scan(argv))) { + + assert(vpi_get(vpiType, arg) == vpiRealVar); + + cb.reason = cbValueChange; + cb.cb_rtn = watchreal_cb; + cb.time = &timerec; + cb.obj = arg; + cb.value = 0; + cb.user_data = (char*)arg; + vpi_register_cb(&cb); + + } + + return 0; +} + +static void my_watchreal_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$my_watchreal"; + tf_data.calltf = my_watchreal_calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[])(void) = { + my_watchreal_register, + 0 +}; diff --git a/ivtest/vpi/realcb.v b/ivtest/vpi/realcb.v new file mode 100644 index 000000000..c1d45abb2 --- /dev/null +++ b/ivtest/vpi/realcb.v @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2003 Stephen Williams (steve@icarus.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + * + * $Id: realcb.v,v 1.1 2003/02/10 05:14:13 stevewilliams Exp $ + */ + +module main; + + real x, y; + + initial begin + $my_watchreal(x, y); + #1 x = 1.0; + #1 y = 2.0; + #1 x = 1.5; + #1 y = 5.1; + end + +endmodule // main diff --git a/ivtest/vpi/realtime.c b/ivtest/vpi/realtime.c new file mode 100644 index 000000000..e4f74e1c6 --- /dev/null +++ b/ivtest/vpi/realtime.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2003 Michael Ruff (mruff at chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test verifies vpiScaledRealTime + */ + +#include +#include "vpi_user.h" + +s_vpi_time get_time = { vpiScaledRealTime, 0, 0, 0 }; + +#ifdef IVERILOG_V0_8 +static PLI_INT32 calltf(char *data) +#else +static PLI_INT32 calltf(PLI_BYTE8 *data) +#endif +{ + vpiHandle hand, iter; + + (void)data; /* Parameter is not used. */ + + hand = vpi_handle(vpiSysTfCall, 0); + iter = vpi_iterate(vpiArgument, hand); + hand = vpi_scan(iter); + vpi_free_object(iter); + + vpi_printf("calltf from %s", vpi_get_str(vpiName, hand)); + + vpi_get_time(0, &get_time); + vpi_printf(" %f,", get_time.real); + + vpi_get_time(hand, &get_time); + vpi_printf(" %f\n", get_time.real); + + return 0; +} + +static void +VPIRegister(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$test"; + tf_data.calltf = calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[]) (void) = { VPIRegister, 0}; diff --git a/ivtest/vpi/realtime.v b/ivtest/vpi/realtime.v new file mode 100644 index 000000000..73d060ba4 --- /dev/null +++ b/ivtest/vpi/realtime.v @@ -0,0 +1,23 @@ +`timescale 1 ms / 1 ps +module test; + initial begin + #12345.6789; + $display("time = %0f", $realtime); + $test(test); + #2345.67891; + $display("time = %0f", $realtime); + $test(test); + end +endmodule + +`timescale 1 ps / 1 ps +module test2; + initial begin + #12345.6789; + $display("time = %0f", $realtime); + $test(test2); + #2345.67891; + $display("time = %0f", $realtime); + $test(test2); + end +endmodule diff --git a/ivtest/vpi/realtime2.c b/ivtest/vpi/realtime2.c new file mode 100644 index 000000000..e4f74e1c6 --- /dev/null +++ b/ivtest/vpi/realtime2.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2003 Michael Ruff (mruff at chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * This test verifies vpiScaledRealTime + */ + +#include +#include "vpi_user.h" + +s_vpi_time get_time = { vpiScaledRealTime, 0, 0, 0 }; + +#ifdef IVERILOG_V0_8 +static PLI_INT32 calltf(char *data) +#else +static PLI_INT32 calltf(PLI_BYTE8 *data) +#endif +{ + vpiHandle hand, iter; + + (void)data; /* Parameter is not used. */ + + hand = vpi_handle(vpiSysTfCall, 0); + iter = vpi_iterate(vpiArgument, hand); + hand = vpi_scan(iter); + vpi_free_object(iter); + + vpi_printf("calltf from %s", vpi_get_str(vpiName, hand)); + + vpi_get_time(0, &get_time); + vpi_printf(" %f,", get_time.real); + + vpi_get_time(hand, &get_time); + vpi_printf(" %f\n", get_time.real); + + return 0; +} + +static void +VPIRegister(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$test"; + tf_data.calltf = calltf; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[]) (void) = { VPIRegister, 0}; diff --git a/ivtest/vpi/realtime2.v b/ivtest/vpi/realtime2.v new file mode 100644 index 000000000..2c95654d7 --- /dev/null +++ b/ivtest/vpi/realtime2.v @@ -0,0 +1,23 @@ +`timescale 1 ns / 1 ps +module test; + initial begin + #12.3456; + $display("$time = %0t", $time); + $test(test); + #34.5678; + $display("$time = %0t", $time); + $test(test); + end +endmodule + +`timescale 1 ps / 1 ps +module test2; + initial begin + #56.7890; + $display("$time = %0t", $time); + $test(test2); + #78.9012; + $display("$time = %0t", $time); + $test(test2); + end +endmodule diff --git a/ivtest/vpi/ro_synch.c b/ivtest/vpi/ro_synch.c new file mode 100644 index 000000000..530295553 --- /dev/null +++ b/ivtest/vpi/ro_synch.c @@ -0,0 +1,108 @@ +# include +# include +# include + +struct poke_details { + vpiHandle dst; + int val; + int dly; +}; + +static PLI_INT32 delayed_poke(p_cb_data cb_data) +{ + s_vpi_value value; + s_vpi_time time; + struct poke_details*poke = (struct poke_details*)cb_data->user_data; + + value.format = vpiIntVal; + value.value.integer = poke->val; + if (poke->dly < 0) { + vpi_put_value(poke->dst, &value, 0, vpiNoDelay); + } else { + time.type = vpiSimTime; + time.high = 0; + time.low = poke->dly; + time.real = 0.0; + vpi_put_value(poke->dst, &value, &time, vpiTransportDelay); + } + fflush(stderr); // for Windows + free(poke); + return 0; +} + +static PLI_INT32 poke_compiletf(char*xx) +{ + (void)xx; /* Parameter is not used. */ + return 0; +} + +static PLI_INT32 poke_calltf(char*xx) +{ + s_vpi_value value; + s_vpi_time poke_time; + s_cb_data cb_data; + vpiHandle sys = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle dst, val, dly, tmp; + + struct poke_details*poke; + + (void)xx; /* Parameter is not used. */ + + assert(argv); + + dst = vpi_scan(argv); + assert(dst); + + val = vpi_scan(argv); + assert(val); + + dly = vpi_scan(argv); + assert(dly); + + tmp = vpi_scan(argv); + assert(tmp == 0); + + poke = calloc(1, sizeof (struct poke_details)); + assert(poke); + + poke->dst = dst; + + value.format = vpiIntVal; + vpi_get_value(val, &value); + poke->val = value.value.integer; + + value.format = vpiIntVal; + vpi_get_value(dly, &value); + poke->dly = value.value.integer; + + poke_time.low = 0; + poke_time.high = 0; + poke_time.type = vpiSimTime; + + cb_data.reason = cbReadOnlySynch; + cb_data.cb_rtn = delayed_poke; + cb_data.user_data = (char*)poke; + cb_data.time = &poke_time; + vpi_register_cb(&cb_data); + + return 0; +} + +static void poke_after_delay_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$delayed_poke"; + tf_data.calltf = poke_calltf; + tf_data.compiletf = poke_compiletf; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); + +} + +void (*vlog_startup_routines[])(void) = { + poke_after_delay_register, + 0 +}; diff --git a/ivtest/vpi/ro_synch.v b/ivtest/vpi/ro_synch.v new file mode 100644 index 000000000..7d10db3d8 --- /dev/null +++ b/ivtest/vpi/ro_synch.v @@ -0,0 +1,23 @@ +module main; + + integer val; + + initial begin + val = 0; + $delayed_poke(val, 1, -1); + $delayed_poke(val, 2, 0); + $delayed_poke(val, 3, 1); + #1 if (val !== 0) begin + $display("FAILED -- val==%0d before legal poke", val); + $finish; + end + #1 if (val !== 3) begin + $display("FAILED -- val==%0d: legal poke didn't happen", val); + $finish; + end + + $display("PASSED"); + $finish(0); + end + +endmodule // main diff --git a/ivtest/vpi/scanmem.cc b/ivtest/vpi/scanmem.cc new file mode 100644 index 000000000..fb19a5e97 --- /dev/null +++ b/ivtest/vpi/scanmem.cc @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com) + * Michael Runyan (mrunyan at chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include +#include +#include "vpi_user.h" + +#ifdef IVERILOG_V0_8 +extern "C" PLI_INT32 MemPeek(char *) +#else +extern "C" PLI_INT32 MemPeek(PLI_BYTE8 *) +#endif +{ + vpiHandle mod_h, mem_h, iterate, handle; + s_vpi_value value; + + vpi_printf("MemPeek Callback\n"); + + // get top module handle + iterate = vpi_iterate(vpiModule, NULL); + if (iterate == NULL) return -1; + mod_h = vpi_scan(iterate); + vpi_free_object(iterate); + + // Get memory + mem_h = NULL; + iterate = vpi_iterate(vpiMemory, mod_h); + if (iterate != NULL) { + while ((handle = vpi_scan(iterate))) { + if (!strcmp("m_peek", vpi_get_str(vpiName, handle))) { + vpiHandle memw_iter = vpi_iterate(vpiMemoryWord, handle); + vpi_printf(" Found %s (%d deep x %d bits)\n", + vpi_get_str(vpiName, handle), + (int)vpi_get(vpiSize, handle), + (int)vpi_get(vpiSize, vpi_scan(memw_iter))); + vpi_free_object(memw_iter); + mem_h = handle; + vpi_free_object(iterate); + break; + } + } + } + + // Invert read memory + iterate = vpi_iterate(vpiMemoryWord, mem_h); + while ((handle = vpi_scan(iterate))) { + // Get current value + value.format=vpiIntVal; + vpi_get_value(handle, &value); + + // Store inverted + value.value.integer ^= 0xffffffff; + if (vpi_get(vpiSize, handle) < 32) { + value.value.integer &= ~((1 << vpi_get(vpiSize, handle)) - 1); + } + vpi_put_value(handle, &value, NULL, vpiNoDelay); + } + + return 0; +} + +#define REP4(x) \ + (((x) & 0xff) << 24 | ((x) & 0xff) << 16 | ((x) & 0xff) << 8 | ((x) & 0xff)) + +#ifdef IVERILOG_V0_8 +extern "C" PLI_INT32 MemPoke(char *) +#else +extern "C" PLI_INT32 MemPoke(PLI_BYTE8 *) +#endif +{ + vpiHandle mod_h, mem_h, iterate, handle; + s_vpi_value value; + + vpi_printf("MemPoke Callback\n"); + + // get top module handle + iterate = vpi_iterate(vpiModule, NULL); + if (iterate == NULL) return -1; + mod_h = vpi_scan(iterate); + vpi_free_object(iterate); + + // Get memory + mem_h = NULL; + iterate = vpi_iterate(vpiMemory, mod_h); + if (iterate != NULL) { + while ((handle = vpi_scan(iterate))) { + if (!strcmp("m_poke", vpi_get_str(vpiName, handle))) { + vpiHandle memw_iter = vpi_iterate(vpiMemoryWord, handle); + vpi_printf(" Found %s (%d deep x %d bits)\n", + vpi_get_str(vpiName, handle), + (int)vpi_get(vpiSize, handle), + (int)vpi_get(vpiSize, vpi_scan(memw_iter))); + vpi_free_object(memw_iter); + mem_h = handle; + vpi_free_object(iterate); + break; + } + } + } + + // Poke memory using integers + iterate = vpi_iterate(vpiMemoryWord, mem_h); + while ((handle = vpi_scan(iterate))) { + value.format = vpiIntVal; + vpi_get_value(vpi_handle(vpiIndex, handle), &value); + value.value.integer = REP4(1 + value.value.integer); + if (vpi_get(vpiSize, handle) < 32) { + value.value.integer &= ~((1 << vpi_get(vpiSize, handle)) - 1); + } + vpi_put_value(handle, &value, NULL, vpiNoDelay); + } + + return 0; +} + +extern "C" void +RegisterCallbacks(void) +{ + s_vpi_systf_data tf_data; + + vpi_printf("Registering Callbacks\n"); + + tf_data.type = vpiSysTask; + tf_data.tfname = "$mempoke"; + tf_data.calltf = MemPoke; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); + + tf_data.tfname = "$mempeek"; + tf_data.calltf = MemPeek; + vpi_register_systf(&tf_data); +} + +#ifdef __SUNPRO_CC +extern "C" +#endif +void (*vlog_startup_routines[]) () = { + RegisterCallbacks, + 0 +}; diff --git a/ivtest/vpi/scanmem.v b/ivtest/vpi/scanmem.v new file mode 100644 index 000000000..024388887 --- /dev/null +++ b/ivtest/vpi/scanmem.v @@ -0,0 +1,67 @@ +// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com) +// Michael Runyan (mrunyan at chiaro.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module test; + + reg [5:0] addr; + reg [31:0] m_poke[4:0]; + reg [31:0] m_peek[4:0]; + + task f_init; + integer i; + begin + for (i = 0; i < 5; i = i + 1) begin + m_poke[i] = $random; + end + end + endtask + + task f_copy; + integer i; + begin + for (i = 0; i < 5; i = i + 1) begin + m_peek[i] = m_poke[i]; + end + end + endtask + + task f_dump; + integer i; + begin + for (i = 0; i < 5; i = i + 1) begin + $display ("m_poke[%0d] <=> m_peek[%0d] 0x%x 0x%x%s", + i, i, m_poke[i], m_peek[i], + m_poke[i] !== ~m_peek[i] ? " - ERROR" : ""); + end + end + endtask + + initial begin + // f_init; + #0; + $mempoke; + #10; + f_copy; + #10; + $mempeek; + #10; + f_dump; + end + +endmodule diff --git a/ivtest/vpi/scanmem2.cc b/ivtest/vpi/scanmem2.cc new file mode 100644 index 000000000..e170d7f73 --- /dev/null +++ b/ivtest/vpi/scanmem2.cc @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com) + * Michael Runyan (mrunyan at chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include +#include +#include +#include "vpi_user.h" + +// A 76 bit value +const char *str[4] = { + "f00cafababedeabbeef", + "70850123451113459662575", + "17001453725653733652737357", + "1111000000001100101011111010101110101011111011011110101010111011111011101111" +}; + +#ifdef IVERILOG_V0_8 +extern "C" PLI_INT32 MemPeek(char *) +#else +extern "C" PLI_INT32 MemPeek(PLI_BYTE8 *) +#endif +{ + vpiHandle mod_h, mem_h, iterate, handle; + s_vpi_value value; + int cnt = 0; + const char *orig; + + vpi_printf("MemPeek Callback\n"); + + // get top module handle + iterate = vpi_iterate(vpiModule, NULL); + if (iterate == NULL) return -1; + mod_h = vpi_scan(iterate); + vpi_free_object(iterate); + + // Get memory + mem_h = NULL; + iterate = vpi_iterate(vpiMemory, mod_h); + if (iterate != NULL) { + while ((handle = vpi_scan(iterate))) { + if (!strcmp("m_peek", vpi_get_str(vpiName, handle))) { + vpiHandle memw_iter = vpi_iterate(vpiMemoryWord, handle); + vpi_printf(" Found %s (%d deep x %d bits)\n", + vpi_get_str(vpiName, handle), + (int)vpi_get(vpiSize, handle), + (int)vpi_get(vpiSize, vpi_scan(memw_iter))); + vpi_free_object(memw_iter); + mem_h = handle; + vpi_free_object(iterate); + break; + } + } + } + + // Get value + orig = ""; + iterate = vpi_iterate(vpiMemoryWord, mem_h); + while ((handle = vpi_scan(iterate))) { + switch (cnt % 4) { + case 0: + value.format=vpiBinStrVal; + orig = str[3]; + break; + case 1: + value.format=vpiOctStrVal; + orig = str[2]; + break; + case 2: + value.format=vpiDecStrVal; + orig = str[1]; + break; + case 3: + value.format=vpiHexStrVal; + orig = str[0]; + break; + } + // Get current value + vpi_get_value(handle, &value); + vpi_printf("%0d: %s%s\n", cnt, value.value.str, + strcmp(orig, value.value.str) ? " ERROR" : ""); + cnt++; + } + + return 0; +} + +#ifdef IVERILOG_V0_8 +extern "C" PLI_INT32 MemPoke(char *) +#else +extern "C" PLI_INT32 MemPoke(PLI_BYTE8 *) +#endif +{ + vpiHandle mod_h, mem_h, iterate, handle; + s_vpi_value value; + int cnt = 0; + + vpi_printf("MemPoke Callback\n"); + + // get top module handle + iterate = vpi_iterate(vpiModule, NULL); + if (iterate == NULL) return -1; + mod_h = vpi_scan(iterate); + vpi_free_object(iterate); + + // Get memory + mem_h = NULL; + iterate = vpi_iterate(vpiMemory, mod_h); + if (iterate != NULL) { + while ((handle = vpi_scan(iterate))) { + if (!strcmp("m_poke", vpi_get_str(vpiName, handle))) { + vpiHandle memw_iter = vpi_iterate(vpiMemoryWord, handle); + vpi_printf(" Found %s (%d deep x %d bits)\n", + vpi_get_str(vpiName, handle), + (int)vpi_get(vpiSize, handle), + (int)vpi_get(vpiSize, vpi_scan(memw_iter))); + vpi_free_object(memw_iter); + mem_h = handle; + vpi_free_object(iterate); + break; + } + } + } + + // Poke memory using strings + iterate = vpi_iterate(vpiMemoryWord, mem_h); + while ((handle = vpi_scan(iterate))) { + switch (cnt % 4) { + case 0: + value.format=vpiHexStrVal; + value.value.str = strdup(str[0]); + break; + case 1: + value.format=vpiDecStrVal; + value.value.str = strdup(str[1]); + break; + case 2: + value.format=vpiOctStrVal; + value.value.str = strdup(str[2]); + break; + case 3: + value.format=vpiBinStrVal; + value.value.str = strdup(str[3]); + break; + } + vpi_printf("%0d: %s\n", cnt, value.value.str); + vpi_put_value(handle, &value, NULL, vpiNoDelay); + free(value.value.str); + cnt++; + } + + return 0; +} + +extern "C" void +RegisterCallbacks(void) +{ + s_vpi_systf_data tf_data; + + vpi_printf("Registering Callbacks\n"); + + tf_data.type = vpiSysTask; + tf_data.tfname = "$mempoke"; + tf_data.calltf = MemPoke; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); + + tf_data.tfname = "$mempeek"; + tf_data.calltf = MemPeek; + vpi_register_systf(&tf_data); +} + +#ifdef __SUNPRO_CC +extern "C" +#endif +void (*vlog_startup_routines[])() = +{ + RegisterCallbacks, + 0 +}; diff --git a/ivtest/vpi/scanmem2.v b/ivtest/vpi/scanmem2.v new file mode 100644 index 000000000..ca5490fde --- /dev/null +++ b/ivtest/vpi/scanmem2.v @@ -0,0 +1,69 @@ +// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com) +// Michael Runyan (mrunyan at chiaro.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module test; + + reg [5:0] addr; + reg [75:0] m_poke[4:0]; + reg [75:0] m_peek[4:0]; + + task f_copy_for_buggy_eda_vendor; + integer i; + reg [75:0] tmp; + begin + for (i = 0; i < 5; i = i + 1) begin + tmp = m_poke[i]; + m_peek[i] = tmp; + end + end + endtask + + task f_copy; + integer i; + begin + for (i = 0; i < 5; i = i + 1) begin + m_peek[i] = m_poke[i]; + end + end + endtask + + task f_dump; + integer i; + begin + for (i = 0; i < 5; i = i + 1) begin + $display ("%0d: m_poke <=> m_peek, 0x%x <=> 0x%x%s", + i, m_poke[i], m_peek[i], + m_poke[i] !== m_peek[i] ? " - ERROR" : ""); + end + end + endtask + + initial begin + #0; + $mempoke; + #10; + f_copy; + //f_copy_buggy_eda_vendor; + #10; + $mempeek; + #10; + f_dump; + end + +endmodule diff --git a/ivtest/vpi/scanmem3.cc b/ivtest/vpi/scanmem3.cc new file mode 100644 index 000000000..39c22be80 --- /dev/null +++ b/ivtest/vpi/scanmem3.cc @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com) + * Michael Runyan (mrunyan at chiaro.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include +#include +#include +#include "vpi_user.h" + +static struct str_s { + int format; + const char *str; +} words[8] = { + {vpiBinStrVal, "x001x001"}, + {vpiOctStrVal, "0x2"}, + {vpiDecStrVal, "3"}, + {vpiHexStrVal, "x4"}, + + {vpiBinStrVal, "x101x101"}, + {vpiOctStrVal, "0x6"}, + {vpiDecStrVal, "7"}, + {vpiHexStrVal, "x8"} +}; + +#ifdef IVERILOG_V0_8 +extern "C" PLI_INT32 MemPeek(char *) +#else +extern "C" PLI_INT32 MemPeek(PLI_BYTE8 *) +#endif +{ + vpiHandle mod_h, mem_h, iterate, handle; + vpiHandle word_h[8]; + s_vpi_value value; + int index; + + vpi_printf("MemPeek Callback\n"); + + // get top module handle + iterate = vpi_iterate(vpiModule, NULL); + if (iterate == NULL) return -1; + mod_h = vpi_scan(iterate); + vpi_free_object(iterate); + + // Get memory + mem_h = NULL; + iterate = vpi_iterate(vpiMemory, mod_h); + if (iterate != NULL) { + while ((handle = vpi_scan(iterate))) { + if (!strcmp("m_peek", vpi_get_str(vpiName, handle))) { + vpiHandle memw_iter = vpi_iterate(vpiMemoryWord, handle); + vpi_printf(" Found %s (%d deep x %d bits)\n", + vpi_get_str(vpiName, handle), + (int)vpi_get(vpiSize, handle), + (int)vpi_get(vpiSize, vpi_scan(memw_iter))); + vpi_free_object(memw_iter); + mem_h = handle; + vpi_free_object(iterate); + break; + } + } + } + + // Get value + iterate = vpi_iterate(vpiMemoryWord, mem_h); + while ((handle = vpi_scan(iterate))) { + // Get word index + value.format=vpiIntVal; + vpi_get_value(vpi_handle(vpiIndex, handle), &value); + index = value.value.integer; + // squirrel away handles + word_h[index] = handle; + } + for (index = 0; index < 8; index++) { + // Print out info + value.format=vpiBinStrVal; + vpi_get_value(word_h[index], &value); + vpi_printf("%3d: 'b_%s,", index, value.value.str); + + value.format=vpiOctStrVal; + vpi_get_value(word_h[index], &value); + vpi_printf(" 'o_%s,", value.value.str); + + value.format=vpiDecStrVal; + vpi_get_value(word_h[index], &value); + vpi_printf(" 'd_%s,", value.value.str); + + value.format=vpiHexStrVal; + vpi_get_value(word_h[index], &value); + vpi_printf(" 'h_%s\n", value.value.str); + } + + return 0; +} + +#ifdef IVERILOG_V0_8 +extern "C" PLI_INT32 MemPoke(char *) +#else +extern "C" PLI_INT32 MemPoke(PLI_BYTE8 *) +#endif +{ + vpiHandle mod_h, mem_h, iterate, handle; + vpiHandle word_h[8]; + s_vpi_value value; + int index; + + vpi_printf("MemPoke Callback\n"); + + // get top module handle + iterate = vpi_iterate(vpiModule, NULL); + if (iterate == NULL) return -1; + mod_h = vpi_scan(iterate); + vpi_free_object(iterate); + + // Get memory + mem_h = NULL; + iterate = vpi_iterate(vpiMemory, mod_h); + if (iterate != NULL) { + while ((handle = vpi_scan(iterate))) { + if (!strcmp("m_poke", vpi_get_str(vpiName, handle))) { + vpiHandle memw_iter = vpi_iterate(vpiMemoryWord, handle); + vpi_printf(" Found %s (%d deep x %d bits)\n", + vpi_get_str(vpiName, handle), + (int)vpi_get(vpiSize, handle), + (int)vpi_get(vpiSize, vpi_scan(memw_iter))); + vpi_free_object(memw_iter); + mem_h = handle; + vpi_free_object(iterate); + break; + } + } + } + + // Poke memory using strings + iterate = vpi_iterate(vpiMemoryWord, mem_h); + + while ((handle = vpi_scan(iterate))) { + // Get word index + value.format=vpiIntVal; + vpi_get_value(vpi_handle(vpiIndex, handle), &value); + index = value.value.integer; + // squirrel away handles + word_h[index] = handle; + } + + for (index = 0; index < 8; index++) { + value.format=words[index].format; + value.value.str=strdup(words[index].str); + vpi_printf("%3d: %s\n", index, value.value.str); + vpi_put_value(word_h[index], &value, NULL, vpiNoDelay); + free(value.value.str); + } + + return 0; +} + +extern "C" void +RegisterCallbacks(void) +{ + s_vpi_systf_data tf_data; + + vpi_printf("Registering Callbacks\n"); + + tf_data.type = vpiSysTask; + tf_data.tfname = "$mempoke"; + tf_data.calltf = MemPoke; + tf_data.compiletf = 0; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); + + tf_data.tfname = "$mempeek"; + tf_data.calltf = MemPeek; + vpi_register_systf(&tf_data); +} + +#ifdef __SUNPRO_CC +extern "C" +#endif +void (*vlog_startup_routines[])() = +{ + RegisterCallbacks, + 0 +}; diff --git a/ivtest/vpi/scanmem3.v b/ivtest/vpi/scanmem3.v new file mode 100644 index 000000000..36e629c7e --- /dev/null +++ b/ivtest/vpi/scanmem3.v @@ -0,0 +1,58 @@ +// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com) +// Michael Runyan (mrunyan at chiaro.com) +// +// This source code is free software; you can redistribute it +// and/or modify it in source code form under the terms of the GNU +// General Public License as published by the Free Software +// Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +// + +module test; + + reg [2:0] addr; + reg [7:0] m_poke[7:0]; + reg [7:0] m_peek[7:0]; + + task f_copy; + integer i; + begin + for (i = 0; i < 8; i = i + 1) begin + m_peek[i] = m_poke[i]; + end + end + endtask + + task f_dump; + integer i; + begin + $display("Verilog compare m_poke <=> m_peek"); + for (i = 0; i < 8; i = i + 1) begin + $display (" %0d: 'b_%b <=> 'b_%b%s", + i, m_poke[i], m_peek[i], + m_poke[i] !== m_peek[i] ? " - ERROR" : ""); + end + end + endtask + + initial begin + #0; + $mempoke; + #10; + f_copy; + #10; + $mempeek; + #10; + f_dump; + end + +endmodule diff --git a/ivtest/vpi/scopes.c b/ivtest/vpi/scopes.c new file mode 100644 index 000000000..a067f0060 --- /dev/null +++ b/ivtest/vpi/scopes.c @@ -0,0 +1,59 @@ +#include +#include +#include "vpi_user.h" + +static void spaces(int num) +{ + while (num > 0) { + vpi_printf(" "); + num--; + } +} + +static void RecurseScope(vpiHandle handle, int depth) +{ + vpiHandle iter, hand; + + iter = !handle ? vpi_iterate(vpiModule, NULL) : + vpi_iterate(vpiInternalScope, handle); + + while (iter && (hand = vpi_scan(iter))) { + spaces(depth); + vpi_printf("%s is type ", vpi_get_str(vpiName, hand)); + switch (vpi_get(vpiType,hand)) { + case vpiModule: vpi_printf("vpiModule\n"); break; + case vpiTask: vpi_printf("vpiTask\n"); break; + case vpiFunction: vpi_printf("vpiFunction\n"); break; + case vpiNamedBegin: vpi_printf("vpiNamedBegin\n"); break; + case vpiNamedFork: vpi_printf("vpiNamedFork\n"); break; + default: vpi_printf("unknown (%d)\n", (int)vpi_get(vpiType,hand)); break; + } + RecurseScope(hand, depth + 2); + } +} + +#ifdef IVERILOG_V0_8 +static PLI_INT32 CompileTF(char *x) +#else +static PLI_INT32 CompileTF(PLI_BYTE8 *x) +#endif +{ + (void)x; /* Parameter is not used. */ + RecurseScope(NULL, 0); + return 0; +} + +static void my_Register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$test"; + tf_data.calltf = 0; + tf_data.compiletf = CompileTF; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[]) (void) = { +my_Register, 0}; diff --git a/ivtest/vpi/scopes.v b/ivtest/vpi/scopes.v new file mode 100644 index 000000000..1fb2d34e9 --- /dev/null +++ b/ivtest/vpi/scopes.v @@ -0,0 +1,67 @@ +module lvl3; + reg [1:0] m[1:0]; + initial begin + fork: my_fork + repeat (1) begin + m[0] = 2'b0; + end + repeat (1) begin + m[1] = 2'b1; + end + join + end +endmodule + + +module lvl2_0; + reg r; + initial r = $random; + lvl3 lvl3(); +endmodule + +module lvl1_0; + reg r; + function f_foo; + input bar; + begin + f_foo = bar; + end + endfunction + initial r = f_foo(r); + lvl2_0 lvl2(); +endmodule + +module top0; + reg r; + task t_bar; + r = 1'b0; + endtask + initial begin: my_init + r = $random; + t_bar; + end + lvl1_0 lvl1(); +endmodule + + +module lvl2_1; + integer i; + initial i = $random; + lvl3 lvl3(); +endmodule + +module lvl1_1; + integer i; + initial i = $random; + lvl2_1 lvl2(); +endmodule + +module top1; + integer i; + initial i = $random; + lvl1_1 lvl1(); +endmodule + +module top2; + initial $test; +endmodule diff --git a/ivtest/vpi/spec_delays.c b/ivtest/vpi/spec_delays.c new file mode 100644 index 000000000..91afc78f6 --- /dev/null +++ b/ivtest/vpi/spec_delays.c @@ -0,0 +1,190 @@ +# include +# include +# include +# include + + +#ifdef IVERILOG_V0_8 +static PLI_INT32 dump_specify_compiletf(char*name) +#else +static PLI_INT32 dump_specify_compiletf(PLI_BYTE8*name) +#endif +{ + vpiHandle sys = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle item; + + item = vpi_scan(argv); + if (argv == 0) { + vpi_printf("%s: scope name argument missing.\n", name); + vpi_control(vpiFinish, 1); + return -1; + } + + if (vpi_get(vpiType, item) != vpiModule) { + vpi_printf("%s: Argument is not a vpiModule\n", name); + vpi_control(vpiFinish, 1); + return -1; + } + + item = vpi_scan(argv); + if (item != 0) { + vpi_printf("%s: Too many arguments.\n", name); + vpi_control(vpiFinish, 1); + return -1; + } + + return 0; +} + +#ifdef IVERILOG_V0_8 +static PLI_INT32 dump_specify_calltf(char*name) +#else +static PLI_INT32 dump_specify_calltf(PLI_BYTE8*name) +#endif +{ + vpiHandle sys = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle item = vpi_scan(argv); + + (void)name; /* Parameter is not used. */ + + assert(item); + vpi_free_object(argv); + + vpi_printf("** Look for vpiModPath objects in %s.\n", + vpi_get_str(vpiName, item)); + + argv = vpi_iterate(vpiModPath, item); + if (argv == 0) { + vpi_printf("** NO modpath items?\n"); + } else { + struct t_vpi_time delay_times[12]; + struct t_vpi_delay delays; + for (item = vpi_scan(argv); item; item = vpi_scan(argv)) { + vpiHandle in_argv = vpi_iterate(vpiModPathIn, item); + vpiHandle in_term = in_argv ? vpi_scan(in_argv) : 0; + vpiHandle in_expr = in_term ? vpi_handle(vpiExpr, in_term) : 0; + if (in_argv) vpi_free_object(in_argv); + vpiHandle out_argv = vpi_iterate(vpiModPathOut, item); + vpiHandle out_term = out_argv ? vpi_scan(out_argv) : 0; + vpiHandle out_expr = out_term ? vpi_handle(vpiExpr, out_term) : 0; + if (out_argv) vpi_free_object(out_argv); + vpi_printf("** got path: %s ", + in_expr ? vpi_get_str(vpiName, in_expr) : "?"); + vpi_printf("--> %s\n", + out_expr ? vpi_get_str(vpiName, out_expr) : "?"); + + delays.da = delay_times; + delays.no_of_delays = 12; + delays.time_type = vpiSimTime; + delays.mtm_flag = 0; + delays.append_flag = 0; +#ifdef IVERILOG_V10 + delays.plusere_flag = 0; +#else + delays.pulsere_flag = 0; +#endif + vpi_get_delays(item, &delays); + vpi_printf("** (%d,%d,%d, %d,%d,%d, %d,%d,%d, %d,%d,%d)\n", + (int)delay_times[0].low, + (int)delay_times[1].low, + (int)delay_times[2].low, + (int)delay_times[3].low, + (int)delay_times[4].low, + (int)delay_times[5].low, + (int)delay_times[6].low, + (int)delay_times[7].low, + (int)delay_times[8].low, + (int)delay_times[9].low, + (int)delay_times[10].low, + (int)delay_times[11].low); + + delays.da = delay_times; + delays.no_of_delays = 12; + delays.time_type = vpiScaledRealTime; + delays.mtm_flag = 0; + delays.append_flag = 0; +#ifdef IVERILOG_V10 + delays.plusere_flag = 0; +#else + delays.pulsere_flag = 0; +#endif + vpi_get_delays(item, &delays); + vpi_printf("** (%f,%f,%f, %f,%f,%f, %f,%f,%f, %f,%f,%f)\n", + delay_times[0].real, + delay_times[1].real, + delay_times[2].real, + delay_times[3].real, + delay_times[4].real, + delay_times[5].real, + delay_times[6].real, + delay_times[7].real, + delay_times[8].real, + delay_times[9].real, + delay_times[10].real, + delay_times[11].real); + + delays.time_type = vpiScaledRealTime; + delay_times[0].real = 3.0; + delay_times[1].real = 3.0; + delay_times[2].real = 3.0; + delay_times[3].real = 3.0; + delay_times[4].real = 3.0; + delay_times[5].real = 3.0; + delay_times[6].real = 3.0; + delay_times[7].real = 3.0; + delay_times[8].real = 3.0; + delay_times[9].real = 3.0; + delay_times[10].real = 3.0; + delay_times[11].real = 3.0; + vpi_put_delays(item, &delays); + + delays.da = delay_times; + delays.no_of_delays = 12; + delays.time_type = vpiScaledRealTime; + delays.mtm_flag = 0; + delays.append_flag = 0; +#ifdef IVERILOG_V10 + delays.plusere_flag = 0; +#else + delays.pulsere_flag = 0; +#endif + vpi_get_delays(item, &delays); + vpi_printf("** (%f,%f,%f, %f,%f,%f, %f,%f,%f, %f,%f,%f)\n", + delay_times[0].real, + delay_times[1].real, + delay_times[2].real, + delay_times[3].real, + delay_times[4].real, + delay_times[5].real, + delay_times[6].real, + delay_times[7].real, + delay_times[8].real, + delay_times[9].real, + delay_times[10].real, + delay_times[11].real); + } + } + + vpi_printf("** done\n"); + return 0; +} + +static void sys_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$dump_specify"; + tf_data.calltf = dump_specify_calltf; + tf_data.compiletf = dump_specify_compiletf; + tf_data.sizetf = 0; + tf_data.user_data = "$dump_specify"; + vpi_register_systf(&tf_data); +} + +void (*vlog_startup_routines[])(void) = { + sys_register, + 0 +}; diff --git a/ivtest/vpi/spec_delays.v b/ivtest/vpi/spec_delays.v new file mode 100644 index 000000000..365a2f4c4 --- /dev/null +++ b/ivtest/vpi/spec_delays.v @@ -0,0 +1,37 @@ +`celldefine +//`timescale 1ns / 1ps + +// Description : 2 input XOR + +module XOR20 (input A, input B, output Q); + + xor (Q,B,A); + + specify + (A => Q) = (1,1); + (B => Q) = (1,1); + endspecify + +endmodule + +`endcelldefine + +module tb; + + reg a, b; + wire q; + XOR20 dut(.A(a), .B(b), .Q(q)); + + initial begin + $monitor($time,, "A=%b, B=%b, Q=%b", a, b, q); + $dump_specify(dut); + + #10 ; + a = 1; + b = 1; + #10 ; + b = 0; + #10 $finish(0); + end + +endmodule // tb diff --git a/ivtest/vpi/start_of_simtime1.c b/ivtest/vpi/start_of_simtime1.c new file mode 100644 index 000000000..078f19e8b --- /dev/null +++ b/ivtest/vpi/start_of_simtime1.c @@ -0,0 +1,96 @@ +# include +# include +# include + +struct poke_details { + vpiHandle dst; + int val; +}; + +static PLI_INT32 delayed_poke(p_cb_data cb_data) +{ + s_vpi_value value; + struct poke_details*poke = (struct poke_details*)cb_data->user_data; + + value.format = vpiIntVal; + value.value.integer = poke->val; + vpi_put_value(poke->dst, &value, 0, vpiNoDelay); + + free(poke); + return 0; +} + +static PLI_INT32 poke_compiletf(char*xx) +{ + (void)xx; /* Parameter is not used. */ + return 0; +} + +static PLI_INT32 poke_calltf(char*xx) +{ + s_vpi_value value; + s_vpi_time poke_time; + s_cb_data cb_data; + vpiHandle sys = vpi_handle(vpiSysTfCall, 0); + vpiHandle argv = vpi_iterate(vpiArgument, sys); + vpiHandle dst, val, del, tmp; + + struct poke_details*poke; + + (void)xx; /* Parameter is not used. */ + + assert(argv); + + dst = vpi_scan(argv); + assert(dst); + + val = vpi_scan(argv); + assert(val); + + del = vpi_scan(argv); + assert(del); + + tmp = vpi_scan(argv); + assert(tmp == 0); + + poke = calloc(1, sizeof (struct poke_details)); + assert(poke); + + poke->dst = dst; + + value.format = vpiIntVal; + vpi_get_value(val, &value); + poke->val = value.value.integer; + + value.format = vpiIntVal; + vpi_get_value(del, &value); + poke_time.low = value.value.integer; + poke_time.high = 0; + poke_time.type = vpiSimTime; + + cb_data.reason = cbAtStartOfSimTime; + cb_data.cb_rtn = delayed_poke; + cb_data.user_data = (char*)poke; + cb_data.time = &poke_time; + vpi_register_cb(&cb_data); + + return 0; +} + +static void poke_after_delay_register(void) +{ + s_vpi_systf_data tf_data; + + tf_data.type = vpiSysTask; + tf_data.tfname = "$poke_at_simtime"; + tf_data.calltf = poke_calltf; + tf_data.compiletf = poke_compiletf; + tf_data.sizetf = 0; + vpi_register_systf(&tf_data); + +} + +void (*vlog_startup_routines[])(void) = { + poke_after_delay_register, + 0 +}; diff --git a/ivtest/vpi/start_of_simtime1.v b/ivtest/vpi/start_of_simtime1.v new file mode 100644 index 000000000..af13069ad --- /dev/null +++ b/ivtest/vpi/start_of_simtime1.v @@ -0,0 +1,31 @@ +// When registering a simulation time callback, some simulators interpret +// the specified time value as relative to the current simulation time. To +// support this case, define the macro CB_TIME_IS_RELATIVE when compiling +// this module. + +module main; + + integer val; + + initial begin + val = 0; + #1 $poke_at_simtime(val, 1, 10); + +`ifdef CB_TIME_IS_RELATIVE + #1; +`endif + #8 if (val !== 0) begin + $display("FAILED -- val==%0d before delayed poke", val); + $finish; + end + + #1 if (val !== 1) begin + $display("FAILED -- val==%0d: poke didn't happen", val); + $finish; + end + + $display("PASSED"); + $finish(0); + end + +endmodule // main diff --git a/ivtest/vpi/timescale.c b/ivtest/vpi/timescale.c new file mode 100644 index 000000000..a75e77402 --- /dev/null +++ b/ivtest/vpi/timescale.c @@ -0,0 +1,74 @@ +#include "veriuser.h" + +extern PLI_INT32 tf_getlongsimtime(PLI_INT32 *high); + +static int +mytest(int ud, int reason) +{ + PLI_INT32 ht, lt; + PLI_BYTE8 *cp; + PLI_BYTE8 *inst = tf_getinstance(); + PLI_BYTE8 *name = tf_spname(); + + (void)ud; /* Parameter is not used. */ + (void)reason; /* Parameter is not used. */ + + io_printf("Module %s\n", name); + + lt = tf_gettime(); + io_printf("\ttf_gettime()\t\t\t-> %d\n", (int)lt); + + cp = tf_strgettime(); + io_printf("\ttf_strgettime()\t\t\t-> %s\n", cp); + + lt = tf_getlongtime(&ht); + io_printf("\ttf_getlongtime()\t\t-> %d/%d\n", (int)ht, (int)lt); + + lt = tf_igetlongtime(&ht, inst); + io_printf("\ttf_igetlongtime(inst)\t\t-> %d/%d\n", (int)ht, (int)lt); + + lt = tf_getlongsimtime(&ht); + io_printf("\ttf_getlongsimtime()\t\t-> %d/%d\n", (int)ht, (int)lt); + + lt = tf_gettimeprecision(); + io_printf("\ttf_gettimeprecision()\t\t-> %d\n", (int)lt); + + lt = tf_igettimeprecision(inst); + io_printf("\ttf_igettimeprecision(inst)\t-> %d\n", (int)lt); + + lt = tf_gettimeunit(); + io_printf("\ttf_gettimeunit()\t\t-> %d\n", (int)lt); + + lt = tf_igettimeunit(inst); + io_printf("\ttf_gettimeunit(inst)\t\t-> %d\n", (int)lt); + + lt = tf_igettimeunit(0); + io_printf("\ttf_gettimeunit(0)\t\t-> %d\n", (int)lt); + + return 0; +} + +static int return_32(int ud, int reason) +{ + (void)ud; /* Parameter is not used. */ + (void)reason; /* Parameter is not used. */ + return 32; +} + +s_tfcell veriusertfs[2] = { + { usertask, 0, 0, return_32, mytest, 0, "$mytest", 1, 0, 0, {0} }, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0} } +}; + +// Icarus registration +p_tfcell icarus_veriusertfs(void) { + return veriusertfs; +} + + // Icarus Verilog compatibility +static void veriusertfs_register(void) +{ + veriusertfs_register_table(veriusertfs); +} + +void (*vlog_startup_routines[])(void) = { &veriusertfs_register, 0 }; diff --git a/ivtest/vpi/timescale.v b/ivtest/vpi/timescale.v new file mode 100644 index 000000000..36d6f681a --- /dev/null +++ b/ivtest/vpi/timescale.v @@ -0,0 +1,17 @@ +`timescale 1us / 1ns + +module usns; + initial begin + #123; + $mytest; + end +endmodule + +`timescale 1ns / 1ns + +module nsns; + initial begin + #456; + $mytest; + end +endmodule diff --git a/ivtest/vpi_gold/br_gh117.gold b/ivtest/vpi_gold/br_gh117.gold new file mode 100644 index 000000000..fb15a536a --- /dev/null +++ b/ivtest/vpi_gold/br_gh117.gold @@ -0,0 +1,19 @@ +Compiling vpi/br_gh117.c... +Making br_gh117.vpi from br_gh117.o... +Register callbacks +After delay - current time 0 +Read write - current time 1 +Read only - current time 9 +After delay - current time 10 +Read write - current time 11 +Read only - current time 19 +After delay - current time 20 +Read write - current time 21 +Read only - current time 29 +After delay - current time 30 +Read write - current time 31 +Read only - current time 39 +After delay - current time 40 +Read write - current time 41 +Read only - current time 49 +Finish sim - current time 50 diff --git a/ivtest/vpi_gold/br_gh141.gold b/ivtest/vpi_gold/br_gh141.gold new file mode 100644 index 000000000..989c439fb --- /dev/null +++ b/ivtest/vpi_gold/br_gh141.gold @@ -0,0 +1,13 @@ +Compiling vpi/br_gh141.c... +Making br_gh141.vpi from br_gh141.o... +misctf called for reason 16 + 0 0 +started background copy +misctf called for reason 7 +misctf called for reason 7 + 1 1 +misctf called for reason 7 +misctf called for reason 7 + 2 2 +finished background copy +misctf called for reason 9 diff --git a/ivtest/vpi_gold/br_gh169a.gold b/ivtest/vpi_gold/br_gh169a.gold new file mode 100644 index 000000000..c648d4066 --- /dev/null +++ b/ivtest/vpi_gold/br_gh169a.gold @@ -0,0 +1,12 @@ +Compiling vpi/br_gh169.c... +Making br_gh169a.vpi from br_gh169.o... +scope test + wire test.a + wire test.c + wire test.b +scope test.dut1 + wire test.dut1.i1 + reg test.dut1.o1 +scope test.dut2 + wire test.dut2.i2 + reg test.dut2.o2 diff --git a/ivtest/vpi_gold/br_gh169b.gold b/ivtest/vpi_gold/br_gh169b.gold new file mode 100644 index 000000000..04768446a --- /dev/null +++ b/ivtest/vpi_gold/br_gh169b.gold @@ -0,0 +1,12 @@ +Compiling vpi/br_gh169.c... +Making br_gh169b.vpi from br_gh169.o... +scope test + real test.a + real test.c + real test.b +scope test.dut1 + real test.dut1.o1 + real test.dut1.i1 +scope test.dut2 + real test.dut2.i2 + real test.dut2.o2 diff --git a/ivtest/vpi_gold/br_gh184.gold b/ivtest/vpi_gold/br_gh184.gold new file mode 100644 index 000000000..c1a526513 --- /dev/null +++ b/ivtest/vpi_gold/br_gh184.gold @@ -0,0 +1,3 @@ +Compiling vpi/start_of_simtime1.c... +Making br_gh184.vpi from start_of_simtime1.o... +PASSED diff --git a/ivtest/vpi_gold/br_gh235.gold b/ivtest/vpi_gold/br_gh235.gold new file mode 100644 index 000000000..b6be9f4f4 --- /dev/null +++ b/ivtest/vpi_gold/br_gh235.gold @@ -0,0 +1,4 @@ +Compiling vpi/br_gh235.c... +Making br_gh235.vpi from br_gh235.o... +1 +PASSED diff --git a/ivtest/vpi_gold/br_gh308.gold b/ivtest/vpi_gold/br_gh308.gold new file mode 100644 index 000000000..d64ba5d37 --- /dev/null +++ b/ivtest/vpi_gold/br_gh308.gold @@ -0,0 +1,4 @@ +Compiling vpi/br_gh308.c... +Making br_gh308.vpi from br_gh308.o... +msb = 'b_00000000000000000000000000011111 +lsb = 'b_00000000000000000000000000000000 diff --git a/ivtest/vpi_gold/br_gh317.gold b/ivtest/vpi_gold/br_gh317.gold new file mode 100644 index 000000000..e88b6c526 --- /dev/null +++ b/ivtest/vpi_gold/br_gh317.gold @@ -0,0 +1,14 @@ +Compiling vpi/br_gh317.c... +Making br_gh317.vpi from br_gh317.o... +Looking for "\esc.port": found "esc.port" +Looking for "\esc.port ": found "esc.port" +Looking for "\esc.mod .\esc.inm .\esc.port": found "esc.port" +Looking for "\esc.mod .\esc.inm .\esc.port ": found "esc.port" +Looking for "\esc.val": found "esc.val" +Looking for "\esc.val ": found "esc.val" +Looking for "\esc.mod .\esc.inm .\esc.val": found "esc.val" +Looking for "\esc.mod .\esc.inm .\esc.val ": found "esc.val" +Looking for "\esc.mod .\esc.inm .normal": found "normal" +Looking for "\esc.mod .inst.\esc.id": found "esc.id" +Looking for "\esc.mod .inst.\esc.id ": found "esc.id" +Looking for "\esc.mod .inst.normal": found "normal" diff --git a/ivtest/vpi_gold/br_gh496.gold b/ivtest/vpi_gold/br_gh496.gold new file mode 100644 index 000000000..d17ed90c2 --- /dev/null +++ b/ivtest/vpi_gold/br_gh496.gold @@ -0,0 +1,8 @@ +Compiling vpi/br_gh496.c... +Making br_gh496.vpi from br_gh496.o... +package $unit +package p1 +package p2 +module m1 +module m2 +module test diff --git a/ivtest/vpi_gold/br_gh59.gold b/ivtest/vpi_gold/br_gh59.gold new file mode 100644 index 000000000..eb572e1eb --- /dev/null +++ b/ivtest/vpi_gold/br_gh59.gold @@ -0,0 +1,6 @@ +Compiling vpi/br_gh59.c... +Making br_gh59.vpi from br_gh59.o... +zz z zz 0 +01 0 01 500 +01 1 zz 1000 +01 0 01 2000 diff --git a/ivtest/vpi_gold/br_gh73a.gold b/ivtest/vpi_gold/br_gh73a.gold new file mode 100644 index 000000000..0b8e3769e --- /dev/null +++ b/ivtest/vpi_gold/br_gh73a.gold @@ -0,0 +1,20 @@ +Compiling vpi/force.c... +Making br_gh73a.vpi from force.o... +peek : zzzz +display : zzzz zz +force : 10 +peek : 0010 +display : 0010 10 +release : zzzz +display : zzzz zz +force : 10 +peek : 0010 +display : 0010 10 +poke : 0 +peek : 0010 +display : 0010 10 +release : 0000 +display : 0000 00 +poke : 1 +peek : 0001 +display : 0001 01 diff --git a/ivtest/vpi_gold/br_gh73b.gold b/ivtest/vpi_gold/br_gh73b.gold new file mode 100644 index 000000000..92eb14322 --- /dev/null +++ b/ivtest/vpi_gold/br_gh73b.gold @@ -0,0 +1,20 @@ +Compiling vpi/force.c... +Making br_gh73b.vpi from force.o... +peek : zz +display : zz zzzz +force : 10 +peek : 10 +display : 10 z10z +release : zz +display : zz zzzz +force : 10 +peek : 10 +display : 10 z10z +poke : 0 +peek : 10 +display : 10 z10z +release : 00 +display : 00 z00z +poke : 1 +peek : 01 +display : 01 z01z diff --git a/ivtest/vpi_gold/br_ml20191013.gold b/ivtest/vpi_gold/br_ml20191013.gold new file mode 100644 index 000000000..889b02f37 --- /dev/null +++ b/ivtest/vpi_gold/br_ml20191013.gold @@ -0,0 +1,20 @@ +Compiling vpi/br_ml20191013.c... +Making br_ml20191013.vpi from br_ml20191013.o... + +$pow PLI compiletf function. + + +$pow PLI compiletf function. + + +$pow StartOfSim callback. + +Start simulation pow_test.v + +$pow PLI calltf function. + +$pow(2,3) returns 8 + +$pow PLI calltf function. + +$pow(a,b) returns 1 (a=1 b=0) diff --git a/ivtest/vpi_gold/by_index.gold b/ivtest/vpi_gold/by_index.gold new file mode 100644 index 000000000..c021e0c1a --- /dev/null +++ b/ivtest/vpi_gold/by_index.gold @@ -0,0 +1,19 @@ +Compiling vpi/by_index.c... +Making by_index.vpi from by_index.o... +The index is 3 +The type is vpiRegBit +val[3] => 1 == 1 +The index is 4 +The type is vpiNetBit +wval[4] => 0 == 0 +The index is 5 +The type is vpiMemoryWord +r_arr[5] => 5.25 == 5.25 +The index is 2 +The type is vpiMemoryWord +i_arr[2] => 1 == 1 +Original value is 01010101 + New value is 01010110 +Original net value is 1010 + New net value is 0110 + net value is now 1001 diff --git a/ivtest/vpi_gold/by_name-std.log b/ivtest/vpi_gold/by_name-std.log new file mode 100644 index 000000000..78abde262 --- /dev/null +++ b/ivtest/vpi_gold/by_name-std.log @@ -0,0 +1,23 @@ +Compiling vpi/by_name.c... +Making by_name.vpi from by_name.o... +Looking up top0: Found name = top0, type = 32 +Looking up top0.t_my: Found name = t_my, type = 59 +Looking up top0.f_my: Found name = f_my, type = 20 +Looking up top0.r: Found name = r, type = 48 +Looking up top0.t: Found name = t, type = 63 +Looking up top0.e: Found name = e, type = 34 +Looking up top0.i: Found name = i, type = 25 +Looking up top0.init: Found name = init, type = 33 +Looking up top0.lvl1_0: Found name = lvl1_0, type = 32 +Looking up top0.lvl1_1: Found name = lvl1_1, type = 32 +Looking up top0.lvl1_0.lvl2.t_my: Found name = t_my, type = 59 +Looking up top0.lvl1_0.lvl2.f_my: Found name = f_my, type = 20 +Looking up top0.lvl1_0.lvl2.r: Found name = r, type = 48 +Looking up top0.lvl1_0.lvl2.t: Found name = t, type = 63 +Looking up top0.lvl1_0.lvl2.e: Found name = e, type = 34 +Looking up top0.lvl1_0.lvl2.i: Found name = i, type = 25 +Looking up top0.lvl1_0.lvl2.init: Found name = init, type = 33 +Looking up top1: Found name = top1, type = 32 +Looking up noexsist: *** Not found *** +Looking up top1.noexsist: *** Not found *** +Looking up top1.lvl1.noexsist: *** Not found *** diff --git a/ivtest/vpi_gold/by_name.log b/ivtest/vpi_gold/by_name.log new file mode 100644 index 000000000..3b72d0304 --- /dev/null +++ b/ivtest/vpi_gold/by_name.log @@ -0,0 +1,23 @@ +Compiling vpi/by_name.c... +Making by_name.vpi from by_name.o... +Looking up top0: Found name = top0, type = 32 +Looking up top0.t_my: Found name = t_my, type = 59 +Looking up top0.f_my: Found name = f_my, type = 20 +Looking up top0.r: Found name = r, type = 48 +Looking up top0.t: Found name = t, type = 48 +Looking up top0.e: Found name = e, type = 34 +Looking up top0.i: Found name = i, type = 25 +Looking up top0.init: Found name = init, type = 33 +Looking up top0.lvl1_0: Found name = lvl1_0, type = 32 +Looking up top0.lvl1_1: Found name = lvl1_1, type = 32 +Looking up top0.lvl1_0.lvl2.t_my: Found name = t_my, type = 59 +Looking up top0.lvl1_0.lvl2.f_my: Found name = f_my, type = 20 +Looking up top0.lvl1_0.lvl2.r: Found name = r, type = 48 +Looking up top0.lvl1_0.lvl2.t: Found name = t, type = 48 +Looking up top0.lvl1_0.lvl2.e: Found name = e, type = 34 +Looking up top0.lvl1_0.lvl2.i: Found name = i, type = 25 +Looking up top0.lvl1_0.lvl2.init: Found name = init, type = 33 +Looking up top1: Found name = top1, type = 32 +Looking up noexsist: *** Not found *** +Looking up top1.noexsist: *** Not found *** +Looking up top1.lvl1.noexsist: *** Not found *** diff --git a/ivtest/vpi_gold/callback1.log b/ivtest/vpi_gold/callback1.log new file mode 100644 index 000000000..eb46e8f52 --- /dev/null +++ b/ivtest/vpi_gold/callback1.log @@ -0,0 +1,10 @@ +Compiling vpi/callback1.c... +Making callback1.vpi from callback1.o... +Registering Callbacks +EndOfCompile EOC +EndOfCompile EOC +StartOfSimulation SOS +StartOfSimulation SOS +Hello World +EndOfSimulation EOS +EndOfSimulation EOS diff --git a/ivtest/vpi_gold/celldefine.gold b/ivtest/vpi_gold/celldefine.gold new file mode 100644 index 000000000..577a59909 --- /dev/null +++ b/ivtest/vpi_gold/celldefine.gold @@ -0,0 +1,5 @@ +Compiling vpi/celldefine.c... +Making celldefine.vpi from celldefine.o... +Verilog checking was OK. +Module instance top.dut is not a cell. +Module instance top.dutb is a cell. diff --git a/ivtest/vpi_gold/check_version.gold b/ivtest/vpi_gold/check_version.gold new file mode 100644 index 000000000..0c9ebfa52 --- /dev/null +++ b/ivtest/vpi_gold/check_version.gold @@ -0,0 +1,3 @@ +Compiling vpi/check_version.c... +Making check_version.vpi from check_version.o... +The two versions matched! diff --git a/ivtest/vpi_gold/display_array.gold b/ivtest/vpi_gold/display_array.gold new file mode 100644 index 000000000..7e2094a5d --- /dev/null +++ b/ivtest/vpi_gold/display_array.gold @@ -0,0 +1,7 @@ +Compiling vpi/display_array.c... +Making display_array.vpi from display_array.o... +{ 1, 2, 3, 4 } +{ 2, 3, 4, 5 } +{ 3.200000, 3.300000 } +{ 16045690984503098047, 841540768339247327, 81985529216486896, 18364758544493064721 } +{ uftu!tusjoh, bopuifs!pof, zfu!pof!npsf, uif!mbtu!pof } diff --git a/ivtest/vpi_gold/event1.log b/ivtest/vpi_gold/event1.log new file mode 100644 index 000000000..f174abf84 --- /dev/null +++ b/ivtest/vpi_gold/event1.log @@ -0,0 +1,4 @@ +Compiling vpi/event1.c... +Making event1.vpi from event1.o... +$test (test.evt [type = 34], test.evt2 [type = 34], test [type = 32]) +PASSED diff --git a/ivtest/vpi_gold/event2.log b/ivtest/vpi_gold/event2.log new file mode 100644 index 000000000..9ce0db9e3 --- /dev/null +++ b/ivtest/vpi_gold/event2.log @@ -0,0 +1,6 @@ +Compiling vpi/event2.c... +Making event2.vpi from event2.o... +Callback @ 10.0 +Callback @ 20.0 +Callback @ 30.0 +vpi_remove_cb returned 1 @ 30.0 diff --git a/ivtest/vpi_gold/final.gold b/ivtest/vpi_gold/final.gold new file mode 100644 index 000000000..b3b020745 --- /dev/null +++ b/ivtest/vpi_gold/final.gold @@ -0,0 +1,4 @@ +Compiling vpi/final.c... +Making final.vpi from final.o... +In final statement. +In VPI cbEndOfSimulation callback. diff --git a/ivtest/vpi_gold/find_sig.gold b/ivtest/vpi_gold/find_sig.gold new file mode 100644 index 000000000..0f53f2ab7 --- /dev/null +++ b/ivtest/vpi_gold/find_sig.gold @@ -0,0 +1,3 @@ +Compiling vpi/find_sig.c... +Making find_sig.vpi from find_sig.o... +PASSED diff --git a/ivtest/vpi_gold/force_reg.gold b/ivtest/vpi_gold/force_reg.gold new file mode 100644 index 000000000..4a120df5b --- /dev/null +++ b/ivtest/vpi_gold/force_reg.gold @@ -0,0 +1,20 @@ +Compiling vpi/force.c... +Making force_reg.vpi from force.o... +peek : xx +display : xx +force : 10 +peek : 10 +display : 10 +release : 10 +display : 10 +force : 10 +peek : 10 +display : 10 +poke : 0 +peek : 10 +display : 10 +release : 10 +display : 10 +poke : 1 +peek : 01 +display : 01 diff --git a/ivtest/vpi_gold/force_reg_pv.gold b/ivtest/vpi_gold/force_reg_pv.gold new file mode 100644 index 000000000..03a9b2909 --- /dev/null +++ b/ivtest/vpi_gold/force_reg_pv.gold @@ -0,0 +1,20 @@ +Compiling vpi/force.c... +Making force_reg_pv.vpi from force.o... +peek : xx +display :xxxx +force : 10 +peek : 10 +display :x10x +release : 10 +display :x10x +force : 10 +peek : 10 +display :x10x +poke : 0 +peek : 10 +display :x10x +release : 10 +display :x10x +poke : 1 +peek : 01 +display :x01x diff --git a/ivtest/vpi_gold/force_reg_real.gold b/ivtest/vpi_gold/force_reg_real.gold new file mode 100644 index 000000000..d3a26616f --- /dev/null +++ b/ivtest/vpi_gold/force_reg_real.gold @@ -0,0 +1,20 @@ +Compiling vpi/force_real.c... +Making force_reg_real.vpi from force_real.o... +peek : 0.000000 +display : 0.000000 +force : 3.000000 +peek : 3.000000 +display : 3.000000 +release : 3.000000 +display : 3.000000 +force : 3.000000 +peek : 3.000000 +display : 3.000000 +poke : 1.000000 +peek : 3.000000 +display : 3.000000 +release : 3.000000 +display : 3.000000 +poke : 2.000000 +peek : 2.000000 +display : 2.000000 diff --git a/ivtest/vpi_gold/force_wire.gold b/ivtest/vpi_gold/force_wire.gold new file mode 100644 index 000000000..0a4d9ed3b --- /dev/null +++ b/ivtest/vpi_gold/force_wire.gold @@ -0,0 +1,20 @@ +Compiling vpi/force.c... +Making force_wire.vpi from force.o... +peek : zz +display : zz +force : 10 +peek : 10 +display : 10 +release : zz +display : zz +force : 10 +peek : 10 +display : 10 +poke : 0 +peek : 10 +display : 10 +release : 00 +display : 00 +poke : 1 +peek : 01 +display : 01 diff --git a/ivtest/vpi_gold/force_wire_pv.gold b/ivtest/vpi_gold/force_wire_pv.gold new file mode 100644 index 000000000..46d68bfab --- /dev/null +++ b/ivtest/vpi_gold/force_wire_pv.gold @@ -0,0 +1,20 @@ +Compiling vpi/force.c... +Making force_wire_pv.vpi from force.o... +peek : zz +display :zzzz +force : 10 +peek : 10 +display :z10z +release : zz +display :zzzz +force : 10 +peek : 10 +display :z10z +poke : 0 +peek : 10 +display :z10z +release : 00 +display :z00z +poke : 1 +peek : 01 +display :z01z diff --git a/ivtest/vpi_gold/force_wire_real.gold b/ivtest/vpi_gold/force_wire_real.gold new file mode 100644 index 000000000..df8684539 --- /dev/null +++ b/ivtest/vpi_gold/force_wire_real.gold @@ -0,0 +1,20 @@ +Compiling vpi/force_real.c... +Making force_wire_real.vpi from force_real.o... +peek : 0.000000 +display : 0.000000 +force : 3.000000 +peek : 3.000000 +display : 3.000000 +release : 0.000000 +display : 0.000000 +force : 3.000000 +peek : 3.000000 +display : 3.000000 +poke : 1.000000 +peek : 3.000000 +display : 3.000000 +release : 1.000000 +display : 1.000000 +poke : 2.000000 +peek : 2.000000 +display : 2.000000 diff --git a/ivtest/vpi_gold/genblk_direct.gold b/ivtest/vpi_gold/genblk_direct.gold new file mode 100644 index 000000000..a5f445862 --- /dev/null +++ b/ivtest/vpi_gold/genblk_direct.gold @@ -0,0 +1,29 @@ +Compiling vpi/genblk_names.c... +Making genblk_direct.vpi from genblk_names.o... +reg test.genblk01[0].r1 +reg test.genblk01[1].r1 +reg test.genblk02[0].genblk1[0].r2 +reg test.genblk02[0].genblk1[1].r2 +reg test.genblk02[1].genblk1[0].r2 +reg test.genblk02[1].genblk1[1].r2 +reg test.genblk03[0].genblk1.r3b +reg test.genblk03[1].genblk1.r3b +reg test.genblk04[0].genblk1.r4a +reg test.genblk04[1].genblk1.r4a +reg test.genblk05[0].genblk1.r5b +reg test.genblk05[1].genblk1.r5b +reg test.genblk06[0].genblk1.r6c +reg test.genblk06[1].genblk1.r6c +reg test.genblk07.r7b +reg test.genblk08.r8d +reg test.genblk09.r9c +reg test.genblk10.r10e +reg test.genblk11.r11f +reg test.genblk12.r12a +reg test.genblk13.r13b +reg test.genblk14.r14c +reg test.genblk15.r15a +reg test.genblk16.r16b +reg test.genblk17.r17b +reg test.genblk18.r18d +reg test.genblk19.r19f diff --git a/ivtest/vpi_gold/genblk_named.gold b/ivtest/vpi_gold/genblk_named.gold new file mode 100644 index 000000000..404fa12a9 --- /dev/null +++ b/ivtest/vpi_gold/genblk_named.gold @@ -0,0 +1,33 @@ +Compiling vpi/genblk_names.c... +Making genblk_named.vpi from genblk_names.o... +reg test.c1.r7b +reg test.c2.c1.r8d +reg test.c3.i1.r9c +reg test.c4.i1.i1.r10e +reg test.c5.i1.i1.r11f +reg test.c6.i1.r12e +reg test.c7.i1.r13f +reg test.i01.r14a +reg test.i02.i1.r15b +reg test.i03.i1.r16c +reg test.i04.r17b +reg test.i05.r18c +reg test.i06.i1.r19a +reg test.i07.i1.r20b +reg test.i08.c1.r21b +reg test.i09.c1.r22d +reg test.i10.c1.r23f +reg test.l1[0].r1 +reg test.l1[1].r1 +reg test.l2[0].l1[0].r2 +reg test.l2[0].l1[1].r2 +reg test.l2[1].l1[0].r2 +reg test.l2[1].l1[1].r2 +reg test.l3[0].c1.r3b +reg test.l3[1].c1.r3b +reg test.l4[0].i1.r4a +reg test.l4[1].i1.r4a +reg test.l5[0].i1.i1.r5b +reg test.l5[1].i1.i1.r5b +reg test.l6[0].i1.i1.r6c +reg test.l6[1].i1.i1.r6c diff --git a/ivtest/vpi_gold/genblk_unnamed.gold b/ivtest/vpi_gold/genblk_unnamed.gold new file mode 100644 index 000000000..1251f630b --- /dev/null +++ b/ivtest/vpi_gold/genblk_unnamed.gold @@ -0,0 +1,33 @@ +Compiling vpi/genblk_names.c... +Making genblk_unnamed.vpi from genblk_names.o... +reg test.genblk01[0].r1 +reg test.genblk01[1].r1 +reg test.genblk02[0].genblk1[0].r2 +reg test.genblk02[0].genblk1[1].r2 +reg test.genblk02[1].genblk1[0].r2 +reg test.genblk02[1].genblk1[1].r2 +reg test.genblk03[0].genblk1.r3b +reg test.genblk03[1].genblk1.r3b +reg test.genblk04[0].genblk1.r4a +reg test.genblk04[1].genblk1.r4a +reg test.genblk05[0].genblk1.genblk1.r5b +reg test.genblk05[1].genblk1.genblk1.r5b +reg test.genblk06[0].genblk1.genblk1.r6c +reg test.genblk06[1].genblk1.genblk1.r6c +reg test.genblk07.r7b +reg test.genblk08.genblk1.r8d +reg test.genblk09.genblk1.r9c +reg test.genblk10.genblk1.genblk1.r10e +reg test.genblk11.genblk1.genblk1.r11f +reg test.genblk12.genblk1.r12e +reg test.genblk13.genblk1.r13f +reg test.genblk14.r14a +reg test.genblk15.genblk1.r15b +reg test.genblk16.genblk1.r16c +reg test.genblk17.r17b +reg test.genblk18.r18c +reg test.genblk19.genblk1.r19a +reg test.genblk20.genblk1.r20b +reg test.genblk21.genblk1.r21b +reg test.genblk22.genblk1.r22d +reg test.genblk23.genblk1.r23f diff --git a/ivtest/vpi_gold/getp.log b/ivtest/vpi_gold/getp.log new file mode 100644 index 000000000..1e227d5be --- /dev/null +++ b/ivtest/vpi_gold/getp.log @@ -0,0 +1,18 @@ +Compiling vpi/getp.c... +Making getp.vpi from getp.o... +tf_getp(1) -> 1 +tf_igetp(1,inst) -> 1 +tf_getrealp(1) -> 1.000000 +tf_igetrealp(1,inst) -> 1.000000 +tf_getp(2) -> 10 +tf_igetp(2,inst) -> 10 +tf_getrealp(2) -> 9.600000 +tf_igetrealp(2,inst) -> 9.600000 +tf_getp(3) -> 3 +tf_igetp(3,inst) -> 3 +tf_getrealp(3) -> 3.000000 +tf_igetrealp(3,inst) -> 3.000000 +tf_getp(4) -> 0 +tf_igetp(4,inst) -> 0 +tf_getrealp(4) -> 0.000000 +tf_igetrealp(4,inst) -> 0.000000 diff --git a/ivtest/vpi_gold/hello.log b/ivtest/vpi_gold/hello.log new file mode 100644 index 000000000..54c075815 --- /dev/null +++ b/ivtest/vpi_gold/hello.log @@ -0,0 +1,3 @@ +Compiling vpi/hello_vpi.c... +Making hello_vpi.vpi from hello_vpi.o... +Hello World, from VPI. diff --git a/ivtest/vpi_gold/hello_poke.log b/ivtest/vpi_gold/hello_poke.log new file mode 100644 index 000000000..06178d64b --- /dev/null +++ b/ivtest/vpi_gold/hello_poke.log @@ -0,0 +1,3 @@ +Compiling vpi/hello_poke.c... +Making hello_poke.vpi from hello_poke.o... +PASSED diff --git a/ivtest/vpi_gold/hello_tf.log b/ivtest/vpi_gold/hello_tf.log new file mode 100644 index 000000000..e48ff3cf8 --- /dev/null +++ b/ivtest/vpi_gold/hello_tf.log @@ -0,0 +1,3 @@ +Compiling vpi/hello_tf.c... +Making hello_tf.vpi from hello_tf.o... +Hello World, from VPI. diff --git a/ivtest/vpi_gold/listparams.log b/ivtest/vpi_gold/listparams.log new file mode 100644 index 000000000..3a5f68729 --- /dev/null +++ b/ivtest/vpi_gold/listparams.log @@ -0,0 +1,4 @@ +Compiling vpi/listparams.c... +Making listparams.vpi from listparams.o... + foo: 0101 + str: String Text diff --git a/ivtest/vpi_gold/memmon.log b/ivtest/vpi_gold/memmon.log new file mode 100644 index 000000000..28746d0b9 --- /dev/null +++ b/ivtest/vpi_gold/memmon.log @@ -0,0 +1,4 @@ +Compiling vpi/memmon.c... +Making memmon.vpi from memmon.o... +ValueChange: index=0, value=00000100 +ValueChange: index=1, value=00000101 diff --git a/ivtest/vpi_gold/memwide-std.log b/ivtest/vpi_gold/memwide-std.log new file mode 100644 index 000000000..61378db54 --- /dev/null +++ b/ivtest/vpi_gold/memwide-std.log @@ -0,0 +1,29 @@ +Compiling vpi/memwide.cc... +Making memwide.vpi from memwide.o... +!!!C++: Registering Callbacks +!!!C++: event_trigger fullname is test.event_trigger +!!!C++: Registered Value Change Callback for event_trigger +!!!VERILOG: big_reg=xxxxxxxxx + my_mem[1]=xxxxxxxxx +!!!C++: callback +!!!C++: big_reg fullname is test.big_reg +!!!C++: big_reg size is 33 +Vec 0) ffffffff ffffffff +Vec 1) 00000001 00000001 +!!!C++: my_mem fullname is test.my_mem +!!!C++: my_mem[1] size is 33 +!!!C++: fullname is test.my_mem[1] +Vec 0) ffffffff ffffffff +Vec 1) 00000001 00000001 +!!!VERILOG: big_reg=123456789 + my_mem[1]=154329876 +!!!C++: callback +!!!C++: big_reg fullname is test.big_reg +!!!C++: big_reg size is 33 +Vec 0) 23456789 00000000 +Vec 1) 00000001 00000000 +!!!C++: my_mem fullname is test.my_mem +!!!C++: my_mem[1] size is 33 +!!!C++: fullname is test.my_mem[1] +Vec 0) 54329876 00000000 +Vec 1) 00000001 00000000 diff --git a/ivtest/vpi_gold/memwide.log b/ivtest/vpi_gold/memwide.log new file mode 100644 index 000000000..a9729d3ea --- /dev/null +++ b/ivtest/vpi_gold/memwide.log @@ -0,0 +1,39 @@ +Compiling vpi/memwide.cc... +Making memwide.vpi from memwide.o... +!!!C++: Registering Callbacks +!!!C++: event_trigger fullname is test.event_trigger +!!!C++: Registered Value Change Callback for event_trigger +!!!C++: callback +!!!C++: big_reg fullname is test.big_reg +!!!C++: big_reg size is 33 +Vec 0) ffffffff ffffffff +Vec 1) 00000001 00000001 +!!!C++: my_mem fullname is test.my_mem +!!!C++: my_mem[1] size is 33 +!!!C++: fullname is test.my_mem[1] +Vec 0) ffffffff ffffffff +Vec 1) 00000001 00000001 +!!!VERILOG: big_reg=xxxxxxxxx + my_mem[1]=xxxxxxxxx +!!!C++: callback +!!!C++: big_reg fullname is test.big_reg +!!!C++: big_reg size is 33 +Vec 0) ffffffff ffffffff +Vec 1) 00000001 00000001 +!!!C++: my_mem fullname is test.my_mem +!!!C++: my_mem[1] size is 33 +!!!C++: fullname is test.my_mem[1] +Vec 0) ffffffff ffffffff +Vec 1) 00000001 00000001 +!!!VERILOG: big_reg=123456789 + my_mem[1]=154329876 +!!!C++: callback +!!!C++: big_reg fullname is test.big_reg +!!!C++: big_reg size is 33 +Vec 0) 23456789 00000000 +Vec 1) 00000001 00000000 +!!!C++: my_mem fullname is test.my_mem +!!!C++: my_mem[1] size is 33 +!!!C++: fullname is test.my_mem[1] +Vec 0) 54329876 00000000 +Vec 1) 00000001 00000000 diff --git a/ivtest/vpi_gold/mipname.log b/ivtest/vpi_gold/mipname.log new file mode 100644 index 000000000..c02dde666 --- /dev/null +++ b/ivtest/vpi_gold/mipname.log @@ -0,0 +1,8 @@ +Compiling vpi/mipname.c... +Making mipname.vpi from mipname.o... +tf_mipname() -> test.t2.t3 +tf_imipname(inst) -> test.t2.t3 +tf_mipname() -> test.t2 +tf_imipname(inst) -> test.t2 +tf_mipname() -> test +tf_imipname(inst) -> test diff --git a/ivtest/vpi_gold/myscope.gold b/ivtest/vpi_gold/myscope.gold new file mode 100644 index 000000000..1a0d8147e --- /dev/null +++ b/ivtest/vpi_gold/myscope.gold @@ -0,0 +1,3 @@ +Compiling vpi/myscope.c... +Making myscope.vpi from myscope.o... +My scope name: xor_try (s.b. xor_try) diff --git a/ivtest/vpi_gold/myscope2.gold b/ivtest/vpi_gold/myscope2.gold new file mode 100644 index 000000000..ea1506911 --- /dev/null +++ b/ivtest/vpi_gold/myscope2.gold @@ -0,0 +1,12 @@ +Compiling vpi/myscope2.c... +Making myscope2.vpi from myscope2.o... +... ise_startup(reason=1) +... ise_vls_misc(reason=16) +... ise_vls_misc(reason=8) +... sn_calltf(reason=8) +high_time=0, low_time=0 +... sn_calltf(reason=3) +high_time=0, low_time=10 +... ise_vls_misc(reason=9) +... sn_calltf(reason=9) +high_time=0, low_time=170 diff --git a/ivtest/vpi_gold/nulls1-std.log b/ivtest/vpi_gold/nulls1-std.log new file mode 100644 index 000000000..296fb0a6c --- /dev/null +++ b/ivtest/vpi_gold/nulls1-std.log @@ -0,0 +1,14 @@ +Compiling vpi/nulls1.c... +Making nulls1.vpi from nulls1.o... +Registering Callbacks + 0: Value Change + 10: Value Change + 20: Value Change + 30: Value Change + 40: Value Change + 50: Value Change + 60: Value Change + 70: Value Change + 80: Value Change + 90: Value Change + 100: Value Change diff --git a/ivtest/vpi_gold/nulls1.log b/ivtest/vpi_gold/nulls1.log new file mode 100644 index 000000000..96c9736ac --- /dev/null +++ b/ivtest/vpi_gold/nulls1.log @@ -0,0 +1,15 @@ +Compiling vpi/nulls1.c... +Making nulls1.vpi from nulls1.o... +Registering Callbacks + 0: Value Change + 0: Value Change + 10: Value Change + 20: Value Change + 30: Value Change + 40: Value Change + 50: Value Change + 60: Value Change + 70: Value Change + 80: Value Change + 90: Value Change + 100: Value Change diff --git a/ivtest/vpi_gold/pokereg.log b/ivtest/vpi_gold/pokereg.log new file mode 100644 index 000000000..d1f96c063 --- /dev/null +++ b/ivtest/vpi_gold/pokereg.log @@ -0,0 +1,21 @@ +Compiling vpi/pokereg.cc... +Making pokereg.vpi from pokereg.o... +Registering Callbacks +RegPoke Callback + 0: x001x001 + 1: 0x2 + 2: 3 + 3: x4 + 4: 69 +RegPeek Callback + 0: 'b_00xxx010, 'o_0x2, 'd_X, 'h_XX + 1: 'b_00000011, 'o_003, 'd_3, 'h_03 + 2: 'b_xxxx0100, 'o_xX4, 'd_X, 'h_x4 + 3: 'b_01000101, 'o_105, 'd_69, 'h_45 + 4: 'b_x001x001, 'o_XX1, 'd_X, 'h_XX +Verilog compare r_poke <=> r_peek + 'b_x001x001 <=> 'b_x001x001 + 'b_00xxx010 <=> 'b_00xxx010 + 'b_00000011 <=> 'b_00000011 + 'b_xxxx0100 <=> 'b_xxxx0100 + 'b_01000101 <=> 'b_01000101 diff --git a/ivtest/vpi_gold/pokevent.log b/ivtest/vpi_gold/pokevent.log new file mode 100644 index 000000000..f9c8bbf37 --- /dev/null +++ b/ivtest/vpi_gold/pokevent.log @@ -0,0 +1,19 @@ +Compiling vpi/pokevent.cc... +Making pokevent.vpi from pokevent.o... +!!!C++: Registering Callbacks +e_Poke received @ 0 +e_Peek asserted @ 10 + callback +e_Poke received @ 10 +e_Peek asserted @ 20 + callback +e_Poke received @ 20 +e_Peek asserted @ 30 + callback +e_Poke received @ 30 +e_Peek asserted @ 40 + callback +e_Poke received @ 40 +e_Peek asserted @ 50 + callback +e_Poke received @ 50 diff --git a/ivtest/vpi_gold/ports_params.gold b/ivtest/vpi_gold/ports_params.gold new file mode 100644 index 000000000..449469c49 --- /dev/null +++ b/ivtest/vpi_gold/ports_params.gold @@ -0,0 +1,13 @@ +Compiling vpi/ports_params.c... +Making ports_params.vpi from ports_params.o... +PARAM NAME=ADC_OFFSET type=2 value=(REAL)-16 local=no +PARAM NAME=ADC_RANGE type=2 value=(REAL)32 local=no +PARAM NAME=CLOCK_INTERVAL type=3 value=(INT)1000 local=no +PARAM NAME=DAC_OFFSET type=2 value=(REAL)-8 local=no +PARAM NAME=DAC_RANGE type=2 value=(REAL)16 local=no +PARAM NAME=STARTUP_DELAY type=3 value=(INT)2000000 local=no +PARAM NAME=UPDATE_FREQ_MHZ type=2 value=(REAL)1 local=no +PORT name=V_load_adc index=0 dir=1 size=16 +PORT name=V_load_valid index=1 dir=1 size=1 +PORT name=pwm index=2 dir=2 size=1 +PORT name=V_src index=3 dir=2 size=8 diff --git a/ivtest/vpi_gold/pr1693971.log b/ivtest/vpi_gold/pr1693971.log new file mode 100644 index 000000000..7509bfd04 --- /dev/null +++ b/ivtest/vpi_gold/pr1693971.log @@ -0,0 +1,14 @@ +Compiling vpi/pr1693971.c... +Making pr1693971.vpi from pr1693971.o... + +$my_pow PLI compiletf function. + + +$my_pow PLI compiletf function. + + +$my_pow StartOfSim callback. + +Start simulation pow_test.v +$my_pow(2,3) returns 8 +$my_pow(a,b) returns 1 (a=1 b=0) diff --git a/ivtest/vpi_gold/pr2048463.log b/ivtest/vpi_gold/pr2048463.log new file mode 100644 index 000000000..0d2dba47b --- /dev/null +++ b/ivtest/vpi_gold/pr2048463.log @@ -0,0 +1,27 @@ +Compiling vpi/pr2048463.c... +Making pr2048463.vpi from pr2048463.o... + +Adding monitors to all nets in module addbit: + +At time 0.00: test.i1.a = 0 +At time 0.00: test.i1.b = 0 +At time 0.00: test.i1.ci = 0 +At time 1.00: test.i1.n1 = 0 +At time 2.00: test.i1.n2 = 0 +At time 3.00: test.i1.n3 = 0 +At time 5.00: test.i1.sum = 0 +At time 7.00: test.i1.co = 0 +At time 10.00: test.i1.a = 1 +At time 11.00: test.i1.n1 = 1 +At time 15.00: test.i1.sum = 1 +At time 20.00: test.i1.a = 0 +At time 21.00: test.i1.n1 = 0 +At time 25.00: test.i1.sum = 0 +At time 30.00: test.i1.b = 1 +At time 31.00: test.i1.n1 = 1 +At time 35.00: test.i1.sum = 1 +At time 40.00: test.i1.a = 1 +At time 41.00: test.i1.n1 = 0 +At time 42.00: test.i1.n2 = 1 +At time 45.00: test.i1.sum = 0 +At time 46.00: test.i1.co = 1 diff --git a/ivtest/vpi_gold/pr2314742.gold b/ivtest/vpi_gold/pr2314742.gold new file mode 100644 index 000000000..84dfd3936 --- /dev/null +++ b/ivtest/vpi_gold/pr2314742.gold @@ -0,0 +1,10 @@ +Compiling vpi/pr2314742.c... +Making pr2314742.vpi from pr2314742.o... +*** Registering XXX PLI functions. ++++ in XXX_REGISTER + 0 The value of A is: 00000000 + 0 The value of B is: 00000000 + 0 The value of C is: 00000000 + 10 The value of A is: 01010101 + 20 The value of B is: x1x1x1x1 + 30 The value of C is: 0xz101xz diff --git a/ivtest/vpi_gold/pr2966059.gold b/ivtest/vpi_gold/pr2966059.gold new file mode 100644 index 000000000..f0fddb41c --- /dev/null +++ b/ivtest/vpi_gold/pr2966059.gold @@ -0,0 +1,44 @@ +Compiling vpi/pr2966059.c... +Making pr2966059.vpi from pr2966059.o... +vpi_get_value (): + format = 9 + value = 1 +vpi_get_value (ip): + format = 9 + value = 1 +vpi_get_value (): + format = 7 + value = 0 +vpi_get_value (rp): + format = 7 + value = 2 +vpi_get_value (): + format = 8 + value = 3 +vpi_get_value (sp): + format = 8 + value = 3 +vpi_get_value (rlval): + format = 7 + value = 0 +vpi_get_value (): + format = 7 + value = 0 +vpi_get_value (wreal): + format = 7 + value = 0 +vpi_get_value (): + format = 7 + value = 0 +vpi_get_value (rval): + format = 9 + value = x +vpi_get_value (): + format = 9 + value = x +vpi_get_value (wval): + format = 9 + value = z +vpi_get_value (): + format = 9 + value = x diff --git a/ivtest/vpi_gold/pr2971220.gold b/ivtest/vpi_gold/pr2971220.gold new file mode 100644 index 000000000..fd7a4f4a7 --- /dev/null +++ b/ivtest/vpi_gold/pr2971220.gold @@ -0,0 +1,19 @@ +Compiling vpi/pr2971220.c... +Making pr2971220.vpi from pr2971220.o... +--> registered task as: $check_sys_task. +--> registered func as: $check_sys_func. +Hello from $hello at vpi/pr2971220.v:4. +registered as: vpiUserSystf - $check_sys_task + vpiUserDefn: is defined. + vpi_get_systf_info: passed. + vpi_get_systf_info (callh): passed. +Looking for all user defined system tasks/functions: + Found task vpiUserSystf - $check_sys_task *****> caller. + Found function (vpiIntFunc) vpiUserSystf - $check_sys_func. + Found task vpiUserSystf - $hello. +Done. +registered as: vpiUserSystf - $check_sys_func + vpiUserDefn: is defined. + vpi_get_systf_info: passed. + vpi_get_systf_info (callh): passed. +Hello from $hello at vpi/pr2971220.v:7. diff --git a/ivtest/vpi_gold/pr521.log b/ivtest/vpi_gold/pr521.log new file mode 100644 index 000000000..b2fa29170 --- /dev/null +++ b/ivtest/vpi_gold/pr521.log @@ -0,0 +1,6 @@ +Compiling vpi/pr521.c... +Making pr521.vpi from pr521.o... +Passing parameter to PLI routine: 0x43 +PLI Parameter received 0x43 +Passing parameter to PLI routine: 0x43 +PLI Parameter received 0x43 diff --git a/ivtest/vpi_gold/pr686.log b/ivtest/vpi_gold/pr686.log new file mode 100644 index 000000000..043093a1d --- /dev/null +++ b/ivtest/vpi_gold/pr686.log @@ -0,0 +1,7 @@ +Compiling vpi/pr686.c... +Making pr686.vpi from pr686.o... +foo should be 0: 1 +Callback time=1 foo=1 +foo should be 1: 1 +Callback time=5 foo=1 +foo is finally 2 diff --git a/ivtest/vpi_gold/pr723-std.log b/ivtest/vpi_gold/pr723-std.log new file mode 100644 index 000000000..71aca527c --- /dev/null +++ b/ivtest/vpi_gold/pr723-std.log @@ -0,0 +1,35 @@ +Compiling vpi/pr723.c... +Making pr723.vpi from pr723.o... +Open some files +open MCD returned 00000002 +open MCD returned 00000004 +open MCD returned 00000008 +open MCD returned 00000010 +open FD ('r') returned 80000003 +open FD ('r') returned 80000004 +open FD ('w') returned 80000005 +open FD ('w') returned 80000006 +open FD ('a') returned 80000007 +open FD ('a') returned 80000008 +MCD 01: stdout +MCD 02: /dev/null +MCD 03: /dev/null +MCD 04: /dev/null +MCD 05: /dev/null +FP 00: stdin +FP 01: stdout +FP 02: stderr +FP 03: /dev/null +FP 04: /dev/null +FP 05: /dev/null +FP 06: /dev/null +FP 07: /dev/null +FP 08: /dev/null +write to MCD 1 +write to FD 2 +write to FD 1 +Close some files +MCD 01: stdout +FP 00: stdin +FP 01: stdout +FP 02: stderr diff --git a/ivtest/vpi_gold/pr723-v10.log b/ivtest/vpi_gold/pr723-v10.log new file mode 100644 index 000000000..e40780e2c --- /dev/null +++ b/ivtest/vpi_gold/pr723-v10.log @@ -0,0 +1,41 @@ +Compiling vpi/pr723.c... +Making pr723.vpi from pr723.o... +Open some files +open MCD returned 00000002 +open MCD returned 00000004 +open MCD returned 00000008 +open MCD returned 00000010 +open FD ('r') returned 80000003 +open FD ('r') returned 80000004 +open FD ('w') returned 80000005 +open FD ('w') returned 80000006 +open FD ('a') returned 80000007 +open FD ('a') returned 80000008 +MCD 01: stdout +MCD 02: /dev/null +MCD 03: /dev/null +MCD 04: /dev/null +MCD 05: /dev/null +FP 00: stdin +FP 01: stdout +FP 02: stderr +FP 03: /dev/null +FP 04: /dev/null +FP 05: /dev/null +FP 06: /dev/null +FP 07: /dev/null +FP 08: /dev/null +write to MCD 1 +write to FD 2 +write to FD 1 +Close some files +WARNING: vpi/pr723.v:48: invalid file descriptor/MCD (0x2) given to $fclose. +WARNING: vpi/pr723.v:49: invalid file descriptor/MCD (0x40000000) given to $fclose. +WARNING: vpi/pr723.v:54: invalid file descriptor/MCD (0x80000003) given to $fclose. +WARNING: vpi/pr723.v:57: invalid file descriptor/MCD (0x81ca1ca0) given to $fclose. +MCD 01: stdout +FP 00: stdin +FP 01: stdout +FP 02: stderr +WARNING: vpi/pr723.v:63: invalid file descriptor/MCD (0x40000000) given to $fdisplay. +WARNING: vpi/pr723.v:64: invalid file descriptor/MCD (0x8000000f) given to $fdisplay. diff --git a/ivtest/vpi_gold/pr723.log b/ivtest/vpi_gold/pr723.log new file mode 100644 index 000000000..6fe39ce28 --- /dev/null +++ b/ivtest/vpi_gold/pr723.log @@ -0,0 +1,45 @@ +Compiling vpi/pr723.c... +Making pr723.vpi from pr723.o... +Open some files +open MCD returned 00000002 +open MCD returned 00000004 +open MCD returned 00000008 +open MCD returned 00000010 +open FD ('r') returned 80000003 +open FD ('r') returned 80000004 +open FD ('w') returned 80000005 +open FD ('w') returned 80000006 +open FD ('a') returned 80000007 +open FD ('a') returned 80000008 +MCD 01: stdout +MCD 02: /dev/null +MCD 03: /dev/null +MCD 04: /dev/null +MCD 05: /dev/null +FP 00: stdin +FP 01: stdout +FP 02: stderr +FP 03: /dev/null +FP 04: /dev/null +FP 05: /dev/null +FP 06: /dev/null +FP 07: /dev/null +FP 08: /dev/null +write to MCD 1 +write to FD 2 +write to FD 1 +Close some files +WARNING: vpi/pr723.v:47: could not close MCD STDOUT (0x1) in $fclose(). +WARNING: vpi/pr723.v:48: invalid MCD (0x2) given to $fclose(). +WARNING: vpi/pr723.v:49: invalid MCD (0x40000000) given to $fclose(). +WARNING: vpi/pr723.v:51: could not close file descriptor STDIN (0x80000000) in $fclose(). +WARNING: vpi/pr723.v:52: could not close file descriptor STDOUT (0x80000001) in $fclose(). +WARNING: vpi/pr723.v:53: could not close file descriptor STDERR (0x80000002) in $fclose(). +WARNING: vpi/pr723.v:54: invalid file descriptor (0x80000003) given to $fclose(). +WARNING: vpi/pr723.v:57: invalid file descriptor (0x81ca1ca0) given to $fclose(). +MCD 01: stdout +FP 00: stdin +FP 01: stdout +FP 02: stderr +WARNING: vpi/pr723.v:63: invalid MCD (0x40000000) given to $fdisplay(). +WARNING: vpi/pr723.v:64: invalid file descriptor (0x8000000f) given to $fdisplay(). diff --git a/ivtest/vpi_gold/putp.log b/ivtest/vpi_gold/putp.log new file mode 100644 index 000000000..d7fe02e5d --- /dev/null +++ b/ivtest/vpi_gold/putp.log @@ -0,0 +1,3 @@ +Compiling vpi/putp.c... +Making putp.vpi from putp.o... +PASSED diff --git a/ivtest/vpi_gold/putp2.log b/ivtest/vpi_gold/putp2.log new file mode 100644 index 000000000..ef3d661d3 --- /dev/null +++ b/ivtest/vpi_gold/putp2.log @@ -0,0 +1,3 @@ +Compiling vpi/putp2.c... +Making putp2.vpi from putp2.o... +PASSED diff --git a/ivtest/vpi_gold/putvalue.log b/ivtest/vpi_gold/putvalue.log new file mode 100644 index 000000000..98e79556a --- /dev/null +++ b/ivtest/vpi_gold/putvalue.log @@ -0,0 +1,17 @@ +Compiling vpi/putvalue.c... +Making putvalue.vpi from putvalue.o... + r = x + r = 0 @ 0 + r = 0 + r = 1 @ 1000 + r = 1 + r = 0 @ 2000 + r = 0 + r = 1 @ 3000 + r = 1 + r = 0 @ 40000000 + r = 0 + r = 1 @ 50000000 + r = 1 + r = 0 @ 60000000 + r = 0 diff --git a/ivtest/vpi_gold/range1.gold b/ivtest/vpi_gold/range1.gold new file mode 100644 index 000000000..3ffbfd148 --- /dev/null +++ b/ivtest/vpi_gold/range1.gold @@ -0,0 +1,3 @@ +Compiling vpi/range1.c... +Making range1.vpi from range1.o... +Dimensions of xor_try.inp_xor: [1:0] diff --git a/ivtest/vpi_gold/realcb.log b/ivtest/vpi_gold/realcb.log new file mode 100644 index 000000000..2a6e571f4 --- /dev/null +++ b/ivtest/vpi_gold/realcb.log @@ -0,0 +1,6 @@ +Compiling vpi/realcb.c... +Making realcb.vpi from realcb.o... +watchreal: x = 1.000000 +watchreal: y = 2.000000 +watchreal: x = 1.500000 +watchreal: y = 5.100000 diff --git a/ivtest/vpi_gold/realtime.log b/ivtest/vpi_gold/realtime.log new file mode 100644 index 000000000..8df43f890 --- /dev/null +++ b/ivtest/vpi_gold/realtime.log @@ -0,0 +1,10 @@ +Compiling vpi/realtime.c... +Making realtime.vpi from realtime.o... +time = 12346.000000 +calltf from test2 12346.000000, 12346.000000 +time = 14692.000000 +calltf from test2 14692.000000, 14692.000000 +time = 12345.678900 +calltf from test 12345678900000.000000, 12345.678900 +time = 14691.357810 +calltf from test 14691357810000.000000, 14691.357810 diff --git a/ivtest/vpi_gold/realtime2.log b/ivtest/vpi_gold/realtime2.log new file mode 100644 index 000000000..310242c2e --- /dev/null +++ b/ivtest/vpi_gold/realtime2.log @@ -0,0 +1,10 @@ +Compiling vpi/realtime2.c... +Making realtime2.vpi from realtime2.o... +$time = 57 +calltf from test2 57.000000, 57.000000 +$time = 136 +calltf from test2 136.000000, 136.000000 +$time = 12000 +calltf from test 12346.000000, 12.346000 +$time = 47000 +calltf from test 46914.000000, 46.914000 diff --git a/ivtest/vpi_gold/ro_synch.gold b/ivtest/vpi_gold/ro_synch.gold new file mode 100644 index 000000000..cd21b756d --- /dev/null +++ b/ivtest/vpi_gold/ro_synch.gold @@ -0,0 +1,5 @@ +Compiling vpi/ro_synch.c... +Making ro_synch.vpi from ro_synch.o... +VPI error: attempted to put a value to variable 'val' during a read-only synch callback. +VPI error: attempted to put a value to variable 'val' during a read-only synch callback. +PASSED diff --git a/ivtest/vpi_gold/scanmem.log b/ivtest/vpi_gold/scanmem.log new file mode 100644 index 000000000..90f19e7b8 --- /dev/null +++ b/ivtest/vpi_gold/scanmem.log @@ -0,0 +1,12 @@ +Compiling vpi/scanmem.cc... +Making scanmem.vpi from scanmem.o... +Registering Callbacks +MemPoke Callback + Found m_poke (5 deep x 32 bits) +MemPeek Callback + Found m_peek (5 deep x 32 bits) +m_poke[0] <=> m_peek[0] 0x01010101 0xfefefefe +m_poke[1] <=> m_peek[1] 0x02020202 0xfdfdfdfd +m_poke[2] <=> m_peek[2] 0x03030303 0xfcfcfcfc +m_poke[3] <=> m_peek[3] 0x04040404 0xfbfbfbfb +m_poke[4] <=> m_peek[4] 0x05050505 0xfafafafa diff --git a/ivtest/vpi_gold/scanmem2.log b/ivtest/vpi_gold/scanmem2.log new file mode 100644 index 000000000..8692829a1 --- /dev/null +++ b/ivtest/vpi_gold/scanmem2.log @@ -0,0 +1,22 @@ +Compiling vpi/scanmem2.cc... +Making scanmem2.vpi from scanmem2.o... +Registering Callbacks +MemPoke Callback + Found m_poke (5 deep x 76 bits) +0: f00cafababedeabbeef +1: 70850123451113459662575 +2: 17001453725653733652737357 +3: 1111000000001100101011111010101110101011111011011110101010111011111011101111 +4: f00cafababedeabbeef +MemPeek Callback + Found m_peek (5 deep x 76 bits) +0: 1111000000001100101011111010101110101011111011011110101010111011111011101111 +1: 17001453725653733652737357 +2: 70850123451113459662575 +3: f00cafababedeabbeef +4: 1111000000001100101011111010101110101011111011011110101010111011111011101111 +0: m_poke <=> m_peek, 0xf00cafababedeabbeef <=> 0xf00cafababedeabbeef +1: m_poke <=> m_peek, 0xf00cafababedeabbeef <=> 0xf00cafababedeabbeef +2: m_poke <=> m_peek, 0xf00cafababedeabbeef <=> 0xf00cafababedeabbeef +3: m_poke <=> m_peek, 0xf00cafababedeabbeef <=> 0xf00cafababedeabbeef +4: m_poke <=> m_peek, 0xf00cafababedeabbeef <=> 0xf00cafababedeabbeef diff --git a/ivtest/vpi_gold/scanmem3.log b/ivtest/vpi_gold/scanmem3.log new file mode 100644 index 000000000..f1261f85a --- /dev/null +++ b/ivtest/vpi_gold/scanmem3.log @@ -0,0 +1,32 @@ +Compiling vpi/scanmem3.cc... +Making scanmem3.vpi from scanmem3.o... +Registering Callbacks +MemPoke Callback + Found m_poke (8 deep x 8 bits) + 0: x001x001 + 1: 0x2 + 2: 3 + 3: x4 + 4: x101x101 + 5: 0x6 + 6: 7 + 7: x8 +MemPeek Callback + Found m_peek (8 deep x 8 bits) + 0: 'b_x001x001, 'o_XX1, 'd_X, 'h_XX + 1: 'b_00xxx010, 'o_0x2, 'd_X, 'h_XX + 2: 'b_00000011, 'o_003, 'd_3, 'h_03 + 3: 'b_xxxx0100, 'o_xX4, 'd_X, 'h_x4 + 4: 'b_x101x101, 'o_XX5, 'd_X, 'h_XX + 5: 'b_00xxx110, 'o_0x6, 'd_X, 'h_XX + 6: 'b_00000111, 'o_007, 'd_7, 'h_07 + 7: 'b_xxxx1000, 'o_xX0, 'd_X, 'h_x8 +Verilog compare m_poke <=> m_peek + 0: 'b_x001x001 <=> 'b_x001x001 + 1: 'b_00xxx010 <=> 'b_00xxx010 + 2: 'b_00000011 <=> 'b_00000011 + 3: 'b_xxxx0100 <=> 'b_xxxx0100 + 4: 'b_x101x101 <=> 'b_x101x101 + 5: 'b_00xxx110 <=> 'b_00xxx110 + 6: 'b_00000111 <=> 'b_00000111 + 7: 'b_xxxx1000 <=> 'b_xxxx1000 diff --git a/ivtest/vpi_gold/scopes-std.log b/ivtest/vpi_gold/scopes-std.log new file mode 100644 index 000000000..266871e81 --- /dev/null +++ b/ivtest/vpi_gold/scopes-std.log @@ -0,0 +1,16 @@ +Compiling vpi/scopes.c... +Making scopes.vpi from scopes.o... +top0 is type vpiModule + t_bar is type vpiTask + my_init is type vpiNamedBegin + lvl1 is type vpiModule + f_foo is type vpiFunction + lvl2 is type vpiModule + lvl3 is type vpiModule + my_fork is type vpiNamedFork +top1 is type vpiModule + lvl1 is type vpiModule + lvl2 is type vpiModule + lvl3 is type vpiModule + my_fork is type vpiNamedFork +top2 is type vpiModule diff --git a/ivtest/vpi_gold/scopes.log b/ivtest/vpi_gold/scopes.log new file mode 100644 index 000000000..302a88d1d --- /dev/null +++ b/ivtest/vpi_gold/scopes.log @@ -0,0 +1,16 @@ +Compiling vpi/scopes.c... +Making scopes.vpi from scopes.o... +top0 is type vpiModule + lvl1 is type vpiModule + f_foo is type vpiFunction + lvl2 is type vpiModule + lvl3 is type vpiModule + my_fork is type vpiNamedFork + my_init is type vpiNamedBegin + t_bar is type vpiTask +top1 is type vpiModule + lvl1 is type vpiModule + lvl2 is type vpiModule + lvl3 is type vpiModule + my_fork is type vpiNamedFork +top2 is type vpiModule diff --git a/ivtest/vpi_gold/spec_delays.log b/ivtest/vpi_gold/spec_delays.log new file mode 100644 index 000000000..e781b1c8f --- /dev/null +++ b/ivtest/vpi_gold/spec_delays.log @@ -0,0 +1,17 @@ +Compiling vpi/spec_delays.c... +Making spec_delays.vpi from spec_delays.o... +** Look for vpiModPath objects in dut. +** got path: A --> Q +** (1,1,1, 1,1,1, 1,1,1, 1,1,1) +** (1.000000,1.000000,1.000000, 1.000000,1.000000,1.000000, 1.000000,1.000000,1.000000, 1.000000,1.000000,1.000000) +** (3.000000,3.000000,3.000000, 3.000000,3.000000,3.000000, 3.000000,3.000000,3.000000, 3.000000,3.000000,3.000000) +** got path: B --> Q +** (1,1,1, 1,1,1, 1,1,1, 1,1,1) +** (1.000000,1.000000,1.000000, 1.000000,1.000000,1.000000, 1.000000,1.000000,1.000000, 1.000000,1.000000,1.000000) +** (3.000000,3.000000,3.000000, 3.000000,3.000000,3.000000, 3.000000,3.000000,3.000000, 3.000000,3.000000,3.000000) +** done + 0 A=x, B=x, Q=x + 10 A=1, B=1, Q=x + 13 A=1, B=1, Q=0 + 20 A=1, B=0, Q=0 + 23 A=1, B=0, Q=1 diff --git a/ivtest/vpi_gold/start_of_simtime1.log b/ivtest/vpi_gold/start_of_simtime1.log new file mode 100644 index 000000000..1458aa37f --- /dev/null +++ b/ivtest/vpi_gold/start_of_simtime1.log @@ -0,0 +1,3 @@ +Compiling vpi/start_of_simtime1.c... +Making start_of_simtime1.vpi from start_of_simtime1.o... +PASSED diff --git a/ivtest/vpi_gold/timescale.log b/ivtest/vpi_gold/timescale.log new file mode 100644 index 000000000..47ce9e9ab --- /dev/null +++ b/ivtest/vpi_gold/timescale.log @@ -0,0 +1,24 @@ +Compiling vpi/timescale.c... +Making timescale.vpi from timescale.o... +Module nsns + tf_gettime() -> 456 + tf_strgettime() -> 456 + tf_getlongtime() -> 0/456 + tf_igetlongtime(inst) -> 0/456 + tf_getlongsimtime() -> 0/456 + tf_gettimeprecision() -> -9 + tf_igettimeprecision(inst) -> -9 + tf_gettimeunit() -> -9 + tf_gettimeunit(inst) -> -9 + tf_gettimeunit(0) -> -9 +Module usns + tf_gettime() -> 123 + tf_strgettime() -> 123000 + tf_getlongtime() -> 0/123 + tf_igetlongtime(inst) -> 0/123 + tf_getlongsimtime() -> 0/123000 + tf_gettimeprecision() -> -9 + tf_igettimeprecision(inst) -> -9 + tf_gettimeunit() -> -6 + tf_gettimeunit(inst) -> -6 + tf_gettimeunit(0) -> -9 diff --git a/ivtest/vpi_reg.pl b/ivtest/vpi_reg.pl new file mode 100755 index 000000000..1abc6f0b5 --- /dev/null +++ b/ivtest/vpi_reg.pl @@ -0,0 +1,291 @@ +#!/usr/bin/env perl +# +# Script to handle regression for VPI routines +# +use lib './perl-lib'; + +use Environment; + +$| = 1; # This turns off buffered I/O + +# We support a --suffix= and --with-valgrind flags. +use Getopt::Long; +$sfx = ""; # Default suffix. +$with_valg = 0; # Default valgrind usage (keep this off). +if (!GetOptions("suffix=s" => \$sfx, + "with-valgrind" => \$with_valg, + "help" => \&usage)) { + die "Error: Invalid argument(s).\n"; +} + +sub usage { + warn "$0 usage:\n\n" . + " --suffix= # The Icarus executables suffix, " . + "default \"\".\n" . + " --with-valgrind # Run the test suite with valgrind, " . + "default \"off\".\n" . + " # The regression file, " . + "default \"./vpi_regress.list\".\n\n"; + exit; +} + +$regress_fn = "./vpi_regress.list"; # Default regression list. + +# Is there a command line argument (alternate regression list)? +if ($#ARGV != -1) { + $regress_fn = $ARGV[0]; + -e $regress_fn or + die "Error: command line regression file $regress_fn doesn't exist.\n"; + -f $regress_fn or + die "Error: command line regression file $regress_fn is not a file.\n"; + -r $regress_fn or + die "Error: command line regression file $regress_fn is not ". + "readable.\n"; + + if ($#ARGV > 0) { + warn "Warning: only using first file argument to script.\n"; + } +} + +# +# Main script +# +my $sys = $ENV{MSYSTEM} ? 'msys2' : 'other'; +my $ver = &get_ivl_version($sfx); +my $msg = $with_valg ? " (with valgrind)" : ""; +print ("Running VPI tests for Icarus Verilog version: $ver$msg.\n"); +print "-" x 76 . "\n"; +&read_regression_list; +&execute_regression; + +# +# parses the regression list file +# +# (from left-to-right in regression file): +# +# test_name type c/c++_code gold_file opt_c/c++_defines +# +sub read_regression_list { + my ($line, @fields, $tname, $tver, %nameidx); + open (REGRESS_LIST, "<$regress_fn") or + die "Error: unable to open $regress_fn for reading.\n"; + + while ($line = ) { + chomp $line; + next if ($line =~ /^\s*#/); # Skip comments. + next if ($line =~ /^\s*$/); # Skip blank lines. + + $line =~ s/#.*$//; # Strip in line comments. + $line =~ s/\s+$//; # Strip trailing white space. + + # You must specify at least the first four fields, cargs is optional + # and gets the rest of the fields if present. + @fields = split(' ', $line, 5); + if (@fields < 3) { + die "Error: $fields[0] must have at least 4 fields.\n"; + } + + $tname = $fields[0]; + # Check for a version or system specific line. + if ($tname =~ /:/) { + ($tver, $tname) = split(':', $tname); + next if (exists($ccode{$tname})); # Skip if already defined. + next if ($tver ne "v$ver" && $tver ne $sys); # Skip if this is not our version or system. + # Get the test type and any iverilog arguments. + if ($fields[1] =~ ',') { + ($testtype, $args{$tname}) = split(',', $fields[1], 2); + # For now we just support args to iverilog. + if ($args{$tname} =~ ',') { + $args{$tname} = join(' ', split(',', $args{$tname})); + } + } else { + $testtype = $fields[1]; + $args{$tname} = ""; + } + # This version of the program does not implement something + # required to run this test. + if ($testtype eq "NI") { + $args{$tname} = ""; + $ccode{$tname} = ""; + $goldfile{$tname} = ""; + $cargs{$tname} = ""; + } else { + $ccode{$tname} = $fields[2]; + $goldfile{$tname} = $fields[3]; + $cargs{$tname} = $fields[4]; + } +# print "Read $tver:$tname=$ccode{$tname}, $goldfile{$tname}, ". +# "$args{$tname}, $cargs{$tname}\n"; + } else { + next if (exists($ccode{$tname})); # Skip if already defined. + # Get the test type and any iverilog arguments. + if ($fields[1] =~ ',') { + ($testtype, $args{$tname}) = split(',', $fields[1], 2); + # For now we just support args to iverilog. + if ($args{$tname} =~ ',') { + $args{$tname} = join(' ', split(',', $args{$tname})); + } + } else { + $args{$tname} = ""; + } + $ccode{$tname} = $fields[2]; + $goldfile{$tname} = $fields[3]; + $cargs{$tname} = $fields[4]; +# print "Read $tname=$ccode{$tname}, $goldfile{$tname}, ". +# "$args{$tname}, $cargs{$tname}\n"; + } + # If there wasn't a cargs field make it a null string. + $cargs{$tname} = "" if (!defined($cargs{$tname})); + + # If the name exists this is a replacement so skip the original one. + if (exists($nameidx{$tname})) { + splice(@testlist, $nameidx{$tname}, 1, ""); + } + push (@testlist,$tname); + $nameidx{$tname} = @testlist - 1; + } + close (REGRESS_LIST); +} + +# +# execute_regression sequentially compiles and executes each test in +# the regression. It then checks that the output matched the gold file. +# +sub execute_regression { + my ($tname, $total, $passed, $failed, $not_impl, $len, $cmd); + + $total = 0; + $passed = 0; + $failed = 0; + $not_impl = 0; + $len = 0; + + foreach $tname (@testlist) { + $len = length($tname) if (length($tname) > $len); + } + + # Make sure we have a log directory. + if (! -d 'vpi_log') { + mkdir 'vpi_log' or die "Error: unable to create vpi_log directory.\n"; + } + + foreach $tname (@testlist) { + next if ($tname eq ""); # Skip test that have been replaced. + + $total++; + printf "%${len}s: ", $tname; + if (-e "vpi_log/$tname.log") { + unlink "vpi_log/$tname.log" or + die "Error: unable to remove old log file ". + "vpi_log/$tname.log.\n"; + } + + if ($ccode{$tname} eq "") { + print "Not Implemented.\n"; + $not_impl++; + next; + } + + $cmd = "iverilog-vpi$sfx --name=$tname $cargs{$tname} " . + "vpi/$ccode{$tname} > vpi_log/$tname.log 2>&1"; + if (system("$cmd")) { + print "==> Failed - running iverilog-vpi.\n"; + $failed++; + next; + } + + $cmd = $with_valg ? "valgrind --trace-children=yes " : ""; + if ($ver < 11) { + $cmd .= "iverilog$sfx $args{$tname} -o vsim vpi/$tname.v >> " . + "vpi_log/$tname.log 2>&1"; + } else { + $cmd .= "iverilog$sfx $args{$tname} -L . -m $tname -o vsim vpi/$tname.v >> " . + "vpi_log/$tname.log 2>&1"; + } + if (system("$cmd")) { + print "==> Failed - running iverilog.\n"; + $failed++; + next; + } + + $cmd = $with_valg ? "valgrind --leak-check=full " . + "--show-reachable=yes " : ""; + if ($ver < 11) { + $cmd .= "vvp$sfx -M . -m $tname vsim >> vpi_log/$tname.log 2>&1"; + } else { + $cmd .= "vvp$sfx vsim >> vpi_log/$tname.log 2>&1"; + } + if (system("$cmd")) { + print "==> Failed - running vvp.\n"; + $failed++; + next; + } + + if (diff("vpi_gold/$goldfile{$tname}", "vpi_log/$tname.log")) { + print "==> Failed - output does not match gold file.\n"; + $failed++; + next; + } + + print "Passed.\n"; + $passed++; + + } continue { + # We have to use system and not unlink here since these files + # were created by this process and it doesn't seem to know they + # are not being used. + if ($tname ne "" and $ccode{$tname} ne "") { + my $doto = $ccode{$tname}; + $doto =~ s/\.(c|cc|cpp)$/.o/; + system("rm -f $doto $tname.vpi vsim") and + die "Error: failed to remove temporary files.\n"; + } + } + + print "=" x 76 . "\n"; + print "Test results: Total=$total, Passed=$passed, Failed=$failed,". + " Not Implemented=$not_impl\n"; + exit $failed; +} + +# +# We only need a simple diff, but we need to strip \r at the end of line. +# +sub diff { + my ($gold, $log) = @_; + my ($diff, $gline, $lline); + $diff = 0; + + open (GOLD, "<$gold") or die "Error: unable to open $gold for reading.\n"; + open (LOG, "<$log") or die "Error: unable to open $log for reading.\n"; + + # Loop on the gold file lines. + foreach $gline () { + if (eof LOG) { + $diff = 1; + last; + } + $lline = ; + # Skip lines from valgrind ^==\d+== or ^**\d+** + while ($lline =~ m/^(==|\*\*)\d+(==|\*\*)/) { + $lline = ; + } + $gline =~ s/\r\n$/\n/; # Strip at the end of line. + $lline =~ s/\r\n$/\n/; # Strip at the end of line. + if ($gline ne $lline) { + $diff = 1; + last; + } + } + + # Check to see if the log file has extra lines. + while (!eof LOG and !$diff) { + $lline = ; + $diff = 1 if ($lline !~ m/^(==|\*\*)\d+(==|\*\*)/); + } + + close (LOG); + close (GOLD); + + return $diff +} diff --git a/ivtest/vpi_regress.list b/ivtest/vpi_regress.list new file mode 100644 index 000000000..d0f85705b --- /dev/null +++ b/ivtest/vpi_regress.list @@ -0,0 +1,152 @@ +#========== +# This file controls how the individual VPI tests are run. The verilog +# file must be named .v. The output log file is named +# .log. The verilog and C/C++ files are located in the +# "vpi" directory and the gold files are located in the "vpi_gold" +# directory. The NI (Not Implemented) type is only available for +# version specific tests. It is ignored by the default case! +# +# The basic steps for each test are: +# iverilog-vpi --name +# iverilog -o sim_file .v +# vvp -M . -m sim_file +# diff +# remove temporary files. +# +# The following are the recognized fields: +# +#ver:test name type C/C++ file gold log file compiler options +# +# The compiler option field is optional and when present will contain +# all subsequent fields. +#========== + +#========== +# For testing with other simulators +#========== + +# Icarus returns vpiReg instead of vpiTimeVar. +vstd:by_name normal by_name.c by_name-std.log + +# This test uses an Icarus language extension ($simparam). +vstd:check_version NI check_version.c check_version.gold + +# Icarus generates spurious value change callback triggers at T=0. +vstd:memwide normal memwide.cc memwide-std.log +vstd:nulls1 normal nulls1.c nulls1-std.log + +# Icarus outputs warning messages. +vstd:pr723 normal pr723.c pr723-std.log + +# This test uses an Icarus language extension (wire real). +vstd:pr2966059 NI pr2966059.c pr2966059.gold + +# This test has a non-deterministic output order. The gold file needs +# to be adjusted to match the simulator being used. +vstd:scopes normal scopes.c scopes-std.log + + +#========== +# MSYS2 exceptions +#========== + +# This still needs investigating. +msys2:pr723 NI pr723.c pr723.log + + +#========== +# V10 exceptions +#========== + +# V10 exceptions +v10:br_gh117 NI br_gh117.c br_gh117.gold +v10:br_ml20191013 NI br_ml20191013.c br_ml20191013.gold +v10:by_index NI by_index.c by_index.gold +v10:pr723 normal pr723.c pr723-v10.log +v10:spec_delays normal,-gspecify spec_delays.c spec_delays.log -DIVERILOG_V10 + + +#========== +# V11 exceptions +#========== + + +#========== +# The default case. +#========== + +br_gh59 normal br_gh59.c br_gh59.gold +br_gh73a normal force.c br_gh73a.gold +br_gh73b normal force.c br_gh73b.gold +br_gh117 normal br_gh117.c br_gh117.gold +br_gh141 normal br_gh141.c br_gh141.gold +br_gh169a normal br_gh169.c br_gh169a.gold +br_gh169b normal,-g2009 br_gh169.c br_gh169b.gold +br_gh184 normal start_of_simtime1.c br_gh184.gold +br_gh235 normal,-g2009 br_gh235.c br_gh235.gold +br_gh308 normal br_gh308.c br_gh308.gold +br_gh317 normal br_gh317.c br_gh317.gold +br_gh496 normal,-g2009 br_gh496.c br_gh496.gold +br_ml20191013 normal br_ml20191013.c br_ml20191013.gold +by_index normal by_index.c by_index.gold +by_name normal by_name.c by_name.log +callback1 normal callback1.c callback1.log +celldefine normal celldefine.c celldefine.gold +check_version normal check_version.c check_version.gold +display_array normal,-g2009 display_array.c display_array.gold +event1 normal event1.c event1.log +event2 normal event2.c event2.log +final normal,-g2009 final.c final.gold +find_sig normal find_sig.c find_sig.gold +force_reg normal force.c force_reg.gold +force_reg_pv normal force.c force_reg_pv.gold +force_reg_real normal force_real.c force_reg_real.gold +force_wire normal force.c force_wire.gold +force_wire_pv normal force.c force_wire_pv.gold +force_wire_real normal force_real.c force_wire_real.gold +genblk_named normal genblk_names.c genblk_named.gold +genblk_unnamed normal genblk_names.c genblk_unnamed.gold +genblk_direct normal,-g2009 genblk_names.c genblk_direct.gold +getp normal getp.c getp.log +hello_poke normal hello_poke.c hello_poke.log +hello_tf normal hello_tf.c hello_tf.log +hello_vpi normal hello_vpi.c hello.log +listparams normal listparams.c listparams.log +memmon normal,-g1995 memmon.c memmon.log +memwide normal memwide.cc memwide.log +mipname normal mipname.c mipname.log +myscope normal myscope.c myscope.gold +myscope2 normal myscope2.c myscope2.gold +nulls1 normal nulls1.c nulls1.log +pokevent normal pokevent.cc pokevent.log +pokereg normal pokereg.cc pokereg.log +ports_params normal ports_params.c ports_params.gold +pr521 normal pr521.c pr521.log +pr686 normal pr686.c pr686.log +pr723 normal pr723.c pr723.log +pr1693971 normal pr1693971.c pr1693971.log +pr2048463 normal pr2048463.c pr2048463.log +pr2314742 normal pr2314742.c pr2314742.gold +pr2966059 normal,-gno-xtypes pr2966059.c pr2966059.gold +pr2971220 normal pr2971220.c pr2971220.gold +putp normal putp.c putp.log +putp2 normal putp2.c putp2.log +putvalue normal putvalue.c putvalue.log +range1 normal range1.c range1.gold +realcb normal realcb.c realcb.log +realtime normal realtime.c realtime.log +realtime2 normal realtime2.c realtime2.log +ro_synch normal ro_synch.c ro_synch.gold +scanmem normal scanmem.cc scanmem.log +scanmem2 normal scanmem2.cc scanmem2.log +scanmem3 normal scanmem3.cc scanmem3.log +scopes normal scopes.c scopes.log +spec_delays normal,-gspecify spec_delays.c spec_delays.log +start_of_simtime1 normal start_of_simtime1.c start_of_simtime1.log +timescale normal timescale.c timescale.log + +# Add new tests in alphabetic/numeric order. If the test needs +# a compile option or a different log file to run with an older +# version or if it uses something not implemented (NI) by other +# versions of the program it will also need a version specific +# line above. diff --git a/ivtest/vvp_reg.pl b/ivtest/vvp_reg.pl new file mode 100755 index 000000000..00a4d9f70 --- /dev/null +++ b/ivtest/vvp_reg.pl @@ -0,0 +1,265 @@ +#!/usr/bin/env perl +# +# Script to handle regression for Icarus Verilog using the vvp target. +# +# This script is based on code with the following Copyright. +# +# Copyright (c) 1999-2021 Guy Hutchison (ghutchis@pacbell.net) +# +# This source code is free software; you can redistribute it +# and/or modify it in source code form under the terms of the GNU +# General Public License as published by the Free Software +# Foundation; either version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + +use lib './perl-lib'; + +use RegressionList; +use Diff; +use Reporting; +use Environment; + + +# +# Main script +# +&open_report_file; +my ($suffix, $strict, $with_valg, $force_sv) = &get_args; +my $ver = &get_ivl_version($suffix); +my $opt = $strict ? ($force_sv ? " (strict, force SV)" : " (strict)") : + ($force_sv ? " (force SV)" : ""); +my $msg = $with_valg ? " (with valgrind)" : ""; +&print_rpt("Running compiler/VVP tests for Icarus Verilog " . + "version: $ver$opt$msg.\n"); +&print_rpt("-" x 76 . "\n"); +if ($#ARGV != -1) { + my $regress_fn = &get_regress_fn; + &read_regression_list($regress_fn, $ver, $force_sv, ""); +} else { + if ($ENV{MSYSTEM}) { + &read_regression_list("regress-msys2.list", $ver, $force_sv, ""); + } + if ($force_sv) { + &read_regression_list("regress-fsv.list", $ver, $force_sv, ""); + } + &read_regression_list("regress-v$ver.list", $ver, $force_sv, ""); + if ($strict == 0) { + &read_regression_list("regress-ivl2.list", $ver, $force_sv, ""); + } + &read_regression_list("regress-ivl1.list", $ver, $force_sv, ""); + &read_regression_list("regress-vlg.list", $ver, $force_sv, ""); + &read_regression_list("regress-vams.list", $ver, $force_sv, ""); + if ($ver >= 10) { + &read_regression_list("regress-sv.list", $ver, $force_sv, ""); + &read_regression_list("regress-vhdl.list", $ver, $force_sv, ""); + } + if ($ver == 0.9 or $force_sv) { + &read_regression_list("regress-synth.list", $ver, $force_sv, ""); + } else { + &read_regression_list("regress-synth.list", $ver, $force_sv, "-S"); + } +} +&execute_regression($suffix, $strict, $with_valg); +&close_report_file; + + +# +# execute_regression sequentially compiles and executes each test in +# the regression. It then checks that the output matches the gold file. +# +sub execute_regression { + my $sfx = shift(@_); + my $strict = shift(@_); + my $with_valg = shift(@_); + my ($tname, $total, $passed, $failed, $expected_fail, $not_impl, + $len, $cmd, $ivl_args, $vvp_args, $diff_file); + + $total = 0; + $passed = 0; + $failed = 0; + $expected_fail = 0; + $not_impl = 0; + $len = 0; + + foreach $tname (@testlist) { + $len = length($tname) if (length($tname) > $len); + } + + # Make sure we have a log and work directory. + if (! -d 'log') { + mkdir 'log' or die "Error: unable to create log directory.\n"; + } + if (! -d 'work') { + mkdir 'work' or die "Error: unable to create work directory.\n"; + } + + if ($strict) { + $ivl_args = "-gstrict-expr-width"; + $vvp_args = "-compatible"; + } else { + $ivl_args = "-D__ICARUS_UNSIZED__"; + $vvp_args = ""; + } + + foreach $tname (@testlist) { + my ($pass_type); + next if ($tname eq ""); # Skip test that have been replaced. + + $total++; + &print_rpt(sprintf("%${len}s: ", $tname)); + if ($diff{$tname} ne "" and -e $diff{$tname}) { + unlink $diff{$tname} or + die "Error: unable to remove old diff file $diff{$tname}.\n"; + } + if (-e "log/$tname.log") { + unlink "log/$tname.log" or + die "Error: unable to remove old log file log/$tname.log.\n"; + } + + if ($testtype{$tname} eq "NI") { + &print_rpt("Not Implemented.\n"); + $not_impl++; + next; + } + + if (! -e "./$srcpath{$tname}/$tname.v") { + &print_rpt("Failed - missing source file.\n"); + $failed++; + next; + } + + # + # Build up the iverilog command line and run it. + # + $pass_type = 0; + $cmd = $with_valg ? "valgrind --trace-children=yes " : ""; + $cmd .= "iverilog$sfx -o vsim $ivl_args $args{$tname}"; + $cmd .= " -s $testmod{$tname}" if ($testmod{$tname} ne ""); + $cmd .= " -t null" if ($testtype{$tname} eq "CN"); + $cmd .= " ./$srcpath{$tname}/$tname.v > log/$tname.log 2>&1"; +# print "$cmd\n"; + if (system("$cmd")) { + if ($testtype{$tname} eq "CE") { + # Check if the system command core dumped! + if ($? >> 8 & 128) { + &print_rpt("==> Failed - CE (core dump).\n"); + $failed++; + next; + } else { + $pass_type = 1; + } + } else { + &print_rpt("==> Failed - running iverilog.\n"); + $failed++; + next; + } + } else { + if ($testtype{$tname} eq "CE") { + &print_rpt("==> Failed - CE (no error reported).\n"); + $failed++; + next; + } + } + + if ($testtype{$tname} eq "CO") { + &print_rpt("Passed - CO.\n"); + $passed++; + next; + } + if ($testtype{$tname} eq "CN") { + &print_rpt("Passed - CN.\n"); + $passed++; + next; + } + + $cmd = $with_valg ? "valgrind --leak-check=full " . + "--show-reachable=yes " : ""; + $cmd .= "vvp$sfx vsim $vvp_args $plargs{$tname} >> log/$tname.log 2>&1"; +# print "$cmd\n"; + if ($pass_type == 0 and system("$cmd")) { + if ($testtype{$tname} eq "RE") { + # Check if the system command core dumped! + if ($? >> 8 & 128) { + &print_rpt("==> Failed - RE (core dump).\n"); + $failed++; + next; + } else { + $pass_type = 2; + } + } else { + &print_rpt("==> Failed - running vvp.\n"); + $failed++; + next; + } + } elsif ($testtype{$tname} eq "RE") { + &print_rpt("==> Failed - RE (no error reported).\n"); + $failed++; + next; + } + + if ($diff{$tname} ne "") { + $diff_file = $diff{$tname} + } elsif ($gold{$tname} ne "") { + $diff_file = "log/$tname.log"; + } else { + if ($pass_type == 1) { + &print_rpt("Passed - CE.\n"); + $passed++; + next; + } elsif ($pass_type == 2) { + &print_rpt("Passed - RE.\n"); + $passed++; + next; + } + $diff_file = "log/$tname.log"; + } +# print "diff $gold{$tname}, $diff_file, $offset{$tname}, $unordered{$tname}\n"; + if (diff($gold{$tname}, $diff_file, $offset{$tname}, $unordered{$tname})) { + if ($testtype{$tname} eq "EF") { + &print_rpt("Passed - expected fail.\n"); + $expected_fail++; + next; + } + &print_rpt("==> Failed -"); + if ($pass_type == 1) { + &print_rpt(" CE -"); + } elsif ($pass_type == 2) { + &print_rpt(" RE -"); + } + &print_rpt(" output does not match gold file.\n"); + $failed++; + next; + } + + if ($pass_type == 1) { + &print_rpt("Passed - CE.\n"); + } elsif ($pass_type == 2) { + &print_rpt("Passed - RE.\n"); + } else { + &print_rpt("Passed.\n"); + } + $passed++; + + } continue { + if ($tname ne "") { + system("rm -f ./vsim && rm -rf ivl_vhdl_work") and + die "Error: failed to remove temporary file.\n"; + } + } + + &print_rpt("=" x 76 . "\n"); + &print_rpt("Test results:\n Total=$total, Passed=$passed, Failed=$failed,". + " Not Implemented=$not_impl, Expected Fail=$expected_fail\n"); + + # Remove remaining temporary files + system("rm -f *.tmp ivltests/*.tmp"); +} From fd30e5733720362334b1e8bae1d81a4487084878 Mon Sep 17 00:00:00 2001 From: Stephen Williams Date: Sat, 15 Jan 2022 11:53:31 -0800 Subject: [PATCH 2/3] Fix up some v11 issues brought on by ivtests issues The ivtest suite from the master branch has a few bits that the v11-branch cannot handle. So here we start seeing the test suites diverge for releases. --- ivtest/regress-v11.list | 4 ++++ ivtest/regression_report-v11.txt | 6 +++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/ivtest/regress-v11.list b/ivtest/regress-v11.list index 57fca1d72..c6118a816 100644 --- a/ivtest/regress-v11.list +++ b/ivtest/regress-v11.list @@ -124,6 +124,7 @@ sf_onehot0_fail normal,-g2009 ivltests gold=sf_onehot0_fail.gold # These tests are not implemented for v11 analog1 NI ivltests analog2 NI ivltests +array_packed NI ivltests br605a NI ivltests br605b NI ivltests br971 NI ivltests @@ -144,8 +145,11 @@ br_gh460 NI ivltests br_gh478 NI ivltests br_gh527 NI ivltests edge NI ivltests +enum_dims_invalid NI ivltests fileline2 NI ivltests ifdef_fail NI ivltests +packed_dims_invalid_class NI ivltests +packed_dims_invalid_module NI ivltests scalar_vector NI ivltests string12 NI ivltests sv_deferred_assert1 NI ivltests diff --git a/ivtest/regression_report-v11.txt b/ivtest/regression_report-v11.txt index f2f06d9f4..837cfa415 100644 --- a/ivtest/regression_report-v11.txt +++ b/ivtest/regression_report-v11.txt @@ -42,6 +42,7 @@ Running compiler/VVP tests for Icarus Verilog version: 11. sf_onehot0_fail: Passed. analog1: Not Implemented. analog2: Not Implemented. + array_packed: Not Implemented. br605a: Not Implemented. br605b: Not Implemented. br971: Not Implemented. @@ -62,8 +63,11 @@ Running compiler/VVP tests for Icarus Verilog version: 11. br_gh478: Not Implemented. br_gh527: Not Implemented. edge: Not Implemented. + enum_dims_invalid: Not Implemented. fileline2: Not Implemented. ifdef_fail: Not Implemented. + packed_dims_invalid_class: Not Implemented. + packed_dims_invalid_module: Not Implemented. scalar_vector: Not Implemented. string12: Not Implemented. sv_deferred_assert1: Not Implemented. @@ -2557,4 +2561,4 @@ test_mos_strength_reduction: Passed. ufuncsynth1: Passed. ============================================================================ Test results: - Total=2555, Passed=2522, Failed=0, Not Implemented=32, Expected Fail=1 + Total=2559, Passed=2522, Failed=0, Not Implemented=36, Expected Fail=1 From 6f114cce177d0f772a532982956e3d06aa8fd8b9 Mon Sep 17 00:00:00 2001 From: Stephen Williams Date: Sat, 15 Jan 2022 13:15:12 -0800 Subject: [PATCH 3/3] Do not fail msys build if there are no pdf files installed. --- msys2/PKGBUILD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/msys2/PKGBUILD b/msys2/PKGBUILD index 42dde1a4b..09716cbb4 100644 --- a/msys2/PKGBUILD +++ b/msys2/PKGBUILD @@ -34,5 +34,5 @@ package() { cd "${srcdir}"/../.. mingw32-make DESTDIR="${pkgdir}" install mkdir -p "${pkgdir}${MINGW_PREFIX}/share/doc/${_realname}" - mv "${pkgdir}${MINGW_PREFIX}"/*.pdf "${pkgdir}${MINGW_PREFIX}/share/doc/${_realname}" + mv "${pkgdir}${MINGW_PREFIX}"/*.pdf "${pkgdir}${MINGW_PREFIX}/share/doc/${_realname}" || true }